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283 lines
12 KiB
<?xml version="1.0"?> |
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<!DOCTYPE refentry PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN" |
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"http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd"> |
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<!-- $Id$ --> |
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<refentry id="yasm_arch"> |
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<refentryinfo> |
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<title>YASM Architectures</title> |
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<date>September 2004</date> |
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<productname>YASM</productname> |
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<author> |
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<firstname>Peter</firstname> |
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<surname>Johnson</surname> |
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<affiliation> |
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<address><email>peter@tortall.net</email></address> |
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</affiliation> |
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</author> |
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<copyright> |
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<year>2004</year> |
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<holder>Peter Johnson</holder> |
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</copyright> |
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</refentryinfo> |
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<refmeta> |
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<refentrytitle>yasm_arch</refentrytitle> |
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<manvolnum>7</manvolnum> |
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</refmeta> |
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<refnamediv> |
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<refname>yasm_arch</refname> |
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<refpurpose>YASM Architectures</refpurpose> |
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</refnamediv> |
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<refsynopsisdiv> |
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<cmdsynopsis> |
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<command>yasm</command> |
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<arg choice="plain"> |
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<option>-a <replaceable>arch</replaceable></option> |
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</arg> |
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<arg choice="opt"> |
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<option>-m <replaceable>machine</replaceable></option> |
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</arg> |
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<arg choice="plain"> |
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<option><replaceable>...</replaceable></option> |
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</arg> |
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</cmdsynopsis> |
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</refsynopsisdiv> |
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<refsect1><title>Description</title> |
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<para>The standard YASM distribution includes a number of loadable modules |
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for different target architectures. Additional target architectures |
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may be installed as third-party modules. Each target architecture can |
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support one or more machine architectures.</para> |
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<para>The architecture and machine are selected on the <citerefentry> |
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<refentrytitle>yasm</refentrytitle> <manvolnum>1</manvolnum> |
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</citerefentry> command line by use of the <option>-a |
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<replaceable>arch</replaceable></option> and <option>-m |
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<replaceable>machine</replaceable></option> command line options, |
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respectively.</para> |
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</refsect1> |
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<refsect1><title>x86 Architecture</title> |
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<para>The <quote>x86</quote> architecture supports the IA-32 instruction |
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set and derivatives and the AMD64 instruction set. It consists of two |
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machines: <quote>x86</quote> (for the IA-32 and derivatives) and |
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<quote>amd64</quote> (for the AMD64 and derivatives). The default |
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machine for the <quote>x86</quote> architecture is the |
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<quote>x86</quote> machine.</para> |
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<refsect2><title>BITS Setting</title> |
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<para>The x86 architecture BITS setting specifies to YASM the |
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processor mode in which the generated code is intended to execute. |
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x86 processors can run in three different major execution modes: |
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16-bit, 32-bit, and on AMD64-supporting processors, 64-bit. As |
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the x86 instruction set contains portions whose function is |
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execution-mode dependent (such as operand-size and address-size |
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override prefixes), YASM cannot assemble x86 instructions |
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correctly unless it is told by the user in what processor mode the |
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code will execute.</para> |
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<para>The BITS setting can be changed in a variety of ways. When |
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using the NASM-compatible parser, the BITS setting can be changed |
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directly via the use of the <userinput>BITS xx</userinput> |
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assembler directive. The default BITS setting is determined by |
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the object format in use.</para> |
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</refsect2> |
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<refsect2><title>BITS 64 Extensions</title> |
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<para>When an AMD64-supporting processor is executing in 64-bit mode, |
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a number of additional extensions are available, including extra |
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general purpose registers, extra SSE2 registers, and RIP-relative |
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addressing.</para> |
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<refsect3><title>Register Changes</title> |
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<para>The additional 64-bit general purpose registers are named |
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r8-r15. There are also 8-bit (rXb), 16-bit (rXw), and 32-bit |
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(rXd) subregisters that map to the least significant 8, 16, or |
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32 bits of the 64-bit register. The original 8 general |
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purpose registers have also been extended to 64-bits: eax, |
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edx, ecx, ebx, esi, edi, esp, and ebp have new 64-bit versions |
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called rax, rdx, rcx, rbx, rsi, rdi, rsp, and rbp |
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respectively. The old 32-bit registers map to the least |
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significant bits of the new 64-bit registers.</para> |
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<para>New 8-bit registers are also available that map to the 8 |
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least significant bits of rsi, rdi, rsp, and rbp. These are |
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called sil, dil, spl, and bpl respectively. Unfortunately, |
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due to the way instructions are encoded, these new 8-bit |
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registers are encoded the same as the old 8-bit registers ah, |
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dh, ch, and bh. The processor tells which is being used by |
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the presence of the new REX prefix that is used to specify the |
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other extended registers. This means it is illegal to mix the |
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use of ah, dh, ch, and bh with an instruction that requires |
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the REX prefix for other reasons. For instance:</para> |
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<screen>add ah, [r10]</screen> |
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<para>(NASM syntax) is not a legal instruction because the use of |
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r10 requires a REX prefix, making it impossible to use |
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ah.</para> |
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<para>In 64-bit mode, an additional 8 SSE2 registers are also |
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available. These are named xmm8-xmm15.</para> |
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</refsect3> |
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<refsect3><title>64 Bit Instructions</title> |
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<para>By default, most operations in 64-bit mode remain 32-bit; |
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operations that are 64-bit usually require a REX prefix (one |
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bit in the REX prefix determines whether an operation is |
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64-bit or 32-bit). Thus, essentially all 32-bit instructions |
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have a 64-bit version, and the 64-bit versions of instructions |
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can use extended registers <quote>for free</quote> (as the REX |
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prefix is already present). Examples in NASM syntax:</para> |
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<screen>mov eax, 1 ; 32-bit instruction</screen> |
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<screen>mov rcx, 1 ; 64-bit instruction</screen> |
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<para>Instructions that modify the stack (push, pop, call, ret, |
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enter, and leave) are implicitly 64-bit. Their 32-bit |
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counterparts are not available, but their 16-bit counterparts |
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are. Examples in NASM syntax:</para> |
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<screen>push eax ; illegal instruction</screen> |
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<screen>push rbx ; 1-byte instruction</screen> |
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<screen>push r11 ; 2-byte instruction with REX prefix</screen> |
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</refsect3> |
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<refsect3><title>Implicit Zero Extension</title> |
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<para>Results of 32-bit operations are implicitly zero-extended to |
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the upper 32 bits of the corresponding 64-bit register. 16 |
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and 8 bit operations, on the other hand, do not affect upper |
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bits of the register (just as in 32-bit and 16-bit modes). |
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This can be used to generate smaller code in some instances. |
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Examples in NASM syntax:</para> |
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<screen>mov ecx, 1 ; 1 byte shorter than mov rcx, 1</screen> |
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<screen>and edx, 3 ; equivalent to and rdx, 3</screen> |
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</refsect3> |
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<refsect3><title>Immediates</title> |
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<para>For most instructions in 64-bit mode, immediate values |
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remain 32 bits; their value is sign-extended into the upper 32 |
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bits of the target register prior to being used. The |
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exception is the mov instruction, which can take a 64-bit |
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immediate when the destination is a 64-bit register. Examples |
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in NASM syntax:</para> |
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<screen>add rax, 1 ; legal</screen> |
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<screen>add rax, 0xffffffff ; sign-extended</screen> |
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<screen>add rax, -1 ; same as above</screen> |
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<screen>add rax, 0xffffffffffffffff ; warning (>32 bit)</screen> |
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<screen>mov eax, 1 ; 5 byte instruction</screen> |
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<screen>mov rax, 1 ; 10 byte instruction</screen> |
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<screen>mov rbx, 0x1234567890abcdef ; 10 byte instruction</screen> |
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<screen>mov rcx, 0xffffffff ; 10 byte instruction</screen> |
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<screen>mov ecx, -1 ; 5 byte instruction equivalent to above</screen> |
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</refsect3> |
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<refsect3><title>Displacements</title> |
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<para>Just like immediates, displacements, for the most part, |
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remain 32 bits and are sign extended prior to use. Again, the |
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exception is one restricted form of the mov instruction: |
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between the al/ax/eax/rax register and a 64-bit absolute |
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address (no registers allowed in the effective address). In |
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NASM syntax, use of the 64-bit absolute form requires |
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<userinput>[qword]</userinput>. Examples in NASM |
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syntax:</para> |
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<screen>mov eax, [1] ; 32 bit, with sign extension</screen> |
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<screen>mov al, [rax-1] ; 32 bit, with sign extension</screen> |
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<screen>mov al, [qword 0x1122334455667788] ; 64-bit absolute</screen> |
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<screen>mov al, [0x1122334455667788] ; truncated to 32-bit (warning)</screen> |
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</refsect3> |
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<refsect3><title>RIP Relative Addressing</title> |
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<para>In 64-bit mode, a new form of effective addressing is |
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available to make it easier to write position-independent |
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code. Any memory reference may be made RIP relative (RIP is |
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the instruction pointer register, which contains the address |
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of the location immediately following the current |
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instruction).</para> |
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<para>In NASM syntax, there are two ways to specify RIP-relative |
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addressing:</para> |
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<screen>mov dword [rip+10], 1</screen> |
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<para>stores the value 1 ten bytes after the end of the |
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instruction. <userinput>10</userinput> can also be a symbolic |
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constant, and will be treated the same way. On the other |
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hand,</para> |
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<screen>mov dword [symb wrt rip], 1</screen> |
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<para>stores the value 1 into the address of symbol |
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<userinput>symb</userinput>. This is distinctly different |
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than the behavior of:</para> |
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<screen>mov dword [symb+rip], 1</screen> |
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<para>which takes the address of the end of the instruction, adds |
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the address of <userinput>symb</userinput> to it, then stores |
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the value 1 there. If <userinput>symb</userinput> is a |
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variable, this will NOT store the value 1 into the |
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<userinput>symb</userinput> variable!</para> |
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</refsect3> |
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</refsect2> |
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</refsect1> |
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<refsect1><title>lc3b Architecture</title> |
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<para>The <quote>lc3b</quote> architecture supports the LC-3b ISA as used |
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in the ECE 312 (now ECE 411) course at the University of Illinois, |
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Urbana-Champaign, as well as other university courses. See <ulink |
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url="http://courses.ece.uiuc.edu/ece411/"/> for more details and |
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example code. The <quote>lc3b</quote> architecture consists of only |
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one machine: <quote>lc3b</quote>.</para> |
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</refsect1> |
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<refsect1><title>See Also</title> |
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<para><citerefentry> |
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<refentrytitle>yasm</refentrytitle> |
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<manvolnum>1</manvolnum> |
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</citerefentry></para> |
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</refsect1> |
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<refsect1><title>Bugs</title> |
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<para>When using the <quote>x86</quote> architecture, it is overly easy to |
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generate AMD64 code (using the <userinput>BITS 64</userinput> |
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directive) and generate a 32-bit object file (by failing to specify |
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<option>-m amd64</option> on the command line). Similarly, specifying |
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<option>-m amd64</option> does not default the BITS setting to |
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64.</para> |
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</refsect1> |
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</refentry>
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