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398 lines
16 KiB
<?xml version="1.0"?> |
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<!DOCTYPE refentry PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN" |
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"http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd"> |
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<refentry id="yasm_arch"> |
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<refentryinfo> |
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<title>Yasm Supported Architectures</title> |
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<date>October 2006</date> |
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<productname>Yasm</productname> |
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<author> |
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<firstname>Peter</firstname> |
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<surname>Johnson</surname> |
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<affiliation> |
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<address><email>peter@tortall.net</email></address> |
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</affiliation> |
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</author> |
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<copyright> |
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<year>2004</year> |
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<year>2005</year> |
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<year>2006</year> |
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<year>2007</year> |
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<holder>Peter Johnson</holder> |
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</copyright> |
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</refentryinfo> |
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<refmeta> |
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<refentrytitle>yasm_arch</refentrytitle> |
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<manvolnum>7</manvolnum> |
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</refmeta> |
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<refnamediv> |
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<refname>yasm_arch</refname> |
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<refpurpose>Yasm Supported Target Architectures</refpurpose> |
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</refnamediv> |
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<refsynopsisdiv> |
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<cmdsynopsis> |
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<command>yasm</command> |
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<arg choice="plain"> |
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<option>-a <replaceable>arch</replaceable></option> |
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</arg> |
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<arg choice="opt"> |
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<option>-m <replaceable>machine</replaceable></option> |
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</arg> |
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<arg choice="plain"> |
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<option><replaceable>...</replaceable></option> |
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</arg> |
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</cmdsynopsis> |
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</refsynopsisdiv> |
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<refsect1> |
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<title>Description</title> |
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|
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<para>The standard Yasm distribution includes a number of modules |
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for different target architectures. Each target architecture can |
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support one or more machine architectures.</para> |
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<para>The architecture and machine are selected on the |
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<citerefentry> |
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<refentrytitle>yasm</refentrytitle> |
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<manvolnum>1</manvolnum> |
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</citerefentry> |
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command line by use of the <option>-a |
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<replaceable>arch</replaceable></option> and <option>-m |
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<replaceable>machine</replaceable></option> command line options, |
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respectively.</para> |
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<para>The machine architecture may also automatically be selected by |
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certain object formats. For example, the <quote>elf32</quote> |
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object format selects the <quote>x86</quote> machine architecture |
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by default, while the <quote>elf64</quote> object format selects |
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the <quote>amd64</quote> machine architecture by default.</para> |
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</refsect1> |
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<refsect1> |
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<title>x86 Architecture</title> |
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<para>The <quote>x86</quote> architecture supports the IA-32 |
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instruction set and derivatives and the AMD64 instruction set. It |
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consists of two machines: <quote>x86</quote> (for the IA-32 and |
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derivatives) and <quote>amd64</quote> (for the AMD64 and |
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derivatives). The default machine for the <quote>x86</quote> |
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architecture is the <quote>x86</quote> machine.</para> |
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<refsect2> |
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<title>BITS Setting</title> |
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<para>The x86 architecture BITS setting specifies to Yasm the |
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processor mode in which the generated code is intended to execute. |
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x86 processors can run in three different major execution modes: |
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16-bit, 32-bit, and on AMD64-supporting processors, 64-bit. As |
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the x86 instruction set contains portions whose function is |
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execution-mode dependent (such as operand-size and address-size |
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override prefixes), Yasm cannot assemble x86 instructions |
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correctly unless it is told by the user in what processor mode the |
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code will execute.</para> |
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<para>The BITS setting can be changed in a variety of ways. When |
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using the NASM-compatible parser, the BITS setting can be changed |
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directly via the use of the <userinput>BITS xx</userinput> |
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assembler directive. The default BITS setting is determined by |
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the object format in use.</para> |
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</refsect2> |
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<refsect2> |
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<title>BITS 64 Extensions</title> |
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<para>The AMD64 architecture is a new 64-bit architecture developed |
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by AMD, based on the 32-bit x86 architecture. It extends the |
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original x86 architecture by doubling the number of general |
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purpose and SIMD registers, extending the arithmetic operations |
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and address space to 64 bits, as well as other features.</para> |
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<para>Recently, Intel has introduced an essentially identical |
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version of AMD64 called EM64T.</para> |
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<para>When an AMD64-supporting processor is executing in 64-bit |
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mode, a number of additional extensions are available, including |
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extra general purpose registers, extra SSE2 registers, and |
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RIP-relative addressing.</para> |
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<para>Yasm extends the base NASM syntax to support AMD64 as |
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follows. To enable assembly of instructions for the 64-bit mode |
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of AMD64 processors, use the directive <userinput>BITS |
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64</userinput>. As with NASM's BITS directive, this does not |
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change the format of the output object file to 64 bits; it only |
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changes the assembler mode to assume that the instructions being |
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assembled will be run in 64-bit mode. To specify an AMD64 object |
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file, use <option>-m amd64</option> on the Yasm command line, or |
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explicitly target a 64-bit object format such as <option>-f |
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win64</option> or <option>-f elf64</option>. <option>-f |
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elfx32</option> can be used to select 32-bit ELF object format |
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for AMD64 processors.</para> |
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<refsect3> |
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<title>Register Changes</title> |
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<para>The additional 64-bit general purpose registers are named |
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r8-r15. There are also 8-bit (rXb), 16-bit (rXw), and 32-bit |
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(rXd) subregisters that map to the least significant 8, 16, or 32 |
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bits of the 64-bit register. The original 8 general purpose |
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registers have also been extended to 64-bits: eax, edx, ecx, ebx, |
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esi, edi, esp, and ebp have new 64-bit versions called rax, rdx, |
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rcx, rbx, rsi, rdi, rsp, and rbp respectively. The old 32-bit |
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registers map to the least significant bits of the new 64-bit |
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registers.</para> |
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<para>New 8-bit registers are also available that map to the 8 |
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least significant bits of rsi, rdi, rsp, and rbp. These are |
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called sil, dil, spl, and bpl respectively. Unfortunately, due |
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to the way instructions are encoded, these new 8-bit registers |
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are encoded the same as the old 8-bit registers ah, dh, ch, and |
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bh. The processor tells which is being used by the presence of |
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the new REX prefix that is used to specify the other extended |
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registers. This means it is illegal to mix the use of ah, dh, |
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ch, and bh with an instruction that requires the REX prefix for |
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other reasons. For instance:</para> |
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<screen>add ah, [r10]</screen> |
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<para>(NASM syntax) is not a legal instruction because the use of |
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r10 requires a REX prefix, making it impossible to use ah.</para> |
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<para>In 64-bit mode, an additional 8 SSE2 registers are also |
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available. These are named xmm8-xmm15.</para> |
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</refsect3> |
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<refsect3> |
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<title>64 Bit Instructions</title> |
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<para>By default, most operations in 64-bit mode remain 32-bit; |
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operations that are 64-bit usually require a REX prefix (one bit |
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in the REX prefix determines whether an operation is 64-bit or |
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32-bit). Thus, essentially all 32-bit instructions have a 64-bit |
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version, and the 64-bit versions of instructions can use extended |
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registers <quote>for free</quote> (as the REX prefix is already |
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present). Examples in NASM syntax:</para> |
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<screen>mov eax, 1 ; 32-bit instruction</screen> |
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<screen>mov rcx, 1 ; 64-bit instruction</screen> |
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<para>Instructions that modify the stack (push, pop, call, ret, |
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enter, and leave) are implicitly 64-bit. Their 32-bit |
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counterparts are not available, but their 16-bit counterparts |
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are. Examples in NASM syntax:</para> |
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<screen>push eax ; illegal instruction</screen> |
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<screen>push rbx ; 1-byte instruction</screen> |
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<screen>push r11 ; 2-byte instruction with REX prefix</screen> |
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</refsect3> |
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<refsect3> |
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<title>Implicit Zero Extension</title> |
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<para>Results of 32-bit operations are implicitly zero-extended to |
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the upper 32 bits of the corresponding 64-bit register. 16 and 8 |
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bit operations, on the other hand, do not affect upper bits of |
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the register (just as in 32-bit and 16-bit modes). This can be |
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used to generate smaller code in some instances. Examples in |
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NASM syntax:</para> |
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<screen>mov ecx, 1 ; 1 byte shorter than mov rcx, 1</screen> |
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<screen>and edx, 3 ; equivalent to and rdx, 3</screen> |
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</refsect3> |
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<refsect3> |
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<title>Immediates</title> |
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<para>For most instructions in 64-bit mode, immediate values |
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remain 32 bits; their value is sign-extended into the upper 32 |
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bits of the target register prior to being used. The exception |
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is the mov instruction, which can take a 64-bit immediate when |
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the destination is a 64-bit register. Examples in NASM |
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syntax:</para> |
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<screen>add rax, 1 ; optimized down to signed 8-bit</screen> |
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<screen>add rax, dword 1 ; force size to 32-bit</screen> |
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<screen>add rax, 0xffffffff ; sign-extended 32-bit</screen> |
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<screen>add rax, -1 ; same as above</screen> |
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<screen>add rax, 0xffffffffffffffff ; truncated to 32-bit (warning)</screen> |
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<screen>mov eax, 1 ; 5 byte</screen> |
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<screen>mov rax, 1 ; 5 byte (optimized to signed 32-bit)</screen> |
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<screen>mov rax, qword 1 ; 10 byte (forced 64-bit)</screen> |
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<screen>mov rbx, 0x1234567890abcdef ; 10 byte</screen> |
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<screen>mov rcx, 0xffffffff ; 10 byte (does not fit in signed 32-bit)</screen> |
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<screen>mov ecx, -1 ; 5 byte, equivalent to above</screen> |
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<screen>mov rcx, sym ; 5 byte, 32-bit size default for symbols</screen> |
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<screen>mov rcx, qword sym ; 10 byte, override default size</screen> |
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<para>The handling of mov reg64, unsized immediate is different |
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between YASM and NASM 2.x; YASM follows the above behavior, while |
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NASM 2.x does the following:</para> |
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<screen>add rax, 0xffffffff ; sign-extended 32-bit immediate</screen> |
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<screen>add rax, -1 ; same as above</screen> |
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<screen>add rax, 0xffffffffffffffff ; truncated 32-bit (warning)</screen> |
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<screen>add rax, sym ; sign-extended 32-bit immediate</screen> |
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<screen>mov eax, 1 ; 5 byte (32-bit immediate)</screen> |
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<screen>mov rax, 1 ; 10 byte (64-bit immediate)</screen> |
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<screen>mov rbx, 0x1234567890abcdef ; 10 byte instruction</screen> |
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<screen>mov rcx, 0xffffffff ; 10 byte instruction</screen> |
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<screen>mov ecx, -1 ; 5 byte, equivalent to above</screen> |
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<screen>mov ecx, sym ; 5 byte (32-bit immediate)</screen> |
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<screen>mov rcx, sym ; 10 byte instruction</screen> |
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<screen>mov rcx, qword sym ; 10 byte (64-bit immediate)</screen> |
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</refsect3> |
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<refsect3> |
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<title>Displacements</title> |
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<para>Just like immediates, displacements, for the most part, |
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remain 32 bits and are sign extended prior to use. Again, the |
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exception is one restricted form of the mov instruction: between |
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the al/ax/eax/rax register and a 64-bit absolute address (no |
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registers allowed in the effective address). In NASM syntax, use |
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of the 64-bit absolute form requires |
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<userinput>[qword]</userinput>. Examples in NASM syntax:</para> |
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<screen>mov eax, [1] ; 32 bit, with sign extension</screen> |
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<screen>mov al, [rax-1] ; 32 bit, with sign extension</screen> |
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<screen>mov al, [qword 0x1122334455667788] ; 64-bit absolute</screen> |
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<screen>mov al, [0x1122334455667788] ; truncated to 32-bit (warning)</screen> |
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</refsect3> |
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<refsect3> |
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<title>RIP Relative Addressing</title> |
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<para>In 64-bit mode, a new form of effective addressing is |
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available to make it easier to write position-independent code. |
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Any memory reference may be made RIP relative (RIP is the |
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instruction pointer register, which contains the address of the |
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location immediately following the current instruction).</para> |
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<para>In NASM syntax, there are two ways to specify RIP-relative |
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addressing:</para> |
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<screen>mov dword [rip+10], 1</screen> |
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<para>stores the value 1 ten bytes after the end of the |
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instruction. <userinput>10</userinput> can also be a symbolic |
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constant, and will be treated the same way. On the other |
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hand,</para> |
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<screen>mov dword [symb wrt rip], 1</screen> |
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<para>stores the value 1 into the address of symbol |
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<userinput>symb</userinput>. This is distinctly different than |
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the behavior of:</para> |
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<screen>mov dword [symb+rip], 1</screen> |
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<para>which takes the address of the end of the instruction, adds |
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the address of <userinput>symb</userinput> to it, then stores the |
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value 1 there. If <userinput>symb</userinput> is a variable, |
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this will <emphasis>not</emphasis> store the value 1 into the |
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<userinput>symb</userinput> variable!</para> |
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<para>Yasm also supports the following syntax for RIP-relative |
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addressing:</para> |
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<screen>mov [rel sym], rax ; RIP-relative</screen> |
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<screen>mov [abs sym], rax ; not RIP-relative</screen> |
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<para>The behavior of:</para> |
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<screen>mov [sym], rax</screen> |
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<para>Depends on a mode set by the DEFAULT directive, as follows. |
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The default mode is always "abs", and in "rel" mode, use of |
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registers, an fs or gs segment override, or an explicit "abs" |
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override will result in a non-RIP-relative effective |
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address.</para> |
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<screen>default rel</screen> |
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<screen>mov [sym], rbx ; RIP-relative</screen> |
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<screen>mov [abs sym], rbx ; not RIP-relative (explicit override)</screen> |
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<screen>mov [rbx+1], rbx ; not RIP-relative (register use)</screen> |
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<screen>mov [fs:sym], rbx ; not RIP-relative (fs or gs use)</screen> |
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<screen>mov [ds:sym], rbx ; RIP-relative (segment, but not fs or gs)</screen> |
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<screen>mov [rel sym], rbx ; RIP-relative (redundant override)</screen> |
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<screen>default abs</screen> |
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<screen>mov [sym], rbx ; not RIP-relative</screen> |
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<screen>mov [abs sym], rbx ; not RIP-relative</screen> |
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<screen>mov [rbx+1], rbx ; not RIP-relative</screen> |
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<screen>mov [fs:sym], rbx ; not RIP-relative</screen> |
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<screen>mov [ds:sym], rbx ; not RIP-relative</screen> |
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<screen>mov [rel sym], rbx ; RIP-relative (explicit override)</screen> |
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</refsect3> |
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<refsect3> |
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<title>Memory references</title> |
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<para>Usually the size of a memory reference can be deduced by |
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which registers you're moving--for example, "mov [rax],ecx" is a |
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32-bit move, because ecx is 32 bits. YASM currently gives the |
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non-obvious "invalid combination of opcode and operands" error if |
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it can't figure out how much memory you're moving. The fix in |
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this case is to add a memory size specifier: qword, dword, word, |
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or byte.</para> |
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<para>Here's a 64-bit memory move, which sets 8 bytes starting at |
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rax:</para> |
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<screen>mov qword [rax], 1</screen> |
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<para>Here's a 32-bit memory move, which sets 4 bytes:</para> |
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<screen>mov dword [rax], 1</screen> |
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<para>Here's a 16-bit memory move, which sets 2 bytes:</para> |
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<screen>mov word [rax], 1</screen> |
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<para>Here's an 8-bit memory move, which sets 1 byte:</para> |
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<screen>mov byte [rax], 1</screen> |
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</refsect3> |
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</refsect2> |
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</refsect1> |
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<refsect1> |
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<title>lc3b Architecture</title> |
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<para>The <quote>lc3b</quote> architecture supports the LC-3b ISA as |
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used in the ECE 312 (now ECE 411) course at the University of |
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Illinois, Urbana-Champaign, as well as other university courses. |
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See <ulink url="http://courses.ece.uiuc.edu/ece411/"/> for more |
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details and example code. The <quote>lc3b</quote> architecture |
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consists of only one machine: <quote>lc3b</quote>.</para> |
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</refsect1> |
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<refsect1> |
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<title>See Also</title> |
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<para><citerefentry> |
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<refentrytitle>yasm</refentrytitle> |
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<manvolnum>1</manvolnum> |
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</citerefentry></para> |
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</refsect1> |
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<refsect1> |
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<title>Bugs</title> |
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<para>When using the <quote>x86</quote> architecture, it is overly |
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easy to generate AMD64 code (using the <userinput>BITS |
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64</userinput> directive) and generate a 32-bit object file (by |
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failing to specify <option>-m amd64</option> on the command line or |
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selecting a 64-bit object format). Similarly, specifying |
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<option>-m amd64</option> does not default the BITS setting to |
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64. An easy way to avoid this is by directly specifying |
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a 64-bit object format such as <option>-f elf64</option>.</para> |
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</refsect1> |
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</refentry>
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