XAXQUIRE
XRELEASE
XABORT
XBEGIN
XEND
XTEST
Also fixed a bug for CALL instruction (opcode 0xE8) - it allowed 16 bit operand with 0x66 prefix in 64 bit mode,
while 16 bit operand is not allowed at all in 64 bit mode.
Added X86_ACQREL prefix group for XACQUIRE/XRELEASE prefixes, since they need to be orthogonal to LOCKREP
prefixes, because TSX prefixes must come together with F0 (LOCK) prefix.
However this commit does not enforce using TSX hints only with instructions they are allowed to be used.
The reason for this is that lock prefix F0 itself is not enforced to be used only with lockable instructions, this seems to be a decision made by
Yasm developers, that user himself must take care of these situations.
Right now TSX hints can come with F0 prefix, can come with REPNE/REPZE prefixes, but they are used together in assembly, only the leftmost would be
encoded to the binary and warning will be issued. This is the behavior of Yasm for duplicate LOCKREP prefixes.
These instructions use "VSIB" encoding, which takes the place of the
usual SIB encoding. Several tests cover various legal and illegal
modes.
Last part of [#227 state:resolved].
Reference: http://www.intel.com/software/avx rev11 spec
This is all AVX2 instructions except for VGATHER*/VPGATHER*, which
require additional ModRM handling.
Portions contributed by: Mark Charney <mark.charney@intel.com>
Part of [#227].
Reference: http://www.intel.com/software/avx rev11 spec
Also add appropriate CPU bits and directive handling for these.
Currently we have no good way of handling an "or" of instruction bits
(in this case needed for LZCNT, where it's either AMD or LZCNT). For
now, make it LZCNT only.
Contributed by: Mark Charney <mark.charney@intel.com>
Part of [#227].
Previously a line such as "times 4 mov rax, [rel foobar]" would result
in incorrect relocations being generated.
Patch by: bird-yasm@anduin.net
[#211 state:resolved]
The register versions worked okay due to size matching, but the memory
versions relied on suffix matching, which wasn't being generated correctly.
Reported by: Tony Goelz <cag@absoft.com>
svn path=/trunk/yasm/; revision=2358
- Fix#193: ljmp/lcall not implemented; add 2-operand far jump to jmp/call.
- Add loop{,z,e} instruction suffixes
- Fix a bunch of jmp/call minor issues.
- Vastly improve suffix handling in general to make more consistent and make
a greater variety of no-suffix instructions work in a way that matches GAS.
svn path=/trunk/yasm/; revision=2238
AMD has obsoleted the SSE5 spec in favor of these instructions. These
instructions use an AVX-like new opcode structure called XOP instead of
the SSE5 DREX byte.
The AMD FMA4 instructions are a copy of the *old* Intel FMA instructions.
Intel has since updated their spec, and AMD may follow, but for now we've
implemented what AMD's spec contains.
svn path=/trunk/yasm/; revision=2199
Also match GAS behavior by using different NOP sequences for AMD and Intel.
Different "Long" NOP opcode sequences are used based on the below criteria.
Defaults in 32-bit mode:
- CPU directive not used: backwards compatible (no long NOP opcodes)
- CPU directive with Intel CPU >= 686: Intel guidelines, using long NOPs
- CPU directive with AMD CPU >= K6: AMD guidelines, using long NOPs
Defaults in 64-bit mode:
- CPU directive not used: Intel guidelines, using long NOPs
- CPU directive with Intel CPU >= 686: Intel guidelines, using long NOPs
- CPU directive with AMD CPU >= K6: AMD guidelines, using long NOPs
The above defaults may be overridden with these options to the CPU directive:
- CPU basicnop: backwards compatible (no long NOP opcodes)
- CPU intelnop: Intel guidelines, using long NOPs
- CPU amdnop: AMD guidelines, using long NOPs
Suggested by: Brian Gladman <brg@gladman.plus.com>
svn path=/trunk/yasm/; revision=2181
To stay consist with handling of other VEX instructions, also add yasm
extensions to support combining the first two operands for direct translation
from non-VEX to VEX-encoded by simply adding a "v" prefix to the opcode.
Contributed by: Mark Charney, Intel Corporation <Mark.Charney@intel.com>
Yasm extensions by: Peter Johnson
svn path=/trunk/yasm/; revision=2173
These were incorrectly identified as invalid. The code would see the
ebx*2 term and identify ebx as the index register. After the ebx was
subtracted, the ebx remained in the index register slot, so eax*2 had
nowhere to go. The code now recognizes this case and frees the slot
when the -ebx is processed, leaving the index register selection up
to the main part of the code.
svn path=/trunk/yasm/; revision=2162
This can happen if somehow this file is retrieved without expanded keywords
(e.g. directly from the webpage, or via something like git-svn).
Reported by: Patrick Walton <pcwalton@cs.ucla.edu>
svn path=/trunk/yasm/; revision=2160
Contributed by: Samuel Thibault <samuel.thibault@ens-lyon.org>
It is built on top of the NASM parser and preproc, with the following
notable extensions for TASM syntax:
- case insensitive symbols and filenames,
- support for segment and size of labels, which permits to avoid giving
them on each memory dereference,
- support for data reservation (i.e. e.g. "var dd ?"),
- support for multiples (i.e. e.g. "var dd 1 dup 10"),
- little endian string integer constants,
- additional expression operators: shl, shr, and, or, low, high,
- additional offset keyword,
- additional fword and df,
- support for doubled quotes within quotes,
- support for array-like and structure-like notations: t[eax] and
[var].field,
- support for tasm directives: macro, rept, irp, locals, proc, struc,
segment, assume.
Notes:
- Almost all extensions are only effective when tasm_compatible_mode is
set, so we should have very reduced possible breakage.
- Because the "and" keyword can be an expression operator and an
instruction name, the data pseudo-instructions explicitly switch the
lexer state to INSTRUCTION state to fix the ambiguity.
- In gen_x86_insn.py, several instructions (namely lds and lea) now take
relaxed memory sizes. The reason is that in the case of tasm, the size
of the actual pointed data is passed up to there, and thus any type of
data should be accepted.
With all of this, loadlin can be compiled by yasm with quite reduced
modifications.
A new TASM-like frontend is also included.
svn path=/trunk/yasm/; revision=2130
syntax.
Previously, the forms of push that did this optimization were disabled in
NASM syntax due to conflicting with the size=BITS case. Fix this via
reordering to allow these forms to be active in NASM syntax.
svn path=/trunk/yasm/; revision=2127
H.J. Lu
Peter Johnson
Vivek Thampi
Scott Graham
sergey semenko
Jason Garrett-Glaser
Brian Gladman