directive for GAS (it's generated by GCC).
* bytecode.c (bytecode_align): Update for full align implementation.
(yasm_bc_create_align): Likewise.
(bc_align_finalize): New.
(bc_align_resolve, bc_align_tobytes): Real implementation.
* bytecode.h (yasm_bc_create_align): Update to match.
* arch.h (get_fill, yasm_arch_get_fill): New, to get NOP fill patterns.
* x86arch.c (x86_get_fill): Implement.
* lc3barch.c (lc3b_get_fill): Likewise (probably buggy, there's no real NOP).
* bytecode.c (bytecode_org): New org bytecode.
(bc_org_callback, bc_org_destroy, bc_org_print, bc_org_resolve)
(bc_org_tobytes, yasm_bc_create_org): Implement.
* gas-parser.h (yasm_parser_gas): Add code_section flag to indicate when to
use code fill vs. data fill.
* gas-parser.c: Initialize flag.
* gas-bison.y: Update flag in various places. Generate org bytecode.
Call gas_parser_align to generate align bytecode.
(gas_parser_align): Generate align bytecode.
* gas-bison.y: Implement .zero directive.
* gas-token.re: Likewise.
* align32, align64: New tests to test align directive NOP generation.
svn path=/trunk/yasm/; revision=1263
defining the mov forms for GAS. While I'm here, fix movq so it also
supports the 64-bit move registers (per Intel's spec, AMD has it under movd)
and copy the MMX/SSE2 versions of movq into mov so they're visible to the
GAS parser (and only the GAS parser).
Add a whole bunch of testcases to test movd and movq in both 32 bit and 64
bit modes for both GAS and NASM parsers.
svn path=/trunk/yasm/; revision=1255
Peter Johnson