Change some optimization settings so that imm8 optimizations actually get

triggered for more cases and optimize from 64-bit down to 32-bit for 64-bit
mov instructions.  This change means that mov reg64, constant will be
auto-sized up to 64 bits, but mov reg64, expr/symbol will default to 32 bits.
You must use mov reg64, qword expr/symbol if you need 64 bits, or in GAS
mode use movabsq expr/symbol, reg64.

This makes the generated code smaller and default most usages into 32-bit
relocations appropriate for ELF64 and Win64.  Right now, 32-bit unsigned
relocs are generated instead of 32-bit signed; this will need to be fixed.

* x86arch.h (x86_insn.postop): Add X86_POSTOP_SIGNEXT_IMM32.
* x86bc.c (x86_bc_insn_resolve): Implement.
* x86id.re (OPAP_SImm32Avail): New flag.
(MOD_Op2AddSp): New modifier to encode spare directly into 2nd opcode byte.
(arith_insn): Use MOD_Op2AddSp and add forced-size override forms.
(mov_insn): Use OPAP_SImm32Avail and add forced-size override form.
(yasm_x86__finalize_insn): Implement new flag and modifier.

Fix up testcases for changes.

svn path=/trunk/yasm/; revision=1314
0.5.0rc2
Peter Johnson 19 years ago
parent 9996855928
commit aa3e6ff9b9
  1. 3
      modules/arch/x86/tests/Makefile.inc
  2. 29
      modules/arch/x86/tests/addbyte.asm
  3. 2
      modules/arch/x86/tests/addbyte.errwarn
  4. 82
      modules/arch/x86/tests/addbyte.hex
  5. 13
      modules/arch/x86/tests/arithsmall.asm
  6. 2
      modules/arch/x86/tests/arithsmall.errwarn
  7. 51
      modules/arch/x86/tests/arithsmall.hex
  8. 17
      modules/arch/x86/tests/nomem64.asm
  9. 1
      modules/arch/x86/tests/nomem64.errwarn
  10. 116
      modules/arch/x86/tests/nomem64.hex
  11. 9
      modules/arch/x86/x86arch.h
  12. 108
      modules/arch/x86/x86bc.c
  13. 82
      modules/arch/x86/x86id.re
  14. 2
      modules/objfmts/bin/tests/bigorg.asm
  15. 2
      modules/objfmts/bin/tests/bigorg.errwarn
  16. 20
      modules/objfmts/bin/tests/bigorg.hex
  17. 28958
      modules/objfmts/coff/tests/x86id.hex
  18. 27087
      modules/objfmts/elf/tests/elf-x86id.hex
  19. 30
      modules/objfmts/elf/tests/elfglobal.hex
  20. 36
      modules/objfmts/elf/tests/gas64/elf_gas64_reloc.hex
  21. 22
      modules/objfmts/win64/tests/win64-dataref.asm
  22. 2
      modules/objfmts/xdf/tests/xdflong.asm

@ -11,6 +11,9 @@ EXTRA_DIST += modules/arch/x86/tests/addrop.errwarn
EXTRA_DIST += modules/arch/x86/tests/addrop.hex
EXTRA_DIST += modules/arch/x86/tests/addrop-err.asm
EXTRA_DIST += modules/arch/x86/tests/addrop-err.errwarn
EXTRA_DIST += modules/arch/x86/tests/arithsmall.asm
EXTRA_DIST += modules/arch/x86/tests/arithsmall.errwarn
EXTRA_DIST += modules/arch/x86/tests/arithsmall.hex
EXTRA_DIST += modules/arch/x86/tests/bittest.asm
EXTRA_DIST += modules/arch/x86/tests/bittest.errwarn
EXTRA_DIST += modules/arch/x86/tests/bittest.hex

@ -1,5 +1,34 @@
; AX forms
add ax,5
add ax,byte 5
add ax,word 5
add ax,-128
add ax,byte -128
add ax,word -128
add ax,0x7f
add ax,byte 0x7f
add ax,word 0x7f
add ax,0x80
add ax,byte 0x80
add ax,word 0x80
add ax,0x100
add ax,byte 0x100
add ax,word 0x100
; non-AX forms
add bx,5
add bx,byte 5
add bx,word 5
add bx,-128
add bx,byte -128
add bx,word -128
add bx,0x7f
add bx,byte 0x7f
add bx,word 0x7f
add bx,0x80
add bx,byte 0x80
add bx,word 0x80
add bx,0x100
add bx,byte 0x100
add bx,word 0x100

@ -0,0 +1,2 @@
-:15: warning: value does not fit in 8 bit field
-:32: warning: value does not fit in 8 bit field

@ -1,15 +1,97 @@
83
c0
05
83
c0
05
05
05
00
83
c0
80
83
c0
80
05
80
ff
83
c0
7f
83
c0
7f
05
7f
00
05
80
00
83
c0
80
05
80
00
05
00
01
83
c0
00
05
00
01
83
c3
05
83
c3
05
81
c3
05
00
83
c3
80
83
c3
80
81
c3
80
ff
83
c3
7f
83
c3
7f
81
c3
7f
00
81
c3
80
00
83
c3
80
81
c3
80
00
81
c3
00
01
83
c3
00
81
c3
00
01

@ -0,0 +1,13 @@
[bits 32]
and eax, 3584
and eax, 35
and eax, dword 3584
and eax, dword 35
and eax, byte 3584
and eax, byte 35
and ebx, 3584
and ebx, 35
and ebx, dword 3584
and ebx, dword 35
and ebx, byte 3584
and ebx, byte 35

@ -0,0 +1,2 @@
-:6: warning: value does not fit in 8 bit field
-:12: warning: value does not fit in 8 bit field

@ -0,0 +1,51 @@
25
00
0e
00
00
83
e0
23
25
00
0e
00
00
25
23
00
00
00
83
e0
00
83
e0
23
81
e3
00
0e
00
00
83
e3
23
81
e3
00
0e
00
00
81
e3
23
00
00
00
83
e3
00
83
e3
23

@ -2,7 +2,22 @@
mov ah, 5
mov ax, 5
mov eax, 5
mov rax, 5
mov rax, 5 ; optimized to signed 32-bit form
mov rax, dword 5 ; explicitly 32-bit
mov rax, qword 5 ; explicitly 64-bit
; test sign optimization cases
mov rax, 0x7fffffff
mov rax, dword 0x7fffffff
mov rax, qword 0x7fffffff
mov rax, 0x80000000
mov rax, dword 0x80000000
mov rax, qword 0x80000000
mov rax, -0x80000000
mov rax, dword -0x80000000
mov rax, qword -0x80000000
mov rax, 0x100000000
mov rax, dword 0x100000000
mov rax, qword 0x100000000
mov ah, bl
mov bl, r8b
mov sil, r9b

@ -0,0 +1 @@
-:19: warning: value does not fit in 32 bit field

@ -10,6 +10,20 @@ b8
00
00
48
c7
c0
05
00
00
00
48
c7
c0
05
00
00
00
48
b8
05
00
@ -19,6 +33,108 @@ b8
00
00
00
48
c7
c0
ff
ff
ff
7f
48
c7
c0
ff
ff
ff
7f
48
b8
ff
ff
ff
7f
00
00
00
00
48
b8
00
00
00
80
00
00
00
00
48
c7
c0
00
00
00
80
48
b8
00
00
00
80
00
00
00
00
48
c7
c0
00
00
00
80
48
c7
c0
00
00
00
80
48
b8
00
00
00
80
ff
ff
ff
ff
48
b8
00
00
00
00
01
00
00
00
48
c7
c0
00
00
00
00
48
b8
00
00
00
00
01
00
00
00
88
dc
44

@ -216,7 +216,14 @@ typedef struct x86_insn {
/* Override any attempt at address-size override to 16 bits, and never
* generate a prefix. This is used for the ENTER opcode.
*/
X86_POSTOP_ADDRESS16
X86_POSTOP_ADDRESS16,
/* Used for 64-bit mov immediate, which can take a sign-extended
* imm32 as well as imm64 values. The imm32 form is put in the
* second byte of the opcode and its ModRM byte is put in the third
* byte of the opcode.
*/
X86_POSTOP_SIGNEXT_IMM32
} postop;
} x86_insn;

@ -624,49 +624,85 @@ x86_bc_insn_resolve(yasm_bytecode *bc, int save,
/* TODO: check imm->len vs. sized len from expr? */
/* Handle signext_imm8 postop special-casing */
if (insn->postop == X86_POSTOP_SIGNEXT_IMM8 && temp &&
(num = yasm_expr_get_intnum(&temp, calc_bc_dist))) {
if (num) {
long val = yasm_intnum_get_int(num);
if (val >= -128 && val <= 127) {
/* We can use the sign-extended byte form: shorten
* the immediate length to 1.
*/
immlen = 1;
num = yasm_expr_get_intnum(&temp, calc_bc_dist);
switch (insn->postop) {
case X86_POSTOP_SIGNEXT_IMM8:
/* Handle signext_imm8 postop special-casing */
if (num) {
long val = yasm_intnum_get_int(num);
if (val >= -128 && val <= 127) {
/* We can use the sign-extended byte form: shorten
* the immediate length to 1.
*/
immlen = 1;
if (save) {
/* Make the byte form permanent. */
insn->opcode.opcode[0] = insn->opcode.opcode[1];
imm->len = 1;
if (insn->opcode.opcode[2] != 0) {
insn->opcode.opcode[1] = insn->opcode.opcode[2];
insn->opcode.len++;
}
} else if (insn->opcode.opcode[2] != 0)
bc->len++;
}
}
/* Not really necessary, but saves confusion over it. */
if (save)
insn->postop = X86_POSTOP_NONE;
break;
case X86_POSTOP_SIGNEXT_IMM32:
/* Handle signext_imm32 postop special-casing */
if (!num || yasm_intnum_check_size(num, 32, 0, 1)) {
bc->len++; /* Due to ModRM byte */
immlen = 4;
if (save) {
/* Make the byte form permanent. */
/* Throwaway REX byte */
unsigned char rex_temp = 0;
/* Build ModRM EA - CAUTION: this depends on
* opcode 0 being a mov instruction!
*/
insn->ea = yasm_x86__ea_create_reg(
(unsigned long)insn->opcode.opcode[0]-0xB8,
&rex_temp, 64);
/* Make the imm32s form permanent. */
insn->opcode.opcode[0] = insn->opcode.opcode[1];
imm->len = 1;
imm->len = 4;
}
}
}
/* Not really necessary, but saves confusion over it. */
if (save)
insn->postop = X86_POSTOP_NONE;
}
/* Not really necessary, but saves confusion over it. */
if (save)
insn->postop = X86_POSTOP_NONE;
break;
/* Handle shift postop special-casing */
if (insn->postop == X86_POSTOP_SHIFT && temp &&
(num = yasm_expr_get_intnum(&temp, calc_bc_dist))) {
if (num && yasm_intnum_get_uint(num) == 1) {
/* We can use the ,1 form: no immediate (set to 0 len) */
immlen = 0;
case X86_POSTOP_SHIFT:
/* Handle shift postop special-casing */
if (num && yasm_intnum_get_uint(num) == 1) {
/* We can use the ,1 form: no imm (set to 0 len) */
immlen = 0;
if (save) {
/* Make the ,1 form permanent. */
insn->opcode.opcode[0] = insn->opcode.opcode[1];
/* Delete imm, as it's not needed. */
yasm_expr_destroy(imm->val);
yasm_xfree(imm);
insn->imm = (yasm_immval *)NULL;
}
} else
retval = YASM_BC_RESOLVE_NONE; /* we could still get ,1 */
if (save) {
/* Make the ,1 form permanent. */
insn->opcode.opcode[0] = insn->opcode.opcode[1];
/* Delete imm, as it's not needed. */
yasm_expr_destroy(imm->val);
yasm_xfree(imm);
insn->imm = (yasm_immval *)NULL;
}
} else
retval = YASM_BC_RESOLVE_NONE; /* could still get ,1 */
/* Not really necessary, but saves confusion over it. */
if (save)
insn->postop = X86_POSTOP_NONE;
break;
/* Not really necessary, but saves confusion over it. */
if (save)
insn->postop = X86_POSTOP_NONE;
default:
break;
}
yasm_expr_destroy(temp);

@ -51,30 +51,31 @@ RCSID("$Id$");
#define MOD_Imm8 (1UL<<9) /* Parameter is included as immediate byte */
#define MOD_AdSizeR (1UL<<10) /* Parameter replaces addrsize (jmp only) */
#define MOD_DOpS64R (1UL<<11) /* Parameter replaces default 64-bit opersize */
#define MOD_Op2AddSp (1UL<<12) /* Parameter is added as "spare" to opcode byte 2 */
/* Modifiers that aren't: these are used with the GAS parser to indicate
* special cases.
*/
#define MOD_GasOnly (1UL<<12) /* Only available in GAS mode */
#define MOD_GasIllegal (1UL<<13) /* Illegal in GAS mode */
#define MOD_GasNoRev (1UL<<14) /* Don't reverse operands */
#define MOD_GasSufB (1UL<<15) /* GAS B suffix ok */
#define MOD_GasSufW (1UL<<16) /* GAS W suffix ok */
#define MOD_GasSufL (1UL<<17) /* GAS L suffix ok */
#define MOD_GasSufQ (1UL<<18) /* GAS Q suffix ok */
#define MOD_GasSufS (1UL<<19) /* GAS S suffix ok */
#define MOD_GasSuf_SHIFT 15
#define MOD_GasSuf_MASK (0x1FUL<<15)
#define MOD_GasOnly (1UL<<13) /* Only available in GAS mode */
#define MOD_GasIllegal (1UL<<14) /* Illegal in GAS mode */
#define MOD_GasNoRev (1UL<<15) /* Don't reverse operands */
#define MOD_GasSufB (1UL<<16) /* GAS B suffix ok */
#define MOD_GasSufW (1UL<<17) /* GAS W suffix ok */
#define MOD_GasSufL (1UL<<18) /* GAS L suffix ok */
#define MOD_GasSufQ (1UL<<19) /* GAS Q suffix ok */
#define MOD_GasSufS (1UL<<20) /* GAS S suffix ok */
#define MOD_GasSuf_SHIFT 16
#define MOD_GasSuf_MASK (0x1FUL<<16)
/* Modifiers that aren't actually used as modifiers. Rather, if set, bits
* 20-27 in the modifier are used as an index into an array.
* Obviously, only one of these may be set at a time.
*/
#define MOD_ExtNone (0UL<<28) /* No extended modifier */
#define MOD_ExtErr (1UL<<28) /* Extended error: index into error strings */
#define MOD_ExtWarn (2UL<<28) /* Extended warning: index into warning strs */
#define MOD_Ext_MASK (0xFUL<<28)
#define MOD_ExtIndex_SHIFT 20
#define MOD_ExtNone (0UL<<29) /* No extended modifier */
#define MOD_ExtErr (1UL<<29) /* Extended error: index into error strings */
#define MOD_ExtWarn (2UL<<29) /* Extended warning: index into warning strs */
#define MOD_Ext_MASK (0x3UL<<29)
#define MOD_ExtIndex_SHIFT 21
#define MOD_ExtIndex(indx) (((unsigned long)(indx))<<MOD_ExtIndex_SHIFT)
#define MOD_ExtIndex_MASK (0xFFUL<<MOD_ExtIndex_SHIFT)
@ -152,6 +153,7 @@ RCSID("$Id$");
* 2 = large imm16/32 that can become a sign-extended imm8.
* 3 = could become a short opcode mov with bits=64 and a32 prefix
* 4 = forced 16-bit address size (override ignored, no prefix)
* 5 = large imm64 that can become a sign-extended imm32.
*/
#define OPT_Imm 0x0
#define OPT_Reg 0x1
@ -219,6 +221,7 @@ RCSID("$Id$");
#define OPAP_SImm8Avail (2UL<<17)
#define OPAP_ShortMov (3UL<<17)
#define OPAP_A16 (4UL<<17)
#define OPAP_SImm32Avail (5UL<<17)
#define OPAP_MASK (7UL<<17)
typedef struct x86_insn_info {
@ -470,8 +473,12 @@ static const x86_insn_info mov_insn[] = {
{OPT_Reg|OPS_16|OPA_Op0Add, OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm, 0} },
{ CPU_386, MOD_GasSufL, 32, 0, 0, 1, {0xB8, 0, 0}, 0, 2,
{OPT_Reg|OPS_32|OPA_Op0Add, OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm, 0} },
{ CPU_Hammer|CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2,
{OPT_Reg|OPS_64|OPA_Op0Add, OPT_Imm|OPS_64|OPS_Relaxed|OPA_Imm, 0} },
/* 64-bit forced size form */
{ CPU_Hammer|CPU_64, MOD_GasIllegal, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2,
{OPT_Reg|OPS_64|OPA_Op0Add, OPT_Imm|OPS_64|OPA_Imm, 0} },
{ CPU_Hammer|CPU_64, MOD_GasSufQ, 64, 0, 0, 1, {0xB8, 0xC7, 0}, 0, 2,
{OPT_Reg|OPS_64|OPA_Op0Add,
OPT_Imm|OPS_64|OPS_Relaxed|OPA_Imm|OPAP_SImm32Avail, 0} },
/* Need two sets here, one for strictness on left side, one for right. */
{ CPU_Any, MOD_GasSufB, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2,
{OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPA_Imm, 0} },
@ -833,33 +840,47 @@ static const x86_insn_info lfgss_insn[] = {
/* Arithmetic - general */
static const x86_insn_info arith_insn[] = {
/* Also have forced-size forms to override the optimization */
{ CPU_Any, MOD_Op0Add|MOD_GasSufB, 0, 0, 0, 1, {0x04, 0, 0}, 0, 2,
{OPT_Areg|OPS_8|OPA_None, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
{ CPU_Any, MOD_Op0Add|MOD_GasSufW, 16, 0, 0, 1, {0x05, 0, 0}, 0, 2,
{OPT_Areg|OPS_16|OPA_None, OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm, 0} },
{ CPU_386, MOD_Op0Add|MOD_GasSufL, 32, 0, 0, 1, {0x05, 0, 0}, 0, 2,
{OPT_Areg|OPS_32|OPA_None, OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm, 0} },
{ CPU_Hammer|CPU_64, MOD_Op0Add|MOD_GasSufQ, 64, 0, 0, 1, {0x05, 0, 0}, 0,
2, {OPT_Areg|OPS_64|OPA_None, OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm, 0} },
{ CPU_Any, MOD_Op0Add|MOD_GasIllegal, 16, 0, 0, 1, {0x05, 0, 0}, 0, 2,
{OPT_Areg|OPS_16|OPA_None, OPT_Imm|OPS_16|OPA_Imm, 0} },
{ CPU_Any, MOD_Op0Add|MOD_Op2AddSp|MOD_GasSufW, 16, 0, 0, 1,
{0x05, 0x83, 0xC0}, 0, 2,
{OPT_Areg|OPS_16|OPA_None,
OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm|OPAP_SImm8Avail, 0} },
{ CPU_386, MOD_Op0Add|MOD_GasIllegal, 32, 0, 0, 1, {0x05, 0, 0}, 0, 2,
{OPT_Areg|OPS_32|OPA_None, OPT_Imm|OPS_32|OPA_Imm, 0} },
{ CPU_386, MOD_Op0Add|MOD_Op2AddSp|MOD_GasSufL, 32, 0, 0, 1,
{0x05, 0x83, 0xC0}, 0, 2,
{OPT_Areg|OPS_32|OPA_None,
OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm|OPAP_SImm8Avail, 0} },
{ CPU_Hammer|CPU_64, MOD_Op0Add|MOD_GasIllegal, 64, 0, 0, 1, {0x05, 0, 0},
0, 2, {OPT_Areg|OPS_64|OPA_None, OPT_Imm|OPS_32|OPA_Imm, 0} },
{ CPU_Hammer|CPU_64, MOD_Op0Add|MOD_Op2AddSp|MOD_GasSufQ, 64, 0, 0, 1,
{0x05, 0x83, 0xC0}, 0,
2, {OPT_Areg|OPS_64|OPA_None,
OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm|OPAP_SImm8Avail, 0} },
/* Also have forced-size forms to override the optimization */
{ CPU_Any, MOD_Gap0|MOD_SpAdd|MOD_GasSufB, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2,
{OPT_RM|OPS_8|OPA_EA, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },
{ CPU_Any, MOD_Gap0|MOD_SpAdd|MOD_GasSufB, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2,
{OPT_RM|OPS_8|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_8|OPA_Imm, 0} },
{ CPU_Any, MOD_Gap0|MOD_SpAdd|MOD_GasSufW, 16, 0, 0, 1, {0x83, 0, 0}, 0, 2,
{OPT_RM|OPS_16|OPA_EA, OPT_Imm|OPS_8|OPA_SImm, 0} },
{ CPU_Any, MOD_Gap0|MOD_SpAdd|MOD_GasIllegal, 16, 0, 0, 1, {0x81, 0, 0}, 0,
2, {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_16|OPA_Imm, 0} },
{ CPU_Any, MOD_Gap0|MOD_SpAdd|MOD_GasSufW, 16, 0, 0, 1, {0x81, 0x83, 0}, 0,
2, {OPT_RM|OPS_16|OPA_EA,
OPT_Imm|OPS_16|OPS_Relaxed|OPA_Imm|OPAP_SImm8Avail, 0} },
{ CPU_Any, MOD_Gap0|MOD_SpAdd|MOD_GasSufW, 16, 0, 0, 1, {0x81, 0, 0}, 0, 2,
{OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_16|OPA_Imm, 0} },
{ CPU_386, MOD_Gap0|MOD_SpAdd|MOD_GasSufL, 32, 0, 0, 1, {0x83, 0, 0}, 0, 2,
{OPT_RM|OPS_32|OPA_EA, OPT_Imm|OPS_8|OPA_SImm, 0} },
{ CPU_386, MOD_Gap0|MOD_SpAdd|MOD_GasIllegal, 32, 0, 0, 1, {0x81, 0, 0}, 0,
2, {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_32|OPA_Imm, 0} },
{ CPU_386, MOD_Gap0|MOD_SpAdd|MOD_GasSufL, 32, 0, 0, 1, {0x81, 0x83, 0}, 0,
2, {OPT_RM|OPS_32|OPA_EA,
OPT_Imm|OPS_32|OPS_Relaxed|OPA_Imm|OPAP_SImm8Avail, 0} },
{ CPU_386, MOD_Gap0|MOD_SpAdd|MOD_GasSufL, 32, 0, 0, 1, {0x81, 0, 0}, 0, 2,
{OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_Imm|OPS_32|OPA_Imm, 0} },
{ CPU_Hammer|CPU_64, MOD_Gap0|MOD_SpAdd|MOD_GasSufQ, 64, 0, 0, 1,
{0x83, 0, 0}, 0, 2,
{OPT_RM|OPS_64|OPA_EA, OPT_Imm|OPS_8|OPA_SImm, 0} },
@ -2646,6 +2667,10 @@ yasm_x86__finalize_insn(yasm_arch *arch, yasm_bytecode *bc,
}
if (info->modifiers & MOD_DOpS64R) {
insn->def_opersize_64 = (unsigned char)(mod_data & 0xFF);
mod_data >>= 8;
}
if (info->modifiers & MOD_Op2AddSp) {
insn->opcode.opcode[2] += (unsigned char)(mod_data & 0xFF)<<3;
/*mod_data >>= 8;*/
}
@ -2790,6 +2815,9 @@ yasm_x86__finalize_insn(yasm_arch *arch, yasm_bytecode *bc,
case OPAP_A16:
insn->postop = X86_POSTOP_ADDRESS16;
break;
case OPAP_SImm32Avail:
insn->postop = X86_POSTOP_SIGNEXT_IMM32;
break;
default:
yasm_internal_error(
N_("unknown operand postponed action"));

@ -4,4 +4,6 @@ dd end-start
start:
mov rax, $
mov rbx, $
mov rax, qword $
mov rbx, qword $
end:

@ -0,0 +1,2 @@
-:5: warning: value does not fit in 32 bit field
-:6: warning: value does not fit in 32 bit field

@ -1,20 +1,34 @@
14
22
00
00
00
48
b8
c7
c0
04
00
00
00
48
c7
c3
0b
00
00
00
48
b8
12
00
00
00
f1
ff
0f
00
48
bb
0e
1c
00
00
00

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

@ -30,7 +30,7 @@
00
00
00
e0
d0
00
00
00
@ -62,15 +62,11 @@ e0
00
00
00
2d
83
e8
30
00
00
00
c3
00
00
00
2e
74
65
@ -250,18 +246,6 @@ ff
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
17
00
00
@ -278,7 +262,7 @@ ff
00
00
00
48
44
00
00
00
@ -318,7 +302,7 @@ ff
00
00
00
6c
68
00
00
00
@ -358,7 +342,7 @@ ff
00
00
00
84
80
00
00
00
@ -402,7 +386,7 @@ ff
00
00
00
06
04
00
00
00

@ -63,11 +63,8 @@ b0
01
00
48
b8
00
00
00
00
c7
c0
00
00
00
@ -162,7 +159,10 @@ b8
00
00
00
0e
00
00
00
0b
00
00
00
@ -186,7 +186,7 @@ b8
00
00
00
15
12
00
00
00
@ -210,7 +210,7 @@ ff
ff
ff
ff
1c
19
00
00
00
@ -234,7 +234,7 @@ ff
00
00
00
24
21
00
00
00
@ -258,7 +258,7 @@ ff
ff
ff
ff
2c
29
00
00
00
@ -282,7 +282,7 @@ c0
00
00
00
33
30
00
00
00
@ -306,7 +306,7 @@ bc
00
00
00
3a
37
00
00
00
@ -330,7 +330,7 @@ c4
00
00
00
42
3f
00
00
00
@ -354,7 +354,7 @@ bc
00
00
00
4a
47
00
00
00
@ -378,7 +378,7 @@ bc
00
00
00
51
4e
00
00
00
@ -402,7 +402,7 @@ ff
ff
ff
ff
58
55
00
00
00
@ -426,7 +426,7 @@ ff
00
00
00
60
5d
00
00
00
@ -1230,7 +1230,7 @@ c0
00
00
00
64
61
00
00
00

@ -32,26 +32,26 @@ x86ident:
; This instruction generates a different relocation than
; MASM does at present.
mov ebx, foobar ; WTF ML64.. this had []
mov rcx, foobar
mov rcx, qword foobar
lea rdx, [foobar wrt rip]
mov rax, [foobar+rcx]
mov rax, foobar
mov rbx, foobar
mov rax, qword foobar
mov rbx, qword foobar
movzx rax, byte [foobar wrt rip]
movzx rax, byte [foobar+rax]
; local "proc"
; See note above
mov ebx, trap
mov rcx, trap
mov rcx, qword trap
; MASM generates a REL32 reloc for this even though it's in
; the same section. I don't know why, as the call instruction
; below doesn't cause a reloc, so the linker can't be moving
; functions around within an object!
lea rdx, [trap wrt rip]
mov rax, [trap+rcx]
mov rax, trap
mov rbx, trap
mov rax, qword trap
mov rbx, qword trap
; MASM generates a REL32 reloc for this even though it's in
; the same section. I don't know why, as the call instruction
; below doesn't cause a reloc, so the linker can't be moving
@ -73,7 +73,7 @@ x86ident:
; See note above
mov ebx, foobar3
mov ebx, [foobar3 wrt rip]
mov rcx, foobar3
mov rcx, qword foobar3
lea rdx, [foobar3 wrt rip]
mov rax, [foobar3+rcx]
mov rax, [foobar3 wrt rip]
@ -85,7 +85,7 @@ x86ident:
; See note above
mov ebx, __savident
mov ebx,[__savident wrt rip]
mov rcx, __savident
mov rcx, qword __savident
lea rdx, [__savident wrt rip]
mov rax, [__savident+rcx]
mov rax, [__savident wrt rip]
@ -97,7 +97,7 @@ x86ident:
; See note above
mov ebx, savidentptr2
mov ebx, [savidentptr2 wrt rip]
mov rcx, savidentptr2
mov rcx, qword savidentptr2
lea rdx, [savidentptr2 wrt rip]
mov rax, [savidentptr2+rcx]
mov rax, [savidentptr2 wrt rip]
@ -109,7 +109,7 @@ x86ident:
; See note above
mov ebx, y
mov ebx, [y wrt rip]
mov rcx, y
mov rcx, qword y
lea rdx, [y wrt rip]
mov rax, [y+rcx]
mov rax, [y wrt rip]
@ -141,7 +141,7 @@ db 1, 7, 2, 0, 7, 1, 0x20, 0
foo_foobar3ptr dd foobar3
foo_foobar3ptr2 dq foobar3
mov ebx, [foobar3 wrt rip]
mov rcx, foobar3
mov rcx, qword foobar3
lea rdx, [foobar3 wrt rip]
mov rax, [foobar3+rcx]
mov rax, [foobar3 wrt rip]

@ -107,7 +107,7 @@ long_mode:
BITS 64
mov rax, test_code ; jmp to testcode
mov rax, qword test_code ; jmp to testcode
jmp [rax]

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