* x86id.re (yasm_x86__parse_check_insn): Enable lahf/sahf for 64-bit mode,

as these are supported on newer processor steppings.

Add testcase for lahf/sahf in all BITS modes.

svn path=/trunk/yasm/; revision=1243

modules/arch/x86/tests/Makefile.inc

@@ -71,6 +71,9 @@ EXTRA_DIST += modules/arch/x86/tests/lds-err.errwarn
 EXTRA_DIST += modules/arch/x86/tests/loopadsz.asm
 EXTRA_DIST += modules/arch/x86/tests/loopadsz.errwarn
 EXTRA_DIST += modules/arch/x86/tests/loopadsz.hex
+EXTRA_DIST += modules/arch/x86/tests/lsahf.asm
+EXTRA_DIST += modules/arch/x86/tests/lsahf.errwarn
+EXTRA_DIST += modules/arch/x86/tests/lsahf.hex
 EXTRA_DIST += modules/arch/x86/tests/mem64-err.asm
 EXTRA_DIST += modules/arch/x86/tests/mem64-err.errwarn
 EXTRA_DIST += modules/arch/x86/tests/mem64.asm

modules/arch/x86/tests/lsahf.asm

@@ -0,0 +1,9 @@
+[bits 16]
+lahf
+sahf
+[bits 32]
+lahf
+sahf
+[bits 64]
+lahf
+sahf

modules/arch/x86/tests/lsahf.hex

@@ -0,0 +1,6 @@
+9f 
+9e 
+9f 
+9e 
+9f 
+9e 

modules/arch/x86/x86id.re

@@ -3420,14 +3420,8 @@ yasm_x86__parse_check_insn(yasm_arch *arch, unsigned long data[4],
 	C L I { RET_INSN(3, onebyte, 0x00FA, CPU_Any); }
 	C L T S { RET_INSN(4, twobyte, 0x0F06, CPU_286|CPU_Priv); }
 	C M C { RET_INSN(3, onebyte, 0x00F5, CPU_Any); }
-	L A H F {
-	    not64 = 1;
- 	    RET_INSN(4, onebyte, 0x009F, CPU_Any);
-	}
-	S A H F {
-	    not64 = 1;
-	    RET_INSN(4, onebyte, 0x009E, CPU_Any);
-	}
+	L A H F { RET_INSN(4, onebyte, 0x009F, CPU_Any); }
+	S A H F { RET_INSN(4, onebyte, 0x009E, CPU_Any); }
 	P U S H F { RET_INSN(5, onebyte, 0x009C, CPU_Any); }
 	P U S H F D { RET_INSN_NONGAS(6, onebyte, 0x209C, CPU_386); }
 	P U S H F W { RET_INSN(6, onebyte, 0x109C, CPU_Any); }