Tag:
Branch:
Tree:
cc2955f21c
2.4
3.4
4.x
5.x
master
next
2.2
2.3.0
2.3.1
2.4.0
2.4.1
2.4.10
2.4.10.1
2.4.10.2
2.4.10.3
2.4.10.4
2.4.11
2.4.12
2.4.12.1
2.4.12.2
2.4.12.3
2.4.13
2.4.13.1
2.4.13.2
2.4.13.3
2.4.13.4
2.4.13.5
2.4.13.6
2.4.13.7
2.4.2
2.4.3
2.4.3-rc
2.4.3.1
2.4.3.2
2.4.4
2.4.4-beta
2.4.5
2.4.6
2.4.6.1
2.4.6.2
2.4.6.2-rc1
2.4.6.2r2
2.4.6.2r3
2.4.7
2.4.7-rc1
2.4.7.1
2.4.7.2
2.4.8
2.4.8.1
2.4.8.2
2.4.8.3
2.4.9
2.4.9.1
3.0-ocl-tech-preview
3.0-ocl-tp2
3.0.0
3.0.0-alpha
3.0.0-beta
3.0.0-rc1
3.1.0
3.2.0
3.2.0-rc
3.3.0
3.3.0-cvsdk
3.3.0-rc
3.3.1
3.3.1-cvsdk
3.4.0
3.4.0-rc
3.4.1
3.4.1-cvsdk
3.4.10
3.4.11
3.4.12
3.4.13
3.4.14
3.4.15
3.4.16
3.4.17
3.4.18
3.4.19
3.4.2
3.4.2-openvino
3.4.20
3.4.3
3.4.3-openvino
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
4.0.0
4.0.0-alpha
4.0.0-beta
4.0.0-openvino
4.0.0-rc
4.0.1
4.0.1-openvino
4.1.0
4.1.0-openvino
4.1.1
4.1.1-openvino
4.1.2
4.1.2-openvino
4.10.0
4.10.0-kleidicv
4.11.0
4.2.0
4.2.0-openvino
4.3.0
4.3.0-openvino
4.3.0-openvino-2020.3.0
4.4.0
4.4.0-openvino
4.5.0
4.5.0-openvino
4.5.1
4.5.1-openvino
4.5.2
4.5.2-openvino
4.5.3
4.5.3-openvino
4.5.3-openvino-2021.4.1
4.5.3-openvino-2021.4.2
4.5.4
4.5.5
4.5.5-openvino-2022.1.0
4.6.0
4.7.0
4.8.0
4.8.1
4.9.0
5.0.0-alpha
${ noResults }
2 Commits (cc2955f21c9e47922c64f2e1cac4ece869a0aade)
| Author | SHA1 | Message | Date |
|---|---|---|---|
HAN Liutong
|
0ef803950b
|
Merge pull request #22179 from hanliutong:new-rvv
[GSoC] New universal intrinsic backend for RVV * Add new rvv backend (partially implemented). * Modify the framework of Universal Intrinsic. * Add CV_SIMD macro guards to current UI code. * Use vlanes() instead of nlanes. * Modify the UI test. * Enable the new RVV (scalable) backend. * Remove whitespace. * Rename and some others modify. * Update intrin.hpp but still not work on AVX/SSE * Update conditional compilation macros. * Use static variable for vlanes. * Use max_nlanes for array defining. |
3 years ago |
Alexander Alekhin
|
3f302cabb8 |
core(test): intrinsic tests for all dispatched CPU optimizations
- tests for both SIMD128 / SIMD256 - different dispatched + baseline(SIMD128) intrinsics |
7 years ago |