Updated KleidiCV HAL to version 0.2. #26241
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* use 2 parms for now to identify the error
* Revert "use 2 parms for now to identify the error"
This reverts commit 86faf993a7.
* replace += with =
* add v_log ref
* refactor intrin_math code
* Add include guard to `intrin_math.hpp` to prevent multiple inclusions
* rename VX to V; make fp64 impl in neon be optional
* add v_setall, v_setzero for all backends; rewrite the intrin_math
* fix error on rvv_scalable
* let v_erf use v_exp_default_32f function
* 1. replaced 'v_setzero(VecType dummy)' with 'v_setzero_<VecType>()'
2. replaced 'v_setall(LaneType x, VecType dummy)' with 'v_setall_<VecType>(LaneType x)'
3. added tests for the new v_setzero_<> and v_setall_<>.
* gcc does not seem to like static_assert in functions even when they are not used
* trying to fix compile errors in Debug mode on Linux
---------
Co-authored-by: Vadim Pisarevsky <vadim.pisarevsky@gmail.com>
Mirror most recent changes from https://github.com/terzakig/sqpnp/pull/24
- rank revealing QR in nullspace computation
- sqrt-free Cholesky (i.e., L*D*Lt) in the SQP solution
- replaced divisions with multiplications by inverses
- simplified checks in computeRowAndNullspace()
- removed unnecessary negations
- broke some dependency chains with parentheses
- minor other changes
HAL interface for Sharr derivatives needed for Lukas-Kanade algorithm #26163
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Documentation update for imagecodecs #26152
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Added and tested yolov5l model. #26154
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Added HAL interface for Lukas-Kanade optical flow #26143
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Documentation update for minMaxLoc #25785Fixes#25784
Update documentation for minMaxLoc to be more specific about when multi-channel images are and are not supported.
Testing:
Built documentation locally to check that updates were incorporated correctly.
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Replace operators with wrapper functions on universal intrinsics backends #26109
This PR aims to replace the operators(logic, arithmetic, bit) with wrapper functions(v_add, v_eq, v_and...)
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RISC-V/AArch64: disable CPU features detection #25901
This PR is the first step in fixing current issues with NEON/RVV, FP16, BF16 and other CPU features on AArch64 and RISC-V platforms.
On AArch64 and RISC-V platforms we usually have the platform set by default in the toolchain when we compile it or in the cmake toolchain file or in CMAKE_CXX_FLAGS by user. Then, there are two ways to set platform options: a) "-mcpu=<some_cpu>" ; b) "-march=<arch description>" (e.g. "rv64gcv"). Furthermore, there are no similar "levels" of optimizations as for x86_64, instead we have features (RVV, FP16,...) which can be enabled or disabled. So, for example, if a user has "rv64gc" set by the toolchain and we want to enable RVV. Then we need to somehow parse their current feature set and append "v" (vector optimizations) to this string. This task is quite hard and the whole procedure is prone to errors.
I propose to use "CPU_BASELINE=DETECT" by default on AArch64 and RISC-V platforms. And somehow remove other features or make them read-only/detect-only, so that OpenCV wouldn't add any extra "-march" flags to the default configuration. We would rely only on the flags provided by the compiler and cmake toolchain file. We can have some predefined configurations in our cmake toolchain files.
Changes made by this PR:
- `CMakeLists.txt`:
- use `CMAKE_CROSSCOMPILING` instead of `CMAKE_TOOLCHAIN_FILE` to detect cross-compilation. This might be useful in cases of native compilation with a toolchain file
- removed obsolete variables `ENABLE_NEON` and `ENABLE_VFPV3`, the first one have been turned ON by default on AArch64 platform which caused setting `CPU_BASELINE=NEON`
- raise minimum cmake version allowed to 3.7 to allow using `CMAKE_CXX_FLAGS_INIT` in toolchain files
- added separate files with arch flags for native compilation on AArch64 and RISC-V, these files will be used in our toolchain files and in regular cmake
- use `DETECT` as default value for `CPU_BASELINE` also allow `NATIVE`, warn user if other values were used (only for AArch64 and RISC-V)
- for each feature listed in `CPU_DISPATCH` check if corresponding `CPU_${opt}_FLAGS_ON` has been provided, warn user if it is empty (only for AArch64 and RISC-V)
- use `CPU_BASELINE_DISABLE` variable to actually turn off macros responsible for corresponding features even if they are enabled by compiler
- removed Aarch64 feature merge procedure (it didn't support `-mcpu` and built-in `-march`)
- reworked AArch64 and two RISC-V cmake toolchain files (does not affect Android/OSX/iOS/Win):
- use `CMAKE_CXX_FLAGS_INIT` to set compiler flags
- use variables `ENABLE_BF16`, `ENABLE_DOTPROD`, `ENABLE_RVV`, `ENABLE_FP16` to control `-march`
- AArch64: removed other compiler and linker flags
- `-fdata-sections`, `-fsigned-char`, `-Wl,--no-undefined`, `-Wl,--gc-sections` - already set by OpenCV
- `-Wa,--noexecstack`, `-Wl,-z,noexecstack`, `-Wl,-z,relro`, `-Wl,-z,now` - can be enabled by OpenCV via `ENABLE_HARDENING`
- `-Wno-psabi` - this option used to disable some warnings on older ARM platforms, shouldn't harm
- ARM: removed same common flags as for AArch64, but left `-mthumb` and `--fix-cortex-a8`, `-z nocopyreloc`
Update zlib-ng to 2.2.1 #26113
Release: https://github.com/zlib-ng/zlib-ng/releases/tag/2.2.1
ARM diagnostics patch: https://github.com/zlib-ng/zlib-ng/pull/1774
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Add size() to CUDA PtrStepSz #26042
According to [cppreference.com compiler support table](https://en.cppreference.com/w/cpp/compiler_support/17), `nvcc` supports `[[nodiscard]]` from version 11.
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Related: https://github.com/opencv/opencv/pull/25659
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