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@ -1038,18 +1038,6 @@ OPENCV_HAL_IMPL_NEON_BIN_FUNC(v_float64x2, v_min, vminq_f64) |
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OPENCV_HAL_IMPL_NEON_BIN_FUNC(v_float64x2, v_max, vmaxq_f64) |
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#endif |
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#if CV_SIMD128_64F |
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inline int64x2_t vmvnq_s64(int64x2_t a) |
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{ |
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int64x2_t vx = vreinterpretq_s64_u32(vdupq_n_u32(0xFFFFFFFF)); |
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return veorq_s64(a, vx); |
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} |
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inline uint64x2_t vmvnq_u64(uint64x2_t a) |
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{ |
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uint64x2_t vx = vreinterpretq_u64_u32(vdupq_n_u32(0xFFFFFFFF)); |
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return veorq_u64(a, vx); |
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} |
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#endif |
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#define OPENCV_HAL_IMPL_NEON_INT_CMP_OP(_Tpvec, cast, suffix, not_suffix) \ |
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inline _Tpvec operator == (const _Tpvec& a, const _Tpvec& b) \
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{ return _Tpvec(cast(vceqq_##suffix(a.val, b.val))); } \
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@ -1071,9 +1059,47 @@ OPENCV_HAL_IMPL_NEON_INT_CMP_OP(v_int16x8, vreinterpretq_s16_u16, s16, u16) |
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OPENCV_HAL_IMPL_NEON_INT_CMP_OP(v_uint32x4, OPENCV_HAL_NOP, u32, u32) |
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OPENCV_HAL_IMPL_NEON_INT_CMP_OP(v_int32x4, vreinterpretq_s32_u32, s32, u32) |
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OPENCV_HAL_IMPL_NEON_INT_CMP_OP(v_float32x4, vreinterpretq_f32_u32, f32, u32) |
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#if defined(__aarch64__) || defined(_M_ARM64) |
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static inline uint64x2_t vmvnq_u64(uint64x2_t a) |
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{ |
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uint64x2_t vx = vreinterpretq_u64_u32(vdupq_n_u32(0xFFFFFFFF)); |
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return veorq_u64(a, vx); |
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} |
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//OPENCV_HAL_IMPL_NEON_INT_CMP_OP(v_uint64x2, OPENCV_HAL_NOP, u64, u64)
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//OPENCV_HAL_IMPL_NEON_INT_CMP_OP(v_int64x2, vreinterpretq_s64_u64, s64, u64)
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static inline v_uint64x2 operator == (const v_uint64x2& a, const v_uint64x2& b) |
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{ return v_uint64x2(vceqq_u64(a.val, b.val)); } |
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static inline v_uint64x2 operator != (const v_uint64x2& a, const v_uint64x2& b) |
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{ return v_uint64x2(vmvnq_u64(vceqq_u64(a.val, b.val))); } |
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static inline v_int64x2 operator == (const v_int64x2& a, const v_int64x2& b) |
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{ return v_int64x2(vreinterpretq_s64_u64(vceqq_s64(a.val, b.val))); } |
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static inline v_int64x2 operator != (const v_int64x2& a, const v_int64x2& b) |
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{ return v_int64x2(vreinterpretq_s64_u64(vmvnq_u64(vceqq_s64(a.val, b.val)))); } |
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#else |
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static inline v_uint64x2 operator == (const v_uint64x2& a, const v_uint64x2& b) |
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{ |
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uint32x4_t cmp = vceqq_u32(vreinterpretq_u32_u64(a.val), vreinterpretq_u32_u64(b.val)); |
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uint32x4_t swapped = vrev64q_u32(cmp); |
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return v_uint64x2(vreinterpretq_u64_u32(vandq_u32(cmp, swapped))); |
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} |
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static inline v_uint64x2 operator != (const v_uint64x2& a, const v_uint64x2& b) |
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{ |
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uint32x4_t cmp = vceqq_u32(vreinterpretq_u32_u64(a.val), vreinterpretq_u32_u64(b.val)); |
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uint32x4_t swapped = vrev64q_u32(cmp); |
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uint64x2_t v_eq = vreinterpretq_u64_u32(vandq_u32(cmp, swapped)); |
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uint64x2_t vx = vreinterpretq_u64_u32(vdupq_n_u32(0xFFFFFFFF)); |
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return v_uint64x2(veorq_u64(v_eq, vx)); |
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} |
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static inline v_int64x2 operator == (const v_int64x2& a, const v_int64x2& b) |
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{ |
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return v_reinterpret_as_s64(v_reinterpret_as_u64(a) == v_reinterpret_as_u64(b)); |
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} |
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static inline v_int64x2 operator != (const v_int64x2& a, const v_int64x2& b) |
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{ |
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return v_reinterpret_as_s64(v_reinterpret_as_u64(a) != v_reinterpret_as_u64(b)); |
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} |
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#endif |
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#if CV_SIMD128_64F |
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OPENCV_HAL_IMPL_NEON_INT_CMP_OP(v_uint64x2, OPENCV_HAL_NOP, u64, u64) |
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OPENCV_HAL_IMPL_NEON_INT_CMP_OP(v_int64x2, vreinterpretq_s64_u64, s64, u64) |
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OPENCV_HAL_IMPL_NEON_INT_CMP_OP(v_float64x2, vreinterpretq_f64_u64, f64, u64) |
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#endif |
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