diff --git a/modules/dnn/src/layers/pooling_layer.cpp b/modules/dnn/src/layers/pooling_layer.cpp
index d4eb1f174a..dbe2332b89 100644
--- a/modules/dnn/src/layers/pooling_layer.cpp
+++ b/modules/dnn/src/layers/pooling_layer.cpp
@@ -68,6 +68,14 @@ using std::min;
 using namespace cv::dnn::ocl4dnn;
 #endif
 
+#ifdef HAVE_HALIDE
+#if 0  // size_t is not well supported in Halide operations
+typedef size_t HALIDE_DIFF_T;
+#else
+typedef int HALIDE_DIFF_T;
+#endif
+#endif
+
 namespace cv
 {
 namespace dnn
@@ -944,12 +952,12 @@ virtual Ptr<BackendNode> initNgraph(const std::vector<Ptr<BackendWrapper> >& inp
         Halide::Buffer<float> inputBuffer = halideBuffer(inputs[0]);
         const int inWidth = inputBuffer.width();
         const int inHeight = inputBuffer.height();
-        const size_t kernelHeight = kernel_size[0];
-        const size_t kernelWidth = kernel_size[1];
-        const size_t strideHeight = strides[0];
-        const size_t strideWidth = strides[1];
-        const size_t paddingTop = pads_begin[0];
-        const size_t paddingLeft = pads_begin[1];
+        const HALIDE_DIFF_T kernelHeight = (HALIDE_DIFF_T)kernel_size[0];
+        const HALIDE_DIFF_T kernelWidth = (HALIDE_DIFF_T)kernel_size[1];
+        const HALIDE_DIFF_T strideHeight = (HALIDE_DIFF_T)strides[0];
+        const HALIDE_DIFF_T strideWidth = (HALIDE_DIFF_T)strides[1];
+        const HALIDE_DIFF_T paddingTop = (HALIDE_DIFF_T)pads_begin[0];
+        const HALIDE_DIFF_T paddingLeft = (HALIDE_DIFF_T)pads_begin[1];
 
         Halide::Var x("x"), y("y"), c("c"), n("n");
         Halide::Func top = (name.empty() ? Halide::Func() : Halide::Func(name));
@@ -995,10 +1003,10 @@ virtual Ptr<BackendNode> initNgraph(const std::vector<Ptr<BackendWrapper> >& inp
         Halide::Buffer<float> inputBuffer = halideBuffer(inputs[0]);
 
         const int inW = inputBuffer.width(), inH = inputBuffer.height();
-        const size_t kernelHeight = kernel_size[0];
-        const size_t kernelWidth = kernel_size[1];
-        const size_t strideHeight = strides[0];
-        const size_t strideWidth = strides[1];
+        const HALIDE_DIFF_T kernelHeight = (HALIDE_DIFF_T)kernel_size[0];
+        const HALIDE_DIFF_T kernelWidth = (HALIDE_DIFF_T)kernel_size[1];
+        const HALIDE_DIFF_T strideHeight = (HALIDE_DIFF_T)strides[0];
+        const HALIDE_DIFF_T strideWidth = (HALIDE_DIFF_T)strides[1];
         if ((inW - kernelWidth) % strideWidth || (inH - kernelHeight) % strideHeight)
         {
             CV_Error(cv::Error::StsNotImplemented,
diff --git a/modules/dnn/test/test_backends.cpp b/modules/dnn/test/test_backends.cpp
index c88f48754c..b9958c107e 100644
--- a/modules/dnn/test/test_backends.cpp
+++ b/modules/dnn/test/test_backends.cpp
@@ -101,6 +101,9 @@ public:
 TEST_P(DNNTestNetwork, AlexNet)
 {
     applyTestTag(CV_TEST_TAG_MEMORY_1GB);
+    if (backend == DNN_BACKEND_HALIDE)  // Realization contains wrong number of Images (1) for realizing pipeline with 2 outputs
+        applyTestTag(CV_TEST_TAG_DNN_SKIP_HALIDE);
+
     processNet("dnn/bvlc_alexnet.caffemodel", "dnn/bvlc_alexnet.prototxt",
                Size(227, 227), "prob",
                target == DNN_TARGET_OPENCL ? "dnn/halide_scheduler_opencl_alexnet.yml" :
@@ -114,6 +117,9 @@ TEST_P(DNNTestNetwork, ResNet_50)
         (target == DNN_TARGET_CPU ? CV_TEST_TAG_MEMORY_512MB : CV_TEST_TAG_MEMORY_1GB),
         CV_TEST_TAG_DEBUG_LONG
     );
+    if (backend == DNN_BACKEND_HALIDE)  // Realization contains wrong number of Images (1) for realizing pipeline with 2 outputs
+        applyTestTag(CV_TEST_TAG_DNN_SKIP_HALIDE);
+
     processNet("dnn/ResNet-50-model.caffemodel", "dnn/ResNet-50-deploy.prototxt",
                Size(224, 224), "prob",
                target == DNN_TARGET_OPENCL ? "dnn/halide_scheduler_opencl_resnet_50.yml" :
@@ -123,6 +129,9 @@ TEST_P(DNNTestNetwork, ResNet_50)
 
 TEST_P(DNNTestNetwork, SqueezeNet_v1_1)
 {
+    if (backend == DNN_BACKEND_HALIDE)  // Realization contains wrong number of Images (1) for realizing pipeline with 2 outputs
+        applyTestTag(CV_TEST_TAG_DNN_SKIP_HALIDE);
+
     processNet("dnn/squeezenet_v1.1.caffemodel", "dnn/squeezenet_v1.1.prototxt",
                Size(227, 227), "prob",
                target == DNN_TARGET_OPENCL ? "dnn/halide_scheduler_opencl_squeezenet_v1_1.yml" :
@@ -133,6 +142,9 @@ TEST_P(DNNTestNetwork, SqueezeNet_v1_1)
 TEST_P(DNNTestNetwork, GoogLeNet)
 {
     applyTestTag(target == DNN_TARGET_CPU ? "" : CV_TEST_TAG_MEMORY_512MB);
+    if (backend == DNN_BACKEND_HALIDE)  // Realization contains wrong number of Images (1) for realizing pipeline with 2 outputs
+        applyTestTag(CV_TEST_TAG_DNN_SKIP_HALIDE);
+
     processNet("dnn/bvlc_googlenet.caffemodel", "dnn/bvlc_googlenet.prototxt",
                Size(224, 224), "prob");
     expectNoFallbacksFromIE(net);
@@ -141,6 +153,9 @@ TEST_P(DNNTestNetwork, GoogLeNet)
 TEST_P(DNNTestNetwork, Inception_5h)
 {
     applyTestTag(CV_TEST_TAG_MEMORY_512MB);
+    if (backend == DNN_BACKEND_HALIDE)  // Realization contains wrong number of Images (1) for realizing pipeline with 2 outputs
+        applyTestTag(CV_TEST_TAG_DNN_SKIP_HALIDE);
+
     double l1 = default_l1, lInf = default_lInf;
     if (backend == DNN_BACKEND_INFERENCE_ENGINE_NN_BUILDER_2019 && (target == DNN_TARGET_CPU || target == DNN_TARGET_OPENCL))
     {
@@ -157,6 +172,9 @@ TEST_P(DNNTestNetwork, Inception_5h)
 TEST_P(DNNTestNetwork, ENet)
 {
     applyTestTag(target == DNN_TARGET_CPU ? "" : CV_TEST_TAG_MEMORY_512MB);
+    if (backend == DNN_BACKEND_HALIDE)  // Realization contains wrong number of Images (1) for realizing pipeline with 2 outputs
+        applyTestTag(CV_TEST_TAG_DNN_SKIP_HALIDE);
+
     if (backend == DNN_BACKEND_INFERENCE_ENGINE_NN_BUILDER_2019)
         applyTestTag(CV_TEST_TAG_DNN_SKIP_IE_NN_BUILDER);
     if (backend == DNN_BACKEND_INFERENCE_ENGINE_NGRAPH)