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@ -180,66 +180,71 @@ struct SumSqr_SIMD |
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} |
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}; |
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template <typename T> |
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inline void addSqrChannels(T * sum, T * sqsum, T * buf, int cn) |
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{ |
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for (int i = 0; i < 4; ++i) |
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{ |
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sum[i % cn] += buf[i]; |
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sqsum[i % cn] += buf[4 + i]; |
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} |
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} |
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#if CV_SSE2 |
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#if CV_SIMD |
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template <> |
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struct SumSqr_SIMD<uchar, int, int> |
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{ |
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int operator () (const uchar * src0, const uchar * mask, int * sum, int * sqsum, int len, int cn) const |
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{ |
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if (mask || (cn != 1 && cn != 2) || !USE_SSE2) |
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if (mask || (cn != 1 && cn != 2 && cn != 4)) |
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return 0; |
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len *= cn; |
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int x = 0; |
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__m128i v_zero = _mm_setzero_si128(), v_sum = v_zero, v_sqsum = v_zero; |
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const int len_16 = len & ~15; |
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v_int32 v_sum = vx_setzero_s32(); |
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v_int32 v_sqsum = vx_setzero_s32(); |
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for ( ; x <= len_16 - 16; ) |
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const int len0 = len & -v_uint8::nlanes; |
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while(x < len0) |
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{ |
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const int len_tmp = min(x + 2048, len_16); |
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__m128i v_sum_tmp = v_zero; |
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for ( ; x <= len_tmp - 16; x += 16) |
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const int len_tmp = min(x + 256*v_uint16::nlanes, len0); |
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v_uint16 v_sum16 = vx_setzero_u16(); |
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for ( ; x < len_tmp; x += v_uint8::nlanes) |
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{ |
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__m128i v_src = _mm_loadu_si128((const __m128i *)(src0 + x)); |
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__m128i v_half_0 = _mm_unpacklo_epi8(v_src, v_zero); |
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__m128i v_half_1 = _mm_unpackhi_epi8(v_src, v_zero); |
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v_sum_tmp = _mm_add_epi16(v_sum_tmp, _mm_add_epi16(v_half_0, v_half_1)); |
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__m128i v_half_2 = _mm_unpacklo_epi16(v_half_0, v_half_1); |
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__m128i v_half_3 = _mm_unpackhi_epi16(v_half_0, v_half_1); |
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v_sqsum = _mm_add_epi32(v_sqsum, _mm_madd_epi16(v_half_2, v_half_2)); |
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v_sqsum = _mm_add_epi32(v_sqsum, _mm_madd_epi16(v_half_3, v_half_3)); |
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v_uint16 v_src0 = vx_load_expand(src0 + x); |
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v_uint16 v_src1 = vx_load_expand(src0 + x + v_uint16::nlanes); |
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v_sum16 += v_src0 + v_src1; |
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v_int16 v_tmp0, v_tmp1; |
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v_zip(v_reinterpret_as_s16(v_src0), v_reinterpret_as_s16(v_src1), v_tmp0, v_tmp1); |
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v_sqsum += v_dotprod(v_tmp0, v_tmp0) + v_dotprod(v_tmp1, v_tmp1); |
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} |
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v_sum = _mm_add_epi32(v_sum, _mm_unpacklo_epi16(v_sum_tmp, v_zero)); |
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v_sum = _mm_add_epi32(v_sum, _mm_unpackhi_epi16(v_sum_tmp, v_zero)); |
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v_uint32 v_half0, v_half1; |
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v_expand(v_sum16, v_half0, v_half1); |
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v_sum += v_reinterpret_as_s32(v_half0 + v_half1); |
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} |
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for ( ; x <= len - 8; x += 8) |
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if (x <= len - v_uint16::nlanes) |
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{ |
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__m128i v_src = _mm_unpacklo_epi8(_mm_loadl_epi64((__m128i const *)(src0 + x)), v_zero); |
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__m128i v_half_0 = _mm_unpackhi_epi64(v_src, v_src); |
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__m128i v_sum_tmp = _mm_add_epi16(v_src, v_half_0); |
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__m128i v_half_1 = _mm_unpacklo_epi16(v_src, v_half_0); |
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v_sum = _mm_add_epi32(v_sum, _mm_unpacklo_epi16(v_sum_tmp, v_zero)); |
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v_sqsum = _mm_add_epi32(v_sqsum, _mm_madd_epi16(v_half_1, v_half_1)); |
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} |
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v_uint16 v_src = vx_load_expand(src0 + x); |
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v_uint16 v_half = v_combine_high(v_src, v_src); |
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int CV_DECL_ALIGNED(16) ar[8]; |
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_mm_store_si128((__m128i*)ar, v_sum); |
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_mm_store_si128((__m128i*)(ar + 4), v_sqsum); |
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v_uint32 v_tmp0, v_tmp1; |
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v_expand(v_src + v_half, v_tmp0, v_tmp1); |
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v_sum += v_reinterpret_as_s32(v_tmp0); |
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addSqrChannels(sum, sqsum, ar, cn); |
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v_int16 v_tmp2, v_tmp3; |
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v_zip(v_reinterpret_as_s16(v_src), v_reinterpret_as_s16(v_half), v_tmp2, v_tmp3); |
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v_sqsum += v_dotprod(v_tmp2, v_tmp2); |
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x += v_uint16::nlanes; |
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} |
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if (cn == 1) |
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{ |
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*sum += v_reduce_sum(v_sum); |
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*sqsum += v_reduce_sum(v_sqsum); |
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} |
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else |
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{ |
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int CV_DECL_ALIGNED(CV_SIMD_WIDTH) ar[2 * v_int32::nlanes]; |
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v_store(ar, v_sum); |
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v_store(ar + v_int32::nlanes, v_sqsum); |
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for (int i = 0; i < v_int32::nlanes; ++i) |
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{ |
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sum[i % cn] += ar[i]; |
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sqsum[i % cn] += ar[v_int32::nlanes + i]; |
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} |
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} |
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v_cleanup(); |
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return x / cn; |
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} |
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}; |
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@ -249,49 +254,64 @@ struct SumSqr_SIMD<schar, int, int> |
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{ |
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int operator () (const schar * src0, const uchar * mask, int * sum, int * sqsum, int len, int cn) const |
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{ |
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if (mask || (cn != 1 && cn != 2) || !USE_SSE2) |
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if (mask || (cn != 1 && cn != 2 && cn != 4)) |
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return 0; |
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len *= cn; |
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int x = 0; |
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__m128i v_zero = _mm_setzero_si128(), v_sum = v_zero, v_sqsum = v_zero; |
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const int len_16 = len & ~15; |
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v_int32 v_sum = vx_setzero_s32(); |
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v_int32 v_sqsum = vx_setzero_s32(); |
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for ( ; x <= len_16 - 16; ) |
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const int len0 = len & -v_int8::nlanes; |
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while (x < len0) |
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{ |
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const int len_tmp = min(x + 2048, len_16); |
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__m128i v_sum_tmp = v_zero; |
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for ( ; x <= len_tmp - 16; x += 16) |
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const int len_tmp = min(x + 256 * v_int16::nlanes, len0); |
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v_int16 v_sum16 = vx_setzero_s16(); |
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for (; x < len_tmp; x += v_int8::nlanes) |
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{ |
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__m128i v_src = _mm_loadu_si128((const __m128i *)(src0 + x)); |
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__m128i v_half_0 = _mm_srai_epi16(_mm_unpacklo_epi8(v_zero, v_src), 8); |
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__m128i v_half_1 = _mm_srai_epi16(_mm_unpackhi_epi8(v_zero, v_src), 8); |
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v_sum_tmp = _mm_add_epi16(v_sum_tmp, _mm_add_epi16(v_half_0, v_half_1)); |
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__m128i v_half_2 = _mm_unpacklo_epi16(v_half_0, v_half_1); |
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__m128i v_half_3 = _mm_unpackhi_epi16(v_half_0, v_half_1); |
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v_sqsum = _mm_add_epi32(v_sqsum, _mm_madd_epi16(v_half_2, v_half_2)); |
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v_sqsum = _mm_add_epi32(v_sqsum, _mm_madd_epi16(v_half_3, v_half_3)); |
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v_int16 v_src0 = vx_load_expand(src0 + x); |
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v_int16 v_src1 = vx_load_expand(src0 + x + v_int16::nlanes); |
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v_sum16 += v_src0 + v_src1; |
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v_int16 v_tmp0, v_tmp1; |
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v_zip(v_src0, v_src1, v_tmp0, v_tmp1); |
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v_sqsum += v_dotprod(v_tmp0, v_tmp0) + v_dotprod(v_tmp1, v_tmp1); |
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} |
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v_sum = _mm_add_epi32(v_sum, _mm_srai_epi32(_mm_unpacklo_epi16(v_zero, v_sum_tmp), 16)); |
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v_sum = _mm_add_epi32(v_sum, _mm_srai_epi32(_mm_unpackhi_epi16(v_zero, v_sum_tmp), 16)); |
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v_int32 v_half0, v_half1; |
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v_expand(v_sum16, v_half0, v_half1); |
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v_sum += v_half0 + v_half1; |
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} |
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for ( ; x <= len - 8; x += 8) |
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if (x <= len - v_int16::nlanes) |
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{ |
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__m128i v_src = _mm_srai_epi16(_mm_unpacklo_epi8(v_zero, _mm_loadl_epi64((__m128i const *)(src0 + x))), 8); |
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__m128i v_half_0 = _mm_unpackhi_epi64(v_src, v_src); |
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__m128i v_sum_tmp = _mm_add_epi16(v_src, v_half_0); |
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__m128i v_half_1 = _mm_unpacklo_epi16(v_src, v_half_0); |
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v_int16 v_src = vx_load_expand(src0 + x); |
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v_int16 v_half = v_combine_high(v_src, v_src); |
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v_sum = _mm_add_epi32(v_sum, _mm_srai_epi32(_mm_unpacklo_epi16(v_zero, v_sum_tmp), 16)); |
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v_sqsum = _mm_add_epi32(v_sqsum, _mm_madd_epi16(v_half_1, v_half_1)); |
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} |
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v_int32 v_tmp0, v_tmp1; |
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v_expand(v_src + v_half, v_tmp0, v_tmp1); |
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v_sum += v_tmp0; |
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int CV_DECL_ALIGNED(16) ar[8]; |
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_mm_store_si128((__m128i*)ar, v_sum); |
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_mm_store_si128((__m128i*)(ar + 4), v_sqsum); |
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addSqrChannels(sum, sqsum, ar, cn); |
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v_int16 v_tmp2, v_tmp3; |
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v_zip(v_src, v_half, v_tmp2, v_tmp3); |
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v_sqsum += v_dotprod(v_tmp2, v_tmp2); |
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x += v_int16::nlanes; |
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} |
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if (cn == 1) |
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{ |
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*sum += v_reduce_sum(v_sum); |
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*sqsum += v_reduce_sum(v_sqsum); |
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} |
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else |
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{ |
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int CV_DECL_ALIGNED(CV_SIMD_WIDTH) ar[2 * v_int32::nlanes]; |
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v_store(ar, v_sum); |
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v_store(ar + v_int32::nlanes, v_sqsum); |
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for (int i = 0; i < v_int32::nlanes; ++i) |
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{ |
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sum[i % cn] += ar[i]; |
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sqsum[i % cn] += ar[v_int32::nlanes + i]; |
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} |
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} |
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v_cleanup(); |
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return x / cn; |
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} |
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}; |
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