From cdd8395f68ca6735fb76ebc630ec965fa6624125 Mon Sep 17 00:00:00 2001 From: Suleyman TURKMEN Date: Wed, 3 Jul 2024 19:55:35 +0300 Subject: [PATCH 01/18] add getFrameCount() --- .../imgcodecs/include/opencv2/imgcodecs.hpp | 6 ++++-- modules/imgcodecs/src/grfmt_avif.cpp | 1 + modules/imgcodecs/src/grfmt_base.cpp | 1 + modules/imgcodecs/src/grfmt_base.hpp | 2 ++ modules/imgcodecs/src/grfmt_tiff.cpp | 1 + modules/imgcodecs/src/loadsave.cpp | 20 +------------------ modules/imgcodecs/test/test_avif.cpp | 1 + 7 files changed, 11 insertions(+), 21 deletions(-) diff --git a/modules/imgcodecs/include/opencv2/imgcodecs.hpp b/modules/imgcodecs/include/opencv2/imgcodecs.hpp index c3a1d4b082..62d895e473 100644 --- a/modules/imgcodecs/include/opencv2/imgcodecs.hpp +++ b/modules/imgcodecs/include/opencv2/imgcodecs.hpp @@ -305,11 +305,13 @@ The function imreadmulti loads a specified range from a multi-page image from th */ CV_EXPORTS_W bool imreadmulti(const String& filename, CV_OUT std::vector& mats, int start, int count, int flags = IMREAD_ANYCOLOR); -/** @brief Returns the number of images inside the give file +/** @brief Returns the number of images inside the given file -The function imcount will return the number of pages in a multi-page image, or 1 for single-page images +The function imcount returns the number of pages in a multi-page image (e.g. TIFF), the number of frames in an animation (e.g. AVIF), and 1 otherwise. +If the image cannot be decoded, 0 is returned. @param filename Name of file to be loaded. @param flags Flag that can take values of cv::ImreadModes, default with cv::IMREAD_ANYCOLOR. +@todo when cv::IMREAD_LOAD_GDAL flag used the return value will be 0 or 1 because OpenCV's GDAL decoder doesn't support multi-page reading yet. */ CV_EXPORTS_W size_t imcount(const String& filename, int flags = IMREAD_ANYCOLOR); diff --git a/modules/imgcodecs/src/grfmt_avif.cpp b/modules/imgcodecs/src/grfmt_avif.cpp index d71843c3f0..c1d3682d0c 100644 --- a/modules/imgcodecs/src/grfmt_avif.cpp +++ b/modules/imgcodecs/src/grfmt_avif.cpp @@ -195,6 +195,7 @@ bool AvifDecoder::readHeader() { m_width = decoder_->image->width; m_height = decoder_->image->height; + m_frame_count = decoder_->imageCount; channels_ = (decoder_->image->yuvFormat == AVIF_PIXEL_FORMAT_YUV400) ? 1 : 3; if (decoder_->alphaPresent) ++channels_; bit_depth_ = decoder_->image->depth; diff --git a/modules/imgcodecs/src/grfmt_base.cpp b/modules/imgcodecs/src/grfmt_base.cpp index da343941bd..6ae9d98f24 100644 --- a/modules/imgcodecs/src/grfmt_base.cpp +++ b/modules/imgcodecs/src/grfmt_base.cpp @@ -54,6 +54,7 @@ BaseImageDecoder::BaseImageDecoder() m_buf_supported = false; m_scale_denom = 1; m_use_rgb = false; + m_frame_count = 1; } diff --git a/modules/imgcodecs/src/grfmt_base.hpp b/modules/imgcodecs/src/grfmt_base.hpp index 0d98c51ae2..9ae23b24df 100644 --- a/modules/imgcodecs/src/grfmt_base.hpp +++ b/modules/imgcodecs/src/grfmt_base.hpp @@ -64,6 +64,7 @@ public: int width() const { return m_width; } int height() const { return m_height; } + size_t getFrameCount() const { return m_frame_count; } virtual int type() const { return m_type; } ExifEntry_t getExifTag(const ExifTagName tag) const; @@ -93,6 +94,7 @@ protected: bool m_buf_supported; bool m_use_rgb; // flag of decode image as RGB order instead of BGR. ExifReader m_exif; + size_t m_frame_count; }; diff --git a/modules/imgcodecs/src/grfmt_tiff.cpp b/modules/imgcodecs/src/grfmt_tiff.cpp index 41607006e2..f68a6e5c0d 100644 --- a/modules/imgcodecs/src/grfmt_tiff.cpp +++ b/modules/imgcodecs/src/grfmt_tiff.cpp @@ -279,6 +279,7 @@ bool TiffDecoder::readHeader() m_width = wdth; m_height = hght; + m_frame_count = TIFFNumberOfDirectories(tif); if (ncn == 3 && photometric == PHOTOMETRIC_LOGLUV) { m_type = CV_32FC3; diff --git a/modules/imgcodecs/src/loadsave.cpp b/modules/imgcodecs/src/loadsave.cpp index 354f2a4b34..8eedb0d907 100644 --- a/modules/imgcodecs/src/loadsave.cpp +++ b/modules/imgcodecs/src/loadsave.cpp @@ -1263,26 +1263,8 @@ void ImageCollection::Impl::init(String const& filename, int flags) { m_decoder->setSource(filename); CV_Assert(m_decoder->readHeader()); - // count the pages of the image collection - size_t count = 1; - while(m_decoder->nextPage()) count++; - - m_size = count; + m_size = m_decoder->getFrameCount(); m_pages.resize(m_size); - // Reinitialize the decoder because we advanced to the last page while counting the pages of the image -#ifdef HAVE_GDAL - if (m_flags != IMREAD_UNCHANGED && (m_flags & IMREAD_LOAD_GDAL) == IMREAD_LOAD_GDAL) { - m_decoder = GdalDecoder().newDecoder(); - } - else { -#endif - m_decoder = findDecoder(m_filename); -#ifdef HAVE_GDAL - } -#endif - - m_decoder->setSource(m_filename); - m_decoder->readHeader(); } size_t ImageCollection::Impl::size() const { return m_size; } diff --git a/modules/imgcodecs/test/test_avif.cpp b/modules/imgcodecs/test/test_avif.cpp index 227c69556d..68678599b2 100644 --- a/modules/imgcodecs/test/test_avif.cpp +++ b/modules/imgcodecs/test/test_avif.cpp @@ -296,6 +296,7 @@ TEST_P(Imgcodecs_Avif_Animation_WriteReadSuite, encode_decode) { return; } EXPECT_NO_THROW(cv::imwritemulti(output, anim_original, encoding_params_)); + EXPECT_EQ(anim_original.size(), imcount(output)); // Read from file. std::vector anim; From da078c4b755267129c83aad9624744b435b0cf3d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Corentin=20No=C3=ABl?= Date: Sat, 13 Jul 2024 12:40:00 +0200 Subject: [PATCH 02/18] highgui: Make GThread mandatory with GTK The GThread API is available since more than 11 years with GLib, it is now safe to assume that it is always available. --- CMakeLists.txt | 8 +------- modules/highgui/CMakeLists.txt | 12 ------------ modules/highgui/cmake/detect_gtk.cmake | 8 +------- .../misc/plugins/plugin_gtk/CMakeLists.txt | 6 ------ modules/highgui/src/window_gtk.cpp | 17 ----------------- 5 files changed, 2 insertions(+), 49 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index f00ac637d5..0587f94e9f 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1465,16 +1465,10 @@ if(WITH_GTK OR HAVE_GTK) status(" GTK+:" "YES (ver ${GTK3_VERSION})") elseif(HAVE_GTK) status(" GTK+:" "YES (ver ${GTK2_VERSION})") + status(" GtkGlExt:" HAVE_GTKGLEXT THEN "YES (ver ${GTKGLEXT_VERSION})" ELSE NO) else() status(" GTK+:" "NO") endif() - - if(HAVE_GTK) - status( " GThread :" HAVE_GTHREAD THEN "YES (ver ${GTHREAD_VERSION})" ELSE NO) - if(NOT HAVE_GTK3) - status( " GtkGlExt:" HAVE_GTKGLEXT THEN "YES (ver ${GTKGLEXT_VERSION})" ELSE NO) - endif() - endif() endif() if(WITH_FRAMEBUFFER OR HAVE_FRAMEBUFFER) diff --git a/modules/highgui/CMakeLists.txt b/modules/highgui/CMakeLists.txt index c1d42444c5..ab5e5391ec 100644 --- a/modules/highgui/CMakeLists.txt +++ b/modules/highgui/CMakeLists.txt @@ -228,9 +228,6 @@ if(TARGET ocv.3rdparty.gtk3 OR TARGET ocv.3rdparty.gtk2) endif() list(APPEND highgui_srcs ${CMAKE_CURRENT_LIST_DIR}/src/window_gtk.cpp) list(APPEND tgts ${__gtk_dependency}) - if(TARGET ocv.3rdparty.gthread) - list(APPEND tgts ocv.3rdparty.gthread) - endif() if(TARGET ocv.3rdparty.gtkglext AND __gtk_dependency STREQUAL "ocv.3rdparty.gtk2" AND NOT OPENCV_GTK_DISABLE_GTKGLEXT @@ -245,27 +242,18 @@ if(TARGET ocv.3rdparty.gtk3 OR TARGET ocv.3rdparty.gtk2) endif() elseif("gtk" IN_LIST HIGHGUI_PLUGIN_LIST) ocv_create_builtin_highgui_plugin(opencv_highgui_gtk ${__gtk_dependency} "window_gtk.cpp") - if(TARGET ocv.3rdparty.gthread) - ocv_target_link_libraries(opencv_highgui_gtk ocv.3rdparty.gthread) - endif() if(TARGET ocv.3rdparty.gtkglext) ocv_target_link_libraries(opencv_highgui_gtk ocv.3rdparty.gtkglext) endif() else() if(TARGET ocv.3rdparty.gtk3 AND ("gtk3" IN_LIST HIGHGUI_PLUGIN_LIST OR HIGHGUI_PLUGIN_LIST STREQUAL "all")) ocv_create_builtin_highgui_plugin(opencv_highgui_gtk3 ocv.3rdparty.gtk3 "window_gtk.cpp") - if(TARGET ocv.3rdparty.gthread) - ocv_target_link_libraries(opencv_highgui_gtk3 ocv.3rdparty.gthread) - endif() if(TARGET ocv.3rdparty.gtkglext) ocv_target_link_libraries(opencv_highgui_gtk3 ocv.3rdparty.gtkglext) endif() endif() if(TARGET ocv.3rdparty.gtk2 AND ("gtk2" IN_LIST HIGHGUI_PLUGIN_LIST OR HIGHGUI_PLUGIN_LIST STREQUAL "all")) ocv_create_builtin_highgui_plugin(opencv_highgui_gtk2 ocv.3rdparty.gtk2 "window_gtk.cpp") - if(TARGET ocv.3rdparty.gthread) - ocv_target_link_libraries(opencv_highgui_gtk2 ocv.3rdparty.gthread) - endif() if(TARGET ocv.3rdparty.gtkglext) ocv_target_link_libraries(opencv_highgui_gtk2 ocv.3rdparty.gtkglext) endif() diff --git a/modules/highgui/cmake/detect_gtk.cmake b/modules/highgui/cmake/detect_gtk.cmake index fdca580aa9..e41da1c68e 100644 --- a/modules/highgui/cmake/detect_gtk.cmake +++ b/modules/highgui/cmake/detect_gtk.cmake @@ -1,5 +1,5 @@ # --- GTK --- -ocv_clear_vars(HAVE_GTK HAVE_GTK2 HAVE_GTK3 HAVE_GTHREAD HAVE_GTKGLEXT) +ocv_clear_vars(HAVE_GTK HAVE_GTK2 HAVE_GTK3 HAVE_GTKGLEXT) if(WITH_GTK) if(NOT WITH_GTK_2_X) ocv_check_modules(GTK3 gtk+-3.0) @@ -20,12 +20,6 @@ if(WITH_GTK) endif() endif() endif() - ocv_check_modules(GTHREAD gthread-2.0>=2.32) - if(HAVE_GTK AND NOT HAVE_GTHREAD) - message(FATAL_ERROR "gthread not found. This library is required when building with GTK support") - else() - ocv_add_external_target(gthread "${GTHREAD_INCLUDE_DIRS}" "${GTHREAD_LIBRARIES}" "HAVE_GTHREAD") - endif() if((WITH_OPENGL OR HAVE_OPENGL) AND (HAVE_GTK2 OR HAVE_GTK3)) if(HAVE_GTK2) ocv_check_modules(GTKGLEXT gtkglext-1.0) diff --git a/modules/highgui/misc/plugins/plugin_gtk/CMakeLists.txt b/modules/highgui/misc/plugins/plugin_gtk/CMakeLists.txt index 6a2da0c9c3..c9cd0b6f1b 100644 --- a/modules/highgui/misc/plugins/plugin_gtk/CMakeLists.txt +++ b/modules/highgui/misc/plugins/plugin_gtk/CMakeLists.txt @@ -50,9 +50,3 @@ elseif(DEFINED GTK_VERSION) else() message(STATUS "GTK+: YES") endif() - -if(HAVE_GTHREAD) - message(STATUS "GThread : YES (ver ${GTHREAD_VERSION})") -else() - message(STATUS "GThread : NO") -endif() diff --git a/modules/highgui/src/window_gtk.cpp b/modules/highgui/src/window_gtk.cpp index aa4c8ea634..178d1b7475 100644 --- a/modules/highgui/src/window_gtk.cpp +++ b/modules/highgui/src/window_gtk.cpp @@ -608,13 +608,11 @@ static gboolean icvOnKeyPress( GtkWidget* widget, GdkEventKey* event, gpointer u static void icvOnTrackbar( GtkWidget* widget, gpointer user_data ); static gboolean icvOnMouse( GtkWidget *widget, GdkEvent *event, gpointer user_data ); -#ifdef HAVE_GTHREAD int thread_started=0; static gpointer icvWindowThreadLoop(gpointer data); GMutex* last_key_mutex = NULL; GCond* cond_have_key = NULL; GThread* window_thread = NULL; -#endif static int last_key = -1; @@ -660,7 +658,6 @@ CV_IMPL int cvInitSystem( int argc, char** argv ) } CV_IMPL int cvStartWindowThread(){ -#ifdef HAVE_GTHREAD cvInitSystem(0,NULL); if (!thread_started) { @@ -676,12 +673,8 @@ CV_IMPL int cvStartWindowThread(){ } thread_started = window_thread!=NULL; return thread_started; -#else - return 0; -#endif } -#ifdef HAVE_GTHREAD gpointer icvWindowThreadLoop(gpointer /*data*/) { while(1){ @@ -698,8 +691,6 @@ gpointer icvWindowThreadLoop(gpointer /*data*/) return NULL; } -#endif - #define CV_LOCK_MUTEX() cv::AutoLock lock(getWindowMutex()) static @@ -1282,7 +1273,6 @@ static void checkLastWindow() // if last window... if (getGTKWindows().empty()) { -#ifdef HAVE_GTHREAD if( thread_started ) { // send key press signal to jump out of any waiting cvWaitKey's @@ -1290,7 +1280,6 @@ static void checkLastWindow() } else { -#endif // Some GTK+ modules (like the Unity module) use GDBusConnection, // which has a habit of postponing cleanup by performing it via // idle sources added to the main loop. Since this was the last window, @@ -1301,9 +1290,7 @@ static void checkLastWindow() // thread will process events continuously. while( gtk_events_pending() ) gtk_main_iteration(); -#ifdef HAVE_GTHREAD } -#endif } } @@ -1852,7 +1839,6 @@ static gboolean icvOnKeyPress(GtkWidget* widget, GdkEventKey* event, gpointer us code |= event->state << 16; -#ifdef HAVE_GTHREAD if(thread_started) { g_mutex_lock(last_key_mutex); @@ -1862,7 +1848,6 @@ static gboolean icvOnKeyPress(GtkWidget* widget, GdkEventKey* event, gpointer us g_mutex_unlock(last_key_mutex); } else -#endif { last_key = code; } @@ -2053,7 +2038,6 @@ static gboolean icvAlarm( gpointer user_data ) CV_IMPL int cvWaitKey( int delay ) { -#ifdef HAVE_GTHREAD if (thread_started && g_thread_self() != window_thread) { gboolean expired = true; @@ -2087,7 +2071,6 @@ CV_IMPL int cvWaitKey( int delay ) return my_last_key; } else -#endif { int expired = 0; guint timer = 0; From d1505693ddcc2c29e71e912f3fc32d2408aeaff7 Mon Sep 17 00:00:00 2001 From: Richard Barnes Date: Mon, 15 Jul 2024 10:48:02 -0700 Subject: [PATCH 03/18] throw() -> noexcept --- modules/core/include/opencv2/core.hpp | 4 ++-- modules/core/src/system.cpp | 4 ++-- modules/videoio/src/cap_gphoto2.cpp | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/modules/core/include/opencv2/core.hpp b/modules/core/include/opencv2/core.hpp index b58a3a6ccb..0a25e2a47b 100644 --- a/modules/core/include/opencv2/core.hpp +++ b/modules/core/include/opencv2/core.hpp @@ -123,12 +123,12 @@ public: Instead, the macros CV_Error(), CV_Error_() and CV_Assert() are used. */ Exception(int _code, const String& _err, const String& _func, const String& _file, int _line); - virtual ~Exception() throw(); + virtual ~Exception() CV_NOEXCEPT; /*! \return the error description and the context as a text string. */ - virtual const char *what() const throw() CV_OVERRIDE; + virtual const char *what() const CV_NOEXCEPT CV_OVERRIDE; void formatMessage(); String msg; ///< the formatted error message diff --git a/modules/core/src/system.cpp b/modules/core/src/system.cpp index 8d72d64f87..9d5304ac5a 100644 --- a/modules/core/src/system.cpp +++ b/modules/core/src/system.cpp @@ -318,12 +318,12 @@ Exception::Exception(int _code, const String& _err, const String& _func, const S formatMessage(); } -Exception::~Exception() throw() {} +Exception::~Exception() CV_NOEXCEPT {} /*! \return the error description and the context as a text string. */ -const char* Exception::what() const throw() { return msg.c_str(); } +const char* Exception::what() const CV_NOEXCEPT { return msg.c_str(); } void Exception::formatMessage() { diff --git a/modules/videoio/src/cap_gphoto2.cpp b/modules/videoio/src/cap_gphoto2.cpp index 8b3898b2ad..d5e787f907 100644 --- a/modules/videoio/src/cap_gphoto2.cpp +++ b/modules/videoio/src/cap_gphoto2.cpp @@ -65,7 +65,7 @@ public: result = gPhoto2Result; method = methodStr; } - virtual const char * what() const throw() CV_OVERRIDE + virtual const char * what() const CV_NOEXCEPT CV_OVERRIDE { return gp_result_as_string(result); } From bcce38c05afa8aa72b9a4fcf1cf8ab1b51c90812 Mon Sep 17 00:00:00 2001 From: Yang Chao Date: Thu, 18 Jul 2024 00:20:17 +0800 Subject: [PATCH 04/18] fix: resolve Swift method name conflicts by adding missing namespace --- modules/objc/generator/gen_objc.py | 1 + 1 file changed, 1 insertion(+) diff --git a/modules/objc/generator/gen_objc.py b/modules/objc/generator/gen_objc.py index 58b7dd555c..c6f8f47be5 100755 --- a/modules/objc/generator/gen_objc.py +++ b/modules/objc/generator/gen_objc.py @@ -481,6 +481,7 @@ class FuncInfo(GeneralInfo): self.objc_name = "getelem" if self.namespace in namespaces_dict: self.objc_name = '%s_%s' % (namespaces_dict[self.namespace], self.objc_name) + self.swift_name = '%s_%s' % (namespaces_dict[self.namespace], self.swift_name) for m in decl[2]: if m.startswith("="): self.objc_name = m[1:] From 32d81a8bae785f5f73081dc5dcffa18e06f99f28 Mon Sep 17 00:00:00 2001 From: Liutong HAN Date: Thu, 18 Jul 2024 13:47:53 +0000 Subject: [PATCH 05/18] Fix toolchain. --- platforms/linux/riscv64-clang.toolchain.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platforms/linux/riscv64-clang.toolchain.cmake b/platforms/linux/riscv64-clang.toolchain.cmake index cec5f7d734..612be05eab 100644 --- a/platforms/linux/riscv64-clang.toolchain.cmake +++ b/platforms/linux/riscv64-clang.toolchain.cmake @@ -18,7 +18,7 @@ set(CMAKE_ASM_COMPILER_TARGET ${CLANG_TARGET_TRIPLE}) set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) set(CMAKE_C_FLAGS "-march=rv64gc --gcc-toolchain=${RISCV_GCC_INSTALL_ROOT} -w ${CMAKE_C_FLAGS}") -set(CMAKE_CXX_FLAGS "-march=rv64gc --gcc-toolchain=${RISCV_GCC_INSTALL_ROOT} -w ${CXX_FLAGS}") +set(CMAKE_CXX_FLAGS "-march=rv64gc --gcc-toolchain=${RISCV_GCC_INSTALL_ROOT} -w ${CMAKE_CXX_FLAGS}") set(CMAKE_FIND_ROOT_PATH ${CMAKE_SYSROOT}) set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) From 1125755345e05ad278edb75404f7652754cecb72 Mon Sep 17 00:00:00 2001 From: zihaomu Date: Thu, 18 Jul 2024 22:18:37 +0800 Subject: [PATCH 06/18] Merge pull request #25931 from zihaomu:clean_code code clean #25931 Align code and remove redundant CMake code ### Pull Request Readiness Checklist See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request - [x] I agree to contribute to the project under Apache 2 License. - [x] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV - [x] The PR is proposed to the proper branch - [ ] There is a reference to the original bug report and related work - [ ] There is accuracy test, performance test and test data in opencv_extra repository, if applicable Patch to opencv_extra has the same branch name. - [ ] The feature is well documented and sample code can be built with the project CMake --- modules/dnn/CMakeLists.txt | 2 +- modules/imgcodecs/src/rgbe.cpp | 115 ++++++++++++++++++++------------- 2 files changed, 70 insertions(+), 47 deletions(-) diff --git a/modules/dnn/CMakeLists.txt b/modules/dnn/CMakeLists.txt index 3b66b460d9..bc22696671 100644 --- a/modules/dnn/CMakeLists.txt +++ b/modules/dnn/CMakeLists.txt @@ -213,7 +213,7 @@ file(GLOB_RECURSE dnn_int_hdrs ) set(dnn_plugin_srcs ${dnn_srcs} ${dnn_int_hdrs}) ocv_list_filterout_ex(dnn_plugin_srcs - "/src/dnn.cpp$|/src/dnn_utils.cpp$|/src/dnn_utils.cpp$|/src/dnn_read.cpp$|/src/registry.cpp$|/src/backend.cpp$" + "/src/dnn.cpp$|/src/dnn_utils.cpp$|/src/dnn_read.cpp$|/src/registry.cpp$|/src/backend.cpp$" # importers "/src/(caffe|darknet|onnx|tensorflow|torch)/" # executors diff --git a/modules/imgcodecs/src/rgbe.cpp b/modules/imgcodecs/src/rgbe.cpp index cea23f6053..331fcaeaf1 100644 --- a/modules/imgcodecs/src/rgbe.cpp +++ b/modules/imgcodecs/src/rgbe.cpp @@ -191,7 +191,7 @@ int RGBE_ReadHeader(FILE *fp, int *width, int *height, rgbe_header_info *info) info->valid |= RGBE_VALID_PROGRAMTYPE; for(i=0;i(sizeof(info->programtype)-1);i++) { if ((buf[i+2] == 0) || isspace(buf[i+2])) - break; + break; info->programtype[i] = buf[i+2]; } info->programtype[i] = 0; @@ -285,34 +285,37 @@ static int RGBE_WriteBytes_RLE(FILE *fp, unsigned char *data, int numbytes) run_count = 1; while( (beg_run + run_count < numbytes) && (run_count < 127) && (data[beg_run] == data[beg_run + run_count])) - run_count++; + run_count++; } /* if data before next big run is a short run then write it as such */ if ((old_run_count > 1)&&(old_run_count == beg_run - cur)) { buf[0] = static_cast(128 + old_run_count); /*write short run*/ buf[1] = data[cur]; if (fwrite(buf,sizeof(buf[0])*2,1,fp) < 1) - return rgbe_error(rgbe_write_error,NULL); + return rgbe_error(rgbe_write_error,NULL); cur = beg_run; } /* write out bytes until we reach the start of the next run */ while(cur < beg_run) { nonrun_count = beg_run - cur; if (nonrun_count > 128) - nonrun_count = 128; + nonrun_count = 128; buf[0] = static_cast(nonrun_count); + if (fwrite(buf,sizeof(buf[0]),1,fp) < 1) - return rgbe_error(rgbe_write_error,NULL); + return rgbe_error(rgbe_write_error,NULL); + if (fwrite(&data[cur],sizeof(data[0])*nonrun_count,1,fp) < 1) - return rgbe_error(rgbe_write_error,NULL); + return rgbe_error(rgbe_write_error,NULL); cur += nonrun_count; } /* write out next run if one was found */ if (run_count >= MINRUNLENGTH) { buf[0] = static_cast(128 + run_count); buf[1] = data[beg_run]; + if (fwrite(buf,sizeof(buf[0])*2,1,fp) < 1) - return rgbe_error(rgbe_write_error,NULL); + return rgbe_error(rgbe_write_error,NULL); cur += run_count; } } @@ -330,19 +333,23 @@ int RGBE_WritePixels_RLE(FILE *fp, float *data, int scanline_width, if ((scanline_width < 8)||(scanline_width > 0x7fff)) /* run length encoding is not allowed so write flat*/ return RGBE_WritePixels(fp,data,scanline_width*num_scanlines); + buffer = (unsigned char *)malloc(sizeof(unsigned char)*4*scanline_width); if (buffer == NULL) /* no buffer space so write flat */ return RGBE_WritePixels(fp,data,scanline_width*num_scanlines); + while(num_scanlines-- > 0) { rgbe[0] = 2; rgbe[1] = 2; rgbe[2] = static_cast(scanline_width >> 8); rgbe[3] = scanline_width & 0xFF; + if (fwrite(rgbe, sizeof(rgbe), 1, fp) < 1) { free(buffer); return rgbe_error(rgbe_write_error,NULL); } + for(i=0;i 0x7fff)) /* run length encoding is not allowed so read flat*/ return RGBE_ReadPixels(fp,data,scanline_width*num_scanlines); + scanline_buffer = NULL; /* read in each successive scanline */ while(num_scanlines > 0) { @@ -383,6 +394,7 @@ int RGBE_ReadPixels_RLE(FILE *fp, float *data, int scanline_width, free(scanline_buffer); return rgbe_error(rgbe_read_error,NULL); } + if ((rgbe[0] != 2)||(rgbe[1] != 2)||(rgbe[2] & 0x80)) { /* this file is not run length encoded */ rgbe2float(&data[RGBE_DATA_RED],&data[RGBE_DATA_GREEN],&data[RGBE_DATA_BLUE],rgbe); @@ -390,13 +402,15 @@ int RGBE_ReadPixels_RLE(FILE *fp, float *data, int scanline_width, free(scanline_buffer); return RGBE_ReadPixels(fp,data,scanline_width*num_scanlines-1); } + if ((((int)rgbe[2])<<8 | rgbe[3]) != scanline_width) { free(scanline_buffer); return rgbe_error(rgbe_format_error,"wrong scanline width"); } + if (scanline_buffer == NULL) - scanline_buffer = (unsigned char *) - malloc(sizeof(unsigned char)*4*scanline_width); + scanline_buffer = (unsigned char *)malloc(sizeof(unsigned char)*4*scanline_width); + if (scanline_buffer == NULL) return rgbe_error(rgbe_memory_error,"unable to allocate buffer space"); @@ -404,47 +418,56 @@ int RGBE_ReadPixels_RLE(FILE *fp, float *data, int scanline_width, /* read each of the four channels for the scanline into the buffer */ for(i=0;i<4;i++) { ptr_end = &scanline_buffer[(i+1)*scanline_width]; - while(ptr < ptr_end) { - if (fread(buf,sizeof(buf[0])*2,1,fp) < 1) { - free(scanline_buffer); - return rgbe_error(rgbe_read_error,NULL); - } - if (buf[0] > 128) { - /* a run of the same value */ - count = buf[0]-128; - if ((count == 0)||(count > ptr_end - ptr)) { - free(scanline_buffer); - return rgbe_error(rgbe_format_error,"bad scanline data"); - } - while(count-- > 0) - *ptr++ = buf[1]; - } - else { - /* a non-run */ - count = buf[0]; - if ((count == 0)||(count > ptr_end - ptr)) { - free(scanline_buffer); - return rgbe_error(rgbe_format_error,"bad scanline data"); - } - *ptr++ = buf[1]; - if (--count > 0) { - if (fread(ptr,sizeof(*ptr)*count,1,fp) < 1) { - free(scanline_buffer); - return rgbe_error(rgbe_read_error,NULL); - } - ptr += count; - } - } + + while(ptr < ptr_end) + { + if (fread(buf,sizeof(buf[0])*2,1,fp) < 1) + { + free(scanline_buffer); + return rgbe_error(rgbe_read_error,NULL); + } + + if (buf[0] > 128) + { + /* a run of the same value */ + count = buf[0]-128; + if ((count == 0)||(count > ptr_end - ptr)) { + free(scanline_buffer); + return rgbe_error(rgbe_format_error,"bad scanline data"); + } + while(count-- > 0) + *ptr++ = buf[1]; + } + else + { + /* a non-run */ + count = buf[0]; + if ((count == 0)||(count > ptr_end - ptr)) + { + free(scanline_buffer); + return rgbe_error(rgbe_format_error,"bad scanline data"); + } + + *ptr++ = buf[1]; + if (--count > 0) { + if (fread(ptr,sizeof(*ptr)*count,1,fp) < 1) + { + free(scanline_buffer); + return rgbe_error(rgbe_read_error,NULL); + } + ptr += count; + } + } } } + /* now convert data from buffer into floats */ for(i=0;i Date: Thu, 18 Jul 2024 22:27:00 +0800 Subject: [PATCH 07/18] Merge pull request #25907 from Andy-SAKN:Andy-SAKN-add_orbbec Add tutorial on using Orbbec 3D cameras (UVC) #25907 ### Pull Request Readiness Checklist See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request - [x] I agree to contribute to the project under Apache 2 License. - [x] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV - [x] The PR is proposed to the proper branch - [ ] There is a reference to the original bug report and related work - [ ] There is accuracy test, performance test and test data in opencv_extra repository, if applicable Patch to opencv_extra has the same branch name. - [ ] The feature is well documented and sample code can be built with the project CMake --- doc/tutorials/app/images/orbbec_uvc_cpp.jpg | Bin 0 -> 32256 bytes .../app/images/orbbec_uvc_python.jpg | Bin 0 -> 16827 bytes doc/tutorials/app/intelperc.markdown | 2 +- .../app/orbbec_astra_openni.markdown | 2 +- doc/tutorials/app/orbbec_uvc.markdown | 126 ++++++++++++++++++ .../app/table_of_content_app.markdown | 1 + 6 files changed, 129 insertions(+), 2 deletions(-) create mode 100644 doc/tutorials/app/images/orbbec_uvc_cpp.jpg create mode 100644 doc/tutorials/app/images/orbbec_uvc_python.jpg create mode 100644 doc/tutorials/app/orbbec_uvc.markdown diff --git a/doc/tutorials/app/images/orbbec_uvc_cpp.jpg b/doc/tutorials/app/images/orbbec_uvc_cpp.jpg new file mode 100644 index 0000000000000000000000000000000000000000..228f919ab49426847fda28642771d10b21b86d73 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For the use of the older +Orbbec 3D cameras which depends on OpenNI, please refer to the +[previous tutorial](https://github.com/opencv/opencv/blob/4.x/doc/tutorials/app/orbbec_astra_openni.markdown). + +Unlike working with the OpenNI based Astra 3D cameras which requires OpenCV built with OpenNI2 SDK, +Orbbec SDK is not required to be installed for accessing Orbbec UVC 3D cameras via OpenCV. By using +`cv::VideoCapture` class, users get the stream data from 3D cameras, similar to working with USB +cameras. The calibration and alignment of the depth map and color image are done internally. + +### Instructions + +In order to use the 3D cameras with OpenCV. You can refer to [Get Started](https://opencv.org/get-started/) +to install OpenCV. + +Note since 4.11 on, Mac OS users need to compile OpenCV from source with flag +`-DOBSENSOR_USE_ORBBEC_SDK=ON` in order to use the cameras: +```bash +cmake -DOBSENSOR_USE_ORBBEC_SDK=ON .. +make +sudo make install +``` + +Code +---- + +@add_toggle_python +This tutorial code's is shown lines below. You can also download it from +[here](https://github.com/opencv/opencv/blob/4.x/samples/python/videocapture_obsensor.py) +@include samples/python/videocapture_obsensor.py +@end_toggle + +@add_toggle_cpp +This tutorial code's is shown lines below. You can also download it from +[here](https://github.com/opencv/opencv/blob/4.x/samples/cpp/videocapture_obsensor.cpp) +@include samples/cpp/videocapture_obsensor.cpp +@end_toggle + +### Code Explanation + +#### Python + +- **Open Orbbec Depth Sensor**: + Using `cv.VideoCapture(0, cv.CAP_OBSENSOR)` to attempt to open the first Orbbec depth sensor device. + If the camera fails to open, the program will exit and display an error message. + +- **Loop to Grab and Process Data**: + In an infinite loop, the code continuously grabs data from the camera. The `orbbec_cap.grab()` + method attempts to grab a frame. + +- **Process BGR Image**: + Using `orbbec_cap.retrieve(None, cv.CAP_OBSENSOR_BGR_IMAGE)` to retrieve the BGR image data. + If successfully retrieved, the BGR image is displayed in a window using `cv.imshow("BGR", bgr_image)`. + +- **Process Depth Image**: + Using `orbbec_cap.retrieve(None, cv.CAP_OBSENSOR_DEPTH_MAP)` to retrieve the depth image data. + If successfully retrieved, the depth image is first normalized to a range of 0 to 255, then a + false color image is applied, and the result is displayed in a window using `cv.imshow("DEPTH", color_depth_map)`. + +- **Keyboard Interrupt**: + Using `cv.pollKey()` to detect keyboard events. If a key is pressed, the loop breaks and + the program ends. + +- **Release Resources**: + After exiting the loop, the camera resources are released using `orbbec_cap.release()`. + +#### C++ + +- **Open Orbbec Depth Sensor**: + Using `VideoCapture obsensorCapture(0, CAP_OBSENSOR)` to attempt to open the first Orbbec depth + sensor device. If the camera fails to open, an error message is displayed, and the program exits. + +- **Retrieve Camera Intrinsic Parameters**: + Using `obsensorCapture.get()` to retrieve the intrinsic parameters of the camera, including focal + lengths (`fx`, `fy`) and principal points (`cx`, `cy`). + +- **Loop to Grab and Process Data**: + In an infinite loop, the code continuously grabs data from the camera. The `obsensorCapture.grab()` + method attempts to grab a frame. + +- **Process BGR Image**: + Using `obsensorCapture.retrieve(image, CAP_OBSENSOR_BGR_IMAGE)` to retrieve the BGR image data. + If successfully retrieved, the BGR image is displayed in a window using `imshow("BGR", image)`. + +- **Process Depth Image**: + Using `obsensorCapture.retrieve(depthMap, CAP_OBSENSOR_DEPTH_MAP)` to retrieve the depth image data. + If successfully retrieved, the depth image is normalized and a false color image is applied, then + the result is displayed in a window using `imshow("DEPTH", adjDepthMap)`. The retrieved depth + values are in millimeters and are truncated to a range between 300 and 5000 (millimeter). + This fixed range can be interpreted as a truncation based on the depth camera's depth range, + removing invalid pixels on the depth map. + +- **Overlay Depth Map on BGR Image**: + Convert the depth map to an 8-bit image, resize it to match the BGR image size, and overlay it + on the BGR image with a specified transparency (`alpha`). The overlaid image is displayed in + a window using `imshow("DepthToColor", image)`. + +- **Keyboard Interrupt**: + Using `pollKey()` to detect keyboard events. If a key is pressed, the loop breaks and the program ends. + +- **Release Resources**: + After exiting the loop, the camera resources are released. +### Results +#### Python + +![BGR And DEPTH frame](images/orbbec_uvc_python.jpg) + +#### C++ + +![BGR And DEPTH And DepthToColor frame](images/orbbec_uvc_cpp.jpg) + +### Note +Mac users need sudo privileges to execute the code. diff --git a/doc/tutorials/app/table_of_content_app.markdown b/doc/tutorials/app/table_of_content_app.markdown index c4dc34b23d..867f570078 100644 --- a/doc/tutorials/app/table_of_content_app.markdown +++ b/doc/tutorials/app/table_of_content_app.markdown @@ -7,5 +7,6 @@ Application utils (highgui, imgcodecs, videoio modules) {#tutorial_table_of_cont - @subpage tutorial_video_write - @subpage tutorial_kinect_openni - @subpage tutorial_orbbec_astra_openni +- @subpage tutorial_orbbec_uvc - @subpage tutorial_intelperc - @subpage tutorial_wayland_ubuntu From a5dacb5bed3008bf9e7bb820f08693fcdfaea852 Mon Sep 17 00:00:00 2001 From: eplankin Date: Thu, 18 Jul 2024 08:16:19 -0700 Subject: [PATCH 08/18] Update IPP integration --- 3rdparty/ippicv/ippicv.cmake | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/3rdparty/ippicv/ippicv.cmake b/3rdparty/ippicv/ippicv.cmake index 744c45882e..7644bbba45 100644 --- a/3rdparty/ippicv/ippicv.cmake +++ b/3rdparty/ippicv/ippicv.cmake @@ -2,7 +2,7 @@ function(download_ippicv root_var) set(${root_var} "" PARENT_SCOPE) # Commit SHA in the opencv_3rdparty repo - set(IPPICV_COMMIT "fd27188235d85e552de31425e7ea0f53ba73ba53") + set(IPPICV_COMMIT "7f55c0c26be418d494615afca15218566775c725") # Define actual ICV versions if(APPLE) set(IPPICV_COMMIT "0cc4aa06bf2bef4b05d237c69a5a96b9cd0cb85a") @@ -14,21 +14,21 @@ function(download_ippicv root_var) set(OPENCV_ICV_PLATFORM "linux") set(OPENCV_ICV_PACKAGE_SUBDIR "ippicv_lnx") if(X86_64) - set(OPENCV_ICV_NAME "ippicv_2021.11.0_lnx_intel64_20240201_general.tgz") - set(OPENCV_ICV_HASH "0f2745ff705ecae31176dad437608f6f") + set(OPENCV_ICV_NAME "ippicv_2021.12.0_lnx_intel64_20240425_general.tgz") + set(OPENCV_ICV_HASH "d06e6d44ece88f7f17a6cd9216761186") else() - set(OPENCV_ICV_NAME "ippicv_2021.11.0_lnx_ia32_20240201_general.tgz") - set(OPENCV_ICV_HASH "63e381bf08076ca34fd5264203043a45") + set(OPENCV_ICV_NAME "ippicv_2021.12.0_lnx_ia32_20240425_general.tgz") + set(OPENCV_ICV_HASH "85ffa2b9ed7802b93c23fa27b0097d36") endif() elseif(WIN32 AND NOT ARM) set(OPENCV_ICV_PLATFORM "windows") set(OPENCV_ICV_PACKAGE_SUBDIR "ippicv_win") if(X86_64) - set(OPENCV_ICV_NAME "ippicv_2021.11.0_win_intel64_20240201_general.zip") - set(OPENCV_ICV_HASH "59d154bf54a1e3eea20d7248f81a2a8e") + set(OPENCV_ICV_NAME "ippicv_2021.12.0_win_intel64_20240425_general.zip") + set(OPENCV_ICV_HASH "402ff8c6b4986738fed71c44e1ce665d") else() - set(OPENCV_ICV_NAME "ippicv_2021.11.0_win_ia32_20240201_general.zip") - set(OPENCV_ICV_HASH "7a6d8ac5825c02fea6cbfc1201b521b5") + set(OPENCV_ICV_NAME "ippicv_2021.12.0_win_ia32_20240425_general.zip") + set(OPENCV_ICV_HASH "8b1d2a23957d57624d0de8f2a5cae5f1") endif() else() return() From 4dd54bbec92ae399d98b41dcf7a167b2c6aa4c51 Mon Sep 17 00:00:00 2001 From: _Ayaka <33724737+Octopus136@users.noreply.github.com> Date: Fri, 19 Jul 2024 14:08:19 +0800 Subject: [PATCH 09/18] Merge pull request #25898 from Octopus136:issue-25853 Add a check for src == dst in ocl warpTransform #25898 As mentioned in #25853, when doing WarpAffine with Mat and UMat respectively, if you force the use of the in-place operation (so that src and dst are passed the same variables), Mat produces the correct results, but UMat produces unexpected results. Obviously in-place operations are not possible with this transformation. When Mat performs the operation, if dst and src are the same variable, the function inherently makes a copy of src without telling the user. https://github.com/opencv/opencv/blob/74b50c7af05c91194469a1f059f971dff00ef889/modules/imgproc/src/imgwarp.cpp#L2831-L2834 So I did the same check in UMat, but I'm not sure if it's appropriate, should we just do a copy operation without telling the user (even if the user thinks he's doing an in-place operation), or should we throw an exception to indicate that we shouldn't pass in two same variables here? The possible reason for this problem is that there is a create function here, so it gives the developer the false impression that this create function has allocated new memory for dst, however it does not. https://github.com/opencv/opencv/blob/74b50c7af05c91194469a1f059f971dff00ef889/modules/imgproc/src/imgwarp.cpp#L2607-L2609 Because by the time the check is done here, the function has returned back. https://github.com/opencv/opencv/blob/74b50c7af05c91194469a1f059f971dff00ef889/modules/core/src/umatrix.cpp#L668-L675 ### Pull Request Readiness Checklist See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request - [x] I agree to contribute to the project under Apache 2 License. - [x] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV - [x] The PR is proposed to the proper branch - [x] There is a reference to the original bug report and related work - [x] There is accuracy test, performance test and test data in opencv_extra repository, if applicable Patch to opencv_extra has the same branch name. - [x] The feature is well documented and sample code can be built with the project CMake --- modules/imgproc/src/imgwarp.cpp | 6 ++++++ modules/imgproc/test/ocl/test_warp.cpp | 20 ++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/modules/imgproc/src/imgwarp.cpp b/modules/imgproc/src/imgwarp.cpp index d7c9c64c3c..c0eaf8114c 100644 --- a/modules/imgproc/src/imgwarp.cpp +++ b/modules/imgproc/src/imgwarp.cpp @@ -2501,6 +2501,9 @@ static bool ocl_warpTransform_cols4(InputArray _src, OutputArray _dst, InputArra _dst.create( dsize.empty() ? src.size() : dsize, src.type() ); UMat dst = _dst.getUMat(); + if (src.u == dst.u) + src = src.clone(); + float M[9] = {0}; int matRows = (op_type == OCL_OP_AFFINE ? 2 : 3); Mat matM(matRows, 3, CV_32F, M), M1 = _M0.getMat(); @@ -2605,6 +2608,9 @@ static bool ocl_warpTransform(InputArray _src, OutputArray _dst, InputArray _M0, _dst.create( dsize.empty() ? src.size() : dsize, src.type() ); UMat dst = _dst.getUMat(); + if (src.u == dst.u) + src = src.clone(); + double M[9] = {0}; int matRows = (op_type == OCL_OP_AFFINE ? 2 : 3); Mat matM(matRows, 3, CV_64F, M), M1 = _M0.getMat(); diff --git a/modules/imgproc/test/ocl/test_warp.cpp b/modules/imgproc/test/ocl/test_warp.cpp index 852dc465ab..73d93bb41f 100644 --- a/modules/imgproc/test/ocl/test_warp.cpp +++ b/modules/imgproc/test/ocl/test_warp.cpp @@ -185,6 +185,26 @@ OCL_TEST_P(WarpAffine, Mat) } } +OCL_TEST_P(WarpAffine, inplace_25853) // when src and dst are the same variable, ocl on/off should produce consistent and correct results +{ + for (int j = 0; j < test_loop_times; j++) + { + double eps = depth < CV_32F ? 0.04 : 0.06; + random_roi(); + + Mat M = getRotationMatrix2D(Point2f(src_roi.cols / 2.0f, src_roi.rows / 2.0f), + rng.uniform(-180.f, 180.f), rng.uniform(0.4f, 2.0f)); + + OCL_OFF(cv::warpAffine(src_roi, src_roi, M, dsize, interpolation)); + OCL_ON(cv::warpAffine(usrc_roi, usrc_roi, M, dsize, interpolation)); + + dst_roi = src_roi.clone(); + udst_roi = usrc_roi.clone(); + + Near(eps); + } +} + typedef WarpTest_cols4_Base WarpAffine_cols4; OCL_TEST_P(WarpAffine_cols4, Mat) From b5ea32158a5fabae3dd8b23e896eb9e623c13ed8 Mon Sep 17 00:00:00 2001 From: HAN Liutong Date: Fri, 19 Jul 2024 16:41:42 +0800 Subject: [PATCH 10/18] Merge pull request #25883 from hanliutong:rvv-intrin-upgrade Upgrade RISC-V Vector intrinsic and cleanup the obsolete RVV backend. #25883 This patch upgrade RISC-V Vector intrinsic from `v0.10` to `v0.12`/`v1.0`: - Update cmake check and options; - Upgrade RVV implement for Universal Intrinsic; - Upgrade RVV optimized DNN kernel. - Cleanup the obsolete RVV backend (`intrin_rvv.hpp`) and compatable header file. With this patch, RVV backend require Clang 17+ or GCC 14+ (which means `__riscv_v_intrinsic >= 12000`, see https://godbolt.org/z/es7ncETE3) This patch is test with Clang 17.0.6 (require extra `-DWITH_PNG=OFF` due to ICE), Clang 18.1.8 and GCC 14.1.0 on QEMU and k230 (with `--gtest_filter="*hal_*"`). ### Pull Request Readiness Checklist See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request - [x] I agree to contribute to the project under Apache 2 License. - [x] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV - [ ] The PR is proposed to the proper branch - [ ] There is a reference to the original bug report and related work - [ ] There is accuracy test, performance test and test data in opencv_extra repository, if applicable Patch to opencv_extra has the same branch name. - [ ] The feature is well documented and sample code can be built with the project CMake --- cmake/OpenCVCompilerOptimizations.cmake | 5 - cmake/checks/cpu_rvv.cpp | 26 +- .../include/opencv2/core/cv_cpu_dispatch.h | 25 +- .../core/include/opencv2/core/hal/intrin.hpp | 4 - .../include/opencv2/core/hal/intrin_rvv.hpp | 3345 --- .../hal/intrin_rvv_010_compat_non-policy.hpp | 24395 ---------------- ...n_rvv_010_compat_overloaded-non-policy.hpp | 768 - .../core/hal/intrin_rvv_011_compat.hpp | 33 - .../core/hal/intrin_rvv_compat_overloaded.hpp | 213 - .../opencv2/core/hal/intrin_rvv_scalable.hpp | 1219 +- .../src/int8layers/fully_connected_layer.cpp | 4 +- .../dnn/src/int8layers/layers_common.simd.hpp | 2 +- modules/dnn/src/layers/convolution_layer.cpp | 2 +- .../src/layers/cpu_kernels/conv_depthwise.cpp | 2 +- .../cpu_kernels/conv_depthwise.simd.hpp | 54 +- .../dnn/src/layers/fully_connected_layer.cpp | 2 +- modules/dnn/src/layers/layers_common.simd.hpp | 208 +- 17 files changed, 783 insertions(+), 29524 deletions(-) delete mode 100644 modules/core/include/opencv2/core/hal/intrin_rvv.hpp delete mode 100644 modules/core/include/opencv2/core/hal/intrin_rvv_010_compat_non-policy.hpp delete mode 100644 modules/core/include/opencv2/core/hal/intrin_rvv_010_compat_overloaded-non-policy.hpp delete mode 100644 modules/core/include/opencv2/core/hal/intrin_rvv_011_compat.hpp delete mode 100644 modules/core/include/opencv2/core/hal/intrin_rvv_compat_overloaded.hpp diff --git a/cmake/OpenCVCompilerOptimizations.cmake b/cmake/OpenCVCompilerOptimizations.cmake index ff0e40c666..e8e1e11f4e 100644 --- a/cmake/OpenCVCompilerOptimizations.cmake +++ b/cmake/OpenCVCompilerOptimizations.cmake @@ -390,14 +390,9 @@ elseif(PPC64LE) set(CPU_BASELINE "VSX" CACHE STRING "${HELP_CPU_BASELINE}") elseif(RISCV) - option(RISCV_RVV_SCALABLE "Use scalable RVV API on RISC-V" ON) - ocv_update(CPU_RVV_TEST_FILE "${OpenCV_SOURCE_DIR}/cmake/checks/cpu_rvv.cpp") ocv_update(CPU_KNOWN_OPTIMIZATIONS "RVV") ocv_update(CPU_RVV_FLAGS_ON "-march=rv64gcv") - if(RISCV_RVV_SCALABLE) - set(CPU_RVV_FLAGS_ON "${CPU_RVV_FLAGS_ON} -DCV_RVV_SCALABLE") - endif() ocv_update(CPU_RVV_FLAGS_CONFLICT "-march=[^ ]*") set(CPU_DISPATCH "" CACHE STRING "${HELP_CPU_DISPATCH}") diff --git a/cmake/checks/cpu_rvv.cpp b/cmake/checks/cpu_rvv.cpp index fb62165167..187f39866a 100644 --- a/cmake/checks/cpu_rvv.cpp +++ b/cmake/checks/cpu_rvv.cpp @@ -1,17 +1,16 @@ #include -#if defined(__riscv) -# include -# define CV_RVV 1 +#if !defined(__riscv) || !defined(__riscv_v) +#error "RISC-V or vector extension(RVV) is not supported by the compiler" #endif -#if defined CV_RVV -#if defined(__riscv_v_intrinsic) && __riscv_v_intrinsic>10999 -#define vreinterpret_v_u64m1_u8m1 __riscv_vreinterpret_v_u64m1_u8m1 -#define vle64_v_u64m1 __riscv_vle64_v_u64m1 -#define vle32_v_f32m1 __riscv_vle32_v_f32m1 -#define vfmv_f_s_f32m1_f32 __riscv_vfmv_f_s_f32m1_f32 +#if !defined(__THEAD_VERSION__) && defined(__riscv_v_intrinsic) && __riscv_v_intrinsic < 12000 +#error "Wrong intrinsics version, v0.12 or higher is required for gcc or clang" #endif + +#include + +#ifdef __THEAD_VERSION__ int test() { const float src[] = { 0.0f, 0.0f, 0.0f, 0.0f }; @@ -21,7 +20,14 @@ int test() return (int)vfmv_f_s_f32m1_f32(val); } #else -#error "RISC-V vector extension(RVV) is not supported" +int test() +{ + const float src[] = { 0.0f, 0.0f, 0.0f, 0.0f }; + uint64_t ptr[2] = {0x0908060504020100, 0xFFFFFFFF0E0D0C0A}; + vuint8m1_t a = __riscv_vreinterpret_v_u64m1_u8m1(__riscv_vle64_v_u64m1(ptr, 2)); + vfloat32m1_t val = __riscv_vle32_v_f32m1((const float*)(src), 4); + return (int)__riscv_vfmv_f_s_f32m1_f32(val); +} #endif int main() diff --git a/modules/core/include/opencv2/core/cv_cpu_dispatch.h b/modules/core/include/opencv2/core/cv_cpu_dispatch.h index 0817e7ec70..607f286615 100644 --- a/modules/core/include/opencv2/core/cv_cpu_dispatch.h +++ b/modules/core/include/opencv2/core/cv_cpu_dispatch.h @@ -146,9 +146,23 @@ # define CV_NEON 1 #endif -#if defined(__riscv) && defined(__riscv_vector) && defined(__riscv_vector_071) -# include -# define CV_RVV071 1 +/* RVV-related macro states with different compiler +// +--------------------+----------+----------+ +// | Macro | Upstream | XuanTie | +// +--------------------+----------+----------+ +// | CV_CPU_COMPILE_RVV | defined | defined | +// | CV_RVV | 1 | 0 | +// | CV_RVV071 | 0 | 1 | +// | CV_TRY_RVV | 1 | 1 | +// +--------------------+----------+----------+ +*/ +#ifdef CV_CPU_COMPILE_RVV +# ifdef __riscv_vector_071 +# define CV_RVV071 1 +# else +# define CV_RVV 1 +# endif +#include #endif #ifdef CV_CPU_COMPILE_VSX @@ -183,11 +197,6 @@ # include #endif -#if defined CV_CPU_COMPILE_RVV -# define CV_RVV 1 -# include -#endif - #endif // CV_ENABLE_INTRINSICS && !CV_DISABLE_OPTIMIZATION && !__CUDACC__ #if defined CV_CPU_COMPILE_AVX && !defined CV_CPU_BASELINE_COMPILE_AVX diff --git a/modules/core/include/opencv2/core/hal/intrin.hpp b/modules/core/include/opencv2/core/hal/intrin.hpp index a57eb5e799..c9407a1d43 100644 --- a/modules/core/include/opencv2/core/hal/intrin.hpp +++ b/modules/core/include/opencv2/core/hal/intrin.hpp @@ -236,11 +236,7 @@ using namespace CV_CPU_OPTIMIZATION_HAL_NAMESPACE; #include "opencv2/core/hal/intrin_wasm.hpp" #elif CV_RVV && !defined(CV_FORCE_SIMD128_CPP) -#if defined(CV_RVV_SCALABLE) #include "opencv2/core/hal/intrin_rvv_scalable.hpp" -#else -#include "opencv2/core/hal/intrin_rvv.hpp" -#endif #elif CV_LSX && !defined(CV_FORCE_SIMD128_CPP) diff --git a/modules/core/include/opencv2/core/hal/intrin_rvv.hpp b/modules/core/include/opencv2/core/hal/intrin_rvv.hpp deleted file mode 100644 index d446a05db5..0000000000 --- a/modules/core/include/opencv2/core/hal/intrin_rvv.hpp +++ /dev/null @@ -1,3345 +0,0 @@ -// This file is part of OpenCV project. -// It is subject to the license terms in the LICENSE file found in the top-level directory -// of this distribution and at http://opencv.org/license.html. - -// The original implementation has been contributed by Yin Zhang. -// Copyright (C) 2020, Institute of Software, Chinese Academy of Sciences. - -#ifndef OPENCV_HAL_INTRIN_RVV_HPP -#define OPENCV_HAL_INTRIN_RVV_HPP - -#include - -// RVV intrinsics have been renamed in version 0.11, so we need to include -// compatibility headers: -// https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/master/auto-generated/rvv-v0p10-compatible-headers -#if defined(__riscv_v_intrinsic) && __riscv_v_intrinsic>10999 -#include "intrin_rvv_010_compat_non-policy.hpp" -#include "intrin_rvv_010_compat_overloaded-non-policy.hpp" -#endif - - -// Building for T-Head C906 core with RVV 0.7.1 using toolchain -// https://github.com/T-head-Semi/xuantie-gnu-toolchain -// with option '-march=rv64gcv0p7' -#ifdef __THEAD_VERSION__ -# if __riscv_v == 7000 -# include -# define CV_RVV_THEAD_0_7 -# endif -#endif - -namespace cv -{ - -//! @cond IGNORED - -CV_CPU_OPTIMIZATION_HAL_NAMESPACE_BEGIN - -#define CV_SIMD128 1 -#ifndef CV_RVV_THEAD_0_7 -# define CV_SIMD128_64F 1 -#else -# define CV_SIMD128_64F 0 -#endif - -//////////// Unsupported native intrinsics in C++ //////////// -// The following types have been defined in clang, but not in GCC yet. -#ifndef __clang__ - -struct vuint8mf2_t -{ - uchar val[8] = {0}; - vuint8mf2_t() {} - vuint8mf2_t(const uchar* ptr) - { - for (int i = 0; i < 8; ++i) - { - val[i] = ptr[i]; - } - } -}; -struct vint8mf2_t -{ - schar val[8] = {0}; - vint8mf2_t() {} - vint8mf2_t(const schar* ptr) - { - for (int i = 0; i < 8; ++i) - { - val[i] = ptr[i]; - } - } -}; -struct vuint16mf2_t -{ - ushort val[4] = {0}; - vuint16mf2_t() {} - vuint16mf2_t(const ushort* ptr) - { - for (int i = 0; i < 4; ++i) - { - val[i] = ptr[i]; - } - } -}; -struct vint16mf2_t -{ - short val[4] = {0}; - vint16mf2_t() {} - vint16mf2_t(const short* ptr) - { - for (int i = 0; i < 4; ++i) - { - val[i] = ptr[i]; - } - } -}; -struct vuint32mf2_t -{ - unsigned val[2] = {0}; - vuint32mf2_t() {} - vuint32mf2_t(const unsigned* ptr) - { - val[0] = ptr[0]; - val[1] = ptr[1]; - } -}; -struct vint32mf2_t -{ - int val[2] = {0}; - vint32mf2_t() {} - vint32mf2_t(const int* ptr) - { - val[0] = ptr[0]; - val[1] = ptr[1]; - } -}; -struct vfloat32mf2_t -{ - float val[2] = {0}; - vfloat32mf2_t() {} - vfloat32mf2_t(const float* ptr) - { - val[0] = ptr[0]; - val[1] = ptr[1]; - } -}; -struct vuint64mf2_t -{ - uint64 val[1] = {0}; - vuint64mf2_t() {} - vuint64mf2_t(const uint64* ptr) - { - val[0] = ptr[0]; - } -}; -struct vint64mf2_t -{ - int64 val[1] = {0}; - vint64mf2_t() {} - vint64mf2_t(const int64* ptr) - { - val[0] = ptr[0]; - } -}; -struct vfloat64mf2_t -{ - double val[1] = {0}; - vfloat64mf2_t() {} - vfloat64mf2_t(const double* ptr) - { - val[0] = ptr[0]; - } -}; -struct vuint8mf4_t -{ - uchar val[4] = {0}; - vuint8mf4_t() {} - vuint8mf4_t(const uchar* ptr) - { - for (int i = 0; i < 4; ++i) - { - val[i] = ptr[i]; - } - } -}; -struct vint8mf4_t -{ - schar val[4] = {0}; - vint8mf4_t() {} - vint8mf4_t(const schar* ptr) - { - for (int i = 0; i < 4; ++i) - { - val[i] = ptr[i]; - } - } -}; - -#define OPENCV_HAL_IMPL_RVV_NATIVE_LOADSTORE_MF2(_Tpvec, _Tp, suffix, width, n) \ -inline _Tpvec vle##width##_v_##suffix##mf2(const _Tp* ptr, size_t vl) \ -{ \ - CV_UNUSED(vl); \ - return _Tpvec(ptr); \ -} \ -inline void vse##width##_v_##suffix##mf2(_Tp* ptr, _Tpvec v, size_t vl) \ -{ \ - CV_UNUSED(vl); \ - for (int i = 0; i < n; ++i) \ - { \ - ptr[i] = v.val[i]; \ - } \ -} - -OPENCV_HAL_IMPL_RVV_NATIVE_LOADSTORE_MF2(vuint8mf2_t, uint8_t, u8, 8, 8) -OPENCV_HAL_IMPL_RVV_NATIVE_LOADSTORE_MF2(vint8mf2_t, int8_t, i8, 8, 8) -OPENCV_HAL_IMPL_RVV_NATIVE_LOADSTORE_MF2(vuint16mf2_t, uint16_t, u16, 16, 4) -OPENCV_HAL_IMPL_RVV_NATIVE_LOADSTORE_MF2(vint16mf2_t, int16_t, i16, 16, 4) -OPENCV_HAL_IMPL_RVV_NATIVE_LOADSTORE_MF2(vuint32mf2_t, uint32_t, u32, 32, 2) -OPENCV_HAL_IMPL_RVV_NATIVE_LOADSTORE_MF2(vint32mf2_t, int32_t, i32, 32, 2) -OPENCV_HAL_IMPL_RVV_NATIVE_LOADSTORE_MF2(vfloat32mf2_t, float32_t, f32, 32, 2) -OPENCV_HAL_IMPL_RVV_NATIVE_LOADSTORE_MF2(vuint64mf2_t, uint64_t, u64, 64, 1) -OPENCV_HAL_IMPL_RVV_NATIVE_LOADSTORE_MF2(vint64mf2_t, int64_t, i64, 64, 1) -OPENCV_HAL_IMPL_RVV_NATIVE_LOADSTORE_MF2(vfloat64mf2_t, float64_t, f64, 64, 1) - - -#define OPENCV_HAL_IMPL_RVV_NATIVE_WCVT(_Tpwvec, _Tpvec, _wTp, wcvt, suffix, width, n) \ -inline _Tpwvec wcvt (_Tpvec v, size_t vl) \ -{ \ - _wTp tmp[n]; \ - for (int i = 0; i < n; ++i) \ - { \ - tmp[i] = (_wTp)v.val[i]; \ - } \ - return vle##width##_v_##suffix##m1(tmp, vl); \ -} - -OPENCV_HAL_IMPL_RVV_NATIVE_WCVT(vuint16m1_t, vuint8mf2_t, ushort, vwcvtu_x_x_v_u16m1, u16, 16, 8) -OPENCV_HAL_IMPL_RVV_NATIVE_WCVT(vint16m1_t, vint8mf2_t, short, vwcvt_x_x_v_i16m1, i16, 16, 8) -OPENCV_HAL_IMPL_RVV_NATIVE_WCVT(vuint32m1_t, vuint16mf2_t, unsigned, vwcvtu_x_x_v_u32m1, u32, 32, 4) -OPENCV_HAL_IMPL_RVV_NATIVE_WCVT(vint32m1_t, vint16mf2_t, int, vwcvt_x_x_v_i32m1, i32, 32, 4) -OPENCV_HAL_IMPL_RVV_NATIVE_WCVT(vuint64m1_t, vuint32mf2_t, uint64, vwcvtu_x_x_v_u64m1, u64, 64, 2) -OPENCV_HAL_IMPL_RVV_NATIVE_WCVT(vint64m1_t, vint32mf2_t, int64, vwcvt_x_x_v_i64m1, i64, 64, 2) - -inline vuint8mf4_t vle8_v_u8mf4 (const uint8_t *base, size_t vl) -{ - CV_UNUSED(vl); - return vuint8mf4_t(base); -} -inline vint8mf4_t vle8_v_i8mf4 (const int8_t *base, size_t vl) -{ - CV_UNUSED(vl); - return vint8mf4_t(base); -} - -inline vuint16mf2_t vwcvtu_x_x_v_u16mf2 (vuint8mf4_t src, size_t vl) -{ - ushort tmp[4]; - for (int i = 0; i < 4; ++i) - { - tmp[i] = (ushort)src.val[i]; - } - return vle16_v_u16mf2(tmp, vl); -} -inline vint16mf2_t vwcvt_x_x_v_i16mf2 (vint8mf4_t src, size_t vl) -{ - short tmp[4]; - for (int i = 0; i < 4; ++i) - { - tmp[i] = (short)src.val[i]; - } - return vle16_v_i16mf2(tmp, vl); -} -#endif - -//////////// Types //////////// - -#ifndef __clang__ -struct v_uint8x16 -{ - typedef uchar lane_type; - enum { nlanes = 16 }; - - v_uint8x16() {} - explicit v_uint8x16(vuint8m1_t v) - { - vse8_v_u8m1(val, v, nlanes); - } - v_uint8x16(uchar v0, uchar v1, uchar v2, uchar v3, uchar v4, uchar v5, uchar v6, uchar v7, - uchar v8, uchar v9, uchar v10, uchar v11, uchar v12, uchar v13, uchar v14, uchar v15) - { - uchar v[] = {v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15}; - for (int i = 0; i < nlanes; ++i) - { - val[i] = v[i]; - } - } - operator vuint8m1_t() const - { - return vle8_v_u8m1(val, nlanes); - } - uchar get0() const - { - return val[0]; - } - - uchar val[16]; -}; - -struct v_int8x16 -{ - typedef schar lane_type; - enum { nlanes = 16 }; - - v_int8x16() {} - explicit v_int8x16(vint8m1_t v) - { - vse8_v_i8m1(val, v, nlanes); - } - v_int8x16(schar v0, schar v1, schar v2, schar v3, schar v4, schar v5, schar v6, schar v7, - schar v8, schar v9, schar v10, schar v11, schar v12, schar v13, schar v14, schar v15) - { - schar v[] = {v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15}; - for (int i = 0; i < nlanes; ++i) - { - val[i] = v[i]; - } - } - operator vint8m1_t() const - { - return vle8_v_i8m1(val, nlanes); - } - schar get0() const - { - return val[0]; - } - - schar val[16]; -}; - -struct v_uint16x8 -{ - typedef ushort lane_type; - enum { nlanes = 8 }; - - v_uint16x8() {} - explicit v_uint16x8(vuint16m1_t v) - { - vse16_v_u16m1(val, v, nlanes); - } - v_uint16x8(ushort v0, ushort v1, ushort v2, ushort v3, ushort v4, ushort v5, ushort v6, ushort v7) - { - ushort v[] = {v0, v1, v2, v3, v4, v5, v6, v7}; - for (int i = 0; i < nlanes; ++i) - { - val[i] = v[i]; - } - } - operator vuint16m1_t() const - { - return vle16_v_u16m1(val, nlanes); - } - ushort get0() const - { - return val[0]; - } - - ushort val[8]; -}; - -struct v_int16x8 -{ - typedef short lane_type; - enum { nlanes = 8 }; - - v_int16x8() {} - explicit v_int16x8(vint16m1_t v) - { - vse16_v_i16m1(val, v, nlanes); - } - v_int16x8(short v0, short v1, short v2, short v3, short v4, short v5, short v6, short v7) - { - short v[] = {v0, v1, v2, v3, v4, v5, v6, v7}; - for (int i = 0; i < nlanes; ++i) - { - val[i] = v[i]; - } - } - operator vint16m1_t() const - { - return vle16_v_i16m1(val, nlanes); - } - short get0() const - { - return val[0]; - } - - short val[8]; -}; - -struct v_uint32x4 -{ - typedef unsigned lane_type; - enum { nlanes = 4 }; - - v_uint32x4() {} - explicit v_uint32x4(vuint32m1_t v) - { - vse32_v_u32m1(val, v, nlanes); - } - v_uint32x4(unsigned v0, unsigned v1, unsigned v2, unsigned v3) - { - unsigned v[] = {v0, v1, v2, v3}; - for (int i = 0; i < nlanes; ++i) - { - val[i] = v[i]; - } - } - operator vuint32m1_t() const - { - return vle32_v_u32m1(val, nlanes); - } - unsigned get0() const - { - return val[0]; - } - - unsigned val[4]; -}; - -struct v_int32x4 -{ - typedef int lane_type; - enum { nlanes = 4 }; - - v_int32x4() {} - explicit v_int32x4(vint32m1_t v) - { - vse32_v_i32m1(val, v, nlanes); - } - v_int32x4(int v0, int v1, int v2, int v3) - { - int v[] = {v0, v1, v2, v3}; - for (int i = 0; i < nlanes; ++i) - { - val[i] = v[i]; - } - } - operator vint32m1_t() const - { - return vle32_v_i32m1(val, nlanes); - } - int get0() const - { - return val[0]; - } - int val[4]; -}; - -struct v_float32x4 -{ - typedef float lane_type; - enum { nlanes = 4 }; - - v_float32x4() {} - explicit v_float32x4(vfloat32m1_t v) - { - vse32_v_f32m1(val, v, nlanes); - } - v_float32x4(float v0, float v1, float v2, float v3) - { - float v[] = {v0, v1, v2, v3}; - for (int i = 0; i < nlanes; ++i) - { - val[i] = v[i]; - } - } - operator vfloat32m1_t() const - { - return vle32_v_f32m1(val, nlanes); - } - float get0() const - { - return val[0]; - } - float val[4]; -}; - -struct v_uint64x2 -{ - typedef uint64 lane_type; - enum { nlanes = 2 }; - - v_uint64x2() {} - explicit v_uint64x2(vuint64m1_t v) - { - vse64_v_u64m1(val, v, nlanes); - } - v_uint64x2(uint64 v0, uint64 v1) - { - uint64 v[] = {v0, v1}; - for (int i = 0; i < nlanes; ++i) - { - val[i] = v[i]; - } - } - operator vuint64m1_t() const - { - return vle64_v_u64m1(val, nlanes); - } - uint64 get0() const - { - return val[0]; - } - - uint64 val[2]; -}; - -struct v_int64x2 -{ - typedef int64 lane_type; - enum { nlanes = 2 }; - - v_int64x2() {} - explicit v_int64x2(vint64m1_t v) - { - vse64_v_i64m1(val, v, nlanes); - } - v_int64x2(int64 v0, int64 v1) - { - int64 v[] = {v0, v1}; - for (int i = 0; i < nlanes; ++i) - { - val[i] = v[i]; - } - } - operator vint64m1_t() const - { - return vle64_v_i64m1(val, nlanes); - } - int64 get0() const - { - return val[0]; - } - - int64 val[2]; -}; - -#if CV_SIMD128_64F -struct v_float64x2 -{ - typedef double lane_type; - enum { nlanes = 2 }; - - v_float64x2() {} - explicit v_float64x2(vfloat64m1_t v) - { - vse64_v_f64m1(val, v, nlanes); - } - v_float64x2(double v0, double v1) - { - double v[] = {v0, v1}; - for (int i = 0; i < nlanes; ++i) - { - val[i] = v[i]; - } - } - operator vfloat64m1_t() const - { - return vle64_v_f64m1(val, nlanes); - } - double get0() const - { - return val[0]; - } - - double val[2]; -}; -#endif -#else -struct v_uint8x16 -{ - typedef uchar lane_type; - enum { nlanes = 16 }; - - v_uint8x16() {} - explicit v_uint8x16(vuint8m1_t v) - { - *pval = v; - } - v_uint8x16(uchar v0, uchar v1, uchar v2, uchar v3, uchar v4, uchar v5, uchar v6, uchar v7, - uchar v8, uchar v9, uchar v10, uchar v11, uchar v12, uchar v13, uchar v14, uchar v15) - { - uchar v[] = {v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15}; - *pval = vle8_v_u8m1(v, nlanes); - } - operator vuint8m1_t() const - { - return *pval; - } - uchar get0() const - { - return vmv_x(*pval); - } - inline v_uint8x16& operator=(const v_uint8x16& vec) { - *pval = *(vec.pval); - return *this; - } - inline v_uint8x16(const v_uint8x16& vec) { - *pval = *(vec.pval); - } - uchar val[16]; - vuint8m1_t* pval = (vuint8m1_t*)val; -}; - -struct v_int8x16 -{ - typedef schar lane_type; - enum { nlanes = 16 }; - - v_int8x16() {} - explicit v_int8x16(vint8m1_t v) - { - *pval = v; - } - v_int8x16(schar v0, schar v1, schar v2, schar v3, schar v4, schar v5, schar v6, schar v7, - schar v8, schar v9, schar v10, schar v11, schar v12, schar v13, schar v14, schar v15) - { - schar v[] = {v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15}; - *pval = vle8_v_i8m1(v, nlanes); - } - operator vint8m1_t() const - { - return *pval; - } - schar get0() const - { - return vmv_x(*pval); - } - inline v_int8x16& operator=(const v_int8x16& vec) { - *pval = *(vec.pval); - return *this; - } - inline v_int8x16(const v_int8x16& vec) { - *pval = *(vec.pval); - } - schar val[16]; - vint8m1_t* pval = (vint8m1_t*)val; -}; - -struct v_uint16x8 -{ - typedef ushort lane_type; - enum { nlanes = 8 }; - - v_uint16x8() {} - explicit v_uint16x8(vuint16m1_t v) - { - *pval = v; - } - v_uint16x8(ushort v0, ushort v1, ushort v2, ushort v3, ushort v4, ushort v5, ushort v6, ushort v7) - { - ushort v[] = {v0, v1, v2, v3, v4, v5, v6, v7}; - *pval = vle16_v_u16m1(v, nlanes); - } - operator vuint16m1_t() const - { - return *pval; - } - ushort get0() const - { - return vmv_x(*pval); - } - - inline v_uint16x8& operator=(const v_uint16x8& vec) { - *pval = *(vec.pval); - return *this; - } - inline v_uint16x8(const v_uint16x8& vec) { - *pval = *(vec.pval); - } - ushort val[8]; - vuint16m1_t* pval = (vuint16m1_t*)val; -}; - -struct v_int16x8 -{ - typedef short lane_type; - enum { nlanes = 8 }; - - v_int16x8() {} - explicit v_int16x8(vint16m1_t v) - { - *pval = v; - } - v_int16x8(short v0, short v1, short v2, short v3, short v4, short v5, short v6, short v7) - { - short v[] = {v0, v1, v2, v3, v4, v5, v6, v7}; - *pval = vle16_v_i16m1(v, nlanes); - } - operator vint16m1_t() const - { - return *pval; - } - short get0() const - { - return vmv_x(*pval); - } - - inline v_int16x8& operator=(const v_int16x8& vec) { - *pval = *(vec.pval); - return *this; - } - inline v_int16x8(const v_int16x8& vec) { - *pval = *(vec.pval); - } - short val[8]; - vint16m1_t* pval = (vint16m1_t*)val; -}; - -struct v_uint32x4 -{ - typedef unsigned lane_type; - enum { nlanes = 4 }; - - v_uint32x4() {} - explicit v_uint32x4(vuint32m1_t v) - { - *pval = v; - } - v_uint32x4(unsigned v0, unsigned v1, unsigned v2, unsigned v3) - { - unsigned v[] = {v0, v1, v2, v3}; - *pval = vle32_v_u32m1(v, nlanes); - } - operator vuint32m1_t() const - { - return *pval; - } - unsigned get0() const - { - return vmv_x(*pval); - } - - inline v_uint32x4& operator=(const v_uint32x4& vec) { - *pval = *(vec.pval); - return *this; - } - inline v_uint32x4(const v_uint32x4& vec) { - *pval = *(vec.pval); - } - unsigned val[4]; - vuint32m1_t* pval = (vuint32m1_t*)val; -}; - -struct v_int32x4 -{ - typedef int lane_type; - enum { nlanes = 4 }; - - v_int32x4() {} - explicit v_int32x4(vint32m1_t v) - { - *pval = v; - } - v_int32x4(int v0, int v1, int v2, int v3) - { - int v[] = {v0, v1, v2, v3}; - *pval = vle32_v_i32m1(v, nlanes); - } - operator vint32m1_t() const - { - return *pval; - } - int get0() const - { - return vmv_x(*pval); - } - - inline v_int32x4& operator=(const v_int32x4& vec) { - *pval = *(vec.pval); - return *this; - } - inline v_int32x4(const v_int32x4& vec) { - *pval = *(vec.pval); - } - int val[4]; - vint32m1_t* pval = (vint32m1_t*)val; -}; - -struct v_float32x4 -{ - typedef float lane_type; - enum { nlanes = 4 }; - - v_float32x4() {} - explicit v_float32x4(vfloat32m1_t v) - { - *pval = v; - } - v_float32x4(float v0, float v1, float v2, float v3) - { - float v[] = {v0, v1, v2, v3}; - *pval = vle32_v_f32m1(v, nlanes); - } - operator vfloat32m1_t() const - { - return *pval; - } - float get0() const - { - return vfmv_f(*pval); - } - inline v_float32x4& operator=(const v_float32x4& vec) { - *pval = *(vec.pval); - return *this; - } - inline v_float32x4(const v_float32x4& vec) { - *pval = *(vec.pval); - } - float val[4]; - vfloat32m1_t* pval = (vfloat32m1_t*)val; -}; - -struct v_uint64x2 -{ - typedef uint64 lane_type; - enum { nlanes = 2 }; - - v_uint64x2() {} - explicit v_uint64x2(vuint64m1_t v) - { - *pval = v; - } - v_uint64x2(uint64 v0, uint64 v1) - { - uint64 v[] = {v0, v1}; - *pval = vle64_v_u64m1(v, nlanes); - } - operator vuint64m1_t() const - { - return *pval; - } - uint64 get0() const - { - return vmv_x(*pval); - } - - inline v_uint64x2& operator=(const v_uint64x2& vec) { - *pval = *(vec.pval); - return *this; - } - inline v_uint64x2(const v_uint64x2& vec) { - *pval = *(vec.pval); - } - uint64 val[2]; - vuint64m1_t* pval = (vuint64m1_t*)val; -}; - -struct v_int64x2 -{ - typedef int64 lane_type; - enum { nlanes = 2 }; - - v_int64x2() {} - explicit v_int64x2(vint64m1_t v) - { - *pval = v; - } - v_int64x2(int64 v0, int64 v1) - { - int64 v[] = {v0, v1}; - *pval = vle64_v_i64m1(v, nlanes); - } - operator vint64m1_t() const - { - return *pval; - } - int64 get0() const - { - return vmv_x(*pval); - } - - inline v_int64x2& operator=(const v_int64x2& vec) { - *pval = *(vec.pval); - return *this; - } - inline v_int64x2(const v_int64x2& vec) { - *pval = *(vec.pval); - } - int64 val[2]; - vint64m1_t* pval = (vint64m1_t*)val; -}; - -#if CV_SIMD128_64F -struct v_float64x2 -{ - typedef double lane_type; - enum { nlanes = 2 }; - - v_float64x2() {} - explicit v_float64x2(vfloat64m1_t v) - { - *pval = v; - } - v_float64x2(double v0, double v1) - { - double v[] = {v0, v1}; - *pval = vle64_v_f64m1(v, nlanes); - } - operator vfloat64m1_t() const - { - return *pval; - } - double get0() const - { - return vfmv_f(*pval); - } - - inline v_float64x2& operator=(const v_float64x2& vec) { - *pval = *(vec.pval); - return *this; - } - inline v_float64x2(const v_float64x2& vec) { - *pval = *(vec.pval); - } - double val[2]; - vfloat64m1_t* pval = (vfloat64m1_t*)val; -}; -#endif // CV_SIMD128_64F -#endif // __clang__ - -//////////// Initial //////////// - -#define OPENCV_HAL_IMPL_RVV_INIT_INTEGER(_Tpvec, _Tp, suffix1, suffix2, vl) \ -inline v_##_Tpvec v_setzero_##suffix1() \ -{ \ - return v_##_Tpvec(vmv_v_x_##suffix2##m1(0, vl)); \ -} \ -inline v_##_Tpvec v_setall_##suffix1(_Tp v) \ -{ \ - return v_##_Tpvec(vmv_v_x_##suffix2##m1(v, vl)); \ -} - -OPENCV_HAL_IMPL_RVV_INIT_INTEGER(uint8x16, uchar, u8, u8, 16) -OPENCV_HAL_IMPL_RVV_INIT_INTEGER(int8x16, schar, s8, i8, 16) -OPENCV_HAL_IMPL_RVV_INIT_INTEGER(uint16x8, ushort, u16, u16, 8) -OPENCV_HAL_IMPL_RVV_INIT_INTEGER(int16x8, short, s16, i16, 8) -OPENCV_HAL_IMPL_RVV_INIT_INTEGER(uint32x4, unsigned, u32, u32, 4) -OPENCV_HAL_IMPL_RVV_INIT_INTEGER(int32x4, int, s32, i32, 4) -OPENCV_HAL_IMPL_RVV_INIT_INTEGER(uint64x2, uint64, u64, u64, 2) -OPENCV_HAL_IMPL_RVV_INIT_INTEGER(int64x2, int64, s64, i64, 2) - -#define OPENCV_HAL_IMPL_RVV_INIT_FP(_Tpv, _Tp, suffix, vl) \ -inline v_##_Tpv v_setzero_##suffix() \ -{ \ - return v_##_Tpv(vfmv_v_f_##suffix##m1(0, vl)); \ -} \ -inline v_##_Tpv v_setall_##suffix(_Tp v) \ -{ \ - return v_##_Tpv(vfmv_v_f_##suffix##m1(v, vl)); \ -} - -OPENCV_HAL_IMPL_RVV_INIT_FP(float32x4, float, f32, 4) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_INIT_FP(float64x2, double, f64, 2) -#endif - -//////////// Reinterpret //////////// - -#define OPENCV_HAL_IMPL_RVV_SELF_REINTERPRET(_Tpvec, suffix) \ -inline v_##_Tpvec v_reinterpret_as_##suffix(const v_##_Tpvec& v) { return v; } - -OPENCV_HAL_IMPL_RVV_SELF_REINTERPRET(uint8x16, u8) -OPENCV_HAL_IMPL_RVV_SELF_REINTERPRET(int8x16, s8) -OPENCV_HAL_IMPL_RVV_SELF_REINTERPRET(uint16x8, u16) -OPENCV_HAL_IMPL_RVV_SELF_REINTERPRET(int16x8, s16) -OPENCV_HAL_IMPL_RVV_SELF_REINTERPRET(uint32x4, u32) -OPENCV_HAL_IMPL_RVV_SELF_REINTERPRET(int32x4, s32) -OPENCV_HAL_IMPL_RVV_SELF_REINTERPRET(float32x4, f32) -OPENCV_HAL_IMPL_RVV_SELF_REINTERPRET(uint64x2, u64) -OPENCV_HAL_IMPL_RVV_SELF_REINTERPRET(int64x2, s64) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_SELF_REINTERPRET(float64x2, f64) -#endif - -#define OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(_Tpvec1, _Tpvec2, suffix1, suffix2, nsuffix1, nsuffix2) \ -inline v_##_Tpvec1 v_reinterpret_as_##suffix1(const v_##_Tpvec2& v) \ -{ \ - return v_##_Tpvec1(vreinterpret_v_##nsuffix2##m1_##nsuffix1##m1(v));\ -} \ -inline v_##_Tpvec2 v_reinterpret_as_##suffix2(const v_##_Tpvec1& v) \ -{ \ - return v_##_Tpvec2(vreinterpret_v_##nsuffix1##m1_##nsuffix2##m1(v));\ -} - -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(uint8x16, int8x16, u8, s8, u8, i8) -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(uint16x8, int16x8, u16, s16, u16, i16) -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(uint32x4, int32x4, u32, s32, u32, i32) -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(uint32x4, float32x4, u32, f32, u32, f32) -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(int32x4, float32x4, s32, f32, i32, f32) -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(uint64x2, int64x2, u64, s64, u64, i64) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(uint64x2, float64x2, u64, f64, u64, f64) -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(int64x2, float64x2, s64, f64, i64, f64) -#endif -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(uint8x16, uint16x8, u8, u16, u8, u16) -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(uint8x16, uint32x4, u8, u32, u8, u32) -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(uint8x16, uint64x2, u8, u64, u8, u64) -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(uint16x8, uint32x4, u16, u32, u16, u32) -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(uint16x8, uint64x2, u16, u64, u16, u64) -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(uint32x4, uint64x2, u32, u64, u32, u64) -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(int8x16, int16x8, s8, s16, i8, i16) -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(int8x16, int32x4, s8, s32, i8, i32) -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(int8x16, int64x2, s8, s64, i8, i64) -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(int16x8, int32x4, s16, s32, i16, i32) -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(int16x8, int64x2, s16, s64, i16, i64) -OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(int32x4, int64x2, s32, s64, i32, i64) - - -#define OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(_Tpvec1, _Tpvec2, suffix1, suffix2, nsuffix1, nsuffix2, width1, width2) \ -inline v_##_Tpvec1 v_reinterpret_as_##suffix1(const v_##_Tpvec2& v) \ -{ \ - return v_##_Tpvec1(vreinterpret_v_##nsuffix1##width2##m1_##nsuffix1##width1##m1(vreinterpret_v_##nsuffix2##width2##m1_##nsuffix1##width2##m1(v)));\ -} \ -inline v_##_Tpvec2 v_reinterpret_as_##suffix2(const v_##_Tpvec1& v) \ -{ \ - return v_##_Tpvec2(vreinterpret_v_##nsuffix1##width2##m1_##nsuffix2##width2##m1(vreinterpret_v_##nsuffix1##width1##m1_##nsuffix1##width2##m1(v)));\ -} - -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint8x16, int16x8, u8, s16, u, i, 8, 16) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint8x16, int32x4, u8, s32, u, i, 8, 32) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint8x16, int64x2, u8, s64, u, i, 8, 64) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint16x8, int8x16, u16, s8, u, i, 16, 8) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint16x8, int32x4, u16, s32, u, i, 16, 32) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint16x8, int64x2, u16, s64, u, i, 16, 64) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint32x4, int8x16, u32, s8, u, i, 32, 8) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint32x4, int16x8, u32, s16, u, i, 32, 16) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint32x4, int64x2, u32, s64, u, i, 32, 64) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint64x2, int8x16, u64, s8, u, i, 64, 8) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint64x2, int16x8, u64, s16, u, i, 64, 16) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint64x2, int32x4, u64, s32, u, i, 64, 32) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint8x16, float32x4, u8, f32, u, f, 8, 32) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint16x8, float32x4, u16, f32, u, f, 16, 32) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint64x2, float32x4, u64, f32, u, f, 64, 32) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(int8x16, float32x4, s8, f32, i, f, 8, 32) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(int16x8, float32x4, s16, f32, i, f, 16, 32) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(int64x2, float32x4, s64, f32, i, f, 64, 32) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint8x16, float64x2, u8, f64, u, f, 8, 64) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint16x8, float64x2, u16, f64, u, f, 16, 64) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint32x4, float64x2, u32, f64, u, f, 32, 64) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(int8x16, float64x2, s8, f64, i, f, 8, 64) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(int16x8, float64x2, s16, f64, i, f, 16, 64) -OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(int32x4, float64x2, s32, f64, i, f, 32, 64) -#endif - -// Three times reinterpret -#if CV_SIMD128_64F -inline v_float32x4 v_reinterpret_as_f32(const v_float64x2& v) \ -{ \ - return v_float32x4(vreinterpret_v_u32m1_f32m1(vreinterpret_v_u64m1_u32m1(vreinterpret_v_f64m1_u64m1(v))));\ -} \ -inline v_float64x2 v_reinterpret_as_f64(const v_float32x4& v) \ -{ \ - return v_float64x2(vreinterpret_v_u64m1_f64m1(vreinterpret_v_u32m1_u64m1(vreinterpret_v_f32m1_u32m1(v))));\ -} -#endif - -////////////// Extract ////////////// - -#define OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(_Tpvec, _Tp, suffix, vmv, vl) \ -template \ -inline _Tpvec v_extract(const _Tpvec& a, const _Tpvec& b) \ -{ \ - return _Tpvec(vslideup_vx_##suffix##m1(vslidedown_vx_##suffix##m1(vmv_v_x_##suffix##m1(0, vl), a, s, vl), b, _Tpvec::nlanes - s, vl)); \ -} \ -template inline _Tp v_extract_n(_Tpvec v) \ -{ \ - return _Tp(vmv(vslidedown_vx_##suffix##m1(vmv_v_x_##suffix##m1(0, vl), v, i, vl))); \ -} - - -OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_uint8x16, uchar, u8, vmv_x_s_u8m1_u8, 16) -OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_int8x16, schar, i8, vmv_x_s_i8m1_i8, 16) -OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_uint16x8, ushort, u16, vmv_x_s_u16m1_u16, 8) -OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_int16x8, short, i16, vmv_x_s_i16m1_i16, 8) -OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_uint32x4, uint, u32, vmv_x_s_u32m1_u32, 4) -OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_int32x4, int, i32, vmv_x_s_i32m1_i32, 4) -OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_uint64x2, uint64, u64, vmv_x_s_u64m1_u64, 2) -OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_int64x2, int64, i64, vmv_x_s_i64m1_i64, 2) - -#define OPENCV_HAL_IMPL_RVV_EXTRACT_FP(_Tpvec, _Tp, suffix, vmv, vl) \ -template \ -inline _Tpvec v_extract(const _Tpvec& a, const _Tpvec& b) \ -{ \ - return _Tpvec(vslideup_vx_##suffix##m1(vslidedown_vx_##suffix##m1(vfmv_v_f_##suffix##m1(0, vl), a, s, vl), b, _Tpvec::nlanes - s, vl)); \ -} \ -template inline _Tp v_extract_n(_Tpvec v) \ -{ \ - return _Tp(vmv(vslidedown_vx_##suffix##m1(vfmv_v_f_##suffix##m1(0, vl), v, i, vl))); \ -} - -OPENCV_HAL_IMPL_RVV_EXTRACT_FP(v_float32x4, float, f32, vfmv_f_s_f32m1_f32, 4) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_EXTRACT_FP(v_float64x2, double, f64, vfmv_f_s_f64m1_f64, 2) -#endif - -////////////// Load/Store ////////////// - -#define OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(_Tpvec, _nTpvec, _Tp, hvl, vl, width, suffix, vmv) \ -inline _Tpvec v_load(const _Tp* ptr) \ -{ \ - return _Tpvec(vle##width##_v_##suffix##m1(ptr, vl)); \ -} \ -inline _Tpvec v_load_aligned(const _Tp* ptr) \ -{ \ - return _Tpvec(vle##width##_v_##suffix##m1(ptr, vl)); \ -} \ -inline _Tpvec v_load_low(const _Tp* ptr) \ -{ \ - _Tpvec res = _Tpvec(vle##width##_v_##suffix##m1(ptr, hvl)); \ - return res; \ -} \ -inline void v_store(_Tp* ptr, const _Tpvec& a) \ -{ \ - vse##width##_v_##suffix##m1(ptr, a, vl); \ -} \ -inline void v_store_aligned(_Tp* ptr, const _Tpvec& a) \ -{ \ - vse##width##_v_##suffix##m1(ptr, a, vl); \ -} \ -inline void v_store_aligned_nocache(_Tp* ptr, const _Tpvec& a) \ -{ \ - vse##width##_v_##suffix##m1(ptr, a, vl); \ -} \ -inline void v_store(_Tp* ptr, const _Tpvec& a, hal::StoreMode /*mode*/) \ -{ \ - vse##width##_v_##suffix##m1(ptr, a, vl); \ -} \ -inline void v_store_low(_Tp* ptr, const _Tpvec& a) \ -{ \ - vse##width##_v_##suffix##m1(ptr, a, hvl); \ -} \ -inline void v_store_high(_Tp* ptr, const _Tpvec& a) \ -{ \ - vse##width##_v_##suffix##m1(ptr, vslidedown_vx_##suffix##m1(vmv(0, vl), a, hvl, vl), hvl); \ -} - -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_uint8x16, vuint8m1_t, uchar, 8, 16, 8, u8, vmv_v_x_u8m1) -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_int8x16, vint8m1_t, schar, 8, 16, 8, i8, vmv_v_x_i8m1) -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_uint16x8, vuint16m1_t, ushort, 4, 8, 16, u16, vmv_v_x_u16m1) -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_int16x8, vint16m1_t, short, 4, 8, 16, i16, vmv_v_x_i16m1) -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_uint32x4, vuint32m1_t, unsigned, 2, 4, 32, u32, vmv_v_x_u32m1) -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_int32x4, vint32m1_t, int, 2, 4, 32, i32, vmv_v_x_i32m1) -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_uint64x2, vuint64m1_t, uint64, 1, 2, 64, u64, vmv_v_x_u64m1) -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_int64x2, vint64m1_t, int64, 1, 2, 64, i64, vmv_v_x_i64m1) -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_float32x4, vfloat32m1_t, float, 2, 4, 32, f32, vfmv_v_f_f32m1) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_float64x2, vfloat64m1_t, double, 1, 2, 64, f64, vfmv_v_f_f64m1) -#endif - -inline v_int8x16 v_load_halves(const schar* ptr0, const schar* ptr1) -{ - schar elems[16] = - { - ptr0[0], ptr0[1], ptr0[2], ptr0[3], ptr0[4], ptr0[5], ptr0[6], ptr0[7], - ptr1[0], ptr1[1], ptr1[2], ptr1[3], ptr1[4], ptr1[5], ptr1[6], ptr1[7] - }; - return v_int8x16(vle8_v_i8m1(elems, 16)); -} -inline v_uint8x16 v_load_halves(const uchar* ptr0, const uchar* ptr1) { return v_reinterpret_as_u8(v_load_halves((schar*)ptr0, (schar*)ptr1)); } - -inline v_int16x8 v_load_halves(const short* ptr0, const short* ptr1) -{ - short elems[8] = - { - ptr0[0], ptr0[1], ptr0[2], ptr0[3], ptr1[0], ptr1[1], ptr1[2], ptr1[3] - }; - return v_int16x8(vle16_v_i16m1(elems, 8)); -} -inline v_uint16x8 v_load_halves(const ushort* ptr0, const ushort* ptr1) { return v_reinterpret_as_u16(v_load_halves((short*)ptr0, (short*)ptr1)); } - -inline v_int32x4 v_load_halves(const int* ptr0, const int* ptr1) -{ - int elems[4] = - { - ptr0[0], ptr0[1], ptr1[0], ptr1[1] - }; - return v_int32x4(vle32_v_i32m1(elems, 4)); -} -inline v_float32x4 v_load_halves(const float* ptr0, const float* ptr1) -{ - float elems[4] = - { - ptr0[0], ptr0[1], ptr1[0], ptr1[1] - }; - return v_float32x4(vle32_v_f32m1(elems, 4)); -} -inline v_uint32x4 v_load_halves(const unsigned* ptr0, const unsigned* ptr1) { return v_reinterpret_as_u32(v_load_halves((int*)ptr0, (int*)ptr1)); } - -inline v_int64x2 v_load_halves(const int64* ptr0, const int64* ptr1) -{ - int64 elems[2] = - { - ptr0[0], ptr1[0] - }; - return v_int64x2(vle64_v_i64m1(elems, 2)); -} -inline v_uint64x2 v_load_halves(const uint64* ptr0, const uint64* ptr1) { return v_reinterpret_as_u64(v_load_halves((int64*)ptr0, (int64*)ptr1)); } - -#if CV_SIMD128_64F -inline v_float64x2 v_load_halves(const double* ptr0, const double* ptr1) -{ - double elems[2] = - { - ptr0[0], ptr1[0] - }; - return v_float64x2(vle64_v_f64m1(elems, 2)); -} -#endif - - -////////////// Lookup table access //////////////////// - -inline v_int8x16 v_lut(const schar* tab, const int* idx) -{ - schar elems[16] = - { - tab[idx[ 0]], - tab[idx[ 1]], - tab[idx[ 2]], - tab[idx[ 3]], - tab[idx[ 4]], - tab[idx[ 5]], - tab[idx[ 6]], - tab[idx[ 7]], - tab[idx[ 8]], - tab[idx[ 9]], - tab[idx[10]], - tab[idx[11]], - tab[idx[12]], - tab[idx[13]], - tab[idx[14]], - tab[idx[15]] - }; - return v_int8x16(vle8_v_i8m1(elems, 16)); -} -inline v_int8x16 v_lut_pairs(const schar* tab, const int* idx) -{ - schar elems[16] = - { - tab[idx[0]], - tab[idx[0] + 1], - tab[idx[1]], - tab[idx[1] + 1], - tab[idx[2]], - tab[idx[2] + 1], - tab[idx[3]], - tab[idx[3] + 1], - tab[idx[4]], - tab[idx[4] + 1], - tab[idx[5]], - tab[idx[5] + 1], - tab[idx[6]], - tab[idx[6] + 1], - tab[idx[7]], - tab[idx[7] + 1] - }; - return v_int8x16(vle8_v_i8m1(elems, 16)); -} -inline v_int8x16 v_lut_quads(const schar* tab, const int* idx) -{ - schar elems[16] = - { - tab[idx[0]], - tab[idx[0] + 1], - tab[idx[0] + 2], - tab[idx[0] + 3], - tab[idx[1]], - tab[idx[1] + 1], - tab[idx[1] + 2], - tab[idx[1] + 3], - tab[idx[2]], - tab[idx[2] + 1], - tab[idx[2] + 2], - tab[idx[2] + 3], - tab[idx[3]], - tab[idx[3] + 1], - tab[idx[3] + 2], - tab[idx[3] + 3] - }; - return v_int8x16(vle8_v_i8m1(elems, 16)); -} -inline v_uint8x16 v_lut(const uchar* tab, const int* idx) { return v_reinterpret_as_u8(v_lut((schar*)tab, idx)); } -inline v_uint8x16 v_lut_pairs(const uchar* tab, const int* idx) { return v_reinterpret_as_u8(v_lut_pairs((schar*)tab, idx)); } -inline v_uint8x16 v_lut_quads(const uchar* tab, const int* idx) { return v_reinterpret_as_u8(v_lut_quads((schar*)tab, idx)); } - -inline v_int16x8 v_lut(const short* tab, const int* idx) -{ - short elems[8] = - { - tab[idx[0]], - tab[idx[1]], - tab[idx[2]], - tab[idx[3]], - tab[idx[4]], - tab[idx[5]], - tab[idx[6]], - tab[idx[7]] - }; - return v_int16x8(vle16_v_i16m1(elems, 8)); -} -inline v_int16x8 v_lut_pairs(const short* tab, const int* idx) -{ - short elems[8] = - { - tab[idx[0]], - tab[idx[0] + 1], - tab[idx[1]], - tab[idx[1] + 1], - tab[idx[2]], - tab[idx[2] + 1], - tab[idx[3]], - tab[idx[3] + 1] - }; - return v_int16x8(vle16_v_i16m1(elems, 8)); -} -inline v_int16x8 v_lut_quads(const short* tab, const int* idx) -{ - short elems[8] = - { - tab[idx[0]], - tab[idx[0] + 1], - tab[idx[0] + 2], - tab[idx[0] + 3], - tab[idx[1]], - tab[idx[1] + 1], - tab[idx[1] + 2], - tab[idx[1] + 3] - }; - return v_int16x8(vle16_v_i16m1(elems, 8)); -} -inline v_uint16x8 v_lut(const ushort* tab, const int* idx) { return v_reinterpret_as_u16(v_lut((short*)tab, idx)); } -inline v_uint16x8 v_lut_pairs(const ushort* tab, const int* idx) { return v_reinterpret_as_u16(v_lut_pairs((short*)tab, idx)); } -inline v_uint16x8 v_lut_quads(const ushort* tab, const int* idx) { return v_reinterpret_as_u16(v_lut_quads((short*)tab, idx)); } - -inline v_int32x4 v_lut(const int* tab, const int* idx) -{ - int elems[4] = - { - tab[idx[0]], - tab[idx[1]], - tab[idx[2]], - tab[idx[3]] - }; - return v_int32x4(vle32_v_i32m1(elems, 4)); -} -inline v_int32x4 v_lut_pairs(const int* tab, const int* idx) -{ - int elems[4] = - { - tab[idx[0]], - tab[idx[0] + 1], - tab[idx[1]], - tab[idx[1] + 1] - }; - return v_int32x4(vle32_v_i32m1(elems, 4)); -} -inline v_int32x4 v_lut_quads(const int* tab, const int* idx) -{ - return v_int32x4(vle32_v_i32m1(tab + idx[0], 4)); -} - -inline v_uint32x4 v_lut(const unsigned* tab, const int* idx) { return v_reinterpret_as_u32(v_lut((int*)tab, idx)); } -inline v_uint32x4 v_lut_pairs(const unsigned* tab, const int* idx) { return v_reinterpret_as_u32(v_lut_pairs((int*)tab, idx)); } -inline v_uint32x4 v_lut_quads(const unsigned* tab, const int* idx) { return v_reinterpret_as_u32(v_lut_quads((int*)tab, idx)); } - -inline v_int64x2 v_lut(const int64_t* tab, const int* idx) -{ - int64_t elems[2] = - { - tab[idx[0]], - tab[idx[1]] - }; - return v_int64x2(vle64_v_i64m1(elems, 2)); -} -inline v_int64x2 v_lut_pairs(const int64* tab, const int* idx) -{ - return v_int64x2(vle64_v_i64m1(tab + idx[0], 2)); -} -inline v_uint64x2 v_lut(const uint64* tab, const int* idx) { return v_reinterpret_as_u64(v_lut((const int64_t *)tab, idx)); } -inline v_uint64x2 v_lut_pairs(const uint64* tab, const int* idx) { return v_reinterpret_as_u64(v_lut_pairs((const int64_t *)tab, idx)); } - -inline v_float32x4 v_lut(const float* tab, const int* idx) -{ - float elems[4] = - { - tab[idx[0]], - tab[idx[1]], - tab[idx[2]], - tab[idx[3]] - }; - return v_float32x4(vle32_v_f32m1(elems, 4)); -} -inline v_float32x4 v_lut_pairs(const float* tab, const int* idx) -{ - float elems[4] = - { - tab[idx[0]], - tab[idx[0] + 1], - tab[idx[1]], - tab[idx[1] + 1] - }; - return v_float32x4(vle32_v_f32m1(elems, 4)); -} -inline v_float32x4 v_lut_quads(const float* tab, const int* idx) -{ - return v_float32x4(vle32_v_f32m1(tab + idx[0], 4)); -} - -inline v_int32x4 v_lut(const int* tab, const v_int32x4& idxvec) -{ - int elems[4] = - { - tab[v_extract_n<0>(idxvec)], - tab[v_extract_n<1>(idxvec)], - tab[v_extract_n<2>(idxvec)], - tab[v_extract_n<3>(idxvec)] - }; - return v_int32x4(vle32_v_i32m1(elems, 4)); -} - -inline v_uint32x4 v_lut(const unsigned* tab, const v_int32x4& idxvec) -{ - unsigned elems[4] = - { - tab[v_extract_n<0>(idxvec)], - tab[v_extract_n<1>(idxvec)], - tab[v_extract_n<2>(idxvec)], - tab[v_extract_n<3>(idxvec)] - }; - return v_uint32x4(vle32_v_u32m1(elems, 4)); -} - -inline v_float32x4 v_lut(const float* tab, const v_int32x4& idxvec) -{ - float elems[4] = - { - tab[v_extract_n<0>(idxvec)], - tab[v_extract_n<1>(idxvec)], - tab[v_extract_n<2>(idxvec)], - tab[v_extract_n<3>(idxvec)] - }; - return v_float32x4(vle32_v_f32m1(elems, 4)); -} - -inline void v_lut_deinterleave(const float* tab, const v_int32x4& idxvec, v_float32x4& x, v_float32x4& y) -{ - int idx[4]; - v_store_aligned(idx, idxvec); - - x = v_float32x4(tab[idx[0]], tab[idx[1]], tab[idx[2]], tab[idx[3]]); - y = v_float32x4(tab[idx[0]+1], tab[idx[1]+1], tab[idx[2]+1], tab[idx[3]+1]); -} - -#if CV_SIMD128_64F -inline v_float64x2 v_lut(const double* tab, const int* idx) -{ - double elems[2] = - { - tab[idx[0]], - tab[idx[1]] - }; - return v_float64x2(vle64_v_f64m1(elems, 2)); -} - -inline v_float64x2 v_lut_pairs(const double* tab, const int* idx) -{ - return v_float64x2(vle64_v_f64m1(tab + idx[0], 2)); -} - -inline v_float64x2 v_lut(const double* tab, const v_int32x4& idxvec) -{ - double elems[2] = - { - tab[v_extract_n<0>(idxvec)], - tab[v_extract_n<1>(idxvec)] - }; - return v_float64x2(vle64_v_f64m1(elems, 2)); -} - -inline void v_lut_deinterleave(const double* tab, const v_int32x4& idxvec, v_float64x2& x, v_float64x2& y) -{ - int idx[4] = {0}; - v_store_aligned(idx, idxvec); - - x = v_float64x2(tab[idx[0]], tab[idx[1]]); - y = v_float64x2(tab[idx[0]+1], tab[idx[1]+1]); -} -#endif - -////////////// Pack boolean //////////////////// - -inline v_uint8x16 v_pack_b(const v_uint16x8& a, const v_uint16x8& b) -{ - ushort ptr[16] = {0}; - v_store(ptr, a); - v_store(ptr + 8, b); - return v_uint8x16(vnsrl_wx_u8m1(vle16_v_u16m2(ptr, 16), 0, 16)); -} - -inline v_uint8x16 v_pack_b(const v_uint32x4& a, const v_uint32x4& b, - const v_uint32x4& c, const v_uint32x4& d) -{ - unsigned ptr[16] = {0}; - v_store(ptr, a); - v_store(ptr + 4, b); - v_store(ptr + 8, c); - v_store(ptr + 12, d); - return v_uint8x16(vnsrl_wx_u8m1(vnsrl_wx_u16m2(vle32_v_u32m4(ptr, 16), 0, 16), 0, 16)); -} - -inline v_uint8x16 v_pack_b(const v_uint64x2& a, const v_uint64x2& b, const v_uint64x2& c, - const v_uint64x2& d, const v_uint64x2& e, const v_uint64x2& f, - const v_uint64x2& g, const v_uint64x2& h) -{ - uint64 ptr[16] = {0}; - v_store(ptr, a); - v_store(ptr + 2, b); - v_store(ptr + 4, c); - v_store(ptr + 6, d); - v_store(ptr + 8, e); - v_store(ptr + 10, f); - v_store(ptr + 12, g); - v_store(ptr + 14, h); - return v_uint8x16(vnsrl_wx_u8m1(vnsrl_wx_u16m2(vnsrl_wx_u32m4(vle64_v_u64m8(ptr, 16), 0, 16), 0, 16), 0, 16)); -} - -////////////// Arithmetics ////////////// -#define OPENCV_HAL_IMPL_RVV_BIN_OP(bin_op, _Tpvec, intrin, vl) \ -inline _Tpvec operator bin_op (const _Tpvec& a, const _Tpvec& b) \ -{ \ - return _Tpvec(intrin(a, b, vl)); \ -} \ -inline _Tpvec& operator bin_op##= (_Tpvec& a, const _Tpvec& b) \ -{ \ - a = _Tpvec(intrin(a, b, vl)); \ - return a; \ -} - -OPENCV_HAL_IMPL_RVV_BIN_OP(+, v_uint8x16, vsaddu_vv_u8m1, 16) -OPENCV_HAL_IMPL_RVV_BIN_OP(-, v_uint8x16, vssubu_vv_u8m1, 16) -OPENCV_HAL_IMPL_RVV_BIN_OP(/, v_uint8x16, vdivu_vv_u8m1, 16) -OPENCV_HAL_IMPL_RVV_BIN_OP(+, v_int8x16, vsadd_vv_i8m1, 16) -OPENCV_HAL_IMPL_RVV_BIN_OP(-, v_int8x16, vssub_vv_i8m1, 16) -OPENCV_HAL_IMPL_RVV_BIN_OP(/, v_int8x16, vdiv_vv_i8m1, 16) -OPENCV_HAL_IMPL_RVV_BIN_OP(+, v_uint16x8, vsaddu_vv_u16m1, 8) -OPENCV_HAL_IMPL_RVV_BIN_OP(-, v_uint16x8, vssubu_vv_u16m1, 8) -OPENCV_HAL_IMPL_RVV_BIN_OP(/, v_uint16x8, vdivu_vv_u16m1, 8) -OPENCV_HAL_IMPL_RVV_BIN_OP(+, v_int16x8, vsadd_vv_i16m1, 8) -OPENCV_HAL_IMPL_RVV_BIN_OP(-, v_int16x8, vssub_vv_i16m1, 8) -OPENCV_HAL_IMPL_RVV_BIN_OP(/, v_int16x8, vdiv_vv_i16m1, 8) -OPENCV_HAL_IMPL_RVV_BIN_OP(+, v_uint32x4, vadd_vv_u32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_OP(-, v_uint32x4, vsub_vv_u32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_OP(*, v_uint32x4, vmul_vv_u32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_OP(/, v_uint32x4, vdivu_vv_u32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_OP(+, v_int32x4, vadd_vv_i32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_OP(-, v_int32x4, vsub_vv_i32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_OP(*, v_int32x4, vmul_vv_i32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_OP(/, v_int32x4, vdiv_vv_i32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_OP(+, v_float32x4, vfadd_vv_f32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_OP(-, v_float32x4, vfsub_vv_f32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_OP(*, v_float32x4, vfmul_vv_f32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_OP(/, v_float32x4, vfdiv_vv_f32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_OP(+, v_uint64x2, vadd_vv_u64m1, 2) -OPENCV_HAL_IMPL_RVV_BIN_OP(-, v_uint64x2, vsub_vv_u64m1, 2) -OPENCV_HAL_IMPL_RVV_BIN_OP(*, v_uint64x2, vmul_vv_u64m1, 2) -OPENCV_HAL_IMPL_RVV_BIN_OP(/, v_uint64x2, vdivu_vv_u64m1, 2) -OPENCV_HAL_IMPL_RVV_BIN_OP(+, v_int64x2, vadd_vv_i64m1, 2) -OPENCV_HAL_IMPL_RVV_BIN_OP(-, v_int64x2, vsub_vv_i64m1, 2) -OPENCV_HAL_IMPL_RVV_BIN_OP(*, v_int64x2, vmul_vv_i64m1, 2) -OPENCV_HAL_IMPL_RVV_BIN_OP(/, v_int64x2, vdiv_vv_i64m1, 2) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_BIN_OP(+, v_float64x2, vfadd_vv_f64m1, 2) -OPENCV_HAL_IMPL_RVV_BIN_OP(-, v_float64x2, vfsub_vv_f64m1, 2) -OPENCV_HAL_IMPL_RVV_BIN_OP(*, v_float64x2, vfmul_vv_f64m1, 2) -OPENCV_HAL_IMPL_RVV_BIN_OP(/, v_float64x2, vfdiv_vv_f64m1, 2) -#endif - - -////////////// Bitwise logic ////////////// - -#define OPENCV_HAL_IMPL_RVV_LOGIC_OP(_Tpvec, suffix, vl) \ -OPENCV_HAL_IMPL_RVV_BIN_OP(&, _Tpvec, vand_vv_##suffix##m1, vl) \ -OPENCV_HAL_IMPL_RVV_BIN_OP(|, _Tpvec, vor_vv_##suffix##m1, vl) \ -OPENCV_HAL_IMPL_RVV_BIN_OP(^, _Tpvec, vxor_vv_##suffix##m1, vl) \ -inline _Tpvec operator ~ (const _Tpvec& a) \ -{ \ - return _Tpvec(vnot_v_##suffix##m1(a, vl)); \ -} - -OPENCV_HAL_IMPL_RVV_LOGIC_OP(v_uint8x16, u8, 16) -OPENCV_HAL_IMPL_RVV_LOGIC_OP(v_int8x16, i8, 16) -OPENCV_HAL_IMPL_RVV_LOGIC_OP(v_uint16x8, u16, 8) -OPENCV_HAL_IMPL_RVV_LOGIC_OP(v_int16x8, i16, 8) -OPENCV_HAL_IMPL_RVV_LOGIC_OP(v_uint32x4, u32, 4) -OPENCV_HAL_IMPL_RVV_LOGIC_OP(v_int32x4, i32, 4) -OPENCV_HAL_IMPL_RVV_LOGIC_OP(v_uint64x2, u64, 2) -OPENCV_HAL_IMPL_RVV_LOGIC_OP(v_int64x2, i64, 2) - -#define OPENCV_HAL_IMPL_RVV_FLT_BIT_OP(bin_op, intrin) \ -inline v_float32x4 operator bin_op (const v_float32x4& a, const v_float32x4& b) \ -{ \ - return v_float32x4(vreinterpret_v_i32m1_f32m1(intrin(vreinterpret_v_f32m1_i32m1(a), vreinterpret_v_f32m1_i32m1(b), 4))); \ -} \ -inline v_float32x4& operator bin_op##= (v_float32x4& a, const v_float32x4& b) \ -{ \ - a = v_float32x4(vreinterpret_v_i32m1_f32m1(intrin(vreinterpret_v_f32m1_i32m1(a), vreinterpret_v_f32m1_i32m1(b), 4))); \ - return a; \ -} - -OPENCV_HAL_IMPL_RVV_FLT_BIT_OP(&, vand_vv_i32m1) -OPENCV_HAL_IMPL_RVV_FLT_BIT_OP(|, vor_vv_i32m1) -OPENCV_HAL_IMPL_RVV_FLT_BIT_OP(^, vxor_vv_i32m1) - -inline v_float32x4 operator ~ (const v_float32x4& a) -{ - return v_float32x4(vreinterpret_v_i32m1_f32m1(vnot_v_i32m1(vreinterpret_v_f32m1_i32m1(a), 4))); -} - -#if CV_SIMD128_64F -#define OPENCV_HAL_IMPL_RVV_FLT64_BIT_OP(bin_op, intrin) \ -inline v_float64x2 operator bin_op (const v_float64x2& a, const v_float64x2& b) \ -{ \ - return v_float64x2(vreinterpret_v_i64m1_f64m1(intrin(vreinterpret_v_f64m1_i64m1(a), vreinterpret_v_f64m1_i64m1(b), 2))); \ -} \ -inline v_float64x2& operator bin_op##= (v_float64x2& a, const v_float64x2& b) \ -{ \ - a = v_float64x2(vreinterpret_v_i64m1_f64m1(intrin(vreinterpret_v_f64m1_i64m1(a), vreinterpret_v_f64m1_i64m1(b), 2))); \ - return a; \ -} - -OPENCV_HAL_IMPL_RVV_FLT64_BIT_OP(&, vand_vv_i64m1) -OPENCV_HAL_IMPL_RVV_FLT64_BIT_OP(|, vor_vv_i64m1) -OPENCV_HAL_IMPL_RVV_FLT64_BIT_OP(^, vxor_vv_i64m1) - -inline v_float64x2 operator ~ (const v_float64x2& a) -{ - return v_float64x2(vreinterpret_v_i64m1_f64m1(vnot_v_i64m1(vreinterpret_v_f64m1_i64m1(a), 2))); -} -#endif - -////////////// Bitwise shifts ////////////// - -#define OPENCV_HAL_IMPL_RVV_UNSIGNED_SHIFT_OP(_Tpvec, suffix, vl) \ -inline _Tpvec operator << (const _Tpvec& a, int n) \ -{ \ - return _Tpvec(vsll_vx_##suffix##m1(a, uint8_t(n), vl)); \ -} \ -inline _Tpvec operator >> (const _Tpvec& a, int n) \ -{ \ - return _Tpvec(vsrl_vx_##suffix##m1(a, uint8_t(n), vl)); \ -} \ -template inline _Tpvec v_shl(const _Tpvec& a) \ -{ \ - return _Tpvec(vsll_vx_##suffix##m1(a, uint8_t(n), vl)); \ -} \ -template inline _Tpvec v_shr(const _Tpvec& a) \ -{ \ - return _Tpvec(vsrl_vx_##suffix##m1(a, uint8_t(n), vl)); \ -} - -#define OPENCV_HAL_IMPL_RVV_SIGNED_SHIFT_OP(_Tpvec, suffix, vl) \ -inline _Tpvec operator << (const _Tpvec& a, int n) \ -{ \ - return _Tpvec(vsll_vx_##suffix##m1(a, uint8_t(n), vl)); \ -} \ -inline _Tpvec operator >> (const _Tpvec& a, int n) \ -{ \ - return _Tpvec(vsra_vx_##suffix##m1(a, uint8_t(n), vl)); \ -} \ -template inline _Tpvec v_shl(const _Tpvec& a) \ -{ \ - return _Tpvec(vsll_vx_##suffix##m1(a, uint8_t(n), vl)); \ -} \ -template inline _Tpvec v_shr(const _Tpvec& a) \ -{ \ - return _Tpvec(vsra_vx_##suffix##m1(a, uint8_t(n), vl)); \ -} - -OPENCV_HAL_IMPL_RVV_UNSIGNED_SHIFT_OP(v_uint8x16, u8, 16) -OPENCV_HAL_IMPL_RVV_UNSIGNED_SHIFT_OP(v_uint16x8, u16, 8) -OPENCV_HAL_IMPL_RVV_UNSIGNED_SHIFT_OP(v_uint32x4, u32, 4) -OPENCV_HAL_IMPL_RVV_UNSIGNED_SHIFT_OP(v_uint64x2, u64, 2) -OPENCV_HAL_IMPL_RVV_SIGNED_SHIFT_OP(v_int8x16, i8, 16) -OPENCV_HAL_IMPL_RVV_SIGNED_SHIFT_OP(v_int16x8, i16, 8) -OPENCV_HAL_IMPL_RVV_SIGNED_SHIFT_OP(v_int32x4, i32, 4) -OPENCV_HAL_IMPL_RVV_SIGNED_SHIFT_OP(v_int64x2, i64, 2) - - -////////////// Comparison ////////////// - -#define OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, op, intrin, suffix, vl) \ -inline _Tpvec operator op (const _Tpvec& a, const _Tpvec& b) \ -{ \ - uint64_t ones = -1; \ - return _Tpvec(vmerge_vxm_##suffix##m1(intrin(a, b, vl), vmv_v_x_##suffix##m1(0, vl), ones, vl)); \ -} - -#define OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, op, intrin, suffix, vl) \ -inline _Tpvec operator op (const _Tpvec& a, const _Tpvec& b) \ -{ \ - union { uint64 u; double d; } ones; ones.u = -1; \ - return _Tpvec(vfmerge_vfm_##suffix##m1(intrin(a, b, vl), vfmv_v_f_##suffix##m1(0, vl), ones.d, vl)); \ -} - -#define OPENCV_HAL_IMPL_RVV_UNSIGNED_CMP(_Tpvec, suffix, width, vl) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, ==, vmseq_vv_##suffix##m1_b##width, suffix, vl) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, !=, vmsne_vv_##suffix##m1_b##width, suffix, vl) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, <, vmsltu_vv_##suffix##m1_b##width, suffix, vl) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, >, vmsgtu_vv_##suffix##m1_b##width, suffix, vl) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, <=, vmsleu_vv_##suffix##m1_b##width, suffix, vl) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, >=, vmsgeu_vv_##suffix##m1_b##width, suffix, vl) - -#define OPENCV_HAL_IMPL_RVV_SIGNED_CMP(_Tpvec, suffix, width, vl) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, ==, vmseq_vv_##suffix##m1_b##width, suffix, vl) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, !=, vmsne_vv_##suffix##m1_b##width, suffix, vl) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, <, vmslt_vv_##suffix##m1_b##width, suffix, vl) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, >, vmsgt_vv_##suffix##m1_b##width, suffix, vl) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, <=, vmsle_vv_##suffix##m1_b##width, suffix, vl) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, >=, vmsge_vv_##suffix##m1_b##width, suffix, vl) - -#define OPENCV_HAL_IMPL_RVV_FLOAT_CMP(_Tpvec, suffix, width, vl) \ -OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, ==, vmfeq_vv_##suffix##m1_b##width, suffix, vl) \ -OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, !=, vmfne_vv_##suffix##m1_b##width, suffix, vl) \ -OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, <, vmflt_vv_##suffix##m1_b##width, suffix, vl) \ -OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, >, vmfgt_vv_##suffix##m1_b##width, suffix, vl) \ -OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, <=, vmfle_vv_##suffix##m1_b##width, suffix, vl) \ -OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, >=, vmfge_vv_##suffix##m1_b##width, suffix, vl) - - -OPENCV_HAL_IMPL_RVV_UNSIGNED_CMP(v_uint8x16, u8, 8, 16) -OPENCV_HAL_IMPL_RVV_UNSIGNED_CMP(v_uint16x8, u16, 16, 8) -OPENCV_HAL_IMPL_RVV_UNSIGNED_CMP(v_uint32x4, u32, 32, 4) -OPENCV_HAL_IMPL_RVV_UNSIGNED_CMP(v_uint64x2, u64, 64, 2) -OPENCV_HAL_IMPL_RVV_SIGNED_CMP(v_int8x16, i8, 8, 16) -OPENCV_HAL_IMPL_RVV_SIGNED_CMP(v_int16x8, i16, 16, 8) -OPENCV_HAL_IMPL_RVV_SIGNED_CMP(v_int32x4, i32, 32, 4) -OPENCV_HAL_IMPL_RVV_SIGNED_CMP(v_int64x2, i64, 64, 2) -OPENCV_HAL_IMPL_RVV_FLOAT_CMP(v_float32x4, f32, 32, 4) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_FLOAT_CMP(v_float64x2, f64, 64, 2) -#endif - -inline v_float32x4 v_not_nan(const v_float32x4& a) -{ return a == a; } - -#if CV_SIMD128_64F -inline v_float64x2 v_not_nan(const v_float64x2& a) -{ return a == a; } -#endif - -////////////// Min/Max ////////////// - -#define OPENCV_HAL_IMPL_RVV_BIN_FUNC(_Tpvec, func, intrin, vl) \ -inline _Tpvec func(const _Tpvec& a, const _Tpvec& b) \ -{ \ - return _Tpvec(intrin(a, b, vl)); \ -} - -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint8x16, v_min, vminu_vv_u8m1, 16) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint8x16, v_max, vmaxu_vv_u8m1, 16) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int8x16, v_min, vmin_vv_i8m1, 16) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int8x16, v_max, vmax_vv_i8m1, 16) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint16x8, v_min, vminu_vv_u16m1, 8) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint16x8, v_max, vmaxu_vv_u16m1, 8) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int16x8, v_min, vmin_vv_i16m1, 8) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int16x8, v_max, vmax_vv_i16m1, 8) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint32x4, v_min, vminu_vv_u32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint32x4, v_max, vmaxu_vv_u32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int32x4, v_min, vmin_vv_i32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int32x4, v_max, vmax_vv_i32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_float32x4, v_min, vfmin_vv_f32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_float32x4, v_max, vfmax_vv_f32m1, 4) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint64x2, v_min, vminu_vv_u64m1, 2) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint64x2, v_max, vmaxu_vv_u64m1, 2) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int64x2, v_min, vmin_vv_i64m1, 2) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int64x2, v_max, vmax_vv_i64m1, 2) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_float64x2, v_min, vfmin_vv_f64m1, 2) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_float64x2, v_max, vfmax_vv_f64m1, 2) -#endif - -////////////// Arithmetics wrap ////////////// - -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint8x16, v_add_wrap, vadd_vv_u8m1, 16) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int8x16, v_add_wrap, vadd_vv_i8m1, 16) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint16x8, v_add_wrap, vadd_vv_u16m1, 8) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int16x8, v_add_wrap, vadd_vv_i16m1, 8) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint8x16, v_sub_wrap, vsub_vv_u8m1, 16) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int8x16, v_sub_wrap, vsub_vv_i8m1, 16) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint16x8, v_sub_wrap, vsub_vv_u16m1, 8) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int16x8, v_sub_wrap, vsub_vv_i16m1, 8) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint8x16, v_mul_wrap, vmul_vv_u8m1, 16) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int8x16, v_mul_wrap, vmul_vv_i8m1, 16) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint16x8, v_mul_wrap, vmul_vv_u16m1, 8) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int16x8, v_mul_wrap, vmul_vv_i16m1, 8) - -////////////// Reduce ////////////// - -#define OPENCV_HAL_IMPL_RVV_REDUCE_SUM(_Tpvec, _wTpvec, _nwTpvec, scalartype, suffix, wsuffix, vl, red) \ -inline scalartype v_reduce_sum(const _Tpvec& a) \ -{ \ - _nwTpvec zero = vmv_v_x_##wsuffix##m1(0, vl); \ - _nwTpvec res = vmv_v_x_##wsuffix##m1(0, vl); \ - res = v##red##_vs_##suffix##m1_##wsuffix##m1(res, a, zero, vl); \ - return (scalartype)(_wTpvec(res).get0()); \ -} - -OPENCV_HAL_IMPL_RVV_REDUCE_SUM(v_uint8x16, v_uint16x8, vuint16m1_t, unsigned, u8, u16, 16, wredsumu) -OPENCV_HAL_IMPL_RVV_REDUCE_SUM(v_int8x16, v_int16x8, vint16m1_t, int, i8, i16, 16, wredsum) -OPENCV_HAL_IMPL_RVV_REDUCE_SUM(v_uint16x8, v_uint32x4, vuint32m1_t, unsigned, u16, u32, 8, wredsumu) -OPENCV_HAL_IMPL_RVV_REDUCE_SUM(v_int16x8, v_int32x4, vint32m1_t, int, i16, i32, 8, wredsum) -OPENCV_HAL_IMPL_RVV_REDUCE_SUM(v_uint32x4, v_uint64x2, vuint64m1_t, unsigned, u32, u64, 4, wredsumu) -OPENCV_HAL_IMPL_RVV_REDUCE_SUM(v_int32x4, v_int64x2, vint64m1_t, int, i32, i64, 4, wredsum) -OPENCV_HAL_IMPL_RVV_REDUCE_SUM(v_uint64x2, v_uint64x2, vuint64m1_t, uint64, u64, u64, 2, redsum) -OPENCV_HAL_IMPL_RVV_REDUCE_SUM(v_int64x2, v_int64x2, vint64m1_t, int64, i64, i64, 2, redsum) - -#define OPENCV_HAL_IMPL_RVV_REDUCE_SUM_FP(_Tpvec, _wTpvec, _nwTpvec, scalartype, suffix, wsuffix, vl, red) \ -inline scalartype v_reduce_sum(const _Tpvec& a) \ -{ \ - _nwTpvec zero = vfmv_v_f_##wsuffix##m1(0, vl); \ - _nwTpvec res = vfmv_v_f_##wsuffix##m1(0, vl); \ - res = v##red##_vs_##suffix##m1_##wsuffix##m1(res, a, zero, vl); \ - return (scalartype)(_wTpvec(res).get0()); \ -} - -// vfredsum for float has renamed to fredosum, also updated in GNU. -OPENCV_HAL_IMPL_RVV_REDUCE_SUM_FP(v_float32x4, v_float32x4, vfloat32m1_t, float, f32, f32, 4, fredosum) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_REDUCE_SUM_FP(v_float64x2, v_float64x2, vfloat64m1_t, double, f64, f64, 2, fredosum) -#endif - - -#define OPENCV_HAL_IMPL_RVV_REDUCE(_Tpvec, func, scalartype, suffix, vl, red) \ -inline scalartype v_reduce_##func(const _Tpvec& a) \ -{ \ - _Tpvec res = _Tpvec(v##red##_vs_##suffix##m1_##suffix##m1(a, a, a, vl)); \ - return scalartype(res.get0()); \ -} - -OPENCV_HAL_IMPL_RVV_REDUCE(v_uint8x16, min, uchar, u8, 16, redminu) -OPENCV_HAL_IMPL_RVV_REDUCE(v_int8x16, min, schar, i8, 16, redmin) -OPENCV_HAL_IMPL_RVV_REDUCE(v_uint16x8, min, ushort, u16, 8, redminu) -OPENCV_HAL_IMPL_RVV_REDUCE(v_int16x8, min, short, i16, 8, redmin) -OPENCV_HAL_IMPL_RVV_REDUCE(v_uint32x4, min, unsigned, u32, 4, redminu) -OPENCV_HAL_IMPL_RVV_REDUCE(v_int32x4, min, int, i32, 4, redmin) -OPENCV_HAL_IMPL_RVV_REDUCE(v_float32x4, min, float, f32, 4, fredmin) -OPENCV_HAL_IMPL_RVV_REDUCE(v_uint8x16, max, uchar, u8, 16, redmaxu) -OPENCV_HAL_IMPL_RVV_REDUCE(v_int8x16, max, schar, i8, 16, redmax) -OPENCV_HAL_IMPL_RVV_REDUCE(v_uint16x8, max, ushort, u16, 8, redmaxu) -OPENCV_HAL_IMPL_RVV_REDUCE(v_int16x8, max, short, i16, 8, redmax) -OPENCV_HAL_IMPL_RVV_REDUCE(v_uint32x4, max, unsigned, u32, 4, redmaxu) -OPENCV_HAL_IMPL_RVV_REDUCE(v_int32x4, max, int, i32, 4, redmax) -OPENCV_HAL_IMPL_RVV_REDUCE(v_float32x4, max, float, f32, 4, fredmax) - - -inline v_float32x4 v_reduce_sum4(const v_float32x4& a, const v_float32x4& b, - const v_float32x4& c, const v_float32x4& d) -{ - float elems[4] = - { - v_reduce_sum(a), - v_reduce_sum(b), - v_reduce_sum(c), - v_reduce_sum(d) - }; - return v_float32x4(vle32_v_f32m1(elems, 4)); -} - -////////////// Square-Root ////////////// - -inline v_float32x4 v_sqrt(const v_float32x4& x) -{ - return v_float32x4(vfsqrt_v_f32m1(x, 4)); -} - -inline v_float32x4 v_invsqrt(const v_float32x4& x) -{ - v_float32x4 one = v_setall_f32(1.0f); - return one / v_sqrt(x); -} - -#if CV_SIMD128_64F -inline v_float64x2 v_sqrt(const v_float64x2& x) -{ - return v_float64x2(vfsqrt_v_f64m1(x, 4)); -} - -inline v_float64x2 v_invsqrt(const v_float64x2& x) -{ - v_float64x2 one = v_setall_f64(1.0f); - return one / v_sqrt(x); -} -#endif - -inline v_float32x4 v_magnitude(const v_float32x4& a, const v_float32x4& b) -{ - v_float32x4 x(vfmacc_vv_f32m1(vfmul_vv_f32m1(a, a, 4), b, b, 4)); - return v_sqrt(x); -} - -inline v_float32x4 v_sqr_magnitude(const v_float32x4& a, const v_float32x4& b) -{ - return v_float32x4(vfmacc_vv_f32m1(vfmul_vv_f32m1(a, a, 4), b, b, 4)); -} - -#if CV_SIMD128_64F -inline v_float64x2 v_magnitude(const v_float64x2& a, const v_float64x2& b) -{ - v_float64x2 x(vfmacc_vv_f64m1(vfmul_vv_f64m1(a, a, 2), b, b, 2)); - return v_sqrt(x); -} - -inline v_float64x2 v_sqr_magnitude(const v_float64x2& a, const v_float64x2& b) -{ - return v_float64x2(vfmacc_vv_f64m1(vfmul_vv_f64m1(a, a, 2), b, b, 2)); -} -#endif - -////////////// Multiply-Add ////////////// - -inline v_float32x4 v_fma(const v_float32x4& a, const v_float32x4& b, const v_float32x4& c) -{ - return v_float32x4(vfmacc_vv_f32m1(c, a, b, 4)); -} -inline v_int32x4 v_fma(const v_int32x4& a, const v_int32x4& b, const v_int32x4& c) -{ - return v_int32x4(vmacc_vv_i32m1(c, a, b, 4)); -} - -inline v_float32x4 v_muladd(const v_float32x4& a, const v_float32x4& b, const v_float32x4& c) -{ - return v_fma(a, b, c); -} - -inline v_int32x4 v_muladd(const v_int32x4& a, const v_int32x4& b, const v_int32x4& c) -{ - return v_fma(a, b, c); -} - -#if CV_SIMD128_64F -inline v_float64x2 v_fma(const v_float64x2& a, const v_float64x2& b, const v_float64x2& c) -{ - return v_float64x2(vfmacc_vv_f64m1(c, a, b, 2)); -} - -inline v_float64x2 v_muladd(const v_float64x2& a, const v_float64x2& b, const v_float64x2& c) -{ - return v_fma(a, b, c); -} -#endif - -////////////// Check all/any ////////////// - -// use overloaded vcpop in clang, no casting like (vuint64m1_t) is needed. -#ifndef __clang__ -#define OPENCV_HAL_IMPL_RVV_CHECK_ALLANY(_Tpvec, suffix, shift, vl) \ -inline bool v_check_all(const _Tpvec& a) \ -{ \ - auto v0 = vsrl_vx_##suffix##m1(vnot_v_##suffix##m1(a, vl), shift, vl); \ - v_uint32x4 v = v_uint32x4(v_reinterpret_as_u32(_Tpvec(v0))); \ - return (v.val[0] | v.val[1] | v.val[2] | v.val[3]) == 0; \ -} \ -inline bool v_check_any(const _Tpvec& a) \ -{ \ - auto v0 = vsrl_vx_##suffix##m1(a, shift, vl); \ - v_uint32x4 v = v_uint32x4(v_reinterpret_as_u32(_Tpvec(v0))); \ - return (v.val[0] | v.val[1] | v.val[2] | v.val[3]) != 0; \ -} - -OPENCV_HAL_IMPL_RVV_CHECK_ALLANY(v_uint8x16, u8, 7, 16) -OPENCV_HAL_IMPL_RVV_CHECK_ALLANY(v_uint16x8, u16, 15, 8) -OPENCV_HAL_IMPL_RVV_CHECK_ALLANY(v_uint32x4, u32, 31, 4) -//OPENCV_HAL_IMPL_RVV_CHECK_ALLANY(v_uint64x2, u64, 63, 2) -inline bool v_check_all(const v_uint64x2& a) -{ - v_uint64x2 v = v_uint64x2(vsrl_vx_u64m1(vnot_v_u64m1(a, 2), 63, 2)); - return (v.val[0] | v.val[1]) == 0; -} -inline bool v_check_any(const v_uint64x2& a) -{ - v_uint64x2 v = v_uint64x2(vsrl_vx_u64m1(a, 63, 2)); - return (v.val[0] | v.val[1]) != 0; -} - -inline bool v_check_all(const v_int8x16& a) -{ return v_check_all(v_reinterpret_as_u8(a)); } -inline bool v_check_any(const v_int8x16& a) -{ return v_check_any(v_reinterpret_as_u8(a)); } - -inline bool v_check_all(const v_int16x8& a) -{ return v_check_all(v_reinterpret_as_u16(a)); } -inline bool v_check_any(const v_int16x8& a) -{ return v_check_any(v_reinterpret_as_u16(a)); } - -inline bool v_check_all(const v_int32x4& a) -{ return v_check_all(v_reinterpret_as_u32(a)); } -inline bool v_check_any(const v_int32x4& a) -{ return v_check_any(v_reinterpret_as_u32(a)); } - -inline bool v_check_all(const v_float32x4& a) -{ return v_check_all(v_reinterpret_as_u32(a)); } -inline bool v_check_any(const v_float32x4& a) -{ return v_check_any(v_reinterpret_as_u32(a)); } - -inline bool v_check_all(const v_int64x2& a) -{ return v_check_all(v_reinterpret_as_u64(a)); } -inline bool v_check_any(const v_int64x2& a) -{ return v_check_any(v_reinterpret_as_u64(a)); } - -#if CV_SIMD128_64F -inline bool v_check_all(const v_float64x2& a) -{ return v_check_all(v_reinterpret_as_u64(a)); } -inline bool v_check_any(const v_float64x2& a) -{ return v_check_any(v_reinterpret_as_u64(a)); } -#endif -#else -#define OPENCV_HAL_IMPL_RVV_CHECK_ALLANY(_Tpvec, vl) \ -inline bool v_check_all(const _Tpvec& a) \ -{ \ - return vcpop(vmslt(a, 0, vl), vl) == vl; \ -} \ -inline bool v_check_any(const _Tpvec& a) \ -{ \ - return vcpop(vmslt(a, 0, vl), vl) != 0; \ -} - -OPENCV_HAL_IMPL_RVV_CHECK_ALLANY(v_int8x16, 16) -OPENCV_HAL_IMPL_RVV_CHECK_ALLANY(v_int16x8, 8) -OPENCV_HAL_IMPL_RVV_CHECK_ALLANY(v_int32x4, 4) -OPENCV_HAL_IMPL_RVV_CHECK_ALLANY(v_int64x2, 2) - - -inline bool v_check_all(const v_uint8x16& a) -{ return v_check_all(v_reinterpret_as_s8(a)); } -inline bool v_check_any(const v_uint8x16& a) -{ return v_check_any(v_reinterpret_as_s8(a)); } - -inline bool v_check_all(const v_uint16x8& a) -{ return v_check_all(v_reinterpret_as_s16(a)); } -inline bool v_check_any(const v_uint16x8& a) -{ return v_check_any(v_reinterpret_as_s16(a)); } - -inline bool v_check_all(const v_uint32x4& a) -{ return v_check_all(v_reinterpret_as_s32(a)); } -inline bool v_check_any(const v_uint32x4& a) -{ return v_check_any(v_reinterpret_as_s32(a)); } - -inline bool v_check_all(const v_float32x4& a) -{ return v_check_all(v_reinterpret_as_s32(a)); } -inline bool v_check_any(const v_float32x4& a) -{ return v_check_any(v_reinterpret_as_s32(a)); } - -inline bool v_check_all(const v_uint64x2& a) -{ return v_check_all(v_reinterpret_as_s64(a)); } -inline bool v_check_any(const v_uint64x2& a) -{ return v_check_any(v_reinterpret_as_s64(a)); } - -#if CV_SIMD128_64F -inline bool v_check_all(const v_float64x2& a) -{ return v_check_all(v_reinterpret_as_s64(a)); } -inline bool v_check_any(const v_float64x2& a) -{ return v_check_any(v_reinterpret_as_s64(a)); } -#endif -#endif -////////////// abs ////////////// - -#define OPENCV_HAL_IMPL_RVV_ABSDIFF(_Tpvec, abs) \ -inline _Tpvec v_##abs(const _Tpvec& a, const _Tpvec& b) \ -{ \ - return v_max(a, b) - v_min(a, b); \ -} - -OPENCV_HAL_IMPL_RVV_ABSDIFF(v_uint8x16, absdiff) -OPENCV_HAL_IMPL_RVV_ABSDIFF(v_uint16x8, absdiff) -OPENCV_HAL_IMPL_RVV_ABSDIFF(v_uint32x4, absdiff) -OPENCV_HAL_IMPL_RVV_ABSDIFF(v_float32x4, absdiff) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_ABSDIFF(v_float64x2, absdiff) -#endif -OPENCV_HAL_IMPL_RVV_ABSDIFF(v_int8x16, absdiffs) -OPENCV_HAL_IMPL_RVV_ABSDIFF(v_int16x8, absdiffs) - -#define OPENCV_HAL_IMPL_RVV_ABSDIFF_S(ivec, uvec, itype, utype, isuf, usuf, vlen) \ -inline uvec v_absdiff(const ivec& a, const ivec& b) \ -{ \ - itype max = vmax_vv_##isuf(a, b, vlen); \ - itype min = vmin_vv_##isuf(a, b, vlen); \ - return uvec(vreinterpret_v_##isuf##_##usuf(vsub_vv_##isuf(max, min, vlen))); \ -} - -OPENCV_HAL_IMPL_RVV_ABSDIFF_S(v_int8x16, v_uint8x16, vint8m1_t, vuint8m1_t, i8m1, u8m1, 16) -OPENCV_HAL_IMPL_RVV_ABSDIFF_S(v_int16x8, v_uint16x8, vint16m1_t, vuint16m1_t, i16m1, u16m1, 8) -OPENCV_HAL_IMPL_RVV_ABSDIFF_S(v_int32x4, v_uint32x4, vint32m1_t, vuint32m1_t, i32m1, u32m1, 4) - -#define OPENCV_HAL_IMPL_RVV_ABS(_Tprvec, _Tpvec, suffix) \ -inline _Tprvec v_abs(const _Tpvec& a) \ -{ \ - return v_absdiff(a, v_setzero_##suffix()); \ -} - -OPENCV_HAL_IMPL_RVV_ABS(v_uint8x16, v_int8x16, s8) -OPENCV_HAL_IMPL_RVV_ABS(v_uint16x8, v_int16x8, s16) -OPENCV_HAL_IMPL_RVV_ABS(v_uint32x4, v_int32x4, s32) -OPENCV_HAL_IMPL_RVV_ABS(v_float32x4, v_float32x4, f32) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_ABS(v_float64x2, v_float64x2, f64) -#endif - - -#define OPENCV_HAL_IMPL_RVV_REDUCE_SAD(_Tpvec, scalartype) \ -inline scalartype v_reduce_sad(const _Tpvec& a, const _Tpvec& b) \ -{ \ - return v_reduce_sum(v_absdiff(a, b)); \ -} - -OPENCV_HAL_IMPL_RVV_REDUCE_SAD(v_uint8x16, unsigned) -OPENCV_HAL_IMPL_RVV_REDUCE_SAD(v_int8x16, unsigned) -OPENCV_HAL_IMPL_RVV_REDUCE_SAD(v_uint16x8, unsigned) -OPENCV_HAL_IMPL_RVV_REDUCE_SAD(v_int16x8, unsigned) -OPENCV_HAL_IMPL_RVV_REDUCE_SAD(v_uint32x4, unsigned) -OPENCV_HAL_IMPL_RVV_REDUCE_SAD(v_int32x4, unsigned) -OPENCV_HAL_IMPL_RVV_REDUCE_SAD(v_float32x4, float) - -////////////// Select ////////////// - -#define OPENCV_HAL_IMPL_RVV_SELECT(_Tpvec, merge, ne, vl) \ -inline _Tpvec v_select(const _Tpvec& mask, const _Tpvec& a, const _Tpvec& b) \ -{ \ - return _Tpvec(merge(ne(mask, 0, vl), b, a, vl)); \ -} - -OPENCV_HAL_IMPL_RVV_SELECT(v_uint8x16, vmerge_vvm_u8m1, vmsne_vx_u8m1_b8, 16) -OPENCV_HAL_IMPL_RVV_SELECT(v_int8x16, vmerge_vvm_i8m1, vmsne_vx_i8m1_b8, 16) -OPENCV_HAL_IMPL_RVV_SELECT(v_uint16x8, vmerge_vvm_u16m1, vmsne_vx_u16m1_b16, 8) -OPENCV_HAL_IMPL_RVV_SELECT(v_int16x8, vmerge_vvm_i16m1, vmsne_vx_i16m1_b16, 8) -OPENCV_HAL_IMPL_RVV_SELECT(v_uint32x4, vmerge_vvm_u32m1, vmsne_vx_u32m1_b32, 4) -OPENCV_HAL_IMPL_RVV_SELECT(v_int32x4, vmerge_vvm_i32m1, vmsne_vx_i32m1_b32, 4) -OPENCV_HAL_IMPL_RVV_SELECT(v_float32x4, vmerge_vvm_f32m1, vmfne_vf_f32m1_b32, 4) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_SELECT(v_float64x2, vmerge_vvm_f64m1, vmfne_vf_f64m1_b64, 2) -#endif - -////////////// Rotate shift ////////////// - -#define OPENCV_HAL_IMPL_RVV_ROTATE_INTEGER(_Tpvec, suffix, vl) \ -template inline _Tpvec v_rotate_right(const _Tpvec& a) \ -{ \ - return _Tpvec(vslidedown_vx_##suffix##m1(vmv_v_x_##suffix##m1(0, vl), a, n, vl)); \ -} \ -template inline _Tpvec v_rotate_left(const _Tpvec& a) \ -{ \ - return _Tpvec(vslideup_vx_##suffix##m1(vmv_v_x_##suffix##m1(0, vl), a, n, vl)); \ -} \ -template<> inline _Tpvec v_rotate_left<0>(const _Tpvec& a) \ -{ return a; } \ -template inline _Tpvec v_rotate_right(const _Tpvec& a, const _Tpvec& b) \ -{ \ - return _Tpvec(vslideup_vx_##suffix##m1(vslidedown_vx_##suffix##m1(vmv_v_x_##suffix##m1(0, vl), a, n, vl), b, _Tpvec::nlanes - n, vl)); \ -} \ -template inline _Tpvec v_rotate_left(const _Tpvec& a, const _Tpvec& b) \ -{ \ - return _Tpvec(vslideup_vx_##suffix##m1(vslidedown_vx_##suffix##m1(vmv_v_x_##suffix##m1(0, vl), b, _Tpvec::nlanes - n, vl), a, n, vl)); \ -} \ -template<> inline _Tpvec v_rotate_left<0>(const _Tpvec& a, const _Tpvec& b) \ -{ CV_UNUSED(b); return a; } - -OPENCV_HAL_IMPL_RVV_ROTATE_INTEGER(v_uint8x16, u8, 16) -OPENCV_HAL_IMPL_RVV_ROTATE_INTEGER(v_int8x16, i8, 16) -OPENCV_HAL_IMPL_RVV_ROTATE_INTEGER(v_uint16x8, u16, 8) -OPENCV_HAL_IMPL_RVV_ROTATE_INTEGER(v_int16x8, i16, 8) -OPENCV_HAL_IMPL_RVV_ROTATE_INTEGER(v_uint32x4, u32, 4) -OPENCV_HAL_IMPL_RVV_ROTATE_INTEGER(v_int32x4, i32, 4) -OPENCV_HAL_IMPL_RVV_ROTATE_INTEGER(v_uint64x2, u64, 2) -OPENCV_HAL_IMPL_RVV_ROTATE_INTEGER(v_int64x2, i64, 2) - -#define OPENCV_HAL_IMPL_RVV_ROTATE_FP(_Tpvec, suffix, vl) \ -template inline _Tpvec v_rotate_right(const _Tpvec& a) \ -{ \ - return _Tpvec(vslidedown_vx_##suffix##m1(vfmv_v_f_##suffix##m1(0, vl), a, n, vl)); \ -} \ -template inline _Tpvec v_rotate_left(const _Tpvec& a) \ -{ \ - return _Tpvec(vslideup_vx_##suffix##m1(vfmv_v_f_##suffix##m1(0, vl), a, n, vl)); \ -} \ -template<> inline _Tpvec v_rotate_left<0>(const _Tpvec& a) \ -{ return a; } \ -template inline _Tpvec v_rotate_right(const _Tpvec& a, const _Tpvec& b) \ -{ \ - return _Tpvec(vslideup_vx_##suffix##m1(vslidedown_vx_##suffix##m1(vfmv_v_f_##suffix##m1(0, vl), a, n, vl), b, _Tpvec::nlanes - n, vl)); \ -} \ -template inline _Tpvec v_rotate_left(const _Tpvec& a, const _Tpvec& b) \ -{ \ - return _Tpvec(vslideup_vx_##suffix##m1(vslidedown_vx_##suffix##m1(vfmv_v_f_##suffix##m1(0, vl), b, _Tpvec::nlanes - n, vl), a, n, vl)); \ -} \ -template<> inline _Tpvec v_rotate_left<0>(const _Tpvec& a, const _Tpvec& b) \ -{ CV_UNUSED(b); return a; } - -OPENCV_HAL_IMPL_RVV_ROTATE_FP(v_float32x4, f32, 4) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_ROTATE_FP(v_float64x2, f64, 2) -#endif - -////////////// Convert to float ////////////// - -inline v_float32x4 v_cvt_f32(const v_int32x4& a) -{ - return v_float32x4(vfcvt_f_x_v_f32m1(a, 4)); -} - -#if CV_SIMD128_64F -#ifndef __clang__ -inline v_float32x4 v_cvt_f32(const v_float64x2& a) -{ - double arr[4] = {a.val[0], a.val[1], 0, 0}; - vfloat64m2_t tmp = vle64_v_f64m2(arr, 4); - return v_float32x4(vfncvt_f_f_w_f32m1(tmp, 4)); -} - -inline v_float32x4 v_cvt_f32(const v_float64x2& a, const v_float64x2& b) -{ - double arr[4] = {a.val[0], a.val[1], b.val[0], b.val[1]}; - vfloat64m2_t tmp = vle64_v_f64m2(arr, 4); - return v_float32x4(vfncvt_f_f_w_f32m1(tmp, 4)); -} -#else -inline v_float32x4 v_cvt_f32(const v_float64x2& a) -{ - vfloat64m2_t zero = vfmv_v_f_f64m2(0, 4); - return v_float32x4(vfncvt_f_f_w_f32m1(vset_v_f64m1_f64m2(zero, 0, a), 4)); -} -inline v_float32x4 v_cvt_f32(const v_float64x2& a, const v_float64x2& b) -{ - vfloat64m2_t dst = vlmul_ext_v_f64m1_f64m2(a); - return v_float32x4(vfncvt_f_f_w_f32m1(vset_v_f64m1_f64m2(dst, 1, b), 4)); -} -#endif - -inline v_float64x2 v_cvt_f64(const v_int32x4& a) -{ - double ptr[4] = {0}; - vse64_v_f64m2(ptr, vfwcvt_f_x_v_f64m2(a, 4), 4); - double elems[2] = - { - ptr[0], ptr[1] - }; - return v_float64x2(vle64_v_f64m1(elems, 2)); -} - -inline v_float64x2 v_cvt_f64_high(const v_int32x4& a) -{ - double ptr[4] = {0}; - vse64_v_f64m2(ptr, vfwcvt_f_x_v_f64m2(a, 4), 4); - double elems[2] = - { - ptr[2], ptr[3] - }; - return v_float64x2(vle64_v_f64m1(elems, 2)); -} - -inline v_float64x2 v_cvt_f64(const v_float32x4& a) -{ - double ptr[4] = {0}; - vse64_v_f64m2(ptr, vfwcvt_f_f_v_f64m2(a, 4), 4); - double elems[2] = - { - ptr[0], ptr[1] - }; - return v_float64x2(vle64_v_f64m1(elems, 2)); -} - -inline v_float64x2 v_cvt_f64_high(const v_float32x4& a) -{ - double ptr[4] = {0}; - vse64_v_f64m2(ptr, vfwcvt_f_f_v_f64m2(a, 4), 4); - double elems[2] = - { - ptr[2], ptr[3] - }; - return v_float64x2(vle64_v_f64m1(elems, 2)); -} - -inline v_float64x2 v_cvt_f64(const v_int64x2& a) -{ - return v_float64x2(vfcvt_f_x_v_f64m1(a, 2)); -} -#endif - -////////////// Broadcast ////////////// - -#define OPENCV_HAL_IMPL_RVV_BROADCAST(_Tpvec, suffix) \ -template inline _Tpvec v_broadcast_element(_Tpvec v) \ -{ \ - return v_setall_##suffix(v_extract_n(v)); \ -} - -OPENCV_HAL_IMPL_RVV_BROADCAST(v_uint8x16, u8) -OPENCV_HAL_IMPL_RVV_BROADCAST(v_int8x16, s8) -OPENCV_HAL_IMPL_RVV_BROADCAST(v_uint16x8, u16) -OPENCV_HAL_IMPL_RVV_BROADCAST(v_int16x8, s16) -OPENCV_HAL_IMPL_RVV_BROADCAST(v_uint32x4, u32) -OPENCV_HAL_IMPL_RVV_BROADCAST(v_int32x4, s32) -OPENCV_HAL_IMPL_RVV_BROADCAST(v_uint64x2, u64) -OPENCV_HAL_IMPL_RVV_BROADCAST(v_int64x2, s64) -OPENCV_HAL_IMPL_RVV_BROADCAST(v_float32x4, f32) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_BROADCAST(v_float64x2, f64) -#endif - -////////////// Transpose4x4 ////////////// - -#define OPENCV_HAL_IMPL_RVV_TRANSPOSE4x4(_Tpvec, _Tp, suffix) \ -inline void v_transpose4x4(const v_##_Tpvec& a0, const v_##_Tpvec& a1, \ - const v_##_Tpvec& a2, const v_##_Tpvec& a3, \ - v_##_Tpvec& b0, v_##_Tpvec& b1, \ - v_##_Tpvec& b2, v_##_Tpvec& b3) \ -{ \ - _Tp elems0[4] = \ - { \ - v_extract_n<0>(a0), \ - v_extract_n<0>(a1), \ - v_extract_n<0>(a2), \ - v_extract_n<0>(a3) \ - }; \ - b0 = v_load(elems0); \ - _Tp elems1[4] = \ - { \ - v_extract_n<1>(a0), \ - v_extract_n<1>(a1), \ - v_extract_n<1>(a2), \ - v_extract_n<1>(a3) \ - }; \ - b1 = v_load(elems1); \ - _Tp elems2[4] = \ - { \ - v_extract_n<2>(a0), \ - v_extract_n<2>(a1), \ - v_extract_n<2>(a2), \ - v_extract_n<2>(a3) \ - }; \ - b2 = v_load(elems2); \ - _Tp elems3[4] = \ - { \ - v_extract_n<3>(a0), \ - v_extract_n<3>(a1), \ - v_extract_n<3>(a2), \ - v_extract_n<3>(a3) \ - }; \ - b3 = v_load(elems3); \ -} - -OPENCV_HAL_IMPL_RVV_TRANSPOSE4x4(uint32x4, unsigned, u32) -OPENCV_HAL_IMPL_RVV_TRANSPOSE4x4(int32x4, int, i32) -OPENCV_HAL_IMPL_RVV_TRANSPOSE4x4(float32x4, float, f32) - -////////////// Reverse ////////////// - -#define OPENCV_HAL_IMPL_RVV_REVERSE(_Tpvec, _Tp, suffix) \ -inline _Tpvec v_reverse(const _Tpvec& a) \ -{ \ - _Tp ptr[_Tpvec::nlanes] = {0}; \ - _Tp ptra[_Tpvec::nlanes] = {0}; \ - v_store(ptra, a); \ - for (int i = 0; i < _Tpvec::nlanes; i++) \ - { \ - ptr[i] = ptra[_Tpvec::nlanes-i-1]; \ - } \ - return v_load(ptr); \ -} - -OPENCV_HAL_IMPL_RVV_REVERSE(v_uint8x16, uchar, u8) -OPENCV_HAL_IMPL_RVV_REVERSE(v_int8x16, schar, i8) -OPENCV_HAL_IMPL_RVV_REVERSE(v_uint16x8, ushort, u16) -OPENCV_HAL_IMPL_RVV_REVERSE(v_int16x8, short, i16) -OPENCV_HAL_IMPL_RVV_REVERSE(v_uint32x4, unsigned, u32) -OPENCV_HAL_IMPL_RVV_REVERSE(v_int32x4, int, i32) -OPENCV_HAL_IMPL_RVV_REVERSE(v_float32x4, float, f32) -OPENCV_HAL_IMPL_RVV_REVERSE(v_uint64x2, uint64, u64) -OPENCV_HAL_IMPL_RVV_REVERSE(v_int64x2, int64, i64) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_REVERSE(v_float64x2, double, f64) -#endif - -//////////// Value reordering //////////// - -#define OPENCV_HAL_IMPL_RVV_EXPAND(_Tpwvec, _Tp, _Tpvec, width, suffix, wcvt, vl) \ -inline void v_expand(const _Tpvec& a, _Tpwvec& b0, _Tpwvec& b1) \ -{ \ - _Tp lptr[_Tpvec::nlanes/2] = {0}; \ - _Tp hptr[_Tpvec::nlanes/2] = {0}; \ - v_store_low(lptr, a); \ - v_store_high(hptr, a); \ - b0 = _Tpwvec(wcvt(vle##width##_v_##suffix##mf2(lptr, vl), vl)); \ - b1 = _Tpwvec(wcvt(vle##width##_v_##suffix##mf2(hptr, vl), vl)); \ -} \ -inline _Tpwvec v_expand_low(const _Tpvec& a) \ -{ \ - _Tp lptr[_Tpvec::nlanes/2] = {0}; \ - v_store_low(lptr, a); \ - return _Tpwvec(wcvt(vle##width##_v_##suffix##mf2(lptr, vl), vl)); \ -} \ -inline _Tpwvec v_expand_high(const _Tpvec& a) \ -{ \ - _Tp hptr[_Tpvec::nlanes/2] = {0}; \ - v_store_high(hptr, a); \ - return _Tpwvec(wcvt(vle##width##_v_##suffix##mf2(hptr, vl), vl)); \ -} \ -inline _Tpwvec v_load_expand(const _Tp* ptr) \ -{ \ - return _Tpwvec(wcvt(vle##width##_v_##suffix##mf2(ptr, vl), vl)); \ -} - -OPENCV_HAL_IMPL_RVV_EXPAND(v_uint16x8, uchar, v_uint8x16, 8, u8, vwcvtu_x_x_v_u16m1, 8) -OPENCV_HAL_IMPL_RVV_EXPAND(v_int16x8, schar, v_int8x16, 8, i8, vwcvt_x_x_v_i16m1, 8) -OPENCV_HAL_IMPL_RVV_EXPAND(v_uint32x4, ushort, v_uint16x8, 16, u16, vwcvtu_x_x_v_u32m1, 4) -OPENCV_HAL_IMPL_RVV_EXPAND(v_int32x4, short, v_int16x8, 16, i16, vwcvt_x_x_v_i32m1, 4) -OPENCV_HAL_IMPL_RVV_EXPAND(v_uint64x2, uint, v_uint32x4, 32, u32, vwcvtu_x_x_v_u64m1, 2) -OPENCV_HAL_IMPL_RVV_EXPAND(v_int64x2, int, v_int32x4, 32, i32, vwcvt_x_x_v_i64m1, 2) - -inline v_uint32x4 v_load_expand_q(const uchar* ptr) -{ - return v_uint32x4(vwcvtu_x_x_v_u32m1(vwcvtu_x_x_v_u16mf2(vle8_v_u8mf4(ptr, 4), 4), 4)); -} - -inline v_int32x4 v_load_expand_q(const schar* ptr) -{ - return v_int32x4(vwcvt_x_x_v_i32m1(vwcvt_x_x_v_i16mf2(vle8_v_i8mf4(ptr, 4), 4), 4)); -} - - -#define OPENCV_HAL_IMPL_RVV_PACK(_Tpvec, _Tp, _wTpvec, _wTp, hwidth, width, hsuffix, suffix, rshr, shr, hvl, vl) \ -inline _Tpvec v_pack(const _wTpvec& a, const _wTpvec& b) \ -{ \ - _wTp arr[_Tpvec::nlanes] = {0}; \ - v_store(arr, a); \ - v_store(arr + _wTpvec::nlanes, b); \ - return _Tpvec(shr(vle##width##_v_##suffix##m2(arr, vl), 0, vl)); \ -} \ -inline void v_pack_store(_Tp* ptr, const _wTpvec& a) \ -{ \ - _wTp arr[_Tpvec::nlanes] = {0}; \ - v_store(arr, a); \ - v_store(arr + _wTpvec::nlanes, _wTpvec(vmv_v_x_##suffix##m1(0, hvl))); \ - vse##hwidth##_v_##hsuffix##m1(ptr, shr(vle##width##_v_##suffix##m2(arr, vl), 0, vl), hvl); \ -} \ -template inline \ -_Tpvec v_rshr_pack(const _wTpvec& a, const _wTpvec& b) \ -{ \ - _wTp arr[_Tpvec::nlanes] = {0}; \ - v_store(arr, a); \ - v_store(arr + _wTpvec::nlanes, b); \ - return _Tpvec(rshr(vle##width##_v_##suffix##m2(arr, vl), n, vl)); \ -} \ -template inline \ -void v_rshr_pack_store(_Tp* ptr, const _wTpvec& a) \ -{ \ - _wTp arr[_Tpvec::nlanes] = {0}; \ - v_store(arr, a); \ - v_store(arr + _wTpvec::nlanes, _wTpvec(vmv_v_x_##suffix##m1(0, hvl))); \ - vse##hwidth##_v_##hsuffix##m1(ptr, _Tpvec(rshr(vle##width##_v_##suffix##m2(arr, vl), n, vl)), hvl); \ -} - -OPENCV_HAL_IMPL_RVV_PACK(v_uint8x16, uchar, v_uint16x8, ushort, 8, 16, u8, u16, vnclipu_wx_u8m1, vnclipu_wx_u8m1, 8, 16) -OPENCV_HAL_IMPL_RVV_PACK(v_int8x16, schar, v_int16x8, short, 8, 16, i8, i16, vnclip_wx_i8m1, vnclip_wx_i8m1, 8, 16) -OPENCV_HAL_IMPL_RVV_PACK(v_uint16x8, ushort, v_uint32x4, unsigned, 16, 32, u16, u32, vnclipu_wx_u16m1, vnclipu_wx_u16m1, 4, 8) -OPENCV_HAL_IMPL_RVV_PACK(v_int16x8, short, v_int32x4, int, 16, 32, i16, i32, vnclip_wx_i16m1, vnclip_wx_i16m1, 4, 8) -OPENCV_HAL_IMPL_RVV_PACK(v_uint32x4, unsigned, v_uint64x2, uint64, 32, 64, u32, u64, vnclipu_wx_u32m1, vnsrl_wx_u32m1, 2, 4) -OPENCV_HAL_IMPL_RVV_PACK(v_int32x4, int, v_int64x2, int64, 32, 64, i32, i64, vnclip_wx_i32m1, vnsra_wx_i32m1, 2, 4) - - -#define OPENCV_HAL_IMPL_RVV_PACK_U(_Tpvec, _Tp, _wTpvec, _wTp, hwidth, width, hsuffix, suffix, rshr, cast, hvl, vl) \ -inline _Tpvec v_pack_u(const _wTpvec& a, const _wTpvec& b) \ -{ \ - _wTp arr[_Tpvec::nlanes] = {0}; \ - v_store(arr, a); \ - v_store(arr + _wTpvec::nlanes, b); \ - return _Tpvec(rshr(cast(vmax_vx_##suffix##m2(vle##width##_v_##suffix##m2(arr, vl), 0, vl)), 0, vl)); \ -} \ -inline void v_pack_u_store(_Tp* ptr, const _wTpvec& a) \ -{ \ - _wTp arr[_Tpvec::nlanes] = {0}; \ - v_store(arr, a); \ - v_store(arr + _wTpvec::nlanes, _wTpvec(vmv_v_x_##suffix##m1(0, hvl))); \ - vse##hwidth##_v_##hsuffix##m1(ptr, rshr(cast(vmax_vx_##suffix##m2(vle##width##_v_##suffix##m2(arr, vl), 0, vl)), 0, vl), hvl); \ -} \ -template inline \ -_Tpvec v_rshr_pack_u(const _wTpvec& a, const _wTpvec& b) \ -{ \ - _wTp arr[_Tpvec::nlanes] = {0}; \ - v_store(arr, a); \ - v_store(arr + _wTpvec::nlanes, b); \ - return _Tpvec(rshr(cast(vmax_vx_##suffix##m2(vle##width##_v_##suffix##m2(arr, vl), 0, vl)), n, vl)); \ -} \ -template inline \ -void v_rshr_pack_u_store(_Tp* ptr, const _wTpvec& a) \ -{ \ - _wTp arr[_Tpvec::nlanes] = {0}; \ - v_store(arr, a); \ - v_store(arr + _wTpvec::nlanes, _wTpvec(vmv_v_x_##suffix##m1(0, hvl))); \ - v_store(ptr, _Tpvec(rshr(cast(vmax_vx_##suffix##m2(vle##width##_v_##suffix##m2(arr, vl), 0, vl)), n, vl))); \ -} - -OPENCV_HAL_IMPL_RVV_PACK_U(v_uint8x16, uchar, v_int16x8, short, 8, 16, u8, i16, vnclipu_wx_u8m1, vreinterpret_v_i16m2_u16m2, 8, 16) -OPENCV_HAL_IMPL_RVV_PACK_U(v_uint16x8, ushort, v_int32x4, int, 16, 32, u16, i32, vnclipu_wx_u16m1, vreinterpret_v_i32m2_u32m2, 4, 8) - - -#define OPENCV_HAL_IMPL_RVV_UNPACKS(_Tpvec, _Tp, suffix) \ -inline void v_zip(const v_##_Tpvec& a0, const v_##_Tpvec& a1, v_##_Tpvec& b0, v_##_Tpvec& b1) \ -{ \ - _Tp ptra0[v_##_Tpvec::nlanes] = {0}; \ - _Tp ptra1[v_##_Tpvec::nlanes] = {0}; \ - _Tp ptrb0[v_##_Tpvec::nlanes] = {0}; \ - _Tp ptrb1[v_##_Tpvec::nlanes] = {0}; \ - v_store(ptra0, a0); \ - v_store(ptra1, a1); \ - int i; \ - for( i = 0; i < v_##_Tpvec::nlanes/2; i++ ) \ - { \ - ptrb0[i*2] = ptra0[i]; \ - ptrb0[i*2+1] = ptra1[i]; \ - } \ - for( ; i < v_##_Tpvec::nlanes; i++ ) \ - { \ - ptrb1[i*2-v_##_Tpvec::nlanes] = ptra0[i]; \ - ptrb1[i*2-v_##_Tpvec::nlanes+1] = ptra1[i]; \ - } \ - b0 = v_load(ptrb0); \ - b1 = v_load(ptrb1); \ -} \ -inline v_##_Tpvec v_combine_low(const v_##_Tpvec& a, const v_##_Tpvec& b) \ -{ \ - _Tp ptra[v_##_Tpvec::nlanes/2] = {0}; \ - _Tp ptrb[v_##_Tpvec::nlanes/2] = {0}; \ - v_store_low(ptra, a); \ - v_store_low(ptrb, b); \ - return v_load_halves(ptra, ptrb); \ -} \ -inline v_##_Tpvec v_combine_high(const v_##_Tpvec& a, const v_##_Tpvec& b) \ -{ \ - _Tp ptra[v_##_Tpvec::nlanes/2] = {0}; \ - _Tp ptrb[v_##_Tpvec::nlanes/2] = {0}; \ - v_store_high(ptra, a); \ - v_store_high(ptrb, b); \ - return v_load_halves(ptra, ptrb); \ -} \ -inline void v_recombine(const v_##_Tpvec& a, const v_##_Tpvec& b, v_##_Tpvec& c, v_##_Tpvec& d) \ -{ \ - c = v_combine_low(a, b); \ - d = v_combine_high(a, b); \ -} - -OPENCV_HAL_IMPL_RVV_UNPACKS(uint8x16, uchar, u8) -OPENCV_HAL_IMPL_RVV_UNPACKS(int8x16, schar, i8) -OPENCV_HAL_IMPL_RVV_UNPACKS(uint16x8, ushort, u16) -OPENCV_HAL_IMPL_RVV_UNPACKS(int16x8, short, i16) -OPENCV_HAL_IMPL_RVV_UNPACKS(uint32x4, unsigned, u32) -OPENCV_HAL_IMPL_RVV_UNPACKS(int32x4, int, i32) -OPENCV_HAL_IMPL_RVV_UNPACKS(float32x4, float, f32) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_UNPACKS(float64x2, double, f64) -#endif - - -#define OPENCV_HAL_IMPL_RVV_INTERLEAVED(_Tpvec, _Tp) \ -inline void v_load_deinterleave(const _Tp* ptr, v_##_Tpvec& a, v_##_Tpvec& b) \ -{ \ - _Tp ptra[v_##_Tpvec::nlanes] = {0}; \ - _Tp ptrb[v_##_Tpvec::nlanes] = {0}; \ - int i, i2; \ - for( i = i2 = 0; i < v_##_Tpvec::nlanes; i++, i2 += 2 ) \ - { \ - ptra[i] = ptr[i2]; \ - ptrb[i] = ptr[i2+1]; \ - } \ - a = v_load(ptra); \ - b = v_load(ptrb); \ -} \ -inline void v_load_deinterleave(const _Tp* ptr, v_##_Tpvec& a, v_##_Tpvec& b, v_##_Tpvec& c) \ -{ \ - _Tp ptra[v_##_Tpvec::nlanes] = {0}; \ - _Tp ptrb[v_##_Tpvec::nlanes] = {0}; \ - _Tp ptrc[v_##_Tpvec::nlanes] = {0}; \ - int i, i3; \ - for( i = i3 = 0; i < v_##_Tpvec::nlanes; i++, i3 += 3 ) \ - { \ - ptra[i] = ptr[i3]; \ - ptrb[i] = ptr[i3+1]; \ - ptrc[i] = ptr[i3+2]; \ - } \ - a = v_load(ptra); \ - b = v_load(ptrb); \ - c = v_load(ptrc); \ -} \ -inline void v_load_deinterleave(const _Tp* ptr, v_##_Tpvec& a, v_##_Tpvec& b, \ - v_##_Tpvec& c, v_##_Tpvec& d) \ -{ \ - _Tp ptra[v_##_Tpvec::nlanes] = {0}; \ - _Tp ptrb[v_##_Tpvec::nlanes] = {0}; \ - _Tp ptrc[v_##_Tpvec::nlanes] = {0}; \ - _Tp ptrd[v_##_Tpvec::nlanes] = {0}; \ - int i, i4; \ - for( i = i4 = 0; i < v_##_Tpvec::nlanes; i++, i4 += 4 ) \ - { \ - ptra[i] = ptr[i4]; \ - ptrb[i] = ptr[i4+1]; \ - ptrc[i] = ptr[i4+2]; \ - ptrd[i] = ptr[i4+3]; \ - } \ - a = v_load(ptra); \ - b = v_load(ptrb); \ - c = v_load(ptrc); \ - d = v_load(ptrd); \ -} \ -inline void v_store_interleave( _Tp* ptr, const v_##_Tpvec& a, const v_##_Tpvec& b, \ - hal::StoreMode /*mode*/=hal::STORE_UNALIGNED) \ -{ \ - int i, i2; \ - _Tp ptra[v_##_Tpvec::nlanes] = {0}; \ - _Tp ptrb[v_##_Tpvec::nlanes] = {0}; \ - v_store(ptra, a); \ - v_store(ptrb, b); \ - for( i = i2 = 0; i < v_##_Tpvec::nlanes; i++, i2 += 2 ) \ - { \ - ptr[i2] = ptra[i]; \ - ptr[i2+1] = ptrb[i]; \ - } \ -} \ -inline void v_store_interleave( _Tp* ptr, const v_##_Tpvec& a, const v_##_Tpvec& b, \ - const v_##_Tpvec& c, hal::StoreMode /*mode*/=hal::STORE_UNALIGNED) \ -{ \ - int i, i3; \ - _Tp ptra[v_##_Tpvec::nlanes] = {0}; \ - _Tp ptrb[v_##_Tpvec::nlanes] = {0}; \ - _Tp ptrc[v_##_Tpvec::nlanes] = {0}; \ - v_store(ptra, a); \ - v_store(ptrb, b); \ - v_store(ptrc, c); \ - for( i = i3 = 0; i < v_##_Tpvec::nlanes; i++, i3 += 3 ) \ - { \ - ptr[i3] = ptra[i]; \ - ptr[i3+1] = ptrb[i]; \ - ptr[i3+2] = ptrc[i]; \ - } \ -} \ -inline void v_store_interleave( _Tp* ptr, const v_##_Tpvec& a, const v_##_Tpvec& b, \ - const v_##_Tpvec& c, const v_##_Tpvec& d, \ - hal::StoreMode /*mode*/=hal::STORE_UNALIGNED ) \ -{ \ - int i, i4; \ - _Tp ptra[v_##_Tpvec::nlanes] = {0}; \ - _Tp ptrb[v_##_Tpvec::nlanes] = {0}; \ - _Tp ptrc[v_##_Tpvec::nlanes] = {0}; \ - _Tp ptrd[v_##_Tpvec::nlanes] = {0}; \ - v_store(ptra, a); \ - v_store(ptrb, b); \ - v_store(ptrc, c); \ - v_store(ptrd, d); \ - for( i = i4 = 0; i < v_##_Tpvec::nlanes; i++, i4 += 4 ) \ - { \ - ptr[i4] = ptra[i]; \ - ptr[i4+1] = ptrb[i]; \ - ptr[i4+2] = ptrc[i]; \ - ptr[i4+3] = ptrd[i]; \ - } \ -} \ -inline v_##_Tpvec v_interleave_pairs(const v_##_Tpvec& vec) \ -{ \ - _Tp ptr[v_##_Tpvec::nlanes] = {0}; \ - _Tp ptrvec[v_##_Tpvec::nlanes] = {0}; \ - v_store(ptrvec, vec); \ - for (int i = 0; i < v_##_Tpvec::nlanes/4; i++) \ - { \ - ptr[4*i ] = ptrvec[4*i ]; \ - ptr[4*i+1] = ptrvec[4*i+2]; \ - ptr[4*i+2] = ptrvec[4*i+1]; \ - ptr[4*i+3] = ptrvec[4*i+3]; \ - } \ - return v_load(ptr); \ -} \ -inline v_##_Tpvec v_interleave_quads(const v_##_Tpvec& vec) \ -{ \ - _Tp ptr[v_##_Tpvec::nlanes] = {0}; \ - _Tp ptrvec[v_##_Tpvec::nlanes] = {0}; \ - v_store(ptrvec, vec); \ - for (int i = 0; i < v_##_Tpvec::nlanes/8; i++) \ - { \ - ptr[8*i ] = ptrvec[8*i ]; \ - ptr[8*i+1] = ptrvec[8*i+4]; \ - ptr[8*i+2] = ptrvec[8*i+1]; \ - ptr[8*i+3] = ptrvec[8*i+5]; \ - ptr[8*i+4] = ptrvec[8*i+2]; \ - ptr[8*i+5] = ptrvec[8*i+6]; \ - ptr[8*i+6] = ptrvec[8*i+3]; \ - ptr[8*i+7] = ptrvec[8*i+7]; \ - } \ - return v_load(ptr); \ -} - -OPENCV_HAL_IMPL_RVV_INTERLEAVED(uint8x16, uchar) -OPENCV_HAL_IMPL_RVV_INTERLEAVED(int8x16, schar) -OPENCV_HAL_IMPL_RVV_INTERLEAVED(uint16x8, ushort) -OPENCV_HAL_IMPL_RVV_INTERLEAVED(int16x8, short) -OPENCV_HAL_IMPL_RVV_INTERLEAVED(uint32x4, unsigned) -OPENCV_HAL_IMPL_RVV_INTERLEAVED(int32x4, int) -OPENCV_HAL_IMPL_RVV_INTERLEAVED(float32x4, float) -OPENCV_HAL_IMPL_RVV_INTERLEAVED(uint64x2, uint64) -OPENCV_HAL_IMPL_RVV_INTERLEAVED(int64x2, int64) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_INTERLEAVED(float64x2, double) -#endif - -//////////// PopCount //////////// - -static const unsigned char popCountTable[] = -{ - 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, - 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, - 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, - 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, - 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, - 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, - 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, - 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, - 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, - 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, - 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, - 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, - 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, - 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, - 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, - 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8, -}; - -#define OPENCV_HAL_IMPL_RVV_POPCOUNT_OP(_rTpvec, _Tpvec, _rTp, _Tp, suffix) \ -inline _rTpvec v_popcount(const _Tpvec& a) \ -{ \ - uchar ptra[16] = {0}; \ - v_store(ptra, v_reinterpret_as_u8(a)); \ - _rTp ptr[_Tpvec::nlanes] = {0}; \ - v_store(ptr, v_setzero_##suffix()); \ - for (int i = 0; i < _Tpvec::nlanes*(int)sizeof(_Tp); i++) \ - ptr[i/sizeof(_Tp)] += popCountTable[ptra[i]]; \ - return v_load(ptr); \ -} - -OPENCV_HAL_IMPL_RVV_POPCOUNT_OP(v_uint8x16, v_uint8x16, uchar, uchar, u8) -OPENCV_HAL_IMPL_RVV_POPCOUNT_OP(v_uint8x16, v_int8x16, uchar, schar, u8) -OPENCV_HAL_IMPL_RVV_POPCOUNT_OP(v_uint16x8, v_uint16x8, ushort, ushort, u16) -OPENCV_HAL_IMPL_RVV_POPCOUNT_OP(v_uint16x8, v_int16x8, ushort, short, u16) -OPENCV_HAL_IMPL_RVV_POPCOUNT_OP(v_uint32x4, v_uint32x4, unsigned, unsigned, u32) -OPENCV_HAL_IMPL_RVV_POPCOUNT_OP(v_uint32x4, v_int32x4, unsigned, int, u32) -OPENCV_HAL_IMPL_RVV_POPCOUNT_OP(v_uint64x2, v_uint64x2, uint64, uint64, u64) -OPENCV_HAL_IMPL_RVV_POPCOUNT_OP(v_uint64x2, v_int64x2, uint64, int64, u64) - -//////////// SignMask //////////// - -#ifndef __clang__ -#define OPENCV_HAL_IMPL_RVV_SIGNMASK_OP(_Tpvec, _Tp, suffix, vl, shift) \ -inline int v_signmask(const _Tpvec& a) \ -{ \ - int mask = 0; \ - _Tpvec tmp = _Tpvec(vsrl_vx_##suffix##m1(a, shift, vl)); \ - for( int i = 0; i < _Tpvec::nlanes; i++ ) \ - mask |= (int)(tmp.val[i]) << i; \ - return mask; \ -} - -OPENCV_HAL_IMPL_RVV_SIGNMASK_OP(v_uint8x16, uchar, u8, 16, 7) -OPENCV_HAL_IMPL_RVV_SIGNMASK_OP(v_uint16x8, ushort, u16, 8, 15) -OPENCV_HAL_IMPL_RVV_SIGNMASK_OP(v_uint32x4, unsigned, u32, 4, 31) -OPENCV_HAL_IMPL_RVV_SIGNMASK_OP(v_uint64x2, uint64, u64, 2, 63) - -inline int v_signmask(const v_int8x16& a) -{ return v_signmask(v_reinterpret_as_u8(a)); } -inline int v_signmask(const v_int16x8& a) -{ return v_signmask(v_reinterpret_as_u16(a)); } -inline int v_signmask(const v_int32x4& a) -{ return v_signmask(v_reinterpret_as_u32(a)); } -inline int v_signmask(const v_float32x4& a) -{ return v_signmask(v_reinterpret_as_u32(a)); } -inline int v_signmask(const v_int64x2& a) -{ return v_signmask(v_reinterpret_as_u64(a)); } -#if CV_SIMD128_64F -inline int v_signmask(const v_float64x2& a) -{ return v_signmask(v_reinterpret_as_u64(a)); } -#endif - -#else -#define OPENCV_HAL_IMPL_RVV_SIGNMASK_OP(_Tpvec, width, vl) \ -inline int v_signmask(const _Tpvec& a) \ -{ \ - uint8_t ans[16] = {0};\ - vsm(ans, vmslt(a, 0, vl), vl);\ - return reinterpret_cast(ans)[0] & ((1 << (vl)) - 1);\ -} - -OPENCV_HAL_IMPL_RVV_SIGNMASK_OP(v_int8x16, 8, 16) -OPENCV_HAL_IMPL_RVV_SIGNMASK_OP(v_int16x8, 16, 8) -OPENCV_HAL_IMPL_RVV_SIGNMASK_OP(v_int32x4, 32, 4) -OPENCV_HAL_IMPL_RVV_SIGNMASK_OP(v_int64x2, 64, 2) - -inline int v_signmask(const v_uint8x16& a) -{ return v_signmask(v_reinterpret_as_s8(a)); } -inline int v_signmask(const v_uint16x8& a) -{ return v_signmask(v_reinterpret_as_s16(a)); } -inline int v_signmask(const v_uint32x4& a) -{ return v_signmask(v_reinterpret_as_s32(a)); } -inline int v_signmask(const v_float32x4& a) -{ return v_signmask(v_reinterpret_as_s32(a)); } -inline int v_signmask(const v_uint64x2& a) -{ return v_signmask(v_reinterpret_as_s64(a)); } -#if CV_SIMD128_64F -inline int v_signmask(const v_float64x2& a) -{ return v_signmask(v_reinterpret_as_s64(a)); } -#endif - -#endif - -//////////// Scan forward //////////// - -#define OPENCV_HAL_IMPL_RVV_SCAN_FORWOARD_OP(_Tpvec, _Tp, suffix) \ -inline int v_scan_forward(const _Tpvec& a) \ -{ \ - _Tp ptr[_Tpvec::nlanes] = {0}; \ - v_store(ptr, v_reinterpret_as_##suffix(a)); \ - for (int i = 0; i < _Tpvec::nlanes; i++) \ - if(int(ptr[i]) < 0) \ - return i; \ - return 0; \ -} - -OPENCV_HAL_IMPL_RVV_SCAN_FORWOARD_OP(v_uint8x16, uchar, u8) -OPENCV_HAL_IMPL_RVV_SCAN_FORWOARD_OP(v_int8x16, schar, s8) -OPENCV_HAL_IMPL_RVV_SCAN_FORWOARD_OP(v_uint16x8, ushort, u16) -OPENCV_HAL_IMPL_RVV_SCAN_FORWOARD_OP(v_int16x8, short, s16) -OPENCV_HAL_IMPL_RVV_SCAN_FORWOARD_OP(v_uint32x4, unsigned, u32) -OPENCV_HAL_IMPL_RVV_SCAN_FORWOARD_OP(v_int32x4, int, s32) -OPENCV_HAL_IMPL_RVV_SCAN_FORWOARD_OP(v_float32x4, float, f32) -OPENCV_HAL_IMPL_RVV_SCAN_FORWOARD_OP(v_uint64x2, uint64, u64) -OPENCV_HAL_IMPL_RVV_SCAN_FORWOARD_OP(v_int64x2, int64, s64) -#if CV_SIMD128_64F -OPENCV_HAL_IMPL_RVV_SCAN_FORWOARD_OP(v_float64x2, double, f64) -#endif - -//////////// Pack triplets //////////// - -inline v_int8x16 v_pack_triplets(const v_int8x16& vec) -{ - const uint64 ptr[2] = {0x0908060504020100, 0xFFFFFF0F0E0D0C0A}; - const v_uint64x2 flags(vle64_v_u64m1(ptr, 2)); - return v_reinterpret_as_s8(v_uint8x16( - vrgather_vv_u8m1( - v_reinterpret_as_u8(vec), - v_reinterpret_as_u8(flags), - 16))); -} -inline v_uint8x16 v_pack_triplets(const v_uint8x16& vec) -{ - return v_reinterpret_as_u8(v_pack_triplets(v_reinterpret_as_s8(vec))); -} - -inline v_int16x8 v_pack_triplets(const v_int16x8& vec) -{ - const uint64 ptr[2] = {0x0908050403020100, 0xFFFF0F0E0D0C0B0A}; - const v_uint64x2 flags(vle64_v_u64m1(ptr, 2)); - return v_reinterpret_as_s16(v_uint8x16( - vrgather_vv_u8m1( - v_reinterpret_as_u8(vec), - v_reinterpret_as_u8(flags), - 16))); -} -inline v_uint16x8 v_pack_triplets(const v_uint16x8& vec) -{ - return v_reinterpret_as_u16(v_pack_triplets(v_reinterpret_as_s16(vec))); -} - -inline v_int32x4 v_pack_triplets(const v_int32x4& vec) { return vec; } -inline v_uint32x4 v_pack_triplets(const v_uint32x4& vec) { return vec; } -inline v_float32x4 v_pack_triplets(const v_float32x4& vec) { return vec; } - -////// FP16 support /////// - -#if CV_FP16 -inline v_float32x4 v_load_expand(const hfloat* ptr) -{ - return v_float32x4(vfwcvt_f_f_v_f32m1(vle16_v_f16mf2(ptr, 4), 4)); -} - -inline void v_pack_store(hfloat* ptr, const v_float32x4& v) -{ - vse16_v_f16mf2(ptr, vfncvt_f_f_w_f16mf2(v, 4), 4); -} -#else -inline v_float32x4 v_load_expand(const hfloat* ptr) -{ - const int N = 4; - float buf[N]; - for( int i = 0; i < N; i++ ) buf[i] = (float)ptr[i]; - return v_load(buf); -} - -inline void v_pack_store(hfloat* ptr, const v_float32x4& v) -{ - const int N = 4; - float buf[N]; - v_store(buf, v); - for( int i = 0; i < N; i++ ) ptr[i] = hfloat(buf[i]); -} -#endif - -////////////// Rounding ////////////// - -inline v_int32x4 v_round(const v_float32x4& a) -{ - return v_int32x4(vfcvt_x_f_v_i32m1(a, 4)); -} - -inline v_int32x4 v_floor(const v_float32x4& a) -{ - v_float32x4 ZP5 = v_setall_f32(0.5f); - v_float32x4 t = a - ZP5; - return v_int32x4(vfcvt_x_f_v_i32m1(t, 4)); -} - -inline v_int32x4 v_ceil(const v_float32x4& a) -{ - v_float32x4 ZP5 = v_setall_f32(0.5f); - v_float32x4 t = a + ZP5; - return v_int32x4(vfcvt_x_f_v_i32m1(t, 4)); -} - -inline v_int32x4 v_trunc(const v_float32x4& a) -{ -#ifndef CV_RVV_THEAD_0_7 - return v_int32x4(vfcvt_rtz_x_f_v_i32m1(a, 4)); -#else - const int old_round = fesetround(FE_TOWARDZERO); - vint32m1_t val = vfcvt_x_f_v_i32m1(a, 4); - fesetround(old_round); - return v_int32x4(val); -#endif -} -#if CV_SIMD128_64F -#ifndef __clang__ -inline v_int32x4 v_round(const v_float64x2& a) -{ - double arr[4] = {a.val[0], a.val[1], 0, 0}; - vfloat64m2_t tmp = vle64_v_f64m2(arr, 4); - return v_int32x4(vfncvt_x_f_w_i32m1(tmp, 4)); -} - -inline v_int32x4 v_round(const v_float64x2& a, const v_float64x2& b) -{ - double arr[4] = {a.val[0], a.val[1], b.val[0], b.val[1]}; - vfloat64m2_t tmp = vle64_v_f64m2(arr, 4); - return v_int32x4(vfncvt_x_f_w_i32m1(tmp, 4)); -} - -inline v_int32x4 v_floor(const v_float64x2& a) -{ - double arr[4] = {a.val[0]-0.5f, a.val[1]-0.5f, 0, 0}; - vfloat64m2_t tmp = vle64_v_f64m2(arr, 4); - return v_int32x4(vfncvt_x_f_w_i32m1(tmp, 4)); -} - -inline v_int32x4 v_ceil(const v_float64x2& a) -{ - double arr[4] = {a.val[0]+0.5f, a.val[1]+0.5f, 0, 0}; - vfloat64m2_t tmp = vle64_v_f64m2(arr, 4); - return v_int32x4(vfncvt_x_f_w_i32m1(tmp, 4)); -} - -inline v_int32x4 v_trunc(const v_float64x2& a) -{ - double arr[4] = {a.val[0], a.val[1], 0, 0}; - vfloat64m2_t tmp = vle64_v_f64m2(arr, 4); -#ifndef CV_RVV_THEAD_0_7 - return v_int32x4(vfncvt_rtz_x_f_w_i32m1(tmp, 4)); -#else - const int old_round = fesetround(FE_TOWARDZERO); - vint32m1_t val = vfncvt_x_f_w_i32m1(tmp, 4); - fesetround(old_round); - return v_int32x4(val); -#endif -} - -#else -inline v_int32x4 v_round(const v_float64x2& a) -{ - vfloat64m2_t zero = vfmv_v_f_f64m2(0, 4); - return v_int32x4(vfncvt_x_f_w_i32m1(vset_v_f64m1_f64m2(zero, 0, a), 4)); -} - -inline v_int32x4 v_round(const v_float64x2& a, const v_float64x2& b) -{ - vfloat64m2_t dst = vlmul_ext_v_f64m1_f64m2(a); - return v_int32x4(vfncvt_x_f_w_i32m1(vset_v_f64m1_f64m2(dst, 1, b), 4)); -} - -inline v_int32x4 v_floor(const v_float64x2& a) -{ - vfloat64m2_t dst = vfmv_v_f_f64m2(0, 4); - dst = vset_v_f64m1_f64m2(dst, 0, a); - dst = vfsub_vf_f64m2(dst, 0.5, 2); - return v_int32x4(vfncvt_x_f_w_i32m1(dst, 4)); -} - -inline v_int32x4 v_ceil(const v_float64x2& a) -{ - vfloat64m2_t dst = vfmv_v_f_f64m2(0, 4); - dst = vset_v_f64m1_f64m2(dst, 0, a); - dst = vfadd_vf_f64m2(dst, 0.5, 2); - return v_int32x4(vfncvt_x_f_w_i32m1(dst, 4)); -} - -inline v_int32x4 v_trunc(const v_float64x2& a) -{ - vfloat64m2_t zero = vfmv_v_f_f64m2(0, 4); - return v_int32x4(vfncvt_rtz_x_f_w_i32m1(vset_v_f64m1_f64m2(zero, 0, a), 4)); -} -#endif -#endif - - -//////// Dot Product //////// - -// 16 >> 32 -inline v_int32x4 v_dotprod(const v_int16x8& a, const v_int16x8& b) -{ - int ptr[8] = {0}; - v_int32x4 t1, t2; - vse32_v_i32m2(ptr, vwmul_vv_i32m2(a, b, 8), 8); - v_load_deinterleave(ptr, t1, t2); - return t1 + t2; -} -inline v_int32x4 v_dotprod(const v_int16x8& a, const v_int16x8& b, const v_int32x4& c) -{ - int ptr[8] = {0}; - v_int32x4 t1, t2; - vse32_v_i32m2(ptr, vwmul_vv_i32m2(a, b, 8), 8); - v_load_deinterleave(ptr, t1, t2); - return t1 + t2 + c; -} - -// 32 >> 64 -inline v_int64x2 v_dotprod(const v_int32x4& a, const v_int32x4& b) -{ - int64 ptr[4] = {0}; - v_int64x2 t1, t2; - vse64_v_i64m2(ptr, vwmul_vv_i64m2(a, b, 4), 4); - v_load_deinterleave(ptr, t1, t2); - return t1 + t2; -} -inline v_int64x2 v_dotprod(const v_int32x4& a, const v_int32x4& b, const v_int64x2& c) -{ - int64 ptr[4] = {0}; - v_int64x2 t1, t2; - vse64_v_i64m2(ptr, vwmul_vv_i64m2(a, b, 4), 4); - v_load_deinterleave(ptr, t1, t2); - return t1 + t2 + c; -} - -// 8 >> 32 -inline v_uint32x4 v_dotprod_expand(const v_uint8x16& a, const v_uint8x16& b) -{ - unsigned ptr[16] = {0}; - v_uint32x4 t1, t2, t3, t4; - vse32_v_u32m4(ptr, vwcvtu_x_x_v_u32m4(vwmulu_vv_u16m2(a, b, 16), 16), 16); - v_load_deinterleave(ptr, t1, t2, t3, t4); - return t1 + t2 + t3 + t4; -} -inline v_uint32x4 v_dotprod_expand(const v_uint8x16& a, const v_uint8x16& b, - const v_uint32x4& c) -{ - unsigned ptr[16] = {0}; - v_uint32x4 t1, t2, t3, t4; - vse32_v_u32m4(ptr, vwcvtu_x_x_v_u32m4(vwmulu_vv_u16m2(a, b, 16), 16), 16); - v_load_deinterleave(ptr, t1, t2, t3, t4); - return t1 + t2 + t3 + t4 + c; -} - -inline v_int32x4 v_dotprod_expand(const v_int8x16& a, const v_int8x16& b) -{ - int ptr[16] = {0}; - v_int32x4 t1, t2, t3, t4; - vse32_v_i32m4(ptr, vwcvt_x_x_v_i32m4(vwmul_vv_i16m2(a, b, 16), 16), 16); - v_load_deinterleave(ptr, t1, t2, t3, t4); - return t1 + t2 + t3 + t4; -} -inline v_int32x4 v_dotprod_expand(const v_int8x16& a, const v_int8x16& b, - const v_int32x4& c) -{ - int ptr[16] = {0}; - v_int32x4 t1, t2, t3, t4; - vse32_v_i32m4(ptr, vwcvt_x_x_v_i32m4(vwmul_vv_i16m2(a, b, 16), 16), 16); - v_load_deinterleave(ptr, t1, t2, t3, t4); - return t1 + t2 + t3 + t4 + c; -} - -// 16 >> 64 -inline v_uint64x2 v_dotprod_expand(const v_uint16x8& a, const v_uint16x8& b) -{ - uint64 ptr[8] = {0}; - v_uint64x2 t1, t2, t3, t4; - vse64_v_u64m4(ptr, vwcvtu_x_x_v_u64m4(vwmulu_vv_u32m2(a, b, 8), 8), 8); - v_load_deinterleave(ptr, t1, t2, t3, t4); - return t1 + t2 + t3 + t4; -} -inline v_uint64x2 v_dotprod_expand(const v_uint16x8& a, const v_uint16x8& b, const v_uint64x2& c) -{ - uint64 ptr[8] = {0}; - v_uint64x2 t1, t2, t3, t4; - vse64_v_u64m4(ptr, vwcvtu_x_x_v_u64m4(vwmulu_vv_u32m2(a, b, 8), 8), 8); - v_load_deinterleave(ptr, t1, t2, t3, t4); - return t1 + t2 + t3 + t4 + c; -} - -inline v_int64x2 v_dotprod_expand(const v_int16x8& a, const v_int16x8& b) -{ - int64 ptr[8] = {0}; - v_int64x2 t1, t2, t3, t4; - vse64_v_i64m4(ptr, vwcvt_x_x_v_i64m4(vwmul_vv_i32m2(a, b, 8), 8), 8); - v_load_deinterleave(ptr, t1, t2, t3, t4); - return t1 + t2 + t3 + t4; -} -inline v_int64x2 v_dotprod_expand(const v_int16x8& a, const v_int16x8& b, - const v_int64x2& c) -{ - int64 ptr[8] = {0}; - v_int64x2 t1, t2, t3, t4; - vse64_v_i64m4(ptr, vwcvt_x_x_v_i64m4(vwmul_vv_i32m2(a, b, 8), 8), 8); - v_load_deinterleave(ptr, t1, t2, t3, t4); - return t1 + t2 + t3 + t4 + c; -} - -// 32 >> 64f -#if CV_SIMD128_64F -inline v_float64x2 v_dotprod_expand(const v_int32x4& a, const v_int32x4& b) -{ return v_cvt_f64(v_dotprod(a, b)); } -inline v_float64x2 v_dotprod_expand(const v_int32x4& a, const v_int32x4& b, - const v_float64x2& c) -{ return v_dotprod_expand(a, b) + c; } -#endif - -//////// Fast Dot Product //////// - -// 16 >> 32 -inline v_int32x4 v_dotprod_fast(const v_int16x8& a, const v_int16x8& b) -{ - int ptr[8] = {0}; - vse32_v_i32m2(ptr, vwmul_vv_i32m2(a, b, 8), 8); - v_int32x4 t1 = v_load(ptr); - v_int32x4 t2 = v_load(ptr+4); - return t1 + t2; -} -inline v_int32x4 v_dotprod_fast(const v_int16x8& a, const v_int16x8& b, const v_int32x4& c) -{ - int ptr[8] = {0}; - vse32_v_i32m2(ptr, vwmul_vv_i32m2(a, b, 8), 8); - v_int32x4 t1 = v_load(ptr); - v_int32x4 t2 = v_load(ptr+4); - return t1 + t2 + c; -} - -// 32 >> 64 -inline v_int64x2 v_dotprod_fast(const v_int32x4& a, const v_int32x4& b) -{ - int64 ptr[4] = {0}; - vse64_v_i64m2(ptr, vwmul_vv_i64m2(a, b, 4), 4); - v_int64x2 t1 = v_load(ptr); - v_int64x2 t2 = v_load(ptr+2); - return t1 + t2; -} -inline v_int64x2 v_dotprod_fast(const v_int32x4& a, const v_int32x4& b, const v_int64x2& c) -{ - int64 ptr[4] = {0}; - vse64_v_i64m2(ptr, vwmul_vv_i64m2(a, b, 4), 4); - v_int64x2 t1 = v_load(ptr); - v_int64x2 t2 = v_load(ptr+2); - return t1 + t2 + c; -} - - -// 8 >> 32 -inline v_uint32x4 v_dotprod_expand_fast(const v_uint8x16& a, const v_uint8x16& b) -{ - unsigned ptr[16] = {0}; - vse32_v_u32m4(ptr, vwcvtu_x_x_v_u32m4(vwmulu_vv_u16m2(a, b, 16), 16), 16); - v_uint32x4 t1 = v_load(ptr); - v_uint32x4 t2 = v_load(ptr+4); - v_uint32x4 t3 = v_load(ptr+8); - v_uint32x4 t4 = v_load(ptr+12); - return t1 + t2 + t3 + t4; -} -inline v_uint32x4 v_dotprod_expand_fast(const v_uint8x16& a, const v_uint8x16& b, const v_uint32x4& c) -{ - unsigned ptr[16] = {0}; - vse32_v_u32m4(ptr, vwcvtu_x_x_v_u32m4(vwmulu_vv_u16m2(a, b, 16), 16), 16); - v_uint32x4 t1 = v_load(ptr); - v_uint32x4 t2 = v_load(ptr+4); - v_uint32x4 t3 = v_load(ptr+8); - v_uint32x4 t4 = v_load(ptr+12); - return t1 + t2 + t3 + t4 + c; -} -inline v_int32x4 v_dotprod_expand_fast(const v_int8x16& a, const v_int8x16& b) -{ - int ptr[16] = {0}; - vse32_v_i32m4(ptr, vwcvt_x_x_v_i32m4(vwmul_vv_i16m2(a, b, 16), 16), 16); - v_int32x4 t1 = v_load(ptr); - v_int32x4 t2 = v_load(ptr+4); - v_int32x4 t3 = v_load(ptr+8); - v_int32x4 t4 = v_load(ptr+12); - return t1 + t2 + t3 + t4; -} -inline v_int32x4 v_dotprod_expand_fast(const v_int8x16& a, const v_int8x16& b, const v_int32x4& c) -{ - int ptr[16] = {0}; - vse32_v_i32m4(ptr, vwcvt_x_x_v_i32m4(vwmul_vv_i16m2(a, b, 16), 16), 16); - v_int32x4 t1 = v_load(ptr); - v_int32x4 t2 = v_load(ptr+4); - v_int32x4 t3 = v_load(ptr+8); - v_int32x4 t4 = v_load(ptr+12); - return t1 + t2 + t3 + t4 + c; -} - -// 16 >> 64 -inline v_uint64x2 v_dotprod_expand_fast(const v_uint16x8& a, const v_uint16x8& b) -{ - uint64 ptr[8] = {0}; - vse64_v_u64m4(ptr, vwcvtu_x_x_v_u64m4(vwmulu_vv_u32m2(a, b, 8), 8), 8); - v_uint64x2 t1 = v_load(ptr); - v_uint64x2 t2 = v_load(ptr+2); - v_uint64x2 t3 = v_load(ptr+4); - v_uint64x2 t4 = v_load(ptr+6); - return t1 + t2 + t3 + t4; -} -inline v_uint64x2 v_dotprod_expand_fast(const v_uint16x8& a, const v_uint16x8& b, const v_uint64x2& c) -{ - uint64 ptr[8] = {0}; - vse64_v_u64m4(ptr, vwcvtu_x_x_v_u64m4(vwmulu_vv_u32m2(a, b, 8), 8), 8); - v_uint64x2 t1 = v_load(ptr); - v_uint64x2 t2 = v_load(ptr+2); - v_uint64x2 t3 = v_load(ptr+4); - v_uint64x2 t4 = v_load(ptr+6); - return t1 + t2 + t3 + t4 + c; -} -inline v_int64x2 v_dotprod_expand_fast(const v_int16x8& a, const v_int16x8& b) -{ - int64 ptr[8] = {0}; - vse64_v_i64m4(ptr, vwcvt_x_x_v_i64m4(vwmul_vv_i32m2(a, b, 8), 8), 8); - v_int64x2 t1 = v_load(ptr); - v_int64x2 t2 = v_load(ptr+2); - v_int64x2 t3 = v_load(ptr+4); - v_int64x2 t4 = v_load(ptr+6); - return t1 + t2 + t3 + t4; -} -inline v_int64x2 v_dotprod_expand_fast(const v_int16x8& a, const v_int16x8& b, const v_int64x2& c) -{ - int64 ptr[8] = {0}; - vse64_v_i64m4(ptr, vwcvt_x_x_v_i64m4(vwmul_vv_i32m2(a, b, 8), 8), 8); - v_int64x2 t1 = v_load(ptr); - v_int64x2 t2 = v_load(ptr+2); - v_int64x2 t3 = v_load(ptr+4); - v_int64x2 t4 = v_load(ptr+6); - return t1 + t2 + t3 + t4 + c; -} - -// 32 >> 64f -#if CV_SIMD128_64F -inline v_float64x2 v_dotprod_expand_fast(const v_int32x4& a, const v_int32x4& b) -{ return v_cvt_f64(v_dotprod_fast(a, b)); } -inline v_float64x2 v_dotprod_expand_fast(const v_int32x4& a, const v_int32x4& b, const v_float64x2& c) -{ return v_dotprod_expand_fast(a, b) + c; } -#endif - - -inline v_float32x4 v_matmul(const v_float32x4& v, const v_float32x4& m0, - const v_float32x4& m1, const v_float32x4& m2, - const v_float32x4& m3) -{ - vfloat32m1_t res = vfmul_vf_f32m1(m0, v_extract_n<0>(v), 4); - res = vfmacc_vf_f32m1(res, v_extract_n<1>(v), m1, 4); - res = vfmacc_vf_f32m1(res, v_extract_n<2>(v), m2, 4); - res = vfmacc_vf_f32m1(res, v_extract_n<3>(v), m3, 4); - return v_float32x4(res); -} - -inline v_float32x4 v_matmuladd(const v_float32x4& v, const v_float32x4& m0, - const v_float32x4& m1, const v_float32x4& m2, - const v_float32x4& a) -{ - vfloat32m1_t res = vfmul_vf_f32m1(m0, v_extract_n<0>(v), 4); - res = vfmacc_vf_f32m1(res, v_extract_n<1>(v), m1, 4); - res = vfmacc_vf_f32m1(res, v_extract_n<2>(v), m2, 4); - return v_float32x4(res) + a; -} - -#define OPENCV_HAL_IMPL_RVV_MUL_EXPAND(_Tpvec, _Tpwvec, _Tpw, suffix, wmul, width, vl, hvl) \ -inline void v_mul_expand(const _Tpvec& a, const _Tpvec& b, _Tpwvec& c, _Tpwvec& d) \ -{ \ - _Tpw ptr[_Tpwvec::nlanes*2] = {0}; \ - vse##width##_v_##suffix##m2(ptr, wmul(a, b, vl), vl); \ - c = _Tpwvec(vle##width##_v_##suffix##m1(ptr, hvl)); \ - d = _Tpwvec(vle##width##_v_##suffix##m1(ptr+_Tpwvec::nlanes, hvl)); \ -} - -OPENCV_HAL_IMPL_RVV_MUL_EXPAND(v_uint8x16, v_uint16x8, ushort, u16, vwmulu_vv_u16m2, 16, 16, 8) -OPENCV_HAL_IMPL_RVV_MUL_EXPAND(v_int8x16, v_int16x8, short, i16, vwmul_vv_i16m2, 16, 16, 8) -OPENCV_HAL_IMPL_RVV_MUL_EXPAND(v_uint16x8, v_uint32x4, unsigned, u32, vwmulu_vv_u32m2, 32, 8, 4) -OPENCV_HAL_IMPL_RVV_MUL_EXPAND(v_int16x8, v_int32x4, int, i32, vwmul_vv_i32m2, 32, 8, 4) -OPENCV_HAL_IMPL_RVV_MUL_EXPAND(v_uint32x4, v_uint64x2, uint64, u64, vwmulu_vv_u64m2, 64, 4, 2) - - -inline v_int16x8 v_mul_hi(const v_int16x8& a, const v_int16x8& b) -{ - return v_int16x8(vnsra_wx_i16m1(vwmul_vv_i32m2(a, b, 8), 16, 8)); -} -inline v_uint16x8 v_mul_hi(const v_uint16x8& a, const v_uint16x8& b) -{ - return v_uint16x8(vnsrl_wx_u16m1(vwmulu_vv_u32m2(a, b, 8), 16, 8)); -} - - -//////// Saturating Multiply //////// - -#define OPENCV_HAL_IMPL_RVV_MUL_SAT(_Tpvec, _wTpvec) \ -inline _Tpvec operator * (const _Tpvec& a, const _Tpvec& b) \ -{ \ - _wTpvec c, d; \ - v_mul_expand(a, b, c, d); \ - return v_pack(c, d); \ -} \ -inline _Tpvec& operator *= (_Tpvec& a, const _Tpvec& b) \ -{ \ - a = a * b; \ - return a; \ -} - -OPENCV_HAL_IMPL_RVV_MUL_SAT(v_uint8x16, v_uint16x8) -OPENCV_HAL_IMPL_RVV_MUL_SAT(v_int8x16, v_int16x8) -OPENCV_HAL_IMPL_RVV_MUL_SAT(v_uint16x8, v_uint32x4) -OPENCV_HAL_IMPL_RVV_MUL_SAT(v_int16x8, v_int32x4) - - -inline void v_cleanup() {} - -CV_CPU_OPTIMIZATION_HAL_NAMESPACE_END - -//! @endcond - -} // namespace cv - -#endif diff --git a/modules/core/include/opencv2/core/hal/intrin_rvv_010_compat_non-policy.hpp b/modules/core/include/opencv2/core/hal/intrin_rvv_010_compat_non-policy.hpp deleted file mode 100644 index 6e19e3087b..0000000000 --- a/modules/core/include/opencv2/core/hal/intrin_rvv_010_compat_non-policy.hpp +++ /dev/null @@ -1,24395 +0,0 @@ -// This file is part of OpenCV project. -// It is subject to the license terms in the LICENSE file found in the top-level directory -// of this distribution and at http://opencv.org/license.html. - -// Copied from -// https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/master/auto-generated/rvv-v0p10-compatible-headers - -#ifndef __RVV_0P10_COMPATIBLE_HEADERS_NON_OVERLOADED_NON_POLICY_H -#define __RVV_0P10_COMPATIBLE_HEADERS_NON_OVERLOADED_NON_POLICY_H - - -#if __has_include ("riscv_vector.h") -#include -#endif -#ifndef __RISCV_VECTOR_H -#include_next -#endif - -#define vsetvl_e8mf8(...) __riscv_vsetvl_e8mf8(__VA_ARGS__) -#define vsetvl_e8mf4(...) __riscv_vsetvl_e8mf4(__VA_ARGS__) -#define vsetvl_e8mf2(...) __riscv_vsetvl_e8mf2(__VA_ARGS__) -#define vsetvl_e8m1(...) __riscv_vsetvl_e8m1(__VA_ARGS__) -#define vsetvl_e8m2(...) __riscv_vsetvl_e8m2(__VA_ARGS__) -#define vsetvl_e8m4(...) __riscv_vsetvl_e8m4(__VA_ARGS__) -#define vsetvl_e8m8(...) __riscv_vsetvl_e8m8(__VA_ARGS__) -#define vsetvl_e16mf4(...) __riscv_vsetvl_e16mf4(__VA_ARGS__) -#define vsetvl_e16mf2(...) __riscv_vsetvl_e16mf2(__VA_ARGS__) -#define vsetvl_e16m1(...) __riscv_vsetvl_e16m1(__VA_ARGS__) -#define vsetvl_e16m2(...) __riscv_vsetvl_e16m2(__VA_ARGS__) -#define vsetvl_e16m4(...) __riscv_vsetvl_e16m4(__VA_ARGS__) -#define vsetvl_e16m8(...) __riscv_vsetvl_e16m8(__VA_ARGS__) -#define vsetvl_e32mf2(...) __riscv_vsetvl_e32mf2(__VA_ARGS__) -#define vsetvl_e32m1(...) __riscv_vsetvl_e32m1(__VA_ARGS__) -#define vsetvl_e32m2(...) __riscv_vsetvl_e32m2(__VA_ARGS__) -#define vsetvl_e32m4(...) __riscv_vsetvl_e32m4(__VA_ARGS__) -#define vsetvl_e32m8(...) __riscv_vsetvl_e32m8(__VA_ARGS__) -#define vsetvl_e64m1(...) __riscv_vsetvl_e64m1(__VA_ARGS__) -#define vsetvl_e64m2(...) __riscv_vsetvl_e64m2(__VA_ARGS__) -#define vsetvl_e64m4(...) __riscv_vsetvl_e64m4(__VA_ARGS__) -#define vsetvl_e64m8(...) __riscv_vsetvl_e64m8(__VA_ARGS__) -#define vsetvlmax_e8mf8(...) __riscv_vsetvlmax_e8mf8(__VA_ARGS__) -#define vsetvlmax_e8mf4(...) __riscv_vsetvlmax_e8mf4(__VA_ARGS__) -#define vsetvlmax_e8mf2(...) __riscv_vsetvlmax_e8mf2(__VA_ARGS__) -#define vsetvlmax_e8m1(...) __riscv_vsetvlmax_e8m1(__VA_ARGS__) -#define vsetvlmax_e8m2(...) __riscv_vsetvlmax_e8m2(__VA_ARGS__) -#define vsetvlmax_e8m4(...) __riscv_vsetvlmax_e8m4(__VA_ARGS__) -#define vsetvlmax_e8m8(...) __riscv_vsetvlmax_e8m8(__VA_ARGS__) -#define vsetvlmax_e16mf4(...) __riscv_vsetvlmax_e16mf4(__VA_ARGS__) -#define vsetvlmax_e16mf2(...) __riscv_vsetvlmax_e16mf2(__VA_ARGS__) -#define vsetvlmax_e16m1(...) __riscv_vsetvlmax_e16m1(__VA_ARGS__) -#define vsetvlmax_e16m2(...) __riscv_vsetvlmax_e16m2(__VA_ARGS__) -#define vsetvlmax_e16m4(...) __riscv_vsetvlmax_e16m4(__VA_ARGS__) -#define vsetvlmax_e16m8(...) __riscv_vsetvlmax_e16m8(__VA_ARGS__) -#define vsetvlmax_e32mf2(...) __riscv_vsetvlmax_e32mf2(__VA_ARGS__) -#define vsetvlmax_e32m1(...) __riscv_vsetvlmax_e32m1(__VA_ARGS__) -#define vsetvlmax_e32m2(...) __riscv_vsetvlmax_e32m2(__VA_ARGS__) -#define vsetvlmax_e32m4(...) __riscv_vsetvlmax_e32m4(__VA_ARGS__) -#define vsetvlmax_e32m8(...) __riscv_vsetvlmax_e32m8(__VA_ARGS__) -#define vsetvlmax_e64m1(...) __riscv_vsetvlmax_e64m1(__VA_ARGS__) -#define vsetvlmax_e64m2(...) __riscv_vsetvlmax_e64m2(__VA_ARGS__) -#define vsetvlmax_e64m4(...) __riscv_vsetvlmax_e64m4(__VA_ARGS__) -#define vsetvlmax_e64m8(...) __riscv_vsetvlmax_e64m8(__VA_ARGS__) -#define vle16_v_f16mf4(...) __riscv_vle16_v_f16mf4(__VA_ARGS__) -#define vle16_v_f16mf2(...) __riscv_vle16_v_f16mf2(__VA_ARGS__) -#define vle16_v_f16m1(...) __riscv_vle16_v_f16m1(__VA_ARGS__) -#define vle16_v_f16m2(...) __riscv_vle16_v_f16m2(__VA_ARGS__) -#define vle16_v_f16m4(...) __riscv_vle16_v_f16m4(__VA_ARGS__) -#define vle16_v_f16m8(...) __riscv_vle16_v_f16m8(__VA_ARGS__) -#define vle32_v_f32mf2(...) __riscv_vle32_v_f32mf2(__VA_ARGS__) -#define vle32_v_f32m1(...) __riscv_vle32_v_f32m1(__VA_ARGS__) -#define vle32_v_f32m2(...) __riscv_vle32_v_f32m2(__VA_ARGS__) -#define vle32_v_f32m4(...) __riscv_vle32_v_f32m4(__VA_ARGS__) -#define vle32_v_f32m8(...) __riscv_vle32_v_f32m8(__VA_ARGS__) -#define vle64_v_f64m1(...) __riscv_vle64_v_f64m1(__VA_ARGS__) -#define vle64_v_f64m2(...) __riscv_vle64_v_f64m2(__VA_ARGS__) -#define vle64_v_f64m4(...) __riscv_vle64_v_f64m4(__VA_ARGS__) -#define vle64_v_f64m8(...) __riscv_vle64_v_f64m8(__VA_ARGS__) -#define vle8_v_i8mf8(...) __riscv_vle8_v_i8mf8(__VA_ARGS__) -#define vle8_v_i8mf4(...) __riscv_vle8_v_i8mf4(__VA_ARGS__) -#define vle8_v_i8mf2(...) __riscv_vle8_v_i8mf2(__VA_ARGS__) -#define vle8_v_i8m1(...) __riscv_vle8_v_i8m1(__VA_ARGS__) -#define vle8_v_i8m2(...) __riscv_vle8_v_i8m2(__VA_ARGS__) -#define vle8_v_i8m4(...) __riscv_vle8_v_i8m4(__VA_ARGS__) -#define vle8_v_i8m8(...) __riscv_vle8_v_i8m8(__VA_ARGS__) -#define vle16_v_i16mf4(...) __riscv_vle16_v_i16mf4(__VA_ARGS__) -#define vle16_v_i16mf2(...) __riscv_vle16_v_i16mf2(__VA_ARGS__) -#define vle16_v_i16m1(...) __riscv_vle16_v_i16m1(__VA_ARGS__) -#define vle16_v_i16m2(...) __riscv_vle16_v_i16m2(__VA_ARGS__) -#define vle16_v_i16m4(...) __riscv_vle16_v_i16m4(__VA_ARGS__) -#define vle16_v_i16m8(...) __riscv_vle16_v_i16m8(__VA_ARGS__) -#define vle32_v_i32mf2(...) __riscv_vle32_v_i32mf2(__VA_ARGS__) -#define vle32_v_i32m1(...) __riscv_vle32_v_i32m1(__VA_ARGS__) -#define vle32_v_i32m2(...) __riscv_vle32_v_i32m2(__VA_ARGS__) -#define vle32_v_i32m4(...) __riscv_vle32_v_i32m4(__VA_ARGS__) -#define vle32_v_i32m8(...) __riscv_vle32_v_i32m8(__VA_ARGS__) -#define vle64_v_i64m1(...) __riscv_vle64_v_i64m1(__VA_ARGS__) -#define vle64_v_i64m2(...) __riscv_vle64_v_i64m2(__VA_ARGS__) -#define vle64_v_i64m4(...) __riscv_vle64_v_i64m4(__VA_ARGS__) -#define vle64_v_i64m8(...) __riscv_vle64_v_i64m8(__VA_ARGS__) -#define vle8_v_u8mf8(...) __riscv_vle8_v_u8mf8(__VA_ARGS__) -#define vle8_v_u8mf4(...) __riscv_vle8_v_u8mf4(__VA_ARGS__) -#define vle8_v_u8mf2(...) __riscv_vle8_v_u8mf2(__VA_ARGS__) -#define vle8_v_u8m1(...) __riscv_vle8_v_u8m1(__VA_ARGS__) -#define vle8_v_u8m2(...) __riscv_vle8_v_u8m2(__VA_ARGS__) -#define vle8_v_u8m4(...) __riscv_vle8_v_u8m4(__VA_ARGS__) -#define vle8_v_u8m8(...) __riscv_vle8_v_u8m8(__VA_ARGS__) -#define vle16_v_u16mf4(...) __riscv_vle16_v_u16mf4(__VA_ARGS__) -#define vle16_v_u16mf2(...) __riscv_vle16_v_u16mf2(__VA_ARGS__) -#define vle16_v_u16m1(...) __riscv_vle16_v_u16m1(__VA_ARGS__) -#define vle16_v_u16m2(...) __riscv_vle16_v_u16m2(__VA_ARGS__) -#define vle16_v_u16m4(...) __riscv_vle16_v_u16m4(__VA_ARGS__) -#define vle16_v_u16m8(...) __riscv_vle16_v_u16m8(__VA_ARGS__) -#define vle32_v_u32mf2(...) __riscv_vle32_v_u32mf2(__VA_ARGS__) -#define vle32_v_u32m1(...) __riscv_vle32_v_u32m1(__VA_ARGS__) -#define vle32_v_u32m2(...) __riscv_vle32_v_u32m2(__VA_ARGS__) -#define vle32_v_u32m4(...) __riscv_vle32_v_u32m4(__VA_ARGS__) -#define vle32_v_u32m8(...) __riscv_vle32_v_u32m8(__VA_ARGS__) -#define vle64_v_u64m1(...) __riscv_vle64_v_u64m1(__VA_ARGS__) -#define vle64_v_u64m2(...) __riscv_vle64_v_u64m2(__VA_ARGS__) -#define vle64_v_u64m4(...) __riscv_vle64_v_u64m4(__VA_ARGS__) -#define vle64_v_u64m8(...) __riscv_vle64_v_u64m8(__VA_ARGS__) -// masked functions -#define vle16_v_f16mf4_m(...) __riscv_vle16_v_f16mf4_tumu(__VA_ARGS__) -#define vle16_v_f16mf2_m(...) __riscv_vle16_v_f16mf2_tumu(__VA_ARGS__) -#define vle16_v_f16m1_m(...) __riscv_vle16_v_f16m1_tumu(__VA_ARGS__) -#define vle16_v_f16m2_m(...) __riscv_vle16_v_f16m2_tumu(__VA_ARGS__) -#define vle16_v_f16m4_m(...) __riscv_vle16_v_f16m4_tumu(__VA_ARGS__) -#define vle16_v_f16m8_m(...) __riscv_vle16_v_f16m8_tumu(__VA_ARGS__) -#define vle32_v_f32mf2_m(...) __riscv_vle32_v_f32mf2_tumu(__VA_ARGS__) -#define vle32_v_f32m1_m(...) __riscv_vle32_v_f32m1_tumu(__VA_ARGS__) -#define vle32_v_f32m2_m(...) __riscv_vle32_v_f32m2_tumu(__VA_ARGS__) -#define vle32_v_f32m4_m(...) __riscv_vle32_v_f32m4_tumu(__VA_ARGS__) -#define vle32_v_f32m8_m(...) __riscv_vle32_v_f32m8_tumu(__VA_ARGS__) -#define vle64_v_f64m1_m(...) __riscv_vle64_v_f64m1_tumu(__VA_ARGS__) -#define vle64_v_f64m2_m(...) __riscv_vle64_v_f64m2_tumu(__VA_ARGS__) -#define vle64_v_f64m4_m(...) __riscv_vle64_v_f64m4_tumu(__VA_ARGS__) -#define vle64_v_f64m8_m(...) __riscv_vle64_v_f64m8_tumu(__VA_ARGS__) -#define vle8_v_i8mf8_m(...) __riscv_vle8_v_i8mf8_tumu(__VA_ARGS__) -#define vle8_v_i8mf4_m(...) __riscv_vle8_v_i8mf4_tumu(__VA_ARGS__) -#define vle8_v_i8mf2_m(...) __riscv_vle8_v_i8mf2_tumu(__VA_ARGS__) -#define vle8_v_i8m1_m(...) __riscv_vle8_v_i8m1_tumu(__VA_ARGS__) -#define vle8_v_i8m2_m(...) __riscv_vle8_v_i8m2_tumu(__VA_ARGS__) -#define vle8_v_i8m4_m(...) __riscv_vle8_v_i8m4_tumu(__VA_ARGS__) -#define vle8_v_i8m8_m(...) __riscv_vle8_v_i8m8_tumu(__VA_ARGS__) -#define vle16_v_i16mf4_m(...) __riscv_vle16_v_i16mf4_tumu(__VA_ARGS__) -#define vle16_v_i16mf2_m(...) __riscv_vle16_v_i16mf2_tumu(__VA_ARGS__) -#define vle16_v_i16m1_m(...) __riscv_vle16_v_i16m1_tumu(__VA_ARGS__) -#define vle16_v_i16m2_m(...) __riscv_vle16_v_i16m2_tumu(__VA_ARGS__) -#define vle16_v_i16m4_m(...) __riscv_vle16_v_i16m4_tumu(__VA_ARGS__) -#define vle16_v_i16m8_m(...) __riscv_vle16_v_i16m8_tumu(__VA_ARGS__) -#define vle32_v_i32mf2_m(...) __riscv_vle32_v_i32mf2_tumu(__VA_ARGS__) -#define vle32_v_i32m1_m(...) __riscv_vle32_v_i32m1_tumu(__VA_ARGS__) -#define vle32_v_i32m2_m(...) __riscv_vle32_v_i32m2_tumu(__VA_ARGS__) -#define vle32_v_i32m4_m(...) __riscv_vle32_v_i32m4_tumu(__VA_ARGS__) -#define vle32_v_i32m8_m(...) __riscv_vle32_v_i32m8_tumu(__VA_ARGS__) -#define vle64_v_i64m1_m(...) __riscv_vle64_v_i64m1_tumu(__VA_ARGS__) -#define vle64_v_i64m2_m(...) __riscv_vle64_v_i64m2_tumu(__VA_ARGS__) -#define vle64_v_i64m4_m(...) __riscv_vle64_v_i64m4_tumu(__VA_ARGS__) -#define vle64_v_i64m8_m(...) __riscv_vle64_v_i64m8_tumu(__VA_ARGS__) -#define vle8_v_u8mf8_m(...) __riscv_vle8_v_u8mf8_tumu(__VA_ARGS__) -#define vle8_v_u8mf4_m(...) __riscv_vle8_v_u8mf4_tumu(__VA_ARGS__) -#define vle8_v_u8mf2_m(...) __riscv_vle8_v_u8mf2_tumu(__VA_ARGS__) -#define vle8_v_u8m1_m(...) __riscv_vle8_v_u8m1_tumu(__VA_ARGS__) -#define vle8_v_u8m2_m(...) __riscv_vle8_v_u8m2_tumu(__VA_ARGS__) -#define vle8_v_u8m4_m(...) __riscv_vle8_v_u8m4_tumu(__VA_ARGS__) -#define vle8_v_u8m8_m(...) __riscv_vle8_v_u8m8_tumu(__VA_ARGS__) -#define vle16_v_u16mf4_m(...) __riscv_vle16_v_u16mf4_tumu(__VA_ARGS__) -#define vle16_v_u16mf2_m(...) __riscv_vle16_v_u16mf2_tumu(__VA_ARGS__) -#define vle16_v_u16m1_m(...) __riscv_vle16_v_u16m1_tumu(__VA_ARGS__) -#define vle16_v_u16m2_m(...) __riscv_vle16_v_u16m2_tumu(__VA_ARGS__) -#define vle16_v_u16m4_m(...) __riscv_vle16_v_u16m4_tumu(__VA_ARGS__) -#define vle16_v_u16m8_m(...) __riscv_vle16_v_u16m8_tumu(__VA_ARGS__) -#define vle32_v_u32mf2_m(...) __riscv_vle32_v_u32mf2_tumu(__VA_ARGS__) -#define vle32_v_u32m1_m(...) __riscv_vle32_v_u32m1_tumu(__VA_ARGS__) -#define vle32_v_u32m2_m(...) __riscv_vle32_v_u32m2_tumu(__VA_ARGS__) -#define vle32_v_u32m4_m(...) __riscv_vle32_v_u32m4_tumu(__VA_ARGS__) -#define vle32_v_u32m8_m(...) __riscv_vle32_v_u32m8_tumu(__VA_ARGS__) -#define vle64_v_u64m1_m(...) __riscv_vle64_v_u64m1_tumu(__VA_ARGS__) -#define vle64_v_u64m2_m(...) __riscv_vle64_v_u64m2_tumu(__VA_ARGS__) -#define vle64_v_u64m4_m(...) __riscv_vle64_v_u64m4_tumu(__VA_ARGS__) -#define vle64_v_u64m8_m(...) __riscv_vle64_v_u64m8_tumu(__VA_ARGS__) -#define vse16_v_f16mf4(...) __riscv_vse16_v_f16mf4(__VA_ARGS__) -#define vse16_v_f16mf2(...) __riscv_vse16_v_f16mf2(__VA_ARGS__) -#define vse16_v_f16m1(...) __riscv_vse16_v_f16m1(__VA_ARGS__) -#define vse16_v_f16m2(...) __riscv_vse16_v_f16m2(__VA_ARGS__) -#define vse16_v_f16m4(...) __riscv_vse16_v_f16m4(__VA_ARGS__) -#define vse16_v_f16m8(...) __riscv_vse16_v_f16m8(__VA_ARGS__) -#define vse32_v_f32mf2(...) __riscv_vse32_v_f32mf2(__VA_ARGS__) -#define vse32_v_f32m1(...) __riscv_vse32_v_f32m1(__VA_ARGS__) -#define vse32_v_f32m2(...) __riscv_vse32_v_f32m2(__VA_ARGS__) -#define vse32_v_f32m4(...) __riscv_vse32_v_f32m4(__VA_ARGS__) -#define vse32_v_f32m8(...) __riscv_vse32_v_f32m8(__VA_ARGS__) -#define vse64_v_f64m1(...) __riscv_vse64_v_f64m1(__VA_ARGS__) -#define vse64_v_f64m2(...) __riscv_vse64_v_f64m2(__VA_ARGS__) -#define vse64_v_f64m4(...) __riscv_vse64_v_f64m4(__VA_ARGS__) -#define vse64_v_f64m8(...) __riscv_vse64_v_f64m8(__VA_ARGS__) -#define vse8_v_i8mf8(...) __riscv_vse8_v_i8mf8(__VA_ARGS__) -#define vse8_v_i8mf4(...) __riscv_vse8_v_i8mf4(__VA_ARGS__) -#define vse8_v_i8mf2(...) __riscv_vse8_v_i8mf2(__VA_ARGS__) -#define vse8_v_i8m1(...) __riscv_vse8_v_i8m1(__VA_ARGS__) -#define vse8_v_i8m2(...) __riscv_vse8_v_i8m2(__VA_ARGS__) -#define vse8_v_i8m4(...) __riscv_vse8_v_i8m4(__VA_ARGS__) -#define vse8_v_i8m8(...) __riscv_vse8_v_i8m8(__VA_ARGS__) -#define vse16_v_i16mf4(...) __riscv_vse16_v_i16mf4(__VA_ARGS__) -#define vse16_v_i16mf2(...) __riscv_vse16_v_i16mf2(__VA_ARGS__) -#define vse16_v_i16m1(...) __riscv_vse16_v_i16m1(__VA_ARGS__) -#define vse16_v_i16m2(...) __riscv_vse16_v_i16m2(__VA_ARGS__) -#define vse16_v_i16m4(...) __riscv_vse16_v_i16m4(__VA_ARGS__) -#define vse16_v_i16m8(...) __riscv_vse16_v_i16m8(__VA_ARGS__) -#define vse32_v_i32mf2(...) __riscv_vse32_v_i32mf2(__VA_ARGS__) -#define vse32_v_i32m1(...) __riscv_vse32_v_i32m1(__VA_ARGS__) -#define vse32_v_i32m2(...) __riscv_vse32_v_i32m2(__VA_ARGS__) -#define vse32_v_i32m4(...) __riscv_vse32_v_i32m4(__VA_ARGS__) -#define vse32_v_i32m8(...) __riscv_vse32_v_i32m8(__VA_ARGS__) -#define vse64_v_i64m1(...) __riscv_vse64_v_i64m1(__VA_ARGS__) -#define vse64_v_i64m2(...) __riscv_vse64_v_i64m2(__VA_ARGS__) -#define vse64_v_i64m4(...) __riscv_vse64_v_i64m4(__VA_ARGS__) -#define vse64_v_i64m8(...) __riscv_vse64_v_i64m8(__VA_ARGS__) -#define vse8_v_u8mf8(...) __riscv_vse8_v_u8mf8(__VA_ARGS__) -#define vse8_v_u8mf4(...) __riscv_vse8_v_u8mf4(__VA_ARGS__) -#define vse8_v_u8mf2(...) __riscv_vse8_v_u8mf2(__VA_ARGS__) -#define vse8_v_u8m1(...) __riscv_vse8_v_u8m1(__VA_ARGS__) -#define vse8_v_u8m2(...) __riscv_vse8_v_u8m2(__VA_ARGS__) -#define vse8_v_u8m4(...) __riscv_vse8_v_u8m4(__VA_ARGS__) -#define vse8_v_u8m8(...) __riscv_vse8_v_u8m8(__VA_ARGS__) -#define vse16_v_u16mf4(...) __riscv_vse16_v_u16mf4(__VA_ARGS__) -#define vse16_v_u16mf2(...) __riscv_vse16_v_u16mf2(__VA_ARGS__) -#define vse16_v_u16m1(...) __riscv_vse16_v_u16m1(__VA_ARGS__) -#define vse16_v_u16m2(...) __riscv_vse16_v_u16m2(__VA_ARGS__) -#define vse16_v_u16m4(...) __riscv_vse16_v_u16m4(__VA_ARGS__) -#define vse16_v_u16m8(...) __riscv_vse16_v_u16m8(__VA_ARGS__) -#define vse32_v_u32mf2(...) __riscv_vse32_v_u32mf2(__VA_ARGS__) -#define vse32_v_u32m1(...) __riscv_vse32_v_u32m1(__VA_ARGS__) -#define vse32_v_u32m2(...) __riscv_vse32_v_u32m2(__VA_ARGS__) -#define vse32_v_u32m4(...) __riscv_vse32_v_u32m4(__VA_ARGS__) -#define vse32_v_u32m8(...) __riscv_vse32_v_u32m8(__VA_ARGS__) -#define vse64_v_u64m1(...) __riscv_vse64_v_u64m1(__VA_ARGS__) -#define vse64_v_u64m2(...) __riscv_vse64_v_u64m2(__VA_ARGS__) -#define vse64_v_u64m4(...) __riscv_vse64_v_u64m4(__VA_ARGS__) -#define vse64_v_u64m8(...) __riscv_vse64_v_u64m8(__VA_ARGS__) -// masked functions -#define vse16_v_f16mf4_m(...) __riscv_vse16_v_f16mf4_m(__VA_ARGS__) -#define vse16_v_f16mf2_m(...) __riscv_vse16_v_f16mf2_m(__VA_ARGS__) -#define vse16_v_f16m1_m(...) __riscv_vse16_v_f16m1_m(__VA_ARGS__) -#define vse16_v_f16m2_m(...) __riscv_vse16_v_f16m2_m(__VA_ARGS__) -#define vse16_v_f16m4_m(...) __riscv_vse16_v_f16m4_m(__VA_ARGS__) -#define vse16_v_f16m8_m(...) __riscv_vse16_v_f16m8_m(__VA_ARGS__) -#define vse32_v_f32mf2_m(...) __riscv_vse32_v_f32mf2_m(__VA_ARGS__) -#define vse32_v_f32m1_m(...) __riscv_vse32_v_f32m1_m(__VA_ARGS__) -#define vse32_v_f32m2_m(...) __riscv_vse32_v_f32m2_m(__VA_ARGS__) -#define vse32_v_f32m4_m(...) __riscv_vse32_v_f32m4_m(__VA_ARGS__) -#define vse32_v_f32m8_m(...) __riscv_vse32_v_f32m8_m(__VA_ARGS__) -#define vse64_v_f64m1_m(...) __riscv_vse64_v_f64m1_m(__VA_ARGS__) -#define vse64_v_f64m2_m(...) __riscv_vse64_v_f64m2_m(__VA_ARGS__) -#define vse64_v_f64m4_m(...) __riscv_vse64_v_f64m4_m(__VA_ARGS__) -#define vse64_v_f64m8_m(...) __riscv_vse64_v_f64m8_m(__VA_ARGS__) -#define vse8_v_i8mf8_m(...) __riscv_vse8_v_i8mf8_m(__VA_ARGS__) -#define vse8_v_i8mf4_m(...) __riscv_vse8_v_i8mf4_m(__VA_ARGS__) -#define vse8_v_i8mf2_m(...) __riscv_vse8_v_i8mf2_m(__VA_ARGS__) -#define vse8_v_i8m1_m(...) __riscv_vse8_v_i8m1_m(__VA_ARGS__) -#define vse8_v_i8m2_m(...) __riscv_vse8_v_i8m2_m(__VA_ARGS__) -#define vse8_v_i8m4_m(...) __riscv_vse8_v_i8m4_m(__VA_ARGS__) -#define vse8_v_i8m8_m(...) __riscv_vse8_v_i8m8_m(__VA_ARGS__) -#define vse16_v_i16mf4_m(...) __riscv_vse16_v_i16mf4_m(__VA_ARGS__) -#define vse16_v_i16mf2_m(...) __riscv_vse16_v_i16mf2_m(__VA_ARGS__) -#define vse16_v_i16m1_m(...) __riscv_vse16_v_i16m1_m(__VA_ARGS__) -#define vse16_v_i16m2_m(...) __riscv_vse16_v_i16m2_m(__VA_ARGS__) -#define vse16_v_i16m4_m(...) __riscv_vse16_v_i16m4_m(__VA_ARGS__) -#define vse16_v_i16m8_m(...) __riscv_vse16_v_i16m8_m(__VA_ARGS__) -#define vse32_v_i32mf2_m(...) __riscv_vse32_v_i32mf2_m(__VA_ARGS__) -#define vse32_v_i32m1_m(...) __riscv_vse32_v_i32m1_m(__VA_ARGS__) -#define vse32_v_i32m2_m(...) __riscv_vse32_v_i32m2_m(__VA_ARGS__) -#define vse32_v_i32m4_m(...) __riscv_vse32_v_i32m4_m(__VA_ARGS__) -#define vse32_v_i32m8_m(...) __riscv_vse32_v_i32m8_m(__VA_ARGS__) -#define vse64_v_i64m1_m(...) __riscv_vse64_v_i64m1_m(__VA_ARGS__) -#define vse64_v_i64m2_m(...) __riscv_vse64_v_i64m2_m(__VA_ARGS__) -#define vse64_v_i64m4_m(...) __riscv_vse64_v_i64m4_m(__VA_ARGS__) -#define vse64_v_i64m8_m(...) __riscv_vse64_v_i64m8_m(__VA_ARGS__) -#define vse8_v_u8mf8_m(...) __riscv_vse8_v_u8mf8_m(__VA_ARGS__) -#define vse8_v_u8mf4_m(...) __riscv_vse8_v_u8mf4_m(__VA_ARGS__) -#define vse8_v_u8mf2_m(...) __riscv_vse8_v_u8mf2_m(__VA_ARGS__) -#define vse8_v_u8m1_m(...) __riscv_vse8_v_u8m1_m(__VA_ARGS__) -#define vse8_v_u8m2_m(...) __riscv_vse8_v_u8m2_m(__VA_ARGS__) -#define vse8_v_u8m4_m(...) __riscv_vse8_v_u8m4_m(__VA_ARGS__) -#define vse8_v_u8m8_m(...) __riscv_vse8_v_u8m8_m(__VA_ARGS__) -#define vse16_v_u16mf4_m(...) __riscv_vse16_v_u16mf4_m(__VA_ARGS__) -#define vse16_v_u16mf2_m(...) __riscv_vse16_v_u16mf2_m(__VA_ARGS__) -#define vse16_v_u16m1_m(...) __riscv_vse16_v_u16m1_m(__VA_ARGS__) -#define vse16_v_u16m2_m(...) __riscv_vse16_v_u16m2_m(__VA_ARGS__) -#define vse16_v_u16m4_m(...) __riscv_vse16_v_u16m4_m(__VA_ARGS__) -#define vse16_v_u16m8_m(...) __riscv_vse16_v_u16m8_m(__VA_ARGS__) -#define vse32_v_u32mf2_m(...) __riscv_vse32_v_u32mf2_m(__VA_ARGS__) -#define vse32_v_u32m1_m(...) __riscv_vse32_v_u32m1_m(__VA_ARGS__) -#define vse32_v_u32m2_m(...) __riscv_vse32_v_u32m2_m(__VA_ARGS__) -#define vse32_v_u32m4_m(...) __riscv_vse32_v_u32m4_m(__VA_ARGS__) -#define vse32_v_u32m8_m(...) __riscv_vse32_v_u32m8_m(__VA_ARGS__) -#define vse64_v_u64m1_m(...) __riscv_vse64_v_u64m1_m(__VA_ARGS__) -#define vse64_v_u64m2_m(...) __riscv_vse64_v_u64m2_m(__VA_ARGS__) -#define vse64_v_u64m4_m(...) __riscv_vse64_v_u64m4_m(__VA_ARGS__) -#define vse64_v_u64m8_m(...) __riscv_vse64_v_u64m8_m(__VA_ARGS__) -#define vlse16_v_f16mf4(...) __riscv_vlse16_v_f16mf4(__VA_ARGS__) -#define vlse16_v_f16mf2(...) __riscv_vlse16_v_f16mf2(__VA_ARGS__) -#define vlse16_v_f16m1(...) __riscv_vlse16_v_f16m1(__VA_ARGS__) -#define vlse16_v_f16m2(...) __riscv_vlse16_v_f16m2(__VA_ARGS__) -#define vlse16_v_f16m4(...) __riscv_vlse16_v_f16m4(__VA_ARGS__) -#define vlse16_v_f16m8(...) __riscv_vlse16_v_f16m8(__VA_ARGS__) -#define vlse32_v_f32mf2(...) __riscv_vlse32_v_f32mf2(__VA_ARGS__) -#define vlse32_v_f32m1(...) __riscv_vlse32_v_f32m1(__VA_ARGS__) -#define vlse32_v_f32m2(...) __riscv_vlse32_v_f32m2(__VA_ARGS__) -#define vlse32_v_f32m4(...) __riscv_vlse32_v_f32m4(__VA_ARGS__) -#define vlse32_v_f32m8(...) __riscv_vlse32_v_f32m8(__VA_ARGS__) -#define vlse64_v_f64m1(...) __riscv_vlse64_v_f64m1(__VA_ARGS__) -#define vlse64_v_f64m2(...) __riscv_vlse64_v_f64m2(__VA_ARGS__) -#define vlse64_v_f64m4(...) __riscv_vlse64_v_f64m4(__VA_ARGS__) -#define vlse64_v_f64m8(...) __riscv_vlse64_v_f64m8(__VA_ARGS__) -#define vlse8_v_i8mf8(...) __riscv_vlse8_v_i8mf8(__VA_ARGS__) -#define vlse8_v_i8mf4(...) __riscv_vlse8_v_i8mf4(__VA_ARGS__) -#define vlse8_v_i8mf2(...) __riscv_vlse8_v_i8mf2(__VA_ARGS__) -#define vlse8_v_i8m1(...) __riscv_vlse8_v_i8m1(__VA_ARGS__) -#define vlse8_v_i8m2(...) __riscv_vlse8_v_i8m2(__VA_ARGS__) -#define vlse8_v_i8m4(...) __riscv_vlse8_v_i8m4(__VA_ARGS__) -#define vlse8_v_i8m8(...) __riscv_vlse8_v_i8m8(__VA_ARGS__) -#define vlse16_v_i16mf4(...) __riscv_vlse16_v_i16mf4(__VA_ARGS__) -#define vlse16_v_i16mf2(...) __riscv_vlse16_v_i16mf2(__VA_ARGS__) -#define vlse16_v_i16m1(...) __riscv_vlse16_v_i16m1(__VA_ARGS__) -#define vlse16_v_i16m2(...) __riscv_vlse16_v_i16m2(__VA_ARGS__) -#define vlse16_v_i16m4(...) __riscv_vlse16_v_i16m4(__VA_ARGS__) -#define vlse16_v_i16m8(...) __riscv_vlse16_v_i16m8(__VA_ARGS__) -#define vlse32_v_i32mf2(...) __riscv_vlse32_v_i32mf2(__VA_ARGS__) -#define vlse32_v_i32m1(...) __riscv_vlse32_v_i32m1(__VA_ARGS__) -#define vlse32_v_i32m2(...) __riscv_vlse32_v_i32m2(__VA_ARGS__) -#define vlse32_v_i32m4(...) __riscv_vlse32_v_i32m4(__VA_ARGS__) -#define vlse32_v_i32m8(...) __riscv_vlse32_v_i32m8(__VA_ARGS__) -#define vlse64_v_i64m1(...) __riscv_vlse64_v_i64m1(__VA_ARGS__) -#define vlse64_v_i64m2(...) __riscv_vlse64_v_i64m2(__VA_ARGS__) -#define vlse64_v_i64m4(...) __riscv_vlse64_v_i64m4(__VA_ARGS__) -#define vlse64_v_i64m8(...) __riscv_vlse64_v_i64m8(__VA_ARGS__) -#define vlse8_v_u8mf8(...) __riscv_vlse8_v_u8mf8(__VA_ARGS__) -#define vlse8_v_u8mf4(...) __riscv_vlse8_v_u8mf4(__VA_ARGS__) -#define vlse8_v_u8mf2(...) __riscv_vlse8_v_u8mf2(__VA_ARGS__) -#define vlse8_v_u8m1(...) __riscv_vlse8_v_u8m1(__VA_ARGS__) -#define vlse8_v_u8m2(...) __riscv_vlse8_v_u8m2(__VA_ARGS__) -#define vlse8_v_u8m4(...) __riscv_vlse8_v_u8m4(__VA_ARGS__) -#define vlse8_v_u8m8(...) __riscv_vlse8_v_u8m8(__VA_ARGS__) -#define vlse16_v_u16mf4(...) __riscv_vlse16_v_u16mf4(__VA_ARGS__) -#define vlse16_v_u16mf2(...) __riscv_vlse16_v_u16mf2(__VA_ARGS__) -#define vlse16_v_u16m1(...) __riscv_vlse16_v_u16m1(__VA_ARGS__) -#define vlse16_v_u16m2(...) __riscv_vlse16_v_u16m2(__VA_ARGS__) -#define vlse16_v_u16m4(...) __riscv_vlse16_v_u16m4(__VA_ARGS__) -#define vlse16_v_u16m8(...) __riscv_vlse16_v_u16m8(__VA_ARGS__) -#define vlse32_v_u32mf2(...) __riscv_vlse32_v_u32mf2(__VA_ARGS__) -#define vlse32_v_u32m1(...) __riscv_vlse32_v_u32m1(__VA_ARGS__) -#define vlse32_v_u32m2(...) __riscv_vlse32_v_u32m2(__VA_ARGS__) -#define vlse32_v_u32m4(...) __riscv_vlse32_v_u32m4(__VA_ARGS__) -#define vlse32_v_u32m8(...) __riscv_vlse32_v_u32m8(__VA_ARGS__) -#define vlse64_v_u64m1(...) __riscv_vlse64_v_u64m1(__VA_ARGS__) -#define vlse64_v_u64m2(...) __riscv_vlse64_v_u64m2(__VA_ARGS__) -#define vlse64_v_u64m4(...) __riscv_vlse64_v_u64m4(__VA_ARGS__) -#define vlse64_v_u64m8(...) __riscv_vlse64_v_u64m8(__VA_ARGS__) -// masked functions -#define vlse16_v_f16mf4_m(...) __riscv_vlse16_v_f16mf4_tumu(__VA_ARGS__) -#define vlse16_v_f16mf2_m(...) __riscv_vlse16_v_f16mf2_tumu(__VA_ARGS__) -#define vlse16_v_f16m1_m(...) __riscv_vlse16_v_f16m1_tumu(__VA_ARGS__) -#define vlse16_v_f16m2_m(...) __riscv_vlse16_v_f16m2_tumu(__VA_ARGS__) -#define vlse16_v_f16m4_m(...) __riscv_vlse16_v_f16m4_tumu(__VA_ARGS__) -#define vlse16_v_f16m8_m(...) __riscv_vlse16_v_f16m8_tumu(__VA_ARGS__) -#define vlse32_v_f32mf2_m(...) __riscv_vlse32_v_f32mf2_tumu(__VA_ARGS__) -#define vlse32_v_f32m1_m(...) __riscv_vlse32_v_f32m1_tumu(__VA_ARGS__) -#define vlse32_v_f32m2_m(...) __riscv_vlse32_v_f32m2_tumu(__VA_ARGS__) -#define vlse32_v_f32m4_m(...) __riscv_vlse32_v_f32m4_tumu(__VA_ARGS__) -#define vlse32_v_f32m8_m(...) __riscv_vlse32_v_f32m8_tumu(__VA_ARGS__) -#define vlse64_v_f64m1_m(...) __riscv_vlse64_v_f64m1_tumu(__VA_ARGS__) -#define vlse64_v_f64m2_m(...) __riscv_vlse64_v_f64m2_tumu(__VA_ARGS__) -#define vlse64_v_f64m4_m(...) __riscv_vlse64_v_f64m4_tumu(__VA_ARGS__) -#define vlse64_v_f64m8_m(...) __riscv_vlse64_v_f64m8_tumu(__VA_ARGS__) -#define vlse8_v_i8mf8_m(...) __riscv_vlse8_v_i8mf8_tumu(__VA_ARGS__) -#define vlse8_v_i8mf4_m(...) __riscv_vlse8_v_i8mf4_tumu(__VA_ARGS__) -#define vlse8_v_i8mf2_m(...) __riscv_vlse8_v_i8mf2_tumu(__VA_ARGS__) -#define vlse8_v_i8m1_m(...) __riscv_vlse8_v_i8m1_tumu(__VA_ARGS__) -#define vlse8_v_i8m2_m(...) __riscv_vlse8_v_i8m2_tumu(__VA_ARGS__) -#define vlse8_v_i8m4_m(...) __riscv_vlse8_v_i8m4_tumu(__VA_ARGS__) -#define vlse8_v_i8m8_m(...) __riscv_vlse8_v_i8m8_tumu(__VA_ARGS__) -#define vlse16_v_i16mf4_m(...) __riscv_vlse16_v_i16mf4_tumu(__VA_ARGS__) -#define vlse16_v_i16mf2_m(...) __riscv_vlse16_v_i16mf2_tumu(__VA_ARGS__) -#define vlse16_v_i16m1_m(...) __riscv_vlse16_v_i16m1_tumu(__VA_ARGS__) -#define vlse16_v_i16m2_m(...) __riscv_vlse16_v_i16m2_tumu(__VA_ARGS__) -#define vlse16_v_i16m4_m(...) __riscv_vlse16_v_i16m4_tumu(__VA_ARGS__) -#define vlse16_v_i16m8_m(...) __riscv_vlse16_v_i16m8_tumu(__VA_ARGS__) -#define vlse32_v_i32mf2_m(...) __riscv_vlse32_v_i32mf2_tumu(__VA_ARGS__) -#define vlse32_v_i32m1_m(...) __riscv_vlse32_v_i32m1_tumu(__VA_ARGS__) -#define vlse32_v_i32m2_m(...) __riscv_vlse32_v_i32m2_tumu(__VA_ARGS__) -#define vlse32_v_i32m4_m(...) __riscv_vlse32_v_i32m4_tumu(__VA_ARGS__) -#define vlse32_v_i32m8_m(...) __riscv_vlse32_v_i32m8_tumu(__VA_ARGS__) -#define vlse64_v_i64m1_m(...) __riscv_vlse64_v_i64m1_tumu(__VA_ARGS__) -#define vlse64_v_i64m2_m(...) __riscv_vlse64_v_i64m2_tumu(__VA_ARGS__) -#define vlse64_v_i64m4_m(...) __riscv_vlse64_v_i64m4_tumu(__VA_ARGS__) -#define vlse64_v_i64m8_m(...) __riscv_vlse64_v_i64m8_tumu(__VA_ARGS__) -#define vlse8_v_u8mf8_m(...) __riscv_vlse8_v_u8mf8_tumu(__VA_ARGS__) -#define vlse8_v_u8mf4_m(...) __riscv_vlse8_v_u8mf4_tumu(__VA_ARGS__) -#define vlse8_v_u8mf2_m(...) __riscv_vlse8_v_u8mf2_tumu(__VA_ARGS__) -#define vlse8_v_u8m1_m(...) __riscv_vlse8_v_u8m1_tumu(__VA_ARGS__) -#define vlse8_v_u8m2_m(...) __riscv_vlse8_v_u8m2_tumu(__VA_ARGS__) -#define vlse8_v_u8m4_m(...) __riscv_vlse8_v_u8m4_tumu(__VA_ARGS__) -#define vlse8_v_u8m8_m(...) __riscv_vlse8_v_u8m8_tumu(__VA_ARGS__) -#define vlse16_v_u16mf4_m(...) __riscv_vlse16_v_u16mf4_tumu(__VA_ARGS__) -#define vlse16_v_u16mf2_m(...) __riscv_vlse16_v_u16mf2_tumu(__VA_ARGS__) -#define vlse16_v_u16m1_m(...) __riscv_vlse16_v_u16m1_tumu(__VA_ARGS__) -#define vlse16_v_u16m2_m(...) __riscv_vlse16_v_u16m2_tumu(__VA_ARGS__) -#define vlse16_v_u16m4_m(...) __riscv_vlse16_v_u16m4_tumu(__VA_ARGS__) -#define vlse16_v_u16m8_m(...) __riscv_vlse16_v_u16m8_tumu(__VA_ARGS__) -#define vlse32_v_u32mf2_m(...) __riscv_vlse32_v_u32mf2_tumu(__VA_ARGS__) -#define vlse32_v_u32m1_m(...) __riscv_vlse32_v_u32m1_tumu(__VA_ARGS__) -#define vlse32_v_u32m2_m(...) __riscv_vlse32_v_u32m2_tumu(__VA_ARGS__) -#define vlse32_v_u32m4_m(...) __riscv_vlse32_v_u32m4_tumu(__VA_ARGS__) -#define vlse32_v_u32m8_m(...) __riscv_vlse32_v_u32m8_tumu(__VA_ARGS__) -#define vlse64_v_u64m1_m(...) __riscv_vlse64_v_u64m1_tumu(__VA_ARGS__) -#define vlse64_v_u64m2_m(...) __riscv_vlse64_v_u64m2_tumu(__VA_ARGS__) -#define vlse64_v_u64m4_m(...) __riscv_vlse64_v_u64m4_tumu(__VA_ARGS__) -#define vlse64_v_u64m8_m(...) __riscv_vlse64_v_u64m8_tumu(__VA_ARGS__) -#define vsse16_v_f16mf4(...) __riscv_vsse16_v_f16mf4(__VA_ARGS__) -#define vsse16_v_f16mf2(...) __riscv_vsse16_v_f16mf2(__VA_ARGS__) -#define vsse16_v_f16m1(...) __riscv_vsse16_v_f16m1(__VA_ARGS__) -#define vsse16_v_f16m2(...) __riscv_vsse16_v_f16m2(__VA_ARGS__) -#define vsse16_v_f16m4(...) __riscv_vsse16_v_f16m4(__VA_ARGS__) -#define vsse16_v_f16m8(...) __riscv_vsse16_v_f16m8(__VA_ARGS__) -#define vsse32_v_f32mf2(...) __riscv_vsse32_v_f32mf2(__VA_ARGS__) -#define vsse32_v_f32m1(...) __riscv_vsse32_v_f32m1(__VA_ARGS__) -#define vsse32_v_f32m2(...) __riscv_vsse32_v_f32m2(__VA_ARGS__) -#define vsse32_v_f32m4(...) __riscv_vsse32_v_f32m4(__VA_ARGS__) -#define vsse32_v_f32m8(...) __riscv_vsse32_v_f32m8(__VA_ARGS__) -#define vsse64_v_f64m1(...) __riscv_vsse64_v_f64m1(__VA_ARGS__) -#define vsse64_v_f64m2(...) __riscv_vsse64_v_f64m2(__VA_ARGS__) -#define vsse64_v_f64m4(...) __riscv_vsse64_v_f64m4(__VA_ARGS__) -#define vsse64_v_f64m8(...) __riscv_vsse64_v_f64m8(__VA_ARGS__) -#define vsse8_v_i8mf8(...) __riscv_vsse8_v_i8mf8(__VA_ARGS__) -#define vsse8_v_i8mf4(...) __riscv_vsse8_v_i8mf4(__VA_ARGS__) -#define vsse8_v_i8mf2(...) __riscv_vsse8_v_i8mf2(__VA_ARGS__) -#define vsse8_v_i8m1(...) __riscv_vsse8_v_i8m1(__VA_ARGS__) -#define vsse8_v_i8m2(...) __riscv_vsse8_v_i8m2(__VA_ARGS__) -#define vsse8_v_i8m4(...) __riscv_vsse8_v_i8m4(__VA_ARGS__) -#define vsse8_v_i8m8(...) __riscv_vsse8_v_i8m8(__VA_ARGS__) -#define vsse16_v_i16mf4(...) __riscv_vsse16_v_i16mf4(__VA_ARGS__) -#define vsse16_v_i16mf2(...) __riscv_vsse16_v_i16mf2(__VA_ARGS__) -#define vsse16_v_i16m1(...) __riscv_vsse16_v_i16m1(__VA_ARGS__) -#define vsse16_v_i16m2(...) __riscv_vsse16_v_i16m2(__VA_ARGS__) -#define vsse16_v_i16m4(...) __riscv_vsse16_v_i16m4(__VA_ARGS__) -#define vsse16_v_i16m8(...) __riscv_vsse16_v_i16m8(__VA_ARGS__) -#define vsse32_v_i32mf2(...) __riscv_vsse32_v_i32mf2(__VA_ARGS__) -#define vsse32_v_i32m1(...) __riscv_vsse32_v_i32m1(__VA_ARGS__) -#define vsse32_v_i32m2(...) __riscv_vsse32_v_i32m2(__VA_ARGS__) -#define vsse32_v_i32m4(...) __riscv_vsse32_v_i32m4(__VA_ARGS__) -#define vsse32_v_i32m8(...) __riscv_vsse32_v_i32m8(__VA_ARGS__) -#define vsse64_v_i64m1(...) __riscv_vsse64_v_i64m1(__VA_ARGS__) -#define vsse64_v_i64m2(...) __riscv_vsse64_v_i64m2(__VA_ARGS__) -#define vsse64_v_i64m4(...) __riscv_vsse64_v_i64m4(__VA_ARGS__) -#define vsse64_v_i64m8(...) __riscv_vsse64_v_i64m8(__VA_ARGS__) -#define vsse8_v_u8mf8(...) __riscv_vsse8_v_u8mf8(__VA_ARGS__) -#define vsse8_v_u8mf4(...) __riscv_vsse8_v_u8mf4(__VA_ARGS__) -#define vsse8_v_u8mf2(...) __riscv_vsse8_v_u8mf2(__VA_ARGS__) -#define vsse8_v_u8m1(...) __riscv_vsse8_v_u8m1(__VA_ARGS__) -#define vsse8_v_u8m2(...) __riscv_vsse8_v_u8m2(__VA_ARGS__) -#define vsse8_v_u8m4(...) __riscv_vsse8_v_u8m4(__VA_ARGS__) -#define vsse8_v_u8m8(...) __riscv_vsse8_v_u8m8(__VA_ARGS__) -#define vsse16_v_u16mf4(...) __riscv_vsse16_v_u16mf4(__VA_ARGS__) -#define vsse16_v_u16mf2(...) __riscv_vsse16_v_u16mf2(__VA_ARGS__) -#define vsse16_v_u16m1(...) __riscv_vsse16_v_u16m1(__VA_ARGS__) -#define vsse16_v_u16m2(...) __riscv_vsse16_v_u16m2(__VA_ARGS__) -#define vsse16_v_u16m4(...) __riscv_vsse16_v_u16m4(__VA_ARGS__) -#define vsse16_v_u16m8(...) __riscv_vsse16_v_u16m8(__VA_ARGS__) -#define vsse32_v_u32mf2(...) __riscv_vsse32_v_u32mf2(__VA_ARGS__) -#define vsse32_v_u32m1(...) __riscv_vsse32_v_u32m1(__VA_ARGS__) -#define vsse32_v_u32m2(...) __riscv_vsse32_v_u32m2(__VA_ARGS__) -#define vsse32_v_u32m4(...) __riscv_vsse32_v_u32m4(__VA_ARGS__) -#define vsse32_v_u32m8(...) __riscv_vsse32_v_u32m8(__VA_ARGS__) -#define vsse64_v_u64m1(...) __riscv_vsse64_v_u64m1(__VA_ARGS__) -#define vsse64_v_u64m2(...) __riscv_vsse64_v_u64m2(__VA_ARGS__) -#define vsse64_v_u64m4(...) __riscv_vsse64_v_u64m4(__VA_ARGS__) -#define vsse64_v_u64m8(...) __riscv_vsse64_v_u64m8(__VA_ARGS__) -// masked functions -#define vsse16_v_f16mf4_m(...) __riscv_vsse16_v_f16mf4_m(__VA_ARGS__) -#define vsse16_v_f16mf2_m(...) __riscv_vsse16_v_f16mf2_m(__VA_ARGS__) -#define vsse16_v_f16m1_m(...) __riscv_vsse16_v_f16m1_m(__VA_ARGS__) -#define vsse16_v_f16m2_m(...) __riscv_vsse16_v_f16m2_m(__VA_ARGS__) -#define vsse16_v_f16m4_m(...) __riscv_vsse16_v_f16m4_m(__VA_ARGS__) -#define vsse16_v_f16m8_m(...) __riscv_vsse16_v_f16m8_m(__VA_ARGS__) -#define vsse32_v_f32mf2_m(...) __riscv_vsse32_v_f32mf2_m(__VA_ARGS__) -#define vsse32_v_f32m1_m(...) __riscv_vsse32_v_f32m1_m(__VA_ARGS__) -#define vsse32_v_f32m2_m(...) __riscv_vsse32_v_f32m2_m(__VA_ARGS__) -#define vsse32_v_f32m4_m(...) __riscv_vsse32_v_f32m4_m(__VA_ARGS__) -#define vsse32_v_f32m8_m(...) __riscv_vsse32_v_f32m8_m(__VA_ARGS__) -#define vsse64_v_f64m1_m(...) __riscv_vsse64_v_f64m1_m(__VA_ARGS__) -#define vsse64_v_f64m2_m(...) __riscv_vsse64_v_f64m2_m(__VA_ARGS__) -#define vsse64_v_f64m4_m(...) __riscv_vsse64_v_f64m4_m(__VA_ARGS__) -#define vsse64_v_f64m8_m(...) __riscv_vsse64_v_f64m8_m(__VA_ARGS__) -#define vsse8_v_i8mf8_m(...) __riscv_vsse8_v_i8mf8_m(__VA_ARGS__) -#define vsse8_v_i8mf4_m(...) __riscv_vsse8_v_i8mf4_m(__VA_ARGS__) -#define vsse8_v_i8mf2_m(...) __riscv_vsse8_v_i8mf2_m(__VA_ARGS__) -#define vsse8_v_i8m1_m(...) __riscv_vsse8_v_i8m1_m(__VA_ARGS__) -#define vsse8_v_i8m2_m(...) __riscv_vsse8_v_i8m2_m(__VA_ARGS__) -#define vsse8_v_i8m4_m(...) __riscv_vsse8_v_i8m4_m(__VA_ARGS__) -#define vsse8_v_i8m8_m(...) __riscv_vsse8_v_i8m8_m(__VA_ARGS__) -#define vsse16_v_i16mf4_m(...) __riscv_vsse16_v_i16mf4_m(__VA_ARGS__) -#define vsse16_v_i16mf2_m(...) __riscv_vsse16_v_i16mf2_m(__VA_ARGS__) -#define vsse16_v_i16m1_m(...) __riscv_vsse16_v_i16m1_m(__VA_ARGS__) -#define vsse16_v_i16m2_m(...) __riscv_vsse16_v_i16m2_m(__VA_ARGS__) -#define vsse16_v_i16m4_m(...) __riscv_vsse16_v_i16m4_m(__VA_ARGS__) -#define vsse16_v_i16m8_m(...) __riscv_vsse16_v_i16m8_m(__VA_ARGS__) -#define vsse32_v_i32mf2_m(...) __riscv_vsse32_v_i32mf2_m(__VA_ARGS__) -#define vsse32_v_i32m1_m(...) __riscv_vsse32_v_i32m1_m(__VA_ARGS__) -#define vsse32_v_i32m2_m(...) __riscv_vsse32_v_i32m2_m(__VA_ARGS__) -#define vsse32_v_i32m4_m(...) __riscv_vsse32_v_i32m4_m(__VA_ARGS__) -#define vsse32_v_i32m8_m(...) __riscv_vsse32_v_i32m8_m(__VA_ARGS__) -#define vsse64_v_i64m1_m(...) __riscv_vsse64_v_i64m1_m(__VA_ARGS__) -#define vsse64_v_i64m2_m(...) __riscv_vsse64_v_i64m2_m(__VA_ARGS__) -#define vsse64_v_i64m4_m(...) __riscv_vsse64_v_i64m4_m(__VA_ARGS__) -#define vsse64_v_i64m8_m(...) __riscv_vsse64_v_i64m8_m(__VA_ARGS__) -#define vsse8_v_u8mf8_m(...) __riscv_vsse8_v_u8mf8_m(__VA_ARGS__) -#define vsse8_v_u8mf4_m(...) __riscv_vsse8_v_u8mf4_m(__VA_ARGS__) -#define vsse8_v_u8mf2_m(...) __riscv_vsse8_v_u8mf2_m(__VA_ARGS__) -#define vsse8_v_u8m1_m(...) __riscv_vsse8_v_u8m1_m(__VA_ARGS__) -#define vsse8_v_u8m2_m(...) __riscv_vsse8_v_u8m2_m(__VA_ARGS__) -#define vsse8_v_u8m4_m(...) __riscv_vsse8_v_u8m4_m(__VA_ARGS__) -#define vsse8_v_u8m8_m(...) __riscv_vsse8_v_u8m8_m(__VA_ARGS__) -#define vsse16_v_u16mf4_m(...) __riscv_vsse16_v_u16mf4_m(__VA_ARGS__) -#define vsse16_v_u16mf2_m(...) __riscv_vsse16_v_u16mf2_m(__VA_ARGS__) -#define vsse16_v_u16m1_m(...) __riscv_vsse16_v_u16m1_m(__VA_ARGS__) -#define vsse16_v_u16m2_m(...) __riscv_vsse16_v_u16m2_m(__VA_ARGS__) -#define vsse16_v_u16m4_m(...) __riscv_vsse16_v_u16m4_m(__VA_ARGS__) -#define vsse16_v_u16m8_m(...) __riscv_vsse16_v_u16m8_m(__VA_ARGS__) -#define vsse32_v_u32mf2_m(...) __riscv_vsse32_v_u32mf2_m(__VA_ARGS__) -#define vsse32_v_u32m1_m(...) __riscv_vsse32_v_u32m1_m(__VA_ARGS__) -#define vsse32_v_u32m2_m(...) __riscv_vsse32_v_u32m2_m(__VA_ARGS__) -#define vsse32_v_u32m4_m(...) __riscv_vsse32_v_u32m4_m(__VA_ARGS__) -#define vsse32_v_u32m8_m(...) __riscv_vsse32_v_u32m8_m(__VA_ARGS__) -#define vsse64_v_u64m1_m(...) __riscv_vsse64_v_u64m1_m(__VA_ARGS__) -#define vsse64_v_u64m2_m(...) __riscv_vsse64_v_u64m2_m(__VA_ARGS__) -#define vsse64_v_u64m4_m(...) __riscv_vsse64_v_u64m4_m(__VA_ARGS__) -#define vsse64_v_u64m8_m(...) __riscv_vsse64_v_u64m8_m(__VA_ARGS__) -#define vloxei8_v_f16mf4(...) __riscv_vloxei8_v_f16mf4(__VA_ARGS__) -#define vloxei8_v_f16mf2(...) __riscv_vloxei8_v_f16mf2(__VA_ARGS__) -#define vloxei8_v_f16m1(...) __riscv_vloxei8_v_f16m1(__VA_ARGS__) -#define vloxei8_v_f16m2(...) __riscv_vloxei8_v_f16m2(__VA_ARGS__) -#define vloxei8_v_f16m4(...) __riscv_vloxei8_v_f16m4(__VA_ARGS__) -#define vloxei8_v_f16m8(...) __riscv_vloxei8_v_f16m8(__VA_ARGS__) -#define vloxei16_v_f16mf4(...) __riscv_vloxei16_v_f16mf4(__VA_ARGS__) -#define vloxei16_v_f16mf2(...) __riscv_vloxei16_v_f16mf2(__VA_ARGS__) -#define vloxei16_v_f16m1(...) __riscv_vloxei16_v_f16m1(__VA_ARGS__) -#define vloxei16_v_f16m2(...) __riscv_vloxei16_v_f16m2(__VA_ARGS__) -#define vloxei16_v_f16m4(...) __riscv_vloxei16_v_f16m4(__VA_ARGS__) -#define vloxei16_v_f16m8(...) __riscv_vloxei16_v_f16m8(__VA_ARGS__) -#define vloxei32_v_f16mf4(...) __riscv_vloxei32_v_f16mf4(__VA_ARGS__) -#define vloxei32_v_f16mf2(...) __riscv_vloxei32_v_f16mf2(__VA_ARGS__) -#define vloxei32_v_f16m1(...) __riscv_vloxei32_v_f16m1(__VA_ARGS__) -#define vloxei32_v_f16m2(...) __riscv_vloxei32_v_f16m2(__VA_ARGS__) -#define vloxei32_v_f16m4(...) __riscv_vloxei32_v_f16m4(__VA_ARGS__) -#define vloxei64_v_f16mf4(...) __riscv_vloxei64_v_f16mf4(__VA_ARGS__) -#define vloxei64_v_f16mf2(...) __riscv_vloxei64_v_f16mf2(__VA_ARGS__) -#define vloxei64_v_f16m1(...) __riscv_vloxei64_v_f16m1(__VA_ARGS__) -#define vloxei64_v_f16m2(...) __riscv_vloxei64_v_f16m2(__VA_ARGS__) -#define vloxei8_v_f32mf2(...) __riscv_vloxei8_v_f32mf2(__VA_ARGS__) -#define vloxei8_v_f32m1(...) __riscv_vloxei8_v_f32m1(__VA_ARGS__) -#define vloxei8_v_f32m2(...) __riscv_vloxei8_v_f32m2(__VA_ARGS__) -#define vloxei8_v_f32m4(...) __riscv_vloxei8_v_f32m4(__VA_ARGS__) -#define vloxei8_v_f32m8(...) __riscv_vloxei8_v_f32m8(__VA_ARGS__) -#define vloxei16_v_f32mf2(...) __riscv_vloxei16_v_f32mf2(__VA_ARGS__) -#define vloxei16_v_f32m1(...) __riscv_vloxei16_v_f32m1(__VA_ARGS__) -#define vloxei16_v_f32m2(...) __riscv_vloxei16_v_f32m2(__VA_ARGS__) -#define vloxei16_v_f32m4(...) __riscv_vloxei16_v_f32m4(__VA_ARGS__) -#define vloxei16_v_f32m8(...) __riscv_vloxei16_v_f32m8(__VA_ARGS__) -#define vloxei32_v_f32mf2(...) __riscv_vloxei32_v_f32mf2(__VA_ARGS__) -#define vloxei32_v_f32m1(...) __riscv_vloxei32_v_f32m1(__VA_ARGS__) -#define vloxei32_v_f32m2(...) __riscv_vloxei32_v_f32m2(__VA_ARGS__) -#define vloxei32_v_f32m4(...) __riscv_vloxei32_v_f32m4(__VA_ARGS__) -#define vloxei32_v_f32m8(...) __riscv_vloxei32_v_f32m8(__VA_ARGS__) -#define vloxei64_v_f32mf2(...) __riscv_vloxei64_v_f32mf2(__VA_ARGS__) -#define vloxei64_v_f32m1(...) __riscv_vloxei64_v_f32m1(__VA_ARGS__) -#define vloxei64_v_f32m2(...) __riscv_vloxei64_v_f32m2(__VA_ARGS__) -#define vloxei64_v_f32m4(...) __riscv_vloxei64_v_f32m4(__VA_ARGS__) -#define vloxei8_v_f64m1(...) __riscv_vloxei8_v_f64m1(__VA_ARGS__) -#define vloxei8_v_f64m2(...) __riscv_vloxei8_v_f64m2(__VA_ARGS__) -#define vloxei8_v_f64m4(...) __riscv_vloxei8_v_f64m4(__VA_ARGS__) -#define vloxei8_v_f64m8(...) __riscv_vloxei8_v_f64m8(__VA_ARGS__) -#define vloxei16_v_f64m1(...) __riscv_vloxei16_v_f64m1(__VA_ARGS__) -#define vloxei16_v_f64m2(...) __riscv_vloxei16_v_f64m2(__VA_ARGS__) -#define vloxei16_v_f64m4(...) __riscv_vloxei16_v_f64m4(__VA_ARGS__) -#define vloxei16_v_f64m8(...) __riscv_vloxei16_v_f64m8(__VA_ARGS__) -#define vloxei32_v_f64m1(...) __riscv_vloxei32_v_f64m1(__VA_ARGS__) -#define vloxei32_v_f64m2(...) __riscv_vloxei32_v_f64m2(__VA_ARGS__) -#define vloxei32_v_f64m4(...) __riscv_vloxei32_v_f64m4(__VA_ARGS__) -#define vloxei32_v_f64m8(...) __riscv_vloxei32_v_f64m8(__VA_ARGS__) -#define vloxei64_v_f64m1(...) __riscv_vloxei64_v_f64m1(__VA_ARGS__) -#define vloxei64_v_f64m2(...) __riscv_vloxei64_v_f64m2(__VA_ARGS__) -#define vloxei64_v_f64m4(...) __riscv_vloxei64_v_f64m4(__VA_ARGS__) -#define vloxei64_v_f64m8(...) __riscv_vloxei64_v_f64m8(__VA_ARGS__) -#define vluxei8_v_f16mf4(...) __riscv_vluxei8_v_f16mf4(__VA_ARGS__) -#define vluxei8_v_f16mf2(...) __riscv_vluxei8_v_f16mf2(__VA_ARGS__) -#define vluxei8_v_f16m1(...) __riscv_vluxei8_v_f16m1(__VA_ARGS__) -#define vluxei8_v_f16m2(...) __riscv_vluxei8_v_f16m2(__VA_ARGS__) -#define vluxei8_v_f16m4(...) __riscv_vluxei8_v_f16m4(__VA_ARGS__) -#define vluxei8_v_f16m8(...) __riscv_vluxei8_v_f16m8(__VA_ARGS__) -#define vluxei16_v_f16mf4(...) __riscv_vluxei16_v_f16mf4(__VA_ARGS__) -#define vluxei16_v_f16mf2(...) __riscv_vluxei16_v_f16mf2(__VA_ARGS__) -#define vluxei16_v_f16m1(...) __riscv_vluxei16_v_f16m1(__VA_ARGS__) -#define vluxei16_v_f16m2(...) __riscv_vluxei16_v_f16m2(__VA_ARGS__) -#define vluxei16_v_f16m4(...) __riscv_vluxei16_v_f16m4(__VA_ARGS__) -#define vluxei16_v_f16m8(...) __riscv_vluxei16_v_f16m8(__VA_ARGS__) -#define vluxei32_v_f16mf4(...) __riscv_vluxei32_v_f16mf4(__VA_ARGS__) -#define vluxei32_v_f16mf2(...) __riscv_vluxei32_v_f16mf2(__VA_ARGS__) -#define vluxei32_v_f16m1(...) __riscv_vluxei32_v_f16m1(__VA_ARGS__) -#define vluxei32_v_f16m2(...) __riscv_vluxei32_v_f16m2(__VA_ARGS__) -#define vluxei32_v_f16m4(...) __riscv_vluxei32_v_f16m4(__VA_ARGS__) -#define vluxei64_v_f16mf4(...) __riscv_vluxei64_v_f16mf4(__VA_ARGS__) -#define vluxei64_v_f16mf2(...) __riscv_vluxei64_v_f16mf2(__VA_ARGS__) -#define vluxei64_v_f16m1(...) __riscv_vluxei64_v_f16m1(__VA_ARGS__) -#define vluxei64_v_f16m2(...) __riscv_vluxei64_v_f16m2(__VA_ARGS__) -#define vluxei8_v_f32mf2(...) __riscv_vluxei8_v_f32mf2(__VA_ARGS__) -#define vluxei8_v_f32m1(...) __riscv_vluxei8_v_f32m1(__VA_ARGS__) -#define vluxei8_v_f32m2(...) __riscv_vluxei8_v_f32m2(__VA_ARGS__) -#define vluxei8_v_f32m4(...) __riscv_vluxei8_v_f32m4(__VA_ARGS__) -#define vluxei8_v_f32m8(...) __riscv_vluxei8_v_f32m8(__VA_ARGS__) -#define vluxei16_v_f32mf2(...) __riscv_vluxei16_v_f32mf2(__VA_ARGS__) -#define vluxei16_v_f32m1(...) __riscv_vluxei16_v_f32m1(__VA_ARGS__) -#define vluxei16_v_f32m2(...) __riscv_vluxei16_v_f32m2(__VA_ARGS__) -#define vluxei16_v_f32m4(...) __riscv_vluxei16_v_f32m4(__VA_ARGS__) -#define vluxei16_v_f32m8(...) __riscv_vluxei16_v_f32m8(__VA_ARGS__) -#define vluxei32_v_f32mf2(...) __riscv_vluxei32_v_f32mf2(__VA_ARGS__) -#define vluxei32_v_f32m1(...) __riscv_vluxei32_v_f32m1(__VA_ARGS__) -#define vluxei32_v_f32m2(...) __riscv_vluxei32_v_f32m2(__VA_ARGS__) -#define vluxei32_v_f32m4(...) __riscv_vluxei32_v_f32m4(__VA_ARGS__) -#define vluxei32_v_f32m8(...) __riscv_vluxei32_v_f32m8(__VA_ARGS__) -#define vluxei64_v_f32mf2(...) __riscv_vluxei64_v_f32mf2(__VA_ARGS__) -#define vluxei64_v_f32m1(...) __riscv_vluxei64_v_f32m1(__VA_ARGS__) -#define vluxei64_v_f32m2(...) __riscv_vluxei64_v_f32m2(__VA_ARGS__) -#define vluxei64_v_f32m4(...) __riscv_vluxei64_v_f32m4(__VA_ARGS__) -#define vluxei8_v_f64m1(...) __riscv_vluxei8_v_f64m1(__VA_ARGS__) -#define vluxei8_v_f64m2(...) __riscv_vluxei8_v_f64m2(__VA_ARGS__) -#define vluxei8_v_f64m4(...) __riscv_vluxei8_v_f64m4(__VA_ARGS__) -#define vluxei8_v_f64m8(...) __riscv_vluxei8_v_f64m8(__VA_ARGS__) -#define vluxei16_v_f64m1(...) __riscv_vluxei16_v_f64m1(__VA_ARGS__) -#define vluxei16_v_f64m2(...) __riscv_vluxei16_v_f64m2(__VA_ARGS__) -#define vluxei16_v_f64m4(...) __riscv_vluxei16_v_f64m4(__VA_ARGS__) -#define vluxei16_v_f64m8(...) __riscv_vluxei16_v_f64m8(__VA_ARGS__) -#define vluxei32_v_f64m1(...) __riscv_vluxei32_v_f64m1(__VA_ARGS__) -#define vluxei32_v_f64m2(...) __riscv_vluxei32_v_f64m2(__VA_ARGS__) -#define vluxei32_v_f64m4(...) __riscv_vluxei32_v_f64m4(__VA_ARGS__) -#define vluxei32_v_f64m8(...) __riscv_vluxei32_v_f64m8(__VA_ARGS__) -#define vluxei64_v_f64m1(...) __riscv_vluxei64_v_f64m1(__VA_ARGS__) -#define vluxei64_v_f64m2(...) __riscv_vluxei64_v_f64m2(__VA_ARGS__) -#define vluxei64_v_f64m4(...) __riscv_vluxei64_v_f64m4(__VA_ARGS__) -#define vluxei64_v_f64m8(...) __riscv_vluxei64_v_f64m8(__VA_ARGS__) -#define vloxei8_v_i8mf8(...) __riscv_vloxei8_v_i8mf8(__VA_ARGS__) -#define vloxei8_v_i8mf4(...) __riscv_vloxei8_v_i8mf4(__VA_ARGS__) -#define vloxei8_v_i8mf2(...) __riscv_vloxei8_v_i8mf2(__VA_ARGS__) -#define vloxei8_v_i8m1(...) __riscv_vloxei8_v_i8m1(__VA_ARGS__) -#define vloxei8_v_i8m2(...) __riscv_vloxei8_v_i8m2(__VA_ARGS__) -#define vloxei8_v_i8m4(...) __riscv_vloxei8_v_i8m4(__VA_ARGS__) -#define vloxei8_v_i8m8(...) __riscv_vloxei8_v_i8m8(__VA_ARGS__) -#define vloxei16_v_i8mf8(...) __riscv_vloxei16_v_i8mf8(__VA_ARGS__) -#define vloxei16_v_i8mf4(...) __riscv_vloxei16_v_i8mf4(__VA_ARGS__) -#define vloxei16_v_i8mf2(...) __riscv_vloxei16_v_i8mf2(__VA_ARGS__) -#define vloxei16_v_i8m1(...) __riscv_vloxei16_v_i8m1(__VA_ARGS__) -#define vloxei16_v_i8m2(...) __riscv_vloxei16_v_i8m2(__VA_ARGS__) -#define vloxei16_v_i8m4(...) __riscv_vloxei16_v_i8m4(__VA_ARGS__) -#define vloxei32_v_i8mf8(...) __riscv_vloxei32_v_i8mf8(__VA_ARGS__) -#define vloxei32_v_i8mf4(...) __riscv_vloxei32_v_i8mf4(__VA_ARGS__) -#define vloxei32_v_i8mf2(...) __riscv_vloxei32_v_i8mf2(__VA_ARGS__) -#define vloxei32_v_i8m1(...) __riscv_vloxei32_v_i8m1(__VA_ARGS__) -#define vloxei32_v_i8m2(...) __riscv_vloxei32_v_i8m2(__VA_ARGS__) -#define vloxei64_v_i8mf8(...) __riscv_vloxei64_v_i8mf8(__VA_ARGS__) -#define vloxei64_v_i8mf4(...) __riscv_vloxei64_v_i8mf4(__VA_ARGS__) -#define vloxei64_v_i8mf2(...) __riscv_vloxei64_v_i8mf2(__VA_ARGS__) -#define vloxei64_v_i8m1(...) __riscv_vloxei64_v_i8m1(__VA_ARGS__) -#define vloxei8_v_i16mf4(...) __riscv_vloxei8_v_i16mf4(__VA_ARGS__) -#define vloxei8_v_i16mf2(...) __riscv_vloxei8_v_i16mf2(__VA_ARGS__) -#define vloxei8_v_i16m1(...) __riscv_vloxei8_v_i16m1(__VA_ARGS__) -#define vloxei8_v_i16m2(...) __riscv_vloxei8_v_i16m2(__VA_ARGS__) -#define vloxei8_v_i16m4(...) __riscv_vloxei8_v_i16m4(__VA_ARGS__) -#define vloxei8_v_i16m8(...) __riscv_vloxei8_v_i16m8(__VA_ARGS__) -#define vloxei16_v_i16mf4(...) __riscv_vloxei16_v_i16mf4(__VA_ARGS__) -#define vloxei16_v_i16mf2(...) __riscv_vloxei16_v_i16mf2(__VA_ARGS__) -#define vloxei16_v_i16m1(...) __riscv_vloxei16_v_i16m1(__VA_ARGS__) -#define vloxei16_v_i16m2(...) __riscv_vloxei16_v_i16m2(__VA_ARGS__) -#define vloxei16_v_i16m4(...) __riscv_vloxei16_v_i16m4(__VA_ARGS__) -#define vloxei16_v_i16m8(...) __riscv_vloxei16_v_i16m8(__VA_ARGS__) -#define vloxei32_v_i16mf4(...) __riscv_vloxei32_v_i16mf4(__VA_ARGS__) -#define vloxei32_v_i16mf2(...) __riscv_vloxei32_v_i16mf2(__VA_ARGS__) -#define vloxei32_v_i16m1(...) __riscv_vloxei32_v_i16m1(__VA_ARGS__) -#define vloxei32_v_i16m2(...) __riscv_vloxei32_v_i16m2(__VA_ARGS__) -#define vloxei32_v_i16m4(...) __riscv_vloxei32_v_i16m4(__VA_ARGS__) -#define vloxei64_v_i16mf4(...) __riscv_vloxei64_v_i16mf4(__VA_ARGS__) -#define vloxei64_v_i16mf2(...) __riscv_vloxei64_v_i16mf2(__VA_ARGS__) -#define vloxei64_v_i16m1(...) __riscv_vloxei64_v_i16m1(__VA_ARGS__) -#define vloxei64_v_i16m2(...) __riscv_vloxei64_v_i16m2(__VA_ARGS__) -#define vloxei8_v_i32mf2(...) __riscv_vloxei8_v_i32mf2(__VA_ARGS__) -#define vloxei8_v_i32m1(...) __riscv_vloxei8_v_i32m1(__VA_ARGS__) -#define vloxei8_v_i32m2(...) __riscv_vloxei8_v_i32m2(__VA_ARGS__) -#define vloxei8_v_i32m4(...) __riscv_vloxei8_v_i32m4(__VA_ARGS__) -#define vloxei8_v_i32m8(...) __riscv_vloxei8_v_i32m8(__VA_ARGS__) -#define vloxei16_v_i32mf2(...) __riscv_vloxei16_v_i32mf2(__VA_ARGS__) -#define vloxei16_v_i32m1(...) __riscv_vloxei16_v_i32m1(__VA_ARGS__) -#define vloxei16_v_i32m2(...) __riscv_vloxei16_v_i32m2(__VA_ARGS__) -#define vloxei16_v_i32m4(...) __riscv_vloxei16_v_i32m4(__VA_ARGS__) -#define vloxei16_v_i32m8(...) __riscv_vloxei16_v_i32m8(__VA_ARGS__) -#define vloxei32_v_i32mf2(...) __riscv_vloxei32_v_i32mf2(__VA_ARGS__) -#define vloxei32_v_i32m1(...) __riscv_vloxei32_v_i32m1(__VA_ARGS__) -#define vloxei32_v_i32m2(...) __riscv_vloxei32_v_i32m2(__VA_ARGS__) -#define vloxei32_v_i32m4(...) __riscv_vloxei32_v_i32m4(__VA_ARGS__) -#define vloxei32_v_i32m8(...) __riscv_vloxei32_v_i32m8(__VA_ARGS__) -#define vloxei64_v_i32mf2(...) __riscv_vloxei64_v_i32mf2(__VA_ARGS__) -#define vloxei64_v_i32m1(...) __riscv_vloxei64_v_i32m1(__VA_ARGS__) -#define vloxei64_v_i32m2(...) __riscv_vloxei64_v_i32m2(__VA_ARGS__) -#define vloxei64_v_i32m4(...) __riscv_vloxei64_v_i32m4(__VA_ARGS__) -#define vloxei8_v_i64m1(...) __riscv_vloxei8_v_i64m1(__VA_ARGS__) -#define vloxei8_v_i64m2(...) __riscv_vloxei8_v_i64m2(__VA_ARGS__) -#define vloxei8_v_i64m4(...) __riscv_vloxei8_v_i64m4(__VA_ARGS__) -#define vloxei8_v_i64m8(...) __riscv_vloxei8_v_i64m8(__VA_ARGS__) -#define vloxei16_v_i64m1(...) __riscv_vloxei16_v_i64m1(__VA_ARGS__) -#define vloxei16_v_i64m2(...) __riscv_vloxei16_v_i64m2(__VA_ARGS__) -#define vloxei16_v_i64m4(...) __riscv_vloxei16_v_i64m4(__VA_ARGS__) -#define vloxei16_v_i64m8(...) __riscv_vloxei16_v_i64m8(__VA_ARGS__) -#define vloxei32_v_i64m1(...) __riscv_vloxei32_v_i64m1(__VA_ARGS__) -#define vloxei32_v_i64m2(...) __riscv_vloxei32_v_i64m2(__VA_ARGS__) -#define vloxei32_v_i64m4(...) __riscv_vloxei32_v_i64m4(__VA_ARGS__) -#define vloxei32_v_i64m8(...) __riscv_vloxei32_v_i64m8(__VA_ARGS__) -#define vloxei64_v_i64m1(...) __riscv_vloxei64_v_i64m1(__VA_ARGS__) -#define vloxei64_v_i64m2(...) __riscv_vloxei64_v_i64m2(__VA_ARGS__) -#define vloxei64_v_i64m4(...) __riscv_vloxei64_v_i64m4(__VA_ARGS__) -#define vloxei64_v_i64m8(...) __riscv_vloxei64_v_i64m8(__VA_ARGS__) -#define vluxei8_v_i8mf8(...) __riscv_vluxei8_v_i8mf8(__VA_ARGS__) -#define vluxei8_v_i8mf4(...) __riscv_vluxei8_v_i8mf4(__VA_ARGS__) -#define vluxei8_v_i8mf2(...) __riscv_vluxei8_v_i8mf2(__VA_ARGS__) -#define vluxei8_v_i8m1(...) __riscv_vluxei8_v_i8m1(__VA_ARGS__) -#define vluxei8_v_i8m2(...) __riscv_vluxei8_v_i8m2(__VA_ARGS__) -#define vluxei8_v_i8m4(...) __riscv_vluxei8_v_i8m4(__VA_ARGS__) -#define vluxei8_v_i8m8(...) __riscv_vluxei8_v_i8m8(__VA_ARGS__) -#define vluxei16_v_i8mf8(...) __riscv_vluxei16_v_i8mf8(__VA_ARGS__) -#define vluxei16_v_i8mf4(...) __riscv_vluxei16_v_i8mf4(__VA_ARGS__) -#define vluxei16_v_i8mf2(...) __riscv_vluxei16_v_i8mf2(__VA_ARGS__) -#define vluxei16_v_i8m1(...) __riscv_vluxei16_v_i8m1(__VA_ARGS__) -#define vluxei16_v_i8m2(...) __riscv_vluxei16_v_i8m2(__VA_ARGS__) -#define vluxei16_v_i8m4(...) __riscv_vluxei16_v_i8m4(__VA_ARGS__) -#define vluxei32_v_i8mf8(...) __riscv_vluxei32_v_i8mf8(__VA_ARGS__) -#define vluxei32_v_i8mf4(...) __riscv_vluxei32_v_i8mf4(__VA_ARGS__) -#define vluxei32_v_i8mf2(...) __riscv_vluxei32_v_i8mf2(__VA_ARGS__) -#define vluxei32_v_i8m1(...) __riscv_vluxei32_v_i8m1(__VA_ARGS__) -#define vluxei32_v_i8m2(...) __riscv_vluxei32_v_i8m2(__VA_ARGS__) -#define vluxei64_v_i8mf8(...) __riscv_vluxei64_v_i8mf8(__VA_ARGS__) -#define vluxei64_v_i8mf4(...) __riscv_vluxei64_v_i8mf4(__VA_ARGS__) -#define vluxei64_v_i8mf2(...) __riscv_vluxei64_v_i8mf2(__VA_ARGS__) -#define vluxei64_v_i8m1(...) __riscv_vluxei64_v_i8m1(__VA_ARGS__) -#define vluxei8_v_i16mf4(...) __riscv_vluxei8_v_i16mf4(__VA_ARGS__) -#define vluxei8_v_i16mf2(...) __riscv_vluxei8_v_i16mf2(__VA_ARGS__) -#define vluxei8_v_i16m1(...) __riscv_vluxei8_v_i16m1(__VA_ARGS__) -#define vluxei8_v_i16m2(...) __riscv_vluxei8_v_i16m2(__VA_ARGS__) -#define vluxei8_v_i16m4(...) __riscv_vluxei8_v_i16m4(__VA_ARGS__) -#define vluxei8_v_i16m8(...) __riscv_vluxei8_v_i16m8(__VA_ARGS__) -#define vluxei16_v_i16mf4(...) __riscv_vluxei16_v_i16mf4(__VA_ARGS__) -#define vluxei16_v_i16mf2(...) __riscv_vluxei16_v_i16mf2(__VA_ARGS__) -#define vluxei16_v_i16m1(...) __riscv_vluxei16_v_i16m1(__VA_ARGS__) -#define vluxei16_v_i16m2(...) __riscv_vluxei16_v_i16m2(__VA_ARGS__) -#define vluxei16_v_i16m4(...) __riscv_vluxei16_v_i16m4(__VA_ARGS__) -#define vluxei16_v_i16m8(...) __riscv_vluxei16_v_i16m8(__VA_ARGS__) -#define vluxei32_v_i16mf4(...) __riscv_vluxei32_v_i16mf4(__VA_ARGS__) -#define vluxei32_v_i16mf2(...) __riscv_vluxei32_v_i16mf2(__VA_ARGS__) -#define vluxei32_v_i16m1(...) __riscv_vluxei32_v_i16m1(__VA_ARGS__) -#define vluxei32_v_i16m2(...) __riscv_vluxei32_v_i16m2(__VA_ARGS__) -#define vluxei32_v_i16m4(...) __riscv_vluxei32_v_i16m4(__VA_ARGS__) -#define vluxei64_v_i16mf4(...) __riscv_vluxei64_v_i16mf4(__VA_ARGS__) -#define vluxei64_v_i16mf2(...) __riscv_vluxei64_v_i16mf2(__VA_ARGS__) -#define vluxei64_v_i16m1(...) __riscv_vluxei64_v_i16m1(__VA_ARGS__) -#define vluxei64_v_i16m2(...) __riscv_vluxei64_v_i16m2(__VA_ARGS__) -#define vluxei8_v_i32mf2(...) __riscv_vluxei8_v_i32mf2(__VA_ARGS__) -#define vluxei8_v_i32m1(...) __riscv_vluxei8_v_i32m1(__VA_ARGS__) -#define vluxei8_v_i32m2(...) __riscv_vluxei8_v_i32m2(__VA_ARGS__) -#define vluxei8_v_i32m4(...) __riscv_vluxei8_v_i32m4(__VA_ARGS__) -#define vluxei8_v_i32m8(...) __riscv_vluxei8_v_i32m8(__VA_ARGS__) -#define vluxei16_v_i32mf2(...) __riscv_vluxei16_v_i32mf2(__VA_ARGS__) -#define vluxei16_v_i32m1(...) __riscv_vluxei16_v_i32m1(__VA_ARGS__) -#define vluxei16_v_i32m2(...) __riscv_vluxei16_v_i32m2(__VA_ARGS__) -#define vluxei16_v_i32m4(...) __riscv_vluxei16_v_i32m4(__VA_ARGS__) -#define vluxei16_v_i32m8(...) __riscv_vluxei16_v_i32m8(__VA_ARGS__) -#define vluxei32_v_i32mf2(...) __riscv_vluxei32_v_i32mf2(__VA_ARGS__) -#define vluxei32_v_i32m1(...) __riscv_vluxei32_v_i32m1(__VA_ARGS__) -#define vluxei32_v_i32m2(...) __riscv_vluxei32_v_i32m2(__VA_ARGS__) -#define vluxei32_v_i32m4(...) __riscv_vluxei32_v_i32m4(__VA_ARGS__) -#define vluxei32_v_i32m8(...) __riscv_vluxei32_v_i32m8(__VA_ARGS__) -#define vluxei64_v_i32mf2(...) __riscv_vluxei64_v_i32mf2(__VA_ARGS__) -#define vluxei64_v_i32m1(...) __riscv_vluxei64_v_i32m1(__VA_ARGS__) -#define vluxei64_v_i32m2(...) __riscv_vluxei64_v_i32m2(__VA_ARGS__) -#define vluxei64_v_i32m4(...) __riscv_vluxei64_v_i32m4(__VA_ARGS__) -#define vluxei8_v_i64m1(...) __riscv_vluxei8_v_i64m1(__VA_ARGS__) -#define vluxei8_v_i64m2(...) __riscv_vluxei8_v_i64m2(__VA_ARGS__) -#define vluxei8_v_i64m4(...) __riscv_vluxei8_v_i64m4(__VA_ARGS__) -#define vluxei8_v_i64m8(...) __riscv_vluxei8_v_i64m8(__VA_ARGS__) -#define vluxei16_v_i64m1(...) __riscv_vluxei16_v_i64m1(__VA_ARGS__) -#define vluxei16_v_i64m2(...) __riscv_vluxei16_v_i64m2(__VA_ARGS__) -#define vluxei16_v_i64m4(...) __riscv_vluxei16_v_i64m4(__VA_ARGS__) -#define vluxei16_v_i64m8(...) __riscv_vluxei16_v_i64m8(__VA_ARGS__) -#define vluxei32_v_i64m1(...) __riscv_vluxei32_v_i64m1(__VA_ARGS__) -#define vluxei32_v_i64m2(...) __riscv_vluxei32_v_i64m2(__VA_ARGS__) -#define vluxei32_v_i64m4(...) __riscv_vluxei32_v_i64m4(__VA_ARGS__) -#define vluxei32_v_i64m8(...) __riscv_vluxei32_v_i64m8(__VA_ARGS__) -#define vluxei64_v_i64m1(...) __riscv_vluxei64_v_i64m1(__VA_ARGS__) -#define vluxei64_v_i64m2(...) __riscv_vluxei64_v_i64m2(__VA_ARGS__) -#define vluxei64_v_i64m4(...) __riscv_vluxei64_v_i64m4(__VA_ARGS__) -#define vluxei64_v_i64m8(...) __riscv_vluxei64_v_i64m8(__VA_ARGS__) -#define vloxei8_v_u8mf8(...) __riscv_vloxei8_v_u8mf8(__VA_ARGS__) -#define vloxei8_v_u8mf4(...) __riscv_vloxei8_v_u8mf4(__VA_ARGS__) -#define vloxei8_v_u8mf2(...) __riscv_vloxei8_v_u8mf2(__VA_ARGS__) -#define vloxei8_v_u8m1(...) __riscv_vloxei8_v_u8m1(__VA_ARGS__) -#define vloxei8_v_u8m2(...) __riscv_vloxei8_v_u8m2(__VA_ARGS__) -#define vloxei8_v_u8m4(...) __riscv_vloxei8_v_u8m4(__VA_ARGS__) -#define vloxei8_v_u8m8(...) __riscv_vloxei8_v_u8m8(__VA_ARGS__) -#define vloxei16_v_u8mf8(...) __riscv_vloxei16_v_u8mf8(__VA_ARGS__) -#define vloxei16_v_u8mf4(...) __riscv_vloxei16_v_u8mf4(__VA_ARGS__) -#define vloxei16_v_u8mf2(...) __riscv_vloxei16_v_u8mf2(__VA_ARGS__) -#define vloxei16_v_u8m1(...) __riscv_vloxei16_v_u8m1(__VA_ARGS__) -#define vloxei16_v_u8m2(...) __riscv_vloxei16_v_u8m2(__VA_ARGS__) -#define vloxei16_v_u8m4(...) __riscv_vloxei16_v_u8m4(__VA_ARGS__) -#define vloxei32_v_u8mf8(...) __riscv_vloxei32_v_u8mf8(__VA_ARGS__) -#define vloxei32_v_u8mf4(...) __riscv_vloxei32_v_u8mf4(__VA_ARGS__) -#define vloxei32_v_u8mf2(...) __riscv_vloxei32_v_u8mf2(__VA_ARGS__) -#define vloxei32_v_u8m1(...) __riscv_vloxei32_v_u8m1(__VA_ARGS__) -#define vloxei32_v_u8m2(...) __riscv_vloxei32_v_u8m2(__VA_ARGS__) -#define vloxei64_v_u8mf8(...) __riscv_vloxei64_v_u8mf8(__VA_ARGS__) -#define vloxei64_v_u8mf4(...) __riscv_vloxei64_v_u8mf4(__VA_ARGS__) -#define vloxei64_v_u8mf2(...) __riscv_vloxei64_v_u8mf2(__VA_ARGS__) -#define vloxei64_v_u8m1(...) __riscv_vloxei64_v_u8m1(__VA_ARGS__) -#define vloxei8_v_u16mf4(...) __riscv_vloxei8_v_u16mf4(__VA_ARGS__) -#define vloxei8_v_u16mf2(...) __riscv_vloxei8_v_u16mf2(__VA_ARGS__) -#define vloxei8_v_u16m1(...) __riscv_vloxei8_v_u16m1(__VA_ARGS__) -#define vloxei8_v_u16m2(...) __riscv_vloxei8_v_u16m2(__VA_ARGS__) -#define vloxei8_v_u16m4(...) __riscv_vloxei8_v_u16m4(__VA_ARGS__) -#define vloxei8_v_u16m8(...) __riscv_vloxei8_v_u16m8(__VA_ARGS__) -#define vloxei16_v_u16mf4(...) __riscv_vloxei16_v_u16mf4(__VA_ARGS__) -#define vloxei16_v_u16mf2(...) __riscv_vloxei16_v_u16mf2(__VA_ARGS__) -#define vloxei16_v_u16m1(...) __riscv_vloxei16_v_u16m1(__VA_ARGS__) -#define vloxei16_v_u16m2(...) __riscv_vloxei16_v_u16m2(__VA_ARGS__) -#define vloxei16_v_u16m4(...) __riscv_vloxei16_v_u16m4(__VA_ARGS__) -#define vloxei16_v_u16m8(...) __riscv_vloxei16_v_u16m8(__VA_ARGS__) -#define vloxei32_v_u16mf4(...) __riscv_vloxei32_v_u16mf4(__VA_ARGS__) -#define vloxei32_v_u16mf2(...) __riscv_vloxei32_v_u16mf2(__VA_ARGS__) -#define vloxei32_v_u16m1(...) __riscv_vloxei32_v_u16m1(__VA_ARGS__) -#define vloxei32_v_u16m2(...) __riscv_vloxei32_v_u16m2(__VA_ARGS__) -#define vloxei32_v_u16m4(...) __riscv_vloxei32_v_u16m4(__VA_ARGS__) -#define vloxei64_v_u16mf4(...) __riscv_vloxei64_v_u16mf4(__VA_ARGS__) -#define vloxei64_v_u16mf2(...) __riscv_vloxei64_v_u16mf2(__VA_ARGS__) -#define vloxei64_v_u16m1(...) __riscv_vloxei64_v_u16m1(__VA_ARGS__) -#define vloxei64_v_u16m2(...) __riscv_vloxei64_v_u16m2(__VA_ARGS__) -#define vloxei8_v_u32mf2(...) __riscv_vloxei8_v_u32mf2(__VA_ARGS__) -#define vloxei8_v_u32m1(...) __riscv_vloxei8_v_u32m1(__VA_ARGS__) -#define vloxei8_v_u32m2(...) __riscv_vloxei8_v_u32m2(__VA_ARGS__) -#define vloxei8_v_u32m4(...) __riscv_vloxei8_v_u32m4(__VA_ARGS__) -#define vloxei8_v_u32m8(...) __riscv_vloxei8_v_u32m8(__VA_ARGS__) -#define vloxei16_v_u32mf2(...) __riscv_vloxei16_v_u32mf2(__VA_ARGS__) -#define vloxei16_v_u32m1(...) __riscv_vloxei16_v_u32m1(__VA_ARGS__) -#define vloxei16_v_u32m2(...) __riscv_vloxei16_v_u32m2(__VA_ARGS__) -#define vloxei16_v_u32m4(...) __riscv_vloxei16_v_u32m4(__VA_ARGS__) -#define vloxei16_v_u32m8(...) __riscv_vloxei16_v_u32m8(__VA_ARGS__) -#define vloxei32_v_u32mf2(...) __riscv_vloxei32_v_u32mf2(__VA_ARGS__) -#define vloxei32_v_u32m1(...) __riscv_vloxei32_v_u32m1(__VA_ARGS__) -#define vloxei32_v_u32m2(...) __riscv_vloxei32_v_u32m2(__VA_ARGS__) -#define vloxei32_v_u32m4(...) __riscv_vloxei32_v_u32m4(__VA_ARGS__) -#define vloxei32_v_u32m8(...) __riscv_vloxei32_v_u32m8(__VA_ARGS__) -#define vloxei64_v_u32mf2(...) __riscv_vloxei64_v_u32mf2(__VA_ARGS__) -#define vloxei64_v_u32m1(...) __riscv_vloxei64_v_u32m1(__VA_ARGS__) -#define vloxei64_v_u32m2(...) __riscv_vloxei64_v_u32m2(__VA_ARGS__) -#define vloxei64_v_u32m4(...) __riscv_vloxei64_v_u32m4(__VA_ARGS__) -#define vloxei8_v_u64m1(...) __riscv_vloxei8_v_u64m1(__VA_ARGS__) -#define vloxei8_v_u64m2(...) __riscv_vloxei8_v_u64m2(__VA_ARGS__) -#define vloxei8_v_u64m4(...) __riscv_vloxei8_v_u64m4(__VA_ARGS__) -#define vloxei8_v_u64m8(...) __riscv_vloxei8_v_u64m8(__VA_ARGS__) -#define vloxei16_v_u64m1(...) __riscv_vloxei16_v_u64m1(__VA_ARGS__) -#define vloxei16_v_u64m2(...) __riscv_vloxei16_v_u64m2(__VA_ARGS__) -#define vloxei16_v_u64m4(...) __riscv_vloxei16_v_u64m4(__VA_ARGS__) -#define vloxei16_v_u64m8(...) __riscv_vloxei16_v_u64m8(__VA_ARGS__) -#define vloxei32_v_u64m1(...) __riscv_vloxei32_v_u64m1(__VA_ARGS__) -#define vloxei32_v_u64m2(...) __riscv_vloxei32_v_u64m2(__VA_ARGS__) -#define vloxei32_v_u64m4(...) __riscv_vloxei32_v_u64m4(__VA_ARGS__) -#define vloxei32_v_u64m8(...) __riscv_vloxei32_v_u64m8(__VA_ARGS__) -#define vloxei64_v_u64m1(...) __riscv_vloxei64_v_u64m1(__VA_ARGS__) -#define vloxei64_v_u64m2(...) __riscv_vloxei64_v_u64m2(__VA_ARGS__) -#define vloxei64_v_u64m4(...) __riscv_vloxei64_v_u64m4(__VA_ARGS__) -#define vloxei64_v_u64m8(...) __riscv_vloxei64_v_u64m8(__VA_ARGS__) -#define vluxei8_v_u8mf8(...) __riscv_vluxei8_v_u8mf8(__VA_ARGS__) -#define vluxei8_v_u8mf4(...) __riscv_vluxei8_v_u8mf4(__VA_ARGS__) -#define vluxei8_v_u8mf2(...) __riscv_vluxei8_v_u8mf2(__VA_ARGS__) -#define vluxei8_v_u8m1(...) __riscv_vluxei8_v_u8m1(__VA_ARGS__) -#define vluxei8_v_u8m2(...) __riscv_vluxei8_v_u8m2(__VA_ARGS__) -#define vluxei8_v_u8m4(...) __riscv_vluxei8_v_u8m4(__VA_ARGS__) -#define vluxei8_v_u8m8(...) __riscv_vluxei8_v_u8m8(__VA_ARGS__) -#define vluxei16_v_u8mf8(...) __riscv_vluxei16_v_u8mf8(__VA_ARGS__) -#define vluxei16_v_u8mf4(...) __riscv_vluxei16_v_u8mf4(__VA_ARGS__) -#define vluxei16_v_u8mf2(...) __riscv_vluxei16_v_u8mf2(__VA_ARGS__) -#define vluxei16_v_u8m1(...) __riscv_vluxei16_v_u8m1(__VA_ARGS__) -#define vluxei16_v_u8m2(...) __riscv_vluxei16_v_u8m2(__VA_ARGS__) -#define vluxei16_v_u8m4(...) __riscv_vluxei16_v_u8m4(__VA_ARGS__) -#define vluxei32_v_u8mf8(...) __riscv_vluxei32_v_u8mf8(__VA_ARGS__) -#define vluxei32_v_u8mf4(...) __riscv_vluxei32_v_u8mf4(__VA_ARGS__) -#define vluxei32_v_u8mf2(...) __riscv_vluxei32_v_u8mf2(__VA_ARGS__) -#define vluxei32_v_u8m1(...) __riscv_vluxei32_v_u8m1(__VA_ARGS__) -#define vluxei32_v_u8m2(...) __riscv_vluxei32_v_u8m2(__VA_ARGS__) -#define vluxei64_v_u8mf8(...) __riscv_vluxei64_v_u8mf8(__VA_ARGS__) -#define vluxei64_v_u8mf4(...) __riscv_vluxei64_v_u8mf4(__VA_ARGS__) -#define vluxei64_v_u8mf2(...) __riscv_vluxei64_v_u8mf2(__VA_ARGS__) -#define vluxei64_v_u8m1(...) __riscv_vluxei64_v_u8m1(__VA_ARGS__) -#define vluxei8_v_u16mf4(...) __riscv_vluxei8_v_u16mf4(__VA_ARGS__) -#define vluxei8_v_u16mf2(...) __riscv_vluxei8_v_u16mf2(__VA_ARGS__) -#define vluxei8_v_u16m1(...) __riscv_vluxei8_v_u16m1(__VA_ARGS__) -#define vluxei8_v_u16m2(...) __riscv_vluxei8_v_u16m2(__VA_ARGS__) -#define vluxei8_v_u16m4(...) __riscv_vluxei8_v_u16m4(__VA_ARGS__) -#define vluxei8_v_u16m8(...) __riscv_vluxei8_v_u16m8(__VA_ARGS__) -#define vluxei16_v_u16mf4(...) __riscv_vluxei16_v_u16mf4(__VA_ARGS__) -#define vluxei16_v_u16mf2(...) __riscv_vluxei16_v_u16mf2(__VA_ARGS__) -#define vluxei16_v_u16m1(...) __riscv_vluxei16_v_u16m1(__VA_ARGS__) -#define vluxei16_v_u16m2(...) __riscv_vluxei16_v_u16m2(__VA_ARGS__) -#define vluxei16_v_u16m4(...) __riscv_vluxei16_v_u16m4(__VA_ARGS__) -#define vluxei16_v_u16m8(...) __riscv_vluxei16_v_u16m8(__VA_ARGS__) -#define vluxei32_v_u16mf4(...) __riscv_vluxei32_v_u16mf4(__VA_ARGS__) -#define vluxei32_v_u16mf2(...) __riscv_vluxei32_v_u16mf2(__VA_ARGS__) -#define vluxei32_v_u16m1(...) __riscv_vluxei32_v_u16m1(__VA_ARGS__) -#define vluxei32_v_u16m2(...) __riscv_vluxei32_v_u16m2(__VA_ARGS__) -#define vluxei32_v_u16m4(...) __riscv_vluxei32_v_u16m4(__VA_ARGS__) -#define vluxei64_v_u16mf4(...) __riscv_vluxei64_v_u16mf4(__VA_ARGS__) -#define vluxei64_v_u16mf2(...) __riscv_vluxei64_v_u16mf2(__VA_ARGS__) -#define vluxei64_v_u16m1(...) __riscv_vluxei64_v_u16m1(__VA_ARGS__) -#define vluxei64_v_u16m2(...) __riscv_vluxei64_v_u16m2(__VA_ARGS__) -#define vluxei8_v_u32mf2(...) __riscv_vluxei8_v_u32mf2(__VA_ARGS__) -#define vluxei8_v_u32m1(...) __riscv_vluxei8_v_u32m1(__VA_ARGS__) -#define vluxei8_v_u32m2(...) __riscv_vluxei8_v_u32m2(__VA_ARGS__) -#define vluxei8_v_u32m4(...) __riscv_vluxei8_v_u32m4(__VA_ARGS__) -#define vluxei8_v_u32m8(...) __riscv_vluxei8_v_u32m8(__VA_ARGS__) -#define vluxei16_v_u32mf2(...) __riscv_vluxei16_v_u32mf2(__VA_ARGS__) -#define vluxei16_v_u32m1(...) __riscv_vluxei16_v_u32m1(__VA_ARGS__) -#define vluxei16_v_u32m2(...) __riscv_vluxei16_v_u32m2(__VA_ARGS__) -#define vluxei16_v_u32m4(...) __riscv_vluxei16_v_u32m4(__VA_ARGS__) -#define vluxei16_v_u32m8(...) __riscv_vluxei16_v_u32m8(__VA_ARGS__) -#define vluxei32_v_u32mf2(...) __riscv_vluxei32_v_u32mf2(__VA_ARGS__) -#define vluxei32_v_u32m1(...) __riscv_vluxei32_v_u32m1(__VA_ARGS__) -#define vluxei32_v_u32m2(...) __riscv_vluxei32_v_u32m2(__VA_ARGS__) -#define vluxei32_v_u32m4(...) __riscv_vluxei32_v_u32m4(__VA_ARGS__) -#define vluxei32_v_u32m8(...) __riscv_vluxei32_v_u32m8(__VA_ARGS__) -#define vluxei64_v_u32mf2(...) __riscv_vluxei64_v_u32mf2(__VA_ARGS__) -#define vluxei64_v_u32m1(...) __riscv_vluxei64_v_u32m1(__VA_ARGS__) -#define vluxei64_v_u32m2(...) __riscv_vluxei64_v_u32m2(__VA_ARGS__) -#define vluxei64_v_u32m4(...) __riscv_vluxei64_v_u32m4(__VA_ARGS__) -#define vluxei8_v_u64m1(...) __riscv_vluxei8_v_u64m1(__VA_ARGS__) -#define vluxei8_v_u64m2(...) __riscv_vluxei8_v_u64m2(__VA_ARGS__) -#define vluxei8_v_u64m4(...) __riscv_vluxei8_v_u64m4(__VA_ARGS__) -#define vluxei8_v_u64m8(...) __riscv_vluxei8_v_u64m8(__VA_ARGS__) -#define vluxei16_v_u64m1(...) __riscv_vluxei16_v_u64m1(__VA_ARGS__) -#define vluxei16_v_u64m2(...) __riscv_vluxei16_v_u64m2(__VA_ARGS__) -#define vluxei16_v_u64m4(...) __riscv_vluxei16_v_u64m4(__VA_ARGS__) -#define vluxei16_v_u64m8(...) __riscv_vluxei16_v_u64m8(__VA_ARGS__) -#define vluxei32_v_u64m1(...) __riscv_vluxei32_v_u64m1(__VA_ARGS__) -#define vluxei32_v_u64m2(...) __riscv_vluxei32_v_u64m2(__VA_ARGS__) -#define vluxei32_v_u64m4(...) __riscv_vluxei32_v_u64m4(__VA_ARGS__) -#define vluxei32_v_u64m8(...) __riscv_vluxei32_v_u64m8(__VA_ARGS__) -#define vluxei64_v_u64m1(...) __riscv_vluxei64_v_u64m1(__VA_ARGS__) -#define vluxei64_v_u64m2(...) __riscv_vluxei64_v_u64m2(__VA_ARGS__) -#define vluxei64_v_u64m4(...) __riscv_vluxei64_v_u64m4(__VA_ARGS__) -#define vluxei64_v_u64m8(...) __riscv_vluxei64_v_u64m8(__VA_ARGS__) -// masked functions -#define vloxei8_v_f16mf4_m(...) __riscv_vloxei8_v_f16mf4_tumu(__VA_ARGS__) -#define vloxei8_v_f16mf2_m(...) __riscv_vloxei8_v_f16mf2_tumu(__VA_ARGS__) -#define vloxei8_v_f16m1_m(...) __riscv_vloxei8_v_f16m1_tumu(__VA_ARGS__) -#define vloxei8_v_f16m2_m(...) __riscv_vloxei8_v_f16m2_tumu(__VA_ARGS__) -#define vloxei8_v_f16m4_m(...) __riscv_vloxei8_v_f16m4_tumu(__VA_ARGS__) -#define vloxei8_v_f16m8_m(...) __riscv_vloxei8_v_f16m8_tumu(__VA_ARGS__) -#define vloxei16_v_f16mf4_m(...) __riscv_vloxei16_v_f16mf4_tumu(__VA_ARGS__) -#define vloxei16_v_f16mf2_m(...) __riscv_vloxei16_v_f16mf2_tumu(__VA_ARGS__) -#define vloxei16_v_f16m1_m(...) __riscv_vloxei16_v_f16m1_tumu(__VA_ARGS__) -#define vloxei16_v_f16m2_m(...) __riscv_vloxei16_v_f16m2_tumu(__VA_ARGS__) -#define vloxei16_v_f16m4_m(...) __riscv_vloxei16_v_f16m4_tumu(__VA_ARGS__) -#define vloxei16_v_f16m8_m(...) __riscv_vloxei16_v_f16m8_tumu(__VA_ARGS__) -#define vloxei32_v_f16mf4_m(...) __riscv_vloxei32_v_f16mf4_tumu(__VA_ARGS__) -#define vloxei32_v_f16mf2_m(...) __riscv_vloxei32_v_f16mf2_tumu(__VA_ARGS__) -#define vloxei32_v_f16m1_m(...) __riscv_vloxei32_v_f16m1_tumu(__VA_ARGS__) -#define vloxei32_v_f16m2_m(...) __riscv_vloxei32_v_f16m2_tumu(__VA_ARGS__) -#define vloxei32_v_f16m4_m(...) __riscv_vloxei32_v_f16m4_tumu(__VA_ARGS__) -#define vloxei64_v_f16mf4_m(...) __riscv_vloxei64_v_f16mf4_tumu(__VA_ARGS__) -#define vloxei64_v_f16mf2_m(...) __riscv_vloxei64_v_f16mf2_tumu(__VA_ARGS__) -#define vloxei64_v_f16m1_m(...) __riscv_vloxei64_v_f16m1_tumu(__VA_ARGS__) -#define vloxei64_v_f16m2_m(...) __riscv_vloxei64_v_f16m2_tumu(__VA_ARGS__) -#define vloxei8_v_f32mf2_m(...) __riscv_vloxei8_v_f32mf2_tumu(__VA_ARGS__) -#define vloxei8_v_f32m1_m(...) __riscv_vloxei8_v_f32m1_tumu(__VA_ARGS__) -#define vloxei8_v_f32m2_m(...) __riscv_vloxei8_v_f32m2_tumu(__VA_ARGS__) -#define vloxei8_v_f32m4_m(...) __riscv_vloxei8_v_f32m4_tumu(__VA_ARGS__) -#define vloxei8_v_f32m8_m(...) __riscv_vloxei8_v_f32m8_tumu(__VA_ARGS__) -#define vloxei16_v_f32mf2_m(...) __riscv_vloxei16_v_f32mf2_tumu(__VA_ARGS__) -#define vloxei16_v_f32m1_m(...) __riscv_vloxei16_v_f32m1_tumu(__VA_ARGS__) -#define vloxei16_v_f32m2_m(...) __riscv_vloxei16_v_f32m2_tumu(__VA_ARGS__) -#define vloxei16_v_f32m4_m(...) __riscv_vloxei16_v_f32m4_tumu(__VA_ARGS__) -#define vloxei16_v_f32m8_m(...) __riscv_vloxei16_v_f32m8_tumu(__VA_ARGS__) -#define vloxei32_v_f32mf2_m(...) __riscv_vloxei32_v_f32mf2_tumu(__VA_ARGS__) -#define vloxei32_v_f32m1_m(...) __riscv_vloxei32_v_f32m1_tumu(__VA_ARGS__) -#define vloxei32_v_f32m2_m(...) __riscv_vloxei32_v_f32m2_tumu(__VA_ARGS__) -#define vloxei32_v_f32m4_m(...) __riscv_vloxei32_v_f32m4_tumu(__VA_ARGS__) -#define vloxei32_v_f32m8_m(...) __riscv_vloxei32_v_f32m8_tumu(__VA_ARGS__) -#define vloxei64_v_f32mf2_m(...) __riscv_vloxei64_v_f32mf2_tumu(__VA_ARGS__) -#define vloxei64_v_f32m1_m(...) __riscv_vloxei64_v_f32m1_tumu(__VA_ARGS__) -#define vloxei64_v_f32m2_m(...) __riscv_vloxei64_v_f32m2_tumu(__VA_ARGS__) -#define vloxei64_v_f32m4_m(...) __riscv_vloxei64_v_f32m4_tumu(__VA_ARGS__) -#define vloxei8_v_f64m1_m(...) __riscv_vloxei8_v_f64m1_tumu(__VA_ARGS__) -#define vloxei8_v_f64m2_m(...) __riscv_vloxei8_v_f64m2_tumu(__VA_ARGS__) -#define vloxei8_v_f64m4_m(...) __riscv_vloxei8_v_f64m4_tumu(__VA_ARGS__) -#define vloxei8_v_f64m8_m(...) __riscv_vloxei8_v_f64m8_tumu(__VA_ARGS__) -#define vloxei16_v_f64m1_m(...) __riscv_vloxei16_v_f64m1_tumu(__VA_ARGS__) -#define vloxei16_v_f64m2_m(...) __riscv_vloxei16_v_f64m2_tumu(__VA_ARGS__) -#define vloxei16_v_f64m4_m(...) __riscv_vloxei16_v_f64m4_tumu(__VA_ARGS__) -#define vloxei16_v_f64m8_m(...) __riscv_vloxei16_v_f64m8_tumu(__VA_ARGS__) -#define vloxei32_v_f64m1_m(...) __riscv_vloxei32_v_f64m1_tumu(__VA_ARGS__) -#define vloxei32_v_f64m2_m(...) __riscv_vloxei32_v_f64m2_tumu(__VA_ARGS__) -#define vloxei32_v_f64m4_m(...) __riscv_vloxei32_v_f64m4_tumu(__VA_ARGS__) -#define vloxei32_v_f64m8_m(...) __riscv_vloxei32_v_f64m8_tumu(__VA_ARGS__) -#define vloxei64_v_f64m1_m(...) __riscv_vloxei64_v_f64m1_tumu(__VA_ARGS__) -#define vloxei64_v_f64m2_m(...) __riscv_vloxei64_v_f64m2_tumu(__VA_ARGS__) -#define vloxei64_v_f64m4_m(...) __riscv_vloxei64_v_f64m4_tumu(__VA_ARGS__) -#define vloxei64_v_f64m8_m(...) __riscv_vloxei64_v_f64m8_tumu(__VA_ARGS__) -#define vluxei8_v_f16mf4_m(...) __riscv_vluxei8_v_f16mf4_tumu(__VA_ARGS__) -#define vluxei8_v_f16mf2_m(...) __riscv_vluxei8_v_f16mf2_tumu(__VA_ARGS__) -#define vluxei8_v_f16m1_m(...) __riscv_vluxei8_v_f16m1_tumu(__VA_ARGS__) -#define vluxei8_v_f16m2_m(...) __riscv_vluxei8_v_f16m2_tumu(__VA_ARGS__) -#define vluxei8_v_f16m4_m(...) __riscv_vluxei8_v_f16m4_tumu(__VA_ARGS__) -#define vluxei8_v_f16m8_m(...) __riscv_vluxei8_v_f16m8_tumu(__VA_ARGS__) -#define vluxei16_v_f16mf4_m(...) __riscv_vluxei16_v_f16mf4_tumu(__VA_ARGS__) -#define vluxei16_v_f16mf2_m(...) __riscv_vluxei16_v_f16mf2_tumu(__VA_ARGS__) -#define vluxei16_v_f16m1_m(...) __riscv_vluxei16_v_f16m1_tumu(__VA_ARGS__) -#define vluxei16_v_f16m2_m(...) __riscv_vluxei16_v_f16m2_tumu(__VA_ARGS__) -#define vluxei16_v_f16m4_m(...) __riscv_vluxei16_v_f16m4_tumu(__VA_ARGS__) -#define vluxei16_v_f16m8_m(...) __riscv_vluxei16_v_f16m8_tumu(__VA_ARGS__) -#define vluxei32_v_f16mf4_m(...) __riscv_vluxei32_v_f16mf4_tumu(__VA_ARGS__) -#define vluxei32_v_f16mf2_m(...) __riscv_vluxei32_v_f16mf2_tumu(__VA_ARGS__) -#define vluxei32_v_f16m1_m(...) __riscv_vluxei32_v_f16m1_tumu(__VA_ARGS__) -#define vluxei32_v_f16m2_m(...) __riscv_vluxei32_v_f16m2_tumu(__VA_ARGS__) -#define vluxei32_v_f16m4_m(...) __riscv_vluxei32_v_f16m4_tumu(__VA_ARGS__) -#define vluxei64_v_f16mf4_m(...) __riscv_vluxei64_v_f16mf4_tumu(__VA_ARGS__) -#define vluxei64_v_f16mf2_m(...) __riscv_vluxei64_v_f16mf2_tumu(__VA_ARGS__) -#define vluxei64_v_f16m1_m(...) __riscv_vluxei64_v_f16m1_tumu(__VA_ARGS__) -#define vluxei64_v_f16m2_m(...) __riscv_vluxei64_v_f16m2_tumu(__VA_ARGS__) -#define vluxei8_v_f32mf2_m(...) __riscv_vluxei8_v_f32mf2_tumu(__VA_ARGS__) -#define vluxei8_v_f32m1_m(...) __riscv_vluxei8_v_f32m1_tumu(__VA_ARGS__) -#define vluxei8_v_f32m2_m(...) __riscv_vluxei8_v_f32m2_tumu(__VA_ARGS__) -#define vluxei8_v_f32m4_m(...) __riscv_vluxei8_v_f32m4_tumu(__VA_ARGS__) -#define vluxei8_v_f32m8_m(...) __riscv_vluxei8_v_f32m8_tumu(__VA_ARGS__) -#define vluxei16_v_f32mf2_m(...) __riscv_vluxei16_v_f32mf2_tumu(__VA_ARGS__) -#define vluxei16_v_f32m1_m(...) __riscv_vluxei16_v_f32m1_tumu(__VA_ARGS__) -#define vluxei16_v_f32m2_m(...) __riscv_vluxei16_v_f32m2_tumu(__VA_ARGS__) -#define vluxei16_v_f32m4_m(...) __riscv_vluxei16_v_f32m4_tumu(__VA_ARGS__) -#define vluxei16_v_f32m8_m(...) __riscv_vluxei16_v_f32m8_tumu(__VA_ARGS__) -#define vluxei32_v_f32mf2_m(...) __riscv_vluxei32_v_f32mf2_tumu(__VA_ARGS__) -#define vluxei32_v_f32m1_m(...) __riscv_vluxei32_v_f32m1_tumu(__VA_ARGS__) -#define vluxei32_v_f32m2_m(...) __riscv_vluxei32_v_f32m2_tumu(__VA_ARGS__) -#define vluxei32_v_f32m4_m(...) __riscv_vluxei32_v_f32m4_tumu(__VA_ARGS__) -#define vluxei32_v_f32m8_m(...) __riscv_vluxei32_v_f32m8_tumu(__VA_ARGS__) -#define vluxei64_v_f32mf2_m(...) __riscv_vluxei64_v_f32mf2_tumu(__VA_ARGS__) -#define vluxei64_v_f32m1_m(...) __riscv_vluxei64_v_f32m1_tumu(__VA_ARGS__) -#define vluxei64_v_f32m2_m(...) __riscv_vluxei64_v_f32m2_tumu(__VA_ARGS__) -#define vluxei64_v_f32m4_m(...) __riscv_vluxei64_v_f32m4_tumu(__VA_ARGS__) -#define vluxei8_v_f64m1_m(...) __riscv_vluxei8_v_f64m1_tumu(__VA_ARGS__) -#define vluxei8_v_f64m2_m(...) __riscv_vluxei8_v_f64m2_tumu(__VA_ARGS__) -#define vluxei8_v_f64m4_m(...) __riscv_vluxei8_v_f64m4_tumu(__VA_ARGS__) -#define vluxei8_v_f64m8_m(...) __riscv_vluxei8_v_f64m8_tumu(__VA_ARGS__) -#define vluxei16_v_f64m1_m(...) __riscv_vluxei16_v_f64m1_tumu(__VA_ARGS__) -#define vluxei16_v_f64m2_m(...) __riscv_vluxei16_v_f64m2_tumu(__VA_ARGS__) -#define vluxei16_v_f64m4_m(...) __riscv_vluxei16_v_f64m4_tumu(__VA_ARGS__) -#define vluxei16_v_f64m8_m(...) __riscv_vluxei16_v_f64m8_tumu(__VA_ARGS__) -#define vluxei32_v_f64m1_m(...) __riscv_vluxei32_v_f64m1_tumu(__VA_ARGS__) -#define vluxei32_v_f64m2_m(...) __riscv_vluxei32_v_f64m2_tumu(__VA_ARGS__) -#define vluxei32_v_f64m4_m(...) __riscv_vluxei32_v_f64m4_tumu(__VA_ARGS__) -#define vluxei32_v_f64m8_m(...) __riscv_vluxei32_v_f64m8_tumu(__VA_ARGS__) -#define vluxei64_v_f64m1_m(...) __riscv_vluxei64_v_f64m1_tumu(__VA_ARGS__) -#define vluxei64_v_f64m2_m(...) __riscv_vluxei64_v_f64m2_tumu(__VA_ARGS__) -#define vluxei64_v_f64m4_m(...) __riscv_vluxei64_v_f64m4_tumu(__VA_ARGS__) -#define vluxei64_v_f64m8_m(...) __riscv_vluxei64_v_f64m8_tumu(__VA_ARGS__) -#define vloxei8_v_i8mf8_m(...) __riscv_vloxei8_v_i8mf8_tumu(__VA_ARGS__) -#define vloxei8_v_i8mf4_m(...) __riscv_vloxei8_v_i8mf4_tumu(__VA_ARGS__) -#define vloxei8_v_i8mf2_m(...) __riscv_vloxei8_v_i8mf2_tumu(__VA_ARGS__) -#define vloxei8_v_i8m1_m(...) __riscv_vloxei8_v_i8m1_tumu(__VA_ARGS__) -#define vloxei8_v_i8m2_m(...) __riscv_vloxei8_v_i8m2_tumu(__VA_ARGS__) -#define vloxei8_v_i8m4_m(...) __riscv_vloxei8_v_i8m4_tumu(__VA_ARGS__) -#define vloxei8_v_i8m8_m(...) __riscv_vloxei8_v_i8m8_tumu(__VA_ARGS__) -#define vloxei16_v_i8mf8_m(...) __riscv_vloxei16_v_i8mf8_tumu(__VA_ARGS__) -#define vloxei16_v_i8mf4_m(...) __riscv_vloxei16_v_i8mf4_tumu(__VA_ARGS__) -#define vloxei16_v_i8mf2_m(...) __riscv_vloxei16_v_i8mf2_tumu(__VA_ARGS__) -#define vloxei16_v_i8m1_m(...) __riscv_vloxei16_v_i8m1_tumu(__VA_ARGS__) -#define vloxei16_v_i8m2_m(...) __riscv_vloxei16_v_i8m2_tumu(__VA_ARGS__) -#define vloxei16_v_i8m4_m(...) __riscv_vloxei16_v_i8m4_tumu(__VA_ARGS__) -#define vloxei32_v_i8mf8_m(...) __riscv_vloxei32_v_i8mf8_tumu(__VA_ARGS__) -#define vloxei32_v_i8mf4_m(...) __riscv_vloxei32_v_i8mf4_tumu(__VA_ARGS__) -#define vloxei32_v_i8mf2_m(...) __riscv_vloxei32_v_i8mf2_tumu(__VA_ARGS__) -#define vloxei32_v_i8m1_m(...) __riscv_vloxei32_v_i8m1_tumu(__VA_ARGS__) -#define vloxei32_v_i8m2_m(...) __riscv_vloxei32_v_i8m2_tumu(__VA_ARGS__) -#define vloxei64_v_i8mf8_m(...) __riscv_vloxei64_v_i8mf8_tumu(__VA_ARGS__) -#define vloxei64_v_i8mf4_m(...) __riscv_vloxei64_v_i8mf4_tumu(__VA_ARGS__) -#define vloxei64_v_i8mf2_m(...) __riscv_vloxei64_v_i8mf2_tumu(__VA_ARGS__) -#define vloxei64_v_i8m1_m(...) __riscv_vloxei64_v_i8m1_tumu(__VA_ARGS__) -#define vloxei8_v_i16mf4_m(...) __riscv_vloxei8_v_i16mf4_tumu(__VA_ARGS__) -#define vloxei8_v_i16mf2_m(...) __riscv_vloxei8_v_i16mf2_tumu(__VA_ARGS__) -#define vloxei8_v_i16m1_m(...) __riscv_vloxei8_v_i16m1_tumu(__VA_ARGS__) -#define vloxei8_v_i16m2_m(...) __riscv_vloxei8_v_i16m2_tumu(__VA_ARGS__) -#define vloxei8_v_i16m4_m(...) __riscv_vloxei8_v_i16m4_tumu(__VA_ARGS__) -#define vloxei8_v_i16m8_m(...) __riscv_vloxei8_v_i16m8_tumu(__VA_ARGS__) -#define vloxei16_v_i16mf4_m(...) __riscv_vloxei16_v_i16mf4_tumu(__VA_ARGS__) -#define vloxei16_v_i16mf2_m(...) __riscv_vloxei16_v_i16mf2_tumu(__VA_ARGS__) -#define vloxei16_v_i16m1_m(...) __riscv_vloxei16_v_i16m1_tumu(__VA_ARGS__) -#define vloxei16_v_i16m2_m(...) __riscv_vloxei16_v_i16m2_tumu(__VA_ARGS__) -#define vloxei16_v_i16m4_m(...) __riscv_vloxei16_v_i16m4_tumu(__VA_ARGS__) -#define vloxei16_v_i16m8_m(...) __riscv_vloxei16_v_i16m8_tumu(__VA_ARGS__) -#define vloxei32_v_i16mf4_m(...) __riscv_vloxei32_v_i16mf4_tumu(__VA_ARGS__) -#define vloxei32_v_i16mf2_m(...) __riscv_vloxei32_v_i16mf2_tumu(__VA_ARGS__) -#define vloxei32_v_i16m1_m(...) __riscv_vloxei32_v_i16m1_tumu(__VA_ARGS__) -#define vloxei32_v_i16m2_m(...) __riscv_vloxei32_v_i16m2_tumu(__VA_ARGS__) -#define vloxei32_v_i16m4_m(...) __riscv_vloxei32_v_i16m4_tumu(__VA_ARGS__) -#define vloxei64_v_i16mf4_m(...) __riscv_vloxei64_v_i16mf4_tumu(__VA_ARGS__) -#define vloxei64_v_i16mf2_m(...) __riscv_vloxei64_v_i16mf2_tumu(__VA_ARGS__) -#define vloxei64_v_i16m1_m(...) __riscv_vloxei64_v_i16m1_tumu(__VA_ARGS__) -#define vloxei64_v_i16m2_m(...) __riscv_vloxei64_v_i16m2_tumu(__VA_ARGS__) -#define vloxei8_v_i32mf2_m(...) __riscv_vloxei8_v_i32mf2_tumu(__VA_ARGS__) -#define vloxei8_v_i32m1_m(...) __riscv_vloxei8_v_i32m1_tumu(__VA_ARGS__) -#define vloxei8_v_i32m2_m(...) __riscv_vloxei8_v_i32m2_tumu(__VA_ARGS__) -#define vloxei8_v_i32m4_m(...) __riscv_vloxei8_v_i32m4_tumu(__VA_ARGS__) -#define vloxei8_v_i32m8_m(...) __riscv_vloxei8_v_i32m8_tumu(__VA_ARGS__) -#define vloxei16_v_i32mf2_m(...) __riscv_vloxei16_v_i32mf2_tumu(__VA_ARGS__) -#define vloxei16_v_i32m1_m(...) __riscv_vloxei16_v_i32m1_tumu(__VA_ARGS__) -#define vloxei16_v_i32m2_m(...) __riscv_vloxei16_v_i32m2_tumu(__VA_ARGS__) -#define vloxei16_v_i32m4_m(...) __riscv_vloxei16_v_i32m4_tumu(__VA_ARGS__) -#define vloxei16_v_i32m8_m(...) __riscv_vloxei16_v_i32m8_tumu(__VA_ARGS__) -#define vloxei32_v_i32mf2_m(...) __riscv_vloxei32_v_i32mf2_tumu(__VA_ARGS__) -#define vloxei32_v_i32m1_m(...) __riscv_vloxei32_v_i32m1_tumu(__VA_ARGS__) -#define vloxei32_v_i32m2_m(...) __riscv_vloxei32_v_i32m2_tumu(__VA_ARGS__) -#define vloxei32_v_i32m4_m(...) __riscv_vloxei32_v_i32m4_tumu(__VA_ARGS__) -#define vloxei32_v_i32m8_m(...) __riscv_vloxei32_v_i32m8_tumu(__VA_ARGS__) -#define vloxei64_v_i32mf2_m(...) __riscv_vloxei64_v_i32mf2_tumu(__VA_ARGS__) -#define vloxei64_v_i32m1_m(...) __riscv_vloxei64_v_i32m1_tumu(__VA_ARGS__) -#define vloxei64_v_i32m2_m(...) __riscv_vloxei64_v_i32m2_tumu(__VA_ARGS__) -#define vloxei64_v_i32m4_m(...) __riscv_vloxei64_v_i32m4_tumu(__VA_ARGS__) -#define vloxei8_v_i64m1_m(...) __riscv_vloxei8_v_i64m1_tumu(__VA_ARGS__) -#define vloxei8_v_i64m2_m(...) __riscv_vloxei8_v_i64m2_tumu(__VA_ARGS__) -#define vloxei8_v_i64m4_m(...) __riscv_vloxei8_v_i64m4_tumu(__VA_ARGS__) -#define vloxei8_v_i64m8_m(...) __riscv_vloxei8_v_i64m8_tumu(__VA_ARGS__) -#define vloxei16_v_i64m1_m(...) __riscv_vloxei16_v_i64m1_tumu(__VA_ARGS__) -#define vloxei16_v_i64m2_m(...) __riscv_vloxei16_v_i64m2_tumu(__VA_ARGS__) -#define vloxei16_v_i64m4_m(...) __riscv_vloxei16_v_i64m4_tumu(__VA_ARGS__) -#define vloxei16_v_i64m8_m(...) __riscv_vloxei16_v_i64m8_tumu(__VA_ARGS__) -#define vloxei32_v_i64m1_m(...) __riscv_vloxei32_v_i64m1_tumu(__VA_ARGS__) -#define vloxei32_v_i64m2_m(...) __riscv_vloxei32_v_i64m2_tumu(__VA_ARGS__) -#define vloxei32_v_i64m4_m(...) __riscv_vloxei32_v_i64m4_tumu(__VA_ARGS__) -#define vloxei32_v_i64m8_m(...) __riscv_vloxei32_v_i64m8_tumu(__VA_ARGS__) -#define vloxei64_v_i64m1_m(...) __riscv_vloxei64_v_i64m1_tumu(__VA_ARGS__) -#define vloxei64_v_i64m2_m(...) __riscv_vloxei64_v_i64m2_tumu(__VA_ARGS__) -#define vloxei64_v_i64m4_m(...) __riscv_vloxei64_v_i64m4_tumu(__VA_ARGS__) -#define vloxei64_v_i64m8_m(...) __riscv_vloxei64_v_i64m8_tumu(__VA_ARGS__) -#define vluxei8_v_i8mf8_m(...) __riscv_vluxei8_v_i8mf8_tumu(__VA_ARGS__) -#define vluxei8_v_i8mf4_m(...) __riscv_vluxei8_v_i8mf4_tumu(__VA_ARGS__) -#define vluxei8_v_i8mf2_m(...) __riscv_vluxei8_v_i8mf2_tumu(__VA_ARGS__) -#define vluxei8_v_i8m1_m(...) __riscv_vluxei8_v_i8m1_tumu(__VA_ARGS__) -#define vluxei8_v_i8m2_m(...) __riscv_vluxei8_v_i8m2_tumu(__VA_ARGS__) -#define vluxei8_v_i8m4_m(...) __riscv_vluxei8_v_i8m4_tumu(__VA_ARGS__) -#define vluxei8_v_i8m8_m(...) __riscv_vluxei8_v_i8m8_tumu(__VA_ARGS__) -#define vluxei16_v_i8mf8_m(...) __riscv_vluxei16_v_i8mf8_tumu(__VA_ARGS__) -#define vluxei16_v_i8mf4_m(...) __riscv_vluxei16_v_i8mf4_tumu(__VA_ARGS__) -#define vluxei16_v_i8mf2_m(...) __riscv_vluxei16_v_i8mf2_tumu(__VA_ARGS__) -#define vluxei16_v_i8m1_m(...) __riscv_vluxei16_v_i8m1_tumu(__VA_ARGS__) -#define vluxei16_v_i8m2_m(...) __riscv_vluxei16_v_i8m2_tumu(__VA_ARGS__) -#define vluxei16_v_i8m4_m(...) __riscv_vluxei16_v_i8m4_tumu(__VA_ARGS__) -#define vluxei32_v_i8mf8_m(...) __riscv_vluxei32_v_i8mf8_tumu(__VA_ARGS__) -#define vluxei32_v_i8mf4_m(...) __riscv_vluxei32_v_i8mf4_tumu(__VA_ARGS__) -#define vluxei32_v_i8mf2_m(...) __riscv_vluxei32_v_i8mf2_tumu(__VA_ARGS__) -#define vluxei32_v_i8m1_m(...) __riscv_vluxei32_v_i8m1_tumu(__VA_ARGS__) -#define vluxei32_v_i8m2_m(...) __riscv_vluxei32_v_i8m2_tumu(__VA_ARGS__) -#define vluxei64_v_i8mf8_m(...) __riscv_vluxei64_v_i8mf8_tumu(__VA_ARGS__) -#define vluxei64_v_i8mf4_m(...) __riscv_vluxei64_v_i8mf4_tumu(__VA_ARGS__) -#define vluxei64_v_i8mf2_m(...) __riscv_vluxei64_v_i8mf2_tumu(__VA_ARGS__) -#define vluxei64_v_i8m1_m(...) __riscv_vluxei64_v_i8m1_tumu(__VA_ARGS__) -#define vluxei8_v_i16mf4_m(...) __riscv_vluxei8_v_i16mf4_tumu(__VA_ARGS__) -#define vluxei8_v_i16mf2_m(...) __riscv_vluxei8_v_i16mf2_tumu(__VA_ARGS__) -#define vluxei8_v_i16m1_m(...) __riscv_vluxei8_v_i16m1_tumu(__VA_ARGS__) -#define vluxei8_v_i16m2_m(...) __riscv_vluxei8_v_i16m2_tumu(__VA_ARGS__) -#define vluxei8_v_i16m4_m(...) __riscv_vluxei8_v_i16m4_tumu(__VA_ARGS__) -#define vluxei8_v_i16m8_m(...) __riscv_vluxei8_v_i16m8_tumu(__VA_ARGS__) -#define vluxei16_v_i16mf4_m(...) __riscv_vluxei16_v_i16mf4_tumu(__VA_ARGS__) -#define vluxei16_v_i16mf2_m(...) __riscv_vluxei16_v_i16mf2_tumu(__VA_ARGS__) -#define vluxei16_v_i16m1_m(...) __riscv_vluxei16_v_i16m1_tumu(__VA_ARGS__) -#define vluxei16_v_i16m2_m(...) __riscv_vluxei16_v_i16m2_tumu(__VA_ARGS__) -#define vluxei16_v_i16m4_m(...) __riscv_vluxei16_v_i16m4_tumu(__VA_ARGS__) -#define vluxei16_v_i16m8_m(...) __riscv_vluxei16_v_i16m8_tumu(__VA_ARGS__) -#define vluxei32_v_i16mf4_m(...) __riscv_vluxei32_v_i16mf4_tumu(__VA_ARGS__) -#define vluxei32_v_i16mf2_m(...) __riscv_vluxei32_v_i16mf2_tumu(__VA_ARGS__) -#define vluxei32_v_i16m1_m(...) __riscv_vluxei32_v_i16m1_tumu(__VA_ARGS__) -#define vluxei32_v_i16m2_m(...) __riscv_vluxei32_v_i16m2_tumu(__VA_ARGS__) -#define vluxei32_v_i16m4_m(...) __riscv_vluxei32_v_i16m4_tumu(__VA_ARGS__) -#define vluxei64_v_i16mf4_m(...) __riscv_vluxei64_v_i16mf4_tumu(__VA_ARGS__) -#define vluxei64_v_i16mf2_m(...) __riscv_vluxei64_v_i16mf2_tumu(__VA_ARGS__) -#define vluxei64_v_i16m1_m(...) __riscv_vluxei64_v_i16m1_tumu(__VA_ARGS__) -#define vluxei64_v_i16m2_m(...) __riscv_vluxei64_v_i16m2_tumu(__VA_ARGS__) -#define vluxei8_v_i32mf2_m(...) __riscv_vluxei8_v_i32mf2_tumu(__VA_ARGS__) -#define vluxei8_v_i32m1_m(...) __riscv_vluxei8_v_i32m1_tumu(__VA_ARGS__) -#define vluxei8_v_i32m2_m(...) __riscv_vluxei8_v_i32m2_tumu(__VA_ARGS__) -#define vluxei8_v_i32m4_m(...) __riscv_vluxei8_v_i32m4_tumu(__VA_ARGS__) -#define vluxei8_v_i32m8_m(...) __riscv_vluxei8_v_i32m8_tumu(__VA_ARGS__) -#define vluxei16_v_i32mf2_m(...) __riscv_vluxei16_v_i32mf2_tumu(__VA_ARGS__) -#define vluxei16_v_i32m1_m(...) __riscv_vluxei16_v_i32m1_tumu(__VA_ARGS__) -#define vluxei16_v_i32m2_m(...) __riscv_vluxei16_v_i32m2_tumu(__VA_ARGS__) -#define vluxei16_v_i32m4_m(...) __riscv_vluxei16_v_i32m4_tumu(__VA_ARGS__) -#define vluxei16_v_i32m8_m(...) __riscv_vluxei16_v_i32m8_tumu(__VA_ARGS__) -#define vluxei32_v_i32mf2_m(...) __riscv_vluxei32_v_i32mf2_tumu(__VA_ARGS__) -#define vluxei32_v_i32m1_m(...) __riscv_vluxei32_v_i32m1_tumu(__VA_ARGS__) -#define vluxei32_v_i32m2_m(...) __riscv_vluxei32_v_i32m2_tumu(__VA_ARGS__) -#define vluxei32_v_i32m4_m(...) __riscv_vluxei32_v_i32m4_tumu(__VA_ARGS__) -#define vluxei32_v_i32m8_m(...) __riscv_vluxei32_v_i32m8_tumu(__VA_ARGS__) -#define vluxei64_v_i32mf2_m(...) __riscv_vluxei64_v_i32mf2_tumu(__VA_ARGS__) -#define vluxei64_v_i32m1_m(...) __riscv_vluxei64_v_i32m1_tumu(__VA_ARGS__) -#define vluxei64_v_i32m2_m(...) __riscv_vluxei64_v_i32m2_tumu(__VA_ARGS__) -#define vluxei64_v_i32m4_m(...) __riscv_vluxei64_v_i32m4_tumu(__VA_ARGS__) -#define vluxei8_v_i64m1_m(...) __riscv_vluxei8_v_i64m1_tumu(__VA_ARGS__) -#define vluxei8_v_i64m2_m(...) __riscv_vluxei8_v_i64m2_tumu(__VA_ARGS__) -#define vluxei8_v_i64m4_m(...) __riscv_vluxei8_v_i64m4_tumu(__VA_ARGS__) -#define vluxei8_v_i64m8_m(...) __riscv_vluxei8_v_i64m8_tumu(__VA_ARGS__) -#define vluxei16_v_i64m1_m(...) __riscv_vluxei16_v_i64m1_tumu(__VA_ARGS__) -#define vluxei16_v_i64m2_m(...) __riscv_vluxei16_v_i64m2_tumu(__VA_ARGS__) -#define vluxei16_v_i64m4_m(...) __riscv_vluxei16_v_i64m4_tumu(__VA_ARGS__) -#define vluxei16_v_i64m8_m(...) __riscv_vluxei16_v_i64m8_tumu(__VA_ARGS__) -#define vluxei32_v_i64m1_m(...) __riscv_vluxei32_v_i64m1_tumu(__VA_ARGS__) -#define vluxei32_v_i64m2_m(...) __riscv_vluxei32_v_i64m2_tumu(__VA_ARGS__) -#define vluxei32_v_i64m4_m(...) __riscv_vluxei32_v_i64m4_tumu(__VA_ARGS__) -#define vluxei32_v_i64m8_m(...) __riscv_vluxei32_v_i64m8_tumu(__VA_ARGS__) -#define vluxei64_v_i64m1_m(...) __riscv_vluxei64_v_i64m1_tumu(__VA_ARGS__) -#define vluxei64_v_i64m2_m(...) __riscv_vluxei64_v_i64m2_tumu(__VA_ARGS__) -#define vluxei64_v_i64m4_m(...) __riscv_vluxei64_v_i64m4_tumu(__VA_ARGS__) -#define vluxei64_v_i64m8_m(...) __riscv_vluxei64_v_i64m8_tumu(__VA_ARGS__) -#define vloxei8_v_u8mf8_m(...) __riscv_vloxei8_v_u8mf8_tumu(__VA_ARGS__) -#define vloxei8_v_u8mf4_m(...) __riscv_vloxei8_v_u8mf4_tumu(__VA_ARGS__) -#define vloxei8_v_u8mf2_m(...) __riscv_vloxei8_v_u8mf2_tumu(__VA_ARGS__) -#define vloxei8_v_u8m1_m(...) __riscv_vloxei8_v_u8m1_tumu(__VA_ARGS__) -#define vloxei8_v_u8m2_m(...) __riscv_vloxei8_v_u8m2_tumu(__VA_ARGS__) -#define vloxei8_v_u8m4_m(...) __riscv_vloxei8_v_u8m4_tumu(__VA_ARGS__) -#define vloxei8_v_u8m8_m(...) __riscv_vloxei8_v_u8m8_tumu(__VA_ARGS__) -#define vloxei16_v_u8mf8_m(...) __riscv_vloxei16_v_u8mf8_tumu(__VA_ARGS__) -#define vloxei16_v_u8mf4_m(...) __riscv_vloxei16_v_u8mf4_tumu(__VA_ARGS__) -#define vloxei16_v_u8mf2_m(...) __riscv_vloxei16_v_u8mf2_tumu(__VA_ARGS__) -#define vloxei16_v_u8m1_m(...) __riscv_vloxei16_v_u8m1_tumu(__VA_ARGS__) -#define vloxei16_v_u8m2_m(...) __riscv_vloxei16_v_u8m2_tumu(__VA_ARGS__) -#define vloxei16_v_u8m4_m(...) __riscv_vloxei16_v_u8m4_tumu(__VA_ARGS__) -#define vloxei32_v_u8mf8_m(...) __riscv_vloxei32_v_u8mf8_tumu(__VA_ARGS__) -#define vloxei32_v_u8mf4_m(...) __riscv_vloxei32_v_u8mf4_tumu(__VA_ARGS__) -#define vloxei32_v_u8mf2_m(...) __riscv_vloxei32_v_u8mf2_tumu(__VA_ARGS__) -#define vloxei32_v_u8m1_m(...) __riscv_vloxei32_v_u8m1_tumu(__VA_ARGS__) -#define vloxei32_v_u8m2_m(...) __riscv_vloxei32_v_u8m2_tumu(__VA_ARGS__) -#define vloxei64_v_u8mf8_m(...) __riscv_vloxei64_v_u8mf8_tumu(__VA_ARGS__) -#define vloxei64_v_u8mf4_m(...) __riscv_vloxei64_v_u8mf4_tumu(__VA_ARGS__) -#define vloxei64_v_u8mf2_m(...) __riscv_vloxei64_v_u8mf2_tumu(__VA_ARGS__) -#define vloxei64_v_u8m1_m(...) __riscv_vloxei64_v_u8m1_tumu(__VA_ARGS__) -#define vloxei8_v_u16mf4_m(...) __riscv_vloxei8_v_u16mf4_tumu(__VA_ARGS__) -#define vloxei8_v_u16mf2_m(...) __riscv_vloxei8_v_u16mf2_tumu(__VA_ARGS__) -#define vloxei8_v_u16m1_m(...) __riscv_vloxei8_v_u16m1_tumu(__VA_ARGS__) -#define vloxei8_v_u16m2_m(...) __riscv_vloxei8_v_u16m2_tumu(__VA_ARGS__) -#define vloxei8_v_u16m4_m(...) __riscv_vloxei8_v_u16m4_tumu(__VA_ARGS__) -#define vloxei8_v_u16m8_m(...) __riscv_vloxei8_v_u16m8_tumu(__VA_ARGS__) -#define vloxei16_v_u16mf4_m(...) __riscv_vloxei16_v_u16mf4_tumu(__VA_ARGS__) -#define vloxei16_v_u16mf2_m(...) __riscv_vloxei16_v_u16mf2_tumu(__VA_ARGS__) -#define vloxei16_v_u16m1_m(...) __riscv_vloxei16_v_u16m1_tumu(__VA_ARGS__) -#define vloxei16_v_u16m2_m(...) __riscv_vloxei16_v_u16m2_tumu(__VA_ARGS__) -#define vloxei16_v_u16m4_m(...) __riscv_vloxei16_v_u16m4_tumu(__VA_ARGS__) -#define vloxei16_v_u16m8_m(...) __riscv_vloxei16_v_u16m8_tumu(__VA_ARGS__) -#define vloxei32_v_u16mf4_m(...) __riscv_vloxei32_v_u16mf4_tumu(__VA_ARGS__) -#define vloxei32_v_u16mf2_m(...) __riscv_vloxei32_v_u16mf2_tumu(__VA_ARGS__) -#define vloxei32_v_u16m1_m(...) __riscv_vloxei32_v_u16m1_tumu(__VA_ARGS__) -#define vloxei32_v_u16m2_m(...) __riscv_vloxei32_v_u16m2_tumu(__VA_ARGS__) -#define vloxei32_v_u16m4_m(...) __riscv_vloxei32_v_u16m4_tumu(__VA_ARGS__) -#define vloxei64_v_u16mf4_m(...) __riscv_vloxei64_v_u16mf4_tumu(__VA_ARGS__) -#define vloxei64_v_u16mf2_m(...) __riscv_vloxei64_v_u16mf2_tumu(__VA_ARGS__) -#define vloxei64_v_u16m1_m(...) __riscv_vloxei64_v_u16m1_tumu(__VA_ARGS__) -#define vloxei64_v_u16m2_m(...) __riscv_vloxei64_v_u16m2_tumu(__VA_ARGS__) -#define vloxei8_v_u32mf2_m(...) __riscv_vloxei8_v_u32mf2_tumu(__VA_ARGS__) -#define vloxei8_v_u32m1_m(...) __riscv_vloxei8_v_u32m1_tumu(__VA_ARGS__) -#define vloxei8_v_u32m2_m(...) __riscv_vloxei8_v_u32m2_tumu(__VA_ARGS__) -#define vloxei8_v_u32m4_m(...) __riscv_vloxei8_v_u32m4_tumu(__VA_ARGS__) -#define vloxei8_v_u32m8_m(...) __riscv_vloxei8_v_u32m8_tumu(__VA_ARGS__) -#define vloxei16_v_u32mf2_m(...) __riscv_vloxei16_v_u32mf2_tumu(__VA_ARGS__) -#define vloxei16_v_u32m1_m(...) __riscv_vloxei16_v_u32m1_tumu(__VA_ARGS__) -#define vloxei16_v_u32m2_m(...) __riscv_vloxei16_v_u32m2_tumu(__VA_ARGS__) -#define vloxei16_v_u32m4_m(...) __riscv_vloxei16_v_u32m4_tumu(__VA_ARGS__) -#define vloxei16_v_u32m8_m(...) __riscv_vloxei16_v_u32m8_tumu(__VA_ARGS__) -#define vloxei32_v_u32mf2_m(...) __riscv_vloxei32_v_u32mf2_tumu(__VA_ARGS__) -#define vloxei32_v_u32m1_m(...) __riscv_vloxei32_v_u32m1_tumu(__VA_ARGS__) -#define vloxei32_v_u32m2_m(...) __riscv_vloxei32_v_u32m2_tumu(__VA_ARGS__) -#define vloxei32_v_u32m4_m(...) __riscv_vloxei32_v_u32m4_tumu(__VA_ARGS__) -#define vloxei32_v_u32m8_m(...) __riscv_vloxei32_v_u32m8_tumu(__VA_ARGS__) -#define vloxei64_v_u32mf2_m(...) __riscv_vloxei64_v_u32mf2_tumu(__VA_ARGS__) -#define vloxei64_v_u32m1_m(...) __riscv_vloxei64_v_u32m1_tumu(__VA_ARGS__) -#define vloxei64_v_u32m2_m(...) __riscv_vloxei64_v_u32m2_tumu(__VA_ARGS__) -#define vloxei64_v_u32m4_m(...) __riscv_vloxei64_v_u32m4_tumu(__VA_ARGS__) -#define vloxei8_v_u64m1_m(...) __riscv_vloxei8_v_u64m1_tumu(__VA_ARGS__) -#define vloxei8_v_u64m2_m(...) __riscv_vloxei8_v_u64m2_tumu(__VA_ARGS__) -#define vloxei8_v_u64m4_m(...) __riscv_vloxei8_v_u64m4_tumu(__VA_ARGS__) -#define vloxei8_v_u64m8_m(...) __riscv_vloxei8_v_u64m8_tumu(__VA_ARGS__) -#define vloxei16_v_u64m1_m(...) __riscv_vloxei16_v_u64m1_tumu(__VA_ARGS__) -#define vloxei16_v_u64m2_m(...) __riscv_vloxei16_v_u64m2_tumu(__VA_ARGS__) -#define vloxei16_v_u64m4_m(...) __riscv_vloxei16_v_u64m4_tumu(__VA_ARGS__) -#define vloxei16_v_u64m8_m(...) __riscv_vloxei16_v_u64m8_tumu(__VA_ARGS__) -#define vloxei32_v_u64m1_m(...) __riscv_vloxei32_v_u64m1_tumu(__VA_ARGS__) -#define vloxei32_v_u64m2_m(...) __riscv_vloxei32_v_u64m2_tumu(__VA_ARGS__) -#define vloxei32_v_u64m4_m(...) __riscv_vloxei32_v_u64m4_tumu(__VA_ARGS__) -#define vloxei32_v_u64m8_m(...) __riscv_vloxei32_v_u64m8_tumu(__VA_ARGS__) -#define vloxei64_v_u64m1_m(...) __riscv_vloxei64_v_u64m1_tumu(__VA_ARGS__) -#define vloxei64_v_u64m2_m(...) __riscv_vloxei64_v_u64m2_tumu(__VA_ARGS__) -#define vloxei64_v_u64m4_m(...) __riscv_vloxei64_v_u64m4_tumu(__VA_ARGS__) -#define vloxei64_v_u64m8_m(...) __riscv_vloxei64_v_u64m8_tumu(__VA_ARGS__) -#define vluxei8_v_u8mf8_m(...) __riscv_vluxei8_v_u8mf8_tumu(__VA_ARGS__) -#define vluxei8_v_u8mf4_m(...) __riscv_vluxei8_v_u8mf4_tumu(__VA_ARGS__) -#define vluxei8_v_u8mf2_m(...) __riscv_vluxei8_v_u8mf2_tumu(__VA_ARGS__) -#define vluxei8_v_u8m1_m(...) __riscv_vluxei8_v_u8m1_tumu(__VA_ARGS__) -#define vluxei8_v_u8m2_m(...) __riscv_vluxei8_v_u8m2_tumu(__VA_ARGS__) -#define vluxei8_v_u8m4_m(...) __riscv_vluxei8_v_u8m4_tumu(__VA_ARGS__) -#define vluxei8_v_u8m8_m(...) __riscv_vluxei8_v_u8m8_tumu(__VA_ARGS__) -#define vluxei16_v_u8mf8_m(...) __riscv_vluxei16_v_u8mf8_tumu(__VA_ARGS__) -#define vluxei16_v_u8mf4_m(...) __riscv_vluxei16_v_u8mf4_tumu(__VA_ARGS__) -#define vluxei16_v_u8mf2_m(...) __riscv_vluxei16_v_u8mf2_tumu(__VA_ARGS__) -#define vluxei16_v_u8m1_m(...) __riscv_vluxei16_v_u8m1_tumu(__VA_ARGS__) -#define vluxei16_v_u8m2_m(...) __riscv_vluxei16_v_u8m2_tumu(__VA_ARGS__) -#define vluxei16_v_u8m4_m(...) __riscv_vluxei16_v_u8m4_tumu(__VA_ARGS__) -#define vluxei32_v_u8mf8_m(...) __riscv_vluxei32_v_u8mf8_tumu(__VA_ARGS__) -#define vluxei32_v_u8mf4_m(...) __riscv_vluxei32_v_u8mf4_tumu(__VA_ARGS__) -#define vluxei32_v_u8mf2_m(...) __riscv_vluxei32_v_u8mf2_tumu(__VA_ARGS__) -#define vluxei32_v_u8m1_m(...) __riscv_vluxei32_v_u8m1_tumu(__VA_ARGS__) -#define vluxei32_v_u8m2_m(...) __riscv_vluxei32_v_u8m2_tumu(__VA_ARGS__) -#define vluxei64_v_u8mf8_m(...) __riscv_vluxei64_v_u8mf8_tumu(__VA_ARGS__) -#define vluxei64_v_u8mf4_m(...) __riscv_vluxei64_v_u8mf4_tumu(__VA_ARGS__) -#define vluxei64_v_u8mf2_m(...) __riscv_vluxei64_v_u8mf2_tumu(__VA_ARGS__) -#define vluxei64_v_u8m1_m(...) __riscv_vluxei64_v_u8m1_tumu(__VA_ARGS__) -#define vluxei8_v_u16mf4_m(...) __riscv_vluxei8_v_u16mf4_tumu(__VA_ARGS__) -#define vluxei8_v_u16mf2_m(...) __riscv_vluxei8_v_u16mf2_tumu(__VA_ARGS__) -#define vluxei8_v_u16m1_m(...) __riscv_vluxei8_v_u16m1_tumu(__VA_ARGS__) -#define vluxei8_v_u16m2_m(...) __riscv_vluxei8_v_u16m2_tumu(__VA_ARGS__) -#define vluxei8_v_u16m4_m(...) __riscv_vluxei8_v_u16m4_tumu(__VA_ARGS__) -#define vluxei8_v_u16m8_m(...) __riscv_vluxei8_v_u16m8_tumu(__VA_ARGS__) -#define vluxei16_v_u16mf4_m(...) __riscv_vluxei16_v_u16mf4_tumu(__VA_ARGS__) -#define vluxei16_v_u16mf2_m(...) __riscv_vluxei16_v_u16mf2_tumu(__VA_ARGS__) -#define vluxei16_v_u16m1_m(...) __riscv_vluxei16_v_u16m1_tumu(__VA_ARGS__) -#define vluxei16_v_u16m2_m(...) __riscv_vluxei16_v_u16m2_tumu(__VA_ARGS__) -#define vluxei16_v_u16m4_m(...) __riscv_vluxei16_v_u16m4_tumu(__VA_ARGS__) -#define vluxei16_v_u16m8_m(...) __riscv_vluxei16_v_u16m8_tumu(__VA_ARGS__) -#define vluxei32_v_u16mf4_m(...) __riscv_vluxei32_v_u16mf4_tumu(__VA_ARGS__) -#define vluxei32_v_u16mf2_m(...) __riscv_vluxei32_v_u16mf2_tumu(__VA_ARGS__) -#define vluxei32_v_u16m1_m(...) __riscv_vluxei32_v_u16m1_tumu(__VA_ARGS__) -#define vluxei32_v_u16m2_m(...) __riscv_vluxei32_v_u16m2_tumu(__VA_ARGS__) -#define vluxei32_v_u16m4_m(...) __riscv_vluxei32_v_u16m4_tumu(__VA_ARGS__) -#define vluxei64_v_u16mf4_m(...) __riscv_vluxei64_v_u16mf4_tumu(__VA_ARGS__) -#define vluxei64_v_u16mf2_m(...) __riscv_vluxei64_v_u16mf2_tumu(__VA_ARGS__) -#define vluxei64_v_u16m1_m(...) __riscv_vluxei64_v_u16m1_tumu(__VA_ARGS__) -#define vluxei64_v_u16m2_m(...) __riscv_vluxei64_v_u16m2_tumu(__VA_ARGS__) -#define vluxei8_v_u32mf2_m(...) __riscv_vluxei8_v_u32mf2_tumu(__VA_ARGS__) -#define vluxei8_v_u32m1_m(...) __riscv_vluxei8_v_u32m1_tumu(__VA_ARGS__) -#define vluxei8_v_u32m2_m(...) __riscv_vluxei8_v_u32m2_tumu(__VA_ARGS__) -#define vluxei8_v_u32m4_m(...) __riscv_vluxei8_v_u32m4_tumu(__VA_ARGS__) -#define vluxei8_v_u32m8_m(...) __riscv_vluxei8_v_u32m8_tumu(__VA_ARGS__) -#define vluxei16_v_u32mf2_m(...) __riscv_vluxei16_v_u32mf2_tumu(__VA_ARGS__) -#define vluxei16_v_u32m1_m(...) __riscv_vluxei16_v_u32m1_tumu(__VA_ARGS__) -#define vluxei16_v_u32m2_m(...) __riscv_vluxei16_v_u32m2_tumu(__VA_ARGS__) -#define vluxei16_v_u32m4_m(...) __riscv_vluxei16_v_u32m4_tumu(__VA_ARGS__) -#define vluxei16_v_u32m8_m(...) __riscv_vluxei16_v_u32m8_tumu(__VA_ARGS__) -#define vluxei32_v_u32mf2_m(...) __riscv_vluxei32_v_u32mf2_tumu(__VA_ARGS__) -#define vluxei32_v_u32m1_m(...) __riscv_vluxei32_v_u32m1_tumu(__VA_ARGS__) -#define vluxei32_v_u32m2_m(...) __riscv_vluxei32_v_u32m2_tumu(__VA_ARGS__) -#define vluxei32_v_u32m4_m(...) __riscv_vluxei32_v_u32m4_tumu(__VA_ARGS__) -#define vluxei32_v_u32m8_m(...) __riscv_vluxei32_v_u32m8_tumu(__VA_ARGS__) -#define vluxei64_v_u32mf2_m(...) __riscv_vluxei64_v_u32mf2_tumu(__VA_ARGS__) -#define vluxei64_v_u32m1_m(...) __riscv_vluxei64_v_u32m1_tumu(__VA_ARGS__) -#define vluxei64_v_u32m2_m(...) __riscv_vluxei64_v_u32m2_tumu(__VA_ARGS__) -#define vluxei64_v_u32m4_m(...) __riscv_vluxei64_v_u32m4_tumu(__VA_ARGS__) -#define vluxei8_v_u64m1_m(...) __riscv_vluxei8_v_u64m1_tumu(__VA_ARGS__) -#define vluxei8_v_u64m2_m(...) __riscv_vluxei8_v_u64m2_tumu(__VA_ARGS__) -#define vluxei8_v_u64m4_m(...) __riscv_vluxei8_v_u64m4_tumu(__VA_ARGS__) -#define vluxei8_v_u64m8_m(...) __riscv_vluxei8_v_u64m8_tumu(__VA_ARGS__) -#define vluxei16_v_u64m1_m(...) __riscv_vluxei16_v_u64m1_tumu(__VA_ARGS__) -#define vluxei16_v_u64m2_m(...) __riscv_vluxei16_v_u64m2_tumu(__VA_ARGS__) -#define vluxei16_v_u64m4_m(...) __riscv_vluxei16_v_u64m4_tumu(__VA_ARGS__) -#define vluxei16_v_u64m8_m(...) __riscv_vluxei16_v_u64m8_tumu(__VA_ARGS__) -#define vluxei32_v_u64m1_m(...) __riscv_vluxei32_v_u64m1_tumu(__VA_ARGS__) -#define vluxei32_v_u64m2_m(...) __riscv_vluxei32_v_u64m2_tumu(__VA_ARGS__) -#define vluxei32_v_u64m4_m(...) __riscv_vluxei32_v_u64m4_tumu(__VA_ARGS__) -#define vluxei32_v_u64m8_m(...) __riscv_vluxei32_v_u64m8_tumu(__VA_ARGS__) -#define vluxei64_v_u64m1_m(...) __riscv_vluxei64_v_u64m1_tumu(__VA_ARGS__) -#define vluxei64_v_u64m2_m(...) __riscv_vluxei64_v_u64m2_tumu(__VA_ARGS__) -#define vluxei64_v_u64m4_m(...) __riscv_vluxei64_v_u64m4_tumu(__VA_ARGS__) -#define vluxei64_v_u64m8_m(...) __riscv_vluxei64_v_u64m8_tumu(__VA_ARGS__) -#define vsoxei8_v_f16mf4(...) __riscv_vsoxei8_v_f16mf4(__VA_ARGS__) -#define vsoxei8_v_f16mf2(...) __riscv_vsoxei8_v_f16mf2(__VA_ARGS__) -#define vsoxei8_v_f16m1(...) __riscv_vsoxei8_v_f16m1(__VA_ARGS__) -#define vsoxei8_v_f16m2(...) __riscv_vsoxei8_v_f16m2(__VA_ARGS__) -#define vsoxei8_v_f16m4(...) __riscv_vsoxei8_v_f16m4(__VA_ARGS__) -#define vsoxei8_v_f16m8(...) __riscv_vsoxei8_v_f16m8(__VA_ARGS__) -#define vsoxei16_v_f16mf4(...) __riscv_vsoxei16_v_f16mf4(__VA_ARGS__) -#define vsoxei16_v_f16mf2(...) __riscv_vsoxei16_v_f16mf2(__VA_ARGS__) -#define vsoxei16_v_f16m1(...) __riscv_vsoxei16_v_f16m1(__VA_ARGS__) -#define vsoxei16_v_f16m2(...) __riscv_vsoxei16_v_f16m2(__VA_ARGS__) -#define vsoxei16_v_f16m4(...) __riscv_vsoxei16_v_f16m4(__VA_ARGS__) -#define vsoxei16_v_f16m8(...) __riscv_vsoxei16_v_f16m8(__VA_ARGS__) -#define vsoxei32_v_f16mf4(...) __riscv_vsoxei32_v_f16mf4(__VA_ARGS__) -#define vsoxei32_v_f16mf2(...) __riscv_vsoxei32_v_f16mf2(__VA_ARGS__) -#define vsoxei32_v_f16m1(...) __riscv_vsoxei32_v_f16m1(__VA_ARGS__) -#define vsoxei32_v_f16m2(...) __riscv_vsoxei32_v_f16m2(__VA_ARGS__) -#define vsoxei32_v_f16m4(...) __riscv_vsoxei32_v_f16m4(__VA_ARGS__) -#define vsoxei64_v_f16mf4(...) __riscv_vsoxei64_v_f16mf4(__VA_ARGS__) -#define vsoxei64_v_f16mf2(...) __riscv_vsoxei64_v_f16mf2(__VA_ARGS__) -#define vsoxei64_v_f16m1(...) __riscv_vsoxei64_v_f16m1(__VA_ARGS__) -#define vsoxei64_v_f16m2(...) __riscv_vsoxei64_v_f16m2(__VA_ARGS__) -#define vsoxei8_v_f32mf2(...) __riscv_vsoxei8_v_f32mf2(__VA_ARGS__) -#define vsoxei8_v_f32m1(...) __riscv_vsoxei8_v_f32m1(__VA_ARGS__) -#define vsoxei8_v_f32m2(...) __riscv_vsoxei8_v_f32m2(__VA_ARGS__) -#define vsoxei8_v_f32m4(...) __riscv_vsoxei8_v_f32m4(__VA_ARGS__) -#define vsoxei8_v_f32m8(...) __riscv_vsoxei8_v_f32m8(__VA_ARGS__) -#define vsoxei16_v_f32mf2(...) __riscv_vsoxei16_v_f32mf2(__VA_ARGS__) -#define vsoxei16_v_f32m1(...) __riscv_vsoxei16_v_f32m1(__VA_ARGS__) -#define vsoxei16_v_f32m2(...) __riscv_vsoxei16_v_f32m2(__VA_ARGS__) -#define vsoxei16_v_f32m4(...) __riscv_vsoxei16_v_f32m4(__VA_ARGS__) -#define vsoxei16_v_f32m8(...) __riscv_vsoxei16_v_f32m8(__VA_ARGS__) -#define vsoxei32_v_f32mf2(...) __riscv_vsoxei32_v_f32mf2(__VA_ARGS__) -#define vsoxei32_v_f32m1(...) __riscv_vsoxei32_v_f32m1(__VA_ARGS__) -#define vsoxei32_v_f32m2(...) __riscv_vsoxei32_v_f32m2(__VA_ARGS__) -#define vsoxei32_v_f32m4(...) __riscv_vsoxei32_v_f32m4(__VA_ARGS__) -#define vsoxei32_v_f32m8(...) __riscv_vsoxei32_v_f32m8(__VA_ARGS__) -#define vsoxei64_v_f32mf2(...) __riscv_vsoxei64_v_f32mf2(__VA_ARGS__) -#define vsoxei64_v_f32m1(...) __riscv_vsoxei64_v_f32m1(__VA_ARGS__) -#define vsoxei64_v_f32m2(...) __riscv_vsoxei64_v_f32m2(__VA_ARGS__) -#define vsoxei64_v_f32m4(...) __riscv_vsoxei64_v_f32m4(__VA_ARGS__) -#define vsoxei8_v_f64m1(...) __riscv_vsoxei8_v_f64m1(__VA_ARGS__) -#define vsoxei8_v_f64m2(...) __riscv_vsoxei8_v_f64m2(__VA_ARGS__) -#define vsoxei8_v_f64m4(...) __riscv_vsoxei8_v_f64m4(__VA_ARGS__) -#define vsoxei8_v_f64m8(...) __riscv_vsoxei8_v_f64m8(__VA_ARGS__) -#define vsoxei16_v_f64m1(...) __riscv_vsoxei16_v_f64m1(__VA_ARGS__) -#define vsoxei16_v_f64m2(...) __riscv_vsoxei16_v_f64m2(__VA_ARGS__) -#define vsoxei16_v_f64m4(...) __riscv_vsoxei16_v_f64m4(__VA_ARGS__) -#define vsoxei16_v_f64m8(...) __riscv_vsoxei16_v_f64m8(__VA_ARGS__) -#define vsoxei32_v_f64m1(...) __riscv_vsoxei32_v_f64m1(__VA_ARGS__) -#define vsoxei32_v_f64m2(...) __riscv_vsoxei32_v_f64m2(__VA_ARGS__) -#define vsoxei32_v_f64m4(...) __riscv_vsoxei32_v_f64m4(__VA_ARGS__) -#define vsoxei32_v_f64m8(...) __riscv_vsoxei32_v_f64m8(__VA_ARGS__) -#define vsoxei64_v_f64m1(...) __riscv_vsoxei64_v_f64m1(__VA_ARGS__) -#define vsoxei64_v_f64m2(...) __riscv_vsoxei64_v_f64m2(__VA_ARGS__) -#define vsoxei64_v_f64m4(...) __riscv_vsoxei64_v_f64m4(__VA_ARGS__) -#define vsoxei64_v_f64m8(...) __riscv_vsoxei64_v_f64m8(__VA_ARGS__) -#define vsuxei8_v_f16mf4(...) __riscv_vsuxei8_v_f16mf4(__VA_ARGS__) -#define vsuxei8_v_f16mf2(...) __riscv_vsuxei8_v_f16mf2(__VA_ARGS__) -#define vsuxei8_v_f16m1(...) __riscv_vsuxei8_v_f16m1(__VA_ARGS__) -#define vsuxei8_v_f16m2(...) __riscv_vsuxei8_v_f16m2(__VA_ARGS__) -#define vsuxei8_v_f16m4(...) __riscv_vsuxei8_v_f16m4(__VA_ARGS__) -#define vsuxei8_v_f16m8(...) __riscv_vsuxei8_v_f16m8(__VA_ARGS__) -#define vsuxei16_v_f16mf4(...) __riscv_vsuxei16_v_f16mf4(__VA_ARGS__) -#define vsuxei16_v_f16mf2(...) __riscv_vsuxei16_v_f16mf2(__VA_ARGS__) -#define vsuxei16_v_f16m1(...) __riscv_vsuxei16_v_f16m1(__VA_ARGS__) -#define vsuxei16_v_f16m2(...) __riscv_vsuxei16_v_f16m2(__VA_ARGS__) -#define vsuxei16_v_f16m4(...) __riscv_vsuxei16_v_f16m4(__VA_ARGS__) -#define vsuxei16_v_f16m8(...) __riscv_vsuxei16_v_f16m8(__VA_ARGS__) -#define vsuxei32_v_f16mf4(...) __riscv_vsuxei32_v_f16mf4(__VA_ARGS__) -#define vsuxei32_v_f16mf2(...) __riscv_vsuxei32_v_f16mf2(__VA_ARGS__) -#define vsuxei32_v_f16m1(...) __riscv_vsuxei32_v_f16m1(__VA_ARGS__) -#define vsuxei32_v_f16m2(...) __riscv_vsuxei32_v_f16m2(__VA_ARGS__) -#define vsuxei32_v_f16m4(...) __riscv_vsuxei32_v_f16m4(__VA_ARGS__) -#define vsuxei64_v_f16mf4(...) __riscv_vsuxei64_v_f16mf4(__VA_ARGS__) -#define vsuxei64_v_f16mf2(...) __riscv_vsuxei64_v_f16mf2(__VA_ARGS__) -#define vsuxei64_v_f16m1(...) __riscv_vsuxei64_v_f16m1(__VA_ARGS__) -#define vsuxei64_v_f16m2(...) __riscv_vsuxei64_v_f16m2(__VA_ARGS__) -#define vsuxei8_v_f32mf2(...) __riscv_vsuxei8_v_f32mf2(__VA_ARGS__) -#define vsuxei8_v_f32m1(...) __riscv_vsuxei8_v_f32m1(__VA_ARGS__) -#define vsuxei8_v_f32m2(...) __riscv_vsuxei8_v_f32m2(__VA_ARGS__) -#define vsuxei8_v_f32m4(...) __riscv_vsuxei8_v_f32m4(__VA_ARGS__) -#define vsuxei8_v_f32m8(...) __riscv_vsuxei8_v_f32m8(__VA_ARGS__) -#define vsuxei16_v_f32mf2(...) __riscv_vsuxei16_v_f32mf2(__VA_ARGS__) -#define vsuxei16_v_f32m1(...) __riscv_vsuxei16_v_f32m1(__VA_ARGS__) -#define vsuxei16_v_f32m2(...) __riscv_vsuxei16_v_f32m2(__VA_ARGS__) -#define vsuxei16_v_f32m4(...) __riscv_vsuxei16_v_f32m4(__VA_ARGS__) -#define vsuxei16_v_f32m8(...) __riscv_vsuxei16_v_f32m8(__VA_ARGS__) -#define vsuxei32_v_f32mf2(...) __riscv_vsuxei32_v_f32mf2(__VA_ARGS__) -#define vsuxei32_v_f32m1(...) __riscv_vsuxei32_v_f32m1(__VA_ARGS__) -#define vsuxei32_v_f32m2(...) __riscv_vsuxei32_v_f32m2(__VA_ARGS__) -#define vsuxei32_v_f32m4(...) __riscv_vsuxei32_v_f32m4(__VA_ARGS__) -#define vsuxei32_v_f32m8(...) __riscv_vsuxei32_v_f32m8(__VA_ARGS__) -#define vsuxei64_v_f32mf2(...) __riscv_vsuxei64_v_f32mf2(__VA_ARGS__) -#define vsuxei64_v_f32m1(...) __riscv_vsuxei64_v_f32m1(__VA_ARGS__) -#define vsuxei64_v_f32m2(...) __riscv_vsuxei64_v_f32m2(__VA_ARGS__) -#define vsuxei64_v_f32m4(...) __riscv_vsuxei64_v_f32m4(__VA_ARGS__) -#define vsuxei8_v_f64m1(...) __riscv_vsuxei8_v_f64m1(__VA_ARGS__) -#define vsuxei8_v_f64m2(...) __riscv_vsuxei8_v_f64m2(__VA_ARGS__) -#define vsuxei8_v_f64m4(...) __riscv_vsuxei8_v_f64m4(__VA_ARGS__) -#define vsuxei8_v_f64m8(...) __riscv_vsuxei8_v_f64m8(__VA_ARGS__) -#define vsuxei16_v_f64m1(...) __riscv_vsuxei16_v_f64m1(__VA_ARGS__) -#define vsuxei16_v_f64m2(...) __riscv_vsuxei16_v_f64m2(__VA_ARGS__) -#define vsuxei16_v_f64m4(...) __riscv_vsuxei16_v_f64m4(__VA_ARGS__) -#define vsuxei16_v_f64m8(...) __riscv_vsuxei16_v_f64m8(__VA_ARGS__) -#define vsuxei32_v_f64m1(...) __riscv_vsuxei32_v_f64m1(__VA_ARGS__) -#define vsuxei32_v_f64m2(...) __riscv_vsuxei32_v_f64m2(__VA_ARGS__) -#define vsuxei32_v_f64m4(...) __riscv_vsuxei32_v_f64m4(__VA_ARGS__) -#define vsuxei32_v_f64m8(...) __riscv_vsuxei32_v_f64m8(__VA_ARGS__) -#define vsuxei64_v_f64m1(...) __riscv_vsuxei64_v_f64m1(__VA_ARGS__) -#define vsuxei64_v_f64m2(...) __riscv_vsuxei64_v_f64m2(__VA_ARGS__) -#define vsuxei64_v_f64m4(...) __riscv_vsuxei64_v_f64m4(__VA_ARGS__) -#define vsuxei64_v_f64m8(...) __riscv_vsuxei64_v_f64m8(__VA_ARGS__) -#define vsoxei8_v_i8mf8(...) __riscv_vsoxei8_v_i8mf8(__VA_ARGS__) -#define vsoxei8_v_i8mf4(...) __riscv_vsoxei8_v_i8mf4(__VA_ARGS__) -#define vsoxei8_v_i8mf2(...) __riscv_vsoxei8_v_i8mf2(__VA_ARGS__) -#define vsoxei8_v_i8m1(...) __riscv_vsoxei8_v_i8m1(__VA_ARGS__) -#define vsoxei8_v_i8m2(...) __riscv_vsoxei8_v_i8m2(__VA_ARGS__) -#define vsoxei8_v_i8m4(...) __riscv_vsoxei8_v_i8m4(__VA_ARGS__) -#define vsoxei8_v_i8m8(...) __riscv_vsoxei8_v_i8m8(__VA_ARGS__) -#define vsoxei16_v_i8mf8(...) __riscv_vsoxei16_v_i8mf8(__VA_ARGS__) -#define vsoxei16_v_i8mf4(...) __riscv_vsoxei16_v_i8mf4(__VA_ARGS__) -#define vsoxei16_v_i8mf2(...) __riscv_vsoxei16_v_i8mf2(__VA_ARGS__) -#define vsoxei16_v_i8m1(...) __riscv_vsoxei16_v_i8m1(__VA_ARGS__) -#define vsoxei16_v_i8m2(...) __riscv_vsoxei16_v_i8m2(__VA_ARGS__) -#define vsoxei16_v_i8m4(...) __riscv_vsoxei16_v_i8m4(__VA_ARGS__) -#define vsoxei32_v_i8mf8(...) __riscv_vsoxei32_v_i8mf8(__VA_ARGS__) -#define vsoxei32_v_i8mf4(...) __riscv_vsoxei32_v_i8mf4(__VA_ARGS__) -#define vsoxei32_v_i8mf2(...) __riscv_vsoxei32_v_i8mf2(__VA_ARGS__) -#define vsoxei32_v_i8m1(...) __riscv_vsoxei32_v_i8m1(__VA_ARGS__) -#define vsoxei32_v_i8m2(...) __riscv_vsoxei32_v_i8m2(__VA_ARGS__) -#define vsoxei64_v_i8mf8(...) __riscv_vsoxei64_v_i8mf8(__VA_ARGS__) -#define vsoxei64_v_i8mf4(...) __riscv_vsoxei64_v_i8mf4(__VA_ARGS__) -#define vsoxei64_v_i8mf2(...) __riscv_vsoxei64_v_i8mf2(__VA_ARGS__) -#define vsoxei64_v_i8m1(...) __riscv_vsoxei64_v_i8m1(__VA_ARGS__) -#define vsoxei8_v_i16mf4(...) __riscv_vsoxei8_v_i16mf4(__VA_ARGS__) -#define vsoxei8_v_i16mf2(...) __riscv_vsoxei8_v_i16mf2(__VA_ARGS__) -#define vsoxei8_v_i16m1(...) __riscv_vsoxei8_v_i16m1(__VA_ARGS__) -#define vsoxei8_v_i16m2(...) __riscv_vsoxei8_v_i16m2(__VA_ARGS__) -#define vsoxei8_v_i16m4(...) __riscv_vsoxei8_v_i16m4(__VA_ARGS__) -#define vsoxei8_v_i16m8(...) __riscv_vsoxei8_v_i16m8(__VA_ARGS__) -#define vsoxei16_v_i16mf4(...) __riscv_vsoxei16_v_i16mf4(__VA_ARGS__) -#define vsoxei16_v_i16mf2(...) __riscv_vsoxei16_v_i16mf2(__VA_ARGS__) -#define vsoxei16_v_i16m1(...) __riscv_vsoxei16_v_i16m1(__VA_ARGS__) -#define vsoxei16_v_i16m2(...) __riscv_vsoxei16_v_i16m2(__VA_ARGS__) -#define vsoxei16_v_i16m4(...) __riscv_vsoxei16_v_i16m4(__VA_ARGS__) -#define vsoxei16_v_i16m8(...) __riscv_vsoxei16_v_i16m8(__VA_ARGS__) -#define vsoxei32_v_i16mf4(...) __riscv_vsoxei32_v_i16mf4(__VA_ARGS__) -#define vsoxei32_v_i16mf2(...) __riscv_vsoxei32_v_i16mf2(__VA_ARGS__) -#define vsoxei32_v_i16m1(...) __riscv_vsoxei32_v_i16m1(__VA_ARGS__) -#define vsoxei32_v_i16m2(...) __riscv_vsoxei32_v_i16m2(__VA_ARGS__) -#define vsoxei32_v_i16m4(...) __riscv_vsoxei32_v_i16m4(__VA_ARGS__) -#define vsoxei64_v_i16mf4(...) __riscv_vsoxei64_v_i16mf4(__VA_ARGS__) -#define vsoxei64_v_i16mf2(...) __riscv_vsoxei64_v_i16mf2(__VA_ARGS__) -#define vsoxei64_v_i16m1(...) __riscv_vsoxei64_v_i16m1(__VA_ARGS__) -#define vsoxei64_v_i16m2(...) __riscv_vsoxei64_v_i16m2(__VA_ARGS__) -#define vsoxei8_v_i32mf2(...) __riscv_vsoxei8_v_i32mf2(__VA_ARGS__) -#define vsoxei8_v_i32m1(...) __riscv_vsoxei8_v_i32m1(__VA_ARGS__) -#define vsoxei8_v_i32m2(...) __riscv_vsoxei8_v_i32m2(__VA_ARGS__) -#define vsoxei8_v_i32m4(...) __riscv_vsoxei8_v_i32m4(__VA_ARGS__) -#define vsoxei8_v_i32m8(...) __riscv_vsoxei8_v_i32m8(__VA_ARGS__) -#define vsoxei16_v_i32mf2(...) __riscv_vsoxei16_v_i32mf2(__VA_ARGS__) -#define vsoxei16_v_i32m1(...) __riscv_vsoxei16_v_i32m1(__VA_ARGS__) -#define vsoxei16_v_i32m2(...) __riscv_vsoxei16_v_i32m2(__VA_ARGS__) -#define vsoxei16_v_i32m4(...) __riscv_vsoxei16_v_i32m4(__VA_ARGS__) -#define vsoxei16_v_i32m8(...) __riscv_vsoxei16_v_i32m8(__VA_ARGS__) -#define vsoxei32_v_i32mf2(...) __riscv_vsoxei32_v_i32mf2(__VA_ARGS__) -#define vsoxei32_v_i32m1(...) __riscv_vsoxei32_v_i32m1(__VA_ARGS__) -#define vsoxei32_v_i32m2(...) __riscv_vsoxei32_v_i32m2(__VA_ARGS__) -#define vsoxei32_v_i32m4(...) __riscv_vsoxei32_v_i32m4(__VA_ARGS__) -#define vsoxei32_v_i32m8(...) __riscv_vsoxei32_v_i32m8(__VA_ARGS__) -#define vsoxei64_v_i32mf2(...) __riscv_vsoxei64_v_i32mf2(__VA_ARGS__) -#define vsoxei64_v_i32m1(...) __riscv_vsoxei64_v_i32m1(__VA_ARGS__) -#define vsoxei64_v_i32m2(...) __riscv_vsoxei64_v_i32m2(__VA_ARGS__) -#define vsoxei64_v_i32m4(...) __riscv_vsoxei64_v_i32m4(__VA_ARGS__) -#define vsoxei8_v_i64m1(...) __riscv_vsoxei8_v_i64m1(__VA_ARGS__) -#define vsoxei8_v_i64m2(...) __riscv_vsoxei8_v_i64m2(__VA_ARGS__) -#define vsoxei8_v_i64m4(...) __riscv_vsoxei8_v_i64m4(__VA_ARGS__) -#define vsoxei8_v_i64m8(...) __riscv_vsoxei8_v_i64m8(__VA_ARGS__) -#define vsoxei16_v_i64m1(...) __riscv_vsoxei16_v_i64m1(__VA_ARGS__) -#define vsoxei16_v_i64m2(...) __riscv_vsoxei16_v_i64m2(__VA_ARGS__) -#define vsoxei16_v_i64m4(...) __riscv_vsoxei16_v_i64m4(__VA_ARGS__) -#define vsoxei16_v_i64m8(...) __riscv_vsoxei16_v_i64m8(__VA_ARGS__) -#define vsoxei32_v_i64m1(...) __riscv_vsoxei32_v_i64m1(__VA_ARGS__) -#define vsoxei32_v_i64m2(...) __riscv_vsoxei32_v_i64m2(__VA_ARGS__) -#define vsoxei32_v_i64m4(...) __riscv_vsoxei32_v_i64m4(__VA_ARGS__) -#define vsoxei32_v_i64m8(...) __riscv_vsoxei32_v_i64m8(__VA_ARGS__) -#define vsoxei64_v_i64m1(...) __riscv_vsoxei64_v_i64m1(__VA_ARGS__) -#define vsoxei64_v_i64m2(...) __riscv_vsoxei64_v_i64m2(__VA_ARGS__) -#define vsoxei64_v_i64m4(...) __riscv_vsoxei64_v_i64m4(__VA_ARGS__) -#define vsoxei64_v_i64m8(...) __riscv_vsoxei64_v_i64m8(__VA_ARGS__) -#define vsuxei8_v_i8mf8(...) __riscv_vsuxei8_v_i8mf8(__VA_ARGS__) -#define vsuxei8_v_i8mf4(...) __riscv_vsuxei8_v_i8mf4(__VA_ARGS__) -#define vsuxei8_v_i8mf2(...) __riscv_vsuxei8_v_i8mf2(__VA_ARGS__) -#define vsuxei8_v_i8m1(...) __riscv_vsuxei8_v_i8m1(__VA_ARGS__) -#define vsuxei8_v_i8m2(...) __riscv_vsuxei8_v_i8m2(__VA_ARGS__) -#define vsuxei8_v_i8m4(...) __riscv_vsuxei8_v_i8m4(__VA_ARGS__) -#define vsuxei8_v_i8m8(...) __riscv_vsuxei8_v_i8m8(__VA_ARGS__) -#define vsuxei16_v_i8mf8(...) __riscv_vsuxei16_v_i8mf8(__VA_ARGS__) -#define vsuxei16_v_i8mf4(...) __riscv_vsuxei16_v_i8mf4(__VA_ARGS__) -#define vsuxei16_v_i8mf2(...) __riscv_vsuxei16_v_i8mf2(__VA_ARGS__) -#define vsuxei16_v_i8m1(...) __riscv_vsuxei16_v_i8m1(__VA_ARGS__) -#define vsuxei16_v_i8m2(...) __riscv_vsuxei16_v_i8m2(__VA_ARGS__) -#define vsuxei16_v_i8m4(...) __riscv_vsuxei16_v_i8m4(__VA_ARGS__) -#define vsuxei32_v_i8mf8(...) __riscv_vsuxei32_v_i8mf8(__VA_ARGS__) -#define vsuxei32_v_i8mf4(...) __riscv_vsuxei32_v_i8mf4(__VA_ARGS__) -#define vsuxei32_v_i8mf2(...) __riscv_vsuxei32_v_i8mf2(__VA_ARGS__) -#define vsuxei32_v_i8m1(...) __riscv_vsuxei32_v_i8m1(__VA_ARGS__) -#define vsuxei32_v_i8m2(...) __riscv_vsuxei32_v_i8m2(__VA_ARGS__) -#define vsuxei64_v_i8mf8(...) __riscv_vsuxei64_v_i8mf8(__VA_ARGS__) -#define vsuxei64_v_i8mf4(...) __riscv_vsuxei64_v_i8mf4(__VA_ARGS__) -#define vsuxei64_v_i8mf2(...) __riscv_vsuxei64_v_i8mf2(__VA_ARGS__) -#define vsuxei64_v_i8m1(...) __riscv_vsuxei64_v_i8m1(__VA_ARGS__) -#define vsuxei8_v_i16mf4(...) __riscv_vsuxei8_v_i16mf4(__VA_ARGS__) -#define vsuxei8_v_i16mf2(...) __riscv_vsuxei8_v_i16mf2(__VA_ARGS__) -#define vsuxei8_v_i16m1(...) __riscv_vsuxei8_v_i16m1(__VA_ARGS__) -#define vsuxei8_v_i16m2(...) __riscv_vsuxei8_v_i16m2(__VA_ARGS__) -#define vsuxei8_v_i16m4(...) __riscv_vsuxei8_v_i16m4(__VA_ARGS__) -#define vsuxei8_v_i16m8(...) __riscv_vsuxei8_v_i16m8(__VA_ARGS__) -#define vsuxei16_v_i16mf4(...) __riscv_vsuxei16_v_i16mf4(__VA_ARGS__) -#define vsuxei16_v_i16mf2(...) __riscv_vsuxei16_v_i16mf2(__VA_ARGS__) -#define vsuxei16_v_i16m1(...) __riscv_vsuxei16_v_i16m1(__VA_ARGS__) -#define vsuxei16_v_i16m2(...) __riscv_vsuxei16_v_i16m2(__VA_ARGS__) -#define vsuxei16_v_i16m4(...) __riscv_vsuxei16_v_i16m4(__VA_ARGS__) -#define vsuxei16_v_i16m8(...) __riscv_vsuxei16_v_i16m8(__VA_ARGS__) -#define vsuxei32_v_i16mf4(...) __riscv_vsuxei32_v_i16mf4(__VA_ARGS__) -#define vsuxei32_v_i16mf2(...) __riscv_vsuxei32_v_i16mf2(__VA_ARGS__) -#define vsuxei32_v_i16m1(...) __riscv_vsuxei32_v_i16m1(__VA_ARGS__) -#define vsuxei32_v_i16m2(...) __riscv_vsuxei32_v_i16m2(__VA_ARGS__) -#define vsuxei32_v_i16m4(...) __riscv_vsuxei32_v_i16m4(__VA_ARGS__) -#define vsuxei64_v_i16mf4(...) __riscv_vsuxei64_v_i16mf4(__VA_ARGS__) -#define vsuxei64_v_i16mf2(...) __riscv_vsuxei64_v_i16mf2(__VA_ARGS__) -#define vsuxei64_v_i16m1(...) __riscv_vsuxei64_v_i16m1(__VA_ARGS__) -#define vsuxei64_v_i16m2(...) __riscv_vsuxei64_v_i16m2(__VA_ARGS__) -#define vsuxei8_v_i32mf2(...) __riscv_vsuxei8_v_i32mf2(__VA_ARGS__) -#define vsuxei8_v_i32m1(...) __riscv_vsuxei8_v_i32m1(__VA_ARGS__) -#define vsuxei8_v_i32m2(...) __riscv_vsuxei8_v_i32m2(__VA_ARGS__) -#define vsuxei8_v_i32m4(...) __riscv_vsuxei8_v_i32m4(__VA_ARGS__) -#define vsuxei8_v_i32m8(...) __riscv_vsuxei8_v_i32m8(__VA_ARGS__) -#define vsuxei16_v_i32mf2(...) __riscv_vsuxei16_v_i32mf2(__VA_ARGS__) -#define vsuxei16_v_i32m1(...) __riscv_vsuxei16_v_i32m1(__VA_ARGS__) -#define vsuxei16_v_i32m2(...) __riscv_vsuxei16_v_i32m2(__VA_ARGS__) -#define vsuxei16_v_i32m4(...) __riscv_vsuxei16_v_i32m4(__VA_ARGS__) -#define vsuxei16_v_i32m8(...) __riscv_vsuxei16_v_i32m8(__VA_ARGS__) -#define vsuxei32_v_i32mf2(...) __riscv_vsuxei32_v_i32mf2(__VA_ARGS__) -#define vsuxei32_v_i32m1(...) __riscv_vsuxei32_v_i32m1(__VA_ARGS__) -#define vsuxei32_v_i32m2(...) __riscv_vsuxei32_v_i32m2(__VA_ARGS__) -#define vsuxei32_v_i32m4(...) __riscv_vsuxei32_v_i32m4(__VA_ARGS__) -#define vsuxei32_v_i32m8(...) __riscv_vsuxei32_v_i32m8(__VA_ARGS__) -#define vsuxei64_v_i32mf2(...) __riscv_vsuxei64_v_i32mf2(__VA_ARGS__) -#define vsuxei64_v_i32m1(...) __riscv_vsuxei64_v_i32m1(__VA_ARGS__) -#define vsuxei64_v_i32m2(...) __riscv_vsuxei64_v_i32m2(__VA_ARGS__) -#define vsuxei64_v_i32m4(...) __riscv_vsuxei64_v_i32m4(__VA_ARGS__) -#define vsuxei8_v_i64m1(...) __riscv_vsuxei8_v_i64m1(__VA_ARGS__) -#define vsuxei8_v_i64m2(...) __riscv_vsuxei8_v_i64m2(__VA_ARGS__) -#define vsuxei8_v_i64m4(...) __riscv_vsuxei8_v_i64m4(__VA_ARGS__) -#define vsuxei8_v_i64m8(...) __riscv_vsuxei8_v_i64m8(__VA_ARGS__) -#define vsuxei16_v_i64m1(...) __riscv_vsuxei16_v_i64m1(__VA_ARGS__) -#define vsuxei16_v_i64m2(...) __riscv_vsuxei16_v_i64m2(__VA_ARGS__) -#define vsuxei16_v_i64m4(...) __riscv_vsuxei16_v_i64m4(__VA_ARGS__) -#define vsuxei16_v_i64m8(...) __riscv_vsuxei16_v_i64m8(__VA_ARGS__) -#define vsuxei32_v_i64m1(...) __riscv_vsuxei32_v_i64m1(__VA_ARGS__) -#define vsuxei32_v_i64m2(...) __riscv_vsuxei32_v_i64m2(__VA_ARGS__) -#define vsuxei32_v_i64m4(...) __riscv_vsuxei32_v_i64m4(__VA_ARGS__) -#define vsuxei32_v_i64m8(...) __riscv_vsuxei32_v_i64m8(__VA_ARGS__) -#define vsuxei64_v_i64m1(...) __riscv_vsuxei64_v_i64m1(__VA_ARGS__) -#define vsuxei64_v_i64m2(...) __riscv_vsuxei64_v_i64m2(__VA_ARGS__) -#define vsuxei64_v_i64m4(...) __riscv_vsuxei64_v_i64m4(__VA_ARGS__) -#define vsuxei64_v_i64m8(...) __riscv_vsuxei64_v_i64m8(__VA_ARGS__) -#define vsoxei8_v_u8mf8(...) __riscv_vsoxei8_v_u8mf8(__VA_ARGS__) -#define vsoxei8_v_u8mf4(...) __riscv_vsoxei8_v_u8mf4(__VA_ARGS__) -#define vsoxei8_v_u8mf2(...) __riscv_vsoxei8_v_u8mf2(__VA_ARGS__) -#define vsoxei8_v_u8m1(...) __riscv_vsoxei8_v_u8m1(__VA_ARGS__) -#define vsoxei8_v_u8m2(...) __riscv_vsoxei8_v_u8m2(__VA_ARGS__) -#define vsoxei8_v_u8m4(...) __riscv_vsoxei8_v_u8m4(__VA_ARGS__) -#define vsoxei8_v_u8m8(...) __riscv_vsoxei8_v_u8m8(__VA_ARGS__) -#define vsoxei16_v_u8mf8(...) __riscv_vsoxei16_v_u8mf8(__VA_ARGS__) -#define vsoxei16_v_u8mf4(...) __riscv_vsoxei16_v_u8mf4(__VA_ARGS__) -#define vsoxei16_v_u8mf2(...) __riscv_vsoxei16_v_u8mf2(__VA_ARGS__) -#define vsoxei16_v_u8m1(...) __riscv_vsoxei16_v_u8m1(__VA_ARGS__) -#define vsoxei16_v_u8m2(...) __riscv_vsoxei16_v_u8m2(__VA_ARGS__) -#define vsoxei16_v_u8m4(...) __riscv_vsoxei16_v_u8m4(__VA_ARGS__) -#define vsoxei32_v_u8mf8(...) __riscv_vsoxei32_v_u8mf8(__VA_ARGS__) -#define vsoxei32_v_u8mf4(...) __riscv_vsoxei32_v_u8mf4(__VA_ARGS__) -#define vsoxei32_v_u8mf2(...) __riscv_vsoxei32_v_u8mf2(__VA_ARGS__) -#define vsoxei32_v_u8m1(...) __riscv_vsoxei32_v_u8m1(__VA_ARGS__) -#define vsoxei32_v_u8m2(...) __riscv_vsoxei32_v_u8m2(__VA_ARGS__) -#define vsoxei64_v_u8mf8(...) __riscv_vsoxei64_v_u8mf8(__VA_ARGS__) -#define vsoxei64_v_u8mf4(...) __riscv_vsoxei64_v_u8mf4(__VA_ARGS__) -#define vsoxei64_v_u8mf2(...) __riscv_vsoxei64_v_u8mf2(__VA_ARGS__) -#define vsoxei64_v_u8m1(...) __riscv_vsoxei64_v_u8m1(__VA_ARGS__) -#define vsoxei8_v_u16mf4(...) __riscv_vsoxei8_v_u16mf4(__VA_ARGS__) -#define vsoxei8_v_u16mf2(...) __riscv_vsoxei8_v_u16mf2(__VA_ARGS__) -#define vsoxei8_v_u16m1(...) __riscv_vsoxei8_v_u16m1(__VA_ARGS__) -#define vsoxei8_v_u16m2(...) __riscv_vsoxei8_v_u16m2(__VA_ARGS__) -#define vsoxei8_v_u16m4(...) __riscv_vsoxei8_v_u16m4(__VA_ARGS__) -#define vsoxei8_v_u16m8(...) __riscv_vsoxei8_v_u16m8(__VA_ARGS__) -#define vsoxei16_v_u16mf4(...) __riscv_vsoxei16_v_u16mf4(__VA_ARGS__) -#define vsoxei16_v_u16mf2(...) __riscv_vsoxei16_v_u16mf2(__VA_ARGS__) -#define vsoxei16_v_u16m1(...) __riscv_vsoxei16_v_u16m1(__VA_ARGS__) -#define vsoxei16_v_u16m2(...) __riscv_vsoxei16_v_u16m2(__VA_ARGS__) -#define vsoxei16_v_u16m4(...) __riscv_vsoxei16_v_u16m4(__VA_ARGS__) -#define vsoxei16_v_u16m8(...) __riscv_vsoxei16_v_u16m8(__VA_ARGS__) -#define vsoxei32_v_u16mf4(...) __riscv_vsoxei32_v_u16mf4(__VA_ARGS__) -#define vsoxei32_v_u16mf2(...) __riscv_vsoxei32_v_u16mf2(__VA_ARGS__) -#define vsoxei32_v_u16m1(...) __riscv_vsoxei32_v_u16m1(__VA_ARGS__) -#define vsoxei32_v_u16m2(...) __riscv_vsoxei32_v_u16m2(__VA_ARGS__) -#define vsoxei32_v_u16m4(...) __riscv_vsoxei32_v_u16m4(__VA_ARGS__) -#define vsoxei64_v_u16mf4(...) __riscv_vsoxei64_v_u16mf4(__VA_ARGS__) -#define vsoxei64_v_u16mf2(...) __riscv_vsoxei64_v_u16mf2(__VA_ARGS__) -#define vsoxei64_v_u16m1(...) __riscv_vsoxei64_v_u16m1(__VA_ARGS__) -#define vsoxei64_v_u16m2(...) __riscv_vsoxei64_v_u16m2(__VA_ARGS__) -#define vsoxei8_v_u32mf2(...) __riscv_vsoxei8_v_u32mf2(__VA_ARGS__) -#define vsoxei8_v_u32m1(...) __riscv_vsoxei8_v_u32m1(__VA_ARGS__) -#define vsoxei8_v_u32m2(...) __riscv_vsoxei8_v_u32m2(__VA_ARGS__) -#define vsoxei8_v_u32m4(...) __riscv_vsoxei8_v_u32m4(__VA_ARGS__) -#define vsoxei8_v_u32m8(...) __riscv_vsoxei8_v_u32m8(__VA_ARGS__) -#define vsoxei16_v_u32mf2(...) __riscv_vsoxei16_v_u32mf2(__VA_ARGS__) -#define vsoxei16_v_u32m1(...) __riscv_vsoxei16_v_u32m1(__VA_ARGS__) -#define vsoxei16_v_u32m2(...) __riscv_vsoxei16_v_u32m2(__VA_ARGS__) -#define vsoxei16_v_u32m4(...) __riscv_vsoxei16_v_u32m4(__VA_ARGS__) -#define vsoxei16_v_u32m8(...) __riscv_vsoxei16_v_u32m8(__VA_ARGS__) -#define vsoxei32_v_u32mf2(...) __riscv_vsoxei32_v_u32mf2(__VA_ARGS__) -#define vsoxei32_v_u32m1(...) __riscv_vsoxei32_v_u32m1(__VA_ARGS__) -#define vsoxei32_v_u32m2(...) __riscv_vsoxei32_v_u32m2(__VA_ARGS__) -#define vsoxei32_v_u32m4(...) __riscv_vsoxei32_v_u32m4(__VA_ARGS__) -#define vsoxei32_v_u32m8(...) __riscv_vsoxei32_v_u32m8(__VA_ARGS__) -#define vsoxei64_v_u32mf2(...) __riscv_vsoxei64_v_u32mf2(__VA_ARGS__) -#define vsoxei64_v_u32m1(...) __riscv_vsoxei64_v_u32m1(__VA_ARGS__) -#define vsoxei64_v_u32m2(...) __riscv_vsoxei64_v_u32m2(__VA_ARGS__) -#define vsoxei64_v_u32m4(...) __riscv_vsoxei64_v_u32m4(__VA_ARGS__) -#define vsoxei8_v_u64m1(...) __riscv_vsoxei8_v_u64m1(__VA_ARGS__) -#define vsoxei8_v_u64m2(...) __riscv_vsoxei8_v_u64m2(__VA_ARGS__) -#define vsoxei8_v_u64m4(...) __riscv_vsoxei8_v_u64m4(__VA_ARGS__) -#define vsoxei8_v_u64m8(...) __riscv_vsoxei8_v_u64m8(__VA_ARGS__) -#define vsoxei16_v_u64m1(...) __riscv_vsoxei16_v_u64m1(__VA_ARGS__) -#define vsoxei16_v_u64m2(...) __riscv_vsoxei16_v_u64m2(__VA_ARGS__) -#define vsoxei16_v_u64m4(...) __riscv_vsoxei16_v_u64m4(__VA_ARGS__) -#define vsoxei16_v_u64m8(...) __riscv_vsoxei16_v_u64m8(__VA_ARGS__) -#define vsoxei32_v_u64m1(...) __riscv_vsoxei32_v_u64m1(__VA_ARGS__) -#define vsoxei32_v_u64m2(...) __riscv_vsoxei32_v_u64m2(__VA_ARGS__) -#define vsoxei32_v_u64m4(...) __riscv_vsoxei32_v_u64m4(__VA_ARGS__) -#define vsoxei32_v_u64m8(...) __riscv_vsoxei32_v_u64m8(__VA_ARGS__) -#define vsoxei64_v_u64m1(...) __riscv_vsoxei64_v_u64m1(__VA_ARGS__) -#define vsoxei64_v_u64m2(...) __riscv_vsoxei64_v_u64m2(__VA_ARGS__) -#define vsoxei64_v_u64m4(...) __riscv_vsoxei64_v_u64m4(__VA_ARGS__) -#define vsoxei64_v_u64m8(...) __riscv_vsoxei64_v_u64m8(__VA_ARGS__) -#define vsuxei8_v_u8mf8(...) __riscv_vsuxei8_v_u8mf8(__VA_ARGS__) -#define vsuxei8_v_u8mf4(...) __riscv_vsuxei8_v_u8mf4(__VA_ARGS__) -#define vsuxei8_v_u8mf2(...) __riscv_vsuxei8_v_u8mf2(__VA_ARGS__) -#define vsuxei8_v_u8m1(...) __riscv_vsuxei8_v_u8m1(__VA_ARGS__) -#define vsuxei8_v_u8m2(...) __riscv_vsuxei8_v_u8m2(__VA_ARGS__) -#define vsuxei8_v_u8m4(...) __riscv_vsuxei8_v_u8m4(__VA_ARGS__) -#define vsuxei8_v_u8m8(...) __riscv_vsuxei8_v_u8m8(__VA_ARGS__) -#define vsuxei16_v_u8mf8(...) __riscv_vsuxei16_v_u8mf8(__VA_ARGS__) -#define vsuxei16_v_u8mf4(...) __riscv_vsuxei16_v_u8mf4(__VA_ARGS__) -#define vsuxei16_v_u8mf2(...) __riscv_vsuxei16_v_u8mf2(__VA_ARGS__) -#define vsuxei16_v_u8m1(...) __riscv_vsuxei16_v_u8m1(__VA_ARGS__) -#define vsuxei16_v_u8m2(...) __riscv_vsuxei16_v_u8m2(__VA_ARGS__) -#define vsuxei16_v_u8m4(...) __riscv_vsuxei16_v_u8m4(__VA_ARGS__) -#define vsuxei32_v_u8mf8(...) __riscv_vsuxei32_v_u8mf8(__VA_ARGS__) -#define vsuxei32_v_u8mf4(...) __riscv_vsuxei32_v_u8mf4(__VA_ARGS__) -#define vsuxei32_v_u8mf2(...) __riscv_vsuxei32_v_u8mf2(__VA_ARGS__) -#define vsuxei32_v_u8m1(...) __riscv_vsuxei32_v_u8m1(__VA_ARGS__) -#define vsuxei32_v_u8m2(...) __riscv_vsuxei32_v_u8m2(__VA_ARGS__) -#define vsuxei64_v_u8mf8(...) __riscv_vsuxei64_v_u8mf8(__VA_ARGS__) -#define vsuxei64_v_u8mf4(...) __riscv_vsuxei64_v_u8mf4(__VA_ARGS__) -#define vsuxei64_v_u8mf2(...) __riscv_vsuxei64_v_u8mf2(__VA_ARGS__) -#define vsuxei64_v_u8m1(...) __riscv_vsuxei64_v_u8m1(__VA_ARGS__) -#define vsuxei8_v_u16mf4(...) __riscv_vsuxei8_v_u16mf4(__VA_ARGS__) -#define vsuxei8_v_u16mf2(...) __riscv_vsuxei8_v_u16mf2(__VA_ARGS__) -#define vsuxei8_v_u16m1(...) __riscv_vsuxei8_v_u16m1(__VA_ARGS__) -#define vsuxei8_v_u16m2(...) __riscv_vsuxei8_v_u16m2(__VA_ARGS__) -#define vsuxei8_v_u16m4(...) __riscv_vsuxei8_v_u16m4(__VA_ARGS__) -#define vsuxei8_v_u16m8(...) __riscv_vsuxei8_v_u16m8(__VA_ARGS__) -#define vsuxei16_v_u16mf4(...) __riscv_vsuxei16_v_u16mf4(__VA_ARGS__) -#define vsuxei16_v_u16mf2(...) __riscv_vsuxei16_v_u16mf2(__VA_ARGS__) -#define vsuxei16_v_u16m1(...) __riscv_vsuxei16_v_u16m1(__VA_ARGS__) -#define vsuxei16_v_u16m2(...) __riscv_vsuxei16_v_u16m2(__VA_ARGS__) -#define vsuxei16_v_u16m4(...) __riscv_vsuxei16_v_u16m4(__VA_ARGS__) -#define vsuxei16_v_u16m8(...) __riscv_vsuxei16_v_u16m8(__VA_ARGS__) -#define vsuxei32_v_u16mf4(...) __riscv_vsuxei32_v_u16mf4(__VA_ARGS__) -#define vsuxei32_v_u16mf2(...) __riscv_vsuxei32_v_u16mf2(__VA_ARGS__) -#define vsuxei32_v_u16m1(...) __riscv_vsuxei32_v_u16m1(__VA_ARGS__) -#define vsuxei32_v_u16m2(...) __riscv_vsuxei32_v_u16m2(__VA_ARGS__) -#define vsuxei32_v_u16m4(...) __riscv_vsuxei32_v_u16m4(__VA_ARGS__) -#define vsuxei64_v_u16mf4(...) __riscv_vsuxei64_v_u16mf4(__VA_ARGS__) -#define vsuxei64_v_u16mf2(...) __riscv_vsuxei64_v_u16mf2(__VA_ARGS__) -#define vsuxei64_v_u16m1(...) __riscv_vsuxei64_v_u16m1(__VA_ARGS__) -#define vsuxei64_v_u16m2(...) __riscv_vsuxei64_v_u16m2(__VA_ARGS__) -#define vsuxei8_v_u32mf2(...) __riscv_vsuxei8_v_u32mf2(__VA_ARGS__) -#define vsuxei8_v_u32m1(...) __riscv_vsuxei8_v_u32m1(__VA_ARGS__) -#define vsuxei8_v_u32m2(...) __riscv_vsuxei8_v_u32m2(__VA_ARGS__) -#define vsuxei8_v_u32m4(...) __riscv_vsuxei8_v_u32m4(__VA_ARGS__) -#define vsuxei8_v_u32m8(...) __riscv_vsuxei8_v_u32m8(__VA_ARGS__) -#define vsuxei16_v_u32mf2(...) __riscv_vsuxei16_v_u32mf2(__VA_ARGS__) -#define vsuxei16_v_u32m1(...) __riscv_vsuxei16_v_u32m1(__VA_ARGS__) -#define vsuxei16_v_u32m2(...) __riscv_vsuxei16_v_u32m2(__VA_ARGS__) -#define vsuxei16_v_u32m4(...) __riscv_vsuxei16_v_u32m4(__VA_ARGS__) -#define vsuxei16_v_u32m8(...) __riscv_vsuxei16_v_u32m8(__VA_ARGS__) -#define vsuxei32_v_u32mf2(...) __riscv_vsuxei32_v_u32mf2(__VA_ARGS__) -#define vsuxei32_v_u32m1(...) __riscv_vsuxei32_v_u32m1(__VA_ARGS__) -#define vsuxei32_v_u32m2(...) __riscv_vsuxei32_v_u32m2(__VA_ARGS__) -#define vsuxei32_v_u32m4(...) __riscv_vsuxei32_v_u32m4(__VA_ARGS__) -#define vsuxei32_v_u32m8(...) __riscv_vsuxei32_v_u32m8(__VA_ARGS__) -#define vsuxei64_v_u32mf2(...) __riscv_vsuxei64_v_u32mf2(__VA_ARGS__) -#define vsuxei64_v_u32m1(...) __riscv_vsuxei64_v_u32m1(__VA_ARGS__) -#define vsuxei64_v_u32m2(...) __riscv_vsuxei64_v_u32m2(__VA_ARGS__) -#define vsuxei64_v_u32m4(...) __riscv_vsuxei64_v_u32m4(__VA_ARGS__) -#define vsuxei8_v_u64m1(...) __riscv_vsuxei8_v_u64m1(__VA_ARGS__) -#define vsuxei8_v_u64m2(...) __riscv_vsuxei8_v_u64m2(__VA_ARGS__) -#define vsuxei8_v_u64m4(...) __riscv_vsuxei8_v_u64m4(__VA_ARGS__) -#define vsuxei8_v_u64m8(...) __riscv_vsuxei8_v_u64m8(__VA_ARGS__) -#define vsuxei16_v_u64m1(...) __riscv_vsuxei16_v_u64m1(__VA_ARGS__) -#define vsuxei16_v_u64m2(...) __riscv_vsuxei16_v_u64m2(__VA_ARGS__) -#define vsuxei16_v_u64m4(...) __riscv_vsuxei16_v_u64m4(__VA_ARGS__) -#define vsuxei16_v_u64m8(...) __riscv_vsuxei16_v_u64m8(__VA_ARGS__) -#define vsuxei32_v_u64m1(...) __riscv_vsuxei32_v_u64m1(__VA_ARGS__) -#define vsuxei32_v_u64m2(...) __riscv_vsuxei32_v_u64m2(__VA_ARGS__) -#define vsuxei32_v_u64m4(...) __riscv_vsuxei32_v_u64m4(__VA_ARGS__) -#define vsuxei32_v_u64m8(...) __riscv_vsuxei32_v_u64m8(__VA_ARGS__) -#define vsuxei64_v_u64m1(...) __riscv_vsuxei64_v_u64m1(__VA_ARGS__) -#define vsuxei64_v_u64m2(...) __riscv_vsuxei64_v_u64m2(__VA_ARGS__) -#define vsuxei64_v_u64m4(...) __riscv_vsuxei64_v_u64m4(__VA_ARGS__) -#define vsuxei64_v_u64m8(...) __riscv_vsuxei64_v_u64m8(__VA_ARGS__) -// masked functions -#define vsoxei8_v_f16mf4_m(...) __riscv_vsoxei8_v_f16mf4_m(__VA_ARGS__) -#define vsoxei8_v_f16mf2_m(...) __riscv_vsoxei8_v_f16mf2_m(__VA_ARGS__) -#define vsoxei8_v_f16m1_m(...) __riscv_vsoxei8_v_f16m1_m(__VA_ARGS__) -#define vsoxei8_v_f16m2_m(...) __riscv_vsoxei8_v_f16m2_m(__VA_ARGS__) -#define vsoxei8_v_f16m4_m(...) __riscv_vsoxei8_v_f16m4_m(__VA_ARGS__) -#define vsoxei8_v_f16m8_m(...) __riscv_vsoxei8_v_f16m8_m(__VA_ARGS__) -#define vsoxei16_v_f16mf4_m(...) __riscv_vsoxei16_v_f16mf4_m(__VA_ARGS__) -#define vsoxei16_v_f16mf2_m(...) __riscv_vsoxei16_v_f16mf2_m(__VA_ARGS__) -#define vsoxei16_v_f16m1_m(...) __riscv_vsoxei16_v_f16m1_m(__VA_ARGS__) -#define vsoxei16_v_f16m2_m(...) __riscv_vsoxei16_v_f16m2_m(__VA_ARGS__) -#define vsoxei16_v_f16m4_m(...) __riscv_vsoxei16_v_f16m4_m(__VA_ARGS__) -#define vsoxei16_v_f16m8_m(...) __riscv_vsoxei16_v_f16m8_m(__VA_ARGS__) -#define vsoxei32_v_f16mf4_m(...) __riscv_vsoxei32_v_f16mf4_m(__VA_ARGS__) -#define vsoxei32_v_f16mf2_m(...) __riscv_vsoxei32_v_f16mf2_m(__VA_ARGS__) -#define vsoxei32_v_f16m1_m(...) __riscv_vsoxei32_v_f16m1_m(__VA_ARGS__) -#define vsoxei32_v_f16m2_m(...) __riscv_vsoxei32_v_f16m2_m(__VA_ARGS__) -#define vsoxei32_v_f16m4_m(...) __riscv_vsoxei32_v_f16m4_m(__VA_ARGS__) -#define vsoxei64_v_f16mf4_m(...) __riscv_vsoxei64_v_f16mf4_m(__VA_ARGS__) -#define vsoxei64_v_f16mf2_m(...) __riscv_vsoxei64_v_f16mf2_m(__VA_ARGS__) -#define vsoxei64_v_f16m1_m(...) __riscv_vsoxei64_v_f16m1_m(__VA_ARGS__) -#define vsoxei64_v_f16m2_m(...) __riscv_vsoxei64_v_f16m2_m(__VA_ARGS__) -#define vsoxei8_v_f32mf2_m(...) __riscv_vsoxei8_v_f32mf2_m(__VA_ARGS__) -#define vsoxei8_v_f32m1_m(...) __riscv_vsoxei8_v_f32m1_m(__VA_ARGS__) -#define vsoxei8_v_f32m2_m(...) __riscv_vsoxei8_v_f32m2_m(__VA_ARGS__) -#define vsoxei8_v_f32m4_m(...) __riscv_vsoxei8_v_f32m4_m(__VA_ARGS__) -#define vsoxei8_v_f32m8_m(...) __riscv_vsoxei8_v_f32m8_m(__VA_ARGS__) -#define vsoxei16_v_f32mf2_m(...) __riscv_vsoxei16_v_f32mf2_m(__VA_ARGS__) -#define vsoxei16_v_f32m1_m(...) __riscv_vsoxei16_v_f32m1_m(__VA_ARGS__) -#define vsoxei16_v_f32m2_m(...) __riscv_vsoxei16_v_f32m2_m(__VA_ARGS__) -#define vsoxei16_v_f32m4_m(...) __riscv_vsoxei16_v_f32m4_m(__VA_ARGS__) -#define vsoxei16_v_f32m8_m(...) __riscv_vsoxei16_v_f32m8_m(__VA_ARGS__) -#define vsoxei32_v_f32mf2_m(...) __riscv_vsoxei32_v_f32mf2_m(__VA_ARGS__) -#define vsoxei32_v_f32m1_m(...) __riscv_vsoxei32_v_f32m1_m(__VA_ARGS__) -#define vsoxei32_v_f32m2_m(...) __riscv_vsoxei32_v_f32m2_m(__VA_ARGS__) -#define vsoxei32_v_f32m4_m(...) __riscv_vsoxei32_v_f32m4_m(__VA_ARGS__) -#define vsoxei32_v_f32m8_m(...) __riscv_vsoxei32_v_f32m8_m(__VA_ARGS__) -#define vsoxei64_v_f32mf2_m(...) __riscv_vsoxei64_v_f32mf2_m(__VA_ARGS__) -#define vsoxei64_v_f32m1_m(...) __riscv_vsoxei64_v_f32m1_m(__VA_ARGS__) -#define vsoxei64_v_f32m2_m(...) __riscv_vsoxei64_v_f32m2_m(__VA_ARGS__) -#define vsoxei64_v_f32m4_m(...) __riscv_vsoxei64_v_f32m4_m(__VA_ARGS__) -#define vsoxei8_v_f64m1_m(...) __riscv_vsoxei8_v_f64m1_m(__VA_ARGS__) -#define vsoxei8_v_f64m2_m(...) __riscv_vsoxei8_v_f64m2_m(__VA_ARGS__) -#define vsoxei8_v_f64m4_m(...) __riscv_vsoxei8_v_f64m4_m(__VA_ARGS__) -#define vsoxei8_v_f64m8_m(...) __riscv_vsoxei8_v_f64m8_m(__VA_ARGS__) -#define vsoxei16_v_f64m1_m(...) __riscv_vsoxei16_v_f64m1_m(__VA_ARGS__) -#define vsoxei16_v_f64m2_m(...) __riscv_vsoxei16_v_f64m2_m(__VA_ARGS__) -#define vsoxei16_v_f64m4_m(...) __riscv_vsoxei16_v_f64m4_m(__VA_ARGS__) -#define vsoxei16_v_f64m8_m(...) __riscv_vsoxei16_v_f64m8_m(__VA_ARGS__) -#define vsoxei32_v_f64m1_m(...) __riscv_vsoxei32_v_f64m1_m(__VA_ARGS__) -#define vsoxei32_v_f64m2_m(...) __riscv_vsoxei32_v_f64m2_m(__VA_ARGS__) -#define vsoxei32_v_f64m4_m(...) __riscv_vsoxei32_v_f64m4_m(__VA_ARGS__) -#define vsoxei32_v_f64m8_m(...) __riscv_vsoxei32_v_f64m8_m(__VA_ARGS__) -#define vsoxei64_v_f64m1_m(...) __riscv_vsoxei64_v_f64m1_m(__VA_ARGS__) -#define vsoxei64_v_f64m2_m(...) __riscv_vsoxei64_v_f64m2_m(__VA_ARGS__) -#define vsoxei64_v_f64m4_m(...) __riscv_vsoxei64_v_f64m4_m(__VA_ARGS__) -#define vsoxei64_v_f64m8_m(...) __riscv_vsoxei64_v_f64m8_m(__VA_ARGS__) -#define vsuxei8_v_f16mf4_m(...) __riscv_vsuxei8_v_f16mf4_m(__VA_ARGS__) -#define vsuxei8_v_f16mf2_m(...) __riscv_vsuxei8_v_f16mf2_m(__VA_ARGS__) -#define vsuxei8_v_f16m1_m(...) __riscv_vsuxei8_v_f16m1_m(__VA_ARGS__) -#define vsuxei8_v_f16m2_m(...) __riscv_vsuxei8_v_f16m2_m(__VA_ARGS__) -#define vsuxei8_v_f16m4_m(...) __riscv_vsuxei8_v_f16m4_m(__VA_ARGS__) -#define vsuxei8_v_f16m8_m(...) __riscv_vsuxei8_v_f16m8_m(__VA_ARGS__) -#define vsuxei16_v_f16mf4_m(...) __riscv_vsuxei16_v_f16mf4_m(__VA_ARGS__) -#define vsuxei16_v_f16mf2_m(...) __riscv_vsuxei16_v_f16mf2_m(__VA_ARGS__) -#define vsuxei16_v_f16m1_m(...) __riscv_vsuxei16_v_f16m1_m(__VA_ARGS__) -#define vsuxei16_v_f16m2_m(...) __riscv_vsuxei16_v_f16m2_m(__VA_ARGS__) -#define vsuxei16_v_f16m4_m(...) __riscv_vsuxei16_v_f16m4_m(__VA_ARGS__) -#define vsuxei16_v_f16m8_m(...) __riscv_vsuxei16_v_f16m8_m(__VA_ARGS__) -#define vsuxei32_v_f16mf4_m(...) __riscv_vsuxei32_v_f16mf4_m(__VA_ARGS__) -#define vsuxei32_v_f16mf2_m(...) __riscv_vsuxei32_v_f16mf2_m(__VA_ARGS__) -#define vsuxei32_v_f16m1_m(...) __riscv_vsuxei32_v_f16m1_m(__VA_ARGS__) -#define vsuxei32_v_f16m2_m(...) __riscv_vsuxei32_v_f16m2_m(__VA_ARGS__) -#define vsuxei32_v_f16m4_m(...) __riscv_vsuxei32_v_f16m4_m(__VA_ARGS__) -#define vsuxei64_v_f16mf4_m(...) __riscv_vsuxei64_v_f16mf4_m(__VA_ARGS__) -#define vsuxei64_v_f16mf2_m(...) __riscv_vsuxei64_v_f16mf2_m(__VA_ARGS__) -#define vsuxei64_v_f16m1_m(...) __riscv_vsuxei64_v_f16m1_m(__VA_ARGS__) -#define vsuxei64_v_f16m2_m(...) __riscv_vsuxei64_v_f16m2_m(__VA_ARGS__) -#define vsuxei8_v_f32mf2_m(...) __riscv_vsuxei8_v_f32mf2_m(__VA_ARGS__) -#define vsuxei8_v_f32m1_m(...) __riscv_vsuxei8_v_f32m1_m(__VA_ARGS__) -#define vsuxei8_v_f32m2_m(...) __riscv_vsuxei8_v_f32m2_m(__VA_ARGS__) -#define vsuxei8_v_f32m4_m(...) __riscv_vsuxei8_v_f32m4_m(__VA_ARGS__) -#define vsuxei8_v_f32m8_m(...) __riscv_vsuxei8_v_f32m8_m(__VA_ARGS__) -#define vsuxei16_v_f32mf2_m(...) __riscv_vsuxei16_v_f32mf2_m(__VA_ARGS__) -#define vsuxei16_v_f32m1_m(...) __riscv_vsuxei16_v_f32m1_m(__VA_ARGS__) -#define vsuxei16_v_f32m2_m(...) __riscv_vsuxei16_v_f32m2_m(__VA_ARGS__) -#define vsuxei16_v_f32m4_m(...) __riscv_vsuxei16_v_f32m4_m(__VA_ARGS__) -#define vsuxei16_v_f32m8_m(...) __riscv_vsuxei16_v_f32m8_m(__VA_ARGS__) -#define vsuxei32_v_f32mf2_m(...) __riscv_vsuxei32_v_f32mf2_m(__VA_ARGS__) -#define vsuxei32_v_f32m1_m(...) __riscv_vsuxei32_v_f32m1_m(__VA_ARGS__) -#define vsuxei32_v_f32m2_m(...) __riscv_vsuxei32_v_f32m2_m(__VA_ARGS__) -#define vsuxei32_v_f32m4_m(...) __riscv_vsuxei32_v_f32m4_m(__VA_ARGS__) -#define vsuxei32_v_f32m8_m(...) __riscv_vsuxei32_v_f32m8_m(__VA_ARGS__) -#define vsuxei64_v_f32mf2_m(...) __riscv_vsuxei64_v_f32mf2_m(__VA_ARGS__) -#define vsuxei64_v_f32m1_m(...) __riscv_vsuxei64_v_f32m1_m(__VA_ARGS__) -#define vsuxei64_v_f32m2_m(...) __riscv_vsuxei64_v_f32m2_m(__VA_ARGS__) -#define vsuxei64_v_f32m4_m(...) __riscv_vsuxei64_v_f32m4_m(__VA_ARGS__) -#define vsuxei8_v_f64m1_m(...) __riscv_vsuxei8_v_f64m1_m(__VA_ARGS__) -#define vsuxei8_v_f64m2_m(...) __riscv_vsuxei8_v_f64m2_m(__VA_ARGS__) -#define vsuxei8_v_f64m4_m(...) __riscv_vsuxei8_v_f64m4_m(__VA_ARGS__) -#define vsuxei8_v_f64m8_m(...) __riscv_vsuxei8_v_f64m8_m(__VA_ARGS__) -#define vsuxei16_v_f64m1_m(...) __riscv_vsuxei16_v_f64m1_m(__VA_ARGS__) -#define vsuxei16_v_f64m2_m(...) __riscv_vsuxei16_v_f64m2_m(__VA_ARGS__) -#define vsuxei16_v_f64m4_m(...) __riscv_vsuxei16_v_f64m4_m(__VA_ARGS__) -#define vsuxei16_v_f64m8_m(...) __riscv_vsuxei16_v_f64m8_m(__VA_ARGS__) -#define vsuxei32_v_f64m1_m(...) __riscv_vsuxei32_v_f64m1_m(__VA_ARGS__) -#define vsuxei32_v_f64m2_m(...) __riscv_vsuxei32_v_f64m2_m(__VA_ARGS__) -#define vsuxei32_v_f64m4_m(...) __riscv_vsuxei32_v_f64m4_m(__VA_ARGS__) -#define vsuxei32_v_f64m8_m(...) __riscv_vsuxei32_v_f64m8_m(__VA_ARGS__) -#define vsuxei64_v_f64m1_m(...) __riscv_vsuxei64_v_f64m1_m(__VA_ARGS__) -#define vsuxei64_v_f64m2_m(...) __riscv_vsuxei64_v_f64m2_m(__VA_ARGS__) -#define vsuxei64_v_f64m4_m(...) __riscv_vsuxei64_v_f64m4_m(__VA_ARGS__) -#define vsuxei64_v_f64m8_m(...) __riscv_vsuxei64_v_f64m8_m(__VA_ARGS__) -#define vsoxei8_v_i8mf8_m(...) __riscv_vsoxei8_v_i8mf8_m(__VA_ARGS__) -#define vsoxei8_v_i8mf4_m(...) __riscv_vsoxei8_v_i8mf4_m(__VA_ARGS__) -#define vsoxei8_v_i8mf2_m(...) __riscv_vsoxei8_v_i8mf2_m(__VA_ARGS__) -#define vsoxei8_v_i8m1_m(...) __riscv_vsoxei8_v_i8m1_m(__VA_ARGS__) -#define vsoxei8_v_i8m2_m(...) __riscv_vsoxei8_v_i8m2_m(__VA_ARGS__) -#define vsoxei8_v_i8m4_m(...) __riscv_vsoxei8_v_i8m4_m(__VA_ARGS__) -#define vsoxei8_v_i8m8_m(...) __riscv_vsoxei8_v_i8m8_m(__VA_ARGS__) -#define vsoxei16_v_i8mf8_m(...) __riscv_vsoxei16_v_i8mf8_m(__VA_ARGS__) -#define vsoxei16_v_i8mf4_m(...) __riscv_vsoxei16_v_i8mf4_m(__VA_ARGS__) -#define vsoxei16_v_i8mf2_m(...) __riscv_vsoxei16_v_i8mf2_m(__VA_ARGS__) -#define vsoxei16_v_i8m1_m(...) __riscv_vsoxei16_v_i8m1_m(__VA_ARGS__) -#define vsoxei16_v_i8m2_m(...) __riscv_vsoxei16_v_i8m2_m(__VA_ARGS__) -#define vsoxei16_v_i8m4_m(...) __riscv_vsoxei16_v_i8m4_m(__VA_ARGS__) -#define vsoxei32_v_i8mf8_m(...) __riscv_vsoxei32_v_i8mf8_m(__VA_ARGS__) -#define vsoxei32_v_i8mf4_m(...) __riscv_vsoxei32_v_i8mf4_m(__VA_ARGS__) -#define vsoxei32_v_i8mf2_m(...) __riscv_vsoxei32_v_i8mf2_m(__VA_ARGS__) -#define vsoxei32_v_i8m1_m(...) __riscv_vsoxei32_v_i8m1_m(__VA_ARGS__) -#define vsoxei32_v_i8m2_m(...) __riscv_vsoxei32_v_i8m2_m(__VA_ARGS__) -#define vsoxei64_v_i8mf8_m(...) __riscv_vsoxei64_v_i8mf8_m(__VA_ARGS__) -#define vsoxei64_v_i8mf4_m(...) __riscv_vsoxei64_v_i8mf4_m(__VA_ARGS__) -#define vsoxei64_v_i8mf2_m(...) __riscv_vsoxei64_v_i8mf2_m(__VA_ARGS__) -#define vsoxei64_v_i8m1_m(...) __riscv_vsoxei64_v_i8m1_m(__VA_ARGS__) -#define vsoxei8_v_i16mf4_m(...) __riscv_vsoxei8_v_i16mf4_m(__VA_ARGS__) -#define vsoxei8_v_i16mf2_m(...) __riscv_vsoxei8_v_i16mf2_m(__VA_ARGS__) -#define vsoxei8_v_i16m1_m(...) __riscv_vsoxei8_v_i16m1_m(__VA_ARGS__) -#define vsoxei8_v_i16m2_m(...) __riscv_vsoxei8_v_i16m2_m(__VA_ARGS__) -#define vsoxei8_v_i16m4_m(...) __riscv_vsoxei8_v_i16m4_m(__VA_ARGS__) -#define vsoxei8_v_i16m8_m(...) __riscv_vsoxei8_v_i16m8_m(__VA_ARGS__) -#define vsoxei16_v_i16mf4_m(...) __riscv_vsoxei16_v_i16mf4_m(__VA_ARGS__) -#define vsoxei16_v_i16mf2_m(...) __riscv_vsoxei16_v_i16mf2_m(__VA_ARGS__) -#define vsoxei16_v_i16m1_m(...) __riscv_vsoxei16_v_i16m1_m(__VA_ARGS__) -#define vsoxei16_v_i16m2_m(...) __riscv_vsoxei16_v_i16m2_m(__VA_ARGS__) -#define vsoxei16_v_i16m4_m(...) __riscv_vsoxei16_v_i16m4_m(__VA_ARGS__) -#define vsoxei16_v_i16m8_m(...) __riscv_vsoxei16_v_i16m8_m(__VA_ARGS__) -#define vsoxei32_v_i16mf4_m(...) __riscv_vsoxei32_v_i16mf4_m(__VA_ARGS__) -#define vsoxei32_v_i16mf2_m(...) __riscv_vsoxei32_v_i16mf2_m(__VA_ARGS__) -#define vsoxei32_v_i16m1_m(...) __riscv_vsoxei32_v_i16m1_m(__VA_ARGS__) -#define vsoxei32_v_i16m2_m(...) __riscv_vsoxei32_v_i16m2_m(__VA_ARGS__) -#define vsoxei32_v_i16m4_m(...) __riscv_vsoxei32_v_i16m4_m(__VA_ARGS__) -#define vsoxei64_v_i16mf4_m(...) __riscv_vsoxei64_v_i16mf4_m(__VA_ARGS__) -#define vsoxei64_v_i16mf2_m(...) __riscv_vsoxei64_v_i16mf2_m(__VA_ARGS__) -#define vsoxei64_v_i16m1_m(...) __riscv_vsoxei64_v_i16m1_m(__VA_ARGS__) -#define vsoxei64_v_i16m2_m(...) __riscv_vsoxei64_v_i16m2_m(__VA_ARGS__) -#define vsoxei8_v_i32mf2_m(...) __riscv_vsoxei8_v_i32mf2_m(__VA_ARGS__) -#define vsoxei8_v_i32m1_m(...) __riscv_vsoxei8_v_i32m1_m(__VA_ARGS__) -#define vsoxei8_v_i32m2_m(...) __riscv_vsoxei8_v_i32m2_m(__VA_ARGS__) -#define vsoxei8_v_i32m4_m(...) __riscv_vsoxei8_v_i32m4_m(__VA_ARGS__) -#define vsoxei8_v_i32m8_m(...) __riscv_vsoxei8_v_i32m8_m(__VA_ARGS__) -#define vsoxei16_v_i32mf2_m(...) __riscv_vsoxei16_v_i32mf2_m(__VA_ARGS__) -#define vsoxei16_v_i32m1_m(...) __riscv_vsoxei16_v_i32m1_m(__VA_ARGS__) -#define vsoxei16_v_i32m2_m(...) __riscv_vsoxei16_v_i32m2_m(__VA_ARGS__) -#define vsoxei16_v_i32m4_m(...) __riscv_vsoxei16_v_i32m4_m(__VA_ARGS__) -#define vsoxei16_v_i32m8_m(...) __riscv_vsoxei16_v_i32m8_m(__VA_ARGS__) -#define vsoxei32_v_i32mf2_m(...) __riscv_vsoxei32_v_i32mf2_m(__VA_ARGS__) -#define vsoxei32_v_i32m1_m(...) __riscv_vsoxei32_v_i32m1_m(__VA_ARGS__) -#define vsoxei32_v_i32m2_m(...) __riscv_vsoxei32_v_i32m2_m(__VA_ARGS__) -#define vsoxei32_v_i32m4_m(...) __riscv_vsoxei32_v_i32m4_m(__VA_ARGS__) -#define vsoxei32_v_i32m8_m(...) __riscv_vsoxei32_v_i32m8_m(__VA_ARGS__) -#define vsoxei64_v_i32mf2_m(...) __riscv_vsoxei64_v_i32mf2_m(__VA_ARGS__) -#define vsoxei64_v_i32m1_m(...) __riscv_vsoxei64_v_i32m1_m(__VA_ARGS__) -#define vsoxei64_v_i32m2_m(...) __riscv_vsoxei64_v_i32m2_m(__VA_ARGS__) -#define vsoxei64_v_i32m4_m(...) __riscv_vsoxei64_v_i32m4_m(__VA_ARGS__) -#define vsoxei8_v_i64m1_m(...) __riscv_vsoxei8_v_i64m1_m(__VA_ARGS__) -#define vsoxei8_v_i64m2_m(...) __riscv_vsoxei8_v_i64m2_m(__VA_ARGS__) -#define vsoxei8_v_i64m4_m(...) __riscv_vsoxei8_v_i64m4_m(__VA_ARGS__) -#define vsoxei8_v_i64m8_m(...) __riscv_vsoxei8_v_i64m8_m(__VA_ARGS__) -#define vsoxei16_v_i64m1_m(...) __riscv_vsoxei16_v_i64m1_m(__VA_ARGS__) -#define vsoxei16_v_i64m2_m(...) __riscv_vsoxei16_v_i64m2_m(__VA_ARGS__) -#define vsoxei16_v_i64m4_m(...) __riscv_vsoxei16_v_i64m4_m(__VA_ARGS__) -#define vsoxei16_v_i64m8_m(...) __riscv_vsoxei16_v_i64m8_m(__VA_ARGS__) -#define vsoxei32_v_i64m1_m(...) __riscv_vsoxei32_v_i64m1_m(__VA_ARGS__) -#define vsoxei32_v_i64m2_m(...) __riscv_vsoxei32_v_i64m2_m(__VA_ARGS__) -#define vsoxei32_v_i64m4_m(...) __riscv_vsoxei32_v_i64m4_m(__VA_ARGS__) -#define vsoxei32_v_i64m8_m(...) __riscv_vsoxei32_v_i64m8_m(__VA_ARGS__) -#define vsoxei64_v_i64m1_m(...) __riscv_vsoxei64_v_i64m1_m(__VA_ARGS__) -#define vsoxei64_v_i64m2_m(...) __riscv_vsoxei64_v_i64m2_m(__VA_ARGS__) -#define vsoxei64_v_i64m4_m(...) __riscv_vsoxei64_v_i64m4_m(__VA_ARGS__) -#define vsoxei64_v_i64m8_m(...) __riscv_vsoxei64_v_i64m8_m(__VA_ARGS__) -#define vsuxei8_v_i8mf8_m(...) __riscv_vsuxei8_v_i8mf8_m(__VA_ARGS__) -#define vsuxei8_v_i8mf4_m(...) __riscv_vsuxei8_v_i8mf4_m(__VA_ARGS__) -#define vsuxei8_v_i8mf2_m(...) __riscv_vsuxei8_v_i8mf2_m(__VA_ARGS__) -#define vsuxei8_v_i8m1_m(...) __riscv_vsuxei8_v_i8m1_m(__VA_ARGS__) -#define vsuxei8_v_i8m2_m(...) __riscv_vsuxei8_v_i8m2_m(__VA_ARGS__) -#define vsuxei8_v_i8m4_m(...) __riscv_vsuxei8_v_i8m4_m(__VA_ARGS__) -#define vsuxei8_v_i8m8_m(...) __riscv_vsuxei8_v_i8m8_m(__VA_ARGS__) -#define vsuxei16_v_i8mf8_m(...) __riscv_vsuxei16_v_i8mf8_m(__VA_ARGS__) -#define vsuxei16_v_i8mf4_m(...) __riscv_vsuxei16_v_i8mf4_m(__VA_ARGS__) -#define vsuxei16_v_i8mf2_m(...) __riscv_vsuxei16_v_i8mf2_m(__VA_ARGS__) -#define vsuxei16_v_i8m1_m(...) __riscv_vsuxei16_v_i8m1_m(__VA_ARGS__) -#define vsuxei16_v_i8m2_m(...) __riscv_vsuxei16_v_i8m2_m(__VA_ARGS__) -#define vsuxei16_v_i8m4_m(...) __riscv_vsuxei16_v_i8m4_m(__VA_ARGS__) -#define vsuxei32_v_i8mf8_m(...) __riscv_vsuxei32_v_i8mf8_m(__VA_ARGS__) -#define vsuxei32_v_i8mf4_m(...) __riscv_vsuxei32_v_i8mf4_m(__VA_ARGS__) -#define vsuxei32_v_i8mf2_m(...) __riscv_vsuxei32_v_i8mf2_m(__VA_ARGS__) -#define vsuxei32_v_i8m1_m(...) __riscv_vsuxei32_v_i8m1_m(__VA_ARGS__) -#define vsuxei32_v_i8m2_m(...) __riscv_vsuxei32_v_i8m2_m(__VA_ARGS__) -#define vsuxei64_v_i8mf8_m(...) __riscv_vsuxei64_v_i8mf8_m(__VA_ARGS__) -#define vsuxei64_v_i8mf4_m(...) __riscv_vsuxei64_v_i8mf4_m(__VA_ARGS__) -#define vsuxei64_v_i8mf2_m(...) __riscv_vsuxei64_v_i8mf2_m(__VA_ARGS__) -#define vsuxei64_v_i8m1_m(...) __riscv_vsuxei64_v_i8m1_m(__VA_ARGS__) -#define vsuxei8_v_i16mf4_m(...) __riscv_vsuxei8_v_i16mf4_m(__VA_ARGS__) -#define vsuxei8_v_i16mf2_m(...) __riscv_vsuxei8_v_i16mf2_m(__VA_ARGS__) -#define vsuxei8_v_i16m1_m(...) __riscv_vsuxei8_v_i16m1_m(__VA_ARGS__) -#define vsuxei8_v_i16m2_m(...) __riscv_vsuxei8_v_i16m2_m(__VA_ARGS__) -#define vsuxei8_v_i16m4_m(...) __riscv_vsuxei8_v_i16m4_m(__VA_ARGS__) -#define vsuxei8_v_i16m8_m(...) __riscv_vsuxei8_v_i16m8_m(__VA_ARGS__) -#define vsuxei16_v_i16mf4_m(...) __riscv_vsuxei16_v_i16mf4_m(__VA_ARGS__) -#define vsuxei16_v_i16mf2_m(...) __riscv_vsuxei16_v_i16mf2_m(__VA_ARGS__) -#define vsuxei16_v_i16m1_m(...) __riscv_vsuxei16_v_i16m1_m(__VA_ARGS__) -#define vsuxei16_v_i16m2_m(...) __riscv_vsuxei16_v_i16m2_m(__VA_ARGS__) -#define vsuxei16_v_i16m4_m(...) __riscv_vsuxei16_v_i16m4_m(__VA_ARGS__) -#define vsuxei16_v_i16m8_m(...) __riscv_vsuxei16_v_i16m8_m(__VA_ARGS__) -#define vsuxei32_v_i16mf4_m(...) __riscv_vsuxei32_v_i16mf4_m(__VA_ARGS__) -#define vsuxei32_v_i16mf2_m(...) __riscv_vsuxei32_v_i16mf2_m(__VA_ARGS__) -#define vsuxei32_v_i16m1_m(...) __riscv_vsuxei32_v_i16m1_m(__VA_ARGS__) -#define vsuxei32_v_i16m2_m(...) __riscv_vsuxei32_v_i16m2_m(__VA_ARGS__) -#define vsuxei32_v_i16m4_m(...) __riscv_vsuxei32_v_i16m4_m(__VA_ARGS__) -#define vsuxei64_v_i16mf4_m(...) __riscv_vsuxei64_v_i16mf4_m(__VA_ARGS__) -#define vsuxei64_v_i16mf2_m(...) __riscv_vsuxei64_v_i16mf2_m(__VA_ARGS__) -#define vsuxei64_v_i16m1_m(...) __riscv_vsuxei64_v_i16m1_m(__VA_ARGS__) -#define vsuxei64_v_i16m2_m(...) __riscv_vsuxei64_v_i16m2_m(__VA_ARGS__) -#define vsuxei8_v_i32mf2_m(...) __riscv_vsuxei8_v_i32mf2_m(__VA_ARGS__) -#define vsuxei8_v_i32m1_m(...) __riscv_vsuxei8_v_i32m1_m(__VA_ARGS__) -#define vsuxei8_v_i32m2_m(...) __riscv_vsuxei8_v_i32m2_m(__VA_ARGS__) -#define vsuxei8_v_i32m4_m(...) __riscv_vsuxei8_v_i32m4_m(__VA_ARGS__) -#define vsuxei8_v_i32m8_m(...) __riscv_vsuxei8_v_i32m8_m(__VA_ARGS__) -#define vsuxei16_v_i32mf2_m(...) __riscv_vsuxei16_v_i32mf2_m(__VA_ARGS__) -#define vsuxei16_v_i32m1_m(...) __riscv_vsuxei16_v_i32m1_m(__VA_ARGS__) -#define vsuxei16_v_i32m2_m(...) __riscv_vsuxei16_v_i32m2_m(__VA_ARGS__) -#define vsuxei16_v_i32m4_m(...) __riscv_vsuxei16_v_i32m4_m(__VA_ARGS__) -#define vsuxei16_v_i32m8_m(...) __riscv_vsuxei16_v_i32m8_m(__VA_ARGS__) -#define vsuxei32_v_i32mf2_m(...) __riscv_vsuxei32_v_i32mf2_m(__VA_ARGS__) -#define vsuxei32_v_i32m1_m(...) __riscv_vsuxei32_v_i32m1_m(__VA_ARGS__) -#define vsuxei32_v_i32m2_m(...) __riscv_vsuxei32_v_i32m2_m(__VA_ARGS__) -#define vsuxei32_v_i32m4_m(...) __riscv_vsuxei32_v_i32m4_m(__VA_ARGS__) -#define vsuxei32_v_i32m8_m(...) __riscv_vsuxei32_v_i32m8_m(__VA_ARGS__) -#define vsuxei64_v_i32mf2_m(...) __riscv_vsuxei64_v_i32mf2_m(__VA_ARGS__) -#define vsuxei64_v_i32m1_m(...) __riscv_vsuxei64_v_i32m1_m(__VA_ARGS__) -#define vsuxei64_v_i32m2_m(...) __riscv_vsuxei64_v_i32m2_m(__VA_ARGS__) -#define vsuxei64_v_i32m4_m(...) __riscv_vsuxei64_v_i32m4_m(__VA_ARGS__) -#define vsuxei8_v_i64m1_m(...) __riscv_vsuxei8_v_i64m1_m(__VA_ARGS__) -#define vsuxei8_v_i64m2_m(...) __riscv_vsuxei8_v_i64m2_m(__VA_ARGS__) -#define vsuxei8_v_i64m4_m(...) __riscv_vsuxei8_v_i64m4_m(__VA_ARGS__) -#define vsuxei8_v_i64m8_m(...) __riscv_vsuxei8_v_i64m8_m(__VA_ARGS__) -#define vsuxei16_v_i64m1_m(...) __riscv_vsuxei16_v_i64m1_m(__VA_ARGS__) -#define vsuxei16_v_i64m2_m(...) __riscv_vsuxei16_v_i64m2_m(__VA_ARGS__) -#define vsuxei16_v_i64m4_m(...) __riscv_vsuxei16_v_i64m4_m(__VA_ARGS__) -#define vsuxei16_v_i64m8_m(...) __riscv_vsuxei16_v_i64m8_m(__VA_ARGS__) -#define vsuxei32_v_i64m1_m(...) __riscv_vsuxei32_v_i64m1_m(__VA_ARGS__) -#define vsuxei32_v_i64m2_m(...) __riscv_vsuxei32_v_i64m2_m(__VA_ARGS__) -#define vsuxei32_v_i64m4_m(...) __riscv_vsuxei32_v_i64m4_m(__VA_ARGS__) -#define vsuxei32_v_i64m8_m(...) __riscv_vsuxei32_v_i64m8_m(__VA_ARGS__) -#define vsuxei64_v_i64m1_m(...) __riscv_vsuxei64_v_i64m1_m(__VA_ARGS__) -#define vsuxei64_v_i64m2_m(...) __riscv_vsuxei64_v_i64m2_m(__VA_ARGS__) -#define vsuxei64_v_i64m4_m(...) __riscv_vsuxei64_v_i64m4_m(__VA_ARGS__) -#define vsuxei64_v_i64m8_m(...) __riscv_vsuxei64_v_i64m8_m(__VA_ARGS__) -#define vsoxei8_v_u8mf8_m(...) __riscv_vsoxei8_v_u8mf8_m(__VA_ARGS__) -#define vsoxei8_v_u8mf4_m(...) __riscv_vsoxei8_v_u8mf4_m(__VA_ARGS__) -#define vsoxei8_v_u8mf2_m(...) __riscv_vsoxei8_v_u8mf2_m(__VA_ARGS__) -#define vsoxei8_v_u8m1_m(...) __riscv_vsoxei8_v_u8m1_m(__VA_ARGS__) -#define vsoxei8_v_u8m2_m(...) __riscv_vsoxei8_v_u8m2_m(__VA_ARGS__) -#define vsoxei8_v_u8m4_m(...) __riscv_vsoxei8_v_u8m4_m(__VA_ARGS__) -#define vsoxei8_v_u8m8_m(...) __riscv_vsoxei8_v_u8m8_m(__VA_ARGS__) -#define vsoxei16_v_u8mf8_m(...) __riscv_vsoxei16_v_u8mf8_m(__VA_ARGS__) -#define vsoxei16_v_u8mf4_m(...) __riscv_vsoxei16_v_u8mf4_m(__VA_ARGS__) -#define vsoxei16_v_u8mf2_m(...) __riscv_vsoxei16_v_u8mf2_m(__VA_ARGS__) -#define vsoxei16_v_u8m1_m(...) __riscv_vsoxei16_v_u8m1_m(__VA_ARGS__) -#define vsoxei16_v_u8m2_m(...) __riscv_vsoxei16_v_u8m2_m(__VA_ARGS__) -#define vsoxei16_v_u8m4_m(...) __riscv_vsoxei16_v_u8m4_m(__VA_ARGS__) -#define vsoxei32_v_u8mf8_m(...) __riscv_vsoxei32_v_u8mf8_m(__VA_ARGS__) -#define vsoxei32_v_u8mf4_m(...) __riscv_vsoxei32_v_u8mf4_m(__VA_ARGS__) -#define vsoxei32_v_u8mf2_m(...) __riscv_vsoxei32_v_u8mf2_m(__VA_ARGS__) -#define vsoxei32_v_u8m1_m(...) __riscv_vsoxei32_v_u8m1_m(__VA_ARGS__) -#define vsoxei32_v_u8m2_m(...) __riscv_vsoxei32_v_u8m2_m(__VA_ARGS__) -#define vsoxei64_v_u8mf8_m(...) __riscv_vsoxei64_v_u8mf8_m(__VA_ARGS__) -#define vsoxei64_v_u8mf4_m(...) __riscv_vsoxei64_v_u8mf4_m(__VA_ARGS__) -#define vsoxei64_v_u8mf2_m(...) __riscv_vsoxei64_v_u8mf2_m(__VA_ARGS__) -#define vsoxei64_v_u8m1_m(...) __riscv_vsoxei64_v_u8m1_m(__VA_ARGS__) -#define vsoxei8_v_u16mf4_m(...) __riscv_vsoxei8_v_u16mf4_m(__VA_ARGS__) -#define vsoxei8_v_u16mf2_m(...) __riscv_vsoxei8_v_u16mf2_m(__VA_ARGS__) -#define vsoxei8_v_u16m1_m(...) __riscv_vsoxei8_v_u16m1_m(__VA_ARGS__) -#define vsoxei8_v_u16m2_m(...) __riscv_vsoxei8_v_u16m2_m(__VA_ARGS__) -#define vsoxei8_v_u16m4_m(...) __riscv_vsoxei8_v_u16m4_m(__VA_ARGS__) -#define vsoxei8_v_u16m8_m(...) __riscv_vsoxei8_v_u16m8_m(__VA_ARGS__) -#define vsoxei16_v_u16mf4_m(...) __riscv_vsoxei16_v_u16mf4_m(__VA_ARGS__) -#define vsoxei16_v_u16mf2_m(...) __riscv_vsoxei16_v_u16mf2_m(__VA_ARGS__) -#define vsoxei16_v_u16m1_m(...) __riscv_vsoxei16_v_u16m1_m(__VA_ARGS__) -#define vsoxei16_v_u16m2_m(...) __riscv_vsoxei16_v_u16m2_m(__VA_ARGS__) -#define vsoxei16_v_u16m4_m(...) __riscv_vsoxei16_v_u16m4_m(__VA_ARGS__) -#define vsoxei16_v_u16m8_m(...) __riscv_vsoxei16_v_u16m8_m(__VA_ARGS__) -#define vsoxei32_v_u16mf4_m(...) __riscv_vsoxei32_v_u16mf4_m(__VA_ARGS__) -#define vsoxei32_v_u16mf2_m(...) __riscv_vsoxei32_v_u16mf2_m(__VA_ARGS__) -#define vsoxei32_v_u16m1_m(...) __riscv_vsoxei32_v_u16m1_m(__VA_ARGS__) -#define vsoxei32_v_u16m2_m(...) __riscv_vsoxei32_v_u16m2_m(__VA_ARGS__) -#define vsoxei32_v_u16m4_m(...) __riscv_vsoxei32_v_u16m4_m(__VA_ARGS__) -#define vsoxei64_v_u16mf4_m(...) __riscv_vsoxei64_v_u16mf4_m(__VA_ARGS__) -#define vsoxei64_v_u16mf2_m(...) __riscv_vsoxei64_v_u16mf2_m(__VA_ARGS__) -#define vsoxei64_v_u16m1_m(...) __riscv_vsoxei64_v_u16m1_m(__VA_ARGS__) -#define vsoxei64_v_u16m2_m(...) __riscv_vsoxei64_v_u16m2_m(__VA_ARGS__) -#define vsoxei8_v_u32mf2_m(...) __riscv_vsoxei8_v_u32mf2_m(__VA_ARGS__) -#define vsoxei8_v_u32m1_m(...) __riscv_vsoxei8_v_u32m1_m(__VA_ARGS__) -#define vsoxei8_v_u32m2_m(...) __riscv_vsoxei8_v_u32m2_m(__VA_ARGS__) -#define vsoxei8_v_u32m4_m(...) __riscv_vsoxei8_v_u32m4_m(__VA_ARGS__) -#define vsoxei8_v_u32m8_m(...) __riscv_vsoxei8_v_u32m8_m(__VA_ARGS__) -#define vsoxei16_v_u32mf2_m(...) __riscv_vsoxei16_v_u32mf2_m(__VA_ARGS__) -#define vsoxei16_v_u32m1_m(...) __riscv_vsoxei16_v_u32m1_m(__VA_ARGS__) -#define vsoxei16_v_u32m2_m(...) __riscv_vsoxei16_v_u32m2_m(__VA_ARGS__) -#define vsoxei16_v_u32m4_m(...) __riscv_vsoxei16_v_u32m4_m(__VA_ARGS__) -#define vsoxei16_v_u32m8_m(...) __riscv_vsoxei16_v_u32m8_m(__VA_ARGS__) -#define vsoxei32_v_u32mf2_m(...) __riscv_vsoxei32_v_u32mf2_m(__VA_ARGS__) -#define vsoxei32_v_u32m1_m(...) __riscv_vsoxei32_v_u32m1_m(__VA_ARGS__) -#define vsoxei32_v_u32m2_m(...) __riscv_vsoxei32_v_u32m2_m(__VA_ARGS__) -#define vsoxei32_v_u32m4_m(...) __riscv_vsoxei32_v_u32m4_m(__VA_ARGS__) -#define vsoxei32_v_u32m8_m(...) __riscv_vsoxei32_v_u32m8_m(__VA_ARGS__) -#define vsoxei64_v_u32mf2_m(...) __riscv_vsoxei64_v_u32mf2_m(__VA_ARGS__) -#define vsoxei64_v_u32m1_m(...) __riscv_vsoxei64_v_u32m1_m(__VA_ARGS__) -#define vsoxei64_v_u32m2_m(...) __riscv_vsoxei64_v_u32m2_m(__VA_ARGS__) -#define vsoxei64_v_u32m4_m(...) __riscv_vsoxei64_v_u32m4_m(__VA_ARGS__) -#define vsoxei8_v_u64m1_m(...) __riscv_vsoxei8_v_u64m1_m(__VA_ARGS__) -#define vsoxei8_v_u64m2_m(...) __riscv_vsoxei8_v_u64m2_m(__VA_ARGS__) -#define vsoxei8_v_u64m4_m(...) __riscv_vsoxei8_v_u64m4_m(__VA_ARGS__) -#define vsoxei8_v_u64m8_m(...) __riscv_vsoxei8_v_u64m8_m(__VA_ARGS__) -#define vsoxei16_v_u64m1_m(...) __riscv_vsoxei16_v_u64m1_m(__VA_ARGS__) -#define vsoxei16_v_u64m2_m(...) __riscv_vsoxei16_v_u64m2_m(__VA_ARGS__) -#define vsoxei16_v_u64m4_m(...) __riscv_vsoxei16_v_u64m4_m(__VA_ARGS__) -#define vsoxei16_v_u64m8_m(...) __riscv_vsoxei16_v_u64m8_m(__VA_ARGS__) -#define vsoxei32_v_u64m1_m(...) __riscv_vsoxei32_v_u64m1_m(__VA_ARGS__) -#define vsoxei32_v_u64m2_m(...) __riscv_vsoxei32_v_u64m2_m(__VA_ARGS__) -#define vsoxei32_v_u64m4_m(...) __riscv_vsoxei32_v_u64m4_m(__VA_ARGS__) -#define vsoxei32_v_u64m8_m(...) __riscv_vsoxei32_v_u64m8_m(__VA_ARGS__) -#define vsoxei64_v_u64m1_m(...) __riscv_vsoxei64_v_u64m1_m(__VA_ARGS__) -#define vsoxei64_v_u64m2_m(...) __riscv_vsoxei64_v_u64m2_m(__VA_ARGS__) -#define vsoxei64_v_u64m4_m(...) __riscv_vsoxei64_v_u64m4_m(__VA_ARGS__) -#define vsoxei64_v_u64m8_m(...) __riscv_vsoxei64_v_u64m8_m(__VA_ARGS__) -#define vsuxei8_v_u8mf8_m(...) __riscv_vsuxei8_v_u8mf8_m(__VA_ARGS__) -#define vsuxei8_v_u8mf4_m(...) __riscv_vsuxei8_v_u8mf4_m(__VA_ARGS__) -#define vsuxei8_v_u8mf2_m(...) __riscv_vsuxei8_v_u8mf2_m(__VA_ARGS__) -#define vsuxei8_v_u8m1_m(...) __riscv_vsuxei8_v_u8m1_m(__VA_ARGS__) -#define vsuxei8_v_u8m2_m(...) __riscv_vsuxei8_v_u8m2_m(__VA_ARGS__) -#define vsuxei8_v_u8m4_m(...) __riscv_vsuxei8_v_u8m4_m(__VA_ARGS__) -#define vsuxei8_v_u8m8_m(...) __riscv_vsuxei8_v_u8m8_m(__VA_ARGS__) -#define vsuxei16_v_u8mf8_m(...) __riscv_vsuxei16_v_u8mf8_m(__VA_ARGS__) -#define vsuxei16_v_u8mf4_m(...) __riscv_vsuxei16_v_u8mf4_m(__VA_ARGS__) -#define vsuxei16_v_u8mf2_m(...) __riscv_vsuxei16_v_u8mf2_m(__VA_ARGS__) -#define vsuxei16_v_u8m1_m(...) __riscv_vsuxei16_v_u8m1_m(__VA_ARGS__) -#define vsuxei16_v_u8m2_m(...) __riscv_vsuxei16_v_u8m2_m(__VA_ARGS__) -#define vsuxei16_v_u8m4_m(...) __riscv_vsuxei16_v_u8m4_m(__VA_ARGS__) -#define vsuxei32_v_u8mf8_m(...) __riscv_vsuxei32_v_u8mf8_m(__VA_ARGS__) -#define vsuxei32_v_u8mf4_m(...) __riscv_vsuxei32_v_u8mf4_m(__VA_ARGS__) -#define vsuxei32_v_u8mf2_m(...) __riscv_vsuxei32_v_u8mf2_m(__VA_ARGS__) -#define vsuxei32_v_u8m1_m(...) __riscv_vsuxei32_v_u8m1_m(__VA_ARGS__) -#define vsuxei32_v_u8m2_m(...) __riscv_vsuxei32_v_u8m2_m(__VA_ARGS__) -#define vsuxei64_v_u8mf8_m(...) __riscv_vsuxei64_v_u8mf8_m(__VA_ARGS__) -#define vsuxei64_v_u8mf4_m(...) __riscv_vsuxei64_v_u8mf4_m(__VA_ARGS__) -#define vsuxei64_v_u8mf2_m(...) __riscv_vsuxei64_v_u8mf2_m(__VA_ARGS__) -#define vsuxei64_v_u8m1_m(...) __riscv_vsuxei64_v_u8m1_m(__VA_ARGS__) -#define vsuxei8_v_u16mf4_m(...) __riscv_vsuxei8_v_u16mf4_m(__VA_ARGS__) -#define vsuxei8_v_u16mf2_m(...) __riscv_vsuxei8_v_u16mf2_m(__VA_ARGS__) -#define vsuxei8_v_u16m1_m(...) __riscv_vsuxei8_v_u16m1_m(__VA_ARGS__) -#define vsuxei8_v_u16m2_m(...) __riscv_vsuxei8_v_u16m2_m(__VA_ARGS__) -#define vsuxei8_v_u16m4_m(...) __riscv_vsuxei8_v_u16m4_m(__VA_ARGS__) -#define vsuxei8_v_u16m8_m(...) __riscv_vsuxei8_v_u16m8_m(__VA_ARGS__) -#define vsuxei16_v_u16mf4_m(...) __riscv_vsuxei16_v_u16mf4_m(__VA_ARGS__) -#define vsuxei16_v_u16mf2_m(...) __riscv_vsuxei16_v_u16mf2_m(__VA_ARGS__) -#define vsuxei16_v_u16m1_m(...) __riscv_vsuxei16_v_u16m1_m(__VA_ARGS__) -#define vsuxei16_v_u16m2_m(...) __riscv_vsuxei16_v_u16m2_m(__VA_ARGS__) -#define vsuxei16_v_u16m4_m(...) __riscv_vsuxei16_v_u16m4_m(__VA_ARGS__) -#define vsuxei16_v_u16m8_m(...) __riscv_vsuxei16_v_u16m8_m(__VA_ARGS__) -#define vsuxei32_v_u16mf4_m(...) __riscv_vsuxei32_v_u16mf4_m(__VA_ARGS__) -#define vsuxei32_v_u16mf2_m(...) __riscv_vsuxei32_v_u16mf2_m(__VA_ARGS__) -#define vsuxei32_v_u16m1_m(...) __riscv_vsuxei32_v_u16m1_m(__VA_ARGS__) -#define vsuxei32_v_u16m2_m(...) __riscv_vsuxei32_v_u16m2_m(__VA_ARGS__) -#define vsuxei32_v_u16m4_m(...) __riscv_vsuxei32_v_u16m4_m(__VA_ARGS__) -#define vsuxei64_v_u16mf4_m(...) __riscv_vsuxei64_v_u16mf4_m(__VA_ARGS__) -#define vsuxei64_v_u16mf2_m(...) __riscv_vsuxei64_v_u16mf2_m(__VA_ARGS__) -#define vsuxei64_v_u16m1_m(...) __riscv_vsuxei64_v_u16m1_m(__VA_ARGS__) -#define vsuxei64_v_u16m2_m(...) __riscv_vsuxei64_v_u16m2_m(__VA_ARGS__) -#define vsuxei8_v_u32mf2_m(...) __riscv_vsuxei8_v_u32mf2_m(__VA_ARGS__) -#define vsuxei8_v_u32m1_m(...) __riscv_vsuxei8_v_u32m1_m(__VA_ARGS__) -#define vsuxei8_v_u32m2_m(...) __riscv_vsuxei8_v_u32m2_m(__VA_ARGS__) -#define vsuxei8_v_u32m4_m(...) __riscv_vsuxei8_v_u32m4_m(__VA_ARGS__) -#define vsuxei8_v_u32m8_m(...) __riscv_vsuxei8_v_u32m8_m(__VA_ARGS__) -#define vsuxei16_v_u32mf2_m(...) __riscv_vsuxei16_v_u32mf2_m(__VA_ARGS__) -#define vsuxei16_v_u32m1_m(...) __riscv_vsuxei16_v_u32m1_m(__VA_ARGS__) -#define vsuxei16_v_u32m2_m(...) __riscv_vsuxei16_v_u32m2_m(__VA_ARGS__) -#define vsuxei16_v_u32m4_m(...) __riscv_vsuxei16_v_u32m4_m(__VA_ARGS__) -#define vsuxei16_v_u32m8_m(...) __riscv_vsuxei16_v_u32m8_m(__VA_ARGS__) -#define vsuxei32_v_u32mf2_m(...) __riscv_vsuxei32_v_u32mf2_m(__VA_ARGS__) -#define vsuxei32_v_u32m1_m(...) __riscv_vsuxei32_v_u32m1_m(__VA_ARGS__) -#define vsuxei32_v_u32m2_m(...) __riscv_vsuxei32_v_u32m2_m(__VA_ARGS__) -#define vsuxei32_v_u32m4_m(...) __riscv_vsuxei32_v_u32m4_m(__VA_ARGS__) -#define vsuxei32_v_u32m8_m(...) __riscv_vsuxei32_v_u32m8_m(__VA_ARGS__) -#define vsuxei64_v_u32mf2_m(...) __riscv_vsuxei64_v_u32mf2_m(__VA_ARGS__) -#define vsuxei64_v_u32m1_m(...) __riscv_vsuxei64_v_u32m1_m(__VA_ARGS__) -#define vsuxei64_v_u32m2_m(...) __riscv_vsuxei64_v_u32m2_m(__VA_ARGS__) -#define vsuxei64_v_u32m4_m(...) __riscv_vsuxei64_v_u32m4_m(__VA_ARGS__) -#define vsuxei8_v_u64m1_m(...) __riscv_vsuxei8_v_u64m1_m(__VA_ARGS__) -#define vsuxei8_v_u64m2_m(...) __riscv_vsuxei8_v_u64m2_m(__VA_ARGS__) -#define vsuxei8_v_u64m4_m(...) __riscv_vsuxei8_v_u64m4_m(__VA_ARGS__) -#define vsuxei8_v_u64m8_m(...) __riscv_vsuxei8_v_u64m8_m(__VA_ARGS__) -#define vsuxei16_v_u64m1_m(...) __riscv_vsuxei16_v_u64m1_m(__VA_ARGS__) -#define vsuxei16_v_u64m2_m(...) __riscv_vsuxei16_v_u64m2_m(__VA_ARGS__) -#define vsuxei16_v_u64m4_m(...) __riscv_vsuxei16_v_u64m4_m(__VA_ARGS__) -#define vsuxei16_v_u64m8_m(...) __riscv_vsuxei16_v_u64m8_m(__VA_ARGS__) -#define vsuxei32_v_u64m1_m(...) __riscv_vsuxei32_v_u64m1_m(__VA_ARGS__) -#define vsuxei32_v_u64m2_m(...) __riscv_vsuxei32_v_u64m2_m(__VA_ARGS__) -#define vsuxei32_v_u64m4_m(...) __riscv_vsuxei32_v_u64m4_m(__VA_ARGS__) -#define vsuxei32_v_u64m8_m(...) __riscv_vsuxei32_v_u64m8_m(__VA_ARGS__) -#define vsuxei64_v_u64m1_m(...) __riscv_vsuxei64_v_u64m1_m(__VA_ARGS__) -#define vsuxei64_v_u64m2_m(...) __riscv_vsuxei64_v_u64m2_m(__VA_ARGS__) -#define vsuxei64_v_u64m4_m(...) __riscv_vsuxei64_v_u64m4_m(__VA_ARGS__) -#define vsuxei64_v_u64m8_m(...) __riscv_vsuxei64_v_u64m8_m(__VA_ARGS__) -#define vle16ff_v_f16mf4(...) __riscv_vle16ff_v_f16mf4(__VA_ARGS__) -#define vle16ff_v_f16mf2(...) __riscv_vle16ff_v_f16mf2(__VA_ARGS__) -#define vle16ff_v_f16m1(...) __riscv_vle16ff_v_f16m1(__VA_ARGS__) -#define vle16ff_v_f16m2(...) __riscv_vle16ff_v_f16m2(__VA_ARGS__) -#define vle16ff_v_f16m4(...) __riscv_vle16ff_v_f16m4(__VA_ARGS__) -#define vle16ff_v_f16m8(...) __riscv_vle16ff_v_f16m8(__VA_ARGS__) -#define vle32ff_v_f32mf2(...) __riscv_vle32ff_v_f32mf2(__VA_ARGS__) -#define vle32ff_v_f32m1(...) __riscv_vle32ff_v_f32m1(__VA_ARGS__) -#define vle32ff_v_f32m2(...) __riscv_vle32ff_v_f32m2(__VA_ARGS__) -#define vle32ff_v_f32m4(...) __riscv_vle32ff_v_f32m4(__VA_ARGS__) -#define vle32ff_v_f32m8(...) __riscv_vle32ff_v_f32m8(__VA_ARGS__) -#define vle64ff_v_f64m1(...) __riscv_vle64ff_v_f64m1(__VA_ARGS__) -#define vle64ff_v_f64m2(...) __riscv_vle64ff_v_f64m2(__VA_ARGS__) -#define vle64ff_v_f64m4(...) __riscv_vle64ff_v_f64m4(__VA_ARGS__) -#define vle64ff_v_f64m8(...) __riscv_vle64ff_v_f64m8(__VA_ARGS__) -#define vle8ff_v_i8mf8(...) __riscv_vle8ff_v_i8mf8(__VA_ARGS__) -#define vle8ff_v_i8mf4(...) __riscv_vle8ff_v_i8mf4(__VA_ARGS__) -#define vle8ff_v_i8mf2(...) __riscv_vle8ff_v_i8mf2(__VA_ARGS__) -#define vle8ff_v_i8m1(...) __riscv_vle8ff_v_i8m1(__VA_ARGS__) -#define vle8ff_v_i8m2(...) __riscv_vle8ff_v_i8m2(__VA_ARGS__) -#define vle8ff_v_i8m4(...) __riscv_vle8ff_v_i8m4(__VA_ARGS__) -#define vle8ff_v_i8m8(...) __riscv_vle8ff_v_i8m8(__VA_ARGS__) -#define vle16ff_v_i16mf4(...) __riscv_vle16ff_v_i16mf4(__VA_ARGS__) -#define vle16ff_v_i16mf2(...) __riscv_vle16ff_v_i16mf2(__VA_ARGS__) -#define vle16ff_v_i16m1(...) __riscv_vle16ff_v_i16m1(__VA_ARGS__) -#define vle16ff_v_i16m2(...) __riscv_vle16ff_v_i16m2(__VA_ARGS__) -#define vle16ff_v_i16m4(...) __riscv_vle16ff_v_i16m4(__VA_ARGS__) -#define vle16ff_v_i16m8(...) __riscv_vle16ff_v_i16m8(__VA_ARGS__) -#define vle32ff_v_i32mf2(...) __riscv_vle32ff_v_i32mf2(__VA_ARGS__) -#define vle32ff_v_i32m1(...) __riscv_vle32ff_v_i32m1(__VA_ARGS__) -#define vle32ff_v_i32m2(...) __riscv_vle32ff_v_i32m2(__VA_ARGS__) -#define vle32ff_v_i32m4(...) __riscv_vle32ff_v_i32m4(__VA_ARGS__) -#define vle32ff_v_i32m8(...) __riscv_vle32ff_v_i32m8(__VA_ARGS__) -#define vle64ff_v_i64m1(...) __riscv_vle64ff_v_i64m1(__VA_ARGS__) -#define vle64ff_v_i64m2(...) __riscv_vle64ff_v_i64m2(__VA_ARGS__) -#define vle64ff_v_i64m4(...) __riscv_vle64ff_v_i64m4(__VA_ARGS__) -#define vle64ff_v_i64m8(...) __riscv_vle64ff_v_i64m8(__VA_ARGS__) -#define vle8ff_v_u8mf8(...) __riscv_vle8ff_v_u8mf8(__VA_ARGS__) -#define vle8ff_v_u8mf4(...) __riscv_vle8ff_v_u8mf4(__VA_ARGS__) -#define vle8ff_v_u8mf2(...) __riscv_vle8ff_v_u8mf2(__VA_ARGS__) -#define vle8ff_v_u8m1(...) __riscv_vle8ff_v_u8m1(__VA_ARGS__) -#define vle8ff_v_u8m2(...) __riscv_vle8ff_v_u8m2(__VA_ARGS__) -#define vle8ff_v_u8m4(...) __riscv_vle8ff_v_u8m4(__VA_ARGS__) -#define vle8ff_v_u8m8(...) __riscv_vle8ff_v_u8m8(__VA_ARGS__) -#define vle16ff_v_u16mf4(...) __riscv_vle16ff_v_u16mf4(__VA_ARGS__) -#define vle16ff_v_u16mf2(...) __riscv_vle16ff_v_u16mf2(__VA_ARGS__) -#define vle16ff_v_u16m1(...) __riscv_vle16ff_v_u16m1(__VA_ARGS__) -#define vle16ff_v_u16m2(...) __riscv_vle16ff_v_u16m2(__VA_ARGS__) -#define vle16ff_v_u16m4(...) __riscv_vle16ff_v_u16m4(__VA_ARGS__) -#define vle16ff_v_u16m8(...) __riscv_vle16ff_v_u16m8(__VA_ARGS__) -#define vle32ff_v_u32mf2(...) __riscv_vle32ff_v_u32mf2(__VA_ARGS__) -#define vle32ff_v_u32m1(...) __riscv_vle32ff_v_u32m1(__VA_ARGS__) -#define vle32ff_v_u32m2(...) __riscv_vle32ff_v_u32m2(__VA_ARGS__) -#define vle32ff_v_u32m4(...) __riscv_vle32ff_v_u32m4(__VA_ARGS__) -#define vle32ff_v_u32m8(...) __riscv_vle32ff_v_u32m8(__VA_ARGS__) -#define vle64ff_v_u64m1(...) __riscv_vle64ff_v_u64m1(__VA_ARGS__) -#define vle64ff_v_u64m2(...) __riscv_vle64ff_v_u64m2(__VA_ARGS__) -#define vle64ff_v_u64m4(...) __riscv_vle64ff_v_u64m4(__VA_ARGS__) -#define vle64ff_v_u64m8(...) __riscv_vle64ff_v_u64m8(__VA_ARGS__) -// masked functions -#define vle16ff_v_f16mf4_m(...) __riscv_vle16ff_v_f16mf4_tumu(__VA_ARGS__) -#define vle16ff_v_f16mf2_m(...) __riscv_vle16ff_v_f16mf2_tumu(__VA_ARGS__) -#define vle16ff_v_f16m1_m(...) __riscv_vle16ff_v_f16m1_tumu(__VA_ARGS__) -#define vle16ff_v_f16m2_m(...) __riscv_vle16ff_v_f16m2_tumu(__VA_ARGS__) -#define vle16ff_v_f16m4_m(...) __riscv_vle16ff_v_f16m4_tumu(__VA_ARGS__) -#define vle16ff_v_f16m8_m(...) __riscv_vle16ff_v_f16m8_tumu(__VA_ARGS__) -#define vle32ff_v_f32mf2_m(...) __riscv_vle32ff_v_f32mf2_tumu(__VA_ARGS__) -#define vle32ff_v_f32m1_m(...) __riscv_vle32ff_v_f32m1_tumu(__VA_ARGS__) -#define vle32ff_v_f32m2_m(...) __riscv_vle32ff_v_f32m2_tumu(__VA_ARGS__) -#define vle32ff_v_f32m4_m(...) __riscv_vle32ff_v_f32m4_tumu(__VA_ARGS__) -#define vle32ff_v_f32m8_m(...) __riscv_vle32ff_v_f32m8_tumu(__VA_ARGS__) -#define vle64ff_v_f64m1_m(...) __riscv_vle64ff_v_f64m1_tumu(__VA_ARGS__) -#define vle64ff_v_f64m2_m(...) __riscv_vle64ff_v_f64m2_tumu(__VA_ARGS__) -#define vle64ff_v_f64m4_m(...) __riscv_vle64ff_v_f64m4_tumu(__VA_ARGS__) -#define vle64ff_v_f64m8_m(...) __riscv_vle64ff_v_f64m8_tumu(__VA_ARGS__) -#define vle8ff_v_i8mf8_m(...) __riscv_vle8ff_v_i8mf8_tumu(__VA_ARGS__) -#define vle8ff_v_i8mf4_m(...) __riscv_vle8ff_v_i8mf4_tumu(__VA_ARGS__) -#define vle8ff_v_i8mf2_m(...) __riscv_vle8ff_v_i8mf2_tumu(__VA_ARGS__) -#define vle8ff_v_i8m1_m(...) __riscv_vle8ff_v_i8m1_tumu(__VA_ARGS__) -#define vle8ff_v_i8m2_m(...) __riscv_vle8ff_v_i8m2_tumu(__VA_ARGS__) -#define vle8ff_v_i8m4_m(...) __riscv_vle8ff_v_i8m4_tumu(__VA_ARGS__) -#define vle8ff_v_i8m8_m(...) __riscv_vle8ff_v_i8m8_tumu(__VA_ARGS__) -#define vle16ff_v_i16mf4_m(...) __riscv_vle16ff_v_i16mf4_tumu(__VA_ARGS__) -#define vle16ff_v_i16mf2_m(...) __riscv_vle16ff_v_i16mf2_tumu(__VA_ARGS__) -#define vle16ff_v_i16m1_m(...) __riscv_vle16ff_v_i16m1_tumu(__VA_ARGS__) -#define vle16ff_v_i16m2_m(...) __riscv_vle16ff_v_i16m2_tumu(__VA_ARGS__) -#define vle16ff_v_i16m4_m(...) __riscv_vle16ff_v_i16m4_tumu(__VA_ARGS__) -#define vle16ff_v_i16m8_m(...) __riscv_vle16ff_v_i16m8_tumu(__VA_ARGS__) -#define vle32ff_v_i32mf2_m(...) __riscv_vle32ff_v_i32mf2_tumu(__VA_ARGS__) -#define vle32ff_v_i32m1_m(...) __riscv_vle32ff_v_i32m1_tumu(__VA_ARGS__) -#define vle32ff_v_i32m2_m(...) __riscv_vle32ff_v_i32m2_tumu(__VA_ARGS__) -#define vle32ff_v_i32m4_m(...) __riscv_vle32ff_v_i32m4_tumu(__VA_ARGS__) -#define vle32ff_v_i32m8_m(...) __riscv_vle32ff_v_i32m8_tumu(__VA_ARGS__) -#define vle64ff_v_i64m1_m(...) __riscv_vle64ff_v_i64m1_tumu(__VA_ARGS__) -#define vle64ff_v_i64m2_m(...) __riscv_vle64ff_v_i64m2_tumu(__VA_ARGS__) -#define vle64ff_v_i64m4_m(...) __riscv_vle64ff_v_i64m4_tumu(__VA_ARGS__) -#define vle64ff_v_i64m8_m(...) __riscv_vle64ff_v_i64m8_tumu(__VA_ARGS__) -#define vle8ff_v_u8mf8_m(...) __riscv_vle8ff_v_u8mf8_tumu(__VA_ARGS__) -#define vle8ff_v_u8mf4_m(...) __riscv_vle8ff_v_u8mf4_tumu(__VA_ARGS__) -#define vle8ff_v_u8mf2_m(...) __riscv_vle8ff_v_u8mf2_tumu(__VA_ARGS__) -#define vle8ff_v_u8m1_m(...) __riscv_vle8ff_v_u8m1_tumu(__VA_ARGS__) -#define vle8ff_v_u8m2_m(...) __riscv_vle8ff_v_u8m2_tumu(__VA_ARGS__) -#define vle8ff_v_u8m4_m(...) __riscv_vle8ff_v_u8m4_tumu(__VA_ARGS__) -#define vle8ff_v_u8m8_m(...) __riscv_vle8ff_v_u8m8_tumu(__VA_ARGS__) -#define vle16ff_v_u16mf4_m(...) __riscv_vle16ff_v_u16mf4_tumu(__VA_ARGS__) -#define vle16ff_v_u16mf2_m(...) __riscv_vle16ff_v_u16mf2_tumu(__VA_ARGS__) -#define vle16ff_v_u16m1_m(...) __riscv_vle16ff_v_u16m1_tumu(__VA_ARGS__) -#define vle16ff_v_u16m2_m(...) __riscv_vle16ff_v_u16m2_tumu(__VA_ARGS__) -#define vle16ff_v_u16m4_m(...) __riscv_vle16ff_v_u16m4_tumu(__VA_ARGS__) -#define vle16ff_v_u16m8_m(...) __riscv_vle16ff_v_u16m8_tumu(__VA_ARGS__) -#define vle32ff_v_u32mf2_m(...) __riscv_vle32ff_v_u32mf2_tumu(__VA_ARGS__) -#define vle32ff_v_u32m1_m(...) __riscv_vle32ff_v_u32m1_tumu(__VA_ARGS__) -#define vle32ff_v_u32m2_m(...) __riscv_vle32ff_v_u32m2_tumu(__VA_ARGS__) -#define vle32ff_v_u32m4_m(...) __riscv_vle32ff_v_u32m4_tumu(__VA_ARGS__) -#define vle32ff_v_u32m8_m(...) __riscv_vle32ff_v_u32m8_tumu(__VA_ARGS__) -#define vle64ff_v_u64m1_m(...) __riscv_vle64ff_v_u64m1_tumu(__VA_ARGS__) -#define vle64ff_v_u64m2_m(...) __riscv_vle64ff_v_u64m2_tumu(__VA_ARGS__) -#define vle64ff_v_u64m4_m(...) __riscv_vle64ff_v_u64m4_tumu(__VA_ARGS__) -#define vle64ff_v_u64m8_m(...) __riscv_vle64ff_v_u64m8_tumu(__VA_ARGS__) -#define vlseg2e16_v_f16mf4(...) __riscv_vlseg2e16_v_f16mf4(__VA_ARGS__) -#define vlseg3e16_v_f16mf4(...) __riscv_vlseg3e16_v_f16mf4(__VA_ARGS__) -#define vlseg4e16_v_f16mf4(...) __riscv_vlseg4e16_v_f16mf4(__VA_ARGS__) -#define vlseg5e16_v_f16mf4(...) __riscv_vlseg5e16_v_f16mf4(__VA_ARGS__) -#define vlseg6e16_v_f16mf4(...) __riscv_vlseg6e16_v_f16mf4(__VA_ARGS__) -#define vlseg7e16_v_f16mf4(...) __riscv_vlseg7e16_v_f16mf4(__VA_ARGS__) -#define vlseg8e16_v_f16mf4(...) __riscv_vlseg8e16_v_f16mf4(__VA_ARGS__) -#define vlseg2e16_v_f16mf2(...) __riscv_vlseg2e16_v_f16mf2(__VA_ARGS__) -#define vlseg3e16_v_f16mf2(...) __riscv_vlseg3e16_v_f16mf2(__VA_ARGS__) -#define vlseg4e16_v_f16mf2(...) __riscv_vlseg4e16_v_f16mf2(__VA_ARGS__) -#define vlseg5e16_v_f16mf2(...) __riscv_vlseg5e16_v_f16mf2(__VA_ARGS__) -#define vlseg6e16_v_f16mf2(...) __riscv_vlseg6e16_v_f16mf2(__VA_ARGS__) -#define vlseg7e16_v_f16mf2(...) __riscv_vlseg7e16_v_f16mf2(__VA_ARGS__) -#define vlseg8e16_v_f16mf2(...) __riscv_vlseg8e16_v_f16mf2(__VA_ARGS__) -#define vlseg2e16_v_f16m1(...) __riscv_vlseg2e16_v_f16m1(__VA_ARGS__) -#define vlseg3e16_v_f16m1(...) __riscv_vlseg3e16_v_f16m1(__VA_ARGS__) -#define vlseg4e16_v_f16m1(...) __riscv_vlseg4e16_v_f16m1(__VA_ARGS__) -#define vlseg5e16_v_f16m1(...) __riscv_vlseg5e16_v_f16m1(__VA_ARGS__) -#define vlseg6e16_v_f16m1(...) __riscv_vlseg6e16_v_f16m1(__VA_ARGS__) -#define vlseg7e16_v_f16m1(...) __riscv_vlseg7e16_v_f16m1(__VA_ARGS__) -#define vlseg8e16_v_f16m1(...) __riscv_vlseg8e16_v_f16m1(__VA_ARGS__) -#define vlseg2e16_v_f16m2(...) __riscv_vlseg2e16_v_f16m2(__VA_ARGS__) -#define vlseg3e16_v_f16m2(...) __riscv_vlseg3e16_v_f16m2(__VA_ARGS__) -#define vlseg4e16_v_f16m2(...) __riscv_vlseg4e16_v_f16m2(__VA_ARGS__) -#define vlseg2e16_v_f16m4(...) __riscv_vlseg2e16_v_f16m4(__VA_ARGS__) -#define vlseg2e32_v_f32mf2(...) __riscv_vlseg2e32_v_f32mf2(__VA_ARGS__) -#define vlseg3e32_v_f32mf2(...) __riscv_vlseg3e32_v_f32mf2(__VA_ARGS__) -#define vlseg4e32_v_f32mf2(...) __riscv_vlseg4e32_v_f32mf2(__VA_ARGS__) -#define vlseg5e32_v_f32mf2(...) __riscv_vlseg5e32_v_f32mf2(__VA_ARGS__) -#define vlseg6e32_v_f32mf2(...) __riscv_vlseg6e32_v_f32mf2(__VA_ARGS__) -#define vlseg7e32_v_f32mf2(...) __riscv_vlseg7e32_v_f32mf2(__VA_ARGS__) -#define vlseg8e32_v_f32mf2(...) __riscv_vlseg8e32_v_f32mf2(__VA_ARGS__) -#define vlseg2e32_v_f32m1(...) __riscv_vlseg2e32_v_f32m1(__VA_ARGS__) -#define vlseg3e32_v_f32m1(...) __riscv_vlseg3e32_v_f32m1(__VA_ARGS__) -#define vlseg4e32_v_f32m1(...) __riscv_vlseg4e32_v_f32m1(__VA_ARGS__) -#define vlseg5e32_v_f32m1(...) __riscv_vlseg5e32_v_f32m1(__VA_ARGS__) -#define vlseg6e32_v_f32m1(...) __riscv_vlseg6e32_v_f32m1(__VA_ARGS__) -#define vlseg7e32_v_f32m1(...) __riscv_vlseg7e32_v_f32m1(__VA_ARGS__) -#define vlseg8e32_v_f32m1(...) __riscv_vlseg8e32_v_f32m1(__VA_ARGS__) -#define vlseg2e32_v_f32m2(...) __riscv_vlseg2e32_v_f32m2(__VA_ARGS__) -#define vlseg3e32_v_f32m2(...) __riscv_vlseg3e32_v_f32m2(__VA_ARGS__) -#define vlseg4e32_v_f32m2(...) __riscv_vlseg4e32_v_f32m2(__VA_ARGS__) -#define vlseg2e32_v_f32m4(...) __riscv_vlseg2e32_v_f32m4(__VA_ARGS__) -#define vlseg2e64_v_f64m1(...) __riscv_vlseg2e64_v_f64m1(__VA_ARGS__) -#define vlseg3e64_v_f64m1(...) __riscv_vlseg3e64_v_f64m1(__VA_ARGS__) -#define vlseg4e64_v_f64m1(...) __riscv_vlseg4e64_v_f64m1(__VA_ARGS__) -#define vlseg5e64_v_f64m1(...) __riscv_vlseg5e64_v_f64m1(__VA_ARGS__) -#define vlseg6e64_v_f64m1(...) __riscv_vlseg6e64_v_f64m1(__VA_ARGS__) -#define vlseg7e64_v_f64m1(...) __riscv_vlseg7e64_v_f64m1(__VA_ARGS__) -#define vlseg8e64_v_f64m1(...) __riscv_vlseg8e64_v_f64m1(__VA_ARGS__) -#define vlseg2e64_v_f64m2(...) __riscv_vlseg2e64_v_f64m2(__VA_ARGS__) -#define vlseg3e64_v_f64m2(...) __riscv_vlseg3e64_v_f64m2(__VA_ARGS__) -#define vlseg4e64_v_f64m2(...) __riscv_vlseg4e64_v_f64m2(__VA_ARGS__) -#define vlseg2e64_v_f64m4(...) __riscv_vlseg2e64_v_f64m4(__VA_ARGS__) -#define vlseg2e16ff_v_f16mf4(...) __riscv_vlseg2e16ff_v_f16mf4(__VA_ARGS__) -#define vlseg3e16ff_v_f16mf4(...) __riscv_vlseg3e16ff_v_f16mf4(__VA_ARGS__) -#define vlseg4e16ff_v_f16mf4(...) __riscv_vlseg4e16ff_v_f16mf4(__VA_ARGS__) -#define vlseg5e16ff_v_f16mf4(...) __riscv_vlseg5e16ff_v_f16mf4(__VA_ARGS__) -#define vlseg6e16ff_v_f16mf4(...) __riscv_vlseg6e16ff_v_f16mf4(__VA_ARGS__) -#define vlseg7e16ff_v_f16mf4(...) __riscv_vlseg7e16ff_v_f16mf4(__VA_ARGS__) -#define vlseg8e16ff_v_f16mf4(...) __riscv_vlseg8e16ff_v_f16mf4(__VA_ARGS__) -#define vlseg2e16ff_v_f16mf2(...) __riscv_vlseg2e16ff_v_f16mf2(__VA_ARGS__) -#define vlseg3e16ff_v_f16mf2(...) __riscv_vlseg3e16ff_v_f16mf2(__VA_ARGS__) -#define vlseg4e16ff_v_f16mf2(...) __riscv_vlseg4e16ff_v_f16mf2(__VA_ARGS__) -#define vlseg5e16ff_v_f16mf2(...) __riscv_vlseg5e16ff_v_f16mf2(__VA_ARGS__) -#define vlseg6e16ff_v_f16mf2(...) __riscv_vlseg6e16ff_v_f16mf2(__VA_ARGS__) -#define vlseg7e16ff_v_f16mf2(...) __riscv_vlseg7e16ff_v_f16mf2(__VA_ARGS__) -#define vlseg8e16ff_v_f16mf2(...) __riscv_vlseg8e16ff_v_f16mf2(__VA_ARGS__) -#define vlseg2e16ff_v_f16m1(...) __riscv_vlseg2e16ff_v_f16m1(__VA_ARGS__) -#define vlseg3e16ff_v_f16m1(...) __riscv_vlseg3e16ff_v_f16m1(__VA_ARGS__) -#define vlseg4e16ff_v_f16m1(...) __riscv_vlseg4e16ff_v_f16m1(__VA_ARGS__) -#define vlseg5e16ff_v_f16m1(...) __riscv_vlseg5e16ff_v_f16m1(__VA_ARGS__) -#define vlseg6e16ff_v_f16m1(...) __riscv_vlseg6e16ff_v_f16m1(__VA_ARGS__) -#define vlseg7e16ff_v_f16m1(...) __riscv_vlseg7e16ff_v_f16m1(__VA_ARGS__) -#define vlseg8e16ff_v_f16m1(...) __riscv_vlseg8e16ff_v_f16m1(__VA_ARGS__) -#define vlseg2e16ff_v_f16m2(...) __riscv_vlseg2e16ff_v_f16m2(__VA_ARGS__) -#define vlseg3e16ff_v_f16m2(...) __riscv_vlseg3e16ff_v_f16m2(__VA_ARGS__) -#define vlseg4e16ff_v_f16m2(...) __riscv_vlseg4e16ff_v_f16m2(__VA_ARGS__) -#define vlseg2e16ff_v_f16m4(...) __riscv_vlseg2e16ff_v_f16m4(__VA_ARGS__) -#define vlseg2e32ff_v_f32mf2(...) __riscv_vlseg2e32ff_v_f32mf2(__VA_ARGS__) -#define vlseg3e32ff_v_f32mf2(...) __riscv_vlseg3e32ff_v_f32mf2(__VA_ARGS__) -#define vlseg4e32ff_v_f32mf2(...) __riscv_vlseg4e32ff_v_f32mf2(__VA_ARGS__) -#define vlseg5e32ff_v_f32mf2(...) __riscv_vlseg5e32ff_v_f32mf2(__VA_ARGS__) -#define vlseg6e32ff_v_f32mf2(...) __riscv_vlseg6e32ff_v_f32mf2(__VA_ARGS__) -#define vlseg7e32ff_v_f32mf2(...) __riscv_vlseg7e32ff_v_f32mf2(__VA_ARGS__) -#define vlseg8e32ff_v_f32mf2(...) __riscv_vlseg8e32ff_v_f32mf2(__VA_ARGS__) -#define vlseg2e32ff_v_f32m1(...) __riscv_vlseg2e32ff_v_f32m1(__VA_ARGS__) -#define vlseg3e32ff_v_f32m1(...) __riscv_vlseg3e32ff_v_f32m1(__VA_ARGS__) -#define vlseg4e32ff_v_f32m1(...) __riscv_vlseg4e32ff_v_f32m1(__VA_ARGS__) -#define vlseg5e32ff_v_f32m1(...) __riscv_vlseg5e32ff_v_f32m1(__VA_ARGS__) -#define vlseg6e32ff_v_f32m1(...) __riscv_vlseg6e32ff_v_f32m1(__VA_ARGS__) -#define vlseg7e32ff_v_f32m1(...) __riscv_vlseg7e32ff_v_f32m1(__VA_ARGS__) -#define vlseg8e32ff_v_f32m1(...) __riscv_vlseg8e32ff_v_f32m1(__VA_ARGS__) -#define vlseg2e32ff_v_f32m2(...) __riscv_vlseg2e32ff_v_f32m2(__VA_ARGS__) -#define vlseg3e32ff_v_f32m2(...) __riscv_vlseg3e32ff_v_f32m2(__VA_ARGS__) -#define vlseg4e32ff_v_f32m2(...) __riscv_vlseg4e32ff_v_f32m2(__VA_ARGS__) -#define vlseg2e32ff_v_f32m4(...) __riscv_vlseg2e32ff_v_f32m4(__VA_ARGS__) -#define vlseg2e64ff_v_f64m1(...) __riscv_vlseg2e64ff_v_f64m1(__VA_ARGS__) -#define vlseg3e64ff_v_f64m1(...) __riscv_vlseg3e64ff_v_f64m1(__VA_ARGS__) -#define vlseg4e64ff_v_f64m1(...) __riscv_vlseg4e64ff_v_f64m1(__VA_ARGS__) -#define vlseg5e64ff_v_f64m1(...) __riscv_vlseg5e64ff_v_f64m1(__VA_ARGS__) -#define vlseg6e64ff_v_f64m1(...) __riscv_vlseg6e64ff_v_f64m1(__VA_ARGS__) -#define vlseg7e64ff_v_f64m1(...) __riscv_vlseg7e64ff_v_f64m1(__VA_ARGS__) -#define vlseg8e64ff_v_f64m1(...) __riscv_vlseg8e64ff_v_f64m1(__VA_ARGS__) -#define vlseg2e64ff_v_f64m2(...) __riscv_vlseg2e64ff_v_f64m2(__VA_ARGS__) -#define vlseg3e64ff_v_f64m2(...) __riscv_vlseg3e64ff_v_f64m2(__VA_ARGS__) -#define vlseg4e64ff_v_f64m2(...) __riscv_vlseg4e64ff_v_f64m2(__VA_ARGS__) -#define vlseg2e64ff_v_f64m4(...) __riscv_vlseg2e64ff_v_f64m4(__VA_ARGS__) -#define vlseg2e8_v_i8mf8(...) __riscv_vlseg2e8_v_i8mf8(__VA_ARGS__) -#define vlseg3e8_v_i8mf8(...) __riscv_vlseg3e8_v_i8mf8(__VA_ARGS__) -#define vlseg4e8_v_i8mf8(...) __riscv_vlseg4e8_v_i8mf8(__VA_ARGS__) -#define vlseg5e8_v_i8mf8(...) __riscv_vlseg5e8_v_i8mf8(__VA_ARGS__) -#define vlseg6e8_v_i8mf8(...) __riscv_vlseg6e8_v_i8mf8(__VA_ARGS__) -#define vlseg7e8_v_i8mf8(...) __riscv_vlseg7e8_v_i8mf8(__VA_ARGS__) -#define vlseg8e8_v_i8mf8(...) __riscv_vlseg8e8_v_i8mf8(__VA_ARGS__) -#define vlseg2e8_v_i8mf4(...) __riscv_vlseg2e8_v_i8mf4(__VA_ARGS__) -#define vlseg3e8_v_i8mf4(...) __riscv_vlseg3e8_v_i8mf4(__VA_ARGS__) -#define vlseg4e8_v_i8mf4(...) __riscv_vlseg4e8_v_i8mf4(__VA_ARGS__) -#define vlseg5e8_v_i8mf4(...) __riscv_vlseg5e8_v_i8mf4(__VA_ARGS__) -#define vlseg6e8_v_i8mf4(...) __riscv_vlseg6e8_v_i8mf4(__VA_ARGS__) -#define vlseg7e8_v_i8mf4(...) __riscv_vlseg7e8_v_i8mf4(__VA_ARGS__) -#define vlseg8e8_v_i8mf4(...) __riscv_vlseg8e8_v_i8mf4(__VA_ARGS__) -#define vlseg2e8_v_i8mf2(...) __riscv_vlseg2e8_v_i8mf2(__VA_ARGS__) -#define vlseg3e8_v_i8mf2(...) __riscv_vlseg3e8_v_i8mf2(__VA_ARGS__) -#define vlseg4e8_v_i8mf2(...) __riscv_vlseg4e8_v_i8mf2(__VA_ARGS__) -#define vlseg5e8_v_i8mf2(...) __riscv_vlseg5e8_v_i8mf2(__VA_ARGS__) -#define vlseg6e8_v_i8mf2(...) __riscv_vlseg6e8_v_i8mf2(__VA_ARGS__) -#define vlseg7e8_v_i8mf2(...) __riscv_vlseg7e8_v_i8mf2(__VA_ARGS__) -#define vlseg8e8_v_i8mf2(...) __riscv_vlseg8e8_v_i8mf2(__VA_ARGS__) -#define vlseg2e8_v_i8m1(...) __riscv_vlseg2e8_v_i8m1(__VA_ARGS__) -#define vlseg3e8_v_i8m1(...) __riscv_vlseg3e8_v_i8m1(__VA_ARGS__) -#define vlseg4e8_v_i8m1(...) __riscv_vlseg4e8_v_i8m1(__VA_ARGS__) -#define vlseg5e8_v_i8m1(...) __riscv_vlseg5e8_v_i8m1(__VA_ARGS__) -#define vlseg6e8_v_i8m1(...) __riscv_vlseg6e8_v_i8m1(__VA_ARGS__) -#define vlseg7e8_v_i8m1(...) __riscv_vlseg7e8_v_i8m1(__VA_ARGS__) -#define vlseg8e8_v_i8m1(...) __riscv_vlseg8e8_v_i8m1(__VA_ARGS__) -#define vlseg2e8_v_i8m2(...) __riscv_vlseg2e8_v_i8m2(__VA_ARGS__) -#define vlseg3e8_v_i8m2(...) __riscv_vlseg3e8_v_i8m2(__VA_ARGS__) -#define vlseg4e8_v_i8m2(...) __riscv_vlseg4e8_v_i8m2(__VA_ARGS__) -#define vlseg2e8_v_i8m4(...) __riscv_vlseg2e8_v_i8m4(__VA_ARGS__) -#define vlseg2e16_v_i16mf4(...) __riscv_vlseg2e16_v_i16mf4(__VA_ARGS__) -#define vlseg3e16_v_i16mf4(...) __riscv_vlseg3e16_v_i16mf4(__VA_ARGS__) -#define vlseg4e16_v_i16mf4(...) __riscv_vlseg4e16_v_i16mf4(__VA_ARGS__) -#define vlseg5e16_v_i16mf4(...) __riscv_vlseg5e16_v_i16mf4(__VA_ARGS__) -#define vlseg6e16_v_i16mf4(...) __riscv_vlseg6e16_v_i16mf4(__VA_ARGS__) -#define vlseg7e16_v_i16mf4(...) __riscv_vlseg7e16_v_i16mf4(__VA_ARGS__) -#define vlseg8e16_v_i16mf4(...) __riscv_vlseg8e16_v_i16mf4(__VA_ARGS__) -#define vlseg2e16_v_i16mf2(...) __riscv_vlseg2e16_v_i16mf2(__VA_ARGS__) -#define vlseg3e16_v_i16mf2(...) __riscv_vlseg3e16_v_i16mf2(__VA_ARGS__) -#define vlseg4e16_v_i16mf2(...) __riscv_vlseg4e16_v_i16mf2(__VA_ARGS__) -#define vlseg5e16_v_i16mf2(...) __riscv_vlseg5e16_v_i16mf2(__VA_ARGS__) -#define vlseg6e16_v_i16mf2(...) __riscv_vlseg6e16_v_i16mf2(__VA_ARGS__) -#define vlseg7e16_v_i16mf2(...) __riscv_vlseg7e16_v_i16mf2(__VA_ARGS__) -#define vlseg8e16_v_i16mf2(...) __riscv_vlseg8e16_v_i16mf2(__VA_ARGS__) -#define vlseg2e16_v_i16m1(...) __riscv_vlseg2e16_v_i16m1(__VA_ARGS__) -#define vlseg3e16_v_i16m1(...) __riscv_vlseg3e16_v_i16m1(__VA_ARGS__) -#define vlseg4e16_v_i16m1(...) __riscv_vlseg4e16_v_i16m1(__VA_ARGS__) -#define vlseg5e16_v_i16m1(...) __riscv_vlseg5e16_v_i16m1(__VA_ARGS__) -#define vlseg6e16_v_i16m1(...) __riscv_vlseg6e16_v_i16m1(__VA_ARGS__) -#define vlseg7e16_v_i16m1(...) __riscv_vlseg7e16_v_i16m1(__VA_ARGS__) -#define vlseg8e16_v_i16m1(...) __riscv_vlseg8e16_v_i16m1(__VA_ARGS__) -#define vlseg2e16_v_i16m2(...) __riscv_vlseg2e16_v_i16m2(__VA_ARGS__) -#define vlseg3e16_v_i16m2(...) __riscv_vlseg3e16_v_i16m2(__VA_ARGS__) -#define vlseg4e16_v_i16m2(...) __riscv_vlseg4e16_v_i16m2(__VA_ARGS__) -#define vlseg2e16_v_i16m4(...) __riscv_vlseg2e16_v_i16m4(__VA_ARGS__) -#define vlseg2e32_v_i32mf2(...) __riscv_vlseg2e32_v_i32mf2(__VA_ARGS__) -#define vlseg3e32_v_i32mf2(...) __riscv_vlseg3e32_v_i32mf2(__VA_ARGS__) -#define vlseg4e32_v_i32mf2(...) __riscv_vlseg4e32_v_i32mf2(__VA_ARGS__) -#define vlseg5e32_v_i32mf2(...) __riscv_vlseg5e32_v_i32mf2(__VA_ARGS__) -#define vlseg6e32_v_i32mf2(...) __riscv_vlseg6e32_v_i32mf2(__VA_ARGS__) -#define vlseg7e32_v_i32mf2(...) __riscv_vlseg7e32_v_i32mf2(__VA_ARGS__) -#define vlseg8e32_v_i32mf2(...) __riscv_vlseg8e32_v_i32mf2(__VA_ARGS__) -#define vlseg2e32_v_i32m1(...) __riscv_vlseg2e32_v_i32m1(__VA_ARGS__) -#define vlseg3e32_v_i32m1(...) __riscv_vlseg3e32_v_i32m1(__VA_ARGS__) -#define vlseg4e32_v_i32m1(...) __riscv_vlseg4e32_v_i32m1(__VA_ARGS__) -#define vlseg5e32_v_i32m1(...) __riscv_vlseg5e32_v_i32m1(__VA_ARGS__) -#define vlseg6e32_v_i32m1(...) __riscv_vlseg6e32_v_i32m1(__VA_ARGS__) -#define vlseg7e32_v_i32m1(...) __riscv_vlseg7e32_v_i32m1(__VA_ARGS__) -#define vlseg8e32_v_i32m1(...) __riscv_vlseg8e32_v_i32m1(__VA_ARGS__) -#define vlseg2e32_v_i32m2(...) __riscv_vlseg2e32_v_i32m2(__VA_ARGS__) -#define vlseg3e32_v_i32m2(...) __riscv_vlseg3e32_v_i32m2(__VA_ARGS__) -#define vlseg4e32_v_i32m2(...) __riscv_vlseg4e32_v_i32m2(__VA_ARGS__) -#define vlseg2e32_v_i32m4(...) __riscv_vlseg2e32_v_i32m4(__VA_ARGS__) -#define vlseg2e64_v_i64m1(...) __riscv_vlseg2e64_v_i64m1(__VA_ARGS__) -#define vlseg3e64_v_i64m1(...) __riscv_vlseg3e64_v_i64m1(__VA_ARGS__) -#define vlseg4e64_v_i64m1(...) __riscv_vlseg4e64_v_i64m1(__VA_ARGS__) -#define vlseg5e64_v_i64m1(...) __riscv_vlseg5e64_v_i64m1(__VA_ARGS__) -#define vlseg6e64_v_i64m1(...) __riscv_vlseg6e64_v_i64m1(__VA_ARGS__) -#define vlseg7e64_v_i64m1(...) __riscv_vlseg7e64_v_i64m1(__VA_ARGS__) -#define vlseg8e64_v_i64m1(...) __riscv_vlseg8e64_v_i64m1(__VA_ARGS__) -#define vlseg2e64_v_i64m2(...) __riscv_vlseg2e64_v_i64m2(__VA_ARGS__) -#define vlseg3e64_v_i64m2(...) __riscv_vlseg3e64_v_i64m2(__VA_ARGS__) -#define vlseg4e64_v_i64m2(...) __riscv_vlseg4e64_v_i64m2(__VA_ARGS__) -#define vlseg2e64_v_i64m4(...) __riscv_vlseg2e64_v_i64m4(__VA_ARGS__) -#define vlseg2e8ff_v_i8mf8(...) __riscv_vlseg2e8ff_v_i8mf8(__VA_ARGS__) -#define vlseg3e8ff_v_i8mf8(...) __riscv_vlseg3e8ff_v_i8mf8(__VA_ARGS__) -#define vlseg4e8ff_v_i8mf8(...) __riscv_vlseg4e8ff_v_i8mf8(__VA_ARGS__) -#define vlseg5e8ff_v_i8mf8(...) __riscv_vlseg5e8ff_v_i8mf8(__VA_ARGS__) -#define vlseg6e8ff_v_i8mf8(...) __riscv_vlseg6e8ff_v_i8mf8(__VA_ARGS__) -#define vlseg7e8ff_v_i8mf8(...) __riscv_vlseg7e8ff_v_i8mf8(__VA_ARGS__) -#define vlseg8e8ff_v_i8mf8(...) __riscv_vlseg8e8ff_v_i8mf8(__VA_ARGS__) -#define vlseg2e8ff_v_i8mf4(...) __riscv_vlseg2e8ff_v_i8mf4(__VA_ARGS__) -#define vlseg3e8ff_v_i8mf4(...) __riscv_vlseg3e8ff_v_i8mf4(__VA_ARGS__) -#define vlseg4e8ff_v_i8mf4(...) __riscv_vlseg4e8ff_v_i8mf4(__VA_ARGS__) -#define vlseg5e8ff_v_i8mf4(...) __riscv_vlseg5e8ff_v_i8mf4(__VA_ARGS__) -#define vlseg6e8ff_v_i8mf4(...) __riscv_vlseg6e8ff_v_i8mf4(__VA_ARGS__) -#define vlseg7e8ff_v_i8mf4(...) __riscv_vlseg7e8ff_v_i8mf4(__VA_ARGS__) -#define vlseg8e8ff_v_i8mf4(...) __riscv_vlseg8e8ff_v_i8mf4(__VA_ARGS__) -#define vlseg2e8ff_v_i8mf2(...) __riscv_vlseg2e8ff_v_i8mf2(__VA_ARGS__) -#define vlseg3e8ff_v_i8mf2(...) __riscv_vlseg3e8ff_v_i8mf2(__VA_ARGS__) -#define vlseg4e8ff_v_i8mf2(...) __riscv_vlseg4e8ff_v_i8mf2(__VA_ARGS__) -#define vlseg5e8ff_v_i8mf2(...) __riscv_vlseg5e8ff_v_i8mf2(__VA_ARGS__) -#define vlseg6e8ff_v_i8mf2(...) __riscv_vlseg6e8ff_v_i8mf2(__VA_ARGS__) -#define vlseg7e8ff_v_i8mf2(...) __riscv_vlseg7e8ff_v_i8mf2(__VA_ARGS__) -#define vlseg8e8ff_v_i8mf2(...) __riscv_vlseg8e8ff_v_i8mf2(__VA_ARGS__) -#define vlseg2e8ff_v_i8m1(...) __riscv_vlseg2e8ff_v_i8m1(__VA_ARGS__) -#define vlseg3e8ff_v_i8m1(...) __riscv_vlseg3e8ff_v_i8m1(__VA_ARGS__) -#define vlseg4e8ff_v_i8m1(...) __riscv_vlseg4e8ff_v_i8m1(__VA_ARGS__) -#define vlseg5e8ff_v_i8m1(...) __riscv_vlseg5e8ff_v_i8m1(__VA_ARGS__) -#define vlseg6e8ff_v_i8m1(...) __riscv_vlseg6e8ff_v_i8m1(__VA_ARGS__) -#define vlseg7e8ff_v_i8m1(...) __riscv_vlseg7e8ff_v_i8m1(__VA_ARGS__) -#define vlseg8e8ff_v_i8m1(...) __riscv_vlseg8e8ff_v_i8m1(__VA_ARGS__) -#define vlseg2e8ff_v_i8m2(...) __riscv_vlseg2e8ff_v_i8m2(__VA_ARGS__) -#define vlseg3e8ff_v_i8m2(...) __riscv_vlseg3e8ff_v_i8m2(__VA_ARGS__) -#define vlseg4e8ff_v_i8m2(...) __riscv_vlseg4e8ff_v_i8m2(__VA_ARGS__) -#define vlseg2e8ff_v_i8m4(...) __riscv_vlseg2e8ff_v_i8m4(__VA_ARGS__) -#define vlseg2e16ff_v_i16mf4(...) __riscv_vlseg2e16ff_v_i16mf4(__VA_ARGS__) -#define vlseg3e16ff_v_i16mf4(...) __riscv_vlseg3e16ff_v_i16mf4(__VA_ARGS__) -#define vlseg4e16ff_v_i16mf4(...) __riscv_vlseg4e16ff_v_i16mf4(__VA_ARGS__) -#define vlseg5e16ff_v_i16mf4(...) __riscv_vlseg5e16ff_v_i16mf4(__VA_ARGS__) -#define vlseg6e16ff_v_i16mf4(...) __riscv_vlseg6e16ff_v_i16mf4(__VA_ARGS__) -#define vlseg7e16ff_v_i16mf4(...) __riscv_vlseg7e16ff_v_i16mf4(__VA_ARGS__) -#define vlseg8e16ff_v_i16mf4(...) __riscv_vlseg8e16ff_v_i16mf4(__VA_ARGS__) -#define vlseg2e16ff_v_i16mf2(...) __riscv_vlseg2e16ff_v_i16mf2(__VA_ARGS__) -#define vlseg3e16ff_v_i16mf2(...) __riscv_vlseg3e16ff_v_i16mf2(__VA_ARGS__) -#define vlseg4e16ff_v_i16mf2(...) __riscv_vlseg4e16ff_v_i16mf2(__VA_ARGS__) -#define vlseg5e16ff_v_i16mf2(...) __riscv_vlseg5e16ff_v_i16mf2(__VA_ARGS__) -#define vlseg6e16ff_v_i16mf2(...) __riscv_vlseg6e16ff_v_i16mf2(__VA_ARGS__) -#define vlseg7e16ff_v_i16mf2(...) __riscv_vlseg7e16ff_v_i16mf2(__VA_ARGS__) -#define vlseg8e16ff_v_i16mf2(...) __riscv_vlseg8e16ff_v_i16mf2(__VA_ARGS__) -#define vlseg2e16ff_v_i16m1(...) __riscv_vlseg2e16ff_v_i16m1(__VA_ARGS__) -#define vlseg3e16ff_v_i16m1(...) __riscv_vlseg3e16ff_v_i16m1(__VA_ARGS__) -#define vlseg4e16ff_v_i16m1(...) __riscv_vlseg4e16ff_v_i16m1(__VA_ARGS__) -#define vlseg5e16ff_v_i16m1(...) __riscv_vlseg5e16ff_v_i16m1(__VA_ARGS__) -#define vlseg6e16ff_v_i16m1(...) __riscv_vlseg6e16ff_v_i16m1(__VA_ARGS__) -#define vlseg7e16ff_v_i16m1(...) __riscv_vlseg7e16ff_v_i16m1(__VA_ARGS__) -#define vlseg8e16ff_v_i16m1(...) __riscv_vlseg8e16ff_v_i16m1(__VA_ARGS__) -#define vlseg2e16ff_v_i16m2(...) __riscv_vlseg2e16ff_v_i16m2(__VA_ARGS__) -#define vlseg3e16ff_v_i16m2(...) __riscv_vlseg3e16ff_v_i16m2(__VA_ARGS__) -#define vlseg4e16ff_v_i16m2(...) __riscv_vlseg4e16ff_v_i16m2(__VA_ARGS__) -#define vlseg2e16ff_v_i16m4(...) __riscv_vlseg2e16ff_v_i16m4(__VA_ARGS__) -#define vlseg2e32ff_v_i32mf2(...) __riscv_vlseg2e32ff_v_i32mf2(__VA_ARGS__) -#define vlseg3e32ff_v_i32mf2(...) __riscv_vlseg3e32ff_v_i32mf2(__VA_ARGS__) -#define vlseg4e32ff_v_i32mf2(...) __riscv_vlseg4e32ff_v_i32mf2(__VA_ARGS__) -#define vlseg5e32ff_v_i32mf2(...) __riscv_vlseg5e32ff_v_i32mf2(__VA_ARGS__) -#define vlseg6e32ff_v_i32mf2(...) __riscv_vlseg6e32ff_v_i32mf2(__VA_ARGS__) -#define vlseg7e32ff_v_i32mf2(...) __riscv_vlseg7e32ff_v_i32mf2(__VA_ARGS__) -#define vlseg8e32ff_v_i32mf2(...) __riscv_vlseg8e32ff_v_i32mf2(__VA_ARGS__) -#define vlseg2e32ff_v_i32m1(...) __riscv_vlseg2e32ff_v_i32m1(__VA_ARGS__) -#define vlseg3e32ff_v_i32m1(...) __riscv_vlseg3e32ff_v_i32m1(__VA_ARGS__) -#define vlseg4e32ff_v_i32m1(...) __riscv_vlseg4e32ff_v_i32m1(__VA_ARGS__) -#define vlseg5e32ff_v_i32m1(...) __riscv_vlseg5e32ff_v_i32m1(__VA_ARGS__) -#define vlseg6e32ff_v_i32m1(...) __riscv_vlseg6e32ff_v_i32m1(__VA_ARGS__) -#define vlseg7e32ff_v_i32m1(...) __riscv_vlseg7e32ff_v_i32m1(__VA_ARGS__) -#define vlseg8e32ff_v_i32m1(...) __riscv_vlseg8e32ff_v_i32m1(__VA_ARGS__) -#define vlseg2e32ff_v_i32m2(...) __riscv_vlseg2e32ff_v_i32m2(__VA_ARGS__) -#define vlseg3e32ff_v_i32m2(...) __riscv_vlseg3e32ff_v_i32m2(__VA_ARGS__) -#define vlseg4e32ff_v_i32m2(...) __riscv_vlseg4e32ff_v_i32m2(__VA_ARGS__) -#define vlseg2e32ff_v_i32m4(...) __riscv_vlseg2e32ff_v_i32m4(__VA_ARGS__) -#define vlseg2e64ff_v_i64m1(...) __riscv_vlseg2e64ff_v_i64m1(__VA_ARGS__) -#define vlseg3e64ff_v_i64m1(...) __riscv_vlseg3e64ff_v_i64m1(__VA_ARGS__) -#define vlseg4e64ff_v_i64m1(...) __riscv_vlseg4e64ff_v_i64m1(__VA_ARGS__) -#define vlseg5e64ff_v_i64m1(...) __riscv_vlseg5e64ff_v_i64m1(__VA_ARGS__) -#define vlseg6e64ff_v_i64m1(...) __riscv_vlseg6e64ff_v_i64m1(__VA_ARGS__) -#define vlseg7e64ff_v_i64m1(...) __riscv_vlseg7e64ff_v_i64m1(__VA_ARGS__) -#define vlseg8e64ff_v_i64m1(...) __riscv_vlseg8e64ff_v_i64m1(__VA_ARGS__) -#define vlseg2e64ff_v_i64m2(...) __riscv_vlseg2e64ff_v_i64m2(__VA_ARGS__) -#define vlseg3e64ff_v_i64m2(...) __riscv_vlseg3e64ff_v_i64m2(__VA_ARGS__) -#define vlseg4e64ff_v_i64m2(...) __riscv_vlseg4e64ff_v_i64m2(__VA_ARGS__) -#define vlseg2e64ff_v_i64m4(...) __riscv_vlseg2e64ff_v_i64m4(__VA_ARGS__) -#define vlseg2e8_v_u8mf8(...) __riscv_vlseg2e8_v_u8mf8(__VA_ARGS__) -#define vlseg3e8_v_u8mf8(...) __riscv_vlseg3e8_v_u8mf8(__VA_ARGS__) -#define vlseg4e8_v_u8mf8(...) __riscv_vlseg4e8_v_u8mf8(__VA_ARGS__) -#define vlseg5e8_v_u8mf8(...) __riscv_vlseg5e8_v_u8mf8(__VA_ARGS__) -#define vlseg6e8_v_u8mf8(...) __riscv_vlseg6e8_v_u8mf8(__VA_ARGS__) -#define vlseg7e8_v_u8mf8(...) __riscv_vlseg7e8_v_u8mf8(__VA_ARGS__) -#define vlseg8e8_v_u8mf8(...) __riscv_vlseg8e8_v_u8mf8(__VA_ARGS__) -#define vlseg2e8_v_u8mf4(...) __riscv_vlseg2e8_v_u8mf4(__VA_ARGS__) -#define vlseg3e8_v_u8mf4(...) __riscv_vlseg3e8_v_u8mf4(__VA_ARGS__) -#define vlseg4e8_v_u8mf4(...) __riscv_vlseg4e8_v_u8mf4(__VA_ARGS__) -#define vlseg5e8_v_u8mf4(...) __riscv_vlseg5e8_v_u8mf4(__VA_ARGS__) -#define vlseg6e8_v_u8mf4(...) __riscv_vlseg6e8_v_u8mf4(__VA_ARGS__) -#define vlseg7e8_v_u8mf4(...) __riscv_vlseg7e8_v_u8mf4(__VA_ARGS__) -#define vlseg8e8_v_u8mf4(...) __riscv_vlseg8e8_v_u8mf4(__VA_ARGS__) -#define vlseg2e8_v_u8mf2(...) __riscv_vlseg2e8_v_u8mf2(__VA_ARGS__) -#define vlseg3e8_v_u8mf2(...) __riscv_vlseg3e8_v_u8mf2(__VA_ARGS__) -#define vlseg4e8_v_u8mf2(...) __riscv_vlseg4e8_v_u8mf2(__VA_ARGS__) -#define vlseg5e8_v_u8mf2(...) __riscv_vlseg5e8_v_u8mf2(__VA_ARGS__) -#define vlseg6e8_v_u8mf2(...) __riscv_vlseg6e8_v_u8mf2(__VA_ARGS__) -#define vlseg7e8_v_u8mf2(...) __riscv_vlseg7e8_v_u8mf2(__VA_ARGS__) -#define vlseg8e8_v_u8mf2(...) __riscv_vlseg8e8_v_u8mf2(__VA_ARGS__) -#define vlseg2e8_v_u8m1(...) __riscv_vlseg2e8_v_u8m1(__VA_ARGS__) -#define vlseg3e8_v_u8m1(...) __riscv_vlseg3e8_v_u8m1(__VA_ARGS__) -#define vlseg4e8_v_u8m1(...) __riscv_vlseg4e8_v_u8m1(__VA_ARGS__) -#define vlseg5e8_v_u8m1(...) __riscv_vlseg5e8_v_u8m1(__VA_ARGS__) -#define vlseg6e8_v_u8m1(...) __riscv_vlseg6e8_v_u8m1(__VA_ARGS__) -#define vlseg7e8_v_u8m1(...) __riscv_vlseg7e8_v_u8m1(__VA_ARGS__) -#define vlseg8e8_v_u8m1(...) __riscv_vlseg8e8_v_u8m1(__VA_ARGS__) -#define vlseg2e8_v_u8m2(...) __riscv_vlseg2e8_v_u8m2(__VA_ARGS__) -#define vlseg3e8_v_u8m2(...) __riscv_vlseg3e8_v_u8m2(__VA_ARGS__) -#define vlseg4e8_v_u8m2(...) __riscv_vlseg4e8_v_u8m2(__VA_ARGS__) -#define vlseg2e8_v_u8m4(...) __riscv_vlseg2e8_v_u8m4(__VA_ARGS__) -#define vlseg2e16_v_u16mf4(...) __riscv_vlseg2e16_v_u16mf4(__VA_ARGS__) -#define vlseg3e16_v_u16mf4(...) __riscv_vlseg3e16_v_u16mf4(__VA_ARGS__) -#define vlseg4e16_v_u16mf4(...) __riscv_vlseg4e16_v_u16mf4(__VA_ARGS__) -#define vlseg5e16_v_u16mf4(...) __riscv_vlseg5e16_v_u16mf4(__VA_ARGS__) -#define vlseg6e16_v_u16mf4(...) __riscv_vlseg6e16_v_u16mf4(__VA_ARGS__) -#define vlseg7e16_v_u16mf4(...) __riscv_vlseg7e16_v_u16mf4(__VA_ARGS__) -#define vlseg8e16_v_u16mf4(...) __riscv_vlseg8e16_v_u16mf4(__VA_ARGS__) -#define vlseg2e16_v_u16mf2(...) __riscv_vlseg2e16_v_u16mf2(__VA_ARGS__) -#define vlseg3e16_v_u16mf2(...) __riscv_vlseg3e16_v_u16mf2(__VA_ARGS__) -#define vlseg4e16_v_u16mf2(...) __riscv_vlseg4e16_v_u16mf2(__VA_ARGS__) -#define vlseg5e16_v_u16mf2(...) __riscv_vlseg5e16_v_u16mf2(__VA_ARGS__) -#define vlseg6e16_v_u16mf2(...) __riscv_vlseg6e16_v_u16mf2(__VA_ARGS__) -#define vlseg7e16_v_u16mf2(...) __riscv_vlseg7e16_v_u16mf2(__VA_ARGS__) -#define vlseg8e16_v_u16mf2(...) __riscv_vlseg8e16_v_u16mf2(__VA_ARGS__) -#define vlseg2e16_v_u16m1(...) __riscv_vlseg2e16_v_u16m1(__VA_ARGS__) -#define vlseg3e16_v_u16m1(...) __riscv_vlseg3e16_v_u16m1(__VA_ARGS__) -#define vlseg4e16_v_u16m1(...) __riscv_vlseg4e16_v_u16m1(__VA_ARGS__) -#define vlseg5e16_v_u16m1(...) __riscv_vlseg5e16_v_u16m1(__VA_ARGS__) -#define vlseg6e16_v_u16m1(...) __riscv_vlseg6e16_v_u16m1(__VA_ARGS__) -#define vlseg7e16_v_u16m1(...) __riscv_vlseg7e16_v_u16m1(__VA_ARGS__) -#define vlseg8e16_v_u16m1(...) __riscv_vlseg8e16_v_u16m1(__VA_ARGS__) -#define vlseg2e16_v_u16m2(...) __riscv_vlseg2e16_v_u16m2(__VA_ARGS__) -#define vlseg3e16_v_u16m2(...) __riscv_vlseg3e16_v_u16m2(__VA_ARGS__) -#define vlseg4e16_v_u16m2(...) __riscv_vlseg4e16_v_u16m2(__VA_ARGS__) -#define vlseg2e16_v_u16m4(...) __riscv_vlseg2e16_v_u16m4(__VA_ARGS__) -#define vlseg2e32_v_u32mf2(...) __riscv_vlseg2e32_v_u32mf2(__VA_ARGS__) -#define vlseg3e32_v_u32mf2(...) __riscv_vlseg3e32_v_u32mf2(__VA_ARGS__) -#define vlseg4e32_v_u32mf2(...) __riscv_vlseg4e32_v_u32mf2(__VA_ARGS__) -#define vlseg5e32_v_u32mf2(...) __riscv_vlseg5e32_v_u32mf2(__VA_ARGS__) -#define vlseg6e32_v_u32mf2(...) __riscv_vlseg6e32_v_u32mf2(__VA_ARGS__) -#define vlseg7e32_v_u32mf2(...) __riscv_vlseg7e32_v_u32mf2(__VA_ARGS__) -#define vlseg8e32_v_u32mf2(...) __riscv_vlseg8e32_v_u32mf2(__VA_ARGS__) -#define vlseg2e32_v_u32m1(...) __riscv_vlseg2e32_v_u32m1(__VA_ARGS__) -#define vlseg3e32_v_u32m1(...) __riscv_vlseg3e32_v_u32m1(__VA_ARGS__) -#define vlseg4e32_v_u32m1(...) __riscv_vlseg4e32_v_u32m1(__VA_ARGS__) -#define vlseg5e32_v_u32m1(...) __riscv_vlseg5e32_v_u32m1(__VA_ARGS__) -#define vlseg6e32_v_u32m1(...) __riscv_vlseg6e32_v_u32m1(__VA_ARGS__) -#define vlseg7e32_v_u32m1(...) __riscv_vlseg7e32_v_u32m1(__VA_ARGS__) -#define vlseg8e32_v_u32m1(...) __riscv_vlseg8e32_v_u32m1(__VA_ARGS__) -#define vlseg2e32_v_u32m2(...) __riscv_vlseg2e32_v_u32m2(__VA_ARGS__) -#define vlseg3e32_v_u32m2(...) __riscv_vlseg3e32_v_u32m2(__VA_ARGS__) -#define vlseg4e32_v_u32m2(...) __riscv_vlseg4e32_v_u32m2(__VA_ARGS__) -#define vlseg2e32_v_u32m4(...) __riscv_vlseg2e32_v_u32m4(__VA_ARGS__) -#define vlseg2e64_v_u64m1(...) __riscv_vlseg2e64_v_u64m1(__VA_ARGS__) -#define vlseg3e64_v_u64m1(...) __riscv_vlseg3e64_v_u64m1(__VA_ARGS__) -#define vlseg4e64_v_u64m1(...) __riscv_vlseg4e64_v_u64m1(__VA_ARGS__) -#define vlseg5e64_v_u64m1(...) __riscv_vlseg5e64_v_u64m1(__VA_ARGS__) -#define vlseg6e64_v_u64m1(...) __riscv_vlseg6e64_v_u64m1(__VA_ARGS__) -#define vlseg7e64_v_u64m1(...) __riscv_vlseg7e64_v_u64m1(__VA_ARGS__) -#define vlseg8e64_v_u64m1(...) __riscv_vlseg8e64_v_u64m1(__VA_ARGS__) -#define vlseg2e64_v_u64m2(...) __riscv_vlseg2e64_v_u64m2(__VA_ARGS__) -#define vlseg3e64_v_u64m2(...) __riscv_vlseg3e64_v_u64m2(__VA_ARGS__) -#define vlseg4e64_v_u64m2(...) __riscv_vlseg4e64_v_u64m2(__VA_ARGS__) -#define vlseg2e64_v_u64m4(...) __riscv_vlseg2e64_v_u64m4(__VA_ARGS__) -#define vlseg2e8ff_v_u8mf8(...) __riscv_vlseg2e8ff_v_u8mf8(__VA_ARGS__) -#define vlseg3e8ff_v_u8mf8(...) __riscv_vlseg3e8ff_v_u8mf8(__VA_ARGS__) -#define vlseg4e8ff_v_u8mf8(...) __riscv_vlseg4e8ff_v_u8mf8(__VA_ARGS__) -#define vlseg5e8ff_v_u8mf8(...) __riscv_vlseg5e8ff_v_u8mf8(__VA_ARGS__) -#define vlseg6e8ff_v_u8mf8(...) __riscv_vlseg6e8ff_v_u8mf8(__VA_ARGS__) -#define vlseg7e8ff_v_u8mf8(...) __riscv_vlseg7e8ff_v_u8mf8(__VA_ARGS__) -#define vlseg8e8ff_v_u8mf8(...) __riscv_vlseg8e8ff_v_u8mf8(__VA_ARGS__) -#define vlseg2e8ff_v_u8mf4(...) __riscv_vlseg2e8ff_v_u8mf4(__VA_ARGS__) -#define vlseg3e8ff_v_u8mf4(...) __riscv_vlseg3e8ff_v_u8mf4(__VA_ARGS__) -#define vlseg4e8ff_v_u8mf4(...) __riscv_vlseg4e8ff_v_u8mf4(__VA_ARGS__) -#define vlseg5e8ff_v_u8mf4(...) __riscv_vlseg5e8ff_v_u8mf4(__VA_ARGS__) -#define vlseg6e8ff_v_u8mf4(...) __riscv_vlseg6e8ff_v_u8mf4(__VA_ARGS__) -#define vlseg7e8ff_v_u8mf4(...) __riscv_vlseg7e8ff_v_u8mf4(__VA_ARGS__) -#define vlseg8e8ff_v_u8mf4(...) __riscv_vlseg8e8ff_v_u8mf4(__VA_ARGS__) -#define vlseg2e8ff_v_u8mf2(...) __riscv_vlseg2e8ff_v_u8mf2(__VA_ARGS__) -#define vlseg3e8ff_v_u8mf2(...) __riscv_vlseg3e8ff_v_u8mf2(__VA_ARGS__) -#define vlseg4e8ff_v_u8mf2(...) __riscv_vlseg4e8ff_v_u8mf2(__VA_ARGS__) -#define vlseg5e8ff_v_u8mf2(...) __riscv_vlseg5e8ff_v_u8mf2(__VA_ARGS__) -#define vlseg6e8ff_v_u8mf2(...) __riscv_vlseg6e8ff_v_u8mf2(__VA_ARGS__) -#define vlseg7e8ff_v_u8mf2(...) __riscv_vlseg7e8ff_v_u8mf2(__VA_ARGS__) -#define vlseg8e8ff_v_u8mf2(...) __riscv_vlseg8e8ff_v_u8mf2(__VA_ARGS__) -#define vlseg2e8ff_v_u8m1(...) __riscv_vlseg2e8ff_v_u8m1(__VA_ARGS__) -#define vlseg3e8ff_v_u8m1(...) __riscv_vlseg3e8ff_v_u8m1(__VA_ARGS__) -#define vlseg4e8ff_v_u8m1(...) __riscv_vlseg4e8ff_v_u8m1(__VA_ARGS__) -#define vlseg5e8ff_v_u8m1(...) __riscv_vlseg5e8ff_v_u8m1(__VA_ARGS__) -#define vlseg6e8ff_v_u8m1(...) __riscv_vlseg6e8ff_v_u8m1(__VA_ARGS__) -#define vlseg7e8ff_v_u8m1(...) __riscv_vlseg7e8ff_v_u8m1(__VA_ARGS__) -#define vlseg8e8ff_v_u8m1(...) __riscv_vlseg8e8ff_v_u8m1(__VA_ARGS__) -#define vlseg2e8ff_v_u8m2(...) __riscv_vlseg2e8ff_v_u8m2(__VA_ARGS__) -#define vlseg3e8ff_v_u8m2(...) __riscv_vlseg3e8ff_v_u8m2(__VA_ARGS__) -#define vlseg4e8ff_v_u8m2(...) __riscv_vlseg4e8ff_v_u8m2(__VA_ARGS__) -#define vlseg2e8ff_v_u8m4(...) __riscv_vlseg2e8ff_v_u8m4(__VA_ARGS__) -#define vlseg2e16ff_v_u16mf4(...) __riscv_vlseg2e16ff_v_u16mf4(__VA_ARGS__) -#define vlseg3e16ff_v_u16mf4(...) __riscv_vlseg3e16ff_v_u16mf4(__VA_ARGS__) -#define vlseg4e16ff_v_u16mf4(...) __riscv_vlseg4e16ff_v_u16mf4(__VA_ARGS__) -#define vlseg5e16ff_v_u16mf4(...) __riscv_vlseg5e16ff_v_u16mf4(__VA_ARGS__) -#define vlseg6e16ff_v_u16mf4(...) __riscv_vlseg6e16ff_v_u16mf4(__VA_ARGS__) -#define vlseg7e16ff_v_u16mf4(...) __riscv_vlseg7e16ff_v_u16mf4(__VA_ARGS__) -#define vlseg8e16ff_v_u16mf4(...) __riscv_vlseg8e16ff_v_u16mf4(__VA_ARGS__) -#define vlseg2e16ff_v_u16mf2(...) __riscv_vlseg2e16ff_v_u16mf2(__VA_ARGS__) -#define vlseg3e16ff_v_u16mf2(...) __riscv_vlseg3e16ff_v_u16mf2(__VA_ARGS__) -#define vlseg4e16ff_v_u16mf2(...) __riscv_vlseg4e16ff_v_u16mf2(__VA_ARGS__) -#define vlseg5e16ff_v_u16mf2(...) __riscv_vlseg5e16ff_v_u16mf2(__VA_ARGS__) -#define vlseg6e16ff_v_u16mf2(...) __riscv_vlseg6e16ff_v_u16mf2(__VA_ARGS__) -#define vlseg7e16ff_v_u16mf2(...) __riscv_vlseg7e16ff_v_u16mf2(__VA_ARGS__) -#define vlseg8e16ff_v_u16mf2(...) __riscv_vlseg8e16ff_v_u16mf2(__VA_ARGS__) -#define vlseg2e16ff_v_u16m1(...) __riscv_vlseg2e16ff_v_u16m1(__VA_ARGS__) -#define vlseg3e16ff_v_u16m1(...) __riscv_vlseg3e16ff_v_u16m1(__VA_ARGS__) -#define vlseg4e16ff_v_u16m1(...) __riscv_vlseg4e16ff_v_u16m1(__VA_ARGS__) -#define vlseg5e16ff_v_u16m1(...) __riscv_vlseg5e16ff_v_u16m1(__VA_ARGS__) -#define vlseg6e16ff_v_u16m1(...) __riscv_vlseg6e16ff_v_u16m1(__VA_ARGS__) -#define vlseg7e16ff_v_u16m1(...) __riscv_vlseg7e16ff_v_u16m1(__VA_ARGS__) -#define vlseg8e16ff_v_u16m1(...) __riscv_vlseg8e16ff_v_u16m1(__VA_ARGS__) -#define vlseg2e16ff_v_u16m2(...) __riscv_vlseg2e16ff_v_u16m2(__VA_ARGS__) -#define vlseg3e16ff_v_u16m2(...) __riscv_vlseg3e16ff_v_u16m2(__VA_ARGS__) -#define vlseg4e16ff_v_u16m2(...) __riscv_vlseg4e16ff_v_u16m2(__VA_ARGS__) -#define vlseg2e16ff_v_u16m4(...) __riscv_vlseg2e16ff_v_u16m4(__VA_ARGS__) -#define vlseg2e32ff_v_u32mf2(...) __riscv_vlseg2e32ff_v_u32mf2(__VA_ARGS__) -#define vlseg3e32ff_v_u32mf2(...) __riscv_vlseg3e32ff_v_u32mf2(__VA_ARGS__) -#define vlseg4e32ff_v_u32mf2(...) __riscv_vlseg4e32ff_v_u32mf2(__VA_ARGS__) -#define vlseg5e32ff_v_u32mf2(...) __riscv_vlseg5e32ff_v_u32mf2(__VA_ARGS__) -#define vlseg6e32ff_v_u32mf2(...) __riscv_vlseg6e32ff_v_u32mf2(__VA_ARGS__) -#define vlseg7e32ff_v_u32mf2(...) __riscv_vlseg7e32ff_v_u32mf2(__VA_ARGS__) -#define vlseg8e32ff_v_u32mf2(...) __riscv_vlseg8e32ff_v_u32mf2(__VA_ARGS__) -#define vlseg2e32ff_v_u32m1(...) __riscv_vlseg2e32ff_v_u32m1(__VA_ARGS__) -#define vlseg3e32ff_v_u32m1(...) __riscv_vlseg3e32ff_v_u32m1(__VA_ARGS__) -#define vlseg4e32ff_v_u32m1(...) __riscv_vlseg4e32ff_v_u32m1(__VA_ARGS__) -#define vlseg5e32ff_v_u32m1(...) __riscv_vlseg5e32ff_v_u32m1(__VA_ARGS__) -#define vlseg6e32ff_v_u32m1(...) __riscv_vlseg6e32ff_v_u32m1(__VA_ARGS__) -#define vlseg7e32ff_v_u32m1(...) __riscv_vlseg7e32ff_v_u32m1(__VA_ARGS__) -#define vlseg8e32ff_v_u32m1(...) __riscv_vlseg8e32ff_v_u32m1(__VA_ARGS__) -#define vlseg2e32ff_v_u32m2(...) __riscv_vlseg2e32ff_v_u32m2(__VA_ARGS__) -#define vlseg3e32ff_v_u32m2(...) __riscv_vlseg3e32ff_v_u32m2(__VA_ARGS__) -#define vlseg4e32ff_v_u32m2(...) __riscv_vlseg4e32ff_v_u32m2(__VA_ARGS__) -#define vlseg2e32ff_v_u32m4(...) __riscv_vlseg2e32ff_v_u32m4(__VA_ARGS__) -#define vlseg2e64ff_v_u64m1(...) __riscv_vlseg2e64ff_v_u64m1(__VA_ARGS__) -#define vlseg3e64ff_v_u64m1(...) __riscv_vlseg3e64ff_v_u64m1(__VA_ARGS__) -#define vlseg4e64ff_v_u64m1(...) __riscv_vlseg4e64ff_v_u64m1(__VA_ARGS__) -#define vlseg5e64ff_v_u64m1(...) __riscv_vlseg5e64ff_v_u64m1(__VA_ARGS__) -#define vlseg6e64ff_v_u64m1(...) __riscv_vlseg6e64ff_v_u64m1(__VA_ARGS__) -#define vlseg7e64ff_v_u64m1(...) __riscv_vlseg7e64ff_v_u64m1(__VA_ARGS__) -#define vlseg8e64ff_v_u64m1(...) __riscv_vlseg8e64ff_v_u64m1(__VA_ARGS__) -#define vlseg2e64ff_v_u64m2(...) __riscv_vlseg2e64ff_v_u64m2(__VA_ARGS__) -#define vlseg3e64ff_v_u64m2(...) __riscv_vlseg3e64ff_v_u64m2(__VA_ARGS__) -#define vlseg4e64ff_v_u64m2(...) __riscv_vlseg4e64ff_v_u64m2(__VA_ARGS__) -#define vlseg2e64ff_v_u64m4(...) __riscv_vlseg2e64ff_v_u64m4(__VA_ARGS__) -// masked functions -#define vlseg2e16_v_f16mf4_m(...) __riscv_vlseg2e16_v_f16mf4_tumu(__VA_ARGS__) -#define vlseg3e16_v_f16mf4_m(...) __riscv_vlseg3e16_v_f16mf4_tumu(__VA_ARGS__) -#define vlseg4e16_v_f16mf4_m(...) __riscv_vlseg4e16_v_f16mf4_tumu(__VA_ARGS__) -#define vlseg5e16_v_f16mf4_m(...) __riscv_vlseg5e16_v_f16mf4_tumu(__VA_ARGS__) -#define vlseg6e16_v_f16mf4_m(...) __riscv_vlseg6e16_v_f16mf4_tumu(__VA_ARGS__) -#define vlseg7e16_v_f16mf4_m(...) __riscv_vlseg7e16_v_f16mf4_tumu(__VA_ARGS__) -#define vlseg8e16_v_f16mf4_m(...) __riscv_vlseg8e16_v_f16mf4_tumu(__VA_ARGS__) -#define vlseg2e16_v_f16mf2_m(...) __riscv_vlseg2e16_v_f16mf2_tumu(__VA_ARGS__) -#define vlseg3e16_v_f16mf2_m(...) __riscv_vlseg3e16_v_f16mf2_tumu(__VA_ARGS__) -#define vlseg4e16_v_f16mf2_m(...) __riscv_vlseg4e16_v_f16mf2_tumu(__VA_ARGS__) -#define vlseg5e16_v_f16mf2_m(...) __riscv_vlseg5e16_v_f16mf2_tumu(__VA_ARGS__) -#define vlseg6e16_v_f16mf2_m(...) __riscv_vlseg6e16_v_f16mf2_tumu(__VA_ARGS__) -#define vlseg7e16_v_f16mf2_m(...) __riscv_vlseg7e16_v_f16mf2_tumu(__VA_ARGS__) -#define vlseg8e16_v_f16mf2_m(...) __riscv_vlseg8e16_v_f16mf2_tumu(__VA_ARGS__) -#define vlseg2e16_v_f16m1_m(...) __riscv_vlseg2e16_v_f16m1_tumu(__VA_ARGS__) -#define vlseg3e16_v_f16m1_m(...) __riscv_vlseg3e16_v_f16m1_tumu(__VA_ARGS__) -#define vlseg4e16_v_f16m1_m(...) __riscv_vlseg4e16_v_f16m1_tumu(__VA_ARGS__) -#define vlseg5e16_v_f16m1_m(...) __riscv_vlseg5e16_v_f16m1_tumu(__VA_ARGS__) -#define vlseg6e16_v_f16m1_m(...) __riscv_vlseg6e16_v_f16m1_tumu(__VA_ARGS__) -#define vlseg7e16_v_f16m1_m(...) __riscv_vlseg7e16_v_f16m1_tumu(__VA_ARGS__) -#define vlseg8e16_v_f16m1_m(...) __riscv_vlseg8e16_v_f16m1_tumu(__VA_ARGS__) -#define vlseg2e16_v_f16m2_m(...) __riscv_vlseg2e16_v_f16m2_tumu(__VA_ARGS__) -#define vlseg3e16_v_f16m2_m(...) __riscv_vlseg3e16_v_f16m2_tumu(__VA_ARGS__) -#define vlseg4e16_v_f16m2_m(...) __riscv_vlseg4e16_v_f16m2_tumu(__VA_ARGS__) -#define vlseg2e16_v_f16m4_m(...) __riscv_vlseg2e16_v_f16m4_tumu(__VA_ARGS__) -#define vlseg2e32_v_f32mf2_m(...) __riscv_vlseg2e32_v_f32mf2_tumu(__VA_ARGS__) -#define vlseg3e32_v_f32mf2_m(...) __riscv_vlseg3e32_v_f32mf2_tumu(__VA_ARGS__) -#define vlseg4e32_v_f32mf2_m(...) __riscv_vlseg4e32_v_f32mf2_tumu(__VA_ARGS__) -#define vlseg5e32_v_f32mf2_m(...) __riscv_vlseg5e32_v_f32mf2_tumu(__VA_ARGS__) -#define vlseg6e32_v_f32mf2_m(...) __riscv_vlseg6e32_v_f32mf2_tumu(__VA_ARGS__) -#define vlseg7e32_v_f32mf2_m(...) __riscv_vlseg7e32_v_f32mf2_tumu(__VA_ARGS__) -#define vlseg8e32_v_f32mf2_m(...) __riscv_vlseg8e32_v_f32mf2_tumu(__VA_ARGS__) -#define vlseg2e32_v_f32m1_m(...) __riscv_vlseg2e32_v_f32m1_tumu(__VA_ARGS__) -#define vlseg3e32_v_f32m1_m(...) __riscv_vlseg3e32_v_f32m1_tumu(__VA_ARGS__) -#define vlseg4e32_v_f32m1_m(...) __riscv_vlseg4e32_v_f32m1_tumu(__VA_ARGS__) -#define vlseg5e32_v_f32m1_m(...) __riscv_vlseg5e32_v_f32m1_tumu(__VA_ARGS__) -#define vlseg6e32_v_f32m1_m(...) __riscv_vlseg6e32_v_f32m1_tumu(__VA_ARGS__) -#define vlseg7e32_v_f32m1_m(...) __riscv_vlseg7e32_v_f32m1_tumu(__VA_ARGS__) -#define vlseg8e32_v_f32m1_m(...) __riscv_vlseg8e32_v_f32m1_tumu(__VA_ARGS__) -#define vlseg2e32_v_f32m2_m(...) __riscv_vlseg2e32_v_f32m2_tumu(__VA_ARGS__) -#define vlseg3e32_v_f32m2_m(...) __riscv_vlseg3e32_v_f32m2_tumu(__VA_ARGS__) -#define vlseg4e32_v_f32m2_m(...) __riscv_vlseg4e32_v_f32m2_tumu(__VA_ARGS__) -#define vlseg2e32_v_f32m4_m(...) __riscv_vlseg2e32_v_f32m4_tumu(__VA_ARGS__) -#define vlseg2e64_v_f64m1_m(...) __riscv_vlseg2e64_v_f64m1_tumu(__VA_ARGS__) -#define vlseg3e64_v_f64m1_m(...) __riscv_vlseg3e64_v_f64m1_tumu(__VA_ARGS__) -#define vlseg4e64_v_f64m1_m(...) __riscv_vlseg4e64_v_f64m1_tumu(__VA_ARGS__) -#define vlseg5e64_v_f64m1_m(...) __riscv_vlseg5e64_v_f64m1_tumu(__VA_ARGS__) -#define vlseg6e64_v_f64m1_m(...) __riscv_vlseg6e64_v_f64m1_tumu(__VA_ARGS__) -#define vlseg7e64_v_f64m1_m(...) __riscv_vlseg7e64_v_f64m1_tumu(__VA_ARGS__) -#define vlseg8e64_v_f64m1_m(...) __riscv_vlseg8e64_v_f64m1_tumu(__VA_ARGS__) -#define vlseg2e64_v_f64m2_m(...) __riscv_vlseg2e64_v_f64m2_tumu(__VA_ARGS__) -#define vlseg3e64_v_f64m2_m(...) __riscv_vlseg3e64_v_f64m2_tumu(__VA_ARGS__) -#define vlseg4e64_v_f64m2_m(...) __riscv_vlseg4e64_v_f64m2_tumu(__VA_ARGS__) -#define vlseg2e64_v_f64m4_m(...) __riscv_vlseg2e64_v_f64m4_tumu(__VA_ARGS__) -#define vlseg2e16ff_v_f16mf4_m(...) __riscv_vlseg2e16ff_v_f16mf4_tumu(__VA_ARGS__) -#define vlseg3e16ff_v_f16mf4_m(...) __riscv_vlseg3e16ff_v_f16mf4_tumu(__VA_ARGS__) -#define vlseg4e16ff_v_f16mf4_m(...) __riscv_vlseg4e16ff_v_f16mf4_tumu(__VA_ARGS__) -#define vlseg5e16ff_v_f16mf4_m(...) __riscv_vlseg5e16ff_v_f16mf4_tumu(__VA_ARGS__) -#define vlseg6e16ff_v_f16mf4_m(...) __riscv_vlseg6e16ff_v_f16mf4_tumu(__VA_ARGS__) -#define vlseg7e16ff_v_f16mf4_m(...) __riscv_vlseg7e16ff_v_f16mf4_tumu(__VA_ARGS__) -#define vlseg8e16ff_v_f16mf4_m(...) __riscv_vlseg8e16ff_v_f16mf4_tumu(__VA_ARGS__) -#define vlseg2e16ff_v_f16mf2_m(...) __riscv_vlseg2e16ff_v_f16mf2_tumu(__VA_ARGS__) -#define vlseg3e16ff_v_f16mf2_m(...) __riscv_vlseg3e16ff_v_f16mf2_tumu(__VA_ARGS__) -#define vlseg4e16ff_v_f16mf2_m(...) __riscv_vlseg4e16ff_v_f16mf2_tumu(__VA_ARGS__) -#define vlseg5e16ff_v_f16mf2_m(...) __riscv_vlseg5e16ff_v_f16mf2_tumu(__VA_ARGS__) -#define vlseg6e16ff_v_f16mf2_m(...) __riscv_vlseg6e16ff_v_f16mf2_tumu(__VA_ARGS__) -#define vlseg7e16ff_v_f16mf2_m(...) __riscv_vlseg7e16ff_v_f16mf2_tumu(__VA_ARGS__) -#define vlseg8e16ff_v_f16mf2_m(...) __riscv_vlseg8e16ff_v_f16mf2_tumu(__VA_ARGS__) -#define vlseg2e16ff_v_f16m1_m(...) __riscv_vlseg2e16ff_v_f16m1_tumu(__VA_ARGS__) -#define vlseg3e16ff_v_f16m1_m(...) __riscv_vlseg3e16ff_v_f16m1_tumu(__VA_ARGS__) -#define vlseg4e16ff_v_f16m1_m(...) __riscv_vlseg4e16ff_v_f16m1_tumu(__VA_ARGS__) -#define vlseg5e16ff_v_f16m1_m(...) __riscv_vlseg5e16ff_v_f16m1_tumu(__VA_ARGS__) -#define vlseg6e16ff_v_f16m1_m(...) __riscv_vlseg6e16ff_v_f16m1_tumu(__VA_ARGS__) -#define vlseg7e16ff_v_f16m1_m(...) __riscv_vlseg7e16ff_v_f16m1_tumu(__VA_ARGS__) -#define vlseg8e16ff_v_f16m1_m(...) __riscv_vlseg8e16ff_v_f16m1_tumu(__VA_ARGS__) -#define vlseg2e16ff_v_f16m2_m(...) __riscv_vlseg2e16ff_v_f16m2_tumu(__VA_ARGS__) -#define vlseg3e16ff_v_f16m2_m(...) __riscv_vlseg3e16ff_v_f16m2_tumu(__VA_ARGS__) -#define vlseg4e16ff_v_f16m2_m(...) __riscv_vlseg4e16ff_v_f16m2_tumu(__VA_ARGS__) -#define vlseg2e16ff_v_f16m4_m(...) __riscv_vlseg2e16ff_v_f16m4_tumu(__VA_ARGS__) -#define vlseg2e32ff_v_f32mf2_m(...) __riscv_vlseg2e32ff_v_f32mf2_tumu(__VA_ARGS__) -#define vlseg3e32ff_v_f32mf2_m(...) __riscv_vlseg3e32ff_v_f32mf2_tumu(__VA_ARGS__) -#define vlseg4e32ff_v_f32mf2_m(...) __riscv_vlseg4e32ff_v_f32mf2_tumu(__VA_ARGS__) -#define vlseg5e32ff_v_f32mf2_m(...) __riscv_vlseg5e32ff_v_f32mf2_tumu(__VA_ARGS__) -#define vlseg6e32ff_v_f32mf2_m(...) __riscv_vlseg6e32ff_v_f32mf2_tumu(__VA_ARGS__) -#define vlseg7e32ff_v_f32mf2_m(...) __riscv_vlseg7e32ff_v_f32mf2_tumu(__VA_ARGS__) -#define vlseg8e32ff_v_f32mf2_m(...) __riscv_vlseg8e32ff_v_f32mf2_tumu(__VA_ARGS__) -#define vlseg2e32ff_v_f32m1_m(...) __riscv_vlseg2e32ff_v_f32m1_tumu(__VA_ARGS__) -#define vlseg3e32ff_v_f32m1_m(...) __riscv_vlseg3e32ff_v_f32m1_tumu(__VA_ARGS__) -#define vlseg4e32ff_v_f32m1_m(...) __riscv_vlseg4e32ff_v_f32m1_tumu(__VA_ARGS__) -#define vlseg5e32ff_v_f32m1_m(...) __riscv_vlseg5e32ff_v_f32m1_tumu(__VA_ARGS__) -#define vlseg6e32ff_v_f32m1_m(...) __riscv_vlseg6e32ff_v_f32m1_tumu(__VA_ARGS__) -#define vlseg7e32ff_v_f32m1_m(...) __riscv_vlseg7e32ff_v_f32m1_tumu(__VA_ARGS__) -#define vlseg8e32ff_v_f32m1_m(...) __riscv_vlseg8e32ff_v_f32m1_tumu(__VA_ARGS__) -#define vlseg2e32ff_v_f32m2_m(...) __riscv_vlseg2e32ff_v_f32m2_tumu(__VA_ARGS__) -#define vlseg3e32ff_v_f32m2_m(...) __riscv_vlseg3e32ff_v_f32m2_tumu(__VA_ARGS__) -#define vlseg4e32ff_v_f32m2_m(...) __riscv_vlseg4e32ff_v_f32m2_tumu(__VA_ARGS__) -#define vlseg2e32ff_v_f32m4_m(...) __riscv_vlseg2e32ff_v_f32m4_tumu(__VA_ARGS__) -#define vlseg2e64ff_v_f64m1_m(...) __riscv_vlseg2e64ff_v_f64m1_tumu(__VA_ARGS__) -#define vlseg3e64ff_v_f64m1_m(...) __riscv_vlseg3e64ff_v_f64m1_tumu(__VA_ARGS__) -#define vlseg4e64ff_v_f64m1_m(...) __riscv_vlseg4e64ff_v_f64m1_tumu(__VA_ARGS__) -#define vlseg5e64ff_v_f64m1_m(...) __riscv_vlseg5e64ff_v_f64m1_tumu(__VA_ARGS__) -#define vlseg6e64ff_v_f64m1_m(...) __riscv_vlseg6e64ff_v_f64m1_tumu(__VA_ARGS__) -#define vlseg7e64ff_v_f64m1_m(...) __riscv_vlseg7e64ff_v_f64m1_tumu(__VA_ARGS__) -#define vlseg8e64ff_v_f64m1_m(...) __riscv_vlseg8e64ff_v_f64m1_tumu(__VA_ARGS__) -#define vlseg2e64ff_v_f64m2_m(...) __riscv_vlseg2e64ff_v_f64m2_tumu(__VA_ARGS__) -#define vlseg3e64ff_v_f64m2_m(...) __riscv_vlseg3e64ff_v_f64m2_tumu(__VA_ARGS__) -#define vlseg4e64ff_v_f64m2_m(...) __riscv_vlseg4e64ff_v_f64m2_tumu(__VA_ARGS__) -#define vlseg2e64ff_v_f64m4_m(...) __riscv_vlseg2e64ff_v_f64m4_tumu(__VA_ARGS__) -#define vlseg2e8_v_i8mf8_m(...) __riscv_vlseg2e8_v_i8mf8_tumu(__VA_ARGS__) -#define vlseg3e8_v_i8mf8_m(...) __riscv_vlseg3e8_v_i8mf8_tumu(__VA_ARGS__) -#define vlseg4e8_v_i8mf8_m(...) __riscv_vlseg4e8_v_i8mf8_tumu(__VA_ARGS__) -#define vlseg5e8_v_i8mf8_m(...) __riscv_vlseg5e8_v_i8mf8_tumu(__VA_ARGS__) -#define vlseg6e8_v_i8mf8_m(...) __riscv_vlseg6e8_v_i8mf8_tumu(__VA_ARGS__) -#define vlseg7e8_v_i8mf8_m(...) __riscv_vlseg7e8_v_i8mf8_tumu(__VA_ARGS__) -#define vlseg8e8_v_i8mf8_m(...) __riscv_vlseg8e8_v_i8mf8_tumu(__VA_ARGS__) -#define vlseg2e8_v_i8mf4_m(...) __riscv_vlseg2e8_v_i8mf4_tumu(__VA_ARGS__) -#define vlseg3e8_v_i8mf4_m(...) __riscv_vlseg3e8_v_i8mf4_tumu(__VA_ARGS__) -#define vlseg4e8_v_i8mf4_m(...) __riscv_vlseg4e8_v_i8mf4_tumu(__VA_ARGS__) -#define vlseg5e8_v_i8mf4_m(...) __riscv_vlseg5e8_v_i8mf4_tumu(__VA_ARGS__) -#define vlseg6e8_v_i8mf4_m(...) __riscv_vlseg6e8_v_i8mf4_tumu(__VA_ARGS__) -#define vlseg7e8_v_i8mf4_m(...) __riscv_vlseg7e8_v_i8mf4_tumu(__VA_ARGS__) -#define vlseg8e8_v_i8mf4_m(...) __riscv_vlseg8e8_v_i8mf4_tumu(__VA_ARGS__) -#define vlseg2e8_v_i8mf2_m(...) __riscv_vlseg2e8_v_i8mf2_tumu(__VA_ARGS__) -#define vlseg3e8_v_i8mf2_m(...) __riscv_vlseg3e8_v_i8mf2_tumu(__VA_ARGS__) -#define vlseg4e8_v_i8mf2_m(...) __riscv_vlseg4e8_v_i8mf2_tumu(__VA_ARGS__) -#define vlseg5e8_v_i8mf2_m(...) __riscv_vlseg5e8_v_i8mf2_tumu(__VA_ARGS__) -#define vlseg6e8_v_i8mf2_m(...) __riscv_vlseg6e8_v_i8mf2_tumu(__VA_ARGS__) -#define vlseg7e8_v_i8mf2_m(...) __riscv_vlseg7e8_v_i8mf2_tumu(__VA_ARGS__) -#define vlseg8e8_v_i8mf2_m(...) __riscv_vlseg8e8_v_i8mf2_tumu(__VA_ARGS__) -#define vlseg2e8_v_i8m1_m(...) __riscv_vlseg2e8_v_i8m1_tumu(__VA_ARGS__) -#define vlseg3e8_v_i8m1_m(...) __riscv_vlseg3e8_v_i8m1_tumu(__VA_ARGS__) -#define vlseg4e8_v_i8m1_m(...) __riscv_vlseg4e8_v_i8m1_tumu(__VA_ARGS__) -#define vlseg5e8_v_i8m1_m(...) __riscv_vlseg5e8_v_i8m1_tumu(__VA_ARGS__) -#define vlseg6e8_v_i8m1_m(...) __riscv_vlseg6e8_v_i8m1_tumu(__VA_ARGS__) -#define vlseg7e8_v_i8m1_m(...) __riscv_vlseg7e8_v_i8m1_tumu(__VA_ARGS__) -#define vlseg8e8_v_i8m1_m(...) __riscv_vlseg8e8_v_i8m1_tumu(__VA_ARGS__) -#define vlseg2e8_v_i8m2_m(...) __riscv_vlseg2e8_v_i8m2_tumu(__VA_ARGS__) -#define vlseg3e8_v_i8m2_m(...) __riscv_vlseg3e8_v_i8m2_tumu(__VA_ARGS__) -#define vlseg4e8_v_i8m2_m(...) __riscv_vlseg4e8_v_i8m2_tumu(__VA_ARGS__) -#define vlseg2e8_v_i8m4_m(...) __riscv_vlseg2e8_v_i8m4_tumu(__VA_ARGS__) -#define vlseg2e16_v_i16mf4_m(...) __riscv_vlseg2e16_v_i16mf4_tumu(__VA_ARGS__) -#define vlseg3e16_v_i16mf4_m(...) __riscv_vlseg3e16_v_i16mf4_tumu(__VA_ARGS__) -#define vlseg4e16_v_i16mf4_m(...) __riscv_vlseg4e16_v_i16mf4_tumu(__VA_ARGS__) -#define vlseg5e16_v_i16mf4_m(...) __riscv_vlseg5e16_v_i16mf4_tumu(__VA_ARGS__) -#define vlseg6e16_v_i16mf4_m(...) __riscv_vlseg6e16_v_i16mf4_tumu(__VA_ARGS__) -#define vlseg7e16_v_i16mf4_m(...) __riscv_vlseg7e16_v_i16mf4_tumu(__VA_ARGS__) -#define vlseg8e16_v_i16mf4_m(...) __riscv_vlseg8e16_v_i16mf4_tumu(__VA_ARGS__) -#define vlseg2e16_v_i16mf2_m(...) __riscv_vlseg2e16_v_i16mf2_tumu(__VA_ARGS__) -#define vlseg3e16_v_i16mf2_m(...) __riscv_vlseg3e16_v_i16mf2_tumu(__VA_ARGS__) -#define vlseg4e16_v_i16mf2_m(...) __riscv_vlseg4e16_v_i16mf2_tumu(__VA_ARGS__) -#define vlseg5e16_v_i16mf2_m(...) __riscv_vlseg5e16_v_i16mf2_tumu(__VA_ARGS__) -#define vlseg6e16_v_i16mf2_m(...) __riscv_vlseg6e16_v_i16mf2_tumu(__VA_ARGS__) -#define vlseg7e16_v_i16mf2_m(...) __riscv_vlseg7e16_v_i16mf2_tumu(__VA_ARGS__) -#define vlseg8e16_v_i16mf2_m(...) __riscv_vlseg8e16_v_i16mf2_tumu(__VA_ARGS__) -#define vlseg2e16_v_i16m1_m(...) __riscv_vlseg2e16_v_i16m1_tumu(__VA_ARGS__) -#define vlseg3e16_v_i16m1_m(...) __riscv_vlseg3e16_v_i16m1_tumu(__VA_ARGS__) -#define vlseg4e16_v_i16m1_m(...) __riscv_vlseg4e16_v_i16m1_tumu(__VA_ARGS__) -#define vlseg5e16_v_i16m1_m(...) __riscv_vlseg5e16_v_i16m1_tumu(__VA_ARGS__) -#define vlseg6e16_v_i16m1_m(...) __riscv_vlseg6e16_v_i16m1_tumu(__VA_ARGS__) -#define vlseg7e16_v_i16m1_m(...) __riscv_vlseg7e16_v_i16m1_tumu(__VA_ARGS__) -#define vlseg8e16_v_i16m1_m(...) __riscv_vlseg8e16_v_i16m1_tumu(__VA_ARGS__) -#define vlseg2e16_v_i16m2_m(...) __riscv_vlseg2e16_v_i16m2_tumu(__VA_ARGS__) -#define vlseg3e16_v_i16m2_m(...) __riscv_vlseg3e16_v_i16m2_tumu(__VA_ARGS__) -#define vlseg4e16_v_i16m2_m(...) __riscv_vlseg4e16_v_i16m2_tumu(__VA_ARGS__) -#define vlseg2e16_v_i16m4_m(...) __riscv_vlseg2e16_v_i16m4_tumu(__VA_ARGS__) -#define vlseg2e32_v_i32mf2_m(...) __riscv_vlseg2e32_v_i32mf2_tumu(__VA_ARGS__) -#define vlseg3e32_v_i32mf2_m(...) __riscv_vlseg3e32_v_i32mf2_tumu(__VA_ARGS__) -#define vlseg4e32_v_i32mf2_m(...) __riscv_vlseg4e32_v_i32mf2_tumu(__VA_ARGS__) -#define vlseg5e32_v_i32mf2_m(...) __riscv_vlseg5e32_v_i32mf2_tumu(__VA_ARGS__) -#define vlseg6e32_v_i32mf2_m(...) __riscv_vlseg6e32_v_i32mf2_tumu(__VA_ARGS__) -#define vlseg7e32_v_i32mf2_m(...) __riscv_vlseg7e32_v_i32mf2_tumu(__VA_ARGS__) -#define vlseg8e32_v_i32mf2_m(...) __riscv_vlseg8e32_v_i32mf2_tumu(__VA_ARGS__) -#define vlseg2e32_v_i32m1_m(...) __riscv_vlseg2e32_v_i32m1_tumu(__VA_ARGS__) -#define vlseg3e32_v_i32m1_m(...) __riscv_vlseg3e32_v_i32m1_tumu(__VA_ARGS__) -#define vlseg4e32_v_i32m1_m(...) __riscv_vlseg4e32_v_i32m1_tumu(__VA_ARGS__) -#define vlseg5e32_v_i32m1_m(...) __riscv_vlseg5e32_v_i32m1_tumu(__VA_ARGS__) -#define vlseg6e32_v_i32m1_m(...) __riscv_vlseg6e32_v_i32m1_tumu(__VA_ARGS__) -#define vlseg7e32_v_i32m1_m(...) __riscv_vlseg7e32_v_i32m1_tumu(__VA_ARGS__) -#define vlseg8e32_v_i32m1_m(...) __riscv_vlseg8e32_v_i32m1_tumu(__VA_ARGS__) -#define vlseg2e32_v_i32m2_m(...) __riscv_vlseg2e32_v_i32m2_tumu(__VA_ARGS__) -#define vlseg3e32_v_i32m2_m(...) __riscv_vlseg3e32_v_i32m2_tumu(__VA_ARGS__) -#define vlseg4e32_v_i32m2_m(...) __riscv_vlseg4e32_v_i32m2_tumu(__VA_ARGS__) -#define vlseg2e32_v_i32m4_m(...) __riscv_vlseg2e32_v_i32m4_tumu(__VA_ARGS__) -#define vlseg2e64_v_i64m1_m(...) __riscv_vlseg2e64_v_i64m1_tumu(__VA_ARGS__) -#define vlseg3e64_v_i64m1_m(...) __riscv_vlseg3e64_v_i64m1_tumu(__VA_ARGS__) -#define vlseg4e64_v_i64m1_m(...) __riscv_vlseg4e64_v_i64m1_tumu(__VA_ARGS__) -#define vlseg5e64_v_i64m1_m(...) __riscv_vlseg5e64_v_i64m1_tumu(__VA_ARGS__) -#define vlseg6e64_v_i64m1_m(...) __riscv_vlseg6e64_v_i64m1_tumu(__VA_ARGS__) -#define vlseg7e64_v_i64m1_m(...) __riscv_vlseg7e64_v_i64m1_tumu(__VA_ARGS__) -#define vlseg8e64_v_i64m1_m(...) __riscv_vlseg8e64_v_i64m1_tumu(__VA_ARGS__) -#define vlseg2e64_v_i64m2_m(...) __riscv_vlseg2e64_v_i64m2_tumu(__VA_ARGS__) -#define vlseg3e64_v_i64m2_m(...) __riscv_vlseg3e64_v_i64m2_tumu(__VA_ARGS__) -#define vlseg4e64_v_i64m2_m(...) __riscv_vlseg4e64_v_i64m2_tumu(__VA_ARGS__) -#define vlseg2e64_v_i64m4_m(...) __riscv_vlseg2e64_v_i64m4_tumu(__VA_ARGS__) -#define vlseg2e8ff_v_i8mf8_m(...) __riscv_vlseg2e8ff_v_i8mf8_tumu(__VA_ARGS__) -#define vlseg3e8ff_v_i8mf8_m(...) __riscv_vlseg3e8ff_v_i8mf8_tumu(__VA_ARGS__) -#define vlseg4e8ff_v_i8mf8_m(...) __riscv_vlseg4e8ff_v_i8mf8_tumu(__VA_ARGS__) -#define vlseg5e8ff_v_i8mf8_m(...) __riscv_vlseg5e8ff_v_i8mf8_tumu(__VA_ARGS__) -#define vlseg6e8ff_v_i8mf8_m(...) __riscv_vlseg6e8ff_v_i8mf8_tumu(__VA_ARGS__) -#define vlseg7e8ff_v_i8mf8_m(...) __riscv_vlseg7e8ff_v_i8mf8_tumu(__VA_ARGS__) -#define vlseg8e8ff_v_i8mf8_m(...) __riscv_vlseg8e8ff_v_i8mf8_tumu(__VA_ARGS__) -#define vlseg2e8ff_v_i8mf4_m(...) __riscv_vlseg2e8ff_v_i8mf4_tumu(__VA_ARGS__) -#define vlseg3e8ff_v_i8mf4_m(...) __riscv_vlseg3e8ff_v_i8mf4_tumu(__VA_ARGS__) -#define vlseg4e8ff_v_i8mf4_m(...) __riscv_vlseg4e8ff_v_i8mf4_tumu(__VA_ARGS__) -#define vlseg5e8ff_v_i8mf4_m(...) __riscv_vlseg5e8ff_v_i8mf4_tumu(__VA_ARGS__) -#define vlseg6e8ff_v_i8mf4_m(...) __riscv_vlseg6e8ff_v_i8mf4_tumu(__VA_ARGS__) -#define vlseg7e8ff_v_i8mf4_m(...) __riscv_vlseg7e8ff_v_i8mf4_tumu(__VA_ARGS__) -#define vlseg8e8ff_v_i8mf4_m(...) __riscv_vlseg8e8ff_v_i8mf4_tumu(__VA_ARGS__) -#define vlseg2e8ff_v_i8mf2_m(...) __riscv_vlseg2e8ff_v_i8mf2_tumu(__VA_ARGS__) -#define vlseg3e8ff_v_i8mf2_m(...) __riscv_vlseg3e8ff_v_i8mf2_tumu(__VA_ARGS__) -#define vlseg4e8ff_v_i8mf2_m(...) __riscv_vlseg4e8ff_v_i8mf2_tumu(__VA_ARGS__) -#define vlseg5e8ff_v_i8mf2_m(...) __riscv_vlseg5e8ff_v_i8mf2_tumu(__VA_ARGS__) -#define vlseg6e8ff_v_i8mf2_m(...) __riscv_vlseg6e8ff_v_i8mf2_tumu(__VA_ARGS__) -#define vlseg7e8ff_v_i8mf2_m(...) __riscv_vlseg7e8ff_v_i8mf2_tumu(__VA_ARGS__) -#define vlseg8e8ff_v_i8mf2_m(...) __riscv_vlseg8e8ff_v_i8mf2_tumu(__VA_ARGS__) -#define vlseg2e8ff_v_i8m1_m(...) __riscv_vlseg2e8ff_v_i8m1_tumu(__VA_ARGS__) -#define vlseg3e8ff_v_i8m1_m(...) __riscv_vlseg3e8ff_v_i8m1_tumu(__VA_ARGS__) -#define vlseg4e8ff_v_i8m1_m(...) __riscv_vlseg4e8ff_v_i8m1_tumu(__VA_ARGS__) -#define vlseg5e8ff_v_i8m1_m(...) __riscv_vlseg5e8ff_v_i8m1_tumu(__VA_ARGS__) -#define vlseg6e8ff_v_i8m1_m(...) __riscv_vlseg6e8ff_v_i8m1_tumu(__VA_ARGS__) -#define vlseg7e8ff_v_i8m1_m(...) __riscv_vlseg7e8ff_v_i8m1_tumu(__VA_ARGS__) -#define vlseg8e8ff_v_i8m1_m(...) __riscv_vlseg8e8ff_v_i8m1_tumu(__VA_ARGS__) -#define vlseg2e8ff_v_i8m2_m(...) __riscv_vlseg2e8ff_v_i8m2_tumu(__VA_ARGS__) -#define vlseg3e8ff_v_i8m2_m(...) __riscv_vlseg3e8ff_v_i8m2_tumu(__VA_ARGS__) -#define vlseg4e8ff_v_i8m2_m(...) __riscv_vlseg4e8ff_v_i8m2_tumu(__VA_ARGS__) -#define vlseg2e8ff_v_i8m4_m(...) __riscv_vlseg2e8ff_v_i8m4_tumu(__VA_ARGS__) -#define vlseg2e16ff_v_i16mf4_m(...) __riscv_vlseg2e16ff_v_i16mf4_tumu(__VA_ARGS__) -#define vlseg3e16ff_v_i16mf4_m(...) __riscv_vlseg3e16ff_v_i16mf4_tumu(__VA_ARGS__) -#define vlseg4e16ff_v_i16mf4_m(...) __riscv_vlseg4e16ff_v_i16mf4_tumu(__VA_ARGS__) -#define vlseg5e16ff_v_i16mf4_m(...) __riscv_vlseg5e16ff_v_i16mf4_tumu(__VA_ARGS__) -#define vlseg6e16ff_v_i16mf4_m(...) __riscv_vlseg6e16ff_v_i16mf4_tumu(__VA_ARGS__) -#define vlseg7e16ff_v_i16mf4_m(...) __riscv_vlseg7e16ff_v_i16mf4_tumu(__VA_ARGS__) -#define vlseg8e16ff_v_i16mf4_m(...) __riscv_vlseg8e16ff_v_i16mf4_tumu(__VA_ARGS__) -#define vlseg2e16ff_v_i16mf2_m(...) __riscv_vlseg2e16ff_v_i16mf2_tumu(__VA_ARGS__) -#define vlseg3e16ff_v_i16mf2_m(...) __riscv_vlseg3e16ff_v_i16mf2_tumu(__VA_ARGS__) -#define vlseg4e16ff_v_i16mf2_m(...) __riscv_vlseg4e16ff_v_i16mf2_tumu(__VA_ARGS__) -#define vlseg5e16ff_v_i16mf2_m(...) __riscv_vlseg5e16ff_v_i16mf2_tumu(__VA_ARGS__) -#define vlseg6e16ff_v_i16mf2_m(...) __riscv_vlseg6e16ff_v_i16mf2_tumu(__VA_ARGS__) -#define vlseg7e16ff_v_i16mf2_m(...) __riscv_vlseg7e16ff_v_i16mf2_tumu(__VA_ARGS__) -#define vlseg8e16ff_v_i16mf2_m(...) __riscv_vlseg8e16ff_v_i16mf2_tumu(__VA_ARGS__) -#define vlseg2e16ff_v_i16m1_m(...) __riscv_vlseg2e16ff_v_i16m1_tumu(__VA_ARGS__) -#define vlseg3e16ff_v_i16m1_m(...) __riscv_vlseg3e16ff_v_i16m1_tumu(__VA_ARGS__) -#define vlseg4e16ff_v_i16m1_m(...) __riscv_vlseg4e16ff_v_i16m1_tumu(__VA_ARGS__) -#define vlseg5e16ff_v_i16m1_m(...) __riscv_vlseg5e16ff_v_i16m1_tumu(__VA_ARGS__) -#define vlseg6e16ff_v_i16m1_m(...) __riscv_vlseg6e16ff_v_i16m1_tumu(__VA_ARGS__) -#define vlseg7e16ff_v_i16m1_m(...) __riscv_vlseg7e16ff_v_i16m1_tumu(__VA_ARGS__) -#define vlseg8e16ff_v_i16m1_m(...) __riscv_vlseg8e16ff_v_i16m1_tumu(__VA_ARGS__) -#define vlseg2e16ff_v_i16m2_m(...) __riscv_vlseg2e16ff_v_i16m2_tumu(__VA_ARGS__) -#define vlseg3e16ff_v_i16m2_m(...) __riscv_vlseg3e16ff_v_i16m2_tumu(__VA_ARGS__) -#define vlseg4e16ff_v_i16m2_m(...) __riscv_vlseg4e16ff_v_i16m2_tumu(__VA_ARGS__) -#define vlseg2e16ff_v_i16m4_m(...) __riscv_vlseg2e16ff_v_i16m4_tumu(__VA_ARGS__) -#define vlseg2e32ff_v_i32mf2_m(...) __riscv_vlseg2e32ff_v_i32mf2_tumu(__VA_ARGS__) -#define vlseg3e32ff_v_i32mf2_m(...) __riscv_vlseg3e32ff_v_i32mf2_tumu(__VA_ARGS__) -#define vlseg4e32ff_v_i32mf2_m(...) __riscv_vlseg4e32ff_v_i32mf2_tumu(__VA_ARGS__) -#define vlseg5e32ff_v_i32mf2_m(...) __riscv_vlseg5e32ff_v_i32mf2_tumu(__VA_ARGS__) -#define vlseg6e32ff_v_i32mf2_m(...) __riscv_vlseg6e32ff_v_i32mf2_tumu(__VA_ARGS__) -#define vlseg7e32ff_v_i32mf2_m(...) __riscv_vlseg7e32ff_v_i32mf2_tumu(__VA_ARGS__) -#define vlseg8e32ff_v_i32mf2_m(...) __riscv_vlseg8e32ff_v_i32mf2_tumu(__VA_ARGS__) -#define vlseg2e32ff_v_i32m1_m(...) __riscv_vlseg2e32ff_v_i32m1_tumu(__VA_ARGS__) -#define vlseg3e32ff_v_i32m1_m(...) __riscv_vlseg3e32ff_v_i32m1_tumu(__VA_ARGS__) -#define vlseg4e32ff_v_i32m1_m(...) __riscv_vlseg4e32ff_v_i32m1_tumu(__VA_ARGS__) -#define vlseg5e32ff_v_i32m1_m(...) __riscv_vlseg5e32ff_v_i32m1_tumu(__VA_ARGS__) -#define vlseg6e32ff_v_i32m1_m(...) __riscv_vlseg6e32ff_v_i32m1_tumu(__VA_ARGS__) -#define vlseg7e32ff_v_i32m1_m(...) __riscv_vlseg7e32ff_v_i32m1_tumu(__VA_ARGS__) -#define vlseg8e32ff_v_i32m1_m(...) __riscv_vlseg8e32ff_v_i32m1_tumu(__VA_ARGS__) -#define vlseg2e32ff_v_i32m2_m(...) __riscv_vlseg2e32ff_v_i32m2_tumu(__VA_ARGS__) -#define vlseg3e32ff_v_i32m2_m(...) __riscv_vlseg3e32ff_v_i32m2_tumu(__VA_ARGS__) -#define vlseg4e32ff_v_i32m2_m(...) __riscv_vlseg4e32ff_v_i32m2_tumu(__VA_ARGS__) -#define vlseg2e32ff_v_i32m4_m(...) __riscv_vlseg2e32ff_v_i32m4_tumu(__VA_ARGS__) -#define vlseg2e64ff_v_i64m1_m(...) __riscv_vlseg2e64ff_v_i64m1_tumu(__VA_ARGS__) -#define vlseg3e64ff_v_i64m1_m(...) __riscv_vlseg3e64ff_v_i64m1_tumu(__VA_ARGS__) -#define vlseg4e64ff_v_i64m1_m(...) __riscv_vlseg4e64ff_v_i64m1_tumu(__VA_ARGS__) -#define vlseg5e64ff_v_i64m1_m(...) __riscv_vlseg5e64ff_v_i64m1_tumu(__VA_ARGS__) -#define vlseg6e64ff_v_i64m1_m(...) __riscv_vlseg6e64ff_v_i64m1_tumu(__VA_ARGS__) -#define vlseg7e64ff_v_i64m1_m(...) __riscv_vlseg7e64ff_v_i64m1_tumu(__VA_ARGS__) -#define vlseg8e64ff_v_i64m1_m(...) __riscv_vlseg8e64ff_v_i64m1_tumu(__VA_ARGS__) -#define vlseg2e64ff_v_i64m2_m(...) __riscv_vlseg2e64ff_v_i64m2_tumu(__VA_ARGS__) -#define vlseg3e64ff_v_i64m2_m(...) __riscv_vlseg3e64ff_v_i64m2_tumu(__VA_ARGS__) -#define vlseg4e64ff_v_i64m2_m(...) __riscv_vlseg4e64ff_v_i64m2_tumu(__VA_ARGS__) -#define vlseg2e64ff_v_i64m4_m(...) __riscv_vlseg2e64ff_v_i64m4_tumu(__VA_ARGS__) -#define vlseg2e8_v_u8mf8_m(...) __riscv_vlseg2e8_v_u8mf8_tumu(__VA_ARGS__) -#define vlseg3e8_v_u8mf8_m(...) __riscv_vlseg3e8_v_u8mf8_tumu(__VA_ARGS__) -#define vlseg4e8_v_u8mf8_m(...) __riscv_vlseg4e8_v_u8mf8_tumu(__VA_ARGS__) -#define vlseg5e8_v_u8mf8_m(...) __riscv_vlseg5e8_v_u8mf8_tumu(__VA_ARGS__) -#define vlseg6e8_v_u8mf8_m(...) __riscv_vlseg6e8_v_u8mf8_tumu(__VA_ARGS__) -#define vlseg7e8_v_u8mf8_m(...) __riscv_vlseg7e8_v_u8mf8_tumu(__VA_ARGS__) -#define vlseg8e8_v_u8mf8_m(...) __riscv_vlseg8e8_v_u8mf8_tumu(__VA_ARGS__) -#define vlseg2e8_v_u8mf4_m(...) __riscv_vlseg2e8_v_u8mf4_tumu(__VA_ARGS__) -#define vlseg3e8_v_u8mf4_m(...) __riscv_vlseg3e8_v_u8mf4_tumu(__VA_ARGS__) -#define vlseg4e8_v_u8mf4_m(...) __riscv_vlseg4e8_v_u8mf4_tumu(__VA_ARGS__) -#define vlseg5e8_v_u8mf4_m(...) __riscv_vlseg5e8_v_u8mf4_tumu(__VA_ARGS__) -#define vlseg6e8_v_u8mf4_m(...) __riscv_vlseg6e8_v_u8mf4_tumu(__VA_ARGS__) -#define vlseg7e8_v_u8mf4_m(...) __riscv_vlseg7e8_v_u8mf4_tumu(__VA_ARGS__) -#define vlseg8e8_v_u8mf4_m(...) __riscv_vlseg8e8_v_u8mf4_tumu(__VA_ARGS__) -#define vlseg2e8_v_u8mf2_m(...) __riscv_vlseg2e8_v_u8mf2_tumu(__VA_ARGS__) -#define vlseg3e8_v_u8mf2_m(...) __riscv_vlseg3e8_v_u8mf2_tumu(__VA_ARGS__) -#define vlseg4e8_v_u8mf2_m(...) __riscv_vlseg4e8_v_u8mf2_tumu(__VA_ARGS__) -#define vlseg5e8_v_u8mf2_m(...) __riscv_vlseg5e8_v_u8mf2_tumu(__VA_ARGS__) -#define vlseg6e8_v_u8mf2_m(...) __riscv_vlseg6e8_v_u8mf2_tumu(__VA_ARGS__) -#define vlseg7e8_v_u8mf2_m(...) __riscv_vlseg7e8_v_u8mf2_tumu(__VA_ARGS__) -#define vlseg8e8_v_u8mf2_m(...) __riscv_vlseg8e8_v_u8mf2_tumu(__VA_ARGS__) -#define vlseg2e8_v_u8m1_m(...) __riscv_vlseg2e8_v_u8m1_tumu(__VA_ARGS__) -#define vlseg3e8_v_u8m1_m(...) __riscv_vlseg3e8_v_u8m1_tumu(__VA_ARGS__) -#define vlseg4e8_v_u8m1_m(...) __riscv_vlseg4e8_v_u8m1_tumu(__VA_ARGS__) -#define vlseg5e8_v_u8m1_m(...) __riscv_vlseg5e8_v_u8m1_tumu(__VA_ARGS__) -#define vlseg6e8_v_u8m1_m(...) __riscv_vlseg6e8_v_u8m1_tumu(__VA_ARGS__) -#define vlseg7e8_v_u8m1_m(...) __riscv_vlseg7e8_v_u8m1_tumu(__VA_ARGS__) -#define vlseg8e8_v_u8m1_m(...) __riscv_vlseg8e8_v_u8m1_tumu(__VA_ARGS__) -#define vlseg2e8_v_u8m2_m(...) __riscv_vlseg2e8_v_u8m2_tumu(__VA_ARGS__) -#define vlseg3e8_v_u8m2_m(...) __riscv_vlseg3e8_v_u8m2_tumu(__VA_ARGS__) -#define vlseg4e8_v_u8m2_m(...) __riscv_vlseg4e8_v_u8m2_tumu(__VA_ARGS__) -#define vlseg2e8_v_u8m4_m(...) __riscv_vlseg2e8_v_u8m4_tumu(__VA_ARGS__) -#define vlseg2e16_v_u16mf4_m(...) __riscv_vlseg2e16_v_u16mf4_tumu(__VA_ARGS__) -#define vlseg3e16_v_u16mf4_m(...) __riscv_vlseg3e16_v_u16mf4_tumu(__VA_ARGS__) -#define vlseg4e16_v_u16mf4_m(...) __riscv_vlseg4e16_v_u16mf4_tumu(__VA_ARGS__) -#define vlseg5e16_v_u16mf4_m(...) __riscv_vlseg5e16_v_u16mf4_tumu(__VA_ARGS__) -#define vlseg6e16_v_u16mf4_m(...) __riscv_vlseg6e16_v_u16mf4_tumu(__VA_ARGS__) -#define vlseg7e16_v_u16mf4_m(...) __riscv_vlseg7e16_v_u16mf4_tumu(__VA_ARGS__) -#define vlseg8e16_v_u16mf4_m(...) __riscv_vlseg8e16_v_u16mf4_tumu(__VA_ARGS__) -#define vlseg2e16_v_u16mf2_m(...) __riscv_vlseg2e16_v_u16mf2_tumu(__VA_ARGS__) -#define vlseg3e16_v_u16mf2_m(...) __riscv_vlseg3e16_v_u16mf2_tumu(__VA_ARGS__) -#define vlseg4e16_v_u16mf2_m(...) __riscv_vlseg4e16_v_u16mf2_tumu(__VA_ARGS__) -#define vlseg5e16_v_u16mf2_m(...) __riscv_vlseg5e16_v_u16mf2_tumu(__VA_ARGS__) -#define vlseg6e16_v_u16mf2_m(...) __riscv_vlseg6e16_v_u16mf2_tumu(__VA_ARGS__) -#define vlseg7e16_v_u16mf2_m(...) __riscv_vlseg7e16_v_u16mf2_tumu(__VA_ARGS__) -#define vlseg8e16_v_u16mf2_m(...) __riscv_vlseg8e16_v_u16mf2_tumu(__VA_ARGS__) -#define vlseg2e16_v_u16m1_m(...) __riscv_vlseg2e16_v_u16m1_tumu(__VA_ARGS__) -#define vlseg3e16_v_u16m1_m(...) __riscv_vlseg3e16_v_u16m1_tumu(__VA_ARGS__) -#define vlseg4e16_v_u16m1_m(...) __riscv_vlseg4e16_v_u16m1_tumu(__VA_ARGS__) -#define vlseg5e16_v_u16m1_m(...) __riscv_vlseg5e16_v_u16m1_tumu(__VA_ARGS__) -#define vlseg6e16_v_u16m1_m(...) __riscv_vlseg6e16_v_u16m1_tumu(__VA_ARGS__) -#define vlseg7e16_v_u16m1_m(...) __riscv_vlseg7e16_v_u16m1_tumu(__VA_ARGS__) -#define vlseg8e16_v_u16m1_m(...) __riscv_vlseg8e16_v_u16m1_tumu(__VA_ARGS__) -#define vlseg2e16_v_u16m2_m(...) __riscv_vlseg2e16_v_u16m2_tumu(__VA_ARGS__) -#define vlseg3e16_v_u16m2_m(...) __riscv_vlseg3e16_v_u16m2_tumu(__VA_ARGS__) -#define vlseg4e16_v_u16m2_m(...) __riscv_vlseg4e16_v_u16m2_tumu(__VA_ARGS__) -#define vlseg2e16_v_u16m4_m(...) __riscv_vlseg2e16_v_u16m4_tumu(__VA_ARGS__) -#define vlseg2e32_v_u32mf2_m(...) __riscv_vlseg2e32_v_u32mf2_tumu(__VA_ARGS__) -#define vlseg3e32_v_u32mf2_m(...) __riscv_vlseg3e32_v_u32mf2_tumu(__VA_ARGS__) -#define vlseg4e32_v_u32mf2_m(...) __riscv_vlseg4e32_v_u32mf2_tumu(__VA_ARGS__) -#define vlseg5e32_v_u32mf2_m(...) __riscv_vlseg5e32_v_u32mf2_tumu(__VA_ARGS__) -#define vlseg6e32_v_u32mf2_m(...) __riscv_vlseg6e32_v_u32mf2_tumu(__VA_ARGS__) -#define vlseg7e32_v_u32mf2_m(...) __riscv_vlseg7e32_v_u32mf2_tumu(__VA_ARGS__) -#define vlseg8e32_v_u32mf2_m(...) __riscv_vlseg8e32_v_u32mf2_tumu(__VA_ARGS__) -#define vlseg2e32_v_u32m1_m(...) __riscv_vlseg2e32_v_u32m1_tumu(__VA_ARGS__) -#define vlseg3e32_v_u32m1_m(...) __riscv_vlseg3e32_v_u32m1_tumu(__VA_ARGS__) -#define vlseg4e32_v_u32m1_m(...) __riscv_vlseg4e32_v_u32m1_tumu(__VA_ARGS__) -#define vlseg5e32_v_u32m1_m(...) __riscv_vlseg5e32_v_u32m1_tumu(__VA_ARGS__) -#define vlseg6e32_v_u32m1_m(...) __riscv_vlseg6e32_v_u32m1_tumu(__VA_ARGS__) -#define vlseg7e32_v_u32m1_m(...) __riscv_vlseg7e32_v_u32m1_tumu(__VA_ARGS__) -#define vlseg8e32_v_u32m1_m(...) __riscv_vlseg8e32_v_u32m1_tumu(__VA_ARGS__) -#define vlseg2e32_v_u32m2_m(...) __riscv_vlseg2e32_v_u32m2_tumu(__VA_ARGS__) -#define vlseg3e32_v_u32m2_m(...) __riscv_vlseg3e32_v_u32m2_tumu(__VA_ARGS__) -#define vlseg4e32_v_u32m2_m(...) __riscv_vlseg4e32_v_u32m2_tumu(__VA_ARGS__) -#define vlseg2e32_v_u32m4_m(...) __riscv_vlseg2e32_v_u32m4_tumu(__VA_ARGS__) -#define vlseg2e64_v_u64m1_m(...) __riscv_vlseg2e64_v_u64m1_tumu(__VA_ARGS__) -#define vlseg3e64_v_u64m1_m(...) __riscv_vlseg3e64_v_u64m1_tumu(__VA_ARGS__) -#define vlseg4e64_v_u64m1_m(...) __riscv_vlseg4e64_v_u64m1_tumu(__VA_ARGS__) -#define vlseg5e64_v_u64m1_m(...) __riscv_vlseg5e64_v_u64m1_tumu(__VA_ARGS__) -#define vlseg6e64_v_u64m1_m(...) __riscv_vlseg6e64_v_u64m1_tumu(__VA_ARGS__) -#define vlseg7e64_v_u64m1_m(...) __riscv_vlseg7e64_v_u64m1_tumu(__VA_ARGS__) -#define vlseg8e64_v_u64m1_m(...) __riscv_vlseg8e64_v_u64m1_tumu(__VA_ARGS__) -#define vlseg2e64_v_u64m2_m(...) __riscv_vlseg2e64_v_u64m2_tumu(__VA_ARGS__) -#define vlseg3e64_v_u64m2_m(...) __riscv_vlseg3e64_v_u64m2_tumu(__VA_ARGS__) -#define vlseg4e64_v_u64m2_m(...) __riscv_vlseg4e64_v_u64m2_tumu(__VA_ARGS__) -#define vlseg2e64_v_u64m4_m(...) __riscv_vlseg2e64_v_u64m4_tumu(__VA_ARGS__) -#define vlseg2e8ff_v_u8mf8_m(...) __riscv_vlseg2e8ff_v_u8mf8_tumu(__VA_ARGS__) -#define vlseg3e8ff_v_u8mf8_m(...) __riscv_vlseg3e8ff_v_u8mf8_tumu(__VA_ARGS__) -#define vlseg4e8ff_v_u8mf8_m(...) __riscv_vlseg4e8ff_v_u8mf8_tumu(__VA_ARGS__) -#define vlseg5e8ff_v_u8mf8_m(...) __riscv_vlseg5e8ff_v_u8mf8_tumu(__VA_ARGS__) -#define vlseg6e8ff_v_u8mf8_m(...) __riscv_vlseg6e8ff_v_u8mf8_tumu(__VA_ARGS__) -#define vlseg7e8ff_v_u8mf8_m(...) __riscv_vlseg7e8ff_v_u8mf8_tumu(__VA_ARGS__) -#define vlseg8e8ff_v_u8mf8_m(...) __riscv_vlseg8e8ff_v_u8mf8_tumu(__VA_ARGS__) -#define vlseg2e8ff_v_u8mf4_m(...) __riscv_vlseg2e8ff_v_u8mf4_tumu(__VA_ARGS__) -#define vlseg3e8ff_v_u8mf4_m(...) __riscv_vlseg3e8ff_v_u8mf4_tumu(__VA_ARGS__) -#define vlseg4e8ff_v_u8mf4_m(...) __riscv_vlseg4e8ff_v_u8mf4_tumu(__VA_ARGS__) -#define vlseg5e8ff_v_u8mf4_m(...) __riscv_vlseg5e8ff_v_u8mf4_tumu(__VA_ARGS__) -#define vlseg6e8ff_v_u8mf4_m(...) __riscv_vlseg6e8ff_v_u8mf4_tumu(__VA_ARGS__) -#define vlseg7e8ff_v_u8mf4_m(...) __riscv_vlseg7e8ff_v_u8mf4_tumu(__VA_ARGS__) -#define vlseg8e8ff_v_u8mf4_m(...) __riscv_vlseg8e8ff_v_u8mf4_tumu(__VA_ARGS__) -#define vlseg2e8ff_v_u8mf2_m(...) __riscv_vlseg2e8ff_v_u8mf2_tumu(__VA_ARGS__) -#define vlseg3e8ff_v_u8mf2_m(...) __riscv_vlseg3e8ff_v_u8mf2_tumu(__VA_ARGS__) -#define vlseg4e8ff_v_u8mf2_m(...) __riscv_vlseg4e8ff_v_u8mf2_tumu(__VA_ARGS__) -#define vlseg5e8ff_v_u8mf2_m(...) __riscv_vlseg5e8ff_v_u8mf2_tumu(__VA_ARGS__) -#define vlseg6e8ff_v_u8mf2_m(...) __riscv_vlseg6e8ff_v_u8mf2_tumu(__VA_ARGS__) -#define vlseg7e8ff_v_u8mf2_m(...) __riscv_vlseg7e8ff_v_u8mf2_tumu(__VA_ARGS__) -#define vlseg8e8ff_v_u8mf2_m(...) __riscv_vlseg8e8ff_v_u8mf2_tumu(__VA_ARGS__) -#define vlseg2e8ff_v_u8m1_m(...) __riscv_vlseg2e8ff_v_u8m1_tumu(__VA_ARGS__) -#define vlseg3e8ff_v_u8m1_m(...) __riscv_vlseg3e8ff_v_u8m1_tumu(__VA_ARGS__) -#define vlseg4e8ff_v_u8m1_m(...) __riscv_vlseg4e8ff_v_u8m1_tumu(__VA_ARGS__) -#define vlseg5e8ff_v_u8m1_m(...) __riscv_vlseg5e8ff_v_u8m1_tumu(__VA_ARGS__) -#define vlseg6e8ff_v_u8m1_m(...) __riscv_vlseg6e8ff_v_u8m1_tumu(__VA_ARGS__) -#define vlseg7e8ff_v_u8m1_m(...) __riscv_vlseg7e8ff_v_u8m1_tumu(__VA_ARGS__) -#define vlseg8e8ff_v_u8m1_m(...) __riscv_vlseg8e8ff_v_u8m1_tumu(__VA_ARGS__) -#define vlseg2e8ff_v_u8m2_m(...) __riscv_vlseg2e8ff_v_u8m2_tumu(__VA_ARGS__) -#define vlseg3e8ff_v_u8m2_m(...) __riscv_vlseg3e8ff_v_u8m2_tumu(__VA_ARGS__) -#define vlseg4e8ff_v_u8m2_m(...) __riscv_vlseg4e8ff_v_u8m2_tumu(__VA_ARGS__) -#define vlseg2e8ff_v_u8m4_m(...) __riscv_vlseg2e8ff_v_u8m4_tumu(__VA_ARGS__) -#define vlseg2e16ff_v_u16mf4_m(...) __riscv_vlseg2e16ff_v_u16mf4_tumu(__VA_ARGS__) -#define vlseg3e16ff_v_u16mf4_m(...) __riscv_vlseg3e16ff_v_u16mf4_tumu(__VA_ARGS__) -#define vlseg4e16ff_v_u16mf4_m(...) __riscv_vlseg4e16ff_v_u16mf4_tumu(__VA_ARGS__) -#define vlseg5e16ff_v_u16mf4_m(...) __riscv_vlseg5e16ff_v_u16mf4_tumu(__VA_ARGS__) -#define vlseg6e16ff_v_u16mf4_m(...) __riscv_vlseg6e16ff_v_u16mf4_tumu(__VA_ARGS__) -#define vlseg7e16ff_v_u16mf4_m(...) __riscv_vlseg7e16ff_v_u16mf4_tumu(__VA_ARGS__) -#define vlseg8e16ff_v_u16mf4_m(...) __riscv_vlseg8e16ff_v_u16mf4_tumu(__VA_ARGS__) -#define vlseg2e16ff_v_u16mf2_m(...) __riscv_vlseg2e16ff_v_u16mf2_tumu(__VA_ARGS__) -#define vlseg3e16ff_v_u16mf2_m(...) __riscv_vlseg3e16ff_v_u16mf2_tumu(__VA_ARGS__) -#define vlseg4e16ff_v_u16mf2_m(...) __riscv_vlseg4e16ff_v_u16mf2_tumu(__VA_ARGS__) -#define vlseg5e16ff_v_u16mf2_m(...) __riscv_vlseg5e16ff_v_u16mf2_tumu(__VA_ARGS__) -#define vlseg6e16ff_v_u16mf2_m(...) __riscv_vlseg6e16ff_v_u16mf2_tumu(__VA_ARGS__) -#define vlseg7e16ff_v_u16mf2_m(...) __riscv_vlseg7e16ff_v_u16mf2_tumu(__VA_ARGS__) -#define vlseg8e16ff_v_u16mf2_m(...) __riscv_vlseg8e16ff_v_u16mf2_tumu(__VA_ARGS__) -#define vlseg2e16ff_v_u16m1_m(...) __riscv_vlseg2e16ff_v_u16m1_tumu(__VA_ARGS__) -#define vlseg3e16ff_v_u16m1_m(...) __riscv_vlseg3e16ff_v_u16m1_tumu(__VA_ARGS__) -#define vlseg4e16ff_v_u16m1_m(...) __riscv_vlseg4e16ff_v_u16m1_tumu(__VA_ARGS__) -#define vlseg5e16ff_v_u16m1_m(...) __riscv_vlseg5e16ff_v_u16m1_tumu(__VA_ARGS__) -#define vlseg6e16ff_v_u16m1_m(...) __riscv_vlseg6e16ff_v_u16m1_tumu(__VA_ARGS__) -#define vlseg7e16ff_v_u16m1_m(...) __riscv_vlseg7e16ff_v_u16m1_tumu(__VA_ARGS__) -#define vlseg8e16ff_v_u16m1_m(...) __riscv_vlseg8e16ff_v_u16m1_tumu(__VA_ARGS__) -#define vlseg2e16ff_v_u16m2_m(...) __riscv_vlseg2e16ff_v_u16m2_tumu(__VA_ARGS__) -#define vlseg3e16ff_v_u16m2_m(...) __riscv_vlseg3e16ff_v_u16m2_tumu(__VA_ARGS__) -#define vlseg4e16ff_v_u16m2_m(...) __riscv_vlseg4e16ff_v_u16m2_tumu(__VA_ARGS__) -#define vlseg2e16ff_v_u16m4_m(...) __riscv_vlseg2e16ff_v_u16m4_tumu(__VA_ARGS__) -#define vlseg2e32ff_v_u32mf2_m(...) __riscv_vlseg2e32ff_v_u32mf2_tumu(__VA_ARGS__) -#define vlseg3e32ff_v_u32mf2_m(...) __riscv_vlseg3e32ff_v_u32mf2_tumu(__VA_ARGS__) -#define vlseg4e32ff_v_u32mf2_m(...) __riscv_vlseg4e32ff_v_u32mf2_tumu(__VA_ARGS__) -#define vlseg5e32ff_v_u32mf2_m(...) __riscv_vlseg5e32ff_v_u32mf2_tumu(__VA_ARGS__) -#define vlseg6e32ff_v_u32mf2_m(...) __riscv_vlseg6e32ff_v_u32mf2_tumu(__VA_ARGS__) -#define vlseg7e32ff_v_u32mf2_m(...) __riscv_vlseg7e32ff_v_u32mf2_tumu(__VA_ARGS__) -#define vlseg8e32ff_v_u32mf2_m(...) __riscv_vlseg8e32ff_v_u32mf2_tumu(__VA_ARGS__) -#define vlseg2e32ff_v_u32m1_m(...) __riscv_vlseg2e32ff_v_u32m1_tumu(__VA_ARGS__) -#define vlseg3e32ff_v_u32m1_m(...) __riscv_vlseg3e32ff_v_u32m1_tumu(__VA_ARGS__) -#define vlseg4e32ff_v_u32m1_m(...) __riscv_vlseg4e32ff_v_u32m1_tumu(__VA_ARGS__) -#define vlseg5e32ff_v_u32m1_m(...) __riscv_vlseg5e32ff_v_u32m1_tumu(__VA_ARGS__) -#define vlseg6e32ff_v_u32m1_m(...) __riscv_vlseg6e32ff_v_u32m1_tumu(__VA_ARGS__) -#define vlseg7e32ff_v_u32m1_m(...) __riscv_vlseg7e32ff_v_u32m1_tumu(__VA_ARGS__) -#define vlseg8e32ff_v_u32m1_m(...) __riscv_vlseg8e32ff_v_u32m1_tumu(__VA_ARGS__) -#define vlseg2e32ff_v_u32m2_m(...) __riscv_vlseg2e32ff_v_u32m2_tumu(__VA_ARGS__) -#define vlseg3e32ff_v_u32m2_m(...) __riscv_vlseg3e32ff_v_u32m2_tumu(__VA_ARGS__) -#define vlseg4e32ff_v_u32m2_m(...) __riscv_vlseg4e32ff_v_u32m2_tumu(__VA_ARGS__) -#define vlseg2e32ff_v_u32m4_m(...) __riscv_vlseg2e32ff_v_u32m4_tumu(__VA_ARGS__) -#define vlseg2e64ff_v_u64m1_m(...) __riscv_vlseg2e64ff_v_u64m1_tumu(__VA_ARGS__) -#define vlseg3e64ff_v_u64m1_m(...) __riscv_vlseg3e64ff_v_u64m1_tumu(__VA_ARGS__) -#define vlseg4e64ff_v_u64m1_m(...) __riscv_vlseg4e64ff_v_u64m1_tumu(__VA_ARGS__) -#define vlseg5e64ff_v_u64m1_m(...) __riscv_vlseg5e64ff_v_u64m1_tumu(__VA_ARGS__) -#define vlseg6e64ff_v_u64m1_m(...) __riscv_vlseg6e64ff_v_u64m1_tumu(__VA_ARGS__) -#define vlseg7e64ff_v_u64m1_m(...) __riscv_vlseg7e64ff_v_u64m1_tumu(__VA_ARGS__) -#define vlseg8e64ff_v_u64m1_m(...) __riscv_vlseg8e64ff_v_u64m1_tumu(__VA_ARGS__) -#define vlseg2e64ff_v_u64m2_m(...) __riscv_vlseg2e64ff_v_u64m2_tumu(__VA_ARGS__) -#define vlseg3e64ff_v_u64m2_m(...) __riscv_vlseg3e64ff_v_u64m2_tumu(__VA_ARGS__) -#define vlseg4e64ff_v_u64m2_m(...) __riscv_vlseg4e64ff_v_u64m2_tumu(__VA_ARGS__) -#define vlseg2e64ff_v_u64m4_m(...) __riscv_vlseg2e64ff_v_u64m4_tumu(__VA_ARGS__) -#define vsseg2e16_v_f16mf4(...) __riscv_vsseg2e16_v_f16mf4(__VA_ARGS__) -#define vsseg3e16_v_f16mf4(...) __riscv_vsseg3e16_v_f16mf4(__VA_ARGS__) -#define vsseg4e16_v_f16mf4(...) __riscv_vsseg4e16_v_f16mf4(__VA_ARGS__) -#define vsseg5e16_v_f16mf4(...) __riscv_vsseg5e16_v_f16mf4(__VA_ARGS__) -#define vsseg6e16_v_f16mf4(...) __riscv_vsseg6e16_v_f16mf4(__VA_ARGS__) -#define vsseg7e16_v_f16mf4(...) __riscv_vsseg7e16_v_f16mf4(__VA_ARGS__) -#define vsseg8e16_v_f16mf4(...) __riscv_vsseg8e16_v_f16mf4(__VA_ARGS__) -#define vsseg2e16_v_f16mf2(...) __riscv_vsseg2e16_v_f16mf2(__VA_ARGS__) -#define vsseg3e16_v_f16mf2(...) __riscv_vsseg3e16_v_f16mf2(__VA_ARGS__) -#define vsseg4e16_v_f16mf2(...) __riscv_vsseg4e16_v_f16mf2(__VA_ARGS__) -#define vsseg5e16_v_f16mf2(...) __riscv_vsseg5e16_v_f16mf2(__VA_ARGS__) -#define vsseg6e16_v_f16mf2(...) __riscv_vsseg6e16_v_f16mf2(__VA_ARGS__) -#define vsseg7e16_v_f16mf2(...) __riscv_vsseg7e16_v_f16mf2(__VA_ARGS__) -#define vsseg8e16_v_f16mf2(...) __riscv_vsseg8e16_v_f16mf2(__VA_ARGS__) -#define vsseg2e16_v_f16m1(...) __riscv_vsseg2e16_v_f16m1(__VA_ARGS__) -#define vsseg3e16_v_f16m1(...) __riscv_vsseg3e16_v_f16m1(__VA_ARGS__) -#define vsseg4e16_v_f16m1(...) __riscv_vsseg4e16_v_f16m1(__VA_ARGS__) -#define vsseg5e16_v_f16m1(...) __riscv_vsseg5e16_v_f16m1(__VA_ARGS__) -#define vsseg6e16_v_f16m1(...) __riscv_vsseg6e16_v_f16m1(__VA_ARGS__) -#define vsseg7e16_v_f16m1(...) __riscv_vsseg7e16_v_f16m1(__VA_ARGS__) -#define vsseg8e16_v_f16m1(...) __riscv_vsseg8e16_v_f16m1(__VA_ARGS__) -#define vsseg2e16_v_f16m2(...) __riscv_vsseg2e16_v_f16m2(__VA_ARGS__) -#define vsseg3e16_v_f16m2(...) __riscv_vsseg3e16_v_f16m2(__VA_ARGS__) -#define vsseg4e16_v_f16m2(...) __riscv_vsseg4e16_v_f16m2(__VA_ARGS__) -#define vsseg2e16_v_f16m4(...) __riscv_vsseg2e16_v_f16m4(__VA_ARGS__) -#define vsseg2e32_v_f32mf2(...) __riscv_vsseg2e32_v_f32mf2(__VA_ARGS__) -#define vsseg3e32_v_f32mf2(...) __riscv_vsseg3e32_v_f32mf2(__VA_ARGS__) -#define vsseg4e32_v_f32mf2(...) __riscv_vsseg4e32_v_f32mf2(__VA_ARGS__) -#define vsseg5e32_v_f32mf2(...) __riscv_vsseg5e32_v_f32mf2(__VA_ARGS__) -#define vsseg6e32_v_f32mf2(...) __riscv_vsseg6e32_v_f32mf2(__VA_ARGS__) -#define vsseg7e32_v_f32mf2(...) __riscv_vsseg7e32_v_f32mf2(__VA_ARGS__) -#define vsseg8e32_v_f32mf2(...) __riscv_vsseg8e32_v_f32mf2(__VA_ARGS__) -#define vsseg2e32_v_f32m1(...) __riscv_vsseg2e32_v_f32m1(__VA_ARGS__) -#define vsseg3e32_v_f32m1(...) __riscv_vsseg3e32_v_f32m1(__VA_ARGS__) -#define vsseg4e32_v_f32m1(...) __riscv_vsseg4e32_v_f32m1(__VA_ARGS__) -#define vsseg5e32_v_f32m1(...) __riscv_vsseg5e32_v_f32m1(__VA_ARGS__) -#define vsseg6e32_v_f32m1(...) __riscv_vsseg6e32_v_f32m1(__VA_ARGS__) -#define vsseg7e32_v_f32m1(...) __riscv_vsseg7e32_v_f32m1(__VA_ARGS__) -#define vsseg8e32_v_f32m1(...) __riscv_vsseg8e32_v_f32m1(__VA_ARGS__) -#define vsseg2e32_v_f32m2(...) __riscv_vsseg2e32_v_f32m2(__VA_ARGS__) -#define vsseg3e32_v_f32m2(...) __riscv_vsseg3e32_v_f32m2(__VA_ARGS__) -#define vsseg4e32_v_f32m2(...) __riscv_vsseg4e32_v_f32m2(__VA_ARGS__) -#define vsseg2e32_v_f32m4(...) __riscv_vsseg2e32_v_f32m4(__VA_ARGS__) -#define vsseg2e64_v_f64m1(...) __riscv_vsseg2e64_v_f64m1(__VA_ARGS__) -#define vsseg3e64_v_f64m1(...) __riscv_vsseg3e64_v_f64m1(__VA_ARGS__) -#define vsseg4e64_v_f64m1(...) __riscv_vsseg4e64_v_f64m1(__VA_ARGS__) -#define vsseg5e64_v_f64m1(...) __riscv_vsseg5e64_v_f64m1(__VA_ARGS__) -#define vsseg6e64_v_f64m1(...) __riscv_vsseg6e64_v_f64m1(__VA_ARGS__) -#define vsseg7e64_v_f64m1(...) __riscv_vsseg7e64_v_f64m1(__VA_ARGS__) -#define vsseg8e64_v_f64m1(...) __riscv_vsseg8e64_v_f64m1(__VA_ARGS__) -#define vsseg2e64_v_f64m2(...) __riscv_vsseg2e64_v_f64m2(__VA_ARGS__) -#define vsseg3e64_v_f64m2(...) __riscv_vsseg3e64_v_f64m2(__VA_ARGS__) -#define vsseg4e64_v_f64m2(...) __riscv_vsseg4e64_v_f64m2(__VA_ARGS__) -#define vsseg2e64_v_f64m4(...) __riscv_vsseg2e64_v_f64m4(__VA_ARGS__) -#define vsseg2e8_v_i8mf8(...) __riscv_vsseg2e8_v_i8mf8(__VA_ARGS__) -#define vsseg3e8_v_i8mf8(...) __riscv_vsseg3e8_v_i8mf8(__VA_ARGS__) -#define vsseg4e8_v_i8mf8(...) __riscv_vsseg4e8_v_i8mf8(__VA_ARGS__) -#define vsseg5e8_v_i8mf8(...) __riscv_vsseg5e8_v_i8mf8(__VA_ARGS__) -#define vsseg6e8_v_i8mf8(...) __riscv_vsseg6e8_v_i8mf8(__VA_ARGS__) -#define vsseg7e8_v_i8mf8(...) __riscv_vsseg7e8_v_i8mf8(__VA_ARGS__) -#define vsseg8e8_v_i8mf8(...) __riscv_vsseg8e8_v_i8mf8(__VA_ARGS__) -#define vsseg2e8_v_i8mf4(...) __riscv_vsseg2e8_v_i8mf4(__VA_ARGS__) -#define vsseg3e8_v_i8mf4(...) __riscv_vsseg3e8_v_i8mf4(__VA_ARGS__) -#define vsseg4e8_v_i8mf4(...) __riscv_vsseg4e8_v_i8mf4(__VA_ARGS__) -#define vsseg5e8_v_i8mf4(...) __riscv_vsseg5e8_v_i8mf4(__VA_ARGS__) -#define vsseg6e8_v_i8mf4(...) __riscv_vsseg6e8_v_i8mf4(__VA_ARGS__) -#define vsseg7e8_v_i8mf4(...) __riscv_vsseg7e8_v_i8mf4(__VA_ARGS__) -#define vsseg8e8_v_i8mf4(...) __riscv_vsseg8e8_v_i8mf4(__VA_ARGS__) -#define vsseg2e8_v_i8mf2(...) __riscv_vsseg2e8_v_i8mf2(__VA_ARGS__) -#define vsseg3e8_v_i8mf2(...) __riscv_vsseg3e8_v_i8mf2(__VA_ARGS__) -#define vsseg4e8_v_i8mf2(...) __riscv_vsseg4e8_v_i8mf2(__VA_ARGS__) -#define vsseg5e8_v_i8mf2(...) __riscv_vsseg5e8_v_i8mf2(__VA_ARGS__) -#define vsseg6e8_v_i8mf2(...) __riscv_vsseg6e8_v_i8mf2(__VA_ARGS__) -#define vsseg7e8_v_i8mf2(...) __riscv_vsseg7e8_v_i8mf2(__VA_ARGS__) -#define vsseg8e8_v_i8mf2(...) __riscv_vsseg8e8_v_i8mf2(__VA_ARGS__) -#define vsseg2e8_v_i8m1(...) __riscv_vsseg2e8_v_i8m1(__VA_ARGS__) -#define vsseg3e8_v_i8m1(...) __riscv_vsseg3e8_v_i8m1(__VA_ARGS__) -#define vsseg4e8_v_i8m1(...) __riscv_vsseg4e8_v_i8m1(__VA_ARGS__) -#define vsseg5e8_v_i8m1(...) __riscv_vsseg5e8_v_i8m1(__VA_ARGS__) -#define vsseg6e8_v_i8m1(...) __riscv_vsseg6e8_v_i8m1(__VA_ARGS__) -#define vsseg7e8_v_i8m1(...) __riscv_vsseg7e8_v_i8m1(__VA_ARGS__) -#define vsseg8e8_v_i8m1(...) __riscv_vsseg8e8_v_i8m1(__VA_ARGS__) -#define vsseg2e8_v_i8m2(...) __riscv_vsseg2e8_v_i8m2(__VA_ARGS__) -#define vsseg3e8_v_i8m2(...) __riscv_vsseg3e8_v_i8m2(__VA_ARGS__) -#define vsseg4e8_v_i8m2(...) __riscv_vsseg4e8_v_i8m2(__VA_ARGS__) -#define vsseg2e8_v_i8m4(...) __riscv_vsseg2e8_v_i8m4(__VA_ARGS__) -#define vsseg2e16_v_i16mf4(...) __riscv_vsseg2e16_v_i16mf4(__VA_ARGS__) -#define vsseg3e16_v_i16mf4(...) __riscv_vsseg3e16_v_i16mf4(__VA_ARGS__) -#define vsseg4e16_v_i16mf4(...) __riscv_vsseg4e16_v_i16mf4(__VA_ARGS__) -#define vsseg5e16_v_i16mf4(...) __riscv_vsseg5e16_v_i16mf4(__VA_ARGS__) -#define vsseg6e16_v_i16mf4(...) __riscv_vsseg6e16_v_i16mf4(__VA_ARGS__) -#define vsseg7e16_v_i16mf4(...) __riscv_vsseg7e16_v_i16mf4(__VA_ARGS__) -#define vsseg8e16_v_i16mf4(...) __riscv_vsseg8e16_v_i16mf4(__VA_ARGS__) -#define vsseg2e16_v_i16mf2(...) __riscv_vsseg2e16_v_i16mf2(__VA_ARGS__) -#define vsseg3e16_v_i16mf2(...) __riscv_vsseg3e16_v_i16mf2(__VA_ARGS__) -#define vsseg4e16_v_i16mf2(...) __riscv_vsseg4e16_v_i16mf2(__VA_ARGS__) -#define vsseg5e16_v_i16mf2(...) __riscv_vsseg5e16_v_i16mf2(__VA_ARGS__) -#define vsseg6e16_v_i16mf2(...) __riscv_vsseg6e16_v_i16mf2(__VA_ARGS__) -#define vsseg7e16_v_i16mf2(...) __riscv_vsseg7e16_v_i16mf2(__VA_ARGS__) -#define vsseg8e16_v_i16mf2(...) __riscv_vsseg8e16_v_i16mf2(__VA_ARGS__) -#define vsseg2e16_v_i16m1(...) __riscv_vsseg2e16_v_i16m1(__VA_ARGS__) -#define vsseg3e16_v_i16m1(...) __riscv_vsseg3e16_v_i16m1(__VA_ARGS__) -#define vsseg4e16_v_i16m1(...) __riscv_vsseg4e16_v_i16m1(__VA_ARGS__) -#define vsseg5e16_v_i16m1(...) __riscv_vsseg5e16_v_i16m1(__VA_ARGS__) -#define vsseg6e16_v_i16m1(...) __riscv_vsseg6e16_v_i16m1(__VA_ARGS__) -#define vsseg7e16_v_i16m1(...) __riscv_vsseg7e16_v_i16m1(__VA_ARGS__) -#define vsseg8e16_v_i16m1(...) __riscv_vsseg8e16_v_i16m1(__VA_ARGS__) -#define vsseg2e16_v_i16m2(...) __riscv_vsseg2e16_v_i16m2(__VA_ARGS__) -#define vsseg3e16_v_i16m2(...) __riscv_vsseg3e16_v_i16m2(__VA_ARGS__) -#define vsseg4e16_v_i16m2(...) __riscv_vsseg4e16_v_i16m2(__VA_ARGS__) -#define vsseg2e16_v_i16m4(...) __riscv_vsseg2e16_v_i16m4(__VA_ARGS__) -#define vsseg2e32_v_i32mf2(...) __riscv_vsseg2e32_v_i32mf2(__VA_ARGS__) -#define vsseg3e32_v_i32mf2(...) __riscv_vsseg3e32_v_i32mf2(__VA_ARGS__) -#define vsseg4e32_v_i32mf2(...) __riscv_vsseg4e32_v_i32mf2(__VA_ARGS__) -#define vsseg5e32_v_i32mf2(...) __riscv_vsseg5e32_v_i32mf2(__VA_ARGS__) -#define vsseg6e32_v_i32mf2(...) __riscv_vsseg6e32_v_i32mf2(__VA_ARGS__) -#define vsseg7e32_v_i32mf2(...) __riscv_vsseg7e32_v_i32mf2(__VA_ARGS__) -#define vsseg8e32_v_i32mf2(...) __riscv_vsseg8e32_v_i32mf2(__VA_ARGS__) -#define vsseg2e32_v_i32m1(...) __riscv_vsseg2e32_v_i32m1(__VA_ARGS__) -#define vsseg3e32_v_i32m1(...) __riscv_vsseg3e32_v_i32m1(__VA_ARGS__) -#define vsseg4e32_v_i32m1(...) __riscv_vsseg4e32_v_i32m1(__VA_ARGS__) -#define vsseg5e32_v_i32m1(...) __riscv_vsseg5e32_v_i32m1(__VA_ARGS__) -#define vsseg6e32_v_i32m1(...) __riscv_vsseg6e32_v_i32m1(__VA_ARGS__) -#define vsseg7e32_v_i32m1(...) __riscv_vsseg7e32_v_i32m1(__VA_ARGS__) -#define vsseg8e32_v_i32m1(...) __riscv_vsseg8e32_v_i32m1(__VA_ARGS__) -#define vsseg2e32_v_i32m2(...) __riscv_vsseg2e32_v_i32m2(__VA_ARGS__) -#define vsseg3e32_v_i32m2(...) __riscv_vsseg3e32_v_i32m2(__VA_ARGS__) -#define vsseg4e32_v_i32m2(...) __riscv_vsseg4e32_v_i32m2(__VA_ARGS__) -#define vsseg2e32_v_i32m4(...) __riscv_vsseg2e32_v_i32m4(__VA_ARGS__) -#define vsseg2e64_v_i64m1(...) __riscv_vsseg2e64_v_i64m1(__VA_ARGS__) -#define vsseg3e64_v_i64m1(...) __riscv_vsseg3e64_v_i64m1(__VA_ARGS__) -#define vsseg4e64_v_i64m1(...) __riscv_vsseg4e64_v_i64m1(__VA_ARGS__) -#define vsseg5e64_v_i64m1(...) __riscv_vsseg5e64_v_i64m1(__VA_ARGS__) -#define vsseg6e64_v_i64m1(...) __riscv_vsseg6e64_v_i64m1(__VA_ARGS__) -#define vsseg7e64_v_i64m1(...) __riscv_vsseg7e64_v_i64m1(__VA_ARGS__) -#define vsseg8e64_v_i64m1(...) __riscv_vsseg8e64_v_i64m1(__VA_ARGS__) -#define vsseg2e64_v_i64m2(...) __riscv_vsseg2e64_v_i64m2(__VA_ARGS__) -#define vsseg3e64_v_i64m2(...) __riscv_vsseg3e64_v_i64m2(__VA_ARGS__) -#define vsseg4e64_v_i64m2(...) __riscv_vsseg4e64_v_i64m2(__VA_ARGS__) -#define vsseg2e64_v_i64m4(...) __riscv_vsseg2e64_v_i64m4(__VA_ARGS__) -#define vsseg2e8_v_u8mf8(...) __riscv_vsseg2e8_v_u8mf8(__VA_ARGS__) -#define vsseg3e8_v_u8mf8(...) __riscv_vsseg3e8_v_u8mf8(__VA_ARGS__) -#define vsseg4e8_v_u8mf8(...) __riscv_vsseg4e8_v_u8mf8(__VA_ARGS__) -#define vsseg5e8_v_u8mf8(...) __riscv_vsseg5e8_v_u8mf8(__VA_ARGS__) -#define vsseg6e8_v_u8mf8(...) __riscv_vsseg6e8_v_u8mf8(__VA_ARGS__) -#define vsseg7e8_v_u8mf8(...) __riscv_vsseg7e8_v_u8mf8(__VA_ARGS__) -#define vsseg8e8_v_u8mf8(...) __riscv_vsseg8e8_v_u8mf8(__VA_ARGS__) -#define vsseg2e8_v_u8mf4(...) __riscv_vsseg2e8_v_u8mf4(__VA_ARGS__) -#define vsseg3e8_v_u8mf4(...) __riscv_vsseg3e8_v_u8mf4(__VA_ARGS__) -#define vsseg4e8_v_u8mf4(...) __riscv_vsseg4e8_v_u8mf4(__VA_ARGS__) -#define vsseg5e8_v_u8mf4(...) __riscv_vsseg5e8_v_u8mf4(__VA_ARGS__) -#define vsseg6e8_v_u8mf4(...) __riscv_vsseg6e8_v_u8mf4(__VA_ARGS__) -#define vsseg7e8_v_u8mf4(...) __riscv_vsseg7e8_v_u8mf4(__VA_ARGS__) -#define vsseg8e8_v_u8mf4(...) __riscv_vsseg8e8_v_u8mf4(__VA_ARGS__) -#define vsseg2e8_v_u8mf2(...) __riscv_vsseg2e8_v_u8mf2(__VA_ARGS__) -#define vsseg3e8_v_u8mf2(...) __riscv_vsseg3e8_v_u8mf2(__VA_ARGS__) -#define vsseg4e8_v_u8mf2(...) __riscv_vsseg4e8_v_u8mf2(__VA_ARGS__) -#define vsseg5e8_v_u8mf2(...) __riscv_vsseg5e8_v_u8mf2(__VA_ARGS__) -#define vsseg6e8_v_u8mf2(...) __riscv_vsseg6e8_v_u8mf2(__VA_ARGS__) -#define vsseg7e8_v_u8mf2(...) __riscv_vsseg7e8_v_u8mf2(__VA_ARGS__) -#define vsseg8e8_v_u8mf2(...) __riscv_vsseg8e8_v_u8mf2(__VA_ARGS__) -#define vsseg2e8_v_u8m1(...) __riscv_vsseg2e8_v_u8m1(__VA_ARGS__) -#define vsseg3e8_v_u8m1(...) __riscv_vsseg3e8_v_u8m1(__VA_ARGS__) -#define vsseg4e8_v_u8m1(...) __riscv_vsseg4e8_v_u8m1(__VA_ARGS__) -#define vsseg5e8_v_u8m1(...) __riscv_vsseg5e8_v_u8m1(__VA_ARGS__) -#define vsseg6e8_v_u8m1(...) __riscv_vsseg6e8_v_u8m1(__VA_ARGS__) -#define vsseg7e8_v_u8m1(...) __riscv_vsseg7e8_v_u8m1(__VA_ARGS__) -#define vsseg8e8_v_u8m1(...) __riscv_vsseg8e8_v_u8m1(__VA_ARGS__) -#define vsseg2e8_v_u8m2(...) __riscv_vsseg2e8_v_u8m2(__VA_ARGS__) -#define vsseg3e8_v_u8m2(...) __riscv_vsseg3e8_v_u8m2(__VA_ARGS__) -#define vsseg4e8_v_u8m2(...) __riscv_vsseg4e8_v_u8m2(__VA_ARGS__) -#define vsseg2e8_v_u8m4(...) __riscv_vsseg2e8_v_u8m4(__VA_ARGS__) -#define vsseg2e16_v_u16mf4(...) __riscv_vsseg2e16_v_u16mf4(__VA_ARGS__) -#define vsseg3e16_v_u16mf4(...) __riscv_vsseg3e16_v_u16mf4(__VA_ARGS__) -#define vsseg4e16_v_u16mf4(...) __riscv_vsseg4e16_v_u16mf4(__VA_ARGS__) -#define vsseg5e16_v_u16mf4(...) __riscv_vsseg5e16_v_u16mf4(__VA_ARGS__) -#define vsseg6e16_v_u16mf4(...) __riscv_vsseg6e16_v_u16mf4(__VA_ARGS__) -#define vsseg7e16_v_u16mf4(...) __riscv_vsseg7e16_v_u16mf4(__VA_ARGS__) -#define vsseg8e16_v_u16mf4(...) __riscv_vsseg8e16_v_u16mf4(__VA_ARGS__) -#define vsseg2e16_v_u16mf2(...) __riscv_vsseg2e16_v_u16mf2(__VA_ARGS__) -#define vsseg3e16_v_u16mf2(...) __riscv_vsseg3e16_v_u16mf2(__VA_ARGS__) -#define vsseg4e16_v_u16mf2(...) __riscv_vsseg4e16_v_u16mf2(__VA_ARGS__) -#define vsseg5e16_v_u16mf2(...) __riscv_vsseg5e16_v_u16mf2(__VA_ARGS__) -#define vsseg6e16_v_u16mf2(...) __riscv_vsseg6e16_v_u16mf2(__VA_ARGS__) -#define vsseg7e16_v_u16mf2(...) __riscv_vsseg7e16_v_u16mf2(__VA_ARGS__) -#define vsseg8e16_v_u16mf2(...) __riscv_vsseg8e16_v_u16mf2(__VA_ARGS__) -#define vsseg2e16_v_u16m1(...) __riscv_vsseg2e16_v_u16m1(__VA_ARGS__) -#define vsseg3e16_v_u16m1(...) __riscv_vsseg3e16_v_u16m1(__VA_ARGS__) -#define vsseg4e16_v_u16m1(...) __riscv_vsseg4e16_v_u16m1(__VA_ARGS__) -#define vsseg5e16_v_u16m1(...) __riscv_vsseg5e16_v_u16m1(__VA_ARGS__) -#define vsseg6e16_v_u16m1(...) __riscv_vsseg6e16_v_u16m1(__VA_ARGS__) -#define vsseg7e16_v_u16m1(...) __riscv_vsseg7e16_v_u16m1(__VA_ARGS__) -#define vsseg8e16_v_u16m1(...) __riscv_vsseg8e16_v_u16m1(__VA_ARGS__) -#define vsseg2e16_v_u16m2(...) __riscv_vsseg2e16_v_u16m2(__VA_ARGS__) -#define vsseg3e16_v_u16m2(...) __riscv_vsseg3e16_v_u16m2(__VA_ARGS__) -#define vsseg4e16_v_u16m2(...) __riscv_vsseg4e16_v_u16m2(__VA_ARGS__) -#define vsseg2e16_v_u16m4(...) __riscv_vsseg2e16_v_u16m4(__VA_ARGS__) -#define vsseg2e32_v_u32mf2(...) __riscv_vsseg2e32_v_u32mf2(__VA_ARGS__) -#define vsseg3e32_v_u32mf2(...) __riscv_vsseg3e32_v_u32mf2(__VA_ARGS__) -#define vsseg4e32_v_u32mf2(...) __riscv_vsseg4e32_v_u32mf2(__VA_ARGS__) -#define vsseg5e32_v_u32mf2(...) __riscv_vsseg5e32_v_u32mf2(__VA_ARGS__) -#define vsseg6e32_v_u32mf2(...) __riscv_vsseg6e32_v_u32mf2(__VA_ARGS__) -#define vsseg7e32_v_u32mf2(...) __riscv_vsseg7e32_v_u32mf2(__VA_ARGS__) -#define vsseg8e32_v_u32mf2(...) __riscv_vsseg8e32_v_u32mf2(__VA_ARGS__) -#define vsseg2e32_v_u32m1(...) __riscv_vsseg2e32_v_u32m1(__VA_ARGS__) -#define vsseg3e32_v_u32m1(...) __riscv_vsseg3e32_v_u32m1(__VA_ARGS__) -#define vsseg4e32_v_u32m1(...) __riscv_vsseg4e32_v_u32m1(__VA_ARGS__) -#define vsseg5e32_v_u32m1(...) __riscv_vsseg5e32_v_u32m1(__VA_ARGS__) -#define vsseg6e32_v_u32m1(...) __riscv_vsseg6e32_v_u32m1(__VA_ARGS__) -#define vsseg7e32_v_u32m1(...) __riscv_vsseg7e32_v_u32m1(__VA_ARGS__) -#define vsseg8e32_v_u32m1(...) __riscv_vsseg8e32_v_u32m1(__VA_ARGS__) -#define vsseg2e32_v_u32m2(...) __riscv_vsseg2e32_v_u32m2(__VA_ARGS__) -#define vsseg3e32_v_u32m2(...) __riscv_vsseg3e32_v_u32m2(__VA_ARGS__) -#define vsseg4e32_v_u32m2(...) __riscv_vsseg4e32_v_u32m2(__VA_ARGS__) -#define vsseg2e32_v_u32m4(...) __riscv_vsseg2e32_v_u32m4(__VA_ARGS__) -#define vsseg2e64_v_u64m1(...) __riscv_vsseg2e64_v_u64m1(__VA_ARGS__) -#define vsseg3e64_v_u64m1(...) __riscv_vsseg3e64_v_u64m1(__VA_ARGS__) -#define vsseg4e64_v_u64m1(...) __riscv_vsseg4e64_v_u64m1(__VA_ARGS__) -#define vsseg5e64_v_u64m1(...) __riscv_vsseg5e64_v_u64m1(__VA_ARGS__) -#define vsseg6e64_v_u64m1(...) __riscv_vsseg6e64_v_u64m1(__VA_ARGS__) -#define vsseg7e64_v_u64m1(...) __riscv_vsseg7e64_v_u64m1(__VA_ARGS__) -#define vsseg8e64_v_u64m1(...) __riscv_vsseg8e64_v_u64m1(__VA_ARGS__) -#define vsseg2e64_v_u64m2(...) __riscv_vsseg2e64_v_u64m2(__VA_ARGS__) -#define vsseg3e64_v_u64m2(...) __riscv_vsseg3e64_v_u64m2(__VA_ARGS__) -#define vsseg4e64_v_u64m2(...) __riscv_vsseg4e64_v_u64m2(__VA_ARGS__) -#define vsseg2e64_v_u64m4(...) __riscv_vsseg2e64_v_u64m4(__VA_ARGS__) -// masked functions -#define vsseg2e16_v_f16mf4_m(...) __riscv_vsseg2e16_v_f16mf4_m(__VA_ARGS__) -#define vsseg3e16_v_f16mf4_m(...) __riscv_vsseg3e16_v_f16mf4_m(__VA_ARGS__) -#define vsseg4e16_v_f16mf4_m(...) __riscv_vsseg4e16_v_f16mf4_m(__VA_ARGS__) -#define vsseg5e16_v_f16mf4_m(...) __riscv_vsseg5e16_v_f16mf4_m(__VA_ARGS__) -#define vsseg6e16_v_f16mf4_m(...) __riscv_vsseg6e16_v_f16mf4_m(__VA_ARGS__) -#define vsseg7e16_v_f16mf4_m(...) __riscv_vsseg7e16_v_f16mf4_m(__VA_ARGS__) -#define vsseg8e16_v_f16mf4_m(...) __riscv_vsseg8e16_v_f16mf4_m(__VA_ARGS__) -#define vsseg2e16_v_f16mf2_m(...) __riscv_vsseg2e16_v_f16mf2_m(__VA_ARGS__) -#define vsseg3e16_v_f16mf2_m(...) __riscv_vsseg3e16_v_f16mf2_m(__VA_ARGS__) -#define vsseg4e16_v_f16mf2_m(...) __riscv_vsseg4e16_v_f16mf2_m(__VA_ARGS__) -#define vsseg5e16_v_f16mf2_m(...) __riscv_vsseg5e16_v_f16mf2_m(__VA_ARGS__) -#define vsseg6e16_v_f16mf2_m(...) __riscv_vsseg6e16_v_f16mf2_m(__VA_ARGS__) -#define vsseg7e16_v_f16mf2_m(...) __riscv_vsseg7e16_v_f16mf2_m(__VA_ARGS__) -#define vsseg8e16_v_f16mf2_m(...) __riscv_vsseg8e16_v_f16mf2_m(__VA_ARGS__) -#define vsseg2e16_v_f16m1_m(...) __riscv_vsseg2e16_v_f16m1_m(__VA_ARGS__) -#define vsseg3e16_v_f16m1_m(...) __riscv_vsseg3e16_v_f16m1_m(__VA_ARGS__) -#define vsseg4e16_v_f16m1_m(...) __riscv_vsseg4e16_v_f16m1_m(__VA_ARGS__) -#define vsseg5e16_v_f16m1_m(...) __riscv_vsseg5e16_v_f16m1_m(__VA_ARGS__) -#define vsseg6e16_v_f16m1_m(...) __riscv_vsseg6e16_v_f16m1_m(__VA_ARGS__) -#define vsseg7e16_v_f16m1_m(...) __riscv_vsseg7e16_v_f16m1_m(__VA_ARGS__) -#define vsseg8e16_v_f16m1_m(...) __riscv_vsseg8e16_v_f16m1_m(__VA_ARGS__) -#define vsseg2e16_v_f16m2_m(...) __riscv_vsseg2e16_v_f16m2_m(__VA_ARGS__) -#define vsseg3e16_v_f16m2_m(...) __riscv_vsseg3e16_v_f16m2_m(__VA_ARGS__) -#define vsseg4e16_v_f16m2_m(...) __riscv_vsseg4e16_v_f16m2_m(__VA_ARGS__) -#define vsseg2e16_v_f16m4_m(...) __riscv_vsseg2e16_v_f16m4_m(__VA_ARGS__) -#define vsseg2e32_v_f32mf2_m(...) __riscv_vsseg2e32_v_f32mf2_m(__VA_ARGS__) -#define vsseg3e32_v_f32mf2_m(...) __riscv_vsseg3e32_v_f32mf2_m(__VA_ARGS__) -#define vsseg4e32_v_f32mf2_m(...) __riscv_vsseg4e32_v_f32mf2_m(__VA_ARGS__) -#define vsseg5e32_v_f32mf2_m(...) __riscv_vsseg5e32_v_f32mf2_m(__VA_ARGS__) -#define vsseg6e32_v_f32mf2_m(...) __riscv_vsseg6e32_v_f32mf2_m(__VA_ARGS__) -#define vsseg7e32_v_f32mf2_m(...) __riscv_vsseg7e32_v_f32mf2_m(__VA_ARGS__) -#define vsseg8e32_v_f32mf2_m(...) __riscv_vsseg8e32_v_f32mf2_m(__VA_ARGS__) -#define vsseg2e32_v_f32m1_m(...) __riscv_vsseg2e32_v_f32m1_m(__VA_ARGS__) -#define vsseg3e32_v_f32m1_m(...) __riscv_vsseg3e32_v_f32m1_m(__VA_ARGS__) -#define vsseg4e32_v_f32m1_m(...) __riscv_vsseg4e32_v_f32m1_m(__VA_ARGS__) -#define vsseg5e32_v_f32m1_m(...) __riscv_vsseg5e32_v_f32m1_m(__VA_ARGS__) -#define vsseg6e32_v_f32m1_m(...) __riscv_vsseg6e32_v_f32m1_m(__VA_ARGS__) -#define vsseg7e32_v_f32m1_m(...) __riscv_vsseg7e32_v_f32m1_m(__VA_ARGS__) -#define vsseg8e32_v_f32m1_m(...) __riscv_vsseg8e32_v_f32m1_m(__VA_ARGS__) -#define vsseg2e32_v_f32m2_m(...) __riscv_vsseg2e32_v_f32m2_m(__VA_ARGS__) -#define vsseg3e32_v_f32m2_m(...) __riscv_vsseg3e32_v_f32m2_m(__VA_ARGS__) -#define vsseg4e32_v_f32m2_m(...) __riscv_vsseg4e32_v_f32m2_m(__VA_ARGS__) -#define vsseg2e32_v_f32m4_m(...) __riscv_vsseg2e32_v_f32m4_m(__VA_ARGS__) -#define vsseg2e64_v_f64m1_m(...) __riscv_vsseg2e64_v_f64m1_m(__VA_ARGS__) -#define vsseg3e64_v_f64m1_m(...) __riscv_vsseg3e64_v_f64m1_m(__VA_ARGS__) -#define vsseg4e64_v_f64m1_m(...) __riscv_vsseg4e64_v_f64m1_m(__VA_ARGS__) -#define vsseg5e64_v_f64m1_m(...) __riscv_vsseg5e64_v_f64m1_m(__VA_ARGS__) -#define vsseg6e64_v_f64m1_m(...) __riscv_vsseg6e64_v_f64m1_m(__VA_ARGS__) -#define vsseg7e64_v_f64m1_m(...) __riscv_vsseg7e64_v_f64m1_m(__VA_ARGS__) -#define vsseg8e64_v_f64m1_m(...) __riscv_vsseg8e64_v_f64m1_m(__VA_ARGS__) -#define vsseg2e64_v_f64m2_m(...) __riscv_vsseg2e64_v_f64m2_m(__VA_ARGS__) -#define vsseg3e64_v_f64m2_m(...) __riscv_vsseg3e64_v_f64m2_m(__VA_ARGS__) -#define vsseg4e64_v_f64m2_m(...) __riscv_vsseg4e64_v_f64m2_m(__VA_ARGS__) -#define vsseg2e64_v_f64m4_m(...) __riscv_vsseg2e64_v_f64m4_m(__VA_ARGS__) -#define vsseg2e8_v_i8mf8_m(...) __riscv_vsseg2e8_v_i8mf8_m(__VA_ARGS__) -#define vsseg3e8_v_i8mf8_m(...) __riscv_vsseg3e8_v_i8mf8_m(__VA_ARGS__) -#define vsseg4e8_v_i8mf8_m(...) __riscv_vsseg4e8_v_i8mf8_m(__VA_ARGS__) -#define vsseg5e8_v_i8mf8_m(...) __riscv_vsseg5e8_v_i8mf8_m(__VA_ARGS__) -#define vsseg6e8_v_i8mf8_m(...) __riscv_vsseg6e8_v_i8mf8_m(__VA_ARGS__) -#define vsseg7e8_v_i8mf8_m(...) __riscv_vsseg7e8_v_i8mf8_m(__VA_ARGS__) -#define vsseg8e8_v_i8mf8_m(...) __riscv_vsseg8e8_v_i8mf8_m(__VA_ARGS__) -#define vsseg2e8_v_i8mf4_m(...) __riscv_vsseg2e8_v_i8mf4_m(__VA_ARGS__) -#define vsseg3e8_v_i8mf4_m(...) __riscv_vsseg3e8_v_i8mf4_m(__VA_ARGS__) -#define vsseg4e8_v_i8mf4_m(...) __riscv_vsseg4e8_v_i8mf4_m(__VA_ARGS__) -#define vsseg5e8_v_i8mf4_m(...) __riscv_vsseg5e8_v_i8mf4_m(__VA_ARGS__) -#define vsseg6e8_v_i8mf4_m(...) __riscv_vsseg6e8_v_i8mf4_m(__VA_ARGS__) -#define vsseg7e8_v_i8mf4_m(...) __riscv_vsseg7e8_v_i8mf4_m(__VA_ARGS__) -#define vsseg8e8_v_i8mf4_m(...) __riscv_vsseg8e8_v_i8mf4_m(__VA_ARGS__) -#define vsseg2e8_v_i8mf2_m(...) __riscv_vsseg2e8_v_i8mf2_m(__VA_ARGS__) -#define vsseg3e8_v_i8mf2_m(...) __riscv_vsseg3e8_v_i8mf2_m(__VA_ARGS__) -#define vsseg4e8_v_i8mf2_m(...) __riscv_vsseg4e8_v_i8mf2_m(__VA_ARGS__) -#define vsseg5e8_v_i8mf2_m(...) __riscv_vsseg5e8_v_i8mf2_m(__VA_ARGS__) -#define vsseg6e8_v_i8mf2_m(...) __riscv_vsseg6e8_v_i8mf2_m(__VA_ARGS__) -#define vsseg7e8_v_i8mf2_m(...) __riscv_vsseg7e8_v_i8mf2_m(__VA_ARGS__) -#define vsseg8e8_v_i8mf2_m(...) __riscv_vsseg8e8_v_i8mf2_m(__VA_ARGS__) -#define vsseg2e8_v_i8m1_m(...) __riscv_vsseg2e8_v_i8m1_m(__VA_ARGS__) -#define vsseg3e8_v_i8m1_m(...) __riscv_vsseg3e8_v_i8m1_m(__VA_ARGS__) -#define vsseg4e8_v_i8m1_m(...) __riscv_vsseg4e8_v_i8m1_m(__VA_ARGS__) -#define vsseg5e8_v_i8m1_m(...) __riscv_vsseg5e8_v_i8m1_m(__VA_ARGS__) -#define vsseg6e8_v_i8m1_m(...) __riscv_vsseg6e8_v_i8m1_m(__VA_ARGS__) -#define vsseg7e8_v_i8m1_m(...) __riscv_vsseg7e8_v_i8m1_m(__VA_ARGS__) -#define vsseg8e8_v_i8m1_m(...) __riscv_vsseg8e8_v_i8m1_m(__VA_ARGS__) -#define vsseg2e8_v_i8m2_m(...) __riscv_vsseg2e8_v_i8m2_m(__VA_ARGS__) -#define vsseg3e8_v_i8m2_m(...) __riscv_vsseg3e8_v_i8m2_m(__VA_ARGS__) -#define vsseg4e8_v_i8m2_m(...) __riscv_vsseg4e8_v_i8m2_m(__VA_ARGS__) -#define vsseg2e8_v_i8m4_m(...) __riscv_vsseg2e8_v_i8m4_m(__VA_ARGS__) -#define vsseg2e16_v_i16mf4_m(...) __riscv_vsseg2e16_v_i16mf4_m(__VA_ARGS__) -#define vsseg3e16_v_i16mf4_m(...) __riscv_vsseg3e16_v_i16mf4_m(__VA_ARGS__) -#define vsseg4e16_v_i16mf4_m(...) __riscv_vsseg4e16_v_i16mf4_m(__VA_ARGS__) -#define vsseg5e16_v_i16mf4_m(...) __riscv_vsseg5e16_v_i16mf4_m(__VA_ARGS__) -#define vsseg6e16_v_i16mf4_m(...) __riscv_vsseg6e16_v_i16mf4_m(__VA_ARGS__) -#define vsseg7e16_v_i16mf4_m(...) __riscv_vsseg7e16_v_i16mf4_m(__VA_ARGS__) -#define vsseg8e16_v_i16mf4_m(...) __riscv_vsseg8e16_v_i16mf4_m(__VA_ARGS__) -#define vsseg2e16_v_i16mf2_m(...) __riscv_vsseg2e16_v_i16mf2_m(__VA_ARGS__) -#define vsseg3e16_v_i16mf2_m(...) __riscv_vsseg3e16_v_i16mf2_m(__VA_ARGS__) -#define vsseg4e16_v_i16mf2_m(...) __riscv_vsseg4e16_v_i16mf2_m(__VA_ARGS__) -#define vsseg5e16_v_i16mf2_m(...) __riscv_vsseg5e16_v_i16mf2_m(__VA_ARGS__) -#define vsseg6e16_v_i16mf2_m(...) __riscv_vsseg6e16_v_i16mf2_m(__VA_ARGS__) -#define vsseg7e16_v_i16mf2_m(...) __riscv_vsseg7e16_v_i16mf2_m(__VA_ARGS__) -#define vsseg8e16_v_i16mf2_m(...) __riscv_vsseg8e16_v_i16mf2_m(__VA_ARGS__) -#define vsseg2e16_v_i16m1_m(...) __riscv_vsseg2e16_v_i16m1_m(__VA_ARGS__) -#define vsseg3e16_v_i16m1_m(...) __riscv_vsseg3e16_v_i16m1_m(__VA_ARGS__) -#define vsseg4e16_v_i16m1_m(...) __riscv_vsseg4e16_v_i16m1_m(__VA_ARGS__) -#define vsseg5e16_v_i16m1_m(...) __riscv_vsseg5e16_v_i16m1_m(__VA_ARGS__) -#define vsseg6e16_v_i16m1_m(...) __riscv_vsseg6e16_v_i16m1_m(__VA_ARGS__) -#define vsseg7e16_v_i16m1_m(...) __riscv_vsseg7e16_v_i16m1_m(__VA_ARGS__) -#define vsseg8e16_v_i16m1_m(...) __riscv_vsseg8e16_v_i16m1_m(__VA_ARGS__) -#define vsseg2e16_v_i16m2_m(...) __riscv_vsseg2e16_v_i16m2_m(__VA_ARGS__) -#define vsseg3e16_v_i16m2_m(...) __riscv_vsseg3e16_v_i16m2_m(__VA_ARGS__) -#define vsseg4e16_v_i16m2_m(...) __riscv_vsseg4e16_v_i16m2_m(__VA_ARGS__) -#define vsseg2e16_v_i16m4_m(...) __riscv_vsseg2e16_v_i16m4_m(__VA_ARGS__) -#define vsseg2e32_v_i32mf2_m(...) __riscv_vsseg2e32_v_i32mf2_m(__VA_ARGS__) -#define vsseg3e32_v_i32mf2_m(...) __riscv_vsseg3e32_v_i32mf2_m(__VA_ARGS__) -#define vsseg4e32_v_i32mf2_m(...) __riscv_vsseg4e32_v_i32mf2_m(__VA_ARGS__) -#define vsseg5e32_v_i32mf2_m(...) __riscv_vsseg5e32_v_i32mf2_m(__VA_ARGS__) -#define vsseg6e32_v_i32mf2_m(...) __riscv_vsseg6e32_v_i32mf2_m(__VA_ARGS__) -#define vsseg7e32_v_i32mf2_m(...) __riscv_vsseg7e32_v_i32mf2_m(__VA_ARGS__) -#define vsseg8e32_v_i32mf2_m(...) __riscv_vsseg8e32_v_i32mf2_m(__VA_ARGS__) -#define vsseg2e32_v_i32m1_m(...) __riscv_vsseg2e32_v_i32m1_m(__VA_ARGS__) -#define vsseg3e32_v_i32m1_m(...) __riscv_vsseg3e32_v_i32m1_m(__VA_ARGS__) -#define vsseg4e32_v_i32m1_m(...) __riscv_vsseg4e32_v_i32m1_m(__VA_ARGS__) -#define vsseg5e32_v_i32m1_m(...) __riscv_vsseg5e32_v_i32m1_m(__VA_ARGS__) -#define vsseg6e32_v_i32m1_m(...) __riscv_vsseg6e32_v_i32m1_m(__VA_ARGS__) -#define vsseg7e32_v_i32m1_m(...) __riscv_vsseg7e32_v_i32m1_m(__VA_ARGS__) -#define vsseg8e32_v_i32m1_m(...) __riscv_vsseg8e32_v_i32m1_m(__VA_ARGS__) -#define vsseg2e32_v_i32m2_m(...) __riscv_vsseg2e32_v_i32m2_m(__VA_ARGS__) -#define vsseg3e32_v_i32m2_m(...) __riscv_vsseg3e32_v_i32m2_m(__VA_ARGS__) -#define vsseg4e32_v_i32m2_m(...) __riscv_vsseg4e32_v_i32m2_m(__VA_ARGS__) -#define vsseg2e32_v_i32m4_m(...) __riscv_vsseg2e32_v_i32m4_m(__VA_ARGS__) -#define vsseg2e64_v_i64m1_m(...) __riscv_vsseg2e64_v_i64m1_m(__VA_ARGS__) -#define vsseg3e64_v_i64m1_m(...) __riscv_vsseg3e64_v_i64m1_m(__VA_ARGS__) -#define vsseg4e64_v_i64m1_m(...) __riscv_vsseg4e64_v_i64m1_m(__VA_ARGS__) -#define vsseg5e64_v_i64m1_m(...) __riscv_vsseg5e64_v_i64m1_m(__VA_ARGS__) -#define vsseg6e64_v_i64m1_m(...) __riscv_vsseg6e64_v_i64m1_m(__VA_ARGS__) -#define vsseg7e64_v_i64m1_m(...) __riscv_vsseg7e64_v_i64m1_m(__VA_ARGS__) -#define vsseg8e64_v_i64m1_m(...) __riscv_vsseg8e64_v_i64m1_m(__VA_ARGS__) -#define vsseg2e64_v_i64m2_m(...) __riscv_vsseg2e64_v_i64m2_m(__VA_ARGS__) -#define vsseg3e64_v_i64m2_m(...) __riscv_vsseg3e64_v_i64m2_m(__VA_ARGS__) -#define vsseg4e64_v_i64m2_m(...) __riscv_vsseg4e64_v_i64m2_m(__VA_ARGS__) -#define vsseg2e64_v_i64m4_m(...) __riscv_vsseg2e64_v_i64m4_m(__VA_ARGS__) -#define vsseg2e8_v_u8mf8_m(...) __riscv_vsseg2e8_v_u8mf8_m(__VA_ARGS__) -#define vsseg3e8_v_u8mf8_m(...) __riscv_vsseg3e8_v_u8mf8_m(__VA_ARGS__) -#define vsseg4e8_v_u8mf8_m(...) __riscv_vsseg4e8_v_u8mf8_m(__VA_ARGS__) -#define vsseg5e8_v_u8mf8_m(...) __riscv_vsseg5e8_v_u8mf8_m(__VA_ARGS__) -#define vsseg6e8_v_u8mf8_m(...) __riscv_vsseg6e8_v_u8mf8_m(__VA_ARGS__) -#define vsseg7e8_v_u8mf8_m(...) __riscv_vsseg7e8_v_u8mf8_m(__VA_ARGS__) -#define vsseg8e8_v_u8mf8_m(...) __riscv_vsseg8e8_v_u8mf8_m(__VA_ARGS__) -#define vsseg2e8_v_u8mf4_m(...) __riscv_vsseg2e8_v_u8mf4_m(__VA_ARGS__) -#define vsseg3e8_v_u8mf4_m(...) __riscv_vsseg3e8_v_u8mf4_m(__VA_ARGS__) -#define vsseg4e8_v_u8mf4_m(...) __riscv_vsseg4e8_v_u8mf4_m(__VA_ARGS__) -#define vsseg5e8_v_u8mf4_m(...) __riscv_vsseg5e8_v_u8mf4_m(__VA_ARGS__) -#define vsseg6e8_v_u8mf4_m(...) __riscv_vsseg6e8_v_u8mf4_m(__VA_ARGS__) -#define vsseg7e8_v_u8mf4_m(...) __riscv_vsseg7e8_v_u8mf4_m(__VA_ARGS__) -#define vsseg8e8_v_u8mf4_m(...) __riscv_vsseg8e8_v_u8mf4_m(__VA_ARGS__) -#define vsseg2e8_v_u8mf2_m(...) __riscv_vsseg2e8_v_u8mf2_m(__VA_ARGS__) -#define vsseg3e8_v_u8mf2_m(...) __riscv_vsseg3e8_v_u8mf2_m(__VA_ARGS__) -#define vsseg4e8_v_u8mf2_m(...) __riscv_vsseg4e8_v_u8mf2_m(__VA_ARGS__) -#define vsseg5e8_v_u8mf2_m(...) __riscv_vsseg5e8_v_u8mf2_m(__VA_ARGS__) -#define vsseg6e8_v_u8mf2_m(...) __riscv_vsseg6e8_v_u8mf2_m(__VA_ARGS__) -#define vsseg7e8_v_u8mf2_m(...) __riscv_vsseg7e8_v_u8mf2_m(__VA_ARGS__) -#define vsseg8e8_v_u8mf2_m(...) __riscv_vsseg8e8_v_u8mf2_m(__VA_ARGS__) -#define vsseg2e8_v_u8m1_m(...) __riscv_vsseg2e8_v_u8m1_m(__VA_ARGS__) -#define vsseg3e8_v_u8m1_m(...) __riscv_vsseg3e8_v_u8m1_m(__VA_ARGS__) -#define vsseg4e8_v_u8m1_m(...) __riscv_vsseg4e8_v_u8m1_m(__VA_ARGS__) -#define vsseg5e8_v_u8m1_m(...) __riscv_vsseg5e8_v_u8m1_m(__VA_ARGS__) -#define vsseg6e8_v_u8m1_m(...) __riscv_vsseg6e8_v_u8m1_m(__VA_ARGS__) -#define vsseg7e8_v_u8m1_m(...) __riscv_vsseg7e8_v_u8m1_m(__VA_ARGS__) -#define vsseg8e8_v_u8m1_m(...) __riscv_vsseg8e8_v_u8m1_m(__VA_ARGS__) -#define vsseg2e8_v_u8m2_m(...) __riscv_vsseg2e8_v_u8m2_m(__VA_ARGS__) -#define vsseg3e8_v_u8m2_m(...) __riscv_vsseg3e8_v_u8m2_m(__VA_ARGS__) -#define vsseg4e8_v_u8m2_m(...) __riscv_vsseg4e8_v_u8m2_m(__VA_ARGS__) -#define vsseg2e8_v_u8m4_m(...) __riscv_vsseg2e8_v_u8m4_m(__VA_ARGS__) -#define vsseg2e16_v_u16mf4_m(...) __riscv_vsseg2e16_v_u16mf4_m(__VA_ARGS__) -#define vsseg3e16_v_u16mf4_m(...) __riscv_vsseg3e16_v_u16mf4_m(__VA_ARGS__) -#define vsseg4e16_v_u16mf4_m(...) __riscv_vsseg4e16_v_u16mf4_m(__VA_ARGS__) -#define vsseg5e16_v_u16mf4_m(...) __riscv_vsseg5e16_v_u16mf4_m(__VA_ARGS__) -#define vsseg6e16_v_u16mf4_m(...) __riscv_vsseg6e16_v_u16mf4_m(__VA_ARGS__) -#define vsseg7e16_v_u16mf4_m(...) __riscv_vsseg7e16_v_u16mf4_m(__VA_ARGS__) -#define vsseg8e16_v_u16mf4_m(...) __riscv_vsseg8e16_v_u16mf4_m(__VA_ARGS__) -#define vsseg2e16_v_u16mf2_m(...) __riscv_vsseg2e16_v_u16mf2_m(__VA_ARGS__) -#define vsseg3e16_v_u16mf2_m(...) __riscv_vsseg3e16_v_u16mf2_m(__VA_ARGS__) -#define vsseg4e16_v_u16mf2_m(...) __riscv_vsseg4e16_v_u16mf2_m(__VA_ARGS__) -#define vsseg5e16_v_u16mf2_m(...) __riscv_vsseg5e16_v_u16mf2_m(__VA_ARGS__) -#define vsseg6e16_v_u16mf2_m(...) __riscv_vsseg6e16_v_u16mf2_m(__VA_ARGS__) -#define vsseg7e16_v_u16mf2_m(...) __riscv_vsseg7e16_v_u16mf2_m(__VA_ARGS__) -#define vsseg8e16_v_u16mf2_m(...) __riscv_vsseg8e16_v_u16mf2_m(__VA_ARGS__) -#define vsseg2e16_v_u16m1_m(...) __riscv_vsseg2e16_v_u16m1_m(__VA_ARGS__) -#define vsseg3e16_v_u16m1_m(...) __riscv_vsseg3e16_v_u16m1_m(__VA_ARGS__) -#define vsseg4e16_v_u16m1_m(...) __riscv_vsseg4e16_v_u16m1_m(__VA_ARGS__) -#define vsseg5e16_v_u16m1_m(...) __riscv_vsseg5e16_v_u16m1_m(__VA_ARGS__) -#define vsseg6e16_v_u16m1_m(...) __riscv_vsseg6e16_v_u16m1_m(__VA_ARGS__) -#define vsseg7e16_v_u16m1_m(...) __riscv_vsseg7e16_v_u16m1_m(__VA_ARGS__) -#define vsseg8e16_v_u16m1_m(...) __riscv_vsseg8e16_v_u16m1_m(__VA_ARGS__) -#define vsseg2e16_v_u16m2_m(...) __riscv_vsseg2e16_v_u16m2_m(__VA_ARGS__) -#define vsseg3e16_v_u16m2_m(...) __riscv_vsseg3e16_v_u16m2_m(__VA_ARGS__) -#define vsseg4e16_v_u16m2_m(...) __riscv_vsseg4e16_v_u16m2_m(__VA_ARGS__) -#define vsseg2e16_v_u16m4_m(...) __riscv_vsseg2e16_v_u16m4_m(__VA_ARGS__) -#define vsseg2e32_v_u32mf2_m(...) __riscv_vsseg2e32_v_u32mf2_m(__VA_ARGS__) -#define vsseg3e32_v_u32mf2_m(...) __riscv_vsseg3e32_v_u32mf2_m(__VA_ARGS__) -#define vsseg4e32_v_u32mf2_m(...) __riscv_vsseg4e32_v_u32mf2_m(__VA_ARGS__) -#define vsseg5e32_v_u32mf2_m(...) __riscv_vsseg5e32_v_u32mf2_m(__VA_ARGS__) -#define vsseg6e32_v_u32mf2_m(...) __riscv_vsseg6e32_v_u32mf2_m(__VA_ARGS__) -#define vsseg7e32_v_u32mf2_m(...) __riscv_vsseg7e32_v_u32mf2_m(__VA_ARGS__) -#define vsseg8e32_v_u32mf2_m(...) __riscv_vsseg8e32_v_u32mf2_m(__VA_ARGS__) -#define vsseg2e32_v_u32m1_m(...) __riscv_vsseg2e32_v_u32m1_m(__VA_ARGS__) -#define vsseg3e32_v_u32m1_m(...) __riscv_vsseg3e32_v_u32m1_m(__VA_ARGS__) -#define vsseg4e32_v_u32m1_m(...) __riscv_vsseg4e32_v_u32m1_m(__VA_ARGS__) -#define vsseg5e32_v_u32m1_m(...) __riscv_vsseg5e32_v_u32m1_m(__VA_ARGS__) -#define vsseg6e32_v_u32m1_m(...) __riscv_vsseg6e32_v_u32m1_m(__VA_ARGS__) -#define vsseg7e32_v_u32m1_m(...) __riscv_vsseg7e32_v_u32m1_m(__VA_ARGS__) -#define vsseg8e32_v_u32m1_m(...) __riscv_vsseg8e32_v_u32m1_m(__VA_ARGS__) -#define vsseg2e32_v_u32m2_m(...) __riscv_vsseg2e32_v_u32m2_m(__VA_ARGS__) -#define vsseg3e32_v_u32m2_m(...) __riscv_vsseg3e32_v_u32m2_m(__VA_ARGS__) -#define vsseg4e32_v_u32m2_m(...) __riscv_vsseg4e32_v_u32m2_m(__VA_ARGS__) -#define vsseg2e32_v_u32m4_m(...) __riscv_vsseg2e32_v_u32m4_m(__VA_ARGS__) -#define vsseg2e64_v_u64m1_m(...) __riscv_vsseg2e64_v_u64m1_m(__VA_ARGS__) -#define vsseg3e64_v_u64m1_m(...) __riscv_vsseg3e64_v_u64m1_m(__VA_ARGS__) -#define vsseg4e64_v_u64m1_m(...) __riscv_vsseg4e64_v_u64m1_m(__VA_ARGS__) -#define vsseg5e64_v_u64m1_m(...) __riscv_vsseg5e64_v_u64m1_m(__VA_ARGS__) -#define vsseg6e64_v_u64m1_m(...) __riscv_vsseg6e64_v_u64m1_m(__VA_ARGS__) -#define vsseg7e64_v_u64m1_m(...) __riscv_vsseg7e64_v_u64m1_m(__VA_ARGS__) -#define vsseg8e64_v_u64m1_m(...) __riscv_vsseg8e64_v_u64m1_m(__VA_ARGS__) -#define vsseg2e64_v_u64m2_m(...) __riscv_vsseg2e64_v_u64m2_m(__VA_ARGS__) -#define vsseg3e64_v_u64m2_m(...) __riscv_vsseg3e64_v_u64m2_m(__VA_ARGS__) -#define vsseg4e64_v_u64m2_m(...) __riscv_vsseg4e64_v_u64m2_m(__VA_ARGS__) -#define vsseg2e64_v_u64m4_m(...) __riscv_vsseg2e64_v_u64m4_m(__VA_ARGS__) -#define vlsseg2e16_v_f16mf4(...) __riscv_vlsseg2e16_v_f16mf4(__VA_ARGS__) -#define vlsseg3e16_v_f16mf4(...) __riscv_vlsseg3e16_v_f16mf4(__VA_ARGS__) -#define vlsseg4e16_v_f16mf4(...) __riscv_vlsseg4e16_v_f16mf4(__VA_ARGS__) -#define vlsseg5e16_v_f16mf4(...) __riscv_vlsseg5e16_v_f16mf4(__VA_ARGS__) -#define vlsseg6e16_v_f16mf4(...) __riscv_vlsseg6e16_v_f16mf4(__VA_ARGS__) -#define vlsseg7e16_v_f16mf4(...) __riscv_vlsseg7e16_v_f16mf4(__VA_ARGS__) -#define vlsseg8e16_v_f16mf4(...) __riscv_vlsseg8e16_v_f16mf4(__VA_ARGS__) -#define vlsseg2e16_v_f16mf2(...) __riscv_vlsseg2e16_v_f16mf2(__VA_ARGS__) -#define vlsseg3e16_v_f16mf2(...) __riscv_vlsseg3e16_v_f16mf2(__VA_ARGS__) -#define vlsseg4e16_v_f16mf2(...) __riscv_vlsseg4e16_v_f16mf2(__VA_ARGS__) -#define vlsseg5e16_v_f16mf2(...) __riscv_vlsseg5e16_v_f16mf2(__VA_ARGS__) -#define vlsseg6e16_v_f16mf2(...) __riscv_vlsseg6e16_v_f16mf2(__VA_ARGS__) -#define vlsseg7e16_v_f16mf2(...) __riscv_vlsseg7e16_v_f16mf2(__VA_ARGS__) -#define vlsseg8e16_v_f16mf2(...) __riscv_vlsseg8e16_v_f16mf2(__VA_ARGS__) -#define vlsseg2e16_v_f16m1(...) __riscv_vlsseg2e16_v_f16m1(__VA_ARGS__) -#define vlsseg3e16_v_f16m1(...) __riscv_vlsseg3e16_v_f16m1(__VA_ARGS__) -#define vlsseg4e16_v_f16m1(...) __riscv_vlsseg4e16_v_f16m1(__VA_ARGS__) -#define vlsseg5e16_v_f16m1(...) __riscv_vlsseg5e16_v_f16m1(__VA_ARGS__) -#define vlsseg6e16_v_f16m1(...) __riscv_vlsseg6e16_v_f16m1(__VA_ARGS__) -#define vlsseg7e16_v_f16m1(...) __riscv_vlsseg7e16_v_f16m1(__VA_ARGS__) -#define vlsseg8e16_v_f16m1(...) __riscv_vlsseg8e16_v_f16m1(__VA_ARGS__) -#define vlsseg2e16_v_f16m2(...) __riscv_vlsseg2e16_v_f16m2(__VA_ARGS__) -#define vlsseg3e16_v_f16m2(...) __riscv_vlsseg3e16_v_f16m2(__VA_ARGS__) -#define vlsseg4e16_v_f16m2(...) __riscv_vlsseg4e16_v_f16m2(__VA_ARGS__) -#define vlsseg2e16_v_f16m4(...) __riscv_vlsseg2e16_v_f16m4(__VA_ARGS__) -#define vlsseg2e32_v_f32mf2(...) __riscv_vlsseg2e32_v_f32mf2(__VA_ARGS__) -#define vlsseg3e32_v_f32mf2(...) __riscv_vlsseg3e32_v_f32mf2(__VA_ARGS__) -#define vlsseg4e32_v_f32mf2(...) __riscv_vlsseg4e32_v_f32mf2(__VA_ARGS__) -#define vlsseg5e32_v_f32mf2(...) __riscv_vlsseg5e32_v_f32mf2(__VA_ARGS__) -#define vlsseg6e32_v_f32mf2(...) __riscv_vlsseg6e32_v_f32mf2(__VA_ARGS__) -#define vlsseg7e32_v_f32mf2(...) __riscv_vlsseg7e32_v_f32mf2(__VA_ARGS__) -#define vlsseg8e32_v_f32mf2(...) __riscv_vlsseg8e32_v_f32mf2(__VA_ARGS__) -#define vlsseg2e32_v_f32m1(...) __riscv_vlsseg2e32_v_f32m1(__VA_ARGS__) -#define vlsseg3e32_v_f32m1(...) __riscv_vlsseg3e32_v_f32m1(__VA_ARGS__) -#define vlsseg4e32_v_f32m1(...) __riscv_vlsseg4e32_v_f32m1(__VA_ARGS__) -#define vlsseg5e32_v_f32m1(...) __riscv_vlsseg5e32_v_f32m1(__VA_ARGS__) -#define vlsseg6e32_v_f32m1(...) __riscv_vlsseg6e32_v_f32m1(__VA_ARGS__) -#define vlsseg7e32_v_f32m1(...) __riscv_vlsseg7e32_v_f32m1(__VA_ARGS__) -#define vlsseg8e32_v_f32m1(...) __riscv_vlsseg8e32_v_f32m1(__VA_ARGS__) -#define vlsseg2e32_v_f32m2(...) __riscv_vlsseg2e32_v_f32m2(__VA_ARGS__) -#define vlsseg3e32_v_f32m2(...) __riscv_vlsseg3e32_v_f32m2(__VA_ARGS__) -#define vlsseg4e32_v_f32m2(...) __riscv_vlsseg4e32_v_f32m2(__VA_ARGS__) -#define vlsseg2e32_v_f32m4(...) __riscv_vlsseg2e32_v_f32m4(__VA_ARGS__) -#define vlsseg2e64_v_f64m1(...) __riscv_vlsseg2e64_v_f64m1(__VA_ARGS__) -#define vlsseg3e64_v_f64m1(...) __riscv_vlsseg3e64_v_f64m1(__VA_ARGS__) -#define vlsseg4e64_v_f64m1(...) __riscv_vlsseg4e64_v_f64m1(__VA_ARGS__) -#define vlsseg5e64_v_f64m1(...) __riscv_vlsseg5e64_v_f64m1(__VA_ARGS__) -#define vlsseg6e64_v_f64m1(...) __riscv_vlsseg6e64_v_f64m1(__VA_ARGS__) -#define vlsseg7e64_v_f64m1(...) __riscv_vlsseg7e64_v_f64m1(__VA_ARGS__) -#define vlsseg8e64_v_f64m1(...) __riscv_vlsseg8e64_v_f64m1(__VA_ARGS__) -#define vlsseg2e64_v_f64m2(...) __riscv_vlsseg2e64_v_f64m2(__VA_ARGS__) -#define vlsseg3e64_v_f64m2(...) __riscv_vlsseg3e64_v_f64m2(__VA_ARGS__) -#define vlsseg4e64_v_f64m2(...) __riscv_vlsseg4e64_v_f64m2(__VA_ARGS__) -#define vlsseg2e64_v_f64m4(...) __riscv_vlsseg2e64_v_f64m4(__VA_ARGS__) -#define vlsseg2e8_v_i8mf8(...) __riscv_vlsseg2e8_v_i8mf8(__VA_ARGS__) -#define vlsseg3e8_v_i8mf8(...) __riscv_vlsseg3e8_v_i8mf8(__VA_ARGS__) -#define vlsseg4e8_v_i8mf8(...) __riscv_vlsseg4e8_v_i8mf8(__VA_ARGS__) -#define vlsseg5e8_v_i8mf8(...) __riscv_vlsseg5e8_v_i8mf8(__VA_ARGS__) -#define vlsseg6e8_v_i8mf8(...) __riscv_vlsseg6e8_v_i8mf8(__VA_ARGS__) -#define vlsseg7e8_v_i8mf8(...) __riscv_vlsseg7e8_v_i8mf8(__VA_ARGS__) -#define vlsseg8e8_v_i8mf8(...) __riscv_vlsseg8e8_v_i8mf8(__VA_ARGS__) -#define vlsseg2e8_v_i8mf4(...) __riscv_vlsseg2e8_v_i8mf4(__VA_ARGS__) -#define vlsseg3e8_v_i8mf4(...) __riscv_vlsseg3e8_v_i8mf4(__VA_ARGS__) -#define vlsseg4e8_v_i8mf4(...) __riscv_vlsseg4e8_v_i8mf4(__VA_ARGS__) -#define vlsseg5e8_v_i8mf4(...) __riscv_vlsseg5e8_v_i8mf4(__VA_ARGS__) -#define vlsseg6e8_v_i8mf4(...) __riscv_vlsseg6e8_v_i8mf4(__VA_ARGS__) -#define vlsseg7e8_v_i8mf4(...) __riscv_vlsseg7e8_v_i8mf4(__VA_ARGS__) -#define vlsseg8e8_v_i8mf4(...) __riscv_vlsseg8e8_v_i8mf4(__VA_ARGS__) -#define vlsseg2e8_v_i8mf2(...) __riscv_vlsseg2e8_v_i8mf2(__VA_ARGS__) -#define vlsseg3e8_v_i8mf2(...) __riscv_vlsseg3e8_v_i8mf2(__VA_ARGS__) -#define vlsseg4e8_v_i8mf2(...) __riscv_vlsseg4e8_v_i8mf2(__VA_ARGS__) -#define vlsseg5e8_v_i8mf2(...) __riscv_vlsseg5e8_v_i8mf2(__VA_ARGS__) -#define vlsseg6e8_v_i8mf2(...) __riscv_vlsseg6e8_v_i8mf2(__VA_ARGS__) -#define vlsseg7e8_v_i8mf2(...) __riscv_vlsseg7e8_v_i8mf2(__VA_ARGS__) -#define vlsseg8e8_v_i8mf2(...) __riscv_vlsseg8e8_v_i8mf2(__VA_ARGS__) -#define vlsseg2e8_v_i8m1(...) __riscv_vlsseg2e8_v_i8m1(__VA_ARGS__) -#define vlsseg3e8_v_i8m1(...) __riscv_vlsseg3e8_v_i8m1(__VA_ARGS__) -#define vlsseg4e8_v_i8m1(...) __riscv_vlsseg4e8_v_i8m1(__VA_ARGS__) -#define vlsseg5e8_v_i8m1(...) __riscv_vlsseg5e8_v_i8m1(__VA_ARGS__) -#define vlsseg6e8_v_i8m1(...) __riscv_vlsseg6e8_v_i8m1(__VA_ARGS__) -#define vlsseg7e8_v_i8m1(...) __riscv_vlsseg7e8_v_i8m1(__VA_ARGS__) -#define vlsseg8e8_v_i8m1(...) __riscv_vlsseg8e8_v_i8m1(__VA_ARGS__) -#define vlsseg2e8_v_i8m2(...) __riscv_vlsseg2e8_v_i8m2(__VA_ARGS__) -#define vlsseg3e8_v_i8m2(...) __riscv_vlsseg3e8_v_i8m2(__VA_ARGS__) -#define vlsseg4e8_v_i8m2(...) __riscv_vlsseg4e8_v_i8m2(__VA_ARGS__) -#define vlsseg2e8_v_i8m4(...) __riscv_vlsseg2e8_v_i8m4(__VA_ARGS__) -#define vlsseg2e16_v_i16mf4(...) __riscv_vlsseg2e16_v_i16mf4(__VA_ARGS__) -#define vlsseg3e16_v_i16mf4(...) __riscv_vlsseg3e16_v_i16mf4(__VA_ARGS__) -#define vlsseg4e16_v_i16mf4(...) __riscv_vlsseg4e16_v_i16mf4(__VA_ARGS__) -#define vlsseg5e16_v_i16mf4(...) __riscv_vlsseg5e16_v_i16mf4(__VA_ARGS__) -#define vlsseg6e16_v_i16mf4(...) __riscv_vlsseg6e16_v_i16mf4(__VA_ARGS__) -#define vlsseg7e16_v_i16mf4(...) __riscv_vlsseg7e16_v_i16mf4(__VA_ARGS__) -#define vlsseg8e16_v_i16mf4(...) __riscv_vlsseg8e16_v_i16mf4(__VA_ARGS__) -#define vlsseg2e16_v_i16mf2(...) __riscv_vlsseg2e16_v_i16mf2(__VA_ARGS__) -#define vlsseg3e16_v_i16mf2(...) __riscv_vlsseg3e16_v_i16mf2(__VA_ARGS__) -#define vlsseg4e16_v_i16mf2(...) __riscv_vlsseg4e16_v_i16mf2(__VA_ARGS__) -#define vlsseg5e16_v_i16mf2(...) __riscv_vlsseg5e16_v_i16mf2(__VA_ARGS__) -#define vlsseg6e16_v_i16mf2(...) __riscv_vlsseg6e16_v_i16mf2(__VA_ARGS__) -#define vlsseg7e16_v_i16mf2(...) __riscv_vlsseg7e16_v_i16mf2(__VA_ARGS__) -#define vlsseg8e16_v_i16mf2(...) __riscv_vlsseg8e16_v_i16mf2(__VA_ARGS__) -#define vlsseg2e16_v_i16m1(...) __riscv_vlsseg2e16_v_i16m1(__VA_ARGS__) -#define vlsseg3e16_v_i16m1(...) __riscv_vlsseg3e16_v_i16m1(__VA_ARGS__) -#define vlsseg4e16_v_i16m1(...) __riscv_vlsseg4e16_v_i16m1(__VA_ARGS__) -#define vlsseg5e16_v_i16m1(...) __riscv_vlsseg5e16_v_i16m1(__VA_ARGS__) -#define vlsseg6e16_v_i16m1(...) __riscv_vlsseg6e16_v_i16m1(__VA_ARGS__) -#define vlsseg7e16_v_i16m1(...) __riscv_vlsseg7e16_v_i16m1(__VA_ARGS__) -#define vlsseg8e16_v_i16m1(...) __riscv_vlsseg8e16_v_i16m1(__VA_ARGS__) -#define vlsseg2e16_v_i16m2(...) __riscv_vlsseg2e16_v_i16m2(__VA_ARGS__) -#define vlsseg3e16_v_i16m2(...) __riscv_vlsseg3e16_v_i16m2(__VA_ARGS__) -#define vlsseg4e16_v_i16m2(...) __riscv_vlsseg4e16_v_i16m2(__VA_ARGS__) -#define vlsseg2e16_v_i16m4(...) __riscv_vlsseg2e16_v_i16m4(__VA_ARGS__) -#define vlsseg2e32_v_i32mf2(...) __riscv_vlsseg2e32_v_i32mf2(__VA_ARGS__) -#define vlsseg3e32_v_i32mf2(...) __riscv_vlsseg3e32_v_i32mf2(__VA_ARGS__) -#define vlsseg4e32_v_i32mf2(...) __riscv_vlsseg4e32_v_i32mf2(__VA_ARGS__) -#define vlsseg5e32_v_i32mf2(...) __riscv_vlsseg5e32_v_i32mf2(__VA_ARGS__) -#define vlsseg6e32_v_i32mf2(...) __riscv_vlsseg6e32_v_i32mf2(__VA_ARGS__) -#define vlsseg7e32_v_i32mf2(...) __riscv_vlsseg7e32_v_i32mf2(__VA_ARGS__) -#define vlsseg8e32_v_i32mf2(...) __riscv_vlsseg8e32_v_i32mf2(__VA_ARGS__) -#define vlsseg2e32_v_i32m1(...) __riscv_vlsseg2e32_v_i32m1(__VA_ARGS__) -#define vlsseg3e32_v_i32m1(...) __riscv_vlsseg3e32_v_i32m1(__VA_ARGS__) -#define vlsseg4e32_v_i32m1(...) __riscv_vlsseg4e32_v_i32m1(__VA_ARGS__) -#define vlsseg5e32_v_i32m1(...) __riscv_vlsseg5e32_v_i32m1(__VA_ARGS__) -#define vlsseg6e32_v_i32m1(...) __riscv_vlsseg6e32_v_i32m1(__VA_ARGS__) -#define vlsseg7e32_v_i32m1(...) __riscv_vlsseg7e32_v_i32m1(__VA_ARGS__) -#define vlsseg8e32_v_i32m1(...) __riscv_vlsseg8e32_v_i32m1(__VA_ARGS__) -#define vlsseg2e32_v_i32m2(...) __riscv_vlsseg2e32_v_i32m2(__VA_ARGS__) -#define vlsseg3e32_v_i32m2(...) __riscv_vlsseg3e32_v_i32m2(__VA_ARGS__) -#define vlsseg4e32_v_i32m2(...) __riscv_vlsseg4e32_v_i32m2(__VA_ARGS__) -#define vlsseg2e32_v_i32m4(...) __riscv_vlsseg2e32_v_i32m4(__VA_ARGS__) -#define vlsseg2e64_v_i64m1(...) __riscv_vlsseg2e64_v_i64m1(__VA_ARGS__) -#define vlsseg3e64_v_i64m1(...) __riscv_vlsseg3e64_v_i64m1(__VA_ARGS__) -#define vlsseg4e64_v_i64m1(...) __riscv_vlsseg4e64_v_i64m1(__VA_ARGS__) -#define vlsseg5e64_v_i64m1(...) __riscv_vlsseg5e64_v_i64m1(__VA_ARGS__) -#define vlsseg6e64_v_i64m1(...) __riscv_vlsseg6e64_v_i64m1(__VA_ARGS__) -#define vlsseg7e64_v_i64m1(...) __riscv_vlsseg7e64_v_i64m1(__VA_ARGS__) -#define vlsseg8e64_v_i64m1(...) __riscv_vlsseg8e64_v_i64m1(__VA_ARGS__) -#define vlsseg2e64_v_i64m2(...) __riscv_vlsseg2e64_v_i64m2(__VA_ARGS__) -#define vlsseg3e64_v_i64m2(...) __riscv_vlsseg3e64_v_i64m2(__VA_ARGS__) -#define vlsseg4e64_v_i64m2(...) __riscv_vlsseg4e64_v_i64m2(__VA_ARGS__) -#define vlsseg2e64_v_i64m4(...) __riscv_vlsseg2e64_v_i64m4(__VA_ARGS__) -#define vlsseg2e8_v_u8mf8(...) __riscv_vlsseg2e8_v_u8mf8(__VA_ARGS__) -#define vlsseg3e8_v_u8mf8(...) __riscv_vlsseg3e8_v_u8mf8(__VA_ARGS__) -#define vlsseg4e8_v_u8mf8(...) __riscv_vlsseg4e8_v_u8mf8(__VA_ARGS__) -#define vlsseg5e8_v_u8mf8(...) __riscv_vlsseg5e8_v_u8mf8(__VA_ARGS__) -#define vlsseg6e8_v_u8mf8(...) __riscv_vlsseg6e8_v_u8mf8(__VA_ARGS__) -#define vlsseg7e8_v_u8mf8(...) __riscv_vlsseg7e8_v_u8mf8(__VA_ARGS__) -#define vlsseg8e8_v_u8mf8(...) __riscv_vlsseg8e8_v_u8mf8(__VA_ARGS__) -#define vlsseg2e8_v_u8mf4(...) __riscv_vlsseg2e8_v_u8mf4(__VA_ARGS__) -#define vlsseg3e8_v_u8mf4(...) __riscv_vlsseg3e8_v_u8mf4(__VA_ARGS__) -#define vlsseg4e8_v_u8mf4(...) __riscv_vlsseg4e8_v_u8mf4(__VA_ARGS__) -#define vlsseg5e8_v_u8mf4(...) __riscv_vlsseg5e8_v_u8mf4(__VA_ARGS__) -#define vlsseg6e8_v_u8mf4(...) __riscv_vlsseg6e8_v_u8mf4(__VA_ARGS__) -#define vlsseg7e8_v_u8mf4(...) __riscv_vlsseg7e8_v_u8mf4(__VA_ARGS__) -#define vlsseg8e8_v_u8mf4(...) __riscv_vlsseg8e8_v_u8mf4(__VA_ARGS__) -#define vlsseg2e8_v_u8mf2(...) __riscv_vlsseg2e8_v_u8mf2(__VA_ARGS__) -#define vlsseg3e8_v_u8mf2(...) __riscv_vlsseg3e8_v_u8mf2(__VA_ARGS__) -#define vlsseg4e8_v_u8mf2(...) __riscv_vlsseg4e8_v_u8mf2(__VA_ARGS__) -#define vlsseg5e8_v_u8mf2(...) __riscv_vlsseg5e8_v_u8mf2(__VA_ARGS__) -#define vlsseg6e8_v_u8mf2(...) __riscv_vlsseg6e8_v_u8mf2(__VA_ARGS__) -#define vlsseg7e8_v_u8mf2(...) __riscv_vlsseg7e8_v_u8mf2(__VA_ARGS__) -#define vlsseg8e8_v_u8mf2(...) __riscv_vlsseg8e8_v_u8mf2(__VA_ARGS__) -#define vlsseg2e8_v_u8m1(...) __riscv_vlsseg2e8_v_u8m1(__VA_ARGS__) -#define vlsseg3e8_v_u8m1(...) __riscv_vlsseg3e8_v_u8m1(__VA_ARGS__) -#define vlsseg4e8_v_u8m1(...) __riscv_vlsseg4e8_v_u8m1(__VA_ARGS__) -#define vlsseg5e8_v_u8m1(...) __riscv_vlsseg5e8_v_u8m1(__VA_ARGS__) -#define vlsseg6e8_v_u8m1(...) __riscv_vlsseg6e8_v_u8m1(__VA_ARGS__) -#define vlsseg7e8_v_u8m1(...) __riscv_vlsseg7e8_v_u8m1(__VA_ARGS__) -#define vlsseg8e8_v_u8m1(...) __riscv_vlsseg8e8_v_u8m1(__VA_ARGS__) -#define vlsseg2e8_v_u8m2(...) __riscv_vlsseg2e8_v_u8m2(__VA_ARGS__) -#define vlsseg3e8_v_u8m2(...) __riscv_vlsseg3e8_v_u8m2(__VA_ARGS__) -#define vlsseg4e8_v_u8m2(...) __riscv_vlsseg4e8_v_u8m2(__VA_ARGS__) -#define vlsseg2e8_v_u8m4(...) __riscv_vlsseg2e8_v_u8m4(__VA_ARGS__) -#define vlsseg2e16_v_u16mf4(...) __riscv_vlsseg2e16_v_u16mf4(__VA_ARGS__) -#define vlsseg3e16_v_u16mf4(...) __riscv_vlsseg3e16_v_u16mf4(__VA_ARGS__) -#define vlsseg4e16_v_u16mf4(...) __riscv_vlsseg4e16_v_u16mf4(__VA_ARGS__) -#define vlsseg5e16_v_u16mf4(...) __riscv_vlsseg5e16_v_u16mf4(__VA_ARGS__) -#define vlsseg6e16_v_u16mf4(...) __riscv_vlsseg6e16_v_u16mf4(__VA_ARGS__) -#define vlsseg7e16_v_u16mf4(...) __riscv_vlsseg7e16_v_u16mf4(__VA_ARGS__) -#define vlsseg8e16_v_u16mf4(...) __riscv_vlsseg8e16_v_u16mf4(__VA_ARGS__) -#define vlsseg2e16_v_u16mf2(...) __riscv_vlsseg2e16_v_u16mf2(__VA_ARGS__) -#define vlsseg3e16_v_u16mf2(...) __riscv_vlsseg3e16_v_u16mf2(__VA_ARGS__) -#define vlsseg4e16_v_u16mf2(...) __riscv_vlsseg4e16_v_u16mf2(__VA_ARGS__) -#define vlsseg5e16_v_u16mf2(...) __riscv_vlsseg5e16_v_u16mf2(__VA_ARGS__) -#define vlsseg6e16_v_u16mf2(...) __riscv_vlsseg6e16_v_u16mf2(__VA_ARGS__) -#define vlsseg7e16_v_u16mf2(...) __riscv_vlsseg7e16_v_u16mf2(__VA_ARGS__) -#define vlsseg8e16_v_u16mf2(...) __riscv_vlsseg8e16_v_u16mf2(__VA_ARGS__) -#define vlsseg2e16_v_u16m1(...) __riscv_vlsseg2e16_v_u16m1(__VA_ARGS__) -#define vlsseg3e16_v_u16m1(...) __riscv_vlsseg3e16_v_u16m1(__VA_ARGS__) -#define vlsseg4e16_v_u16m1(...) __riscv_vlsseg4e16_v_u16m1(__VA_ARGS__) -#define vlsseg5e16_v_u16m1(...) __riscv_vlsseg5e16_v_u16m1(__VA_ARGS__) -#define vlsseg6e16_v_u16m1(...) __riscv_vlsseg6e16_v_u16m1(__VA_ARGS__) -#define vlsseg7e16_v_u16m1(...) __riscv_vlsseg7e16_v_u16m1(__VA_ARGS__) -#define vlsseg8e16_v_u16m1(...) __riscv_vlsseg8e16_v_u16m1(__VA_ARGS__) -#define vlsseg2e16_v_u16m2(...) __riscv_vlsseg2e16_v_u16m2(__VA_ARGS__) -#define vlsseg3e16_v_u16m2(...) __riscv_vlsseg3e16_v_u16m2(__VA_ARGS__) -#define vlsseg4e16_v_u16m2(...) __riscv_vlsseg4e16_v_u16m2(__VA_ARGS__) -#define vlsseg2e16_v_u16m4(...) __riscv_vlsseg2e16_v_u16m4(__VA_ARGS__) -#define vlsseg2e32_v_u32mf2(...) __riscv_vlsseg2e32_v_u32mf2(__VA_ARGS__) -#define vlsseg3e32_v_u32mf2(...) __riscv_vlsseg3e32_v_u32mf2(__VA_ARGS__) -#define vlsseg4e32_v_u32mf2(...) __riscv_vlsseg4e32_v_u32mf2(__VA_ARGS__) -#define vlsseg5e32_v_u32mf2(...) __riscv_vlsseg5e32_v_u32mf2(__VA_ARGS__) -#define vlsseg6e32_v_u32mf2(...) __riscv_vlsseg6e32_v_u32mf2(__VA_ARGS__) -#define vlsseg7e32_v_u32mf2(...) __riscv_vlsseg7e32_v_u32mf2(__VA_ARGS__) -#define vlsseg8e32_v_u32mf2(...) __riscv_vlsseg8e32_v_u32mf2(__VA_ARGS__) -#define vlsseg2e32_v_u32m1(...) __riscv_vlsseg2e32_v_u32m1(__VA_ARGS__) -#define vlsseg3e32_v_u32m1(...) __riscv_vlsseg3e32_v_u32m1(__VA_ARGS__) -#define vlsseg4e32_v_u32m1(...) __riscv_vlsseg4e32_v_u32m1(__VA_ARGS__) -#define vlsseg5e32_v_u32m1(...) __riscv_vlsseg5e32_v_u32m1(__VA_ARGS__) -#define vlsseg6e32_v_u32m1(...) __riscv_vlsseg6e32_v_u32m1(__VA_ARGS__) -#define vlsseg7e32_v_u32m1(...) __riscv_vlsseg7e32_v_u32m1(__VA_ARGS__) -#define vlsseg8e32_v_u32m1(...) __riscv_vlsseg8e32_v_u32m1(__VA_ARGS__) -#define vlsseg2e32_v_u32m2(...) __riscv_vlsseg2e32_v_u32m2(__VA_ARGS__) -#define vlsseg3e32_v_u32m2(...) __riscv_vlsseg3e32_v_u32m2(__VA_ARGS__) -#define vlsseg4e32_v_u32m2(...) __riscv_vlsseg4e32_v_u32m2(__VA_ARGS__) -#define vlsseg2e32_v_u32m4(...) __riscv_vlsseg2e32_v_u32m4(__VA_ARGS__) -#define vlsseg2e64_v_u64m1(...) __riscv_vlsseg2e64_v_u64m1(__VA_ARGS__) -#define vlsseg3e64_v_u64m1(...) __riscv_vlsseg3e64_v_u64m1(__VA_ARGS__) -#define vlsseg4e64_v_u64m1(...) __riscv_vlsseg4e64_v_u64m1(__VA_ARGS__) -#define vlsseg5e64_v_u64m1(...) __riscv_vlsseg5e64_v_u64m1(__VA_ARGS__) -#define vlsseg6e64_v_u64m1(...) __riscv_vlsseg6e64_v_u64m1(__VA_ARGS__) -#define vlsseg7e64_v_u64m1(...) __riscv_vlsseg7e64_v_u64m1(__VA_ARGS__) -#define vlsseg8e64_v_u64m1(...) __riscv_vlsseg8e64_v_u64m1(__VA_ARGS__) -#define vlsseg2e64_v_u64m2(...) __riscv_vlsseg2e64_v_u64m2(__VA_ARGS__) -#define vlsseg3e64_v_u64m2(...) __riscv_vlsseg3e64_v_u64m2(__VA_ARGS__) -#define vlsseg4e64_v_u64m2(...) __riscv_vlsseg4e64_v_u64m2(__VA_ARGS__) -#define vlsseg2e64_v_u64m4(...) __riscv_vlsseg2e64_v_u64m4(__VA_ARGS__) -// masked functions -#define vlsseg2e16_v_f16mf4_m(...) __riscv_vlsseg2e16_v_f16mf4_tumu(__VA_ARGS__) -#define vlsseg3e16_v_f16mf4_m(...) __riscv_vlsseg3e16_v_f16mf4_tumu(__VA_ARGS__) -#define vlsseg4e16_v_f16mf4_m(...) __riscv_vlsseg4e16_v_f16mf4_tumu(__VA_ARGS__) -#define vlsseg5e16_v_f16mf4_m(...) __riscv_vlsseg5e16_v_f16mf4_tumu(__VA_ARGS__) -#define vlsseg6e16_v_f16mf4_m(...) __riscv_vlsseg6e16_v_f16mf4_tumu(__VA_ARGS__) -#define vlsseg7e16_v_f16mf4_m(...) __riscv_vlsseg7e16_v_f16mf4_tumu(__VA_ARGS__) -#define vlsseg8e16_v_f16mf4_m(...) __riscv_vlsseg8e16_v_f16mf4_tumu(__VA_ARGS__) -#define vlsseg2e16_v_f16mf2_m(...) __riscv_vlsseg2e16_v_f16mf2_tumu(__VA_ARGS__) -#define vlsseg3e16_v_f16mf2_m(...) __riscv_vlsseg3e16_v_f16mf2_tumu(__VA_ARGS__) -#define vlsseg4e16_v_f16mf2_m(...) __riscv_vlsseg4e16_v_f16mf2_tumu(__VA_ARGS__) -#define vlsseg5e16_v_f16mf2_m(...) __riscv_vlsseg5e16_v_f16mf2_tumu(__VA_ARGS__) -#define vlsseg6e16_v_f16mf2_m(...) __riscv_vlsseg6e16_v_f16mf2_tumu(__VA_ARGS__) -#define vlsseg7e16_v_f16mf2_m(...) __riscv_vlsseg7e16_v_f16mf2_tumu(__VA_ARGS__) -#define vlsseg8e16_v_f16mf2_m(...) __riscv_vlsseg8e16_v_f16mf2_tumu(__VA_ARGS__) -#define vlsseg2e16_v_f16m1_m(...) __riscv_vlsseg2e16_v_f16m1_tumu(__VA_ARGS__) -#define vlsseg3e16_v_f16m1_m(...) __riscv_vlsseg3e16_v_f16m1_tumu(__VA_ARGS__) -#define vlsseg4e16_v_f16m1_m(...) __riscv_vlsseg4e16_v_f16m1_tumu(__VA_ARGS__) -#define vlsseg5e16_v_f16m1_m(...) __riscv_vlsseg5e16_v_f16m1_tumu(__VA_ARGS__) -#define vlsseg6e16_v_f16m1_m(...) __riscv_vlsseg6e16_v_f16m1_tumu(__VA_ARGS__) -#define vlsseg7e16_v_f16m1_m(...) __riscv_vlsseg7e16_v_f16m1_tumu(__VA_ARGS__) -#define vlsseg8e16_v_f16m1_m(...) __riscv_vlsseg8e16_v_f16m1_tumu(__VA_ARGS__) -#define vlsseg2e16_v_f16m2_m(...) __riscv_vlsseg2e16_v_f16m2_tumu(__VA_ARGS__) -#define vlsseg3e16_v_f16m2_m(...) __riscv_vlsseg3e16_v_f16m2_tumu(__VA_ARGS__) -#define vlsseg4e16_v_f16m2_m(...) __riscv_vlsseg4e16_v_f16m2_tumu(__VA_ARGS__) -#define vlsseg2e16_v_f16m4_m(...) __riscv_vlsseg2e16_v_f16m4_tumu(__VA_ARGS__) -#define vlsseg2e32_v_f32mf2_m(...) __riscv_vlsseg2e32_v_f32mf2_tumu(__VA_ARGS__) -#define vlsseg3e32_v_f32mf2_m(...) __riscv_vlsseg3e32_v_f32mf2_tumu(__VA_ARGS__) -#define vlsseg4e32_v_f32mf2_m(...) __riscv_vlsseg4e32_v_f32mf2_tumu(__VA_ARGS__) -#define vlsseg5e32_v_f32mf2_m(...) __riscv_vlsseg5e32_v_f32mf2_tumu(__VA_ARGS__) -#define vlsseg6e32_v_f32mf2_m(...) __riscv_vlsseg6e32_v_f32mf2_tumu(__VA_ARGS__) -#define vlsseg7e32_v_f32mf2_m(...) __riscv_vlsseg7e32_v_f32mf2_tumu(__VA_ARGS__) -#define vlsseg8e32_v_f32mf2_m(...) __riscv_vlsseg8e32_v_f32mf2_tumu(__VA_ARGS__) -#define vlsseg2e32_v_f32m1_m(...) __riscv_vlsseg2e32_v_f32m1_tumu(__VA_ARGS__) -#define vlsseg3e32_v_f32m1_m(...) __riscv_vlsseg3e32_v_f32m1_tumu(__VA_ARGS__) -#define vlsseg4e32_v_f32m1_m(...) __riscv_vlsseg4e32_v_f32m1_tumu(__VA_ARGS__) -#define vlsseg5e32_v_f32m1_m(...) __riscv_vlsseg5e32_v_f32m1_tumu(__VA_ARGS__) -#define vlsseg6e32_v_f32m1_m(...) __riscv_vlsseg6e32_v_f32m1_tumu(__VA_ARGS__) -#define vlsseg7e32_v_f32m1_m(...) __riscv_vlsseg7e32_v_f32m1_tumu(__VA_ARGS__) -#define vlsseg8e32_v_f32m1_m(...) __riscv_vlsseg8e32_v_f32m1_tumu(__VA_ARGS__) -#define vlsseg2e32_v_f32m2_m(...) __riscv_vlsseg2e32_v_f32m2_tumu(__VA_ARGS__) -#define vlsseg3e32_v_f32m2_m(...) __riscv_vlsseg3e32_v_f32m2_tumu(__VA_ARGS__) -#define vlsseg4e32_v_f32m2_m(...) __riscv_vlsseg4e32_v_f32m2_tumu(__VA_ARGS__) -#define vlsseg2e32_v_f32m4_m(...) __riscv_vlsseg2e32_v_f32m4_tumu(__VA_ARGS__) -#define vlsseg2e64_v_f64m1_m(...) __riscv_vlsseg2e64_v_f64m1_tumu(__VA_ARGS__) -#define vlsseg3e64_v_f64m1_m(...) __riscv_vlsseg3e64_v_f64m1_tumu(__VA_ARGS__) -#define vlsseg4e64_v_f64m1_m(...) __riscv_vlsseg4e64_v_f64m1_tumu(__VA_ARGS__) -#define vlsseg5e64_v_f64m1_m(...) __riscv_vlsseg5e64_v_f64m1_tumu(__VA_ARGS__) -#define vlsseg6e64_v_f64m1_m(...) __riscv_vlsseg6e64_v_f64m1_tumu(__VA_ARGS__) -#define vlsseg7e64_v_f64m1_m(...) __riscv_vlsseg7e64_v_f64m1_tumu(__VA_ARGS__) -#define vlsseg8e64_v_f64m1_m(...) __riscv_vlsseg8e64_v_f64m1_tumu(__VA_ARGS__) -#define vlsseg2e64_v_f64m2_m(...) __riscv_vlsseg2e64_v_f64m2_tumu(__VA_ARGS__) -#define vlsseg3e64_v_f64m2_m(...) __riscv_vlsseg3e64_v_f64m2_tumu(__VA_ARGS__) -#define vlsseg4e64_v_f64m2_m(...) __riscv_vlsseg4e64_v_f64m2_tumu(__VA_ARGS__) -#define vlsseg2e64_v_f64m4_m(...) __riscv_vlsseg2e64_v_f64m4_tumu(__VA_ARGS__) -#define vlsseg2e8_v_i8mf8_m(...) __riscv_vlsseg2e8_v_i8mf8_tumu(__VA_ARGS__) -#define vlsseg3e8_v_i8mf8_m(...) __riscv_vlsseg3e8_v_i8mf8_tumu(__VA_ARGS__) -#define vlsseg4e8_v_i8mf8_m(...) __riscv_vlsseg4e8_v_i8mf8_tumu(__VA_ARGS__) -#define vlsseg5e8_v_i8mf8_m(...) __riscv_vlsseg5e8_v_i8mf8_tumu(__VA_ARGS__) -#define vlsseg6e8_v_i8mf8_m(...) __riscv_vlsseg6e8_v_i8mf8_tumu(__VA_ARGS__) -#define vlsseg7e8_v_i8mf8_m(...) __riscv_vlsseg7e8_v_i8mf8_tumu(__VA_ARGS__) -#define vlsseg8e8_v_i8mf8_m(...) __riscv_vlsseg8e8_v_i8mf8_tumu(__VA_ARGS__) -#define vlsseg2e8_v_i8mf4_m(...) __riscv_vlsseg2e8_v_i8mf4_tumu(__VA_ARGS__) -#define vlsseg3e8_v_i8mf4_m(...) __riscv_vlsseg3e8_v_i8mf4_tumu(__VA_ARGS__) -#define vlsseg4e8_v_i8mf4_m(...) __riscv_vlsseg4e8_v_i8mf4_tumu(__VA_ARGS__) -#define vlsseg5e8_v_i8mf4_m(...) __riscv_vlsseg5e8_v_i8mf4_tumu(__VA_ARGS__) -#define vlsseg6e8_v_i8mf4_m(...) __riscv_vlsseg6e8_v_i8mf4_tumu(__VA_ARGS__) -#define vlsseg7e8_v_i8mf4_m(...) __riscv_vlsseg7e8_v_i8mf4_tumu(__VA_ARGS__) -#define vlsseg8e8_v_i8mf4_m(...) __riscv_vlsseg8e8_v_i8mf4_tumu(__VA_ARGS__) -#define vlsseg2e8_v_i8mf2_m(...) __riscv_vlsseg2e8_v_i8mf2_tumu(__VA_ARGS__) -#define vlsseg3e8_v_i8mf2_m(...) __riscv_vlsseg3e8_v_i8mf2_tumu(__VA_ARGS__) -#define vlsseg4e8_v_i8mf2_m(...) __riscv_vlsseg4e8_v_i8mf2_tumu(__VA_ARGS__) -#define vlsseg5e8_v_i8mf2_m(...) __riscv_vlsseg5e8_v_i8mf2_tumu(__VA_ARGS__) -#define vlsseg6e8_v_i8mf2_m(...) __riscv_vlsseg6e8_v_i8mf2_tumu(__VA_ARGS__) -#define vlsseg7e8_v_i8mf2_m(...) __riscv_vlsseg7e8_v_i8mf2_tumu(__VA_ARGS__) -#define vlsseg8e8_v_i8mf2_m(...) __riscv_vlsseg8e8_v_i8mf2_tumu(__VA_ARGS__) -#define vlsseg2e8_v_i8m1_m(...) __riscv_vlsseg2e8_v_i8m1_tumu(__VA_ARGS__) -#define vlsseg3e8_v_i8m1_m(...) __riscv_vlsseg3e8_v_i8m1_tumu(__VA_ARGS__) -#define vlsseg4e8_v_i8m1_m(...) __riscv_vlsseg4e8_v_i8m1_tumu(__VA_ARGS__) -#define vlsseg5e8_v_i8m1_m(...) __riscv_vlsseg5e8_v_i8m1_tumu(__VA_ARGS__) -#define vlsseg6e8_v_i8m1_m(...) __riscv_vlsseg6e8_v_i8m1_tumu(__VA_ARGS__) -#define vlsseg7e8_v_i8m1_m(...) __riscv_vlsseg7e8_v_i8m1_tumu(__VA_ARGS__) -#define vlsseg8e8_v_i8m1_m(...) __riscv_vlsseg8e8_v_i8m1_tumu(__VA_ARGS__) -#define vlsseg2e8_v_i8m2_m(...) __riscv_vlsseg2e8_v_i8m2_tumu(__VA_ARGS__) -#define vlsseg3e8_v_i8m2_m(...) __riscv_vlsseg3e8_v_i8m2_tumu(__VA_ARGS__) -#define vlsseg4e8_v_i8m2_m(...) __riscv_vlsseg4e8_v_i8m2_tumu(__VA_ARGS__) -#define vlsseg2e8_v_i8m4_m(...) __riscv_vlsseg2e8_v_i8m4_tumu(__VA_ARGS__) -#define vlsseg2e16_v_i16mf4_m(...) __riscv_vlsseg2e16_v_i16mf4_tumu(__VA_ARGS__) -#define vlsseg3e16_v_i16mf4_m(...) __riscv_vlsseg3e16_v_i16mf4_tumu(__VA_ARGS__) -#define vlsseg4e16_v_i16mf4_m(...) __riscv_vlsseg4e16_v_i16mf4_tumu(__VA_ARGS__) -#define vlsseg5e16_v_i16mf4_m(...) __riscv_vlsseg5e16_v_i16mf4_tumu(__VA_ARGS__) -#define vlsseg6e16_v_i16mf4_m(...) __riscv_vlsseg6e16_v_i16mf4_tumu(__VA_ARGS__) -#define vlsseg7e16_v_i16mf4_m(...) __riscv_vlsseg7e16_v_i16mf4_tumu(__VA_ARGS__) -#define vlsseg8e16_v_i16mf4_m(...) __riscv_vlsseg8e16_v_i16mf4_tumu(__VA_ARGS__) -#define vlsseg2e16_v_i16mf2_m(...) __riscv_vlsseg2e16_v_i16mf2_tumu(__VA_ARGS__) -#define vlsseg3e16_v_i16mf2_m(...) __riscv_vlsseg3e16_v_i16mf2_tumu(__VA_ARGS__) -#define vlsseg4e16_v_i16mf2_m(...) __riscv_vlsseg4e16_v_i16mf2_tumu(__VA_ARGS__) -#define vlsseg5e16_v_i16mf2_m(...) __riscv_vlsseg5e16_v_i16mf2_tumu(__VA_ARGS__) -#define vlsseg6e16_v_i16mf2_m(...) __riscv_vlsseg6e16_v_i16mf2_tumu(__VA_ARGS__) -#define vlsseg7e16_v_i16mf2_m(...) __riscv_vlsseg7e16_v_i16mf2_tumu(__VA_ARGS__) -#define vlsseg8e16_v_i16mf2_m(...) __riscv_vlsseg8e16_v_i16mf2_tumu(__VA_ARGS__) -#define vlsseg2e16_v_i16m1_m(...) __riscv_vlsseg2e16_v_i16m1_tumu(__VA_ARGS__) -#define vlsseg3e16_v_i16m1_m(...) __riscv_vlsseg3e16_v_i16m1_tumu(__VA_ARGS__) -#define vlsseg4e16_v_i16m1_m(...) __riscv_vlsseg4e16_v_i16m1_tumu(__VA_ARGS__) -#define vlsseg5e16_v_i16m1_m(...) __riscv_vlsseg5e16_v_i16m1_tumu(__VA_ARGS__) -#define vlsseg6e16_v_i16m1_m(...) __riscv_vlsseg6e16_v_i16m1_tumu(__VA_ARGS__) -#define vlsseg7e16_v_i16m1_m(...) __riscv_vlsseg7e16_v_i16m1_tumu(__VA_ARGS__) -#define vlsseg8e16_v_i16m1_m(...) __riscv_vlsseg8e16_v_i16m1_tumu(__VA_ARGS__) -#define vlsseg2e16_v_i16m2_m(...) __riscv_vlsseg2e16_v_i16m2_tumu(__VA_ARGS__) -#define vlsseg3e16_v_i16m2_m(...) __riscv_vlsseg3e16_v_i16m2_tumu(__VA_ARGS__) -#define vlsseg4e16_v_i16m2_m(...) __riscv_vlsseg4e16_v_i16m2_tumu(__VA_ARGS__) -#define vlsseg2e16_v_i16m4_m(...) __riscv_vlsseg2e16_v_i16m4_tumu(__VA_ARGS__) -#define vlsseg2e32_v_i32mf2_m(...) __riscv_vlsseg2e32_v_i32mf2_tumu(__VA_ARGS__) -#define vlsseg3e32_v_i32mf2_m(...) __riscv_vlsseg3e32_v_i32mf2_tumu(__VA_ARGS__) -#define vlsseg4e32_v_i32mf2_m(...) __riscv_vlsseg4e32_v_i32mf2_tumu(__VA_ARGS__) -#define vlsseg5e32_v_i32mf2_m(...) __riscv_vlsseg5e32_v_i32mf2_tumu(__VA_ARGS__) -#define vlsseg6e32_v_i32mf2_m(...) __riscv_vlsseg6e32_v_i32mf2_tumu(__VA_ARGS__) -#define vlsseg7e32_v_i32mf2_m(...) __riscv_vlsseg7e32_v_i32mf2_tumu(__VA_ARGS__) -#define vlsseg8e32_v_i32mf2_m(...) __riscv_vlsseg8e32_v_i32mf2_tumu(__VA_ARGS__) -#define vlsseg2e32_v_i32m1_m(...) __riscv_vlsseg2e32_v_i32m1_tumu(__VA_ARGS__) -#define vlsseg3e32_v_i32m1_m(...) __riscv_vlsseg3e32_v_i32m1_tumu(__VA_ARGS__) -#define vlsseg4e32_v_i32m1_m(...) __riscv_vlsseg4e32_v_i32m1_tumu(__VA_ARGS__) -#define vlsseg5e32_v_i32m1_m(...) __riscv_vlsseg5e32_v_i32m1_tumu(__VA_ARGS__) -#define vlsseg6e32_v_i32m1_m(...) __riscv_vlsseg6e32_v_i32m1_tumu(__VA_ARGS__) -#define vlsseg7e32_v_i32m1_m(...) __riscv_vlsseg7e32_v_i32m1_tumu(__VA_ARGS__) -#define vlsseg8e32_v_i32m1_m(...) __riscv_vlsseg8e32_v_i32m1_tumu(__VA_ARGS__) -#define vlsseg2e32_v_i32m2_m(...) __riscv_vlsseg2e32_v_i32m2_tumu(__VA_ARGS__) -#define vlsseg3e32_v_i32m2_m(...) __riscv_vlsseg3e32_v_i32m2_tumu(__VA_ARGS__) -#define vlsseg4e32_v_i32m2_m(...) __riscv_vlsseg4e32_v_i32m2_tumu(__VA_ARGS__) -#define vlsseg2e32_v_i32m4_m(...) __riscv_vlsseg2e32_v_i32m4_tumu(__VA_ARGS__) -#define vlsseg2e64_v_i64m1_m(...) __riscv_vlsseg2e64_v_i64m1_tumu(__VA_ARGS__) -#define vlsseg3e64_v_i64m1_m(...) __riscv_vlsseg3e64_v_i64m1_tumu(__VA_ARGS__) -#define vlsseg4e64_v_i64m1_m(...) __riscv_vlsseg4e64_v_i64m1_tumu(__VA_ARGS__) -#define vlsseg5e64_v_i64m1_m(...) __riscv_vlsseg5e64_v_i64m1_tumu(__VA_ARGS__) -#define vlsseg6e64_v_i64m1_m(...) __riscv_vlsseg6e64_v_i64m1_tumu(__VA_ARGS__) -#define vlsseg7e64_v_i64m1_m(...) __riscv_vlsseg7e64_v_i64m1_tumu(__VA_ARGS__) -#define vlsseg8e64_v_i64m1_m(...) __riscv_vlsseg8e64_v_i64m1_tumu(__VA_ARGS__) -#define vlsseg2e64_v_i64m2_m(...) __riscv_vlsseg2e64_v_i64m2_tumu(__VA_ARGS__) -#define vlsseg3e64_v_i64m2_m(...) __riscv_vlsseg3e64_v_i64m2_tumu(__VA_ARGS__) -#define vlsseg4e64_v_i64m2_m(...) __riscv_vlsseg4e64_v_i64m2_tumu(__VA_ARGS__) -#define vlsseg2e64_v_i64m4_m(...) __riscv_vlsseg2e64_v_i64m4_tumu(__VA_ARGS__) -#define vlsseg2e8_v_u8mf8_m(...) __riscv_vlsseg2e8_v_u8mf8_tumu(__VA_ARGS__) -#define vlsseg3e8_v_u8mf8_m(...) __riscv_vlsseg3e8_v_u8mf8_tumu(__VA_ARGS__) -#define vlsseg4e8_v_u8mf8_m(...) __riscv_vlsseg4e8_v_u8mf8_tumu(__VA_ARGS__) -#define vlsseg5e8_v_u8mf8_m(...) __riscv_vlsseg5e8_v_u8mf8_tumu(__VA_ARGS__) -#define vlsseg6e8_v_u8mf8_m(...) __riscv_vlsseg6e8_v_u8mf8_tumu(__VA_ARGS__) -#define vlsseg7e8_v_u8mf8_m(...) __riscv_vlsseg7e8_v_u8mf8_tumu(__VA_ARGS__) -#define vlsseg8e8_v_u8mf8_m(...) __riscv_vlsseg8e8_v_u8mf8_tumu(__VA_ARGS__) -#define vlsseg2e8_v_u8mf4_m(...) __riscv_vlsseg2e8_v_u8mf4_tumu(__VA_ARGS__) -#define vlsseg3e8_v_u8mf4_m(...) __riscv_vlsseg3e8_v_u8mf4_tumu(__VA_ARGS__) -#define vlsseg4e8_v_u8mf4_m(...) __riscv_vlsseg4e8_v_u8mf4_tumu(__VA_ARGS__) -#define vlsseg5e8_v_u8mf4_m(...) __riscv_vlsseg5e8_v_u8mf4_tumu(__VA_ARGS__) -#define vlsseg6e8_v_u8mf4_m(...) __riscv_vlsseg6e8_v_u8mf4_tumu(__VA_ARGS__) -#define vlsseg7e8_v_u8mf4_m(...) __riscv_vlsseg7e8_v_u8mf4_tumu(__VA_ARGS__) -#define vlsseg8e8_v_u8mf4_m(...) __riscv_vlsseg8e8_v_u8mf4_tumu(__VA_ARGS__) -#define vlsseg2e8_v_u8mf2_m(...) __riscv_vlsseg2e8_v_u8mf2_tumu(__VA_ARGS__) -#define vlsseg3e8_v_u8mf2_m(...) __riscv_vlsseg3e8_v_u8mf2_tumu(__VA_ARGS__) -#define vlsseg4e8_v_u8mf2_m(...) __riscv_vlsseg4e8_v_u8mf2_tumu(__VA_ARGS__) -#define vlsseg5e8_v_u8mf2_m(...) __riscv_vlsseg5e8_v_u8mf2_tumu(__VA_ARGS__) -#define vlsseg6e8_v_u8mf2_m(...) __riscv_vlsseg6e8_v_u8mf2_tumu(__VA_ARGS__) -#define vlsseg7e8_v_u8mf2_m(...) __riscv_vlsseg7e8_v_u8mf2_tumu(__VA_ARGS__) -#define vlsseg8e8_v_u8mf2_m(...) __riscv_vlsseg8e8_v_u8mf2_tumu(__VA_ARGS__) -#define vlsseg2e8_v_u8m1_m(...) __riscv_vlsseg2e8_v_u8m1_tumu(__VA_ARGS__) -#define vlsseg3e8_v_u8m1_m(...) __riscv_vlsseg3e8_v_u8m1_tumu(__VA_ARGS__) -#define vlsseg4e8_v_u8m1_m(...) __riscv_vlsseg4e8_v_u8m1_tumu(__VA_ARGS__) -#define vlsseg5e8_v_u8m1_m(...) __riscv_vlsseg5e8_v_u8m1_tumu(__VA_ARGS__) -#define vlsseg6e8_v_u8m1_m(...) __riscv_vlsseg6e8_v_u8m1_tumu(__VA_ARGS__) -#define vlsseg7e8_v_u8m1_m(...) __riscv_vlsseg7e8_v_u8m1_tumu(__VA_ARGS__) -#define vlsseg8e8_v_u8m1_m(...) __riscv_vlsseg8e8_v_u8m1_tumu(__VA_ARGS__) -#define vlsseg2e8_v_u8m2_m(...) __riscv_vlsseg2e8_v_u8m2_tumu(__VA_ARGS__) -#define vlsseg3e8_v_u8m2_m(...) __riscv_vlsseg3e8_v_u8m2_tumu(__VA_ARGS__) -#define vlsseg4e8_v_u8m2_m(...) __riscv_vlsseg4e8_v_u8m2_tumu(__VA_ARGS__) -#define vlsseg2e8_v_u8m4_m(...) __riscv_vlsseg2e8_v_u8m4_tumu(__VA_ARGS__) -#define vlsseg2e16_v_u16mf4_m(...) __riscv_vlsseg2e16_v_u16mf4_tumu(__VA_ARGS__) -#define vlsseg3e16_v_u16mf4_m(...) __riscv_vlsseg3e16_v_u16mf4_tumu(__VA_ARGS__) -#define vlsseg4e16_v_u16mf4_m(...) __riscv_vlsseg4e16_v_u16mf4_tumu(__VA_ARGS__) -#define vlsseg5e16_v_u16mf4_m(...) __riscv_vlsseg5e16_v_u16mf4_tumu(__VA_ARGS__) -#define vlsseg6e16_v_u16mf4_m(...) __riscv_vlsseg6e16_v_u16mf4_tumu(__VA_ARGS__) -#define vlsseg7e16_v_u16mf4_m(...) __riscv_vlsseg7e16_v_u16mf4_tumu(__VA_ARGS__) -#define vlsseg8e16_v_u16mf4_m(...) __riscv_vlsseg8e16_v_u16mf4_tumu(__VA_ARGS__) -#define vlsseg2e16_v_u16mf2_m(...) __riscv_vlsseg2e16_v_u16mf2_tumu(__VA_ARGS__) -#define vlsseg3e16_v_u16mf2_m(...) __riscv_vlsseg3e16_v_u16mf2_tumu(__VA_ARGS__) -#define vlsseg4e16_v_u16mf2_m(...) __riscv_vlsseg4e16_v_u16mf2_tumu(__VA_ARGS__) -#define vlsseg5e16_v_u16mf2_m(...) __riscv_vlsseg5e16_v_u16mf2_tumu(__VA_ARGS__) -#define vlsseg6e16_v_u16mf2_m(...) __riscv_vlsseg6e16_v_u16mf2_tumu(__VA_ARGS__) -#define vlsseg7e16_v_u16mf2_m(...) __riscv_vlsseg7e16_v_u16mf2_tumu(__VA_ARGS__) -#define vlsseg8e16_v_u16mf2_m(...) __riscv_vlsseg8e16_v_u16mf2_tumu(__VA_ARGS__) -#define vlsseg2e16_v_u16m1_m(...) __riscv_vlsseg2e16_v_u16m1_tumu(__VA_ARGS__) -#define vlsseg3e16_v_u16m1_m(...) __riscv_vlsseg3e16_v_u16m1_tumu(__VA_ARGS__) -#define vlsseg4e16_v_u16m1_m(...) __riscv_vlsseg4e16_v_u16m1_tumu(__VA_ARGS__) -#define vlsseg5e16_v_u16m1_m(...) __riscv_vlsseg5e16_v_u16m1_tumu(__VA_ARGS__) -#define vlsseg6e16_v_u16m1_m(...) __riscv_vlsseg6e16_v_u16m1_tumu(__VA_ARGS__) -#define vlsseg7e16_v_u16m1_m(...) __riscv_vlsseg7e16_v_u16m1_tumu(__VA_ARGS__) -#define vlsseg8e16_v_u16m1_m(...) __riscv_vlsseg8e16_v_u16m1_tumu(__VA_ARGS__) -#define vlsseg2e16_v_u16m2_m(...) __riscv_vlsseg2e16_v_u16m2_tumu(__VA_ARGS__) -#define vlsseg3e16_v_u16m2_m(...) __riscv_vlsseg3e16_v_u16m2_tumu(__VA_ARGS__) -#define vlsseg4e16_v_u16m2_m(...) __riscv_vlsseg4e16_v_u16m2_tumu(__VA_ARGS__) -#define vlsseg2e16_v_u16m4_m(...) __riscv_vlsseg2e16_v_u16m4_tumu(__VA_ARGS__) -#define vlsseg2e32_v_u32mf2_m(...) __riscv_vlsseg2e32_v_u32mf2_tumu(__VA_ARGS__) -#define vlsseg3e32_v_u32mf2_m(...) __riscv_vlsseg3e32_v_u32mf2_tumu(__VA_ARGS__) -#define vlsseg4e32_v_u32mf2_m(...) __riscv_vlsseg4e32_v_u32mf2_tumu(__VA_ARGS__) -#define vlsseg5e32_v_u32mf2_m(...) __riscv_vlsseg5e32_v_u32mf2_tumu(__VA_ARGS__) -#define vlsseg6e32_v_u32mf2_m(...) __riscv_vlsseg6e32_v_u32mf2_tumu(__VA_ARGS__) -#define vlsseg7e32_v_u32mf2_m(...) __riscv_vlsseg7e32_v_u32mf2_tumu(__VA_ARGS__) -#define vlsseg8e32_v_u32mf2_m(...) __riscv_vlsseg8e32_v_u32mf2_tumu(__VA_ARGS__) -#define vlsseg2e32_v_u32m1_m(...) __riscv_vlsseg2e32_v_u32m1_tumu(__VA_ARGS__) -#define vlsseg3e32_v_u32m1_m(...) __riscv_vlsseg3e32_v_u32m1_tumu(__VA_ARGS__) -#define vlsseg4e32_v_u32m1_m(...) __riscv_vlsseg4e32_v_u32m1_tumu(__VA_ARGS__) -#define vlsseg5e32_v_u32m1_m(...) __riscv_vlsseg5e32_v_u32m1_tumu(__VA_ARGS__) -#define vlsseg6e32_v_u32m1_m(...) __riscv_vlsseg6e32_v_u32m1_tumu(__VA_ARGS__) -#define vlsseg7e32_v_u32m1_m(...) __riscv_vlsseg7e32_v_u32m1_tumu(__VA_ARGS__) -#define vlsseg8e32_v_u32m1_m(...) __riscv_vlsseg8e32_v_u32m1_tumu(__VA_ARGS__) -#define vlsseg2e32_v_u32m2_m(...) __riscv_vlsseg2e32_v_u32m2_tumu(__VA_ARGS__) -#define vlsseg3e32_v_u32m2_m(...) __riscv_vlsseg3e32_v_u32m2_tumu(__VA_ARGS__) -#define vlsseg4e32_v_u32m2_m(...) __riscv_vlsseg4e32_v_u32m2_tumu(__VA_ARGS__) -#define vlsseg2e32_v_u32m4_m(...) __riscv_vlsseg2e32_v_u32m4_tumu(__VA_ARGS__) -#define vlsseg2e64_v_u64m1_m(...) __riscv_vlsseg2e64_v_u64m1_tumu(__VA_ARGS__) -#define vlsseg3e64_v_u64m1_m(...) __riscv_vlsseg3e64_v_u64m1_tumu(__VA_ARGS__) -#define vlsseg4e64_v_u64m1_m(...) __riscv_vlsseg4e64_v_u64m1_tumu(__VA_ARGS__) -#define vlsseg5e64_v_u64m1_m(...) __riscv_vlsseg5e64_v_u64m1_tumu(__VA_ARGS__) -#define vlsseg6e64_v_u64m1_m(...) __riscv_vlsseg6e64_v_u64m1_tumu(__VA_ARGS__) -#define vlsseg7e64_v_u64m1_m(...) __riscv_vlsseg7e64_v_u64m1_tumu(__VA_ARGS__) -#define vlsseg8e64_v_u64m1_m(...) __riscv_vlsseg8e64_v_u64m1_tumu(__VA_ARGS__) -#define vlsseg2e64_v_u64m2_m(...) __riscv_vlsseg2e64_v_u64m2_tumu(__VA_ARGS__) -#define vlsseg3e64_v_u64m2_m(...) __riscv_vlsseg3e64_v_u64m2_tumu(__VA_ARGS__) -#define vlsseg4e64_v_u64m2_m(...) __riscv_vlsseg4e64_v_u64m2_tumu(__VA_ARGS__) -#define vlsseg2e64_v_u64m4_m(...) __riscv_vlsseg2e64_v_u64m4_tumu(__VA_ARGS__) -#define vssseg2e16_v_f16mf4(...) __riscv_vssseg2e16_v_f16mf4(__VA_ARGS__) -#define vssseg3e16_v_f16mf4(...) __riscv_vssseg3e16_v_f16mf4(__VA_ARGS__) -#define vssseg4e16_v_f16mf4(...) __riscv_vssseg4e16_v_f16mf4(__VA_ARGS__) -#define vssseg5e16_v_f16mf4(...) __riscv_vssseg5e16_v_f16mf4(__VA_ARGS__) -#define vssseg6e16_v_f16mf4(...) __riscv_vssseg6e16_v_f16mf4(__VA_ARGS__) -#define vssseg7e16_v_f16mf4(...) __riscv_vssseg7e16_v_f16mf4(__VA_ARGS__) -#define vssseg8e16_v_f16mf4(...) __riscv_vssseg8e16_v_f16mf4(__VA_ARGS__) -#define vssseg2e16_v_f16mf2(...) __riscv_vssseg2e16_v_f16mf2(__VA_ARGS__) -#define vssseg3e16_v_f16mf2(...) __riscv_vssseg3e16_v_f16mf2(__VA_ARGS__) -#define vssseg4e16_v_f16mf2(...) __riscv_vssseg4e16_v_f16mf2(__VA_ARGS__) -#define vssseg5e16_v_f16mf2(...) __riscv_vssseg5e16_v_f16mf2(__VA_ARGS__) -#define vssseg6e16_v_f16mf2(...) __riscv_vssseg6e16_v_f16mf2(__VA_ARGS__) -#define vssseg7e16_v_f16mf2(...) __riscv_vssseg7e16_v_f16mf2(__VA_ARGS__) -#define vssseg8e16_v_f16mf2(...) __riscv_vssseg8e16_v_f16mf2(__VA_ARGS__) -#define vssseg2e16_v_f16m1(...) __riscv_vssseg2e16_v_f16m1(__VA_ARGS__) -#define vssseg3e16_v_f16m1(...) __riscv_vssseg3e16_v_f16m1(__VA_ARGS__) -#define vssseg4e16_v_f16m1(...) __riscv_vssseg4e16_v_f16m1(__VA_ARGS__) -#define vssseg5e16_v_f16m1(...) __riscv_vssseg5e16_v_f16m1(__VA_ARGS__) -#define vssseg6e16_v_f16m1(...) __riscv_vssseg6e16_v_f16m1(__VA_ARGS__) -#define vssseg7e16_v_f16m1(...) __riscv_vssseg7e16_v_f16m1(__VA_ARGS__) -#define vssseg8e16_v_f16m1(...) __riscv_vssseg8e16_v_f16m1(__VA_ARGS__) -#define vssseg2e16_v_f16m2(...) __riscv_vssseg2e16_v_f16m2(__VA_ARGS__) -#define vssseg3e16_v_f16m2(...) __riscv_vssseg3e16_v_f16m2(__VA_ARGS__) -#define vssseg4e16_v_f16m2(...) __riscv_vssseg4e16_v_f16m2(__VA_ARGS__) -#define vssseg2e16_v_f16m4(...) __riscv_vssseg2e16_v_f16m4(__VA_ARGS__) -#define vssseg2e32_v_f32mf2(...) __riscv_vssseg2e32_v_f32mf2(__VA_ARGS__) -#define vssseg3e32_v_f32mf2(...) __riscv_vssseg3e32_v_f32mf2(__VA_ARGS__) -#define vssseg4e32_v_f32mf2(...) __riscv_vssseg4e32_v_f32mf2(__VA_ARGS__) -#define vssseg5e32_v_f32mf2(...) __riscv_vssseg5e32_v_f32mf2(__VA_ARGS__) -#define vssseg6e32_v_f32mf2(...) __riscv_vssseg6e32_v_f32mf2(__VA_ARGS__) -#define vssseg7e32_v_f32mf2(...) __riscv_vssseg7e32_v_f32mf2(__VA_ARGS__) -#define vssseg8e32_v_f32mf2(...) __riscv_vssseg8e32_v_f32mf2(__VA_ARGS__) -#define vssseg2e32_v_f32m1(...) __riscv_vssseg2e32_v_f32m1(__VA_ARGS__) -#define vssseg3e32_v_f32m1(...) __riscv_vssseg3e32_v_f32m1(__VA_ARGS__) -#define vssseg4e32_v_f32m1(...) __riscv_vssseg4e32_v_f32m1(__VA_ARGS__) -#define vssseg5e32_v_f32m1(...) __riscv_vssseg5e32_v_f32m1(__VA_ARGS__) -#define vssseg6e32_v_f32m1(...) __riscv_vssseg6e32_v_f32m1(__VA_ARGS__) -#define vssseg7e32_v_f32m1(...) __riscv_vssseg7e32_v_f32m1(__VA_ARGS__) -#define vssseg8e32_v_f32m1(...) __riscv_vssseg8e32_v_f32m1(__VA_ARGS__) -#define vssseg2e32_v_f32m2(...) __riscv_vssseg2e32_v_f32m2(__VA_ARGS__) -#define vssseg3e32_v_f32m2(...) __riscv_vssseg3e32_v_f32m2(__VA_ARGS__) -#define vssseg4e32_v_f32m2(...) __riscv_vssseg4e32_v_f32m2(__VA_ARGS__) -#define vssseg2e32_v_f32m4(...) __riscv_vssseg2e32_v_f32m4(__VA_ARGS__) -#define vssseg2e64_v_f64m1(...) __riscv_vssseg2e64_v_f64m1(__VA_ARGS__) -#define vssseg3e64_v_f64m1(...) __riscv_vssseg3e64_v_f64m1(__VA_ARGS__) -#define vssseg4e64_v_f64m1(...) __riscv_vssseg4e64_v_f64m1(__VA_ARGS__) -#define vssseg5e64_v_f64m1(...) __riscv_vssseg5e64_v_f64m1(__VA_ARGS__) -#define vssseg6e64_v_f64m1(...) __riscv_vssseg6e64_v_f64m1(__VA_ARGS__) -#define vssseg7e64_v_f64m1(...) __riscv_vssseg7e64_v_f64m1(__VA_ARGS__) -#define vssseg8e64_v_f64m1(...) __riscv_vssseg8e64_v_f64m1(__VA_ARGS__) -#define vssseg2e64_v_f64m2(...) __riscv_vssseg2e64_v_f64m2(__VA_ARGS__) -#define vssseg3e64_v_f64m2(...) __riscv_vssseg3e64_v_f64m2(__VA_ARGS__) -#define vssseg4e64_v_f64m2(...) __riscv_vssseg4e64_v_f64m2(__VA_ARGS__) -#define vssseg2e64_v_f64m4(...) __riscv_vssseg2e64_v_f64m4(__VA_ARGS__) -#define vssseg2e8_v_i8mf8(...) __riscv_vssseg2e8_v_i8mf8(__VA_ARGS__) -#define vssseg3e8_v_i8mf8(...) __riscv_vssseg3e8_v_i8mf8(__VA_ARGS__) -#define vssseg4e8_v_i8mf8(...) __riscv_vssseg4e8_v_i8mf8(__VA_ARGS__) -#define vssseg5e8_v_i8mf8(...) __riscv_vssseg5e8_v_i8mf8(__VA_ARGS__) -#define vssseg6e8_v_i8mf8(...) __riscv_vssseg6e8_v_i8mf8(__VA_ARGS__) -#define vssseg7e8_v_i8mf8(...) __riscv_vssseg7e8_v_i8mf8(__VA_ARGS__) -#define vssseg8e8_v_i8mf8(...) __riscv_vssseg8e8_v_i8mf8(__VA_ARGS__) -#define vssseg2e8_v_i8mf4(...) __riscv_vssseg2e8_v_i8mf4(__VA_ARGS__) -#define vssseg3e8_v_i8mf4(...) __riscv_vssseg3e8_v_i8mf4(__VA_ARGS__) -#define vssseg4e8_v_i8mf4(...) __riscv_vssseg4e8_v_i8mf4(__VA_ARGS__) -#define vssseg5e8_v_i8mf4(...) __riscv_vssseg5e8_v_i8mf4(__VA_ARGS__) -#define vssseg6e8_v_i8mf4(...) __riscv_vssseg6e8_v_i8mf4(__VA_ARGS__) -#define vssseg7e8_v_i8mf4(...) __riscv_vssseg7e8_v_i8mf4(__VA_ARGS__) -#define vssseg8e8_v_i8mf4(...) __riscv_vssseg8e8_v_i8mf4(__VA_ARGS__) -#define vssseg2e8_v_i8mf2(...) __riscv_vssseg2e8_v_i8mf2(__VA_ARGS__) -#define vssseg3e8_v_i8mf2(...) __riscv_vssseg3e8_v_i8mf2(__VA_ARGS__) -#define vssseg4e8_v_i8mf2(...) __riscv_vssseg4e8_v_i8mf2(__VA_ARGS__) -#define vssseg5e8_v_i8mf2(...) __riscv_vssseg5e8_v_i8mf2(__VA_ARGS__) -#define vssseg6e8_v_i8mf2(...) __riscv_vssseg6e8_v_i8mf2(__VA_ARGS__) -#define vssseg7e8_v_i8mf2(...) __riscv_vssseg7e8_v_i8mf2(__VA_ARGS__) -#define vssseg8e8_v_i8mf2(...) __riscv_vssseg8e8_v_i8mf2(__VA_ARGS__) -#define vssseg2e8_v_i8m1(...) __riscv_vssseg2e8_v_i8m1(__VA_ARGS__) -#define vssseg3e8_v_i8m1(...) __riscv_vssseg3e8_v_i8m1(__VA_ARGS__) -#define vssseg4e8_v_i8m1(...) __riscv_vssseg4e8_v_i8m1(__VA_ARGS__) -#define vssseg5e8_v_i8m1(...) __riscv_vssseg5e8_v_i8m1(__VA_ARGS__) -#define vssseg6e8_v_i8m1(...) __riscv_vssseg6e8_v_i8m1(__VA_ARGS__) -#define vssseg7e8_v_i8m1(...) __riscv_vssseg7e8_v_i8m1(__VA_ARGS__) -#define vssseg8e8_v_i8m1(...) __riscv_vssseg8e8_v_i8m1(__VA_ARGS__) -#define vssseg2e8_v_i8m2(...) __riscv_vssseg2e8_v_i8m2(__VA_ARGS__) -#define vssseg3e8_v_i8m2(...) __riscv_vssseg3e8_v_i8m2(__VA_ARGS__) -#define vssseg4e8_v_i8m2(...) __riscv_vssseg4e8_v_i8m2(__VA_ARGS__) -#define vssseg2e8_v_i8m4(...) __riscv_vssseg2e8_v_i8m4(__VA_ARGS__) -#define vssseg2e16_v_i16mf4(...) __riscv_vssseg2e16_v_i16mf4(__VA_ARGS__) -#define vssseg3e16_v_i16mf4(...) __riscv_vssseg3e16_v_i16mf4(__VA_ARGS__) -#define vssseg4e16_v_i16mf4(...) __riscv_vssseg4e16_v_i16mf4(__VA_ARGS__) -#define vssseg5e16_v_i16mf4(...) __riscv_vssseg5e16_v_i16mf4(__VA_ARGS__) -#define vssseg6e16_v_i16mf4(...) __riscv_vssseg6e16_v_i16mf4(__VA_ARGS__) -#define vssseg7e16_v_i16mf4(...) __riscv_vssseg7e16_v_i16mf4(__VA_ARGS__) -#define vssseg8e16_v_i16mf4(...) __riscv_vssseg8e16_v_i16mf4(__VA_ARGS__) -#define vssseg2e16_v_i16mf2(...) __riscv_vssseg2e16_v_i16mf2(__VA_ARGS__) -#define vssseg3e16_v_i16mf2(...) __riscv_vssseg3e16_v_i16mf2(__VA_ARGS__) -#define vssseg4e16_v_i16mf2(...) __riscv_vssseg4e16_v_i16mf2(__VA_ARGS__) -#define vssseg5e16_v_i16mf2(...) __riscv_vssseg5e16_v_i16mf2(__VA_ARGS__) -#define vssseg6e16_v_i16mf2(...) __riscv_vssseg6e16_v_i16mf2(__VA_ARGS__) -#define vssseg7e16_v_i16mf2(...) __riscv_vssseg7e16_v_i16mf2(__VA_ARGS__) -#define vssseg8e16_v_i16mf2(...) __riscv_vssseg8e16_v_i16mf2(__VA_ARGS__) -#define vssseg2e16_v_i16m1(...) __riscv_vssseg2e16_v_i16m1(__VA_ARGS__) -#define vssseg3e16_v_i16m1(...) __riscv_vssseg3e16_v_i16m1(__VA_ARGS__) -#define vssseg4e16_v_i16m1(...) __riscv_vssseg4e16_v_i16m1(__VA_ARGS__) -#define vssseg5e16_v_i16m1(...) __riscv_vssseg5e16_v_i16m1(__VA_ARGS__) -#define vssseg6e16_v_i16m1(...) __riscv_vssseg6e16_v_i16m1(__VA_ARGS__) -#define vssseg7e16_v_i16m1(...) __riscv_vssseg7e16_v_i16m1(__VA_ARGS__) -#define vssseg8e16_v_i16m1(...) __riscv_vssseg8e16_v_i16m1(__VA_ARGS__) -#define vssseg2e16_v_i16m2(...) __riscv_vssseg2e16_v_i16m2(__VA_ARGS__) -#define vssseg3e16_v_i16m2(...) __riscv_vssseg3e16_v_i16m2(__VA_ARGS__) -#define vssseg4e16_v_i16m2(...) __riscv_vssseg4e16_v_i16m2(__VA_ARGS__) -#define vssseg2e16_v_i16m4(...) __riscv_vssseg2e16_v_i16m4(__VA_ARGS__) -#define vssseg2e32_v_i32mf2(...) __riscv_vssseg2e32_v_i32mf2(__VA_ARGS__) -#define vssseg3e32_v_i32mf2(...) __riscv_vssseg3e32_v_i32mf2(__VA_ARGS__) -#define vssseg4e32_v_i32mf2(...) __riscv_vssseg4e32_v_i32mf2(__VA_ARGS__) -#define vssseg5e32_v_i32mf2(...) __riscv_vssseg5e32_v_i32mf2(__VA_ARGS__) -#define vssseg6e32_v_i32mf2(...) __riscv_vssseg6e32_v_i32mf2(__VA_ARGS__) -#define vssseg7e32_v_i32mf2(...) __riscv_vssseg7e32_v_i32mf2(__VA_ARGS__) -#define vssseg8e32_v_i32mf2(...) __riscv_vssseg8e32_v_i32mf2(__VA_ARGS__) -#define vssseg2e32_v_i32m1(...) __riscv_vssseg2e32_v_i32m1(__VA_ARGS__) -#define vssseg3e32_v_i32m1(...) __riscv_vssseg3e32_v_i32m1(__VA_ARGS__) -#define vssseg4e32_v_i32m1(...) __riscv_vssseg4e32_v_i32m1(__VA_ARGS__) -#define vssseg5e32_v_i32m1(...) __riscv_vssseg5e32_v_i32m1(__VA_ARGS__) -#define vssseg6e32_v_i32m1(...) __riscv_vssseg6e32_v_i32m1(__VA_ARGS__) -#define vssseg7e32_v_i32m1(...) __riscv_vssseg7e32_v_i32m1(__VA_ARGS__) -#define vssseg8e32_v_i32m1(...) __riscv_vssseg8e32_v_i32m1(__VA_ARGS__) -#define vssseg2e32_v_i32m2(...) __riscv_vssseg2e32_v_i32m2(__VA_ARGS__) -#define vssseg3e32_v_i32m2(...) __riscv_vssseg3e32_v_i32m2(__VA_ARGS__) -#define vssseg4e32_v_i32m2(...) __riscv_vssseg4e32_v_i32m2(__VA_ARGS__) -#define vssseg2e32_v_i32m4(...) __riscv_vssseg2e32_v_i32m4(__VA_ARGS__) -#define vssseg2e64_v_i64m1(...) __riscv_vssseg2e64_v_i64m1(__VA_ARGS__) -#define vssseg3e64_v_i64m1(...) __riscv_vssseg3e64_v_i64m1(__VA_ARGS__) -#define vssseg4e64_v_i64m1(...) __riscv_vssseg4e64_v_i64m1(__VA_ARGS__) -#define vssseg5e64_v_i64m1(...) __riscv_vssseg5e64_v_i64m1(__VA_ARGS__) -#define vssseg6e64_v_i64m1(...) __riscv_vssseg6e64_v_i64m1(__VA_ARGS__) -#define vssseg7e64_v_i64m1(...) __riscv_vssseg7e64_v_i64m1(__VA_ARGS__) -#define vssseg8e64_v_i64m1(...) __riscv_vssseg8e64_v_i64m1(__VA_ARGS__) -#define vssseg2e64_v_i64m2(...) __riscv_vssseg2e64_v_i64m2(__VA_ARGS__) -#define vssseg3e64_v_i64m2(...) __riscv_vssseg3e64_v_i64m2(__VA_ARGS__) -#define vssseg4e64_v_i64m2(...) __riscv_vssseg4e64_v_i64m2(__VA_ARGS__) -#define vssseg2e64_v_i64m4(...) __riscv_vssseg2e64_v_i64m4(__VA_ARGS__) -#define vssseg2e8_v_u8mf8(...) __riscv_vssseg2e8_v_u8mf8(__VA_ARGS__) -#define vssseg3e8_v_u8mf8(...) __riscv_vssseg3e8_v_u8mf8(__VA_ARGS__) -#define vssseg4e8_v_u8mf8(...) __riscv_vssseg4e8_v_u8mf8(__VA_ARGS__) -#define vssseg5e8_v_u8mf8(...) __riscv_vssseg5e8_v_u8mf8(__VA_ARGS__) -#define vssseg6e8_v_u8mf8(...) __riscv_vssseg6e8_v_u8mf8(__VA_ARGS__) -#define vssseg7e8_v_u8mf8(...) __riscv_vssseg7e8_v_u8mf8(__VA_ARGS__) -#define vssseg8e8_v_u8mf8(...) __riscv_vssseg8e8_v_u8mf8(__VA_ARGS__) -#define vssseg2e8_v_u8mf4(...) __riscv_vssseg2e8_v_u8mf4(__VA_ARGS__) -#define vssseg3e8_v_u8mf4(...) __riscv_vssseg3e8_v_u8mf4(__VA_ARGS__) -#define vssseg4e8_v_u8mf4(...) __riscv_vssseg4e8_v_u8mf4(__VA_ARGS__) -#define vssseg5e8_v_u8mf4(...) __riscv_vssseg5e8_v_u8mf4(__VA_ARGS__) -#define vssseg6e8_v_u8mf4(...) __riscv_vssseg6e8_v_u8mf4(__VA_ARGS__) -#define vssseg7e8_v_u8mf4(...) __riscv_vssseg7e8_v_u8mf4(__VA_ARGS__) -#define vssseg8e8_v_u8mf4(...) __riscv_vssseg8e8_v_u8mf4(__VA_ARGS__) -#define vssseg2e8_v_u8mf2(...) __riscv_vssseg2e8_v_u8mf2(__VA_ARGS__) -#define vssseg3e8_v_u8mf2(...) __riscv_vssseg3e8_v_u8mf2(__VA_ARGS__) -#define vssseg4e8_v_u8mf2(...) __riscv_vssseg4e8_v_u8mf2(__VA_ARGS__) -#define vssseg5e8_v_u8mf2(...) __riscv_vssseg5e8_v_u8mf2(__VA_ARGS__) -#define vssseg6e8_v_u8mf2(...) __riscv_vssseg6e8_v_u8mf2(__VA_ARGS__) -#define vssseg7e8_v_u8mf2(...) __riscv_vssseg7e8_v_u8mf2(__VA_ARGS__) -#define vssseg8e8_v_u8mf2(...) __riscv_vssseg8e8_v_u8mf2(__VA_ARGS__) -#define vssseg2e8_v_u8m1(...) __riscv_vssseg2e8_v_u8m1(__VA_ARGS__) -#define vssseg3e8_v_u8m1(...) __riscv_vssseg3e8_v_u8m1(__VA_ARGS__) -#define vssseg4e8_v_u8m1(...) __riscv_vssseg4e8_v_u8m1(__VA_ARGS__) -#define vssseg5e8_v_u8m1(...) __riscv_vssseg5e8_v_u8m1(__VA_ARGS__) -#define vssseg6e8_v_u8m1(...) __riscv_vssseg6e8_v_u8m1(__VA_ARGS__) -#define vssseg7e8_v_u8m1(...) __riscv_vssseg7e8_v_u8m1(__VA_ARGS__) -#define vssseg8e8_v_u8m1(...) __riscv_vssseg8e8_v_u8m1(__VA_ARGS__) -#define vssseg2e8_v_u8m2(...) __riscv_vssseg2e8_v_u8m2(__VA_ARGS__) -#define vssseg3e8_v_u8m2(...) __riscv_vssseg3e8_v_u8m2(__VA_ARGS__) -#define vssseg4e8_v_u8m2(...) __riscv_vssseg4e8_v_u8m2(__VA_ARGS__) -#define vssseg2e8_v_u8m4(...) __riscv_vssseg2e8_v_u8m4(__VA_ARGS__) -#define vssseg2e16_v_u16mf4(...) __riscv_vssseg2e16_v_u16mf4(__VA_ARGS__) -#define vssseg3e16_v_u16mf4(...) __riscv_vssseg3e16_v_u16mf4(__VA_ARGS__) -#define vssseg4e16_v_u16mf4(...) __riscv_vssseg4e16_v_u16mf4(__VA_ARGS__) -#define vssseg5e16_v_u16mf4(...) __riscv_vssseg5e16_v_u16mf4(__VA_ARGS__) -#define vssseg6e16_v_u16mf4(...) __riscv_vssseg6e16_v_u16mf4(__VA_ARGS__) -#define vssseg7e16_v_u16mf4(...) __riscv_vssseg7e16_v_u16mf4(__VA_ARGS__) -#define vssseg8e16_v_u16mf4(...) __riscv_vssseg8e16_v_u16mf4(__VA_ARGS__) -#define vssseg2e16_v_u16mf2(...) __riscv_vssseg2e16_v_u16mf2(__VA_ARGS__) -#define vssseg3e16_v_u16mf2(...) __riscv_vssseg3e16_v_u16mf2(__VA_ARGS__) -#define vssseg4e16_v_u16mf2(...) __riscv_vssseg4e16_v_u16mf2(__VA_ARGS__) -#define vssseg5e16_v_u16mf2(...) __riscv_vssseg5e16_v_u16mf2(__VA_ARGS__) -#define vssseg6e16_v_u16mf2(...) __riscv_vssseg6e16_v_u16mf2(__VA_ARGS__) -#define vssseg7e16_v_u16mf2(...) __riscv_vssseg7e16_v_u16mf2(__VA_ARGS__) -#define vssseg8e16_v_u16mf2(...) __riscv_vssseg8e16_v_u16mf2(__VA_ARGS__) -#define vssseg2e16_v_u16m1(...) __riscv_vssseg2e16_v_u16m1(__VA_ARGS__) -#define vssseg3e16_v_u16m1(...) __riscv_vssseg3e16_v_u16m1(__VA_ARGS__) -#define vssseg4e16_v_u16m1(...) __riscv_vssseg4e16_v_u16m1(__VA_ARGS__) -#define vssseg5e16_v_u16m1(...) __riscv_vssseg5e16_v_u16m1(__VA_ARGS__) -#define vssseg6e16_v_u16m1(...) __riscv_vssseg6e16_v_u16m1(__VA_ARGS__) -#define vssseg7e16_v_u16m1(...) __riscv_vssseg7e16_v_u16m1(__VA_ARGS__) -#define vssseg8e16_v_u16m1(...) __riscv_vssseg8e16_v_u16m1(__VA_ARGS__) -#define vssseg2e16_v_u16m2(...) __riscv_vssseg2e16_v_u16m2(__VA_ARGS__) -#define vssseg3e16_v_u16m2(...) __riscv_vssseg3e16_v_u16m2(__VA_ARGS__) -#define vssseg4e16_v_u16m2(...) __riscv_vssseg4e16_v_u16m2(__VA_ARGS__) -#define vssseg2e16_v_u16m4(...) __riscv_vssseg2e16_v_u16m4(__VA_ARGS__) -#define vssseg2e32_v_u32mf2(...) __riscv_vssseg2e32_v_u32mf2(__VA_ARGS__) -#define vssseg3e32_v_u32mf2(...) __riscv_vssseg3e32_v_u32mf2(__VA_ARGS__) -#define vssseg4e32_v_u32mf2(...) __riscv_vssseg4e32_v_u32mf2(__VA_ARGS__) -#define vssseg5e32_v_u32mf2(...) __riscv_vssseg5e32_v_u32mf2(__VA_ARGS__) -#define vssseg6e32_v_u32mf2(...) __riscv_vssseg6e32_v_u32mf2(__VA_ARGS__) -#define vssseg7e32_v_u32mf2(...) __riscv_vssseg7e32_v_u32mf2(__VA_ARGS__) -#define vssseg8e32_v_u32mf2(...) __riscv_vssseg8e32_v_u32mf2(__VA_ARGS__) -#define vssseg2e32_v_u32m1(...) __riscv_vssseg2e32_v_u32m1(__VA_ARGS__) -#define vssseg3e32_v_u32m1(...) __riscv_vssseg3e32_v_u32m1(__VA_ARGS__) -#define vssseg4e32_v_u32m1(...) __riscv_vssseg4e32_v_u32m1(__VA_ARGS__) -#define vssseg5e32_v_u32m1(...) __riscv_vssseg5e32_v_u32m1(__VA_ARGS__) -#define vssseg6e32_v_u32m1(...) __riscv_vssseg6e32_v_u32m1(__VA_ARGS__) -#define vssseg7e32_v_u32m1(...) __riscv_vssseg7e32_v_u32m1(__VA_ARGS__) -#define vssseg8e32_v_u32m1(...) __riscv_vssseg8e32_v_u32m1(__VA_ARGS__) -#define vssseg2e32_v_u32m2(...) __riscv_vssseg2e32_v_u32m2(__VA_ARGS__) -#define vssseg3e32_v_u32m2(...) __riscv_vssseg3e32_v_u32m2(__VA_ARGS__) -#define vssseg4e32_v_u32m2(...) __riscv_vssseg4e32_v_u32m2(__VA_ARGS__) -#define vssseg2e32_v_u32m4(...) __riscv_vssseg2e32_v_u32m4(__VA_ARGS__) -#define vssseg2e64_v_u64m1(...) __riscv_vssseg2e64_v_u64m1(__VA_ARGS__) -#define vssseg3e64_v_u64m1(...) __riscv_vssseg3e64_v_u64m1(__VA_ARGS__) -#define vssseg4e64_v_u64m1(...) __riscv_vssseg4e64_v_u64m1(__VA_ARGS__) -#define vssseg5e64_v_u64m1(...) __riscv_vssseg5e64_v_u64m1(__VA_ARGS__) -#define vssseg6e64_v_u64m1(...) __riscv_vssseg6e64_v_u64m1(__VA_ARGS__) -#define vssseg7e64_v_u64m1(...) __riscv_vssseg7e64_v_u64m1(__VA_ARGS__) -#define vssseg8e64_v_u64m1(...) __riscv_vssseg8e64_v_u64m1(__VA_ARGS__) -#define vssseg2e64_v_u64m2(...) __riscv_vssseg2e64_v_u64m2(__VA_ARGS__) -#define vssseg3e64_v_u64m2(...) __riscv_vssseg3e64_v_u64m2(__VA_ARGS__) -#define vssseg4e64_v_u64m2(...) __riscv_vssseg4e64_v_u64m2(__VA_ARGS__) -#define vssseg2e64_v_u64m4(...) __riscv_vssseg2e64_v_u64m4(__VA_ARGS__) -// masked functions -#define vssseg2e16_v_f16mf4_m(...) __riscv_vssseg2e16_v_f16mf4_m(__VA_ARGS__) -#define vssseg3e16_v_f16mf4_m(...) __riscv_vssseg3e16_v_f16mf4_m(__VA_ARGS__) -#define vssseg4e16_v_f16mf4_m(...) __riscv_vssseg4e16_v_f16mf4_m(__VA_ARGS__) -#define vssseg5e16_v_f16mf4_m(...) __riscv_vssseg5e16_v_f16mf4_m(__VA_ARGS__) -#define vssseg6e16_v_f16mf4_m(...) __riscv_vssseg6e16_v_f16mf4_m(__VA_ARGS__) -#define vssseg7e16_v_f16mf4_m(...) __riscv_vssseg7e16_v_f16mf4_m(__VA_ARGS__) -#define vssseg8e16_v_f16mf4_m(...) __riscv_vssseg8e16_v_f16mf4_m(__VA_ARGS__) -#define vssseg2e16_v_f16mf2_m(...) __riscv_vssseg2e16_v_f16mf2_m(__VA_ARGS__) -#define vssseg3e16_v_f16mf2_m(...) __riscv_vssseg3e16_v_f16mf2_m(__VA_ARGS__) -#define vssseg4e16_v_f16mf2_m(...) __riscv_vssseg4e16_v_f16mf2_m(__VA_ARGS__) -#define vssseg5e16_v_f16mf2_m(...) __riscv_vssseg5e16_v_f16mf2_m(__VA_ARGS__) -#define vssseg6e16_v_f16mf2_m(...) __riscv_vssseg6e16_v_f16mf2_m(__VA_ARGS__) -#define vssseg7e16_v_f16mf2_m(...) __riscv_vssseg7e16_v_f16mf2_m(__VA_ARGS__) -#define vssseg8e16_v_f16mf2_m(...) __riscv_vssseg8e16_v_f16mf2_m(__VA_ARGS__) -#define vssseg2e16_v_f16m1_m(...) __riscv_vssseg2e16_v_f16m1_m(__VA_ARGS__) -#define vssseg3e16_v_f16m1_m(...) __riscv_vssseg3e16_v_f16m1_m(__VA_ARGS__) -#define vssseg4e16_v_f16m1_m(...) __riscv_vssseg4e16_v_f16m1_m(__VA_ARGS__) -#define vssseg5e16_v_f16m1_m(...) __riscv_vssseg5e16_v_f16m1_m(__VA_ARGS__) -#define vssseg6e16_v_f16m1_m(...) __riscv_vssseg6e16_v_f16m1_m(__VA_ARGS__) -#define vssseg7e16_v_f16m1_m(...) __riscv_vssseg7e16_v_f16m1_m(__VA_ARGS__) -#define vssseg8e16_v_f16m1_m(...) __riscv_vssseg8e16_v_f16m1_m(__VA_ARGS__) -#define vssseg2e16_v_f16m2_m(...) __riscv_vssseg2e16_v_f16m2_m(__VA_ARGS__) -#define vssseg3e16_v_f16m2_m(...) __riscv_vssseg3e16_v_f16m2_m(__VA_ARGS__) -#define vssseg4e16_v_f16m2_m(...) __riscv_vssseg4e16_v_f16m2_m(__VA_ARGS__) -#define vssseg2e16_v_f16m4_m(...) __riscv_vssseg2e16_v_f16m4_m(__VA_ARGS__) -#define vssseg2e32_v_f32mf2_m(...) __riscv_vssseg2e32_v_f32mf2_m(__VA_ARGS__) -#define vssseg3e32_v_f32mf2_m(...) __riscv_vssseg3e32_v_f32mf2_m(__VA_ARGS__) -#define vssseg4e32_v_f32mf2_m(...) __riscv_vssseg4e32_v_f32mf2_m(__VA_ARGS__) -#define vssseg5e32_v_f32mf2_m(...) __riscv_vssseg5e32_v_f32mf2_m(__VA_ARGS__) -#define vssseg6e32_v_f32mf2_m(...) __riscv_vssseg6e32_v_f32mf2_m(__VA_ARGS__) -#define vssseg7e32_v_f32mf2_m(...) __riscv_vssseg7e32_v_f32mf2_m(__VA_ARGS__) -#define vssseg8e32_v_f32mf2_m(...) __riscv_vssseg8e32_v_f32mf2_m(__VA_ARGS__) -#define vssseg2e32_v_f32m1_m(...) __riscv_vssseg2e32_v_f32m1_m(__VA_ARGS__) -#define vssseg3e32_v_f32m1_m(...) __riscv_vssseg3e32_v_f32m1_m(__VA_ARGS__) -#define vssseg4e32_v_f32m1_m(...) __riscv_vssseg4e32_v_f32m1_m(__VA_ARGS__) -#define vssseg5e32_v_f32m1_m(...) __riscv_vssseg5e32_v_f32m1_m(__VA_ARGS__) -#define vssseg6e32_v_f32m1_m(...) __riscv_vssseg6e32_v_f32m1_m(__VA_ARGS__) -#define vssseg7e32_v_f32m1_m(...) __riscv_vssseg7e32_v_f32m1_m(__VA_ARGS__) -#define vssseg8e32_v_f32m1_m(...) __riscv_vssseg8e32_v_f32m1_m(__VA_ARGS__) -#define vssseg2e32_v_f32m2_m(...) __riscv_vssseg2e32_v_f32m2_m(__VA_ARGS__) -#define vssseg3e32_v_f32m2_m(...) __riscv_vssseg3e32_v_f32m2_m(__VA_ARGS__) -#define vssseg4e32_v_f32m2_m(...) __riscv_vssseg4e32_v_f32m2_m(__VA_ARGS__) -#define vssseg2e32_v_f32m4_m(...) __riscv_vssseg2e32_v_f32m4_m(__VA_ARGS__) -#define vssseg2e64_v_f64m1_m(...) __riscv_vssseg2e64_v_f64m1_m(__VA_ARGS__) -#define vssseg3e64_v_f64m1_m(...) __riscv_vssseg3e64_v_f64m1_m(__VA_ARGS__) -#define vssseg4e64_v_f64m1_m(...) __riscv_vssseg4e64_v_f64m1_m(__VA_ARGS__) -#define vssseg5e64_v_f64m1_m(...) __riscv_vssseg5e64_v_f64m1_m(__VA_ARGS__) -#define vssseg6e64_v_f64m1_m(...) __riscv_vssseg6e64_v_f64m1_m(__VA_ARGS__) -#define vssseg7e64_v_f64m1_m(...) __riscv_vssseg7e64_v_f64m1_m(__VA_ARGS__) -#define vssseg8e64_v_f64m1_m(...) __riscv_vssseg8e64_v_f64m1_m(__VA_ARGS__) -#define vssseg2e64_v_f64m2_m(...) __riscv_vssseg2e64_v_f64m2_m(__VA_ARGS__) -#define vssseg3e64_v_f64m2_m(...) __riscv_vssseg3e64_v_f64m2_m(__VA_ARGS__) -#define vssseg4e64_v_f64m2_m(...) __riscv_vssseg4e64_v_f64m2_m(__VA_ARGS__) -#define vssseg2e64_v_f64m4_m(...) __riscv_vssseg2e64_v_f64m4_m(__VA_ARGS__) -#define vssseg2e8_v_i8mf8_m(...) __riscv_vssseg2e8_v_i8mf8_m(__VA_ARGS__) -#define vssseg3e8_v_i8mf8_m(...) __riscv_vssseg3e8_v_i8mf8_m(__VA_ARGS__) -#define vssseg4e8_v_i8mf8_m(...) __riscv_vssseg4e8_v_i8mf8_m(__VA_ARGS__) -#define vssseg5e8_v_i8mf8_m(...) __riscv_vssseg5e8_v_i8mf8_m(__VA_ARGS__) -#define vssseg6e8_v_i8mf8_m(...) __riscv_vssseg6e8_v_i8mf8_m(__VA_ARGS__) -#define vssseg7e8_v_i8mf8_m(...) __riscv_vssseg7e8_v_i8mf8_m(__VA_ARGS__) -#define vssseg8e8_v_i8mf8_m(...) __riscv_vssseg8e8_v_i8mf8_m(__VA_ARGS__) -#define vssseg2e8_v_i8mf4_m(...) __riscv_vssseg2e8_v_i8mf4_m(__VA_ARGS__) -#define vssseg3e8_v_i8mf4_m(...) __riscv_vssseg3e8_v_i8mf4_m(__VA_ARGS__) -#define vssseg4e8_v_i8mf4_m(...) __riscv_vssseg4e8_v_i8mf4_m(__VA_ARGS__) -#define vssseg5e8_v_i8mf4_m(...) __riscv_vssseg5e8_v_i8mf4_m(__VA_ARGS__) -#define vssseg6e8_v_i8mf4_m(...) __riscv_vssseg6e8_v_i8mf4_m(__VA_ARGS__) -#define vssseg7e8_v_i8mf4_m(...) __riscv_vssseg7e8_v_i8mf4_m(__VA_ARGS__) -#define vssseg8e8_v_i8mf4_m(...) __riscv_vssseg8e8_v_i8mf4_m(__VA_ARGS__) -#define vssseg2e8_v_i8mf2_m(...) __riscv_vssseg2e8_v_i8mf2_m(__VA_ARGS__) -#define vssseg3e8_v_i8mf2_m(...) __riscv_vssseg3e8_v_i8mf2_m(__VA_ARGS__) -#define vssseg4e8_v_i8mf2_m(...) __riscv_vssseg4e8_v_i8mf2_m(__VA_ARGS__) -#define vssseg5e8_v_i8mf2_m(...) __riscv_vssseg5e8_v_i8mf2_m(__VA_ARGS__) -#define vssseg6e8_v_i8mf2_m(...) __riscv_vssseg6e8_v_i8mf2_m(__VA_ARGS__) -#define vssseg7e8_v_i8mf2_m(...) __riscv_vssseg7e8_v_i8mf2_m(__VA_ARGS__) -#define vssseg8e8_v_i8mf2_m(...) __riscv_vssseg8e8_v_i8mf2_m(__VA_ARGS__) -#define vssseg2e8_v_i8m1_m(...) __riscv_vssseg2e8_v_i8m1_m(__VA_ARGS__) -#define vssseg3e8_v_i8m1_m(...) __riscv_vssseg3e8_v_i8m1_m(__VA_ARGS__) -#define vssseg4e8_v_i8m1_m(...) __riscv_vssseg4e8_v_i8m1_m(__VA_ARGS__) -#define vssseg5e8_v_i8m1_m(...) __riscv_vssseg5e8_v_i8m1_m(__VA_ARGS__) -#define vssseg6e8_v_i8m1_m(...) __riscv_vssseg6e8_v_i8m1_m(__VA_ARGS__) -#define vssseg7e8_v_i8m1_m(...) __riscv_vssseg7e8_v_i8m1_m(__VA_ARGS__) -#define vssseg8e8_v_i8m1_m(...) __riscv_vssseg8e8_v_i8m1_m(__VA_ARGS__) -#define vssseg2e8_v_i8m2_m(...) __riscv_vssseg2e8_v_i8m2_m(__VA_ARGS__) -#define vssseg3e8_v_i8m2_m(...) __riscv_vssseg3e8_v_i8m2_m(__VA_ARGS__) -#define vssseg4e8_v_i8m2_m(...) __riscv_vssseg4e8_v_i8m2_m(__VA_ARGS__) -#define vssseg2e8_v_i8m4_m(...) __riscv_vssseg2e8_v_i8m4_m(__VA_ARGS__) -#define vssseg2e16_v_i16mf4_m(...) __riscv_vssseg2e16_v_i16mf4_m(__VA_ARGS__) -#define vssseg3e16_v_i16mf4_m(...) __riscv_vssseg3e16_v_i16mf4_m(__VA_ARGS__) -#define vssseg4e16_v_i16mf4_m(...) __riscv_vssseg4e16_v_i16mf4_m(__VA_ARGS__) -#define vssseg5e16_v_i16mf4_m(...) __riscv_vssseg5e16_v_i16mf4_m(__VA_ARGS__) -#define vssseg6e16_v_i16mf4_m(...) __riscv_vssseg6e16_v_i16mf4_m(__VA_ARGS__) -#define vssseg7e16_v_i16mf4_m(...) __riscv_vssseg7e16_v_i16mf4_m(__VA_ARGS__) -#define vssseg8e16_v_i16mf4_m(...) __riscv_vssseg8e16_v_i16mf4_m(__VA_ARGS__) -#define vssseg2e16_v_i16mf2_m(...) __riscv_vssseg2e16_v_i16mf2_m(__VA_ARGS__) -#define vssseg3e16_v_i16mf2_m(...) __riscv_vssseg3e16_v_i16mf2_m(__VA_ARGS__) -#define vssseg4e16_v_i16mf2_m(...) __riscv_vssseg4e16_v_i16mf2_m(__VA_ARGS__) -#define vssseg5e16_v_i16mf2_m(...) __riscv_vssseg5e16_v_i16mf2_m(__VA_ARGS__) -#define vssseg6e16_v_i16mf2_m(...) __riscv_vssseg6e16_v_i16mf2_m(__VA_ARGS__) -#define vssseg7e16_v_i16mf2_m(...) __riscv_vssseg7e16_v_i16mf2_m(__VA_ARGS__) -#define vssseg8e16_v_i16mf2_m(...) __riscv_vssseg8e16_v_i16mf2_m(__VA_ARGS__) -#define vssseg2e16_v_i16m1_m(...) __riscv_vssseg2e16_v_i16m1_m(__VA_ARGS__) -#define vssseg3e16_v_i16m1_m(...) __riscv_vssseg3e16_v_i16m1_m(__VA_ARGS__) -#define vssseg4e16_v_i16m1_m(...) __riscv_vssseg4e16_v_i16m1_m(__VA_ARGS__) -#define vssseg5e16_v_i16m1_m(...) __riscv_vssseg5e16_v_i16m1_m(__VA_ARGS__) -#define vssseg6e16_v_i16m1_m(...) __riscv_vssseg6e16_v_i16m1_m(__VA_ARGS__) -#define vssseg7e16_v_i16m1_m(...) __riscv_vssseg7e16_v_i16m1_m(__VA_ARGS__) -#define vssseg8e16_v_i16m1_m(...) __riscv_vssseg8e16_v_i16m1_m(__VA_ARGS__) -#define vssseg2e16_v_i16m2_m(...) __riscv_vssseg2e16_v_i16m2_m(__VA_ARGS__) -#define vssseg3e16_v_i16m2_m(...) __riscv_vssseg3e16_v_i16m2_m(__VA_ARGS__) -#define vssseg4e16_v_i16m2_m(...) __riscv_vssseg4e16_v_i16m2_m(__VA_ARGS__) -#define vssseg2e16_v_i16m4_m(...) __riscv_vssseg2e16_v_i16m4_m(__VA_ARGS__) -#define vssseg2e32_v_i32mf2_m(...) __riscv_vssseg2e32_v_i32mf2_m(__VA_ARGS__) -#define vssseg3e32_v_i32mf2_m(...) __riscv_vssseg3e32_v_i32mf2_m(__VA_ARGS__) -#define vssseg4e32_v_i32mf2_m(...) __riscv_vssseg4e32_v_i32mf2_m(__VA_ARGS__) -#define vssseg5e32_v_i32mf2_m(...) __riscv_vssseg5e32_v_i32mf2_m(__VA_ARGS__) -#define vssseg6e32_v_i32mf2_m(...) __riscv_vssseg6e32_v_i32mf2_m(__VA_ARGS__) -#define vssseg7e32_v_i32mf2_m(...) __riscv_vssseg7e32_v_i32mf2_m(__VA_ARGS__) -#define vssseg8e32_v_i32mf2_m(...) __riscv_vssseg8e32_v_i32mf2_m(__VA_ARGS__) -#define vssseg2e32_v_i32m1_m(...) __riscv_vssseg2e32_v_i32m1_m(__VA_ARGS__) -#define vssseg3e32_v_i32m1_m(...) __riscv_vssseg3e32_v_i32m1_m(__VA_ARGS__) -#define vssseg4e32_v_i32m1_m(...) __riscv_vssseg4e32_v_i32m1_m(__VA_ARGS__) -#define vssseg5e32_v_i32m1_m(...) __riscv_vssseg5e32_v_i32m1_m(__VA_ARGS__) -#define vssseg6e32_v_i32m1_m(...) __riscv_vssseg6e32_v_i32m1_m(__VA_ARGS__) -#define vssseg7e32_v_i32m1_m(...) __riscv_vssseg7e32_v_i32m1_m(__VA_ARGS__) -#define vssseg8e32_v_i32m1_m(...) __riscv_vssseg8e32_v_i32m1_m(__VA_ARGS__) -#define vssseg2e32_v_i32m2_m(...) __riscv_vssseg2e32_v_i32m2_m(__VA_ARGS__) -#define vssseg3e32_v_i32m2_m(...) __riscv_vssseg3e32_v_i32m2_m(__VA_ARGS__) -#define vssseg4e32_v_i32m2_m(...) __riscv_vssseg4e32_v_i32m2_m(__VA_ARGS__) -#define vssseg2e32_v_i32m4_m(...) __riscv_vssseg2e32_v_i32m4_m(__VA_ARGS__) -#define vssseg2e64_v_i64m1_m(...) __riscv_vssseg2e64_v_i64m1_m(__VA_ARGS__) -#define vssseg3e64_v_i64m1_m(...) __riscv_vssseg3e64_v_i64m1_m(__VA_ARGS__) -#define vssseg4e64_v_i64m1_m(...) __riscv_vssseg4e64_v_i64m1_m(__VA_ARGS__) -#define vssseg5e64_v_i64m1_m(...) __riscv_vssseg5e64_v_i64m1_m(__VA_ARGS__) -#define vssseg6e64_v_i64m1_m(...) __riscv_vssseg6e64_v_i64m1_m(__VA_ARGS__) -#define vssseg7e64_v_i64m1_m(...) __riscv_vssseg7e64_v_i64m1_m(__VA_ARGS__) -#define vssseg8e64_v_i64m1_m(...) __riscv_vssseg8e64_v_i64m1_m(__VA_ARGS__) -#define vssseg2e64_v_i64m2_m(...) __riscv_vssseg2e64_v_i64m2_m(__VA_ARGS__) -#define vssseg3e64_v_i64m2_m(...) __riscv_vssseg3e64_v_i64m2_m(__VA_ARGS__) -#define vssseg4e64_v_i64m2_m(...) __riscv_vssseg4e64_v_i64m2_m(__VA_ARGS__) -#define vssseg2e64_v_i64m4_m(...) __riscv_vssseg2e64_v_i64m4_m(__VA_ARGS__) -#define vssseg2e8_v_u8mf8_m(...) __riscv_vssseg2e8_v_u8mf8_m(__VA_ARGS__) -#define vssseg3e8_v_u8mf8_m(...) __riscv_vssseg3e8_v_u8mf8_m(__VA_ARGS__) -#define vssseg4e8_v_u8mf8_m(...) __riscv_vssseg4e8_v_u8mf8_m(__VA_ARGS__) -#define vssseg5e8_v_u8mf8_m(...) __riscv_vssseg5e8_v_u8mf8_m(__VA_ARGS__) -#define vssseg6e8_v_u8mf8_m(...) __riscv_vssseg6e8_v_u8mf8_m(__VA_ARGS__) -#define vssseg7e8_v_u8mf8_m(...) __riscv_vssseg7e8_v_u8mf8_m(__VA_ARGS__) -#define vssseg8e8_v_u8mf8_m(...) __riscv_vssseg8e8_v_u8mf8_m(__VA_ARGS__) -#define vssseg2e8_v_u8mf4_m(...) __riscv_vssseg2e8_v_u8mf4_m(__VA_ARGS__) -#define vssseg3e8_v_u8mf4_m(...) __riscv_vssseg3e8_v_u8mf4_m(__VA_ARGS__) -#define vssseg4e8_v_u8mf4_m(...) __riscv_vssseg4e8_v_u8mf4_m(__VA_ARGS__) -#define vssseg5e8_v_u8mf4_m(...) __riscv_vssseg5e8_v_u8mf4_m(__VA_ARGS__) -#define vssseg6e8_v_u8mf4_m(...) __riscv_vssseg6e8_v_u8mf4_m(__VA_ARGS__) -#define vssseg7e8_v_u8mf4_m(...) __riscv_vssseg7e8_v_u8mf4_m(__VA_ARGS__) -#define vssseg8e8_v_u8mf4_m(...) __riscv_vssseg8e8_v_u8mf4_m(__VA_ARGS__) -#define vssseg2e8_v_u8mf2_m(...) __riscv_vssseg2e8_v_u8mf2_m(__VA_ARGS__) -#define vssseg3e8_v_u8mf2_m(...) __riscv_vssseg3e8_v_u8mf2_m(__VA_ARGS__) -#define vssseg4e8_v_u8mf2_m(...) __riscv_vssseg4e8_v_u8mf2_m(__VA_ARGS__) -#define vssseg5e8_v_u8mf2_m(...) __riscv_vssseg5e8_v_u8mf2_m(__VA_ARGS__) -#define vssseg6e8_v_u8mf2_m(...) __riscv_vssseg6e8_v_u8mf2_m(__VA_ARGS__) -#define vssseg7e8_v_u8mf2_m(...) __riscv_vssseg7e8_v_u8mf2_m(__VA_ARGS__) -#define vssseg8e8_v_u8mf2_m(...) __riscv_vssseg8e8_v_u8mf2_m(__VA_ARGS__) -#define vssseg2e8_v_u8m1_m(...) __riscv_vssseg2e8_v_u8m1_m(__VA_ARGS__) -#define vssseg3e8_v_u8m1_m(...) __riscv_vssseg3e8_v_u8m1_m(__VA_ARGS__) -#define vssseg4e8_v_u8m1_m(...) __riscv_vssseg4e8_v_u8m1_m(__VA_ARGS__) -#define vssseg5e8_v_u8m1_m(...) __riscv_vssseg5e8_v_u8m1_m(__VA_ARGS__) -#define vssseg6e8_v_u8m1_m(...) __riscv_vssseg6e8_v_u8m1_m(__VA_ARGS__) -#define vssseg7e8_v_u8m1_m(...) __riscv_vssseg7e8_v_u8m1_m(__VA_ARGS__) -#define vssseg8e8_v_u8m1_m(...) __riscv_vssseg8e8_v_u8m1_m(__VA_ARGS__) -#define vssseg2e8_v_u8m2_m(...) __riscv_vssseg2e8_v_u8m2_m(__VA_ARGS__) -#define vssseg3e8_v_u8m2_m(...) __riscv_vssseg3e8_v_u8m2_m(__VA_ARGS__) -#define vssseg4e8_v_u8m2_m(...) __riscv_vssseg4e8_v_u8m2_m(__VA_ARGS__) -#define vssseg2e8_v_u8m4_m(...) __riscv_vssseg2e8_v_u8m4_m(__VA_ARGS__) -#define vssseg2e16_v_u16mf4_m(...) __riscv_vssseg2e16_v_u16mf4_m(__VA_ARGS__) -#define vssseg3e16_v_u16mf4_m(...) __riscv_vssseg3e16_v_u16mf4_m(__VA_ARGS__) -#define vssseg4e16_v_u16mf4_m(...) __riscv_vssseg4e16_v_u16mf4_m(__VA_ARGS__) -#define vssseg5e16_v_u16mf4_m(...) __riscv_vssseg5e16_v_u16mf4_m(__VA_ARGS__) -#define vssseg6e16_v_u16mf4_m(...) __riscv_vssseg6e16_v_u16mf4_m(__VA_ARGS__) -#define vssseg7e16_v_u16mf4_m(...) __riscv_vssseg7e16_v_u16mf4_m(__VA_ARGS__) -#define vssseg8e16_v_u16mf4_m(...) __riscv_vssseg8e16_v_u16mf4_m(__VA_ARGS__) -#define vssseg2e16_v_u16mf2_m(...) __riscv_vssseg2e16_v_u16mf2_m(__VA_ARGS__) -#define vssseg3e16_v_u16mf2_m(...) __riscv_vssseg3e16_v_u16mf2_m(__VA_ARGS__) -#define vssseg4e16_v_u16mf2_m(...) __riscv_vssseg4e16_v_u16mf2_m(__VA_ARGS__) -#define vssseg5e16_v_u16mf2_m(...) __riscv_vssseg5e16_v_u16mf2_m(__VA_ARGS__) -#define vssseg6e16_v_u16mf2_m(...) __riscv_vssseg6e16_v_u16mf2_m(__VA_ARGS__) -#define vssseg7e16_v_u16mf2_m(...) __riscv_vssseg7e16_v_u16mf2_m(__VA_ARGS__) -#define vssseg8e16_v_u16mf2_m(...) __riscv_vssseg8e16_v_u16mf2_m(__VA_ARGS__) -#define vssseg2e16_v_u16m1_m(...) __riscv_vssseg2e16_v_u16m1_m(__VA_ARGS__) -#define vssseg3e16_v_u16m1_m(...) __riscv_vssseg3e16_v_u16m1_m(__VA_ARGS__) -#define vssseg4e16_v_u16m1_m(...) __riscv_vssseg4e16_v_u16m1_m(__VA_ARGS__) -#define vssseg5e16_v_u16m1_m(...) __riscv_vssseg5e16_v_u16m1_m(__VA_ARGS__) -#define vssseg6e16_v_u16m1_m(...) __riscv_vssseg6e16_v_u16m1_m(__VA_ARGS__) -#define vssseg7e16_v_u16m1_m(...) __riscv_vssseg7e16_v_u16m1_m(__VA_ARGS__) -#define vssseg8e16_v_u16m1_m(...) __riscv_vssseg8e16_v_u16m1_m(__VA_ARGS__) -#define vssseg2e16_v_u16m2_m(...) __riscv_vssseg2e16_v_u16m2_m(__VA_ARGS__) -#define vssseg3e16_v_u16m2_m(...) __riscv_vssseg3e16_v_u16m2_m(__VA_ARGS__) -#define vssseg4e16_v_u16m2_m(...) __riscv_vssseg4e16_v_u16m2_m(__VA_ARGS__) -#define vssseg2e16_v_u16m4_m(...) __riscv_vssseg2e16_v_u16m4_m(__VA_ARGS__) -#define vssseg2e32_v_u32mf2_m(...) __riscv_vssseg2e32_v_u32mf2_m(__VA_ARGS__) -#define vssseg3e32_v_u32mf2_m(...) __riscv_vssseg3e32_v_u32mf2_m(__VA_ARGS__) -#define vssseg4e32_v_u32mf2_m(...) __riscv_vssseg4e32_v_u32mf2_m(__VA_ARGS__) -#define vssseg5e32_v_u32mf2_m(...) __riscv_vssseg5e32_v_u32mf2_m(__VA_ARGS__) -#define vssseg6e32_v_u32mf2_m(...) __riscv_vssseg6e32_v_u32mf2_m(__VA_ARGS__) -#define vssseg7e32_v_u32mf2_m(...) __riscv_vssseg7e32_v_u32mf2_m(__VA_ARGS__) -#define vssseg8e32_v_u32mf2_m(...) __riscv_vssseg8e32_v_u32mf2_m(__VA_ARGS__) -#define vssseg2e32_v_u32m1_m(...) __riscv_vssseg2e32_v_u32m1_m(__VA_ARGS__) -#define vssseg3e32_v_u32m1_m(...) __riscv_vssseg3e32_v_u32m1_m(__VA_ARGS__) -#define vssseg4e32_v_u32m1_m(...) __riscv_vssseg4e32_v_u32m1_m(__VA_ARGS__) -#define vssseg5e32_v_u32m1_m(...) __riscv_vssseg5e32_v_u32m1_m(__VA_ARGS__) -#define vssseg6e32_v_u32m1_m(...) __riscv_vssseg6e32_v_u32m1_m(__VA_ARGS__) -#define vssseg7e32_v_u32m1_m(...) __riscv_vssseg7e32_v_u32m1_m(__VA_ARGS__) -#define vssseg8e32_v_u32m1_m(...) __riscv_vssseg8e32_v_u32m1_m(__VA_ARGS__) -#define vssseg2e32_v_u32m2_m(...) __riscv_vssseg2e32_v_u32m2_m(__VA_ARGS__) -#define vssseg3e32_v_u32m2_m(...) __riscv_vssseg3e32_v_u32m2_m(__VA_ARGS__) -#define vssseg4e32_v_u32m2_m(...) __riscv_vssseg4e32_v_u32m2_m(__VA_ARGS__) -#define vssseg2e32_v_u32m4_m(...) __riscv_vssseg2e32_v_u32m4_m(__VA_ARGS__) -#define vssseg2e64_v_u64m1_m(...) __riscv_vssseg2e64_v_u64m1_m(__VA_ARGS__) -#define vssseg3e64_v_u64m1_m(...) __riscv_vssseg3e64_v_u64m1_m(__VA_ARGS__) -#define vssseg4e64_v_u64m1_m(...) __riscv_vssseg4e64_v_u64m1_m(__VA_ARGS__) -#define vssseg5e64_v_u64m1_m(...) __riscv_vssseg5e64_v_u64m1_m(__VA_ARGS__) -#define vssseg6e64_v_u64m1_m(...) __riscv_vssseg6e64_v_u64m1_m(__VA_ARGS__) -#define vssseg7e64_v_u64m1_m(...) __riscv_vssseg7e64_v_u64m1_m(__VA_ARGS__) -#define vssseg8e64_v_u64m1_m(...) __riscv_vssseg8e64_v_u64m1_m(__VA_ARGS__) -#define vssseg2e64_v_u64m2_m(...) __riscv_vssseg2e64_v_u64m2_m(__VA_ARGS__) -#define vssseg3e64_v_u64m2_m(...) __riscv_vssseg3e64_v_u64m2_m(__VA_ARGS__) -#define vssseg4e64_v_u64m2_m(...) __riscv_vssseg4e64_v_u64m2_m(__VA_ARGS__) -#define vssseg2e64_v_u64m4_m(...) __riscv_vssseg2e64_v_u64m4_m(__VA_ARGS__) -#define vloxseg2ei8_v_f16mf4(...) __riscv_vloxseg2ei8_v_f16mf4(__VA_ARGS__) -#define vloxseg3ei8_v_f16mf4(...) __riscv_vloxseg3ei8_v_f16mf4(__VA_ARGS__) -#define vloxseg4ei8_v_f16mf4(...) __riscv_vloxseg4ei8_v_f16mf4(__VA_ARGS__) -#define vloxseg5ei8_v_f16mf4(...) __riscv_vloxseg5ei8_v_f16mf4(__VA_ARGS__) -#define vloxseg6ei8_v_f16mf4(...) __riscv_vloxseg6ei8_v_f16mf4(__VA_ARGS__) -#define vloxseg7ei8_v_f16mf4(...) __riscv_vloxseg7ei8_v_f16mf4(__VA_ARGS__) -#define vloxseg8ei8_v_f16mf4(...) __riscv_vloxseg8ei8_v_f16mf4(__VA_ARGS__) -#define vloxseg2ei8_v_f16mf2(...) __riscv_vloxseg2ei8_v_f16mf2(__VA_ARGS__) -#define vloxseg3ei8_v_f16mf2(...) __riscv_vloxseg3ei8_v_f16mf2(__VA_ARGS__) -#define vloxseg4ei8_v_f16mf2(...) __riscv_vloxseg4ei8_v_f16mf2(__VA_ARGS__) -#define vloxseg5ei8_v_f16mf2(...) __riscv_vloxseg5ei8_v_f16mf2(__VA_ARGS__) -#define vloxseg6ei8_v_f16mf2(...) __riscv_vloxseg6ei8_v_f16mf2(__VA_ARGS__) -#define vloxseg7ei8_v_f16mf2(...) __riscv_vloxseg7ei8_v_f16mf2(__VA_ARGS__) -#define vloxseg8ei8_v_f16mf2(...) __riscv_vloxseg8ei8_v_f16mf2(__VA_ARGS__) -#define vloxseg2ei8_v_f16m1(...) __riscv_vloxseg2ei8_v_f16m1(__VA_ARGS__) -#define vloxseg3ei8_v_f16m1(...) __riscv_vloxseg3ei8_v_f16m1(__VA_ARGS__) -#define vloxseg4ei8_v_f16m1(...) __riscv_vloxseg4ei8_v_f16m1(__VA_ARGS__) -#define vloxseg5ei8_v_f16m1(...) __riscv_vloxseg5ei8_v_f16m1(__VA_ARGS__) -#define vloxseg6ei8_v_f16m1(...) __riscv_vloxseg6ei8_v_f16m1(__VA_ARGS__) -#define vloxseg7ei8_v_f16m1(...) __riscv_vloxseg7ei8_v_f16m1(__VA_ARGS__) -#define vloxseg8ei8_v_f16m1(...) __riscv_vloxseg8ei8_v_f16m1(__VA_ARGS__) -#define vloxseg2ei8_v_f16m2(...) __riscv_vloxseg2ei8_v_f16m2(__VA_ARGS__) -#define vloxseg3ei8_v_f16m2(...) __riscv_vloxseg3ei8_v_f16m2(__VA_ARGS__) -#define vloxseg4ei8_v_f16m2(...) __riscv_vloxseg4ei8_v_f16m2(__VA_ARGS__) -#define vloxseg2ei8_v_f16m4(...) __riscv_vloxseg2ei8_v_f16m4(__VA_ARGS__) -#define vloxseg2ei16_v_f16mf4(...) __riscv_vloxseg2ei16_v_f16mf4(__VA_ARGS__) -#define vloxseg3ei16_v_f16mf4(...) __riscv_vloxseg3ei16_v_f16mf4(__VA_ARGS__) -#define vloxseg4ei16_v_f16mf4(...) __riscv_vloxseg4ei16_v_f16mf4(__VA_ARGS__) -#define vloxseg5ei16_v_f16mf4(...) __riscv_vloxseg5ei16_v_f16mf4(__VA_ARGS__) -#define vloxseg6ei16_v_f16mf4(...) __riscv_vloxseg6ei16_v_f16mf4(__VA_ARGS__) -#define vloxseg7ei16_v_f16mf4(...) __riscv_vloxseg7ei16_v_f16mf4(__VA_ARGS__) -#define vloxseg8ei16_v_f16mf4(...) __riscv_vloxseg8ei16_v_f16mf4(__VA_ARGS__) -#define vloxseg2ei16_v_f16mf2(...) __riscv_vloxseg2ei16_v_f16mf2(__VA_ARGS__) -#define vloxseg3ei16_v_f16mf2(...) __riscv_vloxseg3ei16_v_f16mf2(__VA_ARGS__) -#define vloxseg4ei16_v_f16mf2(...) __riscv_vloxseg4ei16_v_f16mf2(__VA_ARGS__) -#define vloxseg5ei16_v_f16mf2(...) __riscv_vloxseg5ei16_v_f16mf2(__VA_ARGS__) -#define vloxseg6ei16_v_f16mf2(...) __riscv_vloxseg6ei16_v_f16mf2(__VA_ARGS__) -#define vloxseg7ei16_v_f16mf2(...) __riscv_vloxseg7ei16_v_f16mf2(__VA_ARGS__) -#define vloxseg8ei16_v_f16mf2(...) __riscv_vloxseg8ei16_v_f16mf2(__VA_ARGS__) -#define vloxseg2ei16_v_f16m1(...) __riscv_vloxseg2ei16_v_f16m1(__VA_ARGS__) -#define vloxseg3ei16_v_f16m1(...) __riscv_vloxseg3ei16_v_f16m1(__VA_ARGS__) -#define vloxseg4ei16_v_f16m1(...) __riscv_vloxseg4ei16_v_f16m1(__VA_ARGS__) -#define vloxseg5ei16_v_f16m1(...) __riscv_vloxseg5ei16_v_f16m1(__VA_ARGS__) -#define vloxseg6ei16_v_f16m1(...) __riscv_vloxseg6ei16_v_f16m1(__VA_ARGS__) -#define vloxseg7ei16_v_f16m1(...) __riscv_vloxseg7ei16_v_f16m1(__VA_ARGS__) -#define vloxseg8ei16_v_f16m1(...) __riscv_vloxseg8ei16_v_f16m1(__VA_ARGS__) -#define vloxseg2ei16_v_f16m2(...) __riscv_vloxseg2ei16_v_f16m2(__VA_ARGS__) -#define vloxseg3ei16_v_f16m2(...) __riscv_vloxseg3ei16_v_f16m2(__VA_ARGS__) -#define vloxseg4ei16_v_f16m2(...) __riscv_vloxseg4ei16_v_f16m2(__VA_ARGS__) -#define vloxseg2ei16_v_f16m4(...) __riscv_vloxseg2ei16_v_f16m4(__VA_ARGS__) -#define vloxseg2ei32_v_f16mf4(...) __riscv_vloxseg2ei32_v_f16mf4(__VA_ARGS__) -#define vloxseg3ei32_v_f16mf4(...) __riscv_vloxseg3ei32_v_f16mf4(__VA_ARGS__) -#define vloxseg4ei32_v_f16mf4(...) __riscv_vloxseg4ei32_v_f16mf4(__VA_ARGS__) -#define vloxseg5ei32_v_f16mf4(...) __riscv_vloxseg5ei32_v_f16mf4(__VA_ARGS__) -#define vloxseg6ei32_v_f16mf4(...) __riscv_vloxseg6ei32_v_f16mf4(__VA_ARGS__) -#define vloxseg7ei32_v_f16mf4(...) __riscv_vloxseg7ei32_v_f16mf4(__VA_ARGS__) -#define vloxseg8ei32_v_f16mf4(...) __riscv_vloxseg8ei32_v_f16mf4(__VA_ARGS__) -#define vloxseg2ei32_v_f16mf2(...) __riscv_vloxseg2ei32_v_f16mf2(__VA_ARGS__) -#define vloxseg3ei32_v_f16mf2(...) __riscv_vloxseg3ei32_v_f16mf2(__VA_ARGS__) -#define vloxseg4ei32_v_f16mf2(...) __riscv_vloxseg4ei32_v_f16mf2(__VA_ARGS__) -#define vloxseg5ei32_v_f16mf2(...) __riscv_vloxseg5ei32_v_f16mf2(__VA_ARGS__) -#define vloxseg6ei32_v_f16mf2(...) __riscv_vloxseg6ei32_v_f16mf2(__VA_ARGS__) -#define vloxseg7ei32_v_f16mf2(...) __riscv_vloxseg7ei32_v_f16mf2(__VA_ARGS__) -#define vloxseg8ei32_v_f16mf2(...) __riscv_vloxseg8ei32_v_f16mf2(__VA_ARGS__) -#define vloxseg2ei32_v_f16m1(...) __riscv_vloxseg2ei32_v_f16m1(__VA_ARGS__) -#define vloxseg3ei32_v_f16m1(...) __riscv_vloxseg3ei32_v_f16m1(__VA_ARGS__) -#define vloxseg4ei32_v_f16m1(...) __riscv_vloxseg4ei32_v_f16m1(__VA_ARGS__) -#define vloxseg5ei32_v_f16m1(...) __riscv_vloxseg5ei32_v_f16m1(__VA_ARGS__) -#define vloxseg6ei32_v_f16m1(...) __riscv_vloxseg6ei32_v_f16m1(__VA_ARGS__) -#define vloxseg7ei32_v_f16m1(...) __riscv_vloxseg7ei32_v_f16m1(__VA_ARGS__) -#define vloxseg8ei32_v_f16m1(...) __riscv_vloxseg8ei32_v_f16m1(__VA_ARGS__) -#define vloxseg2ei32_v_f16m2(...) __riscv_vloxseg2ei32_v_f16m2(__VA_ARGS__) -#define vloxseg3ei32_v_f16m2(...) __riscv_vloxseg3ei32_v_f16m2(__VA_ARGS__) -#define vloxseg4ei32_v_f16m2(...) __riscv_vloxseg4ei32_v_f16m2(__VA_ARGS__) -#define vloxseg2ei32_v_f16m4(...) __riscv_vloxseg2ei32_v_f16m4(__VA_ARGS__) -#define vloxseg2ei64_v_f16mf4(...) __riscv_vloxseg2ei64_v_f16mf4(__VA_ARGS__) -#define vloxseg3ei64_v_f16mf4(...) __riscv_vloxseg3ei64_v_f16mf4(__VA_ARGS__) -#define vloxseg4ei64_v_f16mf4(...) __riscv_vloxseg4ei64_v_f16mf4(__VA_ARGS__) -#define vloxseg5ei64_v_f16mf4(...) __riscv_vloxseg5ei64_v_f16mf4(__VA_ARGS__) -#define vloxseg6ei64_v_f16mf4(...) __riscv_vloxseg6ei64_v_f16mf4(__VA_ARGS__) -#define vloxseg7ei64_v_f16mf4(...) __riscv_vloxseg7ei64_v_f16mf4(__VA_ARGS__) -#define vloxseg8ei64_v_f16mf4(...) __riscv_vloxseg8ei64_v_f16mf4(__VA_ARGS__) -#define vloxseg2ei64_v_f16mf2(...) __riscv_vloxseg2ei64_v_f16mf2(__VA_ARGS__) -#define vloxseg3ei64_v_f16mf2(...) __riscv_vloxseg3ei64_v_f16mf2(__VA_ARGS__) -#define vloxseg4ei64_v_f16mf2(...) __riscv_vloxseg4ei64_v_f16mf2(__VA_ARGS__) -#define vloxseg5ei64_v_f16mf2(...) __riscv_vloxseg5ei64_v_f16mf2(__VA_ARGS__) -#define vloxseg6ei64_v_f16mf2(...) __riscv_vloxseg6ei64_v_f16mf2(__VA_ARGS__) -#define vloxseg7ei64_v_f16mf2(...) __riscv_vloxseg7ei64_v_f16mf2(__VA_ARGS__) -#define vloxseg8ei64_v_f16mf2(...) __riscv_vloxseg8ei64_v_f16mf2(__VA_ARGS__) -#define vloxseg2ei64_v_f16m1(...) __riscv_vloxseg2ei64_v_f16m1(__VA_ARGS__) -#define vloxseg3ei64_v_f16m1(...) __riscv_vloxseg3ei64_v_f16m1(__VA_ARGS__) -#define vloxseg4ei64_v_f16m1(...) __riscv_vloxseg4ei64_v_f16m1(__VA_ARGS__) -#define vloxseg5ei64_v_f16m1(...) __riscv_vloxseg5ei64_v_f16m1(__VA_ARGS__) -#define vloxseg6ei64_v_f16m1(...) __riscv_vloxseg6ei64_v_f16m1(__VA_ARGS__) -#define vloxseg7ei64_v_f16m1(...) __riscv_vloxseg7ei64_v_f16m1(__VA_ARGS__) -#define vloxseg8ei64_v_f16m1(...) __riscv_vloxseg8ei64_v_f16m1(__VA_ARGS__) -#define vloxseg2ei64_v_f16m2(...) __riscv_vloxseg2ei64_v_f16m2(__VA_ARGS__) -#define vloxseg3ei64_v_f16m2(...) __riscv_vloxseg3ei64_v_f16m2(__VA_ARGS__) -#define vloxseg4ei64_v_f16m2(...) __riscv_vloxseg4ei64_v_f16m2(__VA_ARGS__) -#define vloxseg2ei8_v_f32mf2(...) __riscv_vloxseg2ei8_v_f32mf2(__VA_ARGS__) -#define vloxseg3ei8_v_f32mf2(...) __riscv_vloxseg3ei8_v_f32mf2(__VA_ARGS__) -#define vloxseg4ei8_v_f32mf2(...) __riscv_vloxseg4ei8_v_f32mf2(__VA_ARGS__) -#define vloxseg5ei8_v_f32mf2(...) __riscv_vloxseg5ei8_v_f32mf2(__VA_ARGS__) -#define vloxseg6ei8_v_f32mf2(...) __riscv_vloxseg6ei8_v_f32mf2(__VA_ARGS__) -#define vloxseg7ei8_v_f32mf2(...) __riscv_vloxseg7ei8_v_f32mf2(__VA_ARGS__) -#define vloxseg8ei8_v_f32mf2(...) __riscv_vloxseg8ei8_v_f32mf2(__VA_ARGS__) -#define vloxseg2ei8_v_f32m1(...) __riscv_vloxseg2ei8_v_f32m1(__VA_ARGS__) -#define vloxseg3ei8_v_f32m1(...) __riscv_vloxseg3ei8_v_f32m1(__VA_ARGS__) -#define vloxseg4ei8_v_f32m1(...) __riscv_vloxseg4ei8_v_f32m1(__VA_ARGS__) -#define vloxseg5ei8_v_f32m1(...) __riscv_vloxseg5ei8_v_f32m1(__VA_ARGS__) -#define vloxseg6ei8_v_f32m1(...) __riscv_vloxseg6ei8_v_f32m1(__VA_ARGS__) -#define vloxseg7ei8_v_f32m1(...) __riscv_vloxseg7ei8_v_f32m1(__VA_ARGS__) -#define vloxseg8ei8_v_f32m1(...) __riscv_vloxseg8ei8_v_f32m1(__VA_ARGS__) -#define vloxseg2ei8_v_f32m2(...) __riscv_vloxseg2ei8_v_f32m2(__VA_ARGS__) -#define vloxseg3ei8_v_f32m2(...) __riscv_vloxseg3ei8_v_f32m2(__VA_ARGS__) -#define vloxseg4ei8_v_f32m2(...) __riscv_vloxseg4ei8_v_f32m2(__VA_ARGS__) -#define vloxseg2ei8_v_f32m4(...) __riscv_vloxseg2ei8_v_f32m4(__VA_ARGS__) -#define vloxseg2ei16_v_f32mf2(...) __riscv_vloxseg2ei16_v_f32mf2(__VA_ARGS__) -#define vloxseg3ei16_v_f32mf2(...) __riscv_vloxseg3ei16_v_f32mf2(__VA_ARGS__) -#define vloxseg4ei16_v_f32mf2(...) __riscv_vloxseg4ei16_v_f32mf2(__VA_ARGS__) -#define vloxseg5ei16_v_f32mf2(...) __riscv_vloxseg5ei16_v_f32mf2(__VA_ARGS__) -#define vloxseg6ei16_v_f32mf2(...) __riscv_vloxseg6ei16_v_f32mf2(__VA_ARGS__) -#define vloxseg7ei16_v_f32mf2(...) __riscv_vloxseg7ei16_v_f32mf2(__VA_ARGS__) -#define vloxseg8ei16_v_f32mf2(...) __riscv_vloxseg8ei16_v_f32mf2(__VA_ARGS__) -#define vloxseg2ei16_v_f32m1(...) __riscv_vloxseg2ei16_v_f32m1(__VA_ARGS__) -#define vloxseg3ei16_v_f32m1(...) __riscv_vloxseg3ei16_v_f32m1(__VA_ARGS__) -#define vloxseg4ei16_v_f32m1(...) __riscv_vloxseg4ei16_v_f32m1(__VA_ARGS__) -#define vloxseg5ei16_v_f32m1(...) __riscv_vloxseg5ei16_v_f32m1(__VA_ARGS__) -#define vloxseg6ei16_v_f32m1(...) __riscv_vloxseg6ei16_v_f32m1(__VA_ARGS__) -#define vloxseg7ei16_v_f32m1(...) __riscv_vloxseg7ei16_v_f32m1(__VA_ARGS__) -#define vloxseg8ei16_v_f32m1(...) __riscv_vloxseg8ei16_v_f32m1(__VA_ARGS__) -#define vloxseg2ei16_v_f32m2(...) __riscv_vloxseg2ei16_v_f32m2(__VA_ARGS__) -#define vloxseg3ei16_v_f32m2(...) __riscv_vloxseg3ei16_v_f32m2(__VA_ARGS__) -#define vloxseg4ei16_v_f32m2(...) __riscv_vloxseg4ei16_v_f32m2(__VA_ARGS__) -#define vloxseg2ei16_v_f32m4(...) __riscv_vloxseg2ei16_v_f32m4(__VA_ARGS__) -#define vloxseg2ei32_v_f32mf2(...) __riscv_vloxseg2ei32_v_f32mf2(__VA_ARGS__) -#define vloxseg3ei32_v_f32mf2(...) __riscv_vloxseg3ei32_v_f32mf2(__VA_ARGS__) -#define vloxseg4ei32_v_f32mf2(...) __riscv_vloxseg4ei32_v_f32mf2(__VA_ARGS__) -#define vloxseg5ei32_v_f32mf2(...) __riscv_vloxseg5ei32_v_f32mf2(__VA_ARGS__) -#define vloxseg6ei32_v_f32mf2(...) __riscv_vloxseg6ei32_v_f32mf2(__VA_ARGS__) -#define vloxseg7ei32_v_f32mf2(...) __riscv_vloxseg7ei32_v_f32mf2(__VA_ARGS__) -#define vloxseg8ei32_v_f32mf2(...) __riscv_vloxseg8ei32_v_f32mf2(__VA_ARGS__) -#define vloxseg2ei32_v_f32m1(...) __riscv_vloxseg2ei32_v_f32m1(__VA_ARGS__) -#define vloxseg3ei32_v_f32m1(...) __riscv_vloxseg3ei32_v_f32m1(__VA_ARGS__) -#define vloxseg4ei32_v_f32m1(...) __riscv_vloxseg4ei32_v_f32m1(__VA_ARGS__) -#define vloxseg5ei32_v_f32m1(...) __riscv_vloxseg5ei32_v_f32m1(__VA_ARGS__) -#define vloxseg6ei32_v_f32m1(...) __riscv_vloxseg6ei32_v_f32m1(__VA_ARGS__) -#define vloxseg7ei32_v_f32m1(...) __riscv_vloxseg7ei32_v_f32m1(__VA_ARGS__) -#define vloxseg8ei32_v_f32m1(...) __riscv_vloxseg8ei32_v_f32m1(__VA_ARGS__) -#define vloxseg2ei32_v_f32m2(...) __riscv_vloxseg2ei32_v_f32m2(__VA_ARGS__) -#define vloxseg3ei32_v_f32m2(...) __riscv_vloxseg3ei32_v_f32m2(__VA_ARGS__) -#define vloxseg4ei32_v_f32m2(...) __riscv_vloxseg4ei32_v_f32m2(__VA_ARGS__) -#define vloxseg2ei32_v_f32m4(...) __riscv_vloxseg2ei32_v_f32m4(__VA_ARGS__) -#define vloxseg2ei64_v_f32mf2(...) __riscv_vloxseg2ei64_v_f32mf2(__VA_ARGS__) -#define vloxseg3ei64_v_f32mf2(...) __riscv_vloxseg3ei64_v_f32mf2(__VA_ARGS__) -#define vloxseg4ei64_v_f32mf2(...) __riscv_vloxseg4ei64_v_f32mf2(__VA_ARGS__) -#define vloxseg5ei64_v_f32mf2(...) __riscv_vloxseg5ei64_v_f32mf2(__VA_ARGS__) -#define vloxseg6ei64_v_f32mf2(...) __riscv_vloxseg6ei64_v_f32mf2(__VA_ARGS__) -#define vloxseg7ei64_v_f32mf2(...) __riscv_vloxseg7ei64_v_f32mf2(__VA_ARGS__) -#define vloxseg8ei64_v_f32mf2(...) __riscv_vloxseg8ei64_v_f32mf2(__VA_ARGS__) -#define vloxseg2ei64_v_f32m1(...) __riscv_vloxseg2ei64_v_f32m1(__VA_ARGS__) -#define vloxseg3ei64_v_f32m1(...) __riscv_vloxseg3ei64_v_f32m1(__VA_ARGS__) -#define vloxseg4ei64_v_f32m1(...) __riscv_vloxseg4ei64_v_f32m1(__VA_ARGS__) -#define vloxseg5ei64_v_f32m1(...) __riscv_vloxseg5ei64_v_f32m1(__VA_ARGS__) -#define vloxseg6ei64_v_f32m1(...) __riscv_vloxseg6ei64_v_f32m1(__VA_ARGS__) -#define vloxseg7ei64_v_f32m1(...) __riscv_vloxseg7ei64_v_f32m1(__VA_ARGS__) -#define vloxseg8ei64_v_f32m1(...) __riscv_vloxseg8ei64_v_f32m1(__VA_ARGS__) -#define vloxseg2ei64_v_f32m2(...) __riscv_vloxseg2ei64_v_f32m2(__VA_ARGS__) -#define vloxseg3ei64_v_f32m2(...) __riscv_vloxseg3ei64_v_f32m2(__VA_ARGS__) -#define vloxseg4ei64_v_f32m2(...) __riscv_vloxseg4ei64_v_f32m2(__VA_ARGS__) -#define vloxseg2ei64_v_f32m4(...) __riscv_vloxseg2ei64_v_f32m4(__VA_ARGS__) -#define vloxseg2ei8_v_f64m1(...) __riscv_vloxseg2ei8_v_f64m1(__VA_ARGS__) -#define vloxseg3ei8_v_f64m1(...) __riscv_vloxseg3ei8_v_f64m1(__VA_ARGS__) -#define vloxseg4ei8_v_f64m1(...) __riscv_vloxseg4ei8_v_f64m1(__VA_ARGS__) -#define vloxseg5ei8_v_f64m1(...) __riscv_vloxseg5ei8_v_f64m1(__VA_ARGS__) -#define vloxseg6ei8_v_f64m1(...) __riscv_vloxseg6ei8_v_f64m1(__VA_ARGS__) -#define vloxseg7ei8_v_f64m1(...) __riscv_vloxseg7ei8_v_f64m1(__VA_ARGS__) -#define vloxseg8ei8_v_f64m1(...) __riscv_vloxseg8ei8_v_f64m1(__VA_ARGS__) -#define vloxseg2ei8_v_f64m2(...) __riscv_vloxseg2ei8_v_f64m2(__VA_ARGS__) -#define vloxseg3ei8_v_f64m2(...) __riscv_vloxseg3ei8_v_f64m2(__VA_ARGS__) -#define vloxseg4ei8_v_f64m2(...) __riscv_vloxseg4ei8_v_f64m2(__VA_ARGS__) -#define vloxseg2ei8_v_f64m4(...) __riscv_vloxseg2ei8_v_f64m4(__VA_ARGS__) -#define vloxseg2ei16_v_f64m1(...) __riscv_vloxseg2ei16_v_f64m1(__VA_ARGS__) -#define vloxseg3ei16_v_f64m1(...) __riscv_vloxseg3ei16_v_f64m1(__VA_ARGS__) -#define vloxseg4ei16_v_f64m1(...) __riscv_vloxseg4ei16_v_f64m1(__VA_ARGS__) -#define vloxseg5ei16_v_f64m1(...) __riscv_vloxseg5ei16_v_f64m1(__VA_ARGS__) -#define vloxseg6ei16_v_f64m1(...) __riscv_vloxseg6ei16_v_f64m1(__VA_ARGS__) -#define vloxseg7ei16_v_f64m1(...) __riscv_vloxseg7ei16_v_f64m1(__VA_ARGS__) -#define vloxseg8ei16_v_f64m1(...) __riscv_vloxseg8ei16_v_f64m1(__VA_ARGS__) -#define vloxseg2ei16_v_f64m2(...) __riscv_vloxseg2ei16_v_f64m2(__VA_ARGS__) -#define vloxseg3ei16_v_f64m2(...) __riscv_vloxseg3ei16_v_f64m2(__VA_ARGS__) -#define vloxseg4ei16_v_f64m2(...) __riscv_vloxseg4ei16_v_f64m2(__VA_ARGS__) -#define vloxseg2ei16_v_f64m4(...) __riscv_vloxseg2ei16_v_f64m4(__VA_ARGS__) -#define vloxseg2ei32_v_f64m1(...) __riscv_vloxseg2ei32_v_f64m1(__VA_ARGS__) -#define vloxseg3ei32_v_f64m1(...) __riscv_vloxseg3ei32_v_f64m1(__VA_ARGS__) -#define vloxseg4ei32_v_f64m1(...) __riscv_vloxseg4ei32_v_f64m1(__VA_ARGS__) -#define vloxseg5ei32_v_f64m1(...) __riscv_vloxseg5ei32_v_f64m1(__VA_ARGS__) -#define vloxseg6ei32_v_f64m1(...) __riscv_vloxseg6ei32_v_f64m1(__VA_ARGS__) -#define vloxseg7ei32_v_f64m1(...) __riscv_vloxseg7ei32_v_f64m1(__VA_ARGS__) -#define vloxseg8ei32_v_f64m1(...) __riscv_vloxseg8ei32_v_f64m1(__VA_ARGS__) -#define vloxseg2ei32_v_f64m2(...) __riscv_vloxseg2ei32_v_f64m2(__VA_ARGS__) -#define vloxseg3ei32_v_f64m2(...) __riscv_vloxseg3ei32_v_f64m2(__VA_ARGS__) -#define vloxseg4ei32_v_f64m2(...) __riscv_vloxseg4ei32_v_f64m2(__VA_ARGS__) -#define vloxseg2ei32_v_f64m4(...) __riscv_vloxseg2ei32_v_f64m4(__VA_ARGS__) -#define vloxseg2ei64_v_f64m1(...) __riscv_vloxseg2ei64_v_f64m1(__VA_ARGS__) -#define vloxseg3ei64_v_f64m1(...) __riscv_vloxseg3ei64_v_f64m1(__VA_ARGS__) -#define vloxseg4ei64_v_f64m1(...) __riscv_vloxseg4ei64_v_f64m1(__VA_ARGS__) -#define vloxseg5ei64_v_f64m1(...) __riscv_vloxseg5ei64_v_f64m1(__VA_ARGS__) -#define vloxseg6ei64_v_f64m1(...) __riscv_vloxseg6ei64_v_f64m1(__VA_ARGS__) -#define vloxseg7ei64_v_f64m1(...) __riscv_vloxseg7ei64_v_f64m1(__VA_ARGS__) -#define vloxseg8ei64_v_f64m1(...) __riscv_vloxseg8ei64_v_f64m1(__VA_ARGS__) -#define vloxseg2ei64_v_f64m2(...) __riscv_vloxseg2ei64_v_f64m2(__VA_ARGS__) -#define vloxseg3ei64_v_f64m2(...) __riscv_vloxseg3ei64_v_f64m2(__VA_ARGS__) -#define vloxseg4ei64_v_f64m2(...) __riscv_vloxseg4ei64_v_f64m2(__VA_ARGS__) -#define vloxseg2ei64_v_f64m4(...) __riscv_vloxseg2ei64_v_f64m4(__VA_ARGS__) -#define vluxseg2ei8_v_f16mf4(...) __riscv_vluxseg2ei8_v_f16mf4(__VA_ARGS__) -#define vluxseg3ei8_v_f16mf4(...) __riscv_vluxseg3ei8_v_f16mf4(__VA_ARGS__) -#define vluxseg4ei8_v_f16mf4(...) __riscv_vluxseg4ei8_v_f16mf4(__VA_ARGS__) -#define vluxseg5ei8_v_f16mf4(...) __riscv_vluxseg5ei8_v_f16mf4(__VA_ARGS__) -#define vluxseg6ei8_v_f16mf4(...) __riscv_vluxseg6ei8_v_f16mf4(__VA_ARGS__) -#define vluxseg7ei8_v_f16mf4(...) __riscv_vluxseg7ei8_v_f16mf4(__VA_ARGS__) -#define vluxseg8ei8_v_f16mf4(...) __riscv_vluxseg8ei8_v_f16mf4(__VA_ARGS__) -#define vluxseg2ei8_v_f16mf2(...) __riscv_vluxseg2ei8_v_f16mf2(__VA_ARGS__) -#define vluxseg3ei8_v_f16mf2(...) __riscv_vluxseg3ei8_v_f16mf2(__VA_ARGS__) -#define vluxseg4ei8_v_f16mf2(...) __riscv_vluxseg4ei8_v_f16mf2(__VA_ARGS__) -#define vluxseg5ei8_v_f16mf2(...) __riscv_vluxseg5ei8_v_f16mf2(__VA_ARGS__) -#define vluxseg6ei8_v_f16mf2(...) __riscv_vluxseg6ei8_v_f16mf2(__VA_ARGS__) -#define vluxseg7ei8_v_f16mf2(...) __riscv_vluxseg7ei8_v_f16mf2(__VA_ARGS__) -#define vluxseg8ei8_v_f16mf2(...) __riscv_vluxseg8ei8_v_f16mf2(__VA_ARGS__) -#define vluxseg2ei8_v_f16m1(...) __riscv_vluxseg2ei8_v_f16m1(__VA_ARGS__) -#define vluxseg3ei8_v_f16m1(...) __riscv_vluxseg3ei8_v_f16m1(__VA_ARGS__) -#define vluxseg4ei8_v_f16m1(...) __riscv_vluxseg4ei8_v_f16m1(__VA_ARGS__) -#define vluxseg5ei8_v_f16m1(...) __riscv_vluxseg5ei8_v_f16m1(__VA_ARGS__) -#define vluxseg6ei8_v_f16m1(...) __riscv_vluxseg6ei8_v_f16m1(__VA_ARGS__) -#define vluxseg7ei8_v_f16m1(...) __riscv_vluxseg7ei8_v_f16m1(__VA_ARGS__) -#define vluxseg8ei8_v_f16m1(...) __riscv_vluxseg8ei8_v_f16m1(__VA_ARGS__) -#define vluxseg2ei8_v_f16m2(...) __riscv_vluxseg2ei8_v_f16m2(__VA_ARGS__) -#define vluxseg3ei8_v_f16m2(...) __riscv_vluxseg3ei8_v_f16m2(__VA_ARGS__) -#define vluxseg4ei8_v_f16m2(...) __riscv_vluxseg4ei8_v_f16m2(__VA_ARGS__) -#define vluxseg2ei8_v_f16m4(...) __riscv_vluxseg2ei8_v_f16m4(__VA_ARGS__) -#define vluxseg2ei16_v_f16mf4(...) __riscv_vluxseg2ei16_v_f16mf4(__VA_ARGS__) -#define vluxseg3ei16_v_f16mf4(...) __riscv_vluxseg3ei16_v_f16mf4(__VA_ARGS__) -#define vluxseg4ei16_v_f16mf4(...) __riscv_vluxseg4ei16_v_f16mf4(__VA_ARGS__) -#define vluxseg5ei16_v_f16mf4(...) __riscv_vluxseg5ei16_v_f16mf4(__VA_ARGS__) -#define vluxseg6ei16_v_f16mf4(...) __riscv_vluxseg6ei16_v_f16mf4(__VA_ARGS__) -#define vluxseg7ei16_v_f16mf4(...) __riscv_vluxseg7ei16_v_f16mf4(__VA_ARGS__) -#define vluxseg8ei16_v_f16mf4(...) __riscv_vluxseg8ei16_v_f16mf4(__VA_ARGS__) -#define vluxseg2ei16_v_f16mf2(...) __riscv_vluxseg2ei16_v_f16mf2(__VA_ARGS__) -#define vluxseg3ei16_v_f16mf2(...) __riscv_vluxseg3ei16_v_f16mf2(__VA_ARGS__) -#define vluxseg4ei16_v_f16mf2(...) __riscv_vluxseg4ei16_v_f16mf2(__VA_ARGS__) -#define vluxseg5ei16_v_f16mf2(...) __riscv_vluxseg5ei16_v_f16mf2(__VA_ARGS__) -#define vluxseg6ei16_v_f16mf2(...) __riscv_vluxseg6ei16_v_f16mf2(__VA_ARGS__) -#define vluxseg7ei16_v_f16mf2(...) __riscv_vluxseg7ei16_v_f16mf2(__VA_ARGS__) -#define vluxseg8ei16_v_f16mf2(...) __riscv_vluxseg8ei16_v_f16mf2(__VA_ARGS__) -#define vluxseg2ei16_v_f16m1(...) __riscv_vluxseg2ei16_v_f16m1(__VA_ARGS__) -#define vluxseg3ei16_v_f16m1(...) __riscv_vluxseg3ei16_v_f16m1(__VA_ARGS__) -#define vluxseg4ei16_v_f16m1(...) __riscv_vluxseg4ei16_v_f16m1(__VA_ARGS__) -#define vluxseg5ei16_v_f16m1(...) __riscv_vluxseg5ei16_v_f16m1(__VA_ARGS__) -#define vluxseg6ei16_v_f16m1(...) __riscv_vluxseg6ei16_v_f16m1(__VA_ARGS__) -#define vluxseg7ei16_v_f16m1(...) __riscv_vluxseg7ei16_v_f16m1(__VA_ARGS__) -#define vluxseg8ei16_v_f16m1(...) __riscv_vluxseg8ei16_v_f16m1(__VA_ARGS__) -#define vluxseg2ei16_v_f16m2(...) __riscv_vluxseg2ei16_v_f16m2(__VA_ARGS__) -#define vluxseg3ei16_v_f16m2(...) __riscv_vluxseg3ei16_v_f16m2(__VA_ARGS__) -#define vluxseg4ei16_v_f16m2(...) __riscv_vluxseg4ei16_v_f16m2(__VA_ARGS__) -#define vluxseg2ei16_v_f16m4(...) __riscv_vluxseg2ei16_v_f16m4(__VA_ARGS__) -#define vluxseg2ei32_v_f16mf4(...) __riscv_vluxseg2ei32_v_f16mf4(__VA_ARGS__) -#define vluxseg3ei32_v_f16mf4(...) __riscv_vluxseg3ei32_v_f16mf4(__VA_ARGS__) -#define vluxseg4ei32_v_f16mf4(...) __riscv_vluxseg4ei32_v_f16mf4(__VA_ARGS__) -#define vluxseg5ei32_v_f16mf4(...) __riscv_vluxseg5ei32_v_f16mf4(__VA_ARGS__) -#define vluxseg6ei32_v_f16mf4(...) __riscv_vluxseg6ei32_v_f16mf4(__VA_ARGS__) -#define vluxseg7ei32_v_f16mf4(...) __riscv_vluxseg7ei32_v_f16mf4(__VA_ARGS__) -#define vluxseg8ei32_v_f16mf4(...) __riscv_vluxseg8ei32_v_f16mf4(__VA_ARGS__) -#define vluxseg2ei32_v_f16mf2(...) __riscv_vluxseg2ei32_v_f16mf2(__VA_ARGS__) -#define vluxseg3ei32_v_f16mf2(...) __riscv_vluxseg3ei32_v_f16mf2(__VA_ARGS__) -#define vluxseg4ei32_v_f16mf2(...) __riscv_vluxseg4ei32_v_f16mf2(__VA_ARGS__) -#define vluxseg5ei32_v_f16mf2(...) __riscv_vluxseg5ei32_v_f16mf2(__VA_ARGS__) -#define vluxseg6ei32_v_f16mf2(...) __riscv_vluxseg6ei32_v_f16mf2(__VA_ARGS__) -#define vluxseg7ei32_v_f16mf2(...) __riscv_vluxseg7ei32_v_f16mf2(__VA_ARGS__) -#define vluxseg8ei32_v_f16mf2(...) __riscv_vluxseg8ei32_v_f16mf2(__VA_ARGS__) -#define vluxseg2ei32_v_f16m1(...) __riscv_vluxseg2ei32_v_f16m1(__VA_ARGS__) -#define vluxseg3ei32_v_f16m1(...) __riscv_vluxseg3ei32_v_f16m1(__VA_ARGS__) -#define vluxseg4ei32_v_f16m1(...) __riscv_vluxseg4ei32_v_f16m1(__VA_ARGS__) -#define vluxseg5ei32_v_f16m1(...) __riscv_vluxseg5ei32_v_f16m1(__VA_ARGS__) -#define vluxseg6ei32_v_f16m1(...) __riscv_vluxseg6ei32_v_f16m1(__VA_ARGS__) -#define vluxseg7ei32_v_f16m1(...) __riscv_vluxseg7ei32_v_f16m1(__VA_ARGS__) -#define vluxseg8ei32_v_f16m1(...) __riscv_vluxseg8ei32_v_f16m1(__VA_ARGS__) -#define vluxseg2ei32_v_f16m2(...) __riscv_vluxseg2ei32_v_f16m2(__VA_ARGS__) -#define vluxseg3ei32_v_f16m2(...) __riscv_vluxseg3ei32_v_f16m2(__VA_ARGS__) -#define vluxseg4ei32_v_f16m2(...) __riscv_vluxseg4ei32_v_f16m2(__VA_ARGS__) -#define vluxseg2ei32_v_f16m4(...) __riscv_vluxseg2ei32_v_f16m4(__VA_ARGS__) -#define vluxseg2ei64_v_f16mf4(...) __riscv_vluxseg2ei64_v_f16mf4(__VA_ARGS__) -#define vluxseg3ei64_v_f16mf4(...) __riscv_vluxseg3ei64_v_f16mf4(__VA_ARGS__) -#define vluxseg4ei64_v_f16mf4(...) __riscv_vluxseg4ei64_v_f16mf4(__VA_ARGS__) -#define vluxseg5ei64_v_f16mf4(...) __riscv_vluxseg5ei64_v_f16mf4(__VA_ARGS__) -#define vluxseg6ei64_v_f16mf4(...) __riscv_vluxseg6ei64_v_f16mf4(__VA_ARGS__) -#define vluxseg7ei64_v_f16mf4(...) __riscv_vluxseg7ei64_v_f16mf4(__VA_ARGS__) -#define vluxseg8ei64_v_f16mf4(...) __riscv_vluxseg8ei64_v_f16mf4(__VA_ARGS__) -#define vluxseg2ei64_v_f16mf2(...) __riscv_vluxseg2ei64_v_f16mf2(__VA_ARGS__) -#define vluxseg3ei64_v_f16mf2(...) __riscv_vluxseg3ei64_v_f16mf2(__VA_ARGS__) -#define vluxseg4ei64_v_f16mf2(...) __riscv_vluxseg4ei64_v_f16mf2(__VA_ARGS__) -#define vluxseg5ei64_v_f16mf2(...) __riscv_vluxseg5ei64_v_f16mf2(__VA_ARGS__) -#define vluxseg6ei64_v_f16mf2(...) __riscv_vluxseg6ei64_v_f16mf2(__VA_ARGS__) -#define vluxseg7ei64_v_f16mf2(...) __riscv_vluxseg7ei64_v_f16mf2(__VA_ARGS__) -#define vluxseg8ei64_v_f16mf2(...) __riscv_vluxseg8ei64_v_f16mf2(__VA_ARGS__) -#define vluxseg2ei64_v_f16m1(...) __riscv_vluxseg2ei64_v_f16m1(__VA_ARGS__) -#define vluxseg3ei64_v_f16m1(...) __riscv_vluxseg3ei64_v_f16m1(__VA_ARGS__) -#define vluxseg4ei64_v_f16m1(...) __riscv_vluxseg4ei64_v_f16m1(__VA_ARGS__) -#define vluxseg5ei64_v_f16m1(...) __riscv_vluxseg5ei64_v_f16m1(__VA_ARGS__) -#define vluxseg6ei64_v_f16m1(...) __riscv_vluxseg6ei64_v_f16m1(__VA_ARGS__) -#define vluxseg7ei64_v_f16m1(...) __riscv_vluxseg7ei64_v_f16m1(__VA_ARGS__) -#define vluxseg8ei64_v_f16m1(...) __riscv_vluxseg8ei64_v_f16m1(__VA_ARGS__) -#define vluxseg2ei64_v_f16m2(...) __riscv_vluxseg2ei64_v_f16m2(__VA_ARGS__) -#define vluxseg3ei64_v_f16m2(...) __riscv_vluxseg3ei64_v_f16m2(__VA_ARGS__) -#define vluxseg4ei64_v_f16m2(...) __riscv_vluxseg4ei64_v_f16m2(__VA_ARGS__) -#define vluxseg2ei8_v_f32mf2(...) __riscv_vluxseg2ei8_v_f32mf2(__VA_ARGS__) -#define vluxseg3ei8_v_f32mf2(...) __riscv_vluxseg3ei8_v_f32mf2(__VA_ARGS__) -#define vluxseg4ei8_v_f32mf2(...) __riscv_vluxseg4ei8_v_f32mf2(__VA_ARGS__) -#define vluxseg5ei8_v_f32mf2(...) __riscv_vluxseg5ei8_v_f32mf2(__VA_ARGS__) -#define vluxseg6ei8_v_f32mf2(...) __riscv_vluxseg6ei8_v_f32mf2(__VA_ARGS__) -#define vluxseg7ei8_v_f32mf2(...) __riscv_vluxseg7ei8_v_f32mf2(__VA_ARGS__) -#define vluxseg8ei8_v_f32mf2(...) __riscv_vluxseg8ei8_v_f32mf2(__VA_ARGS__) -#define vluxseg2ei8_v_f32m1(...) __riscv_vluxseg2ei8_v_f32m1(__VA_ARGS__) -#define vluxseg3ei8_v_f32m1(...) __riscv_vluxseg3ei8_v_f32m1(__VA_ARGS__) -#define vluxseg4ei8_v_f32m1(...) __riscv_vluxseg4ei8_v_f32m1(__VA_ARGS__) -#define vluxseg5ei8_v_f32m1(...) __riscv_vluxseg5ei8_v_f32m1(__VA_ARGS__) -#define vluxseg6ei8_v_f32m1(...) __riscv_vluxseg6ei8_v_f32m1(__VA_ARGS__) -#define vluxseg7ei8_v_f32m1(...) __riscv_vluxseg7ei8_v_f32m1(__VA_ARGS__) -#define vluxseg8ei8_v_f32m1(...) __riscv_vluxseg8ei8_v_f32m1(__VA_ARGS__) -#define vluxseg2ei8_v_f32m2(...) __riscv_vluxseg2ei8_v_f32m2(__VA_ARGS__) -#define vluxseg3ei8_v_f32m2(...) __riscv_vluxseg3ei8_v_f32m2(__VA_ARGS__) -#define vluxseg4ei8_v_f32m2(...) __riscv_vluxseg4ei8_v_f32m2(__VA_ARGS__) -#define vluxseg2ei8_v_f32m4(...) __riscv_vluxseg2ei8_v_f32m4(__VA_ARGS__) -#define vluxseg2ei16_v_f32mf2(...) __riscv_vluxseg2ei16_v_f32mf2(__VA_ARGS__) -#define vluxseg3ei16_v_f32mf2(...) __riscv_vluxseg3ei16_v_f32mf2(__VA_ARGS__) -#define vluxseg4ei16_v_f32mf2(...) __riscv_vluxseg4ei16_v_f32mf2(__VA_ARGS__) -#define vluxseg5ei16_v_f32mf2(...) __riscv_vluxseg5ei16_v_f32mf2(__VA_ARGS__) -#define vluxseg6ei16_v_f32mf2(...) __riscv_vluxseg6ei16_v_f32mf2(__VA_ARGS__) -#define vluxseg7ei16_v_f32mf2(...) __riscv_vluxseg7ei16_v_f32mf2(__VA_ARGS__) -#define vluxseg8ei16_v_f32mf2(...) __riscv_vluxseg8ei16_v_f32mf2(__VA_ARGS__) -#define vluxseg2ei16_v_f32m1(...) __riscv_vluxseg2ei16_v_f32m1(__VA_ARGS__) -#define vluxseg3ei16_v_f32m1(...) __riscv_vluxseg3ei16_v_f32m1(__VA_ARGS__) -#define vluxseg4ei16_v_f32m1(...) __riscv_vluxseg4ei16_v_f32m1(__VA_ARGS__) -#define vluxseg5ei16_v_f32m1(...) __riscv_vluxseg5ei16_v_f32m1(__VA_ARGS__) -#define vluxseg6ei16_v_f32m1(...) __riscv_vluxseg6ei16_v_f32m1(__VA_ARGS__) -#define vluxseg7ei16_v_f32m1(...) __riscv_vluxseg7ei16_v_f32m1(__VA_ARGS__) -#define vluxseg8ei16_v_f32m1(...) __riscv_vluxseg8ei16_v_f32m1(__VA_ARGS__) -#define vluxseg2ei16_v_f32m2(...) __riscv_vluxseg2ei16_v_f32m2(__VA_ARGS__) -#define vluxseg3ei16_v_f32m2(...) __riscv_vluxseg3ei16_v_f32m2(__VA_ARGS__) -#define vluxseg4ei16_v_f32m2(...) __riscv_vluxseg4ei16_v_f32m2(__VA_ARGS__) -#define vluxseg2ei16_v_f32m4(...) __riscv_vluxseg2ei16_v_f32m4(__VA_ARGS__) -#define vluxseg2ei32_v_f32mf2(...) __riscv_vluxseg2ei32_v_f32mf2(__VA_ARGS__) -#define vluxseg3ei32_v_f32mf2(...) __riscv_vluxseg3ei32_v_f32mf2(__VA_ARGS__) -#define vluxseg4ei32_v_f32mf2(...) __riscv_vluxseg4ei32_v_f32mf2(__VA_ARGS__) -#define vluxseg5ei32_v_f32mf2(...) __riscv_vluxseg5ei32_v_f32mf2(__VA_ARGS__) -#define vluxseg6ei32_v_f32mf2(...) __riscv_vluxseg6ei32_v_f32mf2(__VA_ARGS__) -#define vluxseg7ei32_v_f32mf2(...) __riscv_vluxseg7ei32_v_f32mf2(__VA_ARGS__) -#define vluxseg8ei32_v_f32mf2(...) __riscv_vluxseg8ei32_v_f32mf2(__VA_ARGS__) -#define vluxseg2ei32_v_f32m1(...) __riscv_vluxseg2ei32_v_f32m1(__VA_ARGS__) -#define vluxseg3ei32_v_f32m1(...) __riscv_vluxseg3ei32_v_f32m1(__VA_ARGS__) -#define vluxseg4ei32_v_f32m1(...) __riscv_vluxseg4ei32_v_f32m1(__VA_ARGS__) -#define vluxseg5ei32_v_f32m1(...) __riscv_vluxseg5ei32_v_f32m1(__VA_ARGS__) -#define vluxseg6ei32_v_f32m1(...) __riscv_vluxseg6ei32_v_f32m1(__VA_ARGS__) -#define vluxseg7ei32_v_f32m1(...) __riscv_vluxseg7ei32_v_f32m1(__VA_ARGS__) -#define vluxseg8ei32_v_f32m1(...) __riscv_vluxseg8ei32_v_f32m1(__VA_ARGS__) -#define vluxseg2ei32_v_f32m2(...) __riscv_vluxseg2ei32_v_f32m2(__VA_ARGS__) -#define vluxseg3ei32_v_f32m2(...) __riscv_vluxseg3ei32_v_f32m2(__VA_ARGS__) -#define vluxseg4ei32_v_f32m2(...) __riscv_vluxseg4ei32_v_f32m2(__VA_ARGS__) -#define vluxseg2ei32_v_f32m4(...) __riscv_vluxseg2ei32_v_f32m4(__VA_ARGS__) -#define vluxseg2ei64_v_f32mf2(...) __riscv_vluxseg2ei64_v_f32mf2(__VA_ARGS__) -#define vluxseg3ei64_v_f32mf2(...) __riscv_vluxseg3ei64_v_f32mf2(__VA_ARGS__) -#define vluxseg4ei64_v_f32mf2(...) __riscv_vluxseg4ei64_v_f32mf2(__VA_ARGS__) -#define vluxseg5ei64_v_f32mf2(...) __riscv_vluxseg5ei64_v_f32mf2(__VA_ARGS__) -#define vluxseg6ei64_v_f32mf2(...) __riscv_vluxseg6ei64_v_f32mf2(__VA_ARGS__) -#define vluxseg7ei64_v_f32mf2(...) __riscv_vluxseg7ei64_v_f32mf2(__VA_ARGS__) -#define vluxseg8ei64_v_f32mf2(...) __riscv_vluxseg8ei64_v_f32mf2(__VA_ARGS__) -#define vluxseg2ei64_v_f32m1(...) __riscv_vluxseg2ei64_v_f32m1(__VA_ARGS__) -#define vluxseg3ei64_v_f32m1(...) __riscv_vluxseg3ei64_v_f32m1(__VA_ARGS__) -#define vluxseg4ei64_v_f32m1(...) __riscv_vluxseg4ei64_v_f32m1(__VA_ARGS__) -#define vluxseg5ei64_v_f32m1(...) __riscv_vluxseg5ei64_v_f32m1(__VA_ARGS__) -#define vluxseg6ei64_v_f32m1(...) __riscv_vluxseg6ei64_v_f32m1(__VA_ARGS__) -#define vluxseg7ei64_v_f32m1(...) __riscv_vluxseg7ei64_v_f32m1(__VA_ARGS__) -#define vluxseg8ei64_v_f32m1(...) __riscv_vluxseg8ei64_v_f32m1(__VA_ARGS__) -#define vluxseg2ei64_v_f32m2(...) __riscv_vluxseg2ei64_v_f32m2(__VA_ARGS__) -#define vluxseg3ei64_v_f32m2(...) __riscv_vluxseg3ei64_v_f32m2(__VA_ARGS__) -#define vluxseg4ei64_v_f32m2(...) __riscv_vluxseg4ei64_v_f32m2(__VA_ARGS__) -#define vluxseg2ei64_v_f32m4(...) __riscv_vluxseg2ei64_v_f32m4(__VA_ARGS__) -#define vluxseg2ei8_v_f64m1(...) __riscv_vluxseg2ei8_v_f64m1(__VA_ARGS__) -#define vluxseg3ei8_v_f64m1(...) __riscv_vluxseg3ei8_v_f64m1(__VA_ARGS__) -#define vluxseg4ei8_v_f64m1(...) __riscv_vluxseg4ei8_v_f64m1(__VA_ARGS__) -#define vluxseg5ei8_v_f64m1(...) __riscv_vluxseg5ei8_v_f64m1(__VA_ARGS__) -#define vluxseg6ei8_v_f64m1(...) __riscv_vluxseg6ei8_v_f64m1(__VA_ARGS__) -#define vluxseg7ei8_v_f64m1(...) __riscv_vluxseg7ei8_v_f64m1(__VA_ARGS__) -#define vluxseg8ei8_v_f64m1(...) __riscv_vluxseg8ei8_v_f64m1(__VA_ARGS__) -#define vluxseg2ei8_v_f64m2(...) __riscv_vluxseg2ei8_v_f64m2(__VA_ARGS__) -#define vluxseg3ei8_v_f64m2(...) __riscv_vluxseg3ei8_v_f64m2(__VA_ARGS__) -#define vluxseg4ei8_v_f64m2(...) __riscv_vluxseg4ei8_v_f64m2(__VA_ARGS__) -#define vluxseg2ei8_v_f64m4(...) __riscv_vluxseg2ei8_v_f64m4(__VA_ARGS__) -#define vluxseg2ei16_v_f64m1(...) __riscv_vluxseg2ei16_v_f64m1(__VA_ARGS__) -#define vluxseg3ei16_v_f64m1(...) __riscv_vluxseg3ei16_v_f64m1(__VA_ARGS__) -#define vluxseg4ei16_v_f64m1(...) __riscv_vluxseg4ei16_v_f64m1(__VA_ARGS__) -#define vluxseg5ei16_v_f64m1(...) __riscv_vluxseg5ei16_v_f64m1(__VA_ARGS__) -#define vluxseg6ei16_v_f64m1(...) __riscv_vluxseg6ei16_v_f64m1(__VA_ARGS__) -#define vluxseg7ei16_v_f64m1(...) __riscv_vluxseg7ei16_v_f64m1(__VA_ARGS__) -#define vluxseg8ei16_v_f64m1(...) __riscv_vluxseg8ei16_v_f64m1(__VA_ARGS__) -#define vluxseg2ei16_v_f64m2(...) __riscv_vluxseg2ei16_v_f64m2(__VA_ARGS__) -#define vluxseg3ei16_v_f64m2(...) __riscv_vluxseg3ei16_v_f64m2(__VA_ARGS__) -#define vluxseg4ei16_v_f64m2(...) __riscv_vluxseg4ei16_v_f64m2(__VA_ARGS__) -#define vluxseg2ei16_v_f64m4(...) __riscv_vluxseg2ei16_v_f64m4(__VA_ARGS__) -#define vluxseg2ei32_v_f64m1(...) __riscv_vluxseg2ei32_v_f64m1(__VA_ARGS__) -#define vluxseg3ei32_v_f64m1(...) __riscv_vluxseg3ei32_v_f64m1(__VA_ARGS__) -#define vluxseg4ei32_v_f64m1(...) __riscv_vluxseg4ei32_v_f64m1(__VA_ARGS__) -#define vluxseg5ei32_v_f64m1(...) __riscv_vluxseg5ei32_v_f64m1(__VA_ARGS__) -#define vluxseg6ei32_v_f64m1(...) __riscv_vluxseg6ei32_v_f64m1(__VA_ARGS__) -#define vluxseg7ei32_v_f64m1(...) __riscv_vluxseg7ei32_v_f64m1(__VA_ARGS__) -#define vluxseg8ei32_v_f64m1(...) __riscv_vluxseg8ei32_v_f64m1(__VA_ARGS__) -#define vluxseg2ei32_v_f64m2(...) __riscv_vluxseg2ei32_v_f64m2(__VA_ARGS__) -#define vluxseg3ei32_v_f64m2(...) __riscv_vluxseg3ei32_v_f64m2(__VA_ARGS__) -#define vluxseg4ei32_v_f64m2(...) __riscv_vluxseg4ei32_v_f64m2(__VA_ARGS__) -#define vluxseg2ei32_v_f64m4(...) __riscv_vluxseg2ei32_v_f64m4(__VA_ARGS__) -#define vluxseg2ei64_v_f64m1(...) __riscv_vluxseg2ei64_v_f64m1(__VA_ARGS__) -#define vluxseg3ei64_v_f64m1(...) __riscv_vluxseg3ei64_v_f64m1(__VA_ARGS__) -#define vluxseg4ei64_v_f64m1(...) __riscv_vluxseg4ei64_v_f64m1(__VA_ARGS__) -#define vluxseg5ei64_v_f64m1(...) __riscv_vluxseg5ei64_v_f64m1(__VA_ARGS__) -#define vluxseg6ei64_v_f64m1(...) __riscv_vluxseg6ei64_v_f64m1(__VA_ARGS__) -#define vluxseg7ei64_v_f64m1(...) __riscv_vluxseg7ei64_v_f64m1(__VA_ARGS__) -#define vluxseg8ei64_v_f64m1(...) __riscv_vluxseg8ei64_v_f64m1(__VA_ARGS__) -#define vluxseg2ei64_v_f64m2(...) __riscv_vluxseg2ei64_v_f64m2(__VA_ARGS__) -#define vluxseg3ei64_v_f64m2(...) __riscv_vluxseg3ei64_v_f64m2(__VA_ARGS__) -#define vluxseg4ei64_v_f64m2(...) __riscv_vluxseg4ei64_v_f64m2(__VA_ARGS__) -#define vluxseg2ei64_v_f64m4(...) __riscv_vluxseg2ei64_v_f64m4(__VA_ARGS__) -#define vloxseg2ei8_v_i8mf8(...) __riscv_vloxseg2ei8_v_i8mf8(__VA_ARGS__) -#define vloxseg3ei8_v_i8mf8(...) __riscv_vloxseg3ei8_v_i8mf8(__VA_ARGS__) -#define vloxseg4ei8_v_i8mf8(...) __riscv_vloxseg4ei8_v_i8mf8(__VA_ARGS__) -#define vloxseg5ei8_v_i8mf8(...) __riscv_vloxseg5ei8_v_i8mf8(__VA_ARGS__) -#define vloxseg6ei8_v_i8mf8(...) __riscv_vloxseg6ei8_v_i8mf8(__VA_ARGS__) -#define vloxseg7ei8_v_i8mf8(...) __riscv_vloxseg7ei8_v_i8mf8(__VA_ARGS__) -#define vloxseg8ei8_v_i8mf8(...) __riscv_vloxseg8ei8_v_i8mf8(__VA_ARGS__) -#define vloxseg2ei8_v_i8mf4(...) __riscv_vloxseg2ei8_v_i8mf4(__VA_ARGS__) -#define vloxseg3ei8_v_i8mf4(...) __riscv_vloxseg3ei8_v_i8mf4(__VA_ARGS__) -#define vloxseg4ei8_v_i8mf4(...) __riscv_vloxseg4ei8_v_i8mf4(__VA_ARGS__) -#define vloxseg5ei8_v_i8mf4(...) __riscv_vloxseg5ei8_v_i8mf4(__VA_ARGS__) -#define vloxseg6ei8_v_i8mf4(...) __riscv_vloxseg6ei8_v_i8mf4(__VA_ARGS__) -#define vloxseg7ei8_v_i8mf4(...) __riscv_vloxseg7ei8_v_i8mf4(__VA_ARGS__) -#define vloxseg8ei8_v_i8mf4(...) __riscv_vloxseg8ei8_v_i8mf4(__VA_ARGS__) -#define vloxseg2ei8_v_i8mf2(...) __riscv_vloxseg2ei8_v_i8mf2(__VA_ARGS__) -#define vloxseg3ei8_v_i8mf2(...) __riscv_vloxseg3ei8_v_i8mf2(__VA_ARGS__) -#define vloxseg4ei8_v_i8mf2(...) __riscv_vloxseg4ei8_v_i8mf2(__VA_ARGS__) -#define vloxseg5ei8_v_i8mf2(...) __riscv_vloxseg5ei8_v_i8mf2(__VA_ARGS__) -#define vloxseg6ei8_v_i8mf2(...) __riscv_vloxseg6ei8_v_i8mf2(__VA_ARGS__) -#define vloxseg7ei8_v_i8mf2(...) __riscv_vloxseg7ei8_v_i8mf2(__VA_ARGS__) -#define vloxseg8ei8_v_i8mf2(...) __riscv_vloxseg8ei8_v_i8mf2(__VA_ARGS__) -#define vloxseg2ei8_v_i8m1(...) __riscv_vloxseg2ei8_v_i8m1(__VA_ARGS__) -#define vloxseg3ei8_v_i8m1(...) __riscv_vloxseg3ei8_v_i8m1(__VA_ARGS__) -#define vloxseg4ei8_v_i8m1(...) __riscv_vloxseg4ei8_v_i8m1(__VA_ARGS__) -#define vloxseg5ei8_v_i8m1(...) __riscv_vloxseg5ei8_v_i8m1(__VA_ARGS__) -#define vloxseg6ei8_v_i8m1(...) __riscv_vloxseg6ei8_v_i8m1(__VA_ARGS__) -#define vloxseg7ei8_v_i8m1(...) __riscv_vloxseg7ei8_v_i8m1(__VA_ARGS__) -#define vloxseg8ei8_v_i8m1(...) __riscv_vloxseg8ei8_v_i8m1(__VA_ARGS__) -#define vloxseg2ei8_v_i8m2(...) __riscv_vloxseg2ei8_v_i8m2(__VA_ARGS__) -#define vloxseg3ei8_v_i8m2(...) __riscv_vloxseg3ei8_v_i8m2(__VA_ARGS__) -#define vloxseg4ei8_v_i8m2(...) __riscv_vloxseg4ei8_v_i8m2(__VA_ARGS__) -#define vloxseg2ei8_v_i8m4(...) __riscv_vloxseg2ei8_v_i8m4(__VA_ARGS__) -#define vloxseg2ei16_v_i8mf8(...) __riscv_vloxseg2ei16_v_i8mf8(__VA_ARGS__) -#define vloxseg3ei16_v_i8mf8(...) __riscv_vloxseg3ei16_v_i8mf8(__VA_ARGS__) -#define vloxseg4ei16_v_i8mf8(...) __riscv_vloxseg4ei16_v_i8mf8(__VA_ARGS__) -#define vloxseg5ei16_v_i8mf8(...) __riscv_vloxseg5ei16_v_i8mf8(__VA_ARGS__) -#define vloxseg6ei16_v_i8mf8(...) __riscv_vloxseg6ei16_v_i8mf8(__VA_ARGS__) -#define vloxseg7ei16_v_i8mf8(...) __riscv_vloxseg7ei16_v_i8mf8(__VA_ARGS__) -#define vloxseg8ei16_v_i8mf8(...) __riscv_vloxseg8ei16_v_i8mf8(__VA_ARGS__) -#define vloxseg2ei16_v_i8mf4(...) __riscv_vloxseg2ei16_v_i8mf4(__VA_ARGS__) -#define vloxseg3ei16_v_i8mf4(...) __riscv_vloxseg3ei16_v_i8mf4(__VA_ARGS__) -#define vloxseg4ei16_v_i8mf4(...) __riscv_vloxseg4ei16_v_i8mf4(__VA_ARGS__) -#define vloxseg5ei16_v_i8mf4(...) __riscv_vloxseg5ei16_v_i8mf4(__VA_ARGS__) -#define vloxseg6ei16_v_i8mf4(...) __riscv_vloxseg6ei16_v_i8mf4(__VA_ARGS__) -#define vloxseg7ei16_v_i8mf4(...) __riscv_vloxseg7ei16_v_i8mf4(__VA_ARGS__) -#define vloxseg8ei16_v_i8mf4(...) __riscv_vloxseg8ei16_v_i8mf4(__VA_ARGS__) -#define vloxseg2ei16_v_i8mf2(...) __riscv_vloxseg2ei16_v_i8mf2(__VA_ARGS__) -#define vloxseg3ei16_v_i8mf2(...) __riscv_vloxseg3ei16_v_i8mf2(__VA_ARGS__) -#define vloxseg4ei16_v_i8mf2(...) __riscv_vloxseg4ei16_v_i8mf2(__VA_ARGS__) -#define vloxseg5ei16_v_i8mf2(...) __riscv_vloxseg5ei16_v_i8mf2(__VA_ARGS__) -#define vloxseg6ei16_v_i8mf2(...) __riscv_vloxseg6ei16_v_i8mf2(__VA_ARGS__) -#define vloxseg7ei16_v_i8mf2(...) __riscv_vloxseg7ei16_v_i8mf2(__VA_ARGS__) -#define vloxseg8ei16_v_i8mf2(...) __riscv_vloxseg8ei16_v_i8mf2(__VA_ARGS__) -#define vloxseg2ei16_v_i8m1(...) __riscv_vloxseg2ei16_v_i8m1(__VA_ARGS__) -#define vloxseg3ei16_v_i8m1(...) __riscv_vloxseg3ei16_v_i8m1(__VA_ARGS__) -#define vloxseg4ei16_v_i8m1(...) __riscv_vloxseg4ei16_v_i8m1(__VA_ARGS__) -#define vloxseg5ei16_v_i8m1(...) __riscv_vloxseg5ei16_v_i8m1(__VA_ARGS__) -#define vloxseg6ei16_v_i8m1(...) __riscv_vloxseg6ei16_v_i8m1(__VA_ARGS__) -#define vloxseg7ei16_v_i8m1(...) __riscv_vloxseg7ei16_v_i8m1(__VA_ARGS__) -#define vloxseg8ei16_v_i8m1(...) __riscv_vloxseg8ei16_v_i8m1(__VA_ARGS__) -#define vloxseg2ei16_v_i8m2(...) __riscv_vloxseg2ei16_v_i8m2(__VA_ARGS__) -#define vloxseg3ei16_v_i8m2(...) __riscv_vloxseg3ei16_v_i8m2(__VA_ARGS__) -#define vloxseg4ei16_v_i8m2(...) __riscv_vloxseg4ei16_v_i8m2(__VA_ARGS__) -#define vloxseg2ei16_v_i8m4(...) __riscv_vloxseg2ei16_v_i8m4(__VA_ARGS__) -#define vloxseg2ei32_v_i8mf8(...) __riscv_vloxseg2ei32_v_i8mf8(__VA_ARGS__) -#define vloxseg3ei32_v_i8mf8(...) __riscv_vloxseg3ei32_v_i8mf8(__VA_ARGS__) -#define vloxseg4ei32_v_i8mf8(...) __riscv_vloxseg4ei32_v_i8mf8(__VA_ARGS__) -#define vloxseg5ei32_v_i8mf8(...) __riscv_vloxseg5ei32_v_i8mf8(__VA_ARGS__) -#define vloxseg6ei32_v_i8mf8(...) __riscv_vloxseg6ei32_v_i8mf8(__VA_ARGS__) -#define vloxseg7ei32_v_i8mf8(...) __riscv_vloxseg7ei32_v_i8mf8(__VA_ARGS__) -#define vloxseg8ei32_v_i8mf8(...) __riscv_vloxseg8ei32_v_i8mf8(__VA_ARGS__) -#define vloxseg2ei32_v_i8mf4(...) __riscv_vloxseg2ei32_v_i8mf4(__VA_ARGS__) -#define vloxseg3ei32_v_i8mf4(...) __riscv_vloxseg3ei32_v_i8mf4(__VA_ARGS__) -#define vloxseg4ei32_v_i8mf4(...) __riscv_vloxseg4ei32_v_i8mf4(__VA_ARGS__) -#define vloxseg5ei32_v_i8mf4(...) __riscv_vloxseg5ei32_v_i8mf4(__VA_ARGS__) -#define vloxseg6ei32_v_i8mf4(...) __riscv_vloxseg6ei32_v_i8mf4(__VA_ARGS__) -#define vloxseg7ei32_v_i8mf4(...) __riscv_vloxseg7ei32_v_i8mf4(__VA_ARGS__) -#define vloxseg8ei32_v_i8mf4(...) __riscv_vloxseg8ei32_v_i8mf4(__VA_ARGS__) -#define vloxseg2ei32_v_i8mf2(...) __riscv_vloxseg2ei32_v_i8mf2(__VA_ARGS__) -#define vloxseg3ei32_v_i8mf2(...) __riscv_vloxseg3ei32_v_i8mf2(__VA_ARGS__) -#define vloxseg4ei32_v_i8mf2(...) __riscv_vloxseg4ei32_v_i8mf2(__VA_ARGS__) -#define vloxseg5ei32_v_i8mf2(...) __riscv_vloxseg5ei32_v_i8mf2(__VA_ARGS__) -#define vloxseg6ei32_v_i8mf2(...) __riscv_vloxseg6ei32_v_i8mf2(__VA_ARGS__) -#define vloxseg7ei32_v_i8mf2(...) __riscv_vloxseg7ei32_v_i8mf2(__VA_ARGS__) -#define vloxseg8ei32_v_i8mf2(...) __riscv_vloxseg8ei32_v_i8mf2(__VA_ARGS__) -#define vloxseg2ei32_v_i8m1(...) __riscv_vloxseg2ei32_v_i8m1(__VA_ARGS__) -#define vloxseg3ei32_v_i8m1(...) __riscv_vloxseg3ei32_v_i8m1(__VA_ARGS__) -#define vloxseg4ei32_v_i8m1(...) __riscv_vloxseg4ei32_v_i8m1(__VA_ARGS__) -#define vloxseg5ei32_v_i8m1(...) __riscv_vloxseg5ei32_v_i8m1(__VA_ARGS__) -#define vloxseg6ei32_v_i8m1(...) __riscv_vloxseg6ei32_v_i8m1(__VA_ARGS__) -#define vloxseg7ei32_v_i8m1(...) __riscv_vloxseg7ei32_v_i8m1(__VA_ARGS__) -#define vloxseg8ei32_v_i8m1(...) __riscv_vloxseg8ei32_v_i8m1(__VA_ARGS__) -#define vloxseg2ei32_v_i8m2(...) __riscv_vloxseg2ei32_v_i8m2(__VA_ARGS__) -#define vloxseg3ei32_v_i8m2(...) __riscv_vloxseg3ei32_v_i8m2(__VA_ARGS__) -#define vloxseg4ei32_v_i8m2(...) __riscv_vloxseg4ei32_v_i8m2(__VA_ARGS__) -#define vloxseg2ei64_v_i8mf8(...) __riscv_vloxseg2ei64_v_i8mf8(__VA_ARGS__) -#define vloxseg3ei64_v_i8mf8(...) __riscv_vloxseg3ei64_v_i8mf8(__VA_ARGS__) -#define vloxseg4ei64_v_i8mf8(...) __riscv_vloxseg4ei64_v_i8mf8(__VA_ARGS__) -#define vloxseg5ei64_v_i8mf8(...) __riscv_vloxseg5ei64_v_i8mf8(__VA_ARGS__) -#define vloxseg6ei64_v_i8mf8(...) __riscv_vloxseg6ei64_v_i8mf8(__VA_ARGS__) -#define vloxseg7ei64_v_i8mf8(...) __riscv_vloxseg7ei64_v_i8mf8(__VA_ARGS__) -#define vloxseg8ei64_v_i8mf8(...) __riscv_vloxseg8ei64_v_i8mf8(__VA_ARGS__) -#define vloxseg2ei64_v_i8mf4(...) __riscv_vloxseg2ei64_v_i8mf4(__VA_ARGS__) -#define vloxseg3ei64_v_i8mf4(...) __riscv_vloxseg3ei64_v_i8mf4(__VA_ARGS__) -#define vloxseg4ei64_v_i8mf4(...) __riscv_vloxseg4ei64_v_i8mf4(__VA_ARGS__) -#define vloxseg5ei64_v_i8mf4(...) __riscv_vloxseg5ei64_v_i8mf4(__VA_ARGS__) -#define vloxseg6ei64_v_i8mf4(...) __riscv_vloxseg6ei64_v_i8mf4(__VA_ARGS__) -#define vloxseg7ei64_v_i8mf4(...) __riscv_vloxseg7ei64_v_i8mf4(__VA_ARGS__) -#define vloxseg8ei64_v_i8mf4(...) __riscv_vloxseg8ei64_v_i8mf4(__VA_ARGS__) -#define vloxseg2ei64_v_i8mf2(...) __riscv_vloxseg2ei64_v_i8mf2(__VA_ARGS__) -#define vloxseg3ei64_v_i8mf2(...) __riscv_vloxseg3ei64_v_i8mf2(__VA_ARGS__) -#define vloxseg4ei64_v_i8mf2(...) __riscv_vloxseg4ei64_v_i8mf2(__VA_ARGS__) -#define vloxseg5ei64_v_i8mf2(...) __riscv_vloxseg5ei64_v_i8mf2(__VA_ARGS__) -#define vloxseg6ei64_v_i8mf2(...) __riscv_vloxseg6ei64_v_i8mf2(__VA_ARGS__) -#define vloxseg7ei64_v_i8mf2(...) __riscv_vloxseg7ei64_v_i8mf2(__VA_ARGS__) -#define vloxseg8ei64_v_i8mf2(...) __riscv_vloxseg8ei64_v_i8mf2(__VA_ARGS__) -#define vloxseg2ei64_v_i8m1(...) __riscv_vloxseg2ei64_v_i8m1(__VA_ARGS__) -#define vloxseg3ei64_v_i8m1(...) __riscv_vloxseg3ei64_v_i8m1(__VA_ARGS__) -#define vloxseg4ei64_v_i8m1(...) __riscv_vloxseg4ei64_v_i8m1(__VA_ARGS__) -#define vloxseg5ei64_v_i8m1(...) __riscv_vloxseg5ei64_v_i8m1(__VA_ARGS__) -#define vloxseg6ei64_v_i8m1(...) __riscv_vloxseg6ei64_v_i8m1(__VA_ARGS__) -#define vloxseg7ei64_v_i8m1(...) __riscv_vloxseg7ei64_v_i8m1(__VA_ARGS__) -#define vloxseg8ei64_v_i8m1(...) __riscv_vloxseg8ei64_v_i8m1(__VA_ARGS__) -#define vloxseg2ei8_v_i16mf4(...) __riscv_vloxseg2ei8_v_i16mf4(__VA_ARGS__) -#define vloxseg3ei8_v_i16mf4(...) __riscv_vloxseg3ei8_v_i16mf4(__VA_ARGS__) -#define vloxseg4ei8_v_i16mf4(...) __riscv_vloxseg4ei8_v_i16mf4(__VA_ARGS__) -#define vloxseg5ei8_v_i16mf4(...) __riscv_vloxseg5ei8_v_i16mf4(__VA_ARGS__) -#define vloxseg6ei8_v_i16mf4(...) __riscv_vloxseg6ei8_v_i16mf4(__VA_ARGS__) -#define vloxseg7ei8_v_i16mf4(...) __riscv_vloxseg7ei8_v_i16mf4(__VA_ARGS__) -#define vloxseg8ei8_v_i16mf4(...) __riscv_vloxseg8ei8_v_i16mf4(__VA_ARGS__) -#define vloxseg2ei8_v_i16mf2(...) __riscv_vloxseg2ei8_v_i16mf2(__VA_ARGS__) -#define vloxseg3ei8_v_i16mf2(...) __riscv_vloxseg3ei8_v_i16mf2(__VA_ARGS__) -#define vloxseg4ei8_v_i16mf2(...) __riscv_vloxseg4ei8_v_i16mf2(__VA_ARGS__) -#define vloxseg5ei8_v_i16mf2(...) __riscv_vloxseg5ei8_v_i16mf2(__VA_ARGS__) -#define vloxseg6ei8_v_i16mf2(...) __riscv_vloxseg6ei8_v_i16mf2(__VA_ARGS__) -#define vloxseg7ei8_v_i16mf2(...) __riscv_vloxseg7ei8_v_i16mf2(__VA_ARGS__) -#define vloxseg8ei8_v_i16mf2(...) __riscv_vloxseg8ei8_v_i16mf2(__VA_ARGS__) -#define vloxseg2ei8_v_i16m1(...) __riscv_vloxseg2ei8_v_i16m1(__VA_ARGS__) -#define vloxseg3ei8_v_i16m1(...) __riscv_vloxseg3ei8_v_i16m1(__VA_ARGS__) -#define vloxseg4ei8_v_i16m1(...) __riscv_vloxseg4ei8_v_i16m1(__VA_ARGS__) -#define vloxseg5ei8_v_i16m1(...) __riscv_vloxseg5ei8_v_i16m1(__VA_ARGS__) -#define vloxseg6ei8_v_i16m1(...) __riscv_vloxseg6ei8_v_i16m1(__VA_ARGS__) -#define vloxseg7ei8_v_i16m1(...) __riscv_vloxseg7ei8_v_i16m1(__VA_ARGS__) -#define vloxseg8ei8_v_i16m1(...) __riscv_vloxseg8ei8_v_i16m1(__VA_ARGS__) -#define vloxseg2ei8_v_i16m2(...) __riscv_vloxseg2ei8_v_i16m2(__VA_ARGS__) -#define vloxseg3ei8_v_i16m2(...) __riscv_vloxseg3ei8_v_i16m2(__VA_ARGS__) -#define vloxseg4ei8_v_i16m2(...) __riscv_vloxseg4ei8_v_i16m2(__VA_ARGS__) -#define vloxseg2ei8_v_i16m4(...) __riscv_vloxseg2ei8_v_i16m4(__VA_ARGS__) -#define vloxseg2ei16_v_i16mf4(...) __riscv_vloxseg2ei16_v_i16mf4(__VA_ARGS__) -#define vloxseg3ei16_v_i16mf4(...) __riscv_vloxseg3ei16_v_i16mf4(__VA_ARGS__) -#define vloxseg4ei16_v_i16mf4(...) __riscv_vloxseg4ei16_v_i16mf4(__VA_ARGS__) -#define vloxseg5ei16_v_i16mf4(...) __riscv_vloxseg5ei16_v_i16mf4(__VA_ARGS__) -#define vloxseg6ei16_v_i16mf4(...) __riscv_vloxseg6ei16_v_i16mf4(__VA_ARGS__) -#define vloxseg7ei16_v_i16mf4(...) __riscv_vloxseg7ei16_v_i16mf4(__VA_ARGS__) -#define vloxseg8ei16_v_i16mf4(...) __riscv_vloxseg8ei16_v_i16mf4(__VA_ARGS__) -#define vloxseg2ei16_v_i16mf2(...) __riscv_vloxseg2ei16_v_i16mf2(__VA_ARGS__) -#define vloxseg3ei16_v_i16mf2(...) __riscv_vloxseg3ei16_v_i16mf2(__VA_ARGS__) -#define vloxseg4ei16_v_i16mf2(...) __riscv_vloxseg4ei16_v_i16mf2(__VA_ARGS__) -#define vloxseg5ei16_v_i16mf2(...) __riscv_vloxseg5ei16_v_i16mf2(__VA_ARGS__) -#define vloxseg6ei16_v_i16mf2(...) __riscv_vloxseg6ei16_v_i16mf2(__VA_ARGS__) -#define vloxseg7ei16_v_i16mf2(...) __riscv_vloxseg7ei16_v_i16mf2(__VA_ARGS__) -#define vloxseg8ei16_v_i16mf2(...) __riscv_vloxseg8ei16_v_i16mf2(__VA_ARGS__) -#define vloxseg2ei16_v_i16m1(...) __riscv_vloxseg2ei16_v_i16m1(__VA_ARGS__) -#define vloxseg3ei16_v_i16m1(...) __riscv_vloxseg3ei16_v_i16m1(__VA_ARGS__) -#define vloxseg4ei16_v_i16m1(...) __riscv_vloxseg4ei16_v_i16m1(__VA_ARGS__) -#define vloxseg5ei16_v_i16m1(...) __riscv_vloxseg5ei16_v_i16m1(__VA_ARGS__) -#define vloxseg6ei16_v_i16m1(...) __riscv_vloxseg6ei16_v_i16m1(__VA_ARGS__) -#define vloxseg7ei16_v_i16m1(...) __riscv_vloxseg7ei16_v_i16m1(__VA_ARGS__) -#define vloxseg8ei16_v_i16m1(...) __riscv_vloxseg8ei16_v_i16m1(__VA_ARGS__) -#define vloxseg2ei16_v_i16m2(...) __riscv_vloxseg2ei16_v_i16m2(__VA_ARGS__) -#define vloxseg3ei16_v_i16m2(...) __riscv_vloxseg3ei16_v_i16m2(__VA_ARGS__) -#define vloxseg4ei16_v_i16m2(...) __riscv_vloxseg4ei16_v_i16m2(__VA_ARGS__) -#define vloxseg2ei16_v_i16m4(...) __riscv_vloxseg2ei16_v_i16m4(__VA_ARGS__) -#define vloxseg2ei32_v_i16mf4(...) __riscv_vloxseg2ei32_v_i16mf4(__VA_ARGS__) -#define vloxseg3ei32_v_i16mf4(...) __riscv_vloxseg3ei32_v_i16mf4(__VA_ARGS__) -#define vloxseg4ei32_v_i16mf4(...) __riscv_vloxseg4ei32_v_i16mf4(__VA_ARGS__) -#define vloxseg5ei32_v_i16mf4(...) __riscv_vloxseg5ei32_v_i16mf4(__VA_ARGS__) -#define vloxseg6ei32_v_i16mf4(...) __riscv_vloxseg6ei32_v_i16mf4(__VA_ARGS__) -#define vloxseg7ei32_v_i16mf4(...) __riscv_vloxseg7ei32_v_i16mf4(__VA_ARGS__) -#define vloxseg8ei32_v_i16mf4(...) __riscv_vloxseg8ei32_v_i16mf4(__VA_ARGS__) -#define vloxseg2ei32_v_i16mf2(...) __riscv_vloxseg2ei32_v_i16mf2(__VA_ARGS__) -#define vloxseg3ei32_v_i16mf2(...) __riscv_vloxseg3ei32_v_i16mf2(__VA_ARGS__) -#define vloxseg4ei32_v_i16mf2(...) __riscv_vloxseg4ei32_v_i16mf2(__VA_ARGS__) -#define vloxseg5ei32_v_i16mf2(...) __riscv_vloxseg5ei32_v_i16mf2(__VA_ARGS__) -#define vloxseg6ei32_v_i16mf2(...) __riscv_vloxseg6ei32_v_i16mf2(__VA_ARGS__) -#define vloxseg7ei32_v_i16mf2(...) __riscv_vloxseg7ei32_v_i16mf2(__VA_ARGS__) -#define vloxseg8ei32_v_i16mf2(...) __riscv_vloxseg8ei32_v_i16mf2(__VA_ARGS__) -#define vloxseg2ei32_v_i16m1(...) __riscv_vloxseg2ei32_v_i16m1(__VA_ARGS__) -#define vloxseg3ei32_v_i16m1(...) __riscv_vloxseg3ei32_v_i16m1(__VA_ARGS__) -#define vloxseg4ei32_v_i16m1(...) __riscv_vloxseg4ei32_v_i16m1(__VA_ARGS__) -#define vloxseg5ei32_v_i16m1(...) __riscv_vloxseg5ei32_v_i16m1(__VA_ARGS__) -#define vloxseg6ei32_v_i16m1(...) __riscv_vloxseg6ei32_v_i16m1(__VA_ARGS__) -#define vloxseg7ei32_v_i16m1(...) __riscv_vloxseg7ei32_v_i16m1(__VA_ARGS__) -#define vloxseg8ei32_v_i16m1(...) __riscv_vloxseg8ei32_v_i16m1(__VA_ARGS__) -#define vloxseg2ei32_v_i16m2(...) __riscv_vloxseg2ei32_v_i16m2(__VA_ARGS__) -#define vloxseg3ei32_v_i16m2(...) __riscv_vloxseg3ei32_v_i16m2(__VA_ARGS__) -#define vloxseg4ei32_v_i16m2(...) __riscv_vloxseg4ei32_v_i16m2(__VA_ARGS__) -#define vloxseg2ei32_v_i16m4(...) __riscv_vloxseg2ei32_v_i16m4(__VA_ARGS__) -#define vloxseg2ei64_v_i16mf4(...) __riscv_vloxseg2ei64_v_i16mf4(__VA_ARGS__) -#define vloxseg3ei64_v_i16mf4(...) __riscv_vloxseg3ei64_v_i16mf4(__VA_ARGS__) -#define vloxseg4ei64_v_i16mf4(...) __riscv_vloxseg4ei64_v_i16mf4(__VA_ARGS__) -#define vloxseg5ei64_v_i16mf4(...) __riscv_vloxseg5ei64_v_i16mf4(__VA_ARGS__) -#define vloxseg6ei64_v_i16mf4(...) __riscv_vloxseg6ei64_v_i16mf4(__VA_ARGS__) -#define vloxseg7ei64_v_i16mf4(...) __riscv_vloxseg7ei64_v_i16mf4(__VA_ARGS__) -#define vloxseg8ei64_v_i16mf4(...) __riscv_vloxseg8ei64_v_i16mf4(__VA_ARGS__) -#define vloxseg2ei64_v_i16mf2(...) __riscv_vloxseg2ei64_v_i16mf2(__VA_ARGS__) -#define vloxseg3ei64_v_i16mf2(...) __riscv_vloxseg3ei64_v_i16mf2(__VA_ARGS__) -#define vloxseg4ei64_v_i16mf2(...) __riscv_vloxseg4ei64_v_i16mf2(__VA_ARGS__) -#define vloxseg5ei64_v_i16mf2(...) __riscv_vloxseg5ei64_v_i16mf2(__VA_ARGS__) -#define vloxseg6ei64_v_i16mf2(...) __riscv_vloxseg6ei64_v_i16mf2(__VA_ARGS__) -#define vloxseg7ei64_v_i16mf2(...) __riscv_vloxseg7ei64_v_i16mf2(__VA_ARGS__) -#define vloxseg8ei64_v_i16mf2(...) __riscv_vloxseg8ei64_v_i16mf2(__VA_ARGS__) -#define vloxseg2ei64_v_i16m1(...) __riscv_vloxseg2ei64_v_i16m1(__VA_ARGS__) -#define vloxseg3ei64_v_i16m1(...) __riscv_vloxseg3ei64_v_i16m1(__VA_ARGS__) -#define vloxseg4ei64_v_i16m1(...) __riscv_vloxseg4ei64_v_i16m1(__VA_ARGS__) -#define vloxseg5ei64_v_i16m1(...) __riscv_vloxseg5ei64_v_i16m1(__VA_ARGS__) -#define vloxseg6ei64_v_i16m1(...) __riscv_vloxseg6ei64_v_i16m1(__VA_ARGS__) -#define vloxseg7ei64_v_i16m1(...) __riscv_vloxseg7ei64_v_i16m1(__VA_ARGS__) -#define vloxseg8ei64_v_i16m1(...) __riscv_vloxseg8ei64_v_i16m1(__VA_ARGS__) -#define vloxseg2ei64_v_i16m2(...) __riscv_vloxseg2ei64_v_i16m2(__VA_ARGS__) -#define vloxseg3ei64_v_i16m2(...) __riscv_vloxseg3ei64_v_i16m2(__VA_ARGS__) -#define vloxseg4ei64_v_i16m2(...) __riscv_vloxseg4ei64_v_i16m2(__VA_ARGS__) -#define vloxseg2ei8_v_i32mf2(...) __riscv_vloxseg2ei8_v_i32mf2(__VA_ARGS__) -#define vloxseg3ei8_v_i32mf2(...) __riscv_vloxseg3ei8_v_i32mf2(__VA_ARGS__) -#define vloxseg4ei8_v_i32mf2(...) __riscv_vloxseg4ei8_v_i32mf2(__VA_ARGS__) -#define vloxseg5ei8_v_i32mf2(...) __riscv_vloxseg5ei8_v_i32mf2(__VA_ARGS__) -#define vloxseg6ei8_v_i32mf2(...) __riscv_vloxseg6ei8_v_i32mf2(__VA_ARGS__) -#define vloxseg7ei8_v_i32mf2(...) __riscv_vloxseg7ei8_v_i32mf2(__VA_ARGS__) -#define vloxseg8ei8_v_i32mf2(...) __riscv_vloxseg8ei8_v_i32mf2(__VA_ARGS__) -#define vloxseg2ei8_v_i32m1(...) __riscv_vloxseg2ei8_v_i32m1(__VA_ARGS__) -#define vloxseg3ei8_v_i32m1(...) __riscv_vloxseg3ei8_v_i32m1(__VA_ARGS__) -#define vloxseg4ei8_v_i32m1(...) __riscv_vloxseg4ei8_v_i32m1(__VA_ARGS__) -#define vloxseg5ei8_v_i32m1(...) __riscv_vloxseg5ei8_v_i32m1(__VA_ARGS__) -#define vloxseg6ei8_v_i32m1(...) __riscv_vloxseg6ei8_v_i32m1(__VA_ARGS__) -#define vloxseg7ei8_v_i32m1(...) __riscv_vloxseg7ei8_v_i32m1(__VA_ARGS__) -#define vloxseg8ei8_v_i32m1(...) __riscv_vloxseg8ei8_v_i32m1(__VA_ARGS__) -#define vloxseg2ei8_v_i32m2(...) __riscv_vloxseg2ei8_v_i32m2(__VA_ARGS__) -#define vloxseg3ei8_v_i32m2(...) __riscv_vloxseg3ei8_v_i32m2(__VA_ARGS__) -#define vloxseg4ei8_v_i32m2(...) __riscv_vloxseg4ei8_v_i32m2(__VA_ARGS__) -#define vloxseg2ei8_v_i32m4(...) __riscv_vloxseg2ei8_v_i32m4(__VA_ARGS__) -#define vloxseg2ei16_v_i32mf2(...) __riscv_vloxseg2ei16_v_i32mf2(__VA_ARGS__) -#define vloxseg3ei16_v_i32mf2(...) __riscv_vloxseg3ei16_v_i32mf2(__VA_ARGS__) -#define vloxseg4ei16_v_i32mf2(...) __riscv_vloxseg4ei16_v_i32mf2(__VA_ARGS__) -#define vloxseg5ei16_v_i32mf2(...) __riscv_vloxseg5ei16_v_i32mf2(__VA_ARGS__) -#define vloxseg6ei16_v_i32mf2(...) __riscv_vloxseg6ei16_v_i32mf2(__VA_ARGS__) -#define vloxseg7ei16_v_i32mf2(...) __riscv_vloxseg7ei16_v_i32mf2(__VA_ARGS__) -#define vloxseg8ei16_v_i32mf2(...) __riscv_vloxseg8ei16_v_i32mf2(__VA_ARGS__) -#define vloxseg2ei16_v_i32m1(...) __riscv_vloxseg2ei16_v_i32m1(__VA_ARGS__) -#define vloxseg3ei16_v_i32m1(...) __riscv_vloxseg3ei16_v_i32m1(__VA_ARGS__) -#define vloxseg4ei16_v_i32m1(...) __riscv_vloxseg4ei16_v_i32m1(__VA_ARGS__) -#define vloxseg5ei16_v_i32m1(...) __riscv_vloxseg5ei16_v_i32m1(__VA_ARGS__) -#define vloxseg6ei16_v_i32m1(...) __riscv_vloxseg6ei16_v_i32m1(__VA_ARGS__) -#define vloxseg7ei16_v_i32m1(...) __riscv_vloxseg7ei16_v_i32m1(__VA_ARGS__) -#define vloxseg8ei16_v_i32m1(...) __riscv_vloxseg8ei16_v_i32m1(__VA_ARGS__) -#define vloxseg2ei16_v_i32m2(...) __riscv_vloxseg2ei16_v_i32m2(__VA_ARGS__) -#define vloxseg3ei16_v_i32m2(...) __riscv_vloxseg3ei16_v_i32m2(__VA_ARGS__) -#define vloxseg4ei16_v_i32m2(...) __riscv_vloxseg4ei16_v_i32m2(__VA_ARGS__) -#define vloxseg2ei16_v_i32m4(...) __riscv_vloxseg2ei16_v_i32m4(__VA_ARGS__) -#define vloxseg2ei32_v_i32mf2(...) __riscv_vloxseg2ei32_v_i32mf2(__VA_ARGS__) -#define vloxseg3ei32_v_i32mf2(...) __riscv_vloxseg3ei32_v_i32mf2(__VA_ARGS__) -#define vloxseg4ei32_v_i32mf2(...) __riscv_vloxseg4ei32_v_i32mf2(__VA_ARGS__) -#define vloxseg5ei32_v_i32mf2(...) __riscv_vloxseg5ei32_v_i32mf2(__VA_ARGS__) -#define vloxseg6ei32_v_i32mf2(...) __riscv_vloxseg6ei32_v_i32mf2(__VA_ARGS__) -#define vloxseg7ei32_v_i32mf2(...) __riscv_vloxseg7ei32_v_i32mf2(__VA_ARGS__) -#define vloxseg8ei32_v_i32mf2(...) __riscv_vloxseg8ei32_v_i32mf2(__VA_ARGS__) -#define vloxseg2ei32_v_i32m1(...) __riscv_vloxseg2ei32_v_i32m1(__VA_ARGS__) -#define vloxseg3ei32_v_i32m1(...) __riscv_vloxseg3ei32_v_i32m1(__VA_ARGS__) -#define vloxseg4ei32_v_i32m1(...) __riscv_vloxseg4ei32_v_i32m1(__VA_ARGS__) -#define vloxseg5ei32_v_i32m1(...) __riscv_vloxseg5ei32_v_i32m1(__VA_ARGS__) -#define vloxseg6ei32_v_i32m1(...) __riscv_vloxseg6ei32_v_i32m1(__VA_ARGS__) -#define vloxseg7ei32_v_i32m1(...) __riscv_vloxseg7ei32_v_i32m1(__VA_ARGS__) -#define vloxseg8ei32_v_i32m1(...) __riscv_vloxseg8ei32_v_i32m1(__VA_ARGS__) -#define vloxseg2ei32_v_i32m2(...) __riscv_vloxseg2ei32_v_i32m2(__VA_ARGS__) -#define vloxseg3ei32_v_i32m2(...) __riscv_vloxseg3ei32_v_i32m2(__VA_ARGS__) -#define vloxseg4ei32_v_i32m2(...) __riscv_vloxseg4ei32_v_i32m2(__VA_ARGS__) -#define vloxseg2ei32_v_i32m4(...) __riscv_vloxseg2ei32_v_i32m4(__VA_ARGS__) -#define vloxseg2ei64_v_i32mf2(...) __riscv_vloxseg2ei64_v_i32mf2(__VA_ARGS__) -#define vloxseg3ei64_v_i32mf2(...) __riscv_vloxseg3ei64_v_i32mf2(__VA_ARGS__) -#define vloxseg4ei64_v_i32mf2(...) __riscv_vloxseg4ei64_v_i32mf2(__VA_ARGS__) -#define vloxseg5ei64_v_i32mf2(...) __riscv_vloxseg5ei64_v_i32mf2(__VA_ARGS__) -#define vloxseg6ei64_v_i32mf2(...) __riscv_vloxseg6ei64_v_i32mf2(__VA_ARGS__) -#define vloxseg7ei64_v_i32mf2(...) __riscv_vloxseg7ei64_v_i32mf2(__VA_ARGS__) -#define vloxseg8ei64_v_i32mf2(...) __riscv_vloxseg8ei64_v_i32mf2(__VA_ARGS__) -#define vloxseg2ei64_v_i32m1(...) __riscv_vloxseg2ei64_v_i32m1(__VA_ARGS__) -#define vloxseg3ei64_v_i32m1(...) __riscv_vloxseg3ei64_v_i32m1(__VA_ARGS__) -#define vloxseg4ei64_v_i32m1(...) __riscv_vloxseg4ei64_v_i32m1(__VA_ARGS__) -#define vloxseg5ei64_v_i32m1(...) __riscv_vloxseg5ei64_v_i32m1(__VA_ARGS__) -#define vloxseg6ei64_v_i32m1(...) __riscv_vloxseg6ei64_v_i32m1(__VA_ARGS__) -#define vloxseg7ei64_v_i32m1(...) __riscv_vloxseg7ei64_v_i32m1(__VA_ARGS__) -#define vloxseg8ei64_v_i32m1(...) __riscv_vloxseg8ei64_v_i32m1(__VA_ARGS__) -#define vloxseg2ei64_v_i32m2(...) __riscv_vloxseg2ei64_v_i32m2(__VA_ARGS__) -#define vloxseg3ei64_v_i32m2(...) __riscv_vloxseg3ei64_v_i32m2(__VA_ARGS__) -#define vloxseg4ei64_v_i32m2(...) __riscv_vloxseg4ei64_v_i32m2(__VA_ARGS__) -#define vloxseg2ei64_v_i32m4(...) __riscv_vloxseg2ei64_v_i32m4(__VA_ARGS__) -#define vloxseg2ei8_v_i64m1(...) __riscv_vloxseg2ei8_v_i64m1(__VA_ARGS__) -#define vloxseg3ei8_v_i64m1(...) __riscv_vloxseg3ei8_v_i64m1(__VA_ARGS__) -#define vloxseg4ei8_v_i64m1(...) __riscv_vloxseg4ei8_v_i64m1(__VA_ARGS__) -#define vloxseg5ei8_v_i64m1(...) __riscv_vloxseg5ei8_v_i64m1(__VA_ARGS__) -#define vloxseg6ei8_v_i64m1(...) __riscv_vloxseg6ei8_v_i64m1(__VA_ARGS__) -#define vloxseg7ei8_v_i64m1(...) __riscv_vloxseg7ei8_v_i64m1(__VA_ARGS__) -#define vloxseg8ei8_v_i64m1(...) __riscv_vloxseg8ei8_v_i64m1(__VA_ARGS__) -#define vloxseg2ei8_v_i64m2(...) __riscv_vloxseg2ei8_v_i64m2(__VA_ARGS__) -#define vloxseg3ei8_v_i64m2(...) __riscv_vloxseg3ei8_v_i64m2(__VA_ARGS__) -#define vloxseg4ei8_v_i64m2(...) __riscv_vloxseg4ei8_v_i64m2(__VA_ARGS__) -#define vloxseg2ei8_v_i64m4(...) __riscv_vloxseg2ei8_v_i64m4(__VA_ARGS__) -#define vloxseg2ei16_v_i64m1(...) __riscv_vloxseg2ei16_v_i64m1(__VA_ARGS__) -#define vloxseg3ei16_v_i64m1(...) __riscv_vloxseg3ei16_v_i64m1(__VA_ARGS__) -#define vloxseg4ei16_v_i64m1(...) __riscv_vloxseg4ei16_v_i64m1(__VA_ARGS__) -#define vloxseg5ei16_v_i64m1(...) __riscv_vloxseg5ei16_v_i64m1(__VA_ARGS__) -#define vloxseg6ei16_v_i64m1(...) __riscv_vloxseg6ei16_v_i64m1(__VA_ARGS__) -#define vloxseg7ei16_v_i64m1(...) __riscv_vloxseg7ei16_v_i64m1(__VA_ARGS__) -#define vloxseg8ei16_v_i64m1(...) __riscv_vloxseg8ei16_v_i64m1(__VA_ARGS__) -#define vloxseg2ei16_v_i64m2(...) __riscv_vloxseg2ei16_v_i64m2(__VA_ARGS__) -#define vloxseg3ei16_v_i64m2(...) __riscv_vloxseg3ei16_v_i64m2(__VA_ARGS__) -#define vloxseg4ei16_v_i64m2(...) __riscv_vloxseg4ei16_v_i64m2(__VA_ARGS__) -#define vloxseg2ei16_v_i64m4(...) __riscv_vloxseg2ei16_v_i64m4(__VA_ARGS__) -#define vloxseg2ei32_v_i64m1(...) __riscv_vloxseg2ei32_v_i64m1(__VA_ARGS__) -#define vloxseg3ei32_v_i64m1(...) __riscv_vloxseg3ei32_v_i64m1(__VA_ARGS__) -#define vloxseg4ei32_v_i64m1(...) __riscv_vloxseg4ei32_v_i64m1(__VA_ARGS__) -#define vloxseg5ei32_v_i64m1(...) __riscv_vloxseg5ei32_v_i64m1(__VA_ARGS__) -#define vloxseg6ei32_v_i64m1(...) __riscv_vloxseg6ei32_v_i64m1(__VA_ARGS__) -#define vloxseg7ei32_v_i64m1(...) __riscv_vloxseg7ei32_v_i64m1(__VA_ARGS__) -#define vloxseg8ei32_v_i64m1(...) __riscv_vloxseg8ei32_v_i64m1(__VA_ARGS__) -#define vloxseg2ei32_v_i64m2(...) __riscv_vloxseg2ei32_v_i64m2(__VA_ARGS__) -#define vloxseg3ei32_v_i64m2(...) __riscv_vloxseg3ei32_v_i64m2(__VA_ARGS__) -#define vloxseg4ei32_v_i64m2(...) __riscv_vloxseg4ei32_v_i64m2(__VA_ARGS__) -#define vloxseg2ei32_v_i64m4(...) __riscv_vloxseg2ei32_v_i64m4(__VA_ARGS__) -#define vloxseg2ei64_v_i64m1(...) __riscv_vloxseg2ei64_v_i64m1(__VA_ARGS__) -#define vloxseg3ei64_v_i64m1(...) __riscv_vloxseg3ei64_v_i64m1(__VA_ARGS__) -#define vloxseg4ei64_v_i64m1(...) __riscv_vloxseg4ei64_v_i64m1(__VA_ARGS__) -#define vloxseg5ei64_v_i64m1(...) __riscv_vloxseg5ei64_v_i64m1(__VA_ARGS__) -#define vloxseg6ei64_v_i64m1(...) __riscv_vloxseg6ei64_v_i64m1(__VA_ARGS__) -#define vloxseg7ei64_v_i64m1(...) __riscv_vloxseg7ei64_v_i64m1(__VA_ARGS__) -#define vloxseg8ei64_v_i64m1(...) __riscv_vloxseg8ei64_v_i64m1(__VA_ARGS__) -#define vloxseg2ei64_v_i64m2(...) __riscv_vloxseg2ei64_v_i64m2(__VA_ARGS__) -#define vloxseg3ei64_v_i64m2(...) __riscv_vloxseg3ei64_v_i64m2(__VA_ARGS__) -#define vloxseg4ei64_v_i64m2(...) __riscv_vloxseg4ei64_v_i64m2(__VA_ARGS__) -#define vloxseg2ei64_v_i64m4(...) __riscv_vloxseg2ei64_v_i64m4(__VA_ARGS__) -#define vluxseg2ei8_v_i8mf8(...) __riscv_vluxseg2ei8_v_i8mf8(__VA_ARGS__) -#define vluxseg3ei8_v_i8mf8(...) __riscv_vluxseg3ei8_v_i8mf8(__VA_ARGS__) -#define vluxseg4ei8_v_i8mf8(...) __riscv_vluxseg4ei8_v_i8mf8(__VA_ARGS__) -#define vluxseg5ei8_v_i8mf8(...) __riscv_vluxseg5ei8_v_i8mf8(__VA_ARGS__) -#define vluxseg6ei8_v_i8mf8(...) __riscv_vluxseg6ei8_v_i8mf8(__VA_ARGS__) -#define vluxseg7ei8_v_i8mf8(...) __riscv_vluxseg7ei8_v_i8mf8(__VA_ARGS__) -#define vluxseg8ei8_v_i8mf8(...) __riscv_vluxseg8ei8_v_i8mf8(__VA_ARGS__) -#define vluxseg2ei8_v_i8mf4(...) __riscv_vluxseg2ei8_v_i8mf4(__VA_ARGS__) -#define vluxseg3ei8_v_i8mf4(...) __riscv_vluxseg3ei8_v_i8mf4(__VA_ARGS__) -#define vluxseg4ei8_v_i8mf4(...) __riscv_vluxseg4ei8_v_i8mf4(__VA_ARGS__) -#define vluxseg5ei8_v_i8mf4(...) __riscv_vluxseg5ei8_v_i8mf4(__VA_ARGS__) -#define vluxseg6ei8_v_i8mf4(...) __riscv_vluxseg6ei8_v_i8mf4(__VA_ARGS__) -#define vluxseg7ei8_v_i8mf4(...) __riscv_vluxseg7ei8_v_i8mf4(__VA_ARGS__) -#define vluxseg8ei8_v_i8mf4(...) __riscv_vluxseg8ei8_v_i8mf4(__VA_ARGS__) -#define vluxseg2ei8_v_i8mf2(...) __riscv_vluxseg2ei8_v_i8mf2(__VA_ARGS__) -#define vluxseg3ei8_v_i8mf2(...) __riscv_vluxseg3ei8_v_i8mf2(__VA_ARGS__) -#define vluxseg4ei8_v_i8mf2(...) __riscv_vluxseg4ei8_v_i8mf2(__VA_ARGS__) -#define vluxseg5ei8_v_i8mf2(...) __riscv_vluxseg5ei8_v_i8mf2(__VA_ARGS__) -#define vluxseg6ei8_v_i8mf2(...) __riscv_vluxseg6ei8_v_i8mf2(__VA_ARGS__) -#define vluxseg7ei8_v_i8mf2(...) __riscv_vluxseg7ei8_v_i8mf2(__VA_ARGS__) -#define vluxseg8ei8_v_i8mf2(...) __riscv_vluxseg8ei8_v_i8mf2(__VA_ARGS__) -#define vluxseg2ei8_v_i8m1(...) __riscv_vluxseg2ei8_v_i8m1(__VA_ARGS__) -#define vluxseg3ei8_v_i8m1(...) __riscv_vluxseg3ei8_v_i8m1(__VA_ARGS__) -#define vluxseg4ei8_v_i8m1(...) __riscv_vluxseg4ei8_v_i8m1(__VA_ARGS__) -#define vluxseg5ei8_v_i8m1(...) __riscv_vluxseg5ei8_v_i8m1(__VA_ARGS__) -#define vluxseg6ei8_v_i8m1(...) __riscv_vluxseg6ei8_v_i8m1(__VA_ARGS__) -#define vluxseg7ei8_v_i8m1(...) __riscv_vluxseg7ei8_v_i8m1(__VA_ARGS__) -#define vluxseg8ei8_v_i8m1(...) __riscv_vluxseg8ei8_v_i8m1(__VA_ARGS__) -#define vluxseg2ei8_v_i8m2(...) __riscv_vluxseg2ei8_v_i8m2(__VA_ARGS__) -#define vluxseg3ei8_v_i8m2(...) __riscv_vluxseg3ei8_v_i8m2(__VA_ARGS__) -#define vluxseg4ei8_v_i8m2(...) __riscv_vluxseg4ei8_v_i8m2(__VA_ARGS__) -#define vluxseg2ei8_v_i8m4(...) __riscv_vluxseg2ei8_v_i8m4(__VA_ARGS__) -#define vluxseg2ei16_v_i8mf8(...) __riscv_vluxseg2ei16_v_i8mf8(__VA_ARGS__) -#define vluxseg3ei16_v_i8mf8(...) __riscv_vluxseg3ei16_v_i8mf8(__VA_ARGS__) -#define vluxseg4ei16_v_i8mf8(...) __riscv_vluxseg4ei16_v_i8mf8(__VA_ARGS__) -#define vluxseg5ei16_v_i8mf8(...) __riscv_vluxseg5ei16_v_i8mf8(__VA_ARGS__) -#define vluxseg6ei16_v_i8mf8(...) __riscv_vluxseg6ei16_v_i8mf8(__VA_ARGS__) -#define vluxseg7ei16_v_i8mf8(...) __riscv_vluxseg7ei16_v_i8mf8(__VA_ARGS__) -#define vluxseg8ei16_v_i8mf8(...) __riscv_vluxseg8ei16_v_i8mf8(__VA_ARGS__) -#define vluxseg2ei16_v_i8mf4(...) __riscv_vluxseg2ei16_v_i8mf4(__VA_ARGS__) -#define vluxseg3ei16_v_i8mf4(...) __riscv_vluxseg3ei16_v_i8mf4(__VA_ARGS__) -#define vluxseg4ei16_v_i8mf4(...) __riscv_vluxseg4ei16_v_i8mf4(__VA_ARGS__) -#define vluxseg5ei16_v_i8mf4(...) __riscv_vluxseg5ei16_v_i8mf4(__VA_ARGS__) -#define vluxseg6ei16_v_i8mf4(...) __riscv_vluxseg6ei16_v_i8mf4(__VA_ARGS__) -#define vluxseg7ei16_v_i8mf4(...) __riscv_vluxseg7ei16_v_i8mf4(__VA_ARGS__) -#define vluxseg8ei16_v_i8mf4(...) __riscv_vluxseg8ei16_v_i8mf4(__VA_ARGS__) -#define vluxseg2ei16_v_i8mf2(...) __riscv_vluxseg2ei16_v_i8mf2(__VA_ARGS__) -#define vluxseg3ei16_v_i8mf2(...) __riscv_vluxseg3ei16_v_i8mf2(__VA_ARGS__) -#define vluxseg4ei16_v_i8mf2(...) __riscv_vluxseg4ei16_v_i8mf2(__VA_ARGS__) -#define vluxseg5ei16_v_i8mf2(...) __riscv_vluxseg5ei16_v_i8mf2(__VA_ARGS__) -#define vluxseg6ei16_v_i8mf2(...) __riscv_vluxseg6ei16_v_i8mf2(__VA_ARGS__) -#define vluxseg7ei16_v_i8mf2(...) __riscv_vluxseg7ei16_v_i8mf2(__VA_ARGS__) -#define vluxseg8ei16_v_i8mf2(...) __riscv_vluxseg8ei16_v_i8mf2(__VA_ARGS__) -#define vluxseg2ei16_v_i8m1(...) __riscv_vluxseg2ei16_v_i8m1(__VA_ARGS__) -#define vluxseg3ei16_v_i8m1(...) __riscv_vluxseg3ei16_v_i8m1(__VA_ARGS__) -#define vluxseg4ei16_v_i8m1(...) __riscv_vluxseg4ei16_v_i8m1(__VA_ARGS__) -#define vluxseg5ei16_v_i8m1(...) __riscv_vluxseg5ei16_v_i8m1(__VA_ARGS__) -#define vluxseg6ei16_v_i8m1(...) __riscv_vluxseg6ei16_v_i8m1(__VA_ARGS__) -#define vluxseg7ei16_v_i8m1(...) __riscv_vluxseg7ei16_v_i8m1(__VA_ARGS__) -#define vluxseg8ei16_v_i8m1(...) __riscv_vluxseg8ei16_v_i8m1(__VA_ARGS__) -#define vluxseg2ei16_v_i8m2(...) __riscv_vluxseg2ei16_v_i8m2(__VA_ARGS__) -#define vluxseg3ei16_v_i8m2(...) __riscv_vluxseg3ei16_v_i8m2(__VA_ARGS__) -#define vluxseg4ei16_v_i8m2(...) __riscv_vluxseg4ei16_v_i8m2(__VA_ARGS__) -#define vluxseg2ei16_v_i8m4(...) __riscv_vluxseg2ei16_v_i8m4(__VA_ARGS__) -#define vluxseg2ei32_v_i8mf8(...) __riscv_vluxseg2ei32_v_i8mf8(__VA_ARGS__) -#define vluxseg3ei32_v_i8mf8(...) __riscv_vluxseg3ei32_v_i8mf8(__VA_ARGS__) -#define vluxseg4ei32_v_i8mf8(...) __riscv_vluxseg4ei32_v_i8mf8(__VA_ARGS__) -#define vluxseg5ei32_v_i8mf8(...) __riscv_vluxseg5ei32_v_i8mf8(__VA_ARGS__) -#define vluxseg6ei32_v_i8mf8(...) __riscv_vluxseg6ei32_v_i8mf8(__VA_ARGS__) -#define vluxseg7ei32_v_i8mf8(...) __riscv_vluxseg7ei32_v_i8mf8(__VA_ARGS__) -#define vluxseg8ei32_v_i8mf8(...) __riscv_vluxseg8ei32_v_i8mf8(__VA_ARGS__) -#define vluxseg2ei32_v_i8mf4(...) __riscv_vluxseg2ei32_v_i8mf4(__VA_ARGS__) -#define vluxseg3ei32_v_i8mf4(...) __riscv_vluxseg3ei32_v_i8mf4(__VA_ARGS__) -#define vluxseg4ei32_v_i8mf4(...) __riscv_vluxseg4ei32_v_i8mf4(__VA_ARGS__) -#define vluxseg5ei32_v_i8mf4(...) __riscv_vluxseg5ei32_v_i8mf4(__VA_ARGS__) -#define vluxseg6ei32_v_i8mf4(...) __riscv_vluxseg6ei32_v_i8mf4(__VA_ARGS__) -#define vluxseg7ei32_v_i8mf4(...) __riscv_vluxseg7ei32_v_i8mf4(__VA_ARGS__) -#define vluxseg8ei32_v_i8mf4(...) __riscv_vluxseg8ei32_v_i8mf4(__VA_ARGS__) -#define vluxseg2ei32_v_i8mf2(...) __riscv_vluxseg2ei32_v_i8mf2(__VA_ARGS__) -#define vluxseg3ei32_v_i8mf2(...) __riscv_vluxseg3ei32_v_i8mf2(__VA_ARGS__) -#define vluxseg4ei32_v_i8mf2(...) __riscv_vluxseg4ei32_v_i8mf2(__VA_ARGS__) -#define vluxseg5ei32_v_i8mf2(...) __riscv_vluxseg5ei32_v_i8mf2(__VA_ARGS__) -#define vluxseg6ei32_v_i8mf2(...) __riscv_vluxseg6ei32_v_i8mf2(__VA_ARGS__) -#define vluxseg7ei32_v_i8mf2(...) __riscv_vluxseg7ei32_v_i8mf2(__VA_ARGS__) -#define vluxseg8ei32_v_i8mf2(...) __riscv_vluxseg8ei32_v_i8mf2(__VA_ARGS__) -#define vluxseg2ei32_v_i8m1(...) __riscv_vluxseg2ei32_v_i8m1(__VA_ARGS__) -#define vluxseg3ei32_v_i8m1(...) __riscv_vluxseg3ei32_v_i8m1(__VA_ARGS__) -#define vluxseg4ei32_v_i8m1(...) __riscv_vluxseg4ei32_v_i8m1(__VA_ARGS__) -#define vluxseg5ei32_v_i8m1(...) __riscv_vluxseg5ei32_v_i8m1(__VA_ARGS__) -#define vluxseg6ei32_v_i8m1(...) __riscv_vluxseg6ei32_v_i8m1(__VA_ARGS__) -#define vluxseg7ei32_v_i8m1(...) __riscv_vluxseg7ei32_v_i8m1(__VA_ARGS__) -#define vluxseg8ei32_v_i8m1(...) __riscv_vluxseg8ei32_v_i8m1(__VA_ARGS__) -#define vluxseg2ei32_v_i8m2(...) __riscv_vluxseg2ei32_v_i8m2(__VA_ARGS__) -#define vluxseg3ei32_v_i8m2(...) __riscv_vluxseg3ei32_v_i8m2(__VA_ARGS__) -#define vluxseg4ei32_v_i8m2(...) __riscv_vluxseg4ei32_v_i8m2(__VA_ARGS__) -#define vluxseg2ei64_v_i8mf8(...) __riscv_vluxseg2ei64_v_i8mf8(__VA_ARGS__) -#define vluxseg3ei64_v_i8mf8(...) __riscv_vluxseg3ei64_v_i8mf8(__VA_ARGS__) -#define vluxseg4ei64_v_i8mf8(...) __riscv_vluxseg4ei64_v_i8mf8(__VA_ARGS__) -#define vluxseg5ei64_v_i8mf8(...) __riscv_vluxseg5ei64_v_i8mf8(__VA_ARGS__) -#define vluxseg6ei64_v_i8mf8(...) __riscv_vluxseg6ei64_v_i8mf8(__VA_ARGS__) -#define vluxseg7ei64_v_i8mf8(...) __riscv_vluxseg7ei64_v_i8mf8(__VA_ARGS__) -#define vluxseg8ei64_v_i8mf8(...) __riscv_vluxseg8ei64_v_i8mf8(__VA_ARGS__) -#define vluxseg2ei64_v_i8mf4(...) __riscv_vluxseg2ei64_v_i8mf4(__VA_ARGS__) -#define vluxseg3ei64_v_i8mf4(...) __riscv_vluxseg3ei64_v_i8mf4(__VA_ARGS__) -#define vluxseg4ei64_v_i8mf4(...) __riscv_vluxseg4ei64_v_i8mf4(__VA_ARGS__) -#define vluxseg5ei64_v_i8mf4(...) __riscv_vluxseg5ei64_v_i8mf4(__VA_ARGS__) -#define vluxseg6ei64_v_i8mf4(...) __riscv_vluxseg6ei64_v_i8mf4(__VA_ARGS__) -#define vluxseg7ei64_v_i8mf4(...) __riscv_vluxseg7ei64_v_i8mf4(__VA_ARGS__) -#define vluxseg8ei64_v_i8mf4(...) __riscv_vluxseg8ei64_v_i8mf4(__VA_ARGS__) -#define vluxseg2ei64_v_i8mf2(...) __riscv_vluxseg2ei64_v_i8mf2(__VA_ARGS__) -#define vluxseg3ei64_v_i8mf2(...) __riscv_vluxseg3ei64_v_i8mf2(__VA_ARGS__) -#define vluxseg4ei64_v_i8mf2(...) __riscv_vluxseg4ei64_v_i8mf2(__VA_ARGS__) -#define vluxseg5ei64_v_i8mf2(...) __riscv_vluxseg5ei64_v_i8mf2(__VA_ARGS__) -#define vluxseg6ei64_v_i8mf2(...) __riscv_vluxseg6ei64_v_i8mf2(__VA_ARGS__) -#define vluxseg7ei64_v_i8mf2(...) __riscv_vluxseg7ei64_v_i8mf2(__VA_ARGS__) -#define vluxseg8ei64_v_i8mf2(...) __riscv_vluxseg8ei64_v_i8mf2(__VA_ARGS__) -#define vluxseg2ei64_v_i8m1(...) __riscv_vluxseg2ei64_v_i8m1(__VA_ARGS__) -#define vluxseg3ei64_v_i8m1(...) __riscv_vluxseg3ei64_v_i8m1(__VA_ARGS__) -#define vluxseg4ei64_v_i8m1(...) __riscv_vluxseg4ei64_v_i8m1(__VA_ARGS__) -#define vluxseg5ei64_v_i8m1(...) __riscv_vluxseg5ei64_v_i8m1(__VA_ARGS__) -#define vluxseg6ei64_v_i8m1(...) __riscv_vluxseg6ei64_v_i8m1(__VA_ARGS__) -#define vluxseg7ei64_v_i8m1(...) __riscv_vluxseg7ei64_v_i8m1(__VA_ARGS__) -#define vluxseg8ei64_v_i8m1(...) __riscv_vluxseg8ei64_v_i8m1(__VA_ARGS__) -#define vluxseg2ei8_v_i16mf4(...) __riscv_vluxseg2ei8_v_i16mf4(__VA_ARGS__) -#define vluxseg3ei8_v_i16mf4(...) __riscv_vluxseg3ei8_v_i16mf4(__VA_ARGS__) -#define vluxseg4ei8_v_i16mf4(...) __riscv_vluxseg4ei8_v_i16mf4(__VA_ARGS__) -#define vluxseg5ei8_v_i16mf4(...) __riscv_vluxseg5ei8_v_i16mf4(__VA_ARGS__) -#define vluxseg6ei8_v_i16mf4(...) __riscv_vluxseg6ei8_v_i16mf4(__VA_ARGS__) -#define vluxseg7ei8_v_i16mf4(...) __riscv_vluxseg7ei8_v_i16mf4(__VA_ARGS__) -#define vluxseg8ei8_v_i16mf4(...) __riscv_vluxseg8ei8_v_i16mf4(__VA_ARGS__) -#define vluxseg2ei8_v_i16mf2(...) __riscv_vluxseg2ei8_v_i16mf2(__VA_ARGS__) -#define vluxseg3ei8_v_i16mf2(...) __riscv_vluxseg3ei8_v_i16mf2(__VA_ARGS__) -#define vluxseg4ei8_v_i16mf2(...) __riscv_vluxseg4ei8_v_i16mf2(__VA_ARGS__) -#define vluxseg5ei8_v_i16mf2(...) __riscv_vluxseg5ei8_v_i16mf2(__VA_ARGS__) -#define vluxseg6ei8_v_i16mf2(...) __riscv_vluxseg6ei8_v_i16mf2(__VA_ARGS__) -#define vluxseg7ei8_v_i16mf2(...) __riscv_vluxseg7ei8_v_i16mf2(__VA_ARGS__) -#define vluxseg8ei8_v_i16mf2(...) __riscv_vluxseg8ei8_v_i16mf2(__VA_ARGS__) -#define vluxseg2ei8_v_i16m1(...) __riscv_vluxseg2ei8_v_i16m1(__VA_ARGS__) -#define vluxseg3ei8_v_i16m1(...) __riscv_vluxseg3ei8_v_i16m1(__VA_ARGS__) -#define vluxseg4ei8_v_i16m1(...) __riscv_vluxseg4ei8_v_i16m1(__VA_ARGS__) -#define vluxseg5ei8_v_i16m1(...) __riscv_vluxseg5ei8_v_i16m1(__VA_ARGS__) -#define vluxseg6ei8_v_i16m1(...) __riscv_vluxseg6ei8_v_i16m1(__VA_ARGS__) -#define vluxseg7ei8_v_i16m1(...) __riscv_vluxseg7ei8_v_i16m1(__VA_ARGS__) -#define vluxseg8ei8_v_i16m1(...) __riscv_vluxseg8ei8_v_i16m1(__VA_ARGS__) -#define vluxseg2ei8_v_i16m2(...) __riscv_vluxseg2ei8_v_i16m2(__VA_ARGS__) -#define vluxseg3ei8_v_i16m2(...) __riscv_vluxseg3ei8_v_i16m2(__VA_ARGS__) -#define vluxseg4ei8_v_i16m2(...) __riscv_vluxseg4ei8_v_i16m2(__VA_ARGS__) -#define vluxseg2ei8_v_i16m4(...) __riscv_vluxseg2ei8_v_i16m4(__VA_ARGS__) -#define vluxseg2ei16_v_i16mf4(...) __riscv_vluxseg2ei16_v_i16mf4(__VA_ARGS__) -#define vluxseg3ei16_v_i16mf4(...) __riscv_vluxseg3ei16_v_i16mf4(__VA_ARGS__) -#define vluxseg4ei16_v_i16mf4(...) __riscv_vluxseg4ei16_v_i16mf4(__VA_ARGS__) -#define vluxseg5ei16_v_i16mf4(...) __riscv_vluxseg5ei16_v_i16mf4(__VA_ARGS__) -#define vluxseg6ei16_v_i16mf4(...) __riscv_vluxseg6ei16_v_i16mf4(__VA_ARGS__) -#define vluxseg7ei16_v_i16mf4(...) __riscv_vluxseg7ei16_v_i16mf4(__VA_ARGS__) -#define vluxseg8ei16_v_i16mf4(...) __riscv_vluxseg8ei16_v_i16mf4(__VA_ARGS__) -#define vluxseg2ei16_v_i16mf2(...) __riscv_vluxseg2ei16_v_i16mf2(__VA_ARGS__) -#define vluxseg3ei16_v_i16mf2(...) __riscv_vluxseg3ei16_v_i16mf2(__VA_ARGS__) -#define vluxseg4ei16_v_i16mf2(...) __riscv_vluxseg4ei16_v_i16mf2(__VA_ARGS__) -#define vluxseg5ei16_v_i16mf2(...) __riscv_vluxseg5ei16_v_i16mf2(__VA_ARGS__) -#define vluxseg6ei16_v_i16mf2(...) __riscv_vluxseg6ei16_v_i16mf2(__VA_ARGS__) -#define vluxseg7ei16_v_i16mf2(...) __riscv_vluxseg7ei16_v_i16mf2(__VA_ARGS__) -#define vluxseg8ei16_v_i16mf2(...) __riscv_vluxseg8ei16_v_i16mf2(__VA_ARGS__) -#define vluxseg2ei16_v_i16m1(...) __riscv_vluxseg2ei16_v_i16m1(__VA_ARGS__) -#define vluxseg3ei16_v_i16m1(...) __riscv_vluxseg3ei16_v_i16m1(__VA_ARGS__) -#define vluxseg4ei16_v_i16m1(...) __riscv_vluxseg4ei16_v_i16m1(__VA_ARGS__) -#define vluxseg5ei16_v_i16m1(...) __riscv_vluxseg5ei16_v_i16m1(__VA_ARGS__) -#define vluxseg6ei16_v_i16m1(...) __riscv_vluxseg6ei16_v_i16m1(__VA_ARGS__) -#define vluxseg7ei16_v_i16m1(...) __riscv_vluxseg7ei16_v_i16m1(__VA_ARGS__) -#define vluxseg8ei16_v_i16m1(...) __riscv_vluxseg8ei16_v_i16m1(__VA_ARGS__) -#define vluxseg2ei16_v_i16m2(...) __riscv_vluxseg2ei16_v_i16m2(__VA_ARGS__) -#define vluxseg3ei16_v_i16m2(...) __riscv_vluxseg3ei16_v_i16m2(__VA_ARGS__) -#define vluxseg4ei16_v_i16m2(...) __riscv_vluxseg4ei16_v_i16m2(__VA_ARGS__) -#define vluxseg2ei16_v_i16m4(...) __riscv_vluxseg2ei16_v_i16m4(__VA_ARGS__) -#define vluxseg2ei32_v_i16mf4(...) __riscv_vluxseg2ei32_v_i16mf4(__VA_ARGS__) -#define vluxseg3ei32_v_i16mf4(...) __riscv_vluxseg3ei32_v_i16mf4(__VA_ARGS__) -#define vluxseg4ei32_v_i16mf4(...) __riscv_vluxseg4ei32_v_i16mf4(__VA_ARGS__) -#define vluxseg5ei32_v_i16mf4(...) __riscv_vluxseg5ei32_v_i16mf4(__VA_ARGS__) -#define vluxseg6ei32_v_i16mf4(...) __riscv_vluxseg6ei32_v_i16mf4(__VA_ARGS__) -#define vluxseg7ei32_v_i16mf4(...) __riscv_vluxseg7ei32_v_i16mf4(__VA_ARGS__) -#define vluxseg8ei32_v_i16mf4(...) __riscv_vluxseg8ei32_v_i16mf4(__VA_ARGS__) -#define vluxseg2ei32_v_i16mf2(...) __riscv_vluxseg2ei32_v_i16mf2(__VA_ARGS__) -#define vluxseg3ei32_v_i16mf2(...) __riscv_vluxseg3ei32_v_i16mf2(__VA_ARGS__) -#define vluxseg4ei32_v_i16mf2(...) __riscv_vluxseg4ei32_v_i16mf2(__VA_ARGS__) -#define vluxseg5ei32_v_i16mf2(...) __riscv_vluxseg5ei32_v_i16mf2(__VA_ARGS__) -#define vluxseg6ei32_v_i16mf2(...) __riscv_vluxseg6ei32_v_i16mf2(__VA_ARGS__) -#define vluxseg7ei32_v_i16mf2(...) __riscv_vluxseg7ei32_v_i16mf2(__VA_ARGS__) -#define vluxseg8ei32_v_i16mf2(...) __riscv_vluxseg8ei32_v_i16mf2(__VA_ARGS__) -#define vluxseg2ei32_v_i16m1(...) __riscv_vluxseg2ei32_v_i16m1(__VA_ARGS__) -#define vluxseg3ei32_v_i16m1(...) __riscv_vluxseg3ei32_v_i16m1(__VA_ARGS__) -#define vluxseg4ei32_v_i16m1(...) __riscv_vluxseg4ei32_v_i16m1(__VA_ARGS__) -#define vluxseg5ei32_v_i16m1(...) __riscv_vluxseg5ei32_v_i16m1(__VA_ARGS__) -#define vluxseg6ei32_v_i16m1(...) __riscv_vluxseg6ei32_v_i16m1(__VA_ARGS__) -#define vluxseg7ei32_v_i16m1(...) __riscv_vluxseg7ei32_v_i16m1(__VA_ARGS__) -#define vluxseg8ei32_v_i16m1(...) __riscv_vluxseg8ei32_v_i16m1(__VA_ARGS__) -#define vluxseg2ei32_v_i16m2(...) __riscv_vluxseg2ei32_v_i16m2(__VA_ARGS__) -#define vluxseg3ei32_v_i16m2(...) __riscv_vluxseg3ei32_v_i16m2(__VA_ARGS__) -#define vluxseg4ei32_v_i16m2(...) __riscv_vluxseg4ei32_v_i16m2(__VA_ARGS__) -#define vluxseg2ei32_v_i16m4(...) __riscv_vluxseg2ei32_v_i16m4(__VA_ARGS__) -#define vluxseg2ei64_v_i16mf4(...) __riscv_vluxseg2ei64_v_i16mf4(__VA_ARGS__) -#define vluxseg3ei64_v_i16mf4(...) __riscv_vluxseg3ei64_v_i16mf4(__VA_ARGS__) -#define vluxseg4ei64_v_i16mf4(...) __riscv_vluxseg4ei64_v_i16mf4(__VA_ARGS__) -#define vluxseg5ei64_v_i16mf4(...) __riscv_vluxseg5ei64_v_i16mf4(__VA_ARGS__) -#define vluxseg6ei64_v_i16mf4(...) __riscv_vluxseg6ei64_v_i16mf4(__VA_ARGS__) -#define vluxseg7ei64_v_i16mf4(...) __riscv_vluxseg7ei64_v_i16mf4(__VA_ARGS__) -#define vluxseg8ei64_v_i16mf4(...) __riscv_vluxseg8ei64_v_i16mf4(__VA_ARGS__) -#define vluxseg2ei64_v_i16mf2(...) __riscv_vluxseg2ei64_v_i16mf2(__VA_ARGS__) -#define vluxseg3ei64_v_i16mf2(...) __riscv_vluxseg3ei64_v_i16mf2(__VA_ARGS__) -#define vluxseg4ei64_v_i16mf2(...) __riscv_vluxseg4ei64_v_i16mf2(__VA_ARGS__) -#define vluxseg5ei64_v_i16mf2(...) __riscv_vluxseg5ei64_v_i16mf2(__VA_ARGS__) -#define vluxseg6ei64_v_i16mf2(...) __riscv_vluxseg6ei64_v_i16mf2(__VA_ARGS__) -#define vluxseg7ei64_v_i16mf2(...) __riscv_vluxseg7ei64_v_i16mf2(__VA_ARGS__) -#define vluxseg8ei64_v_i16mf2(...) __riscv_vluxseg8ei64_v_i16mf2(__VA_ARGS__) -#define vluxseg2ei64_v_i16m1(...) __riscv_vluxseg2ei64_v_i16m1(__VA_ARGS__) -#define vluxseg3ei64_v_i16m1(...) __riscv_vluxseg3ei64_v_i16m1(__VA_ARGS__) -#define vluxseg4ei64_v_i16m1(...) __riscv_vluxseg4ei64_v_i16m1(__VA_ARGS__) -#define vluxseg5ei64_v_i16m1(...) __riscv_vluxseg5ei64_v_i16m1(__VA_ARGS__) -#define vluxseg6ei64_v_i16m1(...) __riscv_vluxseg6ei64_v_i16m1(__VA_ARGS__) -#define vluxseg7ei64_v_i16m1(...) __riscv_vluxseg7ei64_v_i16m1(__VA_ARGS__) -#define vluxseg8ei64_v_i16m1(...) __riscv_vluxseg8ei64_v_i16m1(__VA_ARGS__) -#define vluxseg2ei64_v_i16m2(...) __riscv_vluxseg2ei64_v_i16m2(__VA_ARGS__) -#define vluxseg3ei64_v_i16m2(...) __riscv_vluxseg3ei64_v_i16m2(__VA_ARGS__) -#define vluxseg4ei64_v_i16m2(...) __riscv_vluxseg4ei64_v_i16m2(__VA_ARGS__) -#define vluxseg2ei8_v_i32mf2(...) __riscv_vluxseg2ei8_v_i32mf2(__VA_ARGS__) -#define vluxseg3ei8_v_i32mf2(...) __riscv_vluxseg3ei8_v_i32mf2(__VA_ARGS__) -#define vluxseg4ei8_v_i32mf2(...) __riscv_vluxseg4ei8_v_i32mf2(__VA_ARGS__) -#define vluxseg5ei8_v_i32mf2(...) __riscv_vluxseg5ei8_v_i32mf2(__VA_ARGS__) -#define vluxseg6ei8_v_i32mf2(...) __riscv_vluxseg6ei8_v_i32mf2(__VA_ARGS__) -#define vluxseg7ei8_v_i32mf2(...) __riscv_vluxseg7ei8_v_i32mf2(__VA_ARGS__) -#define vluxseg8ei8_v_i32mf2(...) __riscv_vluxseg8ei8_v_i32mf2(__VA_ARGS__) -#define vluxseg2ei8_v_i32m1(...) __riscv_vluxseg2ei8_v_i32m1(__VA_ARGS__) -#define vluxseg3ei8_v_i32m1(...) __riscv_vluxseg3ei8_v_i32m1(__VA_ARGS__) -#define vluxseg4ei8_v_i32m1(...) __riscv_vluxseg4ei8_v_i32m1(__VA_ARGS__) -#define vluxseg5ei8_v_i32m1(...) __riscv_vluxseg5ei8_v_i32m1(__VA_ARGS__) -#define vluxseg6ei8_v_i32m1(...) __riscv_vluxseg6ei8_v_i32m1(__VA_ARGS__) -#define vluxseg7ei8_v_i32m1(...) __riscv_vluxseg7ei8_v_i32m1(__VA_ARGS__) -#define vluxseg8ei8_v_i32m1(...) __riscv_vluxseg8ei8_v_i32m1(__VA_ARGS__) -#define vluxseg2ei8_v_i32m2(...) __riscv_vluxseg2ei8_v_i32m2(__VA_ARGS__) -#define vluxseg3ei8_v_i32m2(...) __riscv_vluxseg3ei8_v_i32m2(__VA_ARGS__) -#define vluxseg4ei8_v_i32m2(...) __riscv_vluxseg4ei8_v_i32m2(__VA_ARGS__) -#define vluxseg2ei8_v_i32m4(...) __riscv_vluxseg2ei8_v_i32m4(__VA_ARGS__) -#define vluxseg2ei16_v_i32mf2(...) __riscv_vluxseg2ei16_v_i32mf2(__VA_ARGS__) -#define vluxseg3ei16_v_i32mf2(...) __riscv_vluxseg3ei16_v_i32mf2(__VA_ARGS__) -#define vluxseg4ei16_v_i32mf2(...) __riscv_vluxseg4ei16_v_i32mf2(__VA_ARGS__) -#define vluxseg5ei16_v_i32mf2(...) __riscv_vluxseg5ei16_v_i32mf2(__VA_ARGS__) -#define vluxseg6ei16_v_i32mf2(...) __riscv_vluxseg6ei16_v_i32mf2(__VA_ARGS__) -#define vluxseg7ei16_v_i32mf2(...) __riscv_vluxseg7ei16_v_i32mf2(__VA_ARGS__) -#define vluxseg8ei16_v_i32mf2(...) __riscv_vluxseg8ei16_v_i32mf2(__VA_ARGS__) -#define vluxseg2ei16_v_i32m1(...) __riscv_vluxseg2ei16_v_i32m1(__VA_ARGS__) -#define vluxseg3ei16_v_i32m1(...) __riscv_vluxseg3ei16_v_i32m1(__VA_ARGS__) -#define vluxseg4ei16_v_i32m1(...) __riscv_vluxseg4ei16_v_i32m1(__VA_ARGS__) -#define vluxseg5ei16_v_i32m1(...) __riscv_vluxseg5ei16_v_i32m1(__VA_ARGS__) -#define vluxseg6ei16_v_i32m1(...) __riscv_vluxseg6ei16_v_i32m1(__VA_ARGS__) -#define vluxseg7ei16_v_i32m1(...) __riscv_vluxseg7ei16_v_i32m1(__VA_ARGS__) -#define vluxseg8ei16_v_i32m1(...) __riscv_vluxseg8ei16_v_i32m1(__VA_ARGS__) -#define vluxseg2ei16_v_i32m2(...) __riscv_vluxseg2ei16_v_i32m2(__VA_ARGS__) -#define vluxseg3ei16_v_i32m2(...) __riscv_vluxseg3ei16_v_i32m2(__VA_ARGS__) -#define vluxseg4ei16_v_i32m2(...) __riscv_vluxseg4ei16_v_i32m2(__VA_ARGS__) -#define vluxseg2ei16_v_i32m4(...) __riscv_vluxseg2ei16_v_i32m4(__VA_ARGS__) -#define vluxseg2ei32_v_i32mf2(...) __riscv_vluxseg2ei32_v_i32mf2(__VA_ARGS__) -#define vluxseg3ei32_v_i32mf2(...) __riscv_vluxseg3ei32_v_i32mf2(__VA_ARGS__) -#define vluxseg4ei32_v_i32mf2(...) __riscv_vluxseg4ei32_v_i32mf2(__VA_ARGS__) -#define vluxseg5ei32_v_i32mf2(...) __riscv_vluxseg5ei32_v_i32mf2(__VA_ARGS__) -#define vluxseg6ei32_v_i32mf2(...) __riscv_vluxseg6ei32_v_i32mf2(__VA_ARGS__) -#define vluxseg7ei32_v_i32mf2(...) __riscv_vluxseg7ei32_v_i32mf2(__VA_ARGS__) -#define vluxseg8ei32_v_i32mf2(...) __riscv_vluxseg8ei32_v_i32mf2(__VA_ARGS__) -#define vluxseg2ei32_v_i32m1(...) __riscv_vluxseg2ei32_v_i32m1(__VA_ARGS__) -#define vluxseg3ei32_v_i32m1(...) __riscv_vluxseg3ei32_v_i32m1(__VA_ARGS__) -#define vluxseg4ei32_v_i32m1(...) __riscv_vluxseg4ei32_v_i32m1(__VA_ARGS__) -#define vluxseg5ei32_v_i32m1(...) __riscv_vluxseg5ei32_v_i32m1(__VA_ARGS__) -#define vluxseg6ei32_v_i32m1(...) __riscv_vluxseg6ei32_v_i32m1(__VA_ARGS__) -#define vluxseg7ei32_v_i32m1(...) __riscv_vluxseg7ei32_v_i32m1(__VA_ARGS__) -#define vluxseg8ei32_v_i32m1(...) __riscv_vluxseg8ei32_v_i32m1(__VA_ARGS__) -#define vluxseg2ei32_v_i32m2(...) __riscv_vluxseg2ei32_v_i32m2(__VA_ARGS__) -#define vluxseg3ei32_v_i32m2(...) __riscv_vluxseg3ei32_v_i32m2(__VA_ARGS__) -#define vluxseg4ei32_v_i32m2(...) __riscv_vluxseg4ei32_v_i32m2(__VA_ARGS__) -#define vluxseg2ei32_v_i32m4(...) __riscv_vluxseg2ei32_v_i32m4(__VA_ARGS__) -#define vluxseg2ei64_v_i32mf2(...) __riscv_vluxseg2ei64_v_i32mf2(__VA_ARGS__) -#define vluxseg3ei64_v_i32mf2(...) __riscv_vluxseg3ei64_v_i32mf2(__VA_ARGS__) -#define vluxseg4ei64_v_i32mf2(...) __riscv_vluxseg4ei64_v_i32mf2(__VA_ARGS__) -#define vluxseg5ei64_v_i32mf2(...) __riscv_vluxseg5ei64_v_i32mf2(__VA_ARGS__) -#define vluxseg6ei64_v_i32mf2(...) __riscv_vluxseg6ei64_v_i32mf2(__VA_ARGS__) -#define vluxseg7ei64_v_i32mf2(...) __riscv_vluxseg7ei64_v_i32mf2(__VA_ARGS__) -#define vluxseg8ei64_v_i32mf2(...) __riscv_vluxseg8ei64_v_i32mf2(__VA_ARGS__) -#define vluxseg2ei64_v_i32m1(...) __riscv_vluxseg2ei64_v_i32m1(__VA_ARGS__) -#define vluxseg3ei64_v_i32m1(...) __riscv_vluxseg3ei64_v_i32m1(__VA_ARGS__) -#define vluxseg4ei64_v_i32m1(...) __riscv_vluxseg4ei64_v_i32m1(__VA_ARGS__) -#define vluxseg5ei64_v_i32m1(...) __riscv_vluxseg5ei64_v_i32m1(__VA_ARGS__) -#define vluxseg6ei64_v_i32m1(...) __riscv_vluxseg6ei64_v_i32m1(__VA_ARGS__) -#define vluxseg7ei64_v_i32m1(...) __riscv_vluxseg7ei64_v_i32m1(__VA_ARGS__) -#define vluxseg8ei64_v_i32m1(...) __riscv_vluxseg8ei64_v_i32m1(__VA_ARGS__) -#define vluxseg2ei64_v_i32m2(...) __riscv_vluxseg2ei64_v_i32m2(__VA_ARGS__) -#define vluxseg3ei64_v_i32m2(...) __riscv_vluxseg3ei64_v_i32m2(__VA_ARGS__) -#define vluxseg4ei64_v_i32m2(...) __riscv_vluxseg4ei64_v_i32m2(__VA_ARGS__) -#define vluxseg2ei64_v_i32m4(...) __riscv_vluxseg2ei64_v_i32m4(__VA_ARGS__) -#define vluxseg2ei8_v_i64m1(...) __riscv_vluxseg2ei8_v_i64m1(__VA_ARGS__) -#define vluxseg3ei8_v_i64m1(...) __riscv_vluxseg3ei8_v_i64m1(__VA_ARGS__) -#define vluxseg4ei8_v_i64m1(...) __riscv_vluxseg4ei8_v_i64m1(__VA_ARGS__) -#define vluxseg5ei8_v_i64m1(...) __riscv_vluxseg5ei8_v_i64m1(__VA_ARGS__) -#define vluxseg6ei8_v_i64m1(...) __riscv_vluxseg6ei8_v_i64m1(__VA_ARGS__) -#define vluxseg7ei8_v_i64m1(...) __riscv_vluxseg7ei8_v_i64m1(__VA_ARGS__) -#define vluxseg8ei8_v_i64m1(...) __riscv_vluxseg8ei8_v_i64m1(__VA_ARGS__) -#define vluxseg2ei8_v_i64m2(...) __riscv_vluxseg2ei8_v_i64m2(__VA_ARGS__) -#define vluxseg3ei8_v_i64m2(...) __riscv_vluxseg3ei8_v_i64m2(__VA_ARGS__) -#define vluxseg4ei8_v_i64m2(...) __riscv_vluxseg4ei8_v_i64m2(__VA_ARGS__) -#define vluxseg2ei8_v_i64m4(...) __riscv_vluxseg2ei8_v_i64m4(__VA_ARGS__) -#define vluxseg2ei16_v_i64m1(...) __riscv_vluxseg2ei16_v_i64m1(__VA_ARGS__) -#define vluxseg3ei16_v_i64m1(...) __riscv_vluxseg3ei16_v_i64m1(__VA_ARGS__) -#define vluxseg4ei16_v_i64m1(...) __riscv_vluxseg4ei16_v_i64m1(__VA_ARGS__) -#define vluxseg5ei16_v_i64m1(...) __riscv_vluxseg5ei16_v_i64m1(__VA_ARGS__) -#define vluxseg6ei16_v_i64m1(...) __riscv_vluxseg6ei16_v_i64m1(__VA_ARGS__) -#define vluxseg7ei16_v_i64m1(...) __riscv_vluxseg7ei16_v_i64m1(__VA_ARGS__) -#define vluxseg8ei16_v_i64m1(...) __riscv_vluxseg8ei16_v_i64m1(__VA_ARGS__) -#define vluxseg2ei16_v_i64m2(...) __riscv_vluxseg2ei16_v_i64m2(__VA_ARGS__) -#define vluxseg3ei16_v_i64m2(...) __riscv_vluxseg3ei16_v_i64m2(__VA_ARGS__) -#define vluxseg4ei16_v_i64m2(...) __riscv_vluxseg4ei16_v_i64m2(__VA_ARGS__) -#define vluxseg2ei16_v_i64m4(...) __riscv_vluxseg2ei16_v_i64m4(__VA_ARGS__) -#define vluxseg2ei32_v_i64m1(...) __riscv_vluxseg2ei32_v_i64m1(__VA_ARGS__) -#define vluxseg3ei32_v_i64m1(...) __riscv_vluxseg3ei32_v_i64m1(__VA_ARGS__) -#define vluxseg4ei32_v_i64m1(...) __riscv_vluxseg4ei32_v_i64m1(__VA_ARGS__) -#define vluxseg5ei32_v_i64m1(...) __riscv_vluxseg5ei32_v_i64m1(__VA_ARGS__) -#define vluxseg6ei32_v_i64m1(...) __riscv_vluxseg6ei32_v_i64m1(__VA_ARGS__) -#define vluxseg7ei32_v_i64m1(...) __riscv_vluxseg7ei32_v_i64m1(__VA_ARGS__) -#define vluxseg8ei32_v_i64m1(...) __riscv_vluxseg8ei32_v_i64m1(__VA_ARGS__) -#define vluxseg2ei32_v_i64m2(...) __riscv_vluxseg2ei32_v_i64m2(__VA_ARGS__) -#define vluxseg3ei32_v_i64m2(...) __riscv_vluxseg3ei32_v_i64m2(__VA_ARGS__) -#define vluxseg4ei32_v_i64m2(...) __riscv_vluxseg4ei32_v_i64m2(__VA_ARGS__) -#define vluxseg2ei32_v_i64m4(...) __riscv_vluxseg2ei32_v_i64m4(__VA_ARGS__) -#define vluxseg2ei64_v_i64m1(...) __riscv_vluxseg2ei64_v_i64m1(__VA_ARGS__) -#define vluxseg3ei64_v_i64m1(...) __riscv_vluxseg3ei64_v_i64m1(__VA_ARGS__) -#define vluxseg4ei64_v_i64m1(...) __riscv_vluxseg4ei64_v_i64m1(__VA_ARGS__) -#define vluxseg5ei64_v_i64m1(...) __riscv_vluxseg5ei64_v_i64m1(__VA_ARGS__) -#define vluxseg6ei64_v_i64m1(...) __riscv_vluxseg6ei64_v_i64m1(__VA_ARGS__) -#define vluxseg7ei64_v_i64m1(...) __riscv_vluxseg7ei64_v_i64m1(__VA_ARGS__) -#define vluxseg8ei64_v_i64m1(...) __riscv_vluxseg8ei64_v_i64m1(__VA_ARGS__) -#define vluxseg2ei64_v_i64m2(...) __riscv_vluxseg2ei64_v_i64m2(__VA_ARGS__) -#define vluxseg3ei64_v_i64m2(...) __riscv_vluxseg3ei64_v_i64m2(__VA_ARGS__) -#define vluxseg4ei64_v_i64m2(...) __riscv_vluxseg4ei64_v_i64m2(__VA_ARGS__) -#define vluxseg2ei64_v_i64m4(...) __riscv_vluxseg2ei64_v_i64m4(__VA_ARGS__) -#define vloxseg2ei8_v_u8mf8(...) __riscv_vloxseg2ei8_v_u8mf8(__VA_ARGS__) -#define vloxseg3ei8_v_u8mf8(...) __riscv_vloxseg3ei8_v_u8mf8(__VA_ARGS__) -#define vloxseg4ei8_v_u8mf8(...) __riscv_vloxseg4ei8_v_u8mf8(__VA_ARGS__) -#define vloxseg5ei8_v_u8mf8(...) __riscv_vloxseg5ei8_v_u8mf8(__VA_ARGS__) -#define vloxseg6ei8_v_u8mf8(...) __riscv_vloxseg6ei8_v_u8mf8(__VA_ARGS__) -#define vloxseg7ei8_v_u8mf8(...) __riscv_vloxseg7ei8_v_u8mf8(__VA_ARGS__) -#define vloxseg8ei8_v_u8mf8(...) __riscv_vloxseg8ei8_v_u8mf8(__VA_ARGS__) -#define vloxseg2ei8_v_u8mf4(...) __riscv_vloxseg2ei8_v_u8mf4(__VA_ARGS__) -#define vloxseg3ei8_v_u8mf4(...) __riscv_vloxseg3ei8_v_u8mf4(__VA_ARGS__) -#define vloxseg4ei8_v_u8mf4(...) __riscv_vloxseg4ei8_v_u8mf4(__VA_ARGS__) -#define vloxseg5ei8_v_u8mf4(...) __riscv_vloxseg5ei8_v_u8mf4(__VA_ARGS__) -#define vloxseg6ei8_v_u8mf4(...) __riscv_vloxseg6ei8_v_u8mf4(__VA_ARGS__) -#define vloxseg7ei8_v_u8mf4(...) __riscv_vloxseg7ei8_v_u8mf4(__VA_ARGS__) -#define vloxseg8ei8_v_u8mf4(...) __riscv_vloxseg8ei8_v_u8mf4(__VA_ARGS__) -#define vloxseg2ei8_v_u8mf2(...) __riscv_vloxseg2ei8_v_u8mf2(__VA_ARGS__) -#define vloxseg3ei8_v_u8mf2(...) __riscv_vloxseg3ei8_v_u8mf2(__VA_ARGS__) -#define vloxseg4ei8_v_u8mf2(...) __riscv_vloxseg4ei8_v_u8mf2(__VA_ARGS__) -#define vloxseg5ei8_v_u8mf2(...) __riscv_vloxseg5ei8_v_u8mf2(__VA_ARGS__) -#define vloxseg6ei8_v_u8mf2(...) __riscv_vloxseg6ei8_v_u8mf2(__VA_ARGS__) -#define vloxseg7ei8_v_u8mf2(...) __riscv_vloxseg7ei8_v_u8mf2(__VA_ARGS__) -#define vloxseg8ei8_v_u8mf2(...) __riscv_vloxseg8ei8_v_u8mf2(__VA_ARGS__) -#define vloxseg2ei8_v_u8m1(...) __riscv_vloxseg2ei8_v_u8m1(__VA_ARGS__) -#define vloxseg3ei8_v_u8m1(...) __riscv_vloxseg3ei8_v_u8m1(__VA_ARGS__) -#define vloxseg4ei8_v_u8m1(...) __riscv_vloxseg4ei8_v_u8m1(__VA_ARGS__) -#define vloxseg5ei8_v_u8m1(...) __riscv_vloxseg5ei8_v_u8m1(__VA_ARGS__) -#define vloxseg6ei8_v_u8m1(...) __riscv_vloxseg6ei8_v_u8m1(__VA_ARGS__) -#define vloxseg7ei8_v_u8m1(...) __riscv_vloxseg7ei8_v_u8m1(__VA_ARGS__) -#define vloxseg8ei8_v_u8m1(...) __riscv_vloxseg8ei8_v_u8m1(__VA_ARGS__) -#define vloxseg2ei8_v_u8m2(...) __riscv_vloxseg2ei8_v_u8m2(__VA_ARGS__) -#define vloxseg3ei8_v_u8m2(...) __riscv_vloxseg3ei8_v_u8m2(__VA_ARGS__) -#define vloxseg4ei8_v_u8m2(...) __riscv_vloxseg4ei8_v_u8m2(__VA_ARGS__) -#define vloxseg2ei8_v_u8m4(...) __riscv_vloxseg2ei8_v_u8m4(__VA_ARGS__) -#define vloxseg2ei16_v_u8mf8(...) __riscv_vloxseg2ei16_v_u8mf8(__VA_ARGS__) -#define vloxseg3ei16_v_u8mf8(...) __riscv_vloxseg3ei16_v_u8mf8(__VA_ARGS__) -#define vloxseg4ei16_v_u8mf8(...) __riscv_vloxseg4ei16_v_u8mf8(__VA_ARGS__) -#define vloxseg5ei16_v_u8mf8(...) __riscv_vloxseg5ei16_v_u8mf8(__VA_ARGS__) -#define vloxseg6ei16_v_u8mf8(...) __riscv_vloxseg6ei16_v_u8mf8(__VA_ARGS__) -#define vloxseg7ei16_v_u8mf8(...) __riscv_vloxseg7ei16_v_u8mf8(__VA_ARGS__) -#define vloxseg8ei16_v_u8mf8(...) __riscv_vloxseg8ei16_v_u8mf8(__VA_ARGS__) -#define vloxseg2ei16_v_u8mf4(...) __riscv_vloxseg2ei16_v_u8mf4(__VA_ARGS__) -#define vloxseg3ei16_v_u8mf4(...) __riscv_vloxseg3ei16_v_u8mf4(__VA_ARGS__) -#define vloxseg4ei16_v_u8mf4(...) __riscv_vloxseg4ei16_v_u8mf4(__VA_ARGS__) -#define vloxseg5ei16_v_u8mf4(...) __riscv_vloxseg5ei16_v_u8mf4(__VA_ARGS__) -#define vloxseg6ei16_v_u8mf4(...) __riscv_vloxseg6ei16_v_u8mf4(__VA_ARGS__) -#define vloxseg7ei16_v_u8mf4(...) __riscv_vloxseg7ei16_v_u8mf4(__VA_ARGS__) -#define vloxseg8ei16_v_u8mf4(...) __riscv_vloxseg8ei16_v_u8mf4(__VA_ARGS__) -#define vloxseg2ei16_v_u8mf2(...) __riscv_vloxseg2ei16_v_u8mf2(__VA_ARGS__) -#define vloxseg3ei16_v_u8mf2(...) __riscv_vloxseg3ei16_v_u8mf2(__VA_ARGS__) -#define vloxseg4ei16_v_u8mf2(...) __riscv_vloxseg4ei16_v_u8mf2(__VA_ARGS__) -#define vloxseg5ei16_v_u8mf2(...) __riscv_vloxseg5ei16_v_u8mf2(__VA_ARGS__) -#define vloxseg6ei16_v_u8mf2(...) __riscv_vloxseg6ei16_v_u8mf2(__VA_ARGS__) -#define vloxseg7ei16_v_u8mf2(...) __riscv_vloxseg7ei16_v_u8mf2(__VA_ARGS__) -#define vloxseg8ei16_v_u8mf2(...) __riscv_vloxseg8ei16_v_u8mf2(__VA_ARGS__) -#define vloxseg2ei16_v_u8m1(...) __riscv_vloxseg2ei16_v_u8m1(__VA_ARGS__) -#define vloxseg3ei16_v_u8m1(...) __riscv_vloxseg3ei16_v_u8m1(__VA_ARGS__) -#define vloxseg4ei16_v_u8m1(...) __riscv_vloxseg4ei16_v_u8m1(__VA_ARGS__) -#define vloxseg5ei16_v_u8m1(...) __riscv_vloxseg5ei16_v_u8m1(__VA_ARGS__) -#define vloxseg6ei16_v_u8m1(...) __riscv_vloxseg6ei16_v_u8m1(__VA_ARGS__) -#define vloxseg7ei16_v_u8m1(...) __riscv_vloxseg7ei16_v_u8m1(__VA_ARGS__) -#define vloxseg8ei16_v_u8m1(...) __riscv_vloxseg8ei16_v_u8m1(__VA_ARGS__) -#define vloxseg2ei16_v_u8m2(...) __riscv_vloxseg2ei16_v_u8m2(__VA_ARGS__) -#define vloxseg3ei16_v_u8m2(...) __riscv_vloxseg3ei16_v_u8m2(__VA_ARGS__) -#define vloxseg4ei16_v_u8m2(...) __riscv_vloxseg4ei16_v_u8m2(__VA_ARGS__) -#define vloxseg2ei16_v_u8m4(...) __riscv_vloxseg2ei16_v_u8m4(__VA_ARGS__) -#define vloxseg2ei32_v_u8mf8(...) __riscv_vloxseg2ei32_v_u8mf8(__VA_ARGS__) -#define vloxseg3ei32_v_u8mf8(...) __riscv_vloxseg3ei32_v_u8mf8(__VA_ARGS__) -#define vloxseg4ei32_v_u8mf8(...) __riscv_vloxseg4ei32_v_u8mf8(__VA_ARGS__) -#define vloxseg5ei32_v_u8mf8(...) __riscv_vloxseg5ei32_v_u8mf8(__VA_ARGS__) -#define vloxseg6ei32_v_u8mf8(...) __riscv_vloxseg6ei32_v_u8mf8(__VA_ARGS__) -#define vloxseg7ei32_v_u8mf8(...) __riscv_vloxseg7ei32_v_u8mf8(__VA_ARGS__) -#define vloxseg8ei32_v_u8mf8(...) __riscv_vloxseg8ei32_v_u8mf8(__VA_ARGS__) -#define vloxseg2ei32_v_u8mf4(...) __riscv_vloxseg2ei32_v_u8mf4(__VA_ARGS__) -#define vloxseg3ei32_v_u8mf4(...) __riscv_vloxseg3ei32_v_u8mf4(__VA_ARGS__) -#define vloxseg4ei32_v_u8mf4(...) __riscv_vloxseg4ei32_v_u8mf4(__VA_ARGS__) -#define vloxseg5ei32_v_u8mf4(...) __riscv_vloxseg5ei32_v_u8mf4(__VA_ARGS__) -#define vloxseg6ei32_v_u8mf4(...) __riscv_vloxseg6ei32_v_u8mf4(__VA_ARGS__) -#define vloxseg7ei32_v_u8mf4(...) __riscv_vloxseg7ei32_v_u8mf4(__VA_ARGS__) -#define vloxseg8ei32_v_u8mf4(...) __riscv_vloxseg8ei32_v_u8mf4(__VA_ARGS__) -#define vloxseg2ei32_v_u8mf2(...) __riscv_vloxseg2ei32_v_u8mf2(__VA_ARGS__) -#define vloxseg3ei32_v_u8mf2(...) __riscv_vloxseg3ei32_v_u8mf2(__VA_ARGS__) -#define vloxseg4ei32_v_u8mf2(...) __riscv_vloxseg4ei32_v_u8mf2(__VA_ARGS__) -#define vloxseg5ei32_v_u8mf2(...) __riscv_vloxseg5ei32_v_u8mf2(__VA_ARGS__) -#define vloxseg6ei32_v_u8mf2(...) __riscv_vloxseg6ei32_v_u8mf2(__VA_ARGS__) -#define vloxseg7ei32_v_u8mf2(...) __riscv_vloxseg7ei32_v_u8mf2(__VA_ARGS__) -#define vloxseg8ei32_v_u8mf2(...) __riscv_vloxseg8ei32_v_u8mf2(__VA_ARGS__) -#define vloxseg2ei32_v_u8m1(...) __riscv_vloxseg2ei32_v_u8m1(__VA_ARGS__) -#define vloxseg3ei32_v_u8m1(...) __riscv_vloxseg3ei32_v_u8m1(__VA_ARGS__) -#define vloxseg4ei32_v_u8m1(...) __riscv_vloxseg4ei32_v_u8m1(__VA_ARGS__) -#define vloxseg5ei32_v_u8m1(...) __riscv_vloxseg5ei32_v_u8m1(__VA_ARGS__) -#define vloxseg6ei32_v_u8m1(...) __riscv_vloxseg6ei32_v_u8m1(__VA_ARGS__) -#define vloxseg7ei32_v_u8m1(...) __riscv_vloxseg7ei32_v_u8m1(__VA_ARGS__) -#define vloxseg8ei32_v_u8m1(...) __riscv_vloxseg8ei32_v_u8m1(__VA_ARGS__) -#define vloxseg2ei32_v_u8m2(...) __riscv_vloxseg2ei32_v_u8m2(__VA_ARGS__) -#define vloxseg3ei32_v_u8m2(...) __riscv_vloxseg3ei32_v_u8m2(__VA_ARGS__) -#define vloxseg4ei32_v_u8m2(...) __riscv_vloxseg4ei32_v_u8m2(__VA_ARGS__) -#define vloxseg2ei64_v_u8mf8(...) __riscv_vloxseg2ei64_v_u8mf8(__VA_ARGS__) -#define vloxseg3ei64_v_u8mf8(...) __riscv_vloxseg3ei64_v_u8mf8(__VA_ARGS__) -#define vloxseg4ei64_v_u8mf8(...) __riscv_vloxseg4ei64_v_u8mf8(__VA_ARGS__) -#define vloxseg5ei64_v_u8mf8(...) __riscv_vloxseg5ei64_v_u8mf8(__VA_ARGS__) -#define vloxseg6ei64_v_u8mf8(...) __riscv_vloxseg6ei64_v_u8mf8(__VA_ARGS__) -#define vloxseg7ei64_v_u8mf8(...) __riscv_vloxseg7ei64_v_u8mf8(__VA_ARGS__) -#define vloxseg8ei64_v_u8mf8(...) __riscv_vloxseg8ei64_v_u8mf8(__VA_ARGS__) -#define vloxseg2ei64_v_u8mf4(...) __riscv_vloxseg2ei64_v_u8mf4(__VA_ARGS__) -#define vloxseg3ei64_v_u8mf4(...) __riscv_vloxseg3ei64_v_u8mf4(__VA_ARGS__) -#define vloxseg4ei64_v_u8mf4(...) __riscv_vloxseg4ei64_v_u8mf4(__VA_ARGS__) -#define vloxseg5ei64_v_u8mf4(...) __riscv_vloxseg5ei64_v_u8mf4(__VA_ARGS__) -#define vloxseg6ei64_v_u8mf4(...) __riscv_vloxseg6ei64_v_u8mf4(__VA_ARGS__) -#define vloxseg7ei64_v_u8mf4(...) __riscv_vloxseg7ei64_v_u8mf4(__VA_ARGS__) -#define vloxseg8ei64_v_u8mf4(...) __riscv_vloxseg8ei64_v_u8mf4(__VA_ARGS__) -#define vloxseg2ei64_v_u8mf2(...) __riscv_vloxseg2ei64_v_u8mf2(__VA_ARGS__) -#define vloxseg3ei64_v_u8mf2(...) __riscv_vloxseg3ei64_v_u8mf2(__VA_ARGS__) -#define vloxseg4ei64_v_u8mf2(...) __riscv_vloxseg4ei64_v_u8mf2(__VA_ARGS__) -#define vloxseg5ei64_v_u8mf2(...) __riscv_vloxseg5ei64_v_u8mf2(__VA_ARGS__) -#define vloxseg6ei64_v_u8mf2(...) __riscv_vloxseg6ei64_v_u8mf2(__VA_ARGS__) -#define vloxseg7ei64_v_u8mf2(...) __riscv_vloxseg7ei64_v_u8mf2(__VA_ARGS__) -#define vloxseg8ei64_v_u8mf2(...) __riscv_vloxseg8ei64_v_u8mf2(__VA_ARGS__) -#define vloxseg2ei64_v_u8m1(...) __riscv_vloxseg2ei64_v_u8m1(__VA_ARGS__) -#define vloxseg3ei64_v_u8m1(...) __riscv_vloxseg3ei64_v_u8m1(__VA_ARGS__) -#define vloxseg4ei64_v_u8m1(...) __riscv_vloxseg4ei64_v_u8m1(__VA_ARGS__) -#define vloxseg5ei64_v_u8m1(...) __riscv_vloxseg5ei64_v_u8m1(__VA_ARGS__) -#define vloxseg6ei64_v_u8m1(...) __riscv_vloxseg6ei64_v_u8m1(__VA_ARGS__) -#define vloxseg7ei64_v_u8m1(...) __riscv_vloxseg7ei64_v_u8m1(__VA_ARGS__) -#define vloxseg8ei64_v_u8m1(...) __riscv_vloxseg8ei64_v_u8m1(__VA_ARGS__) -#define vloxseg2ei8_v_u16mf4(...) __riscv_vloxseg2ei8_v_u16mf4(__VA_ARGS__) -#define vloxseg3ei8_v_u16mf4(...) __riscv_vloxseg3ei8_v_u16mf4(__VA_ARGS__) -#define vloxseg4ei8_v_u16mf4(...) __riscv_vloxseg4ei8_v_u16mf4(__VA_ARGS__) -#define vloxseg5ei8_v_u16mf4(...) __riscv_vloxseg5ei8_v_u16mf4(__VA_ARGS__) -#define vloxseg6ei8_v_u16mf4(...) __riscv_vloxseg6ei8_v_u16mf4(__VA_ARGS__) -#define vloxseg7ei8_v_u16mf4(...) __riscv_vloxseg7ei8_v_u16mf4(__VA_ARGS__) -#define vloxseg8ei8_v_u16mf4(...) __riscv_vloxseg8ei8_v_u16mf4(__VA_ARGS__) -#define vloxseg2ei8_v_u16mf2(...) __riscv_vloxseg2ei8_v_u16mf2(__VA_ARGS__) -#define vloxseg3ei8_v_u16mf2(...) __riscv_vloxseg3ei8_v_u16mf2(__VA_ARGS__) -#define vloxseg4ei8_v_u16mf2(...) __riscv_vloxseg4ei8_v_u16mf2(__VA_ARGS__) -#define vloxseg5ei8_v_u16mf2(...) __riscv_vloxseg5ei8_v_u16mf2(__VA_ARGS__) -#define vloxseg6ei8_v_u16mf2(...) __riscv_vloxseg6ei8_v_u16mf2(__VA_ARGS__) -#define vloxseg7ei8_v_u16mf2(...) __riscv_vloxseg7ei8_v_u16mf2(__VA_ARGS__) -#define vloxseg8ei8_v_u16mf2(...) __riscv_vloxseg8ei8_v_u16mf2(__VA_ARGS__) -#define vloxseg2ei8_v_u16m1(...) __riscv_vloxseg2ei8_v_u16m1(__VA_ARGS__) -#define vloxseg3ei8_v_u16m1(...) __riscv_vloxseg3ei8_v_u16m1(__VA_ARGS__) -#define vloxseg4ei8_v_u16m1(...) __riscv_vloxseg4ei8_v_u16m1(__VA_ARGS__) -#define vloxseg5ei8_v_u16m1(...) __riscv_vloxseg5ei8_v_u16m1(__VA_ARGS__) -#define vloxseg6ei8_v_u16m1(...) __riscv_vloxseg6ei8_v_u16m1(__VA_ARGS__) -#define vloxseg7ei8_v_u16m1(...) __riscv_vloxseg7ei8_v_u16m1(__VA_ARGS__) -#define vloxseg8ei8_v_u16m1(...) __riscv_vloxseg8ei8_v_u16m1(__VA_ARGS__) -#define vloxseg2ei8_v_u16m2(...) __riscv_vloxseg2ei8_v_u16m2(__VA_ARGS__) -#define vloxseg3ei8_v_u16m2(...) __riscv_vloxseg3ei8_v_u16m2(__VA_ARGS__) -#define vloxseg4ei8_v_u16m2(...) __riscv_vloxseg4ei8_v_u16m2(__VA_ARGS__) -#define vloxseg2ei8_v_u16m4(...) __riscv_vloxseg2ei8_v_u16m4(__VA_ARGS__) -#define vloxseg2ei16_v_u16mf4(...) __riscv_vloxseg2ei16_v_u16mf4(__VA_ARGS__) -#define vloxseg3ei16_v_u16mf4(...) __riscv_vloxseg3ei16_v_u16mf4(__VA_ARGS__) -#define vloxseg4ei16_v_u16mf4(...) __riscv_vloxseg4ei16_v_u16mf4(__VA_ARGS__) -#define vloxseg5ei16_v_u16mf4(...) __riscv_vloxseg5ei16_v_u16mf4(__VA_ARGS__) -#define vloxseg6ei16_v_u16mf4(...) __riscv_vloxseg6ei16_v_u16mf4(__VA_ARGS__) -#define vloxseg7ei16_v_u16mf4(...) __riscv_vloxseg7ei16_v_u16mf4(__VA_ARGS__) -#define vloxseg8ei16_v_u16mf4(...) __riscv_vloxseg8ei16_v_u16mf4(__VA_ARGS__) -#define vloxseg2ei16_v_u16mf2(...) __riscv_vloxseg2ei16_v_u16mf2(__VA_ARGS__) -#define vloxseg3ei16_v_u16mf2(...) __riscv_vloxseg3ei16_v_u16mf2(__VA_ARGS__) -#define vloxseg4ei16_v_u16mf2(...) __riscv_vloxseg4ei16_v_u16mf2(__VA_ARGS__) -#define vloxseg5ei16_v_u16mf2(...) __riscv_vloxseg5ei16_v_u16mf2(__VA_ARGS__) -#define vloxseg6ei16_v_u16mf2(...) __riscv_vloxseg6ei16_v_u16mf2(__VA_ARGS__) -#define vloxseg7ei16_v_u16mf2(...) __riscv_vloxseg7ei16_v_u16mf2(__VA_ARGS__) -#define vloxseg8ei16_v_u16mf2(...) __riscv_vloxseg8ei16_v_u16mf2(__VA_ARGS__) -#define vloxseg2ei16_v_u16m1(...) __riscv_vloxseg2ei16_v_u16m1(__VA_ARGS__) -#define vloxseg3ei16_v_u16m1(...) __riscv_vloxseg3ei16_v_u16m1(__VA_ARGS__) -#define vloxseg4ei16_v_u16m1(...) __riscv_vloxseg4ei16_v_u16m1(__VA_ARGS__) -#define vloxseg5ei16_v_u16m1(...) __riscv_vloxseg5ei16_v_u16m1(__VA_ARGS__) -#define vloxseg6ei16_v_u16m1(...) __riscv_vloxseg6ei16_v_u16m1(__VA_ARGS__) -#define vloxseg7ei16_v_u16m1(...) __riscv_vloxseg7ei16_v_u16m1(__VA_ARGS__) -#define vloxseg8ei16_v_u16m1(...) __riscv_vloxseg8ei16_v_u16m1(__VA_ARGS__) -#define vloxseg2ei16_v_u16m2(...) __riscv_vloxseg2ei16_v_u16m2(__VA_ARGS__) -#define vloxseg3ei16_v_u16m2(...) __riscv_vloxseg3ei16_v_u16m2(__VA_ARGS__) -#define vloxseg4ei16_v_u16m2(...) __riscv_vloxseg4ei16_v_u16m2(__VA_ARGS__) -#define vloxseg2ei16_v_u16m4(...) __riscv_vloxseg2ei16_v_u16m4(__VA_ARGS__) -#define vloxseg2ei32_v_u16mf4(...) __riscv_vloxseg2ei32_v_u16mf4(__VA_ARGS__) -#define vloxseg3ei32_v_u16mf4(...) __riscv_vloxseg3ei32_v_u16mf4(__VA_ARGS__) -#define vloxseg4ei32_v_u16mf4(...) __riscv_vloxseg4ei32_v_u16mf4(__VA_ARGS__) -#define vloxseg5ei32_v_u16mf4(...) __riscv_vloxseg5ei32_v_u16mf4(__VA_ARGS__) -#define vloxseg6ei32_v_u16mf4(...) __riscv_vloxseg6ei32_v_u16mf4(__VA_ARGS__) -#define vloxseg7ei32_v_u16mf4(...) __riscv_vloxseg7ei32_v_u16mf4(__VA_ARGS__) -#define vloxseg8ei32_v_u16mf4(...) __riscv_vloxseg8ei32_v_u16mf4(__VA_ARGS__) -#define vloxseg2ei32_v_u16mf2(...) __riscv_vloxseg2ei32_v_u16mf2(__VA_ARGS__) -#define vloxseg3ei32_v_u16mf2(...) __riscv_vloxseg3ei32_v_u16mf2(__VA_ARGS__) -#define vloxseg4ei32_v_u16mf2(...) __riscv_vloxseg4ei32_v_u16mf2(__VA_ARGS__) -#define vloxseg5ei32_v_u16mf2(...) __riscv_vloxseg5ei32_v_u16mf2(__VA_ARGS__) -#define vloxseg6ei32_v_u16mf2(...) __riscv_vloxseg6ei32_v_u16mf2(__VA_ARGS__) -#define vloxseg7ei32_v_u16mf2(...) __riscv_vloxseg7ei32_v_u16mf2(__VA_ARGS__) -#define vloxseg8ei32_v_u16mf2(...) __riscv_vloxseg8ei32_v_u16mf2(__VA_ARGS__) -#define vloxseg2ei32_v_u16m1(...) __riscv_vloxseg2ei32_v_u16m1(__VA_ARGS__) -#define vloxseg3ei32_v_u16m1(...) __riscv_vloxseg3ei32_v_u16m1(__VA_ARGS__) -#define vloxseg4ei32_v_u16m1(...) __riscv_vloxseg4ei32_v_u16m1(__VA_ARGS__) -#define vloxseg5ei32_v_u16m1(...) __riscv_vloxseg5ei32_v_u16m1(__VA_ARGS__) -#define vloxseg6ei32_v_u16m1(...) __riscv_vloxseg6ei32_v_u16m1(__VA_ARGS__) -#define vloxseg7ei32_v_u16m1(...) __riscv_vloxseg7ei32_v_u16m1(__VA_ARGS__) -#define vloxseg8ei32_v_u16m1(...) __riscv_vloxseg8ei32_v_u16m1(__VA_ARGS__) -#define vloxseg2ei32_v_u16m2(...) __riscv_vloxseg2ei32_v_u16m2(__VA_ARGS__) -#define vloxseg3ei32_v_u16m2(...) __riscv_vloxseg3ei32_v_u16m2(__VA_ARGS__) -#define vloxseg4ei32_v_u16m2(...) __riscv_vloxseg4ei32_v_u16m2(__VA_ARGS__) -#define vloxseg2ei32_v_u16m4(...) __riscv_vloxseg2ei32_v_u16m4(__VA_ARGS__) -#define vloxseg2ei64_v_u16mf4(...) __riscv_vloxseg2ei64_v_u16mf4(__VA_ARGS__) -#define vloxseg3ei64_v_u16mf4(...) __riscv_vloxseg3ei64_v_u16mf4(__VA_ARGS__) -#define vloxseg4ei64_v_u16mf4(...) __riscv_vloxseg4ei64_v_u16mf4(__VA_ARGS__) -#define vloxseg5ei64_v_u16mf4(...) __riscv_vloxseg5ei64_v_u16mf4(__VA_ARGS__) -#define vloxseg6ei64_v_u16mf4(...) __riscv_vloxseg6ei64_v_u16mf4(__VA_ARGS__) -#define vloxseg7ei64_v_u16mf4(...) __riscv_vloxseg7ei64_v_u16mf4(__VA_ARGS__) -#define vloxseg8ei64_v_u16mf4(...) __riscv_vloxseg8ei64_v_u16mf4(__VA_ARGS__) -#define vloxseg2ei64_v_u16mf2(...) __riscv_vloxseg2ei64_v_u16mf2(__VA_ARGS__) -#define vloxseg3ei64_v_u16mf2(...) __riscv_vloxseg3ei64_v_u16mf2(__VA_ARGS__) -#define vloxseg4ei64_v_u16mf2(...) __riscv_vloxseg4ei64_v_u16mf2(__VA_ARGS__) -#define vloxseg5ei64_v_u16mf2(...) __riscv_vloxseg5ei64_v_u16mf2(__VA_ARGS__) -#define vloxseg6ei64_v_u16mf2(...) __riscv_vloxseg6ei64_v_u16mf2(__VA_ARGS__) -#define vloxseg7ei64_v_u16mf2(...) __riscv_vloxseg7ei64_v_u16mf2(__VA_ARGS__) -#define vloxseg8ei64_v_u16mf2(...) __riscv_vloxseg8ei64_v_u16mf2(__VA_ARGS__) -#define vloxseg2ei64_v_u16m1(...) __riscv_vloxseg2ei64_v_u16m1(__VA_ARGS__) -#define vloxseg3ei64_v_u16m1(...) __riscv_vloxseg3ei64_v_u16m1(__VA_ARGS__) -#define vloxseg4ei64_v_u16m1(...) __riscv_vloxseg4ei64_v_u16m1(__VA_ARGS__) -#define vloxseg5ei64_v_u16m1(...) __riscv_vloxseg5ei64_v_u16m1(__VA_ARGS__) -#define vloxseg6ei64_v_u16m1(...) __riscv_vloxseg6ei64_v_u16m1(__VA_ARGS__) -#define vloxseg7ei64_v_u16m1(...) __riscv_vloxseg7ei64_v_u16m1(__VA_ARGS__) -#define vloxseg8ei64_v_u16m1(...) __riscv_vloxseg8ei64_v_u16m1(__VA_ARGS__) -#define vloxseg2ei64_v_u16m2(...) __riscv_vloxseg2ei64_v_u16m2(__VA_ARGS__) -#define vloxseg3ei64_v_u16m2(...) __riscv_vloxseg3ei64_v_u16m2(__VA_ARGS__) -#define vloxseg4ei64_v_u16m2(...) __riscv_vloxseg4ei64_v_u16m2(__VA_ARGS__) -#define vloxseg2ei8_v_u32mf2(...) __riscv_vloxseg2ei8_v_u32mf2(__VA_ARGS__) -#define vloxseg3ei8_v_u32mf2(...) __riscv_vloxseg3ei8_v_u32mf2(__VA_ARGS__) -#define vloxseg4ei8_v_u32mf2(...) __riscv_vloxseg4ei8_v_u32mf2(__VA_ARGS__) -#define vloxseg5ei8_v_u32mf2(...) __riscv_vloxseg5ei8_v_u32mf2(__VA_ARGS__) -#define vloxseg6ei8_v_u32mf2(...) __riscv_vloxseg6ei8_v_u32mf2(__VA_ARGS__) -#define vloxseg7ei8_v_u32mf2(...) __riscv_vloxseg7ei8_v_u32mf2(__VA_ARGS__) -#define vloxseg8ei8_v_u32mf2(...) __riscv_vloxseg8ei8_v_u32mf2(__VA_ARGS__) -#define vloxseg2ei8_v_u32m1(...) __riscv_vloxseg2ei8_v_u32m1(__VA_ARGS__) -#define vloxseg3ei8_v_u32m1(...) __riscv_vloxseg3ei8_v_u32m1(__VA_ARGS__) -#define vloxseg4ei8_v_u32m1(...) __riscv_vloxseg4ei8_v_u32m1(__VA_ARGS__) -#define vloxseg5ei8_v_u32m1(...) __riscv_vloxseg5ei8_v_u32m1(__VA_ARGS__) -#define vloxseg6ei8_v_u32m1(...) __riscv_vloxseg6ei8_v_u32m1(__VA_ARGS__) -#define vloxseg7ei8_v_u32m1(...) __riscv_vloxseg7ei8_v_u32m1(__VA_ARGS__) -#define vloxseg8ei8_v_u32m1(...) __riscv_vloxseg8ei8_v_u32m1(__VA_ARGS__) -#define vloxseg2ei8_v_u32m2(...) __riscv_vloxseg2ei8_v_u32m2(__VA_ARGS__) -#define vloxseg3ei8_v_u32m2(...) __riscv_vloxseg3ei8_v_u32m2(__VA_ARGS__) -#define vloxseg4ei8_v_u32m2(...) __riscv_vloxseg4ei8_v_u32m2(__VA_ARGS__) -#define vloxseg2ei8_v_u32m4(...) __riscv_vloxseg2ei8_v_u32m4(__VA_ARGS__) -#define vloxseg2ei16_v_u32mf2(...) __riscv_vloxseg2ei16_v_u32mf2(__VA_ARGS__) -#define vloxseg3ei16_v_u32mf2(...) __riscv_vloxseg3ei16_v_u32mf2(__VA_ARGS__) -#define vloxseg4ei16_v_u32mf2(...) __riscv_vloxseg4ei16_v_u32mf2(__VA_ARGS__) -#define vloxseg5ei16_v_u32mf2(...) __riscv_vloxseg5ei16_v_u32mf2(__VA_ARGS__) -#define vloxseg6ei16_v_u32mf2(...) __riscv_vloxseg6ei16_v_u32mf2(__VA_ARGS__) -#define vloxseg7ei16_v_u32mf2(...) __riscv_vloxseg7ei16_v_u32mf2(__VA_ARGS__) -#define vloxseg8ei16_v_u32mf2(...) __riscv_vloxseg8ei16_v_u32mf2(__VA_ARGS__) -#define vloxseg2ei16_v_u32m1(...) __riscv_vloxseg2ei16_v_u32m1(__VA_ARGS__) -#define vloxseg3ei16_v_u32m1(...) __riscv_vloxseg3ei16_v_u32m1(__VA_ARGS__) -#define vloxseg4ei16_v_u32m1(...) __riscv_vloxseg4ei16_v_u32m1(__VA_ARGS__) -#define vloxseg5ei16_v_u32m1(...) __riscv_vloxseg5ei16_v_u32m1(__VA_ARGS__) -#define vloxseg6ei16_v_u32m1(...) __riscv_vloxseg6ei16_v_u32m1(__VA_ARGS__) -#define vloxseg7ei16_v_u32m1(...) __riscv_vloxseg7ei16_v_u32m1(__VA_ARGS__) -#define vloxseg8ei16_v_u32m1(...) __riscv_vloxseg8ei16_v_u32m1(__VA_ARGS__) -#define vloxseg2ei16_v_u32m2(...) __riscv_vloxseg2ei16_v_u32m2(__VA_ARGS__) -#define vloxseg3ei16_v_u32m2(...) __riscv_vloxseg3ei16_v_u32m2(__VA_ARGS__) -#define vloxseg4ei16_v_u32m2(...) __riscv_vloxseg4ei16_v_u32m2(__VA_ARGS__) -#define vloxseg2ei16_v_u32m4(...) __riscv_vloxseg2ei16_v_u32m4(__VA_ARGS__) -#define vloxseg2ei32_v_u32mf2(...) __riscv_vloxseg2ei32_v_u32mf2(__VA_ARGS__) -#define vloxseg3ei32_v_u32mf2(...) __riscv_vloxseg3ei32_v_u32mf2(__VA_ARGS__) -#define vloxseg4ei32_v_u32mf2(...) __riscv_vloxseg4ei32_v_u32mf2(__VA_ARGS__) -#define vloxseg5ei32_v_u32mf2(...) __riscv_vloxseg5ei32_v_u32mf2(__VA_ARGS__) -#define vloxseg6ei32_v_u32mf2(...) __riscv_vloxseg6ei32_v_u32mf2(__VA_ARGS__) -#define vloxseg7ei32_v_u32mf2(...) __riscv_vloxseg7ei32_v_u32mf2(__VA_ARGS__) -#define vloxseg8ei32_v_u32mf2(...) __riscv_vloxseg8ei32_v_u32mf2(__VA_ARGS__) -#define vloxseg2ei32_v_u32m1(...) __riscv_vloxseg2ei32_v_u32m1(__VA_ARGS__) -#define vloxseg3ei32_v_u32m1(...) __riscv_vloxseg3ei32_v_u32m1(__VA_ARGS__) -#define vloxseg4ei32_v_u32m1(...) __riscv_vloxseg4ei32_v_u32m1(__VA_ARGS__) -#define vloxseg5ei32_v_u32m1(...) __riscv_vloxseg5ei32_v_u32m1(__VA_ARGS__) -#define vloxseg6ei32_v_u32m1(...) __riscv_vloxseg6ei32_v_u32m1(__VA_ARGS__) -#define vloxseg7ei32_v_u32m1(...) __riscv_vloxseg7ei32_v_u32m1(__VA_ARGS__) -#define vloxseg8ei32_v_u32m1(...) __riscv_vloxseg8ei32_v_u32m1(__VA_ARGS__) -#define vloxseg2ei32_v_u32m2(...) __riscv_vloxseg2ei32_v_u32m2(__VA_ARGS__) -#define vloxseg3ei32_v_u32m2(...) __riscv_vloxseg3ei32_v_u32m2(__VA_ARGS__) -#define vloxseg4ei32_v_u32m2(...) __riscv_vloxseg4ei32_v_u32m2(__VA_ARGS__) -#define vloxseg2ei32_v_u32m4(...) __riscv_vloxseg2ei32_v_u32m4(__VA_ARGS__) -#define vloxseg2ei64_v_u32mf2(...) __riscv_vloxseg2ei64_v_u32mf2(__VA_ARGS__) -#define vloxseg3ei64_v_u32mf2(...) __riscv_vloxseg3ei64_v_u32mf2(__VA_ARGS__) -#define vloxseg4ei64_v_u32mf2(...) __riscv_vloxseg4ei64_v_u32mf2(__VA_ARGS__) -#define vloxseg5ei64_v_u32mf2(...) __riscv_vloxseg5ei64_v_u32mf2(__VA_ARGS__) -#define vloxseg6ei64_v_u32mf2(...) __riscv_vloxseg6ei64_v_u32mf2(__VA_ARGS__) -#define vloxseg7ei64_v_u32mf2(...) __riscv_vloxseg7ei64_v_u32mf2(__VA_ARGS__) -#define vloxseg8ei64_v_u32mf2(...) __riscv_vloxseg8ei64_v_u32mf2(__VA_ARGS__) -#define vloxseg2ei64_v_u32m1(...) __riscv_vloxseg2ei64_v_u32m1(__VA_ARGS__) -#define vloxseg3ei64_v_u32m1(...) __riscv_vloxseg3ei64_v_u32m1(__VA_ARGS__) -#define vloxseg4ei64_v_u32m1(...) __riscv_vloxseg4ei64_v_u32m1(__VA_ARGS__) -#define vloxseg5ei64_v_u32m1(...) __riscv_vloxseg5ei64_v_u32m1(__VA_ARGS__) -#define vloxseg6ei64_v_u32m1(...) __riscv_vloxseg6ei64_v_u32m1(__VA_ARGS__) -#define vloxseg7ei64_v_u32m1(...) __riscv_vloxseg7ei64_v_u32m1(__VA_ARGS__) -#define vloxseg8ei64_v_u32m1(...) __riscv_vloxseg8ei64_v_u32m1(__VA_ARGS__) -#define vloxseg2ei64_v_u32m2(...) __riscv_vloxseg2ei64_v_u32m2(__VA_ARGS__) -#define vloxseg3ei64_v_u32m2(...) __riscv_vloxseg3ei64_v_u32m2(__VA_ARGS__) -#define vloxseg4ei64_v_u32m2(...) __riscv_vloxseg4ei64_v_u32m2(__VA_ARGS__) -#define vloxseg2ei64_v_u32m4(...) __riscv_vloxseg2ei64_v_u32m4(__VA_ARGS__) -#define vloxseg2ei8_v_u64m1(...) __riscv_vloxseg2ei8_v_u64m1(__VA_ARGS__) -#define vloxseg3ei8_v_u64m1(...) __riscv_vloxseg3ei8_v_u64m1(__VA_ARGS__) -#define vloxseg4ei8_v_u64m1(...) __riscv_vloxseg4ei8_v_u64m1(__VA_ARGS__) -#define vloxseg5ei8_v_u64m1(...) __riscv_vloxseg5ei8_v_u64m1(__VA_ARGS__) -#define vloxseg6ei8_v_u64m1(...) __riscv_vloxseg6ei8_v_u64m1(__VA_ARGS__) -#define vloxseg7ei8_v_u64m1(...) __riscv_vloxseg7ei8_v_u64m1(__VA_ARGS__) -#define vloxseg8ei8_v_u64m1(...) __riscv_vloxseg8ei8_v_u64m1(__VA_ARGS__) -#define vloxseg2ei8_v_u64m2(...) __riscv_vloxseg2ei8_v_u64m2(__VA_ARGS__) -#define vloxseg3ei8_v_u64m2(...) __riscv_vloxseg3ei8_v_u64m2(__VA_ARGS__) -#define vloxseg4ei8_v_u64m2(...) __riscv_vloxseg4ei8_v_u64m2(__VA_ARGS__) -#define vloxseg2ei8_v_u64m4(...) __riscv_vloxseg2ei8_v_u64m4(__VA_ARGS__) -#define vloxseg2ei16_v_u64m1(...) __riscv_vloxseg2ei16_v_u64m1(__VA_ARGS__) -#define vloxseg3ei16_v_u64m1(...) __riscv_vloxseg3ei16_v_u64m1(__VA_ARGS__) -#define vloxseg4ei16_v_u64m1(...) __riscv_vloxseg4ei16_v_u64m1(__VA_ARGS__) -#define vloxseg5ei16_v_u64m1(...) __riscv_vloxseg5ei16_v_u64m1(__VA_ARGS__) -#define vloxseg6ei16_v_u64m1(...) __riscv_vloxseg6ei16_v_u64m1(__VA_ARGS__) -#define vloxseg7ei16_v_u64m1(...) __riscv_vloxseg7ei16_v_u64m1(__VA_ARGS__) -#define vloxseg8ei16_v_u64m1(...) __riscv_vloxseg8ei16_v_u64m1(__VA_ARGS__) -#define vloxseg2ei16_v_u64m2(...) __riscv_vloxseg2ei16_v_u64m2(__VA_ARGS__) -#define vloxseg3ei16_v_u64m2(...) __riscv_vloxseg3ei16_v_u64m2(__VA_ARGS__) -#define vloxseg4ei16_v_u64m2(...) __riscv_vloxseg4ei16_v_u64m2(__VA_ARGS__) -#define vloxseg2ei16_v_u64m4(...) __riscv_vloxseg2ei16_v_u64m4(__VA_ARGS__) -#define vloxseg2ei32_v_u64m1(...) __riscv_vloxseg2ei32_v_u64m1(__VA_ARGS__) -#define vloxseg3ei32_v_u64m1(...) __riscv_vloxseg3ei32_v_u64m1(__VA_ARGS__) -#define vloxseg4ei32_v_u64m1(...) __riscv_vloxseg4ei32_v_u64m1(__VA_ARGS__) -#define vloxseg5ei32_v_u64m1(...) __riscv_vloxseg5ei32_v_u64m1(__VA_ARGS__) -#define vloxseg6ei32_v_u64m1(...) __riscv_vloxseg6ei32_v_u64m1(__VA_ARGS__) -#define vloxseg7ei32_v_u64m1(...) __riscv_vloxseg7ei32_v_u64m1(__VA_ARGS__) -#define vloxseg8ei32_v_u64m1(...) __riscv_vloxseg8ei32_v_u64m1(__VA_ARGS__) -#define vloxseg2ei32_v_u64m2(...) __riscv_vloxseg2ei32_v_u64m2(__VA_ARGS__) -#define vloxseg3ei32_v_u64m2(...) __riscv_vloxseg3ei32_v_u64m2(__VA_ARGS__) -#define vloxseg4ei32_v_u64m2(...) __riscv_vloxseg4ei32_v_u64m2(__VA_ARGS__) -#define vloxseg2ei32_v_u64m4(...) __riscv_vloxseg2ei32_v_u64m4(__VA_ARGS__) -#define vloxseg2ei64_v_u64m1(...) __riscv_vloxseg2ei64_v_u64m1(__VA_ARGS__) -#define vloxseg3ei64_v_u64m1(...) __riscv_vloxseg3ei64_v_u64m1(__VA_ARGS__) -#define vloxseg4ei64_v_u64m1(...) __riscv_vloxseg4ei64_v_u64m1(__VA_ARGS__) -#define vloxseg5ei64_v_u64m1(...) __riscv_vloxseg5ei64_v_u64m1(__VA_ARGS__) -#define vloxseg6ei64_v_u64m1(...) __riscv_vloxseg6ei64_v_u64m1(__VA_ARGS__) -#define vloxseg7ei64_v_u64m1(...) __riscv_vloxseg7ei64_v_u64m1(__VA_ARGS__) -#define vloxseg8ei64_v_u64m1(...) __riscv_vloxseg8ei64_v_u64m1(__VA_ARGS__) -#define vloxseg2ei64_v_u64m2(...) __riscv_vloxseg2ei64_v_u64m2(__VA_ARGS__) -#define vloxseg3ei64_v_u64m2(...) __riscv_vloxseg3ei64_v_u64m2(__VA_ARGS__) -#define vloxseg4ei64_v_u64m2(...) __riscv_vloxseg4ei64_v_u64m2(__VA_ARGS__) -#define vloxseg2ei64_v_u64m4(...) __riscv_vloxseg2ei64_v_u64m4(__VA_ARGS__) -#define vluxseg2ei8_v_u8mf8(...) __riscv_vluxseg2ei8_v_u8mf8(__VA_ARGS__) -#define vluxseg3ei8_v_u8mf8(...) __riscv_vluxseg3ei8_v_u8mf8(__VA_ARGS__) -#define vluxseg4ei8_v_u8mf8(...) __riscv_vluxseg4ei8_v_u8mf8(__VA_ARGS__) -#define vluxseg5ei8_v_u8mf8(...) __riscv_vluxseg5ei8_v_u8mf8(__VA_ARGS__) -#define vluxseg6ei8_v_u8mf8(...) __riscv_vluxseg6ei8_v_u8mf8(__VA_ARGS__) -#define vluxseg7ei8_v_u8mf8(...) __riscv_vluxseg7ei8_v_u8mf8(__VA_ARGS__) -#define vluxseg8ei8_v_u8mf8(...) __riscv_vluxseg8ei8_v_u8mf8(__VA_ARGS__) -#define vluxseg2ei8_v_u8mf4(...) __riscv_vluxseg2ei8_v_u8mf4(__VA_ARGS__) -#define vluxseg3ei8_v_u8mf4(...) __riscv_vluxseg3ei8_v_u8mf4(__VA_ARGS__) -#define vluxseg4ei8_v_u8mf4(...) __riscv_vluxseg4ei8_v_u8mf4(__VA_ARGS__) -#define vluxseg5ei8_v_u8mf4(...) __riscv_vluxseg5ei8_v_u8mf4(__VA_ARGS__) -#define vluxseg6ei8_v_u8mf4(...) __riscv_vluxseg6ei8_v_u8mf4(__VA_ARGS__) -#define vluxseg7ei8_v_u8mf4(...) __riscv_vluxseg7ei8_v_u8mf4(__VA_ARGS__) -#define vluxseg8ei8_v_u8mf4(...) __riscv_vluxseg8ei8_v_u8mf4(__VA_ARGS__) -#define vluxseg2ei8_v_u8mf2(...) __riscv_vluxseg2ei8_v_u8mf2(__VA_ARGS__) -#define vluxseg3ei8_v_u8mf2(...) __riscv_vluxseg3ei8_v_u8mf2(__VA_ARGS__) -#define vluxseg4ei8_v_u8mf2(...) __riscv_vluxseg4ei8_v_u8mf2(__VA_ARGS__) -#define vluxseg5ei8_v_u8mf2(...) __riscv_vluxseg5ei8_v_u8mf2(__VA_ARGS__) -#define vluxseg6ei8_v_u8mf2(...) __riscv_vluxseg6ei8_v_u8mf2(__VA_ARGS__) -#define vluxseg7ei8_v_u8mf2(...) __riscv_vluxseg7ei8_v_u8mf2(__VA_ARGS__) -#define vluxseg8ei8_v_u8mf2(...) __riscv_vluxseg8ei8_v_u8mf2(__VA_ARGS__) -#define vluxseg2ei8_v_u8m1(...) __riscv_vluxseg2ei8_v_u8m1(__VA_ARGS__) -#define vluxseg3ei8_v_u8m1(...) __riscv_vluxseg3ei8_v_u8m1(__VA_ARGS__) -#define vluxseg4ei8_v_u8m1(...) __riscv_vluxseg4ei8_v_u8m1(__VA_ARGS__) -#define vluxseg5ei8_v_u8m1(...) __riscv_vluxseg5ei8_v_u8m1(__VA_ARGS__) -#define vluxseg6ei8_v_u8m1(...) __riscv_vluxseg6ei8_v_u8m1(__VA_ARGS__) -#define vluxseg7ei8_v_u8m1(...) __riscv_vluxseg7ei8_v_u8m1(__VA_ARGS__) -#define vluxseg8ei8_v_u8m1(...) __riscv_vluxseg8ei8_v_u8m1(__VA_ARGS__) -#define vluxseg2ei8_v_u8m2(...) __riscv_vluxseg2ei8_v_u8m2(__VA_ARGS__) -#define vluxseg3ei8_v_u8m2(...) __riscv_vluxseg3ei8_v_u8m2(__VA_ARGS__) -#define vluxseg4ei8_v_u8m2(...) __riscv_vluxseg4ei8_v_u8m2(__VA_ARGS__) -#define vluxseg2ei8_v_u8m4(...) __riscv_vluxseg2ei8_v_u8m4(__VA_ARGS__) -#define vluxseg2ei16_v_u8mf8(...) __riscv_vluxseg2ei16_v_u8mf8(__VA_ARGS__) -#define vluxseg3ei16_v_u8mf8(...) __riscv_vluxseg3ei16_v_u8mf8(__VA_ARGS__) -#define vluxseg4ei16_v_u8mf8(...) __riscv_vluxseg4ei16_v_u8mf8(__VA_ARGS__) -#define vluxseg5ei16_v_u8mf8(...) __riscv_vluxseg5ei16_v_u8mf8(__VA_ARGS__) -#define vluxseg6ei16_v_u8mf8(...) __riscv_vluxseg6ei16_v_u8mf8(__VA_ARGS__) -#define vluxseg7ei16_v_u8mf8(...) __riscv_vluxseg7ei16_v_u8mf8(__VA_ARGS__) -#define vluxseg8ei16_v_u8mf8(...) __riscv_vluxseg8ei16_v_u8mf8(__VA_ARGS__) -#define vluxseg2ei16_v_u8mf4(...) __riscv_vluxseg2ei16_v_u8mf4(__VA_ARGS__) -#define vluxseg3ei16_v_u8mf4(...) __riscv_vluxseg3ei16_v_u8mf4(__VA_ARGS__) -#define vluxseg4ei16_v_u8mf4(...) __riscv_vluxseg4ei16_v_u8mf4(__VA_ARGS__) -#define vluxseg5ei16_v_u8mf4(...) __riscv_vluxseg5ei16_v_u8mf4(__VA_ARGS__) -#define vluxseg6ei16_v_u8mf4(...) __riscv_vluxseg6ei16_v_u8mf4(__VA_ARGS__) -#define vluxseg7ei16_v_u8mf4(...) __riscv_vluxseg7ei16_v_u8mf4(__VA_ARGS__) -#define vluxseg8ei16_v_u8mf4(...) __riscv_vluxseg8ei16_v_u8mf4(__VA_ARGS__) -#define vluxseg2ei16_v_u8mf2(...) __riscv_vluxseg2ei16_v_u8mf2(__VA_ARGS__) -#define vluxseg3ei16_v_u8mf2(...) __riscv_vluxseg3ei16_v_u8mf2(__VA_ARGS__) -#define vluxseg4ei16_v_u8mf2(...) __riscv_vluxseg4ei16_v_u8mf2(__VA_ARGS__) -#define vluxseg5ei16_v_u8mf2(...) __riscv_vluxseg5ei16_v_u8mf2(__VA_ARGS__) -#define vluxseg6ei16_v_u8mf2(...) __riscv_vluxseg6ei16_v_u8mf2(__VA_ARGS__) -#define vluxseg7ei16_v_u8mf2(...) __riscv_vluxseg7ei16_v_u8mf2(__VA_ARGS__) -#define vluxseg8ei16_v_u8mf2(...) __riscv_vluxseg8ei16_v_u8mf2(__VA_ARGS__) -#define vluxseg2ei16_v_u8m1(...) __riscv_vluxseg2ei16_v_u8m1(__VA_ARGS__) -#define vluxseg3ei16_v_u8m1(...) __riscv_vluxseg3ei16_v_u8m1(__VA_ARGS__) -#define vluxseg4ei16_v_u8m1(...) __riscv_vluxseg4ei16_v_u8m1(__VA_ARGS__) -#define vluxseg5ei16_v_u8m1(...) __riscv_vluxseg5ei16_v_u8m1(__VA_ARGS__) -#define vluxseg6ei16_v_u8m1(...) __riscv_vluxseg6ei16_v_u8m1(__VA_ARGS__) -#define vluxseg7ei16_v_u8m1(...) __riscv_vluxseg7ei16_v_u8m1(__VA_ARGS__) -#define vluxseg8ei16_v_u8m1(...) __riscv_vluxseg8ei16_v_u8m1(__VA_ARGS__) -#define vluxseg2ei16_v_u8m2(...) __riscv_vluxseg2ei16_v_u8m2(__VA_ARGS__) -#define vluxseg3ei16_v_u8m2(...) __riscv_vluxseg3ei16_v_u8m2(__VA_ARGS__) -#define vluxseg4ei16_v_u8m2(...) __riscv_vluxseg4ei16_v_u8m2(__VA_ARGS__) -#define vluxseg2ei16_v_u8m4(...) __riscv_vluxseg2ei16_v_u8m4(__VA_ARGS__) -#define vluxseg2ei32_v_u8mf8(...) __riscv_vluxseg2ei32_v_u8mf8(__VA_ARGS__) -#define vluxseg3ei32_v_u8mf8(...) __riscv_vluxseg3ei32_v_u8mf8(__VA_ARGS__) -#define vluxseg4ei32_v_u8mf8(...) __riscv_vluxseg4ei32_v_u8mf8(__VA_ARGS__) -#define vluxseg5ei32_v_u8mf8(...) __riscv_vluxseg5ei32_v_u8mf8(__VA_ARGS__) -#define vluxseg6ei32_v_u8mf8(...) __riscv_vluxseg6ei32_v_u8mf8(__VA_ARGS__) -#define vluxseg7ei32_v_u8mf8(...) __riscv_vluxseg7ei32_v_u8mf8(__VA_ARGS__) -#define vluxseg8ei32_v_u8mf8(...) __riscv_vluxseg8ei32_v_u8mf8(__VA_ARGS__) -#define vluxseg2ei32_v_u8mf4(...) __riscv_vluxseg2ei32_v_u8mf4(__VA_ARGS__) -#define vluxseg3ei32_v_u8mf4(...) __riscv_vluxseg3ei32_v_u8mf4(__VA_ARGS__) -#define vluxseg4ei32_v_u8mf4(...) __riscv_vluxseg4ei32_v_u8mf4(__VA_ARGS__) -#define vluxseg5ei32_v_u8mf4(...) __riscv_vluxseg5ei32_v_u8mf4(__VA_ARGS__) -#define vluxseg6ei32_v_u8mf4(...) __riscv_vluxseg6ei32_v_u8mf4(__VA_ARGS__) -#define vluxseg7ei32_v_u8mf4(...) __riscv_vluxseg7ei32_v_u8mf4(__VA_ARGS__) -#define vluxseg8ei32_v_u8mf4(...) __riscv_vluxseg8ei32_v_u8mf4(__VA_ARGS__) -#define vluxseg2ei32_v_u8mf2(...) __riscv_vluxseg2ei32_v_u8mf2(__VA_ARGS__) -#define vluxseg3ei32_v_u8mf2(...) __riscv_vluxseg3ei32_v_u8mf2(__VA_ARGS__) -#define vluxseg4ei32_v_u8mf2(...) __riscv_vluxseg4ei32_v_u8mf2(__VA_ARGS__) -#define vluxseg5ei32_v_u8mf2(...) __riscv_vluxseg5ei32_v_u8mf2(__VA_ARGS__) -#define vluxseg6ei32_v_u8mf2(...) __riscv_vluxseg6ei32_v_u8mf2(__VA_ARGS__) -#define vluxseg7ei32_v_u8mf2(...) __riscv_vluxseg7ei32_v_u8mf2(__VA_ARGS__) -#define vluxseg8ei32_v_u8mf2(...) __riscv_vluxseg8ei32_v_u8mf2(__VA_ARGS__) -#define vluxseg2ei32_v_u8m1(...) __riscv_vluxseg2ei32_v_u8m1(__VA_ARGS__) -#define vluxseg3ei32_v_u8m1(...) __riscv_vluxseg3ei32_v_u8m1(__VA_ARGS__) -#define vluxseg4ei32_v_u8m1(...) __riscv_vluxseg4ei32_v_u8m1(__VA_ARGS__) -#define vluxseg5ei32_v_u8m1(...) __riscv_vluxseg5ei32_v_u8m1(__VA_ARGS__) -#define vluxseg6ei32_v_u8m1(...) __riscv_vluxseg6ei32_v_u8m1(__VA_ARGS__) -#define vluxseg7ei32_v_u8m1(...) __riscv_vluxseg7ei32_v_u8m1(__VA_ARGS__) -#define vluxseg8ei32_v_u8m1(...) __riscv_vluxseg8ei32_v_u8m1(__VA_ARGS__) -#define vluxseg2ei32_v_u8m2(...) __riscv_vluxseg2ei32_v_u8m2(__VA_ARGS__) -#define vluxseg3ei32_v_u8m2(...) __riscv_vluxseg3ei32_v_u8m2(__VA_ARGS__) -#define vluxseg4ei32_v_u8m2(...) __riscv_vluxseg4ei32_v_u8m2(__VA_ARGS__) -#define vluxseg2ei64_v_u8mf8(...) __riscv_vluxseg2ei64_v_u8mf8(__VA_ARGS__) -#define vluxseg3ei64_v_u8mf8(...) __riscv_vluxseg3ei64_v_u8mf8(__VA_ARGS__) -#define vluxseg4ei64_v_u8mf8(...) __riscv_vluxseg4ei64_v_u8mf8(__VA_ARGS__) -#define vluxseg5ei64_v_u8mf8(...) __riscv_vluxseg5ei64_v_u8mf8(__VA_ARGS__) -#define vluxseg6ei64_v_u8mf8(...) __riscv_vluxseg6ei64_v_u8mf8(__VA_ARGS__) -#define vluxseg7ei64_v_u8mf8(...) __riscv_vluxseg7ei64_v_u8mf8(__VA_ARGS__) -#define vluxseg8ei64_v_u8mf8(...) __riscv_vluxseg8ei64_v_u8mf8(__VA_ARGS__) -#define vluxseg2ei64_v_u8mf4(...) __riscv_vluxseg2ei64_v_u8mf4(__VA_ARGS__) -#define vluxseg3ei64_v_u8mf4(...) __riscv_vluxseg3ei64_v_u8mf4(__VA_ARGS__) -#define vluxseg4ei64_v_u8mf4(...) __riscv_vluxseg4ei64_v_u8mf4(__VA_ARGS__) -#define vluxseg5ei64_v_u8mf4(...) __riscv_vluxseg5ei64_v_u8mf4(__VA_ARGS__) -#define vluxseg6ei64_v_u8mf4(...) __riscv_vluxseg6ei64_v_u8mf4(__VA_ARGS__) -#define vluxseg7ei64_v_u8mf4(...) __riscv_vluxseg7ei64_v_u8mf4(__VA_ARGS__) -#define vluxseg8ei64_v_u8mf4(...) __riscv_vluxseg8ei64_v_u8mf4(__VA_ARGS__) -#define vluxseg2ei64_v_u8mf2(...) __riscv_vluxseg2ei64_v_u8mf2(__VA_ARGS__) -#define vluxseg3ei64_v_u8mf2(...) __riscv_vluxseg3ei64_v_u8mf2(__VA_ARGS__) -#define vluxseg4ei64_v_u8mf2(...) __riscv_vluxseg4ei64_v_u8mf2(__VA_ARGS__) -#define vluxseg5ei64_v_u8mf2(...) __riscv_vluxseg5ei64_v_u8mf2(__VA_ARGS__) -#define vluxseg6ei64_v_u8mf2(...) __riscv_vluxseg6ei64_v_u8mf2(__VA_ARGS__) -#define vluxseg7ei64_v_u8mf2(...) __riscv_vluxseg7ei64_v_u8mf2(__VA_ARGS__) -#define vluxseg8ei64_v_u8mf2(...) __riscv_vluxseg8ei64_v_u8mf2(__VA_ARGS__) -#define vluxseg2ei64_v_u8m1(...) __riscv_vluxseg2ei64_v_u8m1(__VA_ARGS__) -#define vluxseg3ei64_v_u8m1(...) __riscv_vluxseg3ei64_v_u8m1(__VA_ARGS__) -#define vluxseg4ei64_v_u8m1(...) __riscv_vluxseg4ei64_v_u8m1(__VA_ARGS__) -#define vluxseg5ei64_v_u8m1(...) __riscv_vluxseg5ei64_v_u8m1(__VA_ARGS__) -#define vluxseg6ei64_v_u8m1(...) __riscv_vluxseg6ei64_v_u8m1(__VA_ARGS__) -#define vluxseg7ei64_v_u8m1(...) __riscv_vluxseg7ei64_v_u8m1(__VA_ARGS__) -#define vluxseg8ei64_v_u8m1(...) __riscv_vluxseg8ei64_v_u8m1(__VA_ARGS__) -#define vluxseg2ei8_v_u16mf4(...) __riscv_vluxseg2ei8_v_u16mf4(__VA_ARGS__) -#define vluxseg3ei8_v_u16mf4(...) __riscv_vluxseg3ei8_v_u16mf4(__VA_ARGS__) -#define vluxseg4ei8_v_u16mf4(...) __riscv_vluxseg4ei8_v_u16mf4(__VA_ARGS__) -#define vluxseg5ei8_v_u16mf4(...) __riscv_vluxseg5ei8_v_u16mf4(__VA_ARGS__) -#define vluxseg6ei8_v_u16mf4(...) __riscv_vluxseg6ei8_v_u16mf4(__VA_ARGS__) -#define vluxseg7ei8_v_u16mf4(...) __riscv_vluxseg7ei8_v_u16mf4(__VA_ARGS__) -#define vluxseg8ei8_v_u16mf4(...) __riscv_vluxseg8ei8_v_u16mf4(__VA_ARGS__) -#define vluxseg2ei8_v_u16mf2(...) __riscv_vluxseg2ei8_v_u16mf2(__VA_ARGS__) -#define vluxseg3ei8_v_u16mf2(...) __riscv_vluxseg3ei8_v_u16mf2(__VA_ARGS__) -#define vluxseg4ei8_v_u16mf2(...) __riscv_vluxseg4ei8_v_u16mf2(__VA_ARGS__) -#define vluxseg5ei8_v_u16mf2(...) __riscv_vluxseg5ei8_v_u16mf2(__VA_ARGS__) -#define vluxseg6ei8_v_u16mf2(...) __riscv_vluxseg6ei8_v_u16mf2(__VA_ARGS__) -#define vluxseg7ei8_v_u16mf2(...) __riscv_vluxseg7ei8_v_u16mf2(__VA_ARGS__) -#define vluxseg8ei8_v_u16mf2(...) __riscv_vluxseg8ei8_v_u16mf2(__VA_ARGS__) -#define vluxseg2ei8_v_u16m1(...) __riscv_vluxseg2ei8_v_u16m1(__VA_ARGS__) -#define vluxseg3ei8_v_u16m1(...) __riscv_vluxseg3ei8_v_u16m1(__VA_ARGS__) -#define vluxseg4ei8_v_u16m1(...) __riscv_vluxseg4ei8_v_u16m1(__VA_ARGS__) -#define vluxseg5ei8_v_u16m1(...) __riscv_vluxseg5ei8_v_u16m1(__VA_ARGS__) -#define vluxseg6ei8_v_u16m1(...) __riscv_vluxseg6ei8_v_u16m1(__VA_ARGS__) -#define vluxseg7ei8_v_u16m1(...) __riscv_vluxseg7ei8_v_u16m1(__VA_ARGS__) -#define vluxseg8ei8_v_u16m1(...) __riscv_vluxseg8ei8_v_u16m1(__VA_ARGS__) -#define vluxseg2ei8_v_u16m2(...) __riscv_vluxseg2ei8_v_u16m2(__VA_ARGS__) -#define vluxseg3ei8_v_u16m2(...) __riscv_vluxseg3ei8_v_u16m2(__VA_ARGS__) -#define vluxseg4ei8_v_u16m2(...) __riscv_vluxseg4ei8_v_u16m2(__VA_ARGS__) -#define vluxseg2ei8_v_u16m4(...) __riscv_vluxseg2ei8_v_u16m4(__VA_ARGS__) -#define vluxseg2ei16_v_u16mf4(...) __riscv_vluxseg2ei16_v_u16mf4(__VA_ARGS__) -#define vluxseg3ei16_v_u16mf4(...) __riscv_vluxseg3ei16_v_u16mf4(__VA_ARGS__) -#define vluxseg4ei16_v_u16mf4(...) __riscv_vluxseg4ei16_v_u16mf4(__VA_ARGS__) -#define vluxseg5ei16_v_u16mf4(...) __riscv_vluxseg5ei16_v_u16mf4(__VA_ARGS__) -#define vluxseg6ei16_v_u16mf4(...) __riscv_vluxseg6ei16_v_u16mf4(__VA_ARGS__) -#define vluxseg7ei16_v_u16mf4(...) __riscv_vluxseg7ei16_v_u16mf4(__VA_ARGS__) -#define vluxseg8ei16_v_u16mf4(...) __riscv_vluxseg8ei16_v_u16mf4(__VA_ARGS__) -#define vluxseg2ei16_v_u16mf2(...) __riscv_vluxseg2ei16_v_u16mf2(__VA_ARGS__) -#define vluxseg3ei16_v_u16mf2(...) __riscv_vluxseg3ei16_v_u16mf2(__VA_ARGS__) -#define vluxseg4ei16_v_u16mf2(...) __riscv_vluxseg4ei16_v_u16mf2(__VA_ARGS__) -#define vluxseg5ei16_v_u16mf2(...) __riscv_vluxseg5ei16_v_u16mf2(__VA_ARGS__) -#define vluxseg6ei16_v_u16mf2(...) __riscv_vluxseg6ei16_v_u16mf2(__VA_ARGS__) -#define vluxseg7ei16_v_u16mf2(...) __riscv_vluxseg7ei16_v_u16mf2(__VA_ARGS__) -#define vluxseg8ei16_v_u16mf2(...) __riscv_vluxseg8ei16_v_u16mf2(__VA_ARGS__) -#define vluxseg2ei16_v_u16m1(...) __riscv_vluxseg2ei16_v_u16m1(__VA_ARGS__) -#define vluxseg3ei16_v_u16m1(...) __riscv_vluxseg3ei16_v_u16m1(__VA_ARGS__) -#define vluxseg4ei16_v_u16m1(...) __riscv_vluxseg4ei16_v_u16m1(__VA_ARGS__) -#define vluxseg5ei16_v_u16m1(...) __riscv_vluxseg5ei16_v_u16m1(__VA_ARGS__) -#define vluxseg6ei16_v_u16m1(...) __riscv_vluxseg6ei16_v_u16m1(__VA_ARGS__) -#define vluxseg7ei16_v_u16m1(...) __riscv_vluxseg7ei16_v_u16m1(__VA_ARGS__) -#define vluxseg8ei16_v_u16m1(...) __riscv_vluxseg8ei16_v_u16m1(__VA_ARGS__) -#define vluxseg2ei16_v_u16m2(...) __riscv_vluxseg2ei16_v_u16m2(__VA_ARGS__) -#define vluxseg3ei16_v_u16m2(...) __riscv_vluxseg3ei16_v_u16m2(__VA_ARGS__) -#define vluxseg4ei16_v_u16m2(...) __riscv_vluxseg4ei16_v_u16m2(__VA_ARGS__) -#define vluxseg2ei16_v_u16m4(...) __riscv_vluxseg2ei16_v_u16m4(__VA_ARGS__) -#define vluxseg2ei32_v_u16mf4(...) __riscv_vluxseg2ei32_v_u16mf4(__VA_ARGS__) -#define vluxseg3ei32_v_u16mf4(...) __riscv_vluxseg3ei32_v_u16mf4(__VA_ARGS__) -#define vluxseg4ei32_v_u16mf4(...) __riscv_vluxseg4ei32_v_u16mf4(__VA_ARGS__) -#define vluxseg5ei32_v_u16mf4(...) __riscv_vluxseg5ei32_v_u16mf4(__VA_ARGS__) -#define vluxseg6ei32_v_u16mf4(...) __riscv_vluxseg6ei32_v_u16mf4(__VA_ARGS__) -#define vluxseg7ei32_v_u16mf4(...) __riscv_vluxseg7ei32_v_u16mf4(__VA_ARGS__) -#define vluxseg8ei32_v_u16mf4(...) __riscv_vluxseg8ei32_v_u16mf4(__VA_ARGS__) -#define vluxseg2ei32_v_u16mf2(...) __riscv_vluxseg2ei32_v_u16mf2(__VA_ARGS__) -#define vluxseg3ei32_v_u16mf2(...) __riscv_vluxseg3ei32_v_u16mf2(__VA_ARGS__) -#define vluxseg4ei32_v_u16mf2(...) __riscv_vluxseg4ei32_v_u16mf2(__VA_ARGS__) -#define vluxseg5ei32_v_u16mf2(...) __riscv_vluxseg5ei32_v_u16mf2(__VA_ARGS__) -#define vluxseg6ei32_v_u16mf2(...) __riscv_vluxseg6ei32_v_u16mf2(__VA_ARGS__) -#define vluxseg7ei32_v_u16mf2(...) __riscv_vluxseg7ei32_v_u16mf2(__VA_ARGS__) -#define vluxseg8ei32_v_u16mf2(...) __riscv_vluxseg8ei32_v_u16mf2(__VA_ARGS__) -#define vluxseg2ei32_v_u16m1(...) __riscv_vluxseg2ei32_v_u16m1(__VA_ARGS__) -#define vluxseg3ei32_v_u16m1(...) __riscv_vluxseg3ei32_v_u16m1(__VA_ARGS__) -#define vluxseg4ei32_v_u16m1(...) __riscv_vluxseg4ei32_v_u16m1(__VA_ARGS__) -#define vluxseg5ei32_v_u16m1(...) __riscv_vluxseg5ei32_v_u16m1(__VA_ARGS__) -#define vluxseg6ei32_v_u16m1(...) __riscv_vluxseg6ei32_v_u16m1(__VA_ARGS__) -#define vluxseg7ei32_v_u16m1(...) __riscv_vluxseg7ei32_v_u16m1(__VA_ARGS__) -#define vluxseg8ei32_v_u16m1(...) __riscv_vluxseg8ei32_v_u16m1(__VA_ARGS__) -#define vluxseg2ei32_v_u16m2(...) __riscv_vluxseg2ei32_v_u16m2(__VA_ARGS__) -#define vluxseg3ei32_v_u16m2(...) __riscv_vluxseg3ei32_v_u16m2(__VA_ARGS__) -#define vluxseg4ei32_v_u16m2(...) __riscv_vluxseg4ei32_v_u16m2(__VA_ARGS__) -#define vluxseg2ei32_v_u16m4(...) __riscv_vluxseg2ei32_v_u16m4(__VA_ARGS__) -#define vluxseg2ei64_v_u16mf4(...) __riscv_vluxseg2ei64_v_u16mf4(__VA_ARGS__) -#define vluxseg3ei64_v_u16mf4(...) __riscv_vluxseg3ei64_v_u16mf4(__VA_ARGS__) -#define vluxseg4ei64_v_u16mf4(...) __riscv_vluxseg4ei64_v_u16mf4(__VA_ARGS__) -#define vluxseg5ei64_v_u16mf4(...) __riscv_vluxseg5ei64_v_u16mf4(__VA_ARGS__) -#define vluxseg6ei64_v_u16mf4(...) __riscv_vluxseg6ei64_v_u16mf4(__VA_ARGS__) -#define vluxseg7ei64_v_u16mf4(...) __riscv_vluxseg7ei64_v_u16mf4(__VA_ARGS__) -#define vluxseg8ei64_v_u16mf4(...) __riscv_vluxseg8ei64_v_u16mf4(__VA_ARGS__) -#define vluxseg2ei64_v_u16mf2(...) __riscv_vluxseg2ei64_v_u16mf2(__VA_ARGS__) -#define vluxseg3ei64_v_u16mf2(...) __riscv_vluxseg3ei64_v_u16mf2(__VA_ARGS__) -#define vluxseg4ei64_v_u16mf2(...) __riscv_vluxseg4ei64_v_u16mf2(__VA_ARGS__) -#define vluxseg5ei64_v_u16mf2(...) __riscv_vluxseg5ei64_v_u16mf2(__VA_ARGS__) -#define vluxseg6ei64_v_u16mf2(...) __riscv_vluxseg6ei64_v_u16mf2(__VA_ARGS__) -#define vluxseg7ei64_v_u16mf2(...) __riscv_vluxseg7ei64_v_u16mf2(__VA_ARGS__) -#define vluxseg8ei64_v_u16mf2(...) __riscv_vluxseg8ei64_v_u16mf2(__VA_ARGS__) -#define vluxseg2ei64_v_u16m1(...) __riscv_vluxseg2ei64_v_u16m1(__VA_ARGS__) -#define vluxseg3ei64_v_u16m1(...) __riscv_vluxseg3ei64_v_u16m1(__VA_ARGS__) -#define vluxseg4ei64_v_u16m1(...) __riscv_vluxseg4ei64_v_u16m1(__VA_ARGS__) -#define vluxseg5ei64_v_u16m1(...) __riscv_vluxseg5ei64_v_u16m1(__VA_ARGS__) -#define vluxseg6ei64_v_u16m1(...) __riscv_vluxseg6ei64_v_u16m1(__VA_ARGS__) -#define vluxseg7ei64_v_u16m1(...) __riscv_vluxseg7ei64_v_u16m1(__VA_ARGS__) -#define vluxseg8ei64_v_u16m1(...) __riscv_vluxseg8ei64_v_u16m1(__VA_ARGS__) -#define vluxseg2ei64_v_u16m2(...) __riscv_vluxseg2ei64_v_u16m2(__VA_ARGS__) -#define vluxseg3ei64_v_u16m2(...) __riscv_vluxseg3ei64_v_u16m2(__VA_ARGS__) -#define vluxseg4ei64_v_u16m2(...) __riscv_vluxseg4ei64_v_u16m2(__VA_ARGS__) -#define vluxseg2ei8_v_u32mf2(...) __riscv_vluxseg2ei8_v_u32mf2(__VA_ARGS__) -#define vluxseg3ei8_v_u32mf2(...) __riscv_vluxseg3ei8_v_u32mf2(__VA_ARGS__) -#define vluxseg4ei8_v_u32mf2(...) __riscv_vluxseg4ei8_v_u32mf2(__VA_ARGS__) -#define vluxseg5ei8_v_u32mf2(...) __riscv_vluxseg5ei8_v_u32mf2(__VA_ARGS__) -#define vluxseg6ei8_v_u32mf2(...) __riscv_vluxseg6ei8_v_u32mf2(__VA_ARGS__) -#define vluxseg7ei8_v_u32mf2(...) __riscv_vluxseg7ei8_v_u32mf2(__VA_ARGS__) -#define vluxseg8ei8_v_u32mf2(...) __riscv_vluxseg8ei8_v_u32mf2(__VA_ARGS__) -#define vluxseg2ei8_v_u32m1(...) __riscv_vluxseg2ei8_v_u32m1(__VA_ARGS__) -#define vluxseg3ei8_v_u32m1(...) __riscv_vluxseg3ei8_v_u32m1(__VA_ARGS__) -#define vluxseg4ei8_v_u32m1(...) __riscv_vluxseg4ei8_v_u32m1(__VA_ARGS__) -#define vluxseg5ei8_v_u32m1(...) __riscv_vluxseg5ei8_v_u32m1(__VA_ARGS__) -#define vluxseg6ei8_v_u32m1(...) __riscv_vluxseg6ei8_v_u32m1(__VA_ARGS__) -#define vluxseg7ei8_v_u32m1(...) __riscv_vluxseg7ei8_v_u32m1(__VA_ARGS__) -#define vluxseg8ei8_v_u32m1(...) __riscv_vluxseg8ei8_v_u32m1(__VA_ARGS__) -#define vluxseg2ei8_v_u32m2(...) __riscv_vluxseg2ei8_v_u32m2(__VA_ARGS__) -#define vluxseg3ei8_v_u32m2(...) __riscv_vluxseg3ei8_v_u32m2(__VA_ARGS__) -#define vluxseg4ei8_v_u32m2(...) __riscv_vluxseg4ei8_v_u32m2(__VA_ARGS__) -#define vluxseg2ei8_v_u32m4(...) __riscv_vluxseg2ei8_v_u32m4(__VA_ARGS__) -#define vluxseg2ei16_v_u32mf2(...) __riscv_vluxseg2ei16_v_u32mf2(__VA_ARGS__) -#define vluxseg3ei16_v_u32mf2(...) __riscv_vluxseg3ei16_v_u32mf2(__VA_ARGS__) -#define vluxseg4ei16_v_u32mf2(...) __riscv_vluxseg4ei16_v_u32mf2(__VA_ARGS__) -#define vluxseg5ei16_v_u32mf2(...) __riscv_vluxseg5ei16_v_u32mf2(__VA_ARGS__) -#define vluxseg6ei16_v_u32mf2(...) __riscv_vluxseg6ei16_v_u32mf2(__VA_ARGS__) -#define vluxseg7ei16_v_u32mf2(...) __riscv_vluxseg7ei16_v_u32mf2(__VA_ARGS__) -#define vluxseg8ei16_v_u32mf2(...) __riscv_vluxseg8ei16_v_u32mf2(__VA_ARGS__) -#define vluxseg2ei16_v_u32m1(...) __riscv_vluxseg2ei16_v_u32m1(__VA_ARGS__) -#define vluxseg3ei16_v_u32m1(...) __riscv_vluxseg3ei16_v_u32m1(__VA_ARGS__) -#define vluxseg4ei16_v_u32m1(...) __riscv_vluxseg4ei16_v_u32m1(__VA_ARGS__) -#define vluxseg5ei16_v_u32m1(...) __riscv_vluxseg5ei16_v_u32m1(__VA_ARGS__) -#define vluxseg6ei16_v_u32m1(...) __riscv_vluxseg6ei16_v_u32m1(__VA_ARGS__) -#define vluxseg7ei16_v_u32m1(...) __riscv_vluxseg7ei16_v_u32m1(__VA_ARGS__) -#define vluxseg8ei16_v_u32m1(...) __riscv_vluxseg8ei16_v_u32m1(__VA_ARGS__) -#define vluxseg2ei16_v_u32m2(...) __riscv_vluxseg2ei16_v_u32m2(__VA_ARGS__) -#define vluxseg3ei16_v_u32m2(...) __riscv_vluxseg3ei16_v_u32m2(__VA_ARGS__) -#define vluxseg4ei16_v_u32m2(...) __riscv_vluxseg4ei16_v_u32m2(__VA_ARGS__) -#define vluxseg2ei16_v_u32m4(...) __riscv_vluxseg2ei16_v_u32m4(__VA_ARGS__) -#define vluxseg2ei32_v_u32mf2(...) __riscv_vluxseg2ei32_v_u32mf2(__VA_ARGS__) -#define vluxseg3ei32_v_u32mf2(...) __riscv_vluxseg3ei32_v_u32mf2(__VA_ARGS__) -#define vluxseg4ei32_v_u32mf2(...) __riscv_vluxseg4ei32_v_u32mf2(__VA_ARGS__) -#define vluxseg5ei32_v_u32mf2(...) __riscv_vluxseg5ei32_v_u32mf2(__VA_ARGS__) -#define vluxseg6ei32_v_u32mf2(...) __riscv_vluxseg6ei32_v_u32mf2(__VA_ARGS__) -#define vluxseg7ei32_v_u32mf2(...) __riscv_vluxseg7ei32_v_u32mf2(__VA_ARGS__) -#define vluxseg8ei32_v_u32mf2(...) __riscv_vluxseg8ei32_v_u32mf2(__VA_ARGS__) -#define vluxseg2ei32_v_u32m1(...) __riscv_vluxseg2ei32_v_u32m1(__VA_ARGS__) -#define vluxseg3ei32_v_u32m1(...) __riscv_vluxseg3ei32_v_u32m1(__VA_ARGS__) -#define vluxseg4ei32_v_u32m1(...) __riscv_vluxseg4ei32_v_u32m1(__VA_ARGS__) -#define vluxseg5ei32_v_u32m1(...) __riscv_vluxseg5ei32_v_u32m1(__VA_ARGS__) -#define vluxseg6ei32_v_u32m1(...) __riscv_vluxseg6ei32_v_u32m1(__VA_ARGS__) -#define vluxseg7ei32_v_u32m1(...) __riscv_vluxseg7ei32_v_u32m1(__VA_ARGS__) -#define vluxseg8ei32_v_u32m1(...) __riscv_vluxseg8ei32_v_u32m1(__VA_ARGS__) -#define vluxseg2ei32_v_u32m2(...) __riscv_vluxseg2ei32_v_u32m2(__VA_ARGS__) -#define vluxseg3ei32_v_u32m2(...) __riscv_vluxseg3ei32_v_u32m2(__VA_ARGS__) -#define vluxseg4ei32_v_u32m2(...) __riscv_vluxseg4ei32_v_u32m2(__VA_ARGS__) -#define vluxseg2ei32_v_u32m4(...) __riscv_vluxseg2ei32_v_u32m4(__VA_ARGS__) -#define vluxseg2ei64_v_u32mf2(...) __riscv_vluxseg2ei64_v_u32mf2(__VA_ARGS__) -#define vluxseg3ei64_v_u32mf2(...) __riscv_vluxseg3ei64_v_u32mf2(__VA_ARGS__) -#define vluxseg4ei64_v_u32mf2(...) __riscv_vluxseg4ei64_v_u32mf2(__VA_ARGS__) -#define vluxseg5ei64_v_u32mf2(...) __riscv_vluxseg5ei64_v_u32mf2(__VA_ARGS__) -#define vluxseg6ei64_v_u32mf2(...) __riscv_vluxseg6ei64_v_u32mf2(__VA_ARGS__) -#define vluxseg7ei64_v_u32mf2(...) __riscv_vluxseg7ei64_v_u32mf2(__VA_ARGS__) -#define vluxseg8ei64_v_u32mf2(...) __riscv_vluxseg8ei64_v_u32mf2(__VA_ARGS__) -#define vluxseg2ei64_v_u32m1(...) __riscv_vluxseg2ei64_v_u32m1(__VA_ARGS__) -#define vluxseg3ei64_v_u32m1(...) __riscv_vluxseg3ei64_v_u32m1(__VA_ARGS__) -#define vluxseg4ei64_v_u32m1(...) __riscv_vluxseg4ei64_v_u32m1(__VA_ARGS__) -#define vluxseg5ei64_v_u32m1(...) __riscv_vluxseg5ei64_v_u32m1(__VA_ARGS__) -#define vluxseg6ei64_v_u32m1(...) __riscv_vluxseg6ei64_v_u32m1(__VA_ARGS__) -#define vluxseg7ei64_v_u32m1(...) __riscv_vluxseg7ei64_v_u32m1(__VA_ARGS__) -#define vluxseg8ei64_v_u32m1(...) __riscv_vluxseg8ei64_v_u32m1(__VA_ARGS__) -#define vluxseg2ei64_v_u32m2(...) __riscv_vluxseg2ei64_v_u32m2(__VA_ARGS__) -#define vluxseg3ei64_v_u32m2(...) __riscv_vluxseg3ei64_v_u32m2(__VA_ARGS__) -#define vluxseg4ei64_v_u32m2(...) __riscv_vluxseg4ei64_v_u32m2(__VA_ARGS__) -#define vluxseg2ei64_v_u32m4(...) __riscv_vluxseg2ei64_v_u32m4(__VA_ARGS__) -#define vluxseg2ei8_v_u64m1(...) __riscv_vluxseg2ei8_v_u64m1(__VA_ARGS__) -#define vluxseg3ei8_v_u64m1(...) __riscv_vluxseg3ei8_v_u64m1(__VA_ARGS__) -#define vluxseg4ei8_v_u64m1(...) __riscv_vluxseg4ei8_v_u64m1(__VA_ARGS__) -#define vluxseg5ei8_v_u64m1(...) __riscv_vluxseg5ei8_v_u64m1(__VA_ARGS__) -#define vluxseg6ei8_v_u64m1(...) __riscv_vluxseg6ei8_v_u64m1(__VA_ARGS__) -#define vluxseg7ei8_v_u64m1(...) __riscv_vluxseg7ei8_v_u64m1(__VA_ARGS__) -#define vluxseg8ei8_v_u64m1(...) __riscv_vluxseg8ei8_v_u64m1(__VA_ARGS__) -#define vluxseg2ei8_v_u64m2(...) __riscv_vluxseg2ei8_v_u64m2(__VA_ARGS__) -#define vluxseg3ei8_v_u64m2(...) __riscv_vluxseg3ei8_v_u64m2(__VA_ARGS__) -#define vluxseg4ei8_v_u64m2(...) __riscv_vluxseg4ei8_v_u64m2(__VA_ARGS__) -#define vluxseg2ei8_v_u64m4(...) __riscv_vluxseg2ei8_v_u64m4(__VA_ARGS__) -#define vluxseg2ei16_v_u64m1(...) __riscv_vluxseg2ei16_v_u64m1(__VA_ARGS__) -#define vluxseg3ei16_v_u64m1(...) __riscv_vluxseg3ei16_v_u64m1(__VA_ARGS__) -#define vluxseg4ei16_v_u64m1(...) __riscv_vluxseg4ei16_v_u64m1(__VA_ARGS__) -#define vluxseg5ei16_v_u64m1(...) __riscv_vluxseg5ei16_v_u64m1(__VA_ARGS__) -#define vluxseg6ei16_v_u64m1(...) __riscv_vluxseg6ei16_v_u64m1(__VA_ARGS__) -#define vluxseg7ei16_v_u64m1(...) __riscv_vluxseg7ei16_v_u64m1(__VA_ARGS__) -#define vluxseg8ei16_v_u64m1(...) __riscv_vluxseg8ei16_v_u64m1(__VA_ARGS__) -#define vluxseg2ei16_v_u64m2(...) __riscv_vluxseg2ei16_v_u64m2(__VA_ARGS__) -#define vluxseg3ei16_v_u64m2(...) __riscv_vluxseg3ei16_v_u64m2(__VA_ARGS__) -#define vluxseg4ei16_v_u64m2(...) __riscv_vluxseg4ei16_v_u64m2(__VA_ARGS__) -#define vluxseg2ei16_v_u64m4(...) __riscv_vluxseg2ei16_v_u64m4(__VA_ARGS__) -#define vluxseg2ei32_v_u64m1(...) __riscv_vluxseg2ei32_v_u64m1(__VA_ARGS__) -#define vluxseg3ei32_v_u64m1(...) __riscv_vluxseg3ei32_v_u64m1(__VA_ARGS__) -#define vluxseg4ei32_v_u64m1(...) __riscv_vluxseg4ei32_v_u64m1(__VA_ARGS__) -#define vluxseg5ei32_v_u64m1(...) __riscv_vluxseg5ei32_v_u64m1(__VA_ARGS__) -#define vluxseg6ei32_v_u64m1(...) __riscv_vluxseg6ei32_v_u64m1(__VA_ARGS__) -#define vluxseg7ei32_v_u64m1(...) __riscv_vluxseg7ei32_v_u64m1(__VA_ARGS__) -#define vluxseg8ei32_v_u64m1(...) __riscv_vluxseg8ei32_v_u64m1(__VA_ARGS__) -#define vluxseg2ei32_v_u64m2(...) __riscv_vluxseg2ei32_v_u64m2(__VA_ARGS__) -#define vluxseg3ei32_v_u64m2(...) __riscv_vluxseg3ei32_v_u64m2(__VA_ARGS__) -#define vluxseg4ei32_v_u64m2(...) __riscv_vluxseg4ei32_v_u64m2(__VA_ARGS__) -#define vluxseg2ei32_v_u64m4(...) __riscv_vluxseg2ei32_v_u64m4(__VA_ARGS__) -#define vluxseg2ei64_v_u64m1(...) __riscv_vluxseg2ei64_v_u64m1(__VA_ARGS__) -#define vluxseg3ei64_v_u64m1(...) __riscv_vluxseg3ei64_v_u64m1(__VA_ARGS__) -#define vluxseg4ei64_v_u64m1(...) __riscv_vluxseg4ei64_v_u64m1(__VA_ARGS__) -#define vluxseg5ei64_v_u64m1(...) __riscv_vluxseg5ei64_v_u64m1(__VA_ARGS__) -#define vluxseg6ei64_v_u64m1(...) __riscv_vluxseg6ei64_v_u64m1(__VA_ARGS__) -#define vluxseg7ei64_v_u64m1(...) __riscv_vluxseg7ei64_v_u64m1(__VA_ARGS__) -#define vluxseg8ei64_v_u64m1(...) __riscv_vluxseg8ei64_v_u64m1(__VA_ARGS__) -#define vluxseg2ei64_v_u64m2(...) __riscv_vluxseg2ei64_v_u64m2(__VA_ARGS__) -#define vluxseg3ei64_v_u64m2(...) __riscv_vluxseg3ei64_v_u64m2(__VA_ARGS__) -#define vluxseg4ei64_v_u64m2(...) __riscv_vluxseg4ei64_v_u64m2(__VA_ARGS__) -#define vluxseg2ei64_v_u64m4(...) __riscv_vluxseg2ei64_v_u64m4(__VA_ARGS__) -// masked functions -#define vloxseg2ei8_v_f16mf4_m(...) __riscv_vloxseg2ei8_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_f16mf4_m(...) __riscv_vloxseg3ei8_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_f16mf4_m(...) __riscv_vloxseg4ei8_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_f16mf4_m(...) __riscv_vloxseg5ei8_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_f16mf4_m(...) __riscv_vloxseg6ei8_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_f16mf4_m(...) __riscv_vloxseg7ei8_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_f16mf4_m(...) __riscv_vloxseg8ei8_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_f16mf2_m(...) __riscv_vloxseg2ei8_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_f16mf2_m(...) __riscv_vloxseg3ei8_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_f16mf2_m(...) __riscv_vloxseg4ei8_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_f16mf2_m(...) __riscv_vloxseg5ei8_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_f16mf2_m(...) __riscv_vloxseg6ei8_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_f16mf2_m(...) __riscv_vloxseg7ei8_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_f16mf2_m(...) __riscv_vloxseg8ei8_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_f16m1_m(...) __riscv_vloxseg2ei8_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_f16m1_m(...) __riscv_vloxseg3ei8_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_f16m1_m(...) __riscv_vloxseg4ei8_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_f16m1_m(...) __riscv_vloxseg5ei8_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_f16m1_m(...) __riscv_vloxseg6ei8_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_f16m1_m(...) __riscv_vloxseg7ei8_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_f16m1_m(...) __riscv_vloxseg8ei8_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_f16m2_m(...) __riscv_vloxseg2ei8_v_f16m2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_f16m2_m(...) __riscv_vloxseg3ei8_v_f16m2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_f16m2_m(...) __riscv_vloxseg4ei8_v_f16m2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_f16m4_m(...) __riscv_vloxseg2ei8_v_f16m4_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_f16mf4_m(...) __riscv_vloxseg2ei16_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_f16mf4_m(...) __riscv_vloxseg3ei16_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_f16mf4_m(...) __riscv_vloxseg4ei16_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_f16mf4_m(...) __riscv_vloxseg5ei16_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_f16mf4_m(...) __riscv_vloxseg6ei16_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_f16mf4_m(...) __riscv_vloxseg7ei16_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_f16mf4_m(...) __riscv_vloxseg8ei16_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_f16mf2_m(...) __riscv_vloxseg2ei16_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_f16mf2_m(...) __riscv_vloxseg3ei16_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_f16mf2_m(...) __riscv_vloxseg4ei16_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_f16mf2_m(...) __riscv_vloxseg5ei16_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_f16mf2_m(...) __riscv_vloxseg6ei16_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_f16mf2_m(...) __riscv_vloxseg7ei16_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_f16mf2_m(...) __riscv_vloxseg8ei16_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_f16m1_m(...) __riscv_vloxseg2ei16_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_f16m1_m(...) __riscv_vloxseg3ei16_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_f16m1_m(...) __riscv_vloxseg4ei16_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_f16m1_m(...) __riscv_vloxseg5ei16_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_f16m1_m(...) __riscv_vloxseg6ei16_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_f16m1_m(...) __riscv_vloxseg7ei16_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_f16m1_m(...) __riscv_vloxseg8ei16_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_f16m2_m(...) __riscv_vloxseg2ei16_v_f16m2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_f16m2_m(...) __riscv_vloxseg3ei16_v_f16m2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_f16m2_m(...) __riscv_vloxseg4ei16_v_f16m2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_f16m4_m(...) __riscv_vloxseg2ei16_v_f16m4_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_f16mf4_m(...) __riscv_vloxseg2ei32_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_f16mf4_m(...) __riscv_vloxseg3ei32_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_f16mf4_m(...) __riscv_vloxseg4ei32_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_f16mf4_m(...) __riscv_vloxseg5ei32_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_f16mf4_m(...) __riscv_vloxseg6ei32_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_f16mf4_m(...) __riscv_vloxseg7ei32_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_f16mf4_m(...) __riscv_vloxseg8ei32_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_f16mf2_m(...) __riscv_vloxseg2ei32_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_f16mf2_m(...) __riscv_vloxseg3ei32_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_f16mf2_m(...) __riscv_vloxseg4ei32_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_f16mf2_m(...) __riscv_vloxseg5ei32_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_f16mf2_m(...) __riscv_vloxseg6ei32_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_f16mf2_m(...) __riscv_vloxseg7ei32_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_f16mf2_m(...) __riscv_vloxseg8ei32_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_f16m1_m(...) __riscv_vloxseg2ei32_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_f16m1_m(...) __riscv_vloxseg3ei32_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_f16m1_m(...) __riscv_vloxseg4ei32_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_f16m1_m(...) __riscv_vloxseg5ei32_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_f16m1_m(...) __riscv_vloxseg6ei32_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_f16m1_m(...) __riscv_vloxseg7ei32_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_f16m1_m(...) __riscv_vloxseg8ei32_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_f16m2_m(...) __riscv_vloxseg2ei32_v_f16m2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_f16m2_m(...) __riscv_vloxseg3ei32_v_f16m2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_f16m2_m(...) __riscv_vloxseg4ei32_v_f16m2_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_f16m4_m(...) __riscv_vloxseg2ei32_v_f16m4_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_f16mf4_m(...) __riscv_vloxseg2ei64_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_f16mf4_m(...) __riscv_vloxseg3ei64_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_f16mf4_m(...) __riscv_vloxseg4ei64_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_f16mf4_m(...) __riscv_vloxseg5ei64_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_f16mf4_m(...) __riscv_vloxseg6ei64_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_f16mf4_m(...) __riscv_vloxseg7ei64_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_f16mf4_m(...) __riscv_vloxseg8ei64_v_f16mf4_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_f16mf2_m(...) __riscv_vloxseg2ei64_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_f16mf2_m(...) __riscv_vloxseg3ei64_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_f16mf2_m(...) __riscv_vloxseg4ei64_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_f16mf2_m(...) __riscv_vloxseg5ei64_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_f16mf2_m(...) __riscv_vloxseg6ei64_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_f16mf2_m(...) __riscv_vloxseg7ei64_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_f16mf2_m(...) __riscv_vloxseg8ei64_v_f16mf2_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_f16m1_m(...) __riscv_vloxseg2ei64_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_f16m1_m(...) __riscv_vloxseg3ei64_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_f16m1_m(...) __riscv_vloxseg4ei64_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_f16m1_m(...) __riscv_vloxseg5ei64_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_f16m1_m(...) __riscv_vloxseg6ei64_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_f16m1_m(...) __riscv_vloxseg7ei64_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_f16m1_m(...) __riscv_vloxseg8ei64_v_f16m1_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_f16m2_m(...) __riscv_vloxseg2ei64_v_f16m2_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_f16m2_m(...) __riscv_vloxseg3ei64_v_f16m2_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_f16m2_m(...) __riscv_vloxseg4ei64_v_f16m2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_f32mf2_m(...) __riscv_vloxseg2ei8_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_f32mf2_m(...) __riscv_vloxseg3ei8_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_f32mf2_m(...) __riscv_vloxseg4ei8_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_f32mf2_m(...) __riscv_vloxseg5ei8_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_f32mf2_m(...) __riscv_vloxseg6ei8_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_f32mf2_m(...) __riscv_vloxseg7ei8_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_f32mf2_m(...) __riscv_vloxseg8ei8_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_f32m1_m(...) __riscv_vloxseg2ei8_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_f32m1_m(...) __riscv_vloxseg3ei8_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_f32m1_m(...) __riscv_vloxseg4ei8_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_f32m1_m(...) __riscv_vloxseg5ei8_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_f32m1_m(...) __riscv_vloxseg6ei8_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_f32m1_m(...) __riscv_vloxseg7ei8_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_f32m1_m(...) __riscv_vloxseg8ei8_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_f32m2_m(...) __riscv_vloxseg2ei8_v_f32m2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_f32m2_m(...) __riscv_vloxseg3ei8_v_f32m2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_f32m2_m(...) __riscv_vloxseg4ei8_v_f32m2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_f32m4_m(...) __riscv_vloxseg2ei8_v_f32m4_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_f32mf2_m(...) __riscv_vloxseg2ei16_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_f32mf2_m(...) __riscv_vloxseg3ei16_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_f32mf2_m(...) __riscv_vloxseg4ei16_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_f32mf2_m(...) __riscv_vloxseg5ei16_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_f32mf2_m(...) __riscv_vloxseg6ei16_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_f32mf2_m(...) __riscv_vloxseg7ei16_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_f32mf2_m(...) __riscv_vloxseg8ei16_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_f32m1_m(...) __riscv_vloxseg2ei16_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_f32m1_m(...) __riscv_vloxseg3ei16_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_f32m1_m(...) __riscv_vloxseg4ei16_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_f32m1_m(...) __riscv_vloxseg5ei16_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_f32m1_m(...) __riscv_vloxseg6ei16_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_f32m1_m(...) __riscv_vloxseg7ei16_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_f32m1_m(...) __riscv_vloxseg8ei16_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_f32m2_m(...) __riscv_vloxseg2ei16_v_f32m2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_f32m2_m(...) __riscv_vloxseg3ei16_v_f32m2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_f32m2_m(...) __riscv_vloxseg4ei16_v_f32m2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_f32m4_m(...) __riscv_vloxseg2ei16_v_f32m4_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_f32mf2_m(...) __riscv_vloxseg2ei32_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_f32mf2_m(...) __riscv_vloxseg3ei32_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_f32mf2_m(...) __riscv_vloxseg4ei32_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_f32mf2_m(...) __riscv_vloxseg5ei32_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_f32mf2_m(...) __riscv_vloxseg6ei32_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_f32mf2_m(...) __riscv_vloxseg7ei32_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_f32mf2_m(...) __riscv_vloxseg8ei32_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_f32m1_m(...) __riscv_vloxseg2ei32_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_f32m1_m(...) __riscv_vloxseg3ei32_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_f32m1_m(...) __riscv_vloxseg4ei32_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_f32m1_m(...) __riscv_vloxseg5ei32_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_f32m1_m(...) __riscv_vloxseg6ei32_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_f32m1_m(...) __riscv_vloxseg7ei32_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_f32m1_m(...) __riscv_vloxseg8ei32_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_f32m2_m(...) __riscv_vloxseg2ei32_v_f32m2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_f32m2_m(...) __riscv_vloxseg3ei32_v_f32m2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_f32m2_m(...) __riscv_vloxseg4ei32_v_f32m2_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_f32m4_m(...) __riscv_vloxseg2ei32_v_f32m4_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_f32mf2_m(...) __riscv_vloxseg2ei64_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_f32mf2_m(...) __riscv_vloxseg3ei64_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_f32mf2_m(...) __riscv_vloxseg4ei64_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_f32mf2_m(...) __riscv_vloxseg5ei64_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_f32mf2_m(...) __riscv_vloxseg6ei64_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_f32mf2_m(...) __riscv_vloxseg7ei64_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_f32mf2_m(...) __riscv_vloxseg8ei64_v_f32mf2_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_f32m1_m(...) __riscv_vloxseg2ei64_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_f32m1_m(...) __riscv_vloxseg3ei64_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_f32m1_m(...) __riscv_vloxseg4ei64_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_f32m1_m(...) __riscv_vloxseg5ei64_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_f32m1_m(...) __riscv_vloxseg6ei64_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_f32m1_m(...) __riscv_vloxseg7ei64_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_f32m1_m(...) __riscv_vloxseg8ei64_v_f32m1_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_f32m2_m(...) __riscv_vloxseg2ei64_v_f32m2_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_f32m2_m(...) __riscv_vloxseg3ei64_v_f32m2_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_f32m2_m(...) __riscv_vloxseg4ei64_v_f32m2_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_f32m4_m(...) __riscv_vloxseg2ei64_v_f32m4_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_f64m1_m(...) __riscv_vloxseg2ei8_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_f64m1_m(...) __riscv_vloxseg3ei8_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_f64m1_m(...) __riscv_vloxseg4ei8_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_f64m1_m(...) __riscv_vloxseg5ei8_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_f64m1_m(...) __riscv_vloxseg6ei8_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_f64m1_m(...) __riscv_vloxseg7ei8_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_f64m1_m(...) __riscv_vloxseg8ei8_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_f64m2_m(...) __riscv_vloxseg2ei8_v_f64m2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_f64m2_m(...) __riscv_vloxseg3ei8_v_f64m2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_f64m2_m(...) __riscv_vloxseg4ei8_v_f64m2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_f64m4_m(...) __riscv_vloxseg2ei8_v_f64m4_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_f64m1_m(...) __riscv_vloxseg2ei16_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_f64m1_m(...) __riscv_vloxseg3ei16_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_f64m1_m(...) __riscv_vloxseg4ei16_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_f64m1_m(...) __riscv_vloxseg5ei16_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_f64m1_m(...) __riscv_vloxseg6ei16_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_f64m1_m(...) __riscv_vloxseg7ei16_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_f64m1_m(...) __riscv_vloxseg8ei16_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_f64m2_m(...) __riscv_vloxseg2ei16_v_f64m2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_f64m2_m(...) __riscv_vloxseg3ei16_v_f64m2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_f64m2_m(...) __riscv_vloxseg4ei16_v_f64m2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_f64m4_m(...) __riscv_vloxseg2ei16_v_f64m4_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_f64m1_m(...) __riscv_vloxseg2ei32_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_f64m1_m(...) __riscv_vloxseg3ei32_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_f64m1_m(...) __riscv_vloxseg4ei32_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_f64m1_m(...) __riscv_vloxseg5ei32_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_f64m1_m(...) __riscv_vloxseg6ei32_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_f64m1_m(...) __riscv_vloxseg7ei32_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_f64m1_m(...) __riscv_vloxseg8ei32_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_f64m2_m(...) __riscv_vloxseg2ei32_v_f64m2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_f64m2_m(...) __riscv_vloxseg3ei32_v_f64m2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_f64m2_m(...) __riscv_vloxseg4ei32_v_f64m2_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_f64m4_m(...) __riscv_vloxseg2ei32_v_f64m4_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_f64m1_m(...) __riscv_vloxseg2ei64_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_f64m1_m(...) __riscv_vloxseg3ei64_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_f64m1_m(...) __riscv_vloxseg4ei64_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_f64m1_m(...) __riscv_vloxseg5ei64_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_f64m1_m(...) __riscv_vloxseg6ei64_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_f64m1_m(...) __riscv_vloxseg7ei64_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_f64m1_m(...) __riscv_vloxseg8ei64_v_f64m1_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_f64m2_m(...) __riscv_vloxseg2ei64_v_f64m2_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_f64m2_m(...) __riscv_vloxseg3ei64_v_f64m2_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_f64m2_m(...) __riscv_vloxseg4ei64_v_f64m2_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_f64m4_m(...) __riscv_vloxseg2ei64_v_f64m4_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_f16mf4_m(...) __riscv_vluxseg2ei8_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_f16mf4_m(...) __riscv_vluxseg3ei8_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_f16mf4_m(...) __riscv_vluxseg4ei8_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_f16mf4_m(...) __riscv_vluxseg5ei8_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_f16mf4_m(...) __riscv_vluxseg6ei8_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_f16mf4_m(...) __riscv_vluxseg7ei8_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_f16mf4_m(...) __riscv_vluxseg8ei8_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_f16mf2_m(...) __riscv_vluxseg2ei8_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_f16mf2_m(...) __riscv_vluxseg3ei8_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_f16mf2_m(...) __riscv_vluxseg4ei8_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_f16mf2_m(...) __riscv_vluxseg5ei8_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_f16mf2_m(...) __riscv_vluxseg6ei8_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_f16mf2_m(...) __riscv_vluxseg7ei8_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_f16mf2_m(...) __riscv_vluxseg8ei8_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_f16m1_m(...) __riscv_vluxseg2ei8_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_f16m1_m(...) __riscv_vluxseg3ei8_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_f16m1_m(...) __riscv_vluxseg4ei8_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_f16m1_m(...) __riscv_vluxseg5ei8_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_f16m1_m(...) __riscv_vluxseg6ei8_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_f16m1_m(...) __riscv_vluxseg7ei8_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_f16m1_m(...) __riscv_vluxseg8ei8_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_f16m2_m(...) __riscv_vluxseg2ei8_v_f16m2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_f16m2_m(...) __riscv_vluxseg3ei8_v_f16m2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_f16m2_m(...) __riscv_vluxseg4ei8_v_f16m2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_f16m4_m(...) __riscv_vluxseg2ei8_v_f16m4_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_f16mf4_m(...) __riscv_vluxseg2ei16_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_f16mf4_m(...) __riscv_vluxseg3ei16_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_f16mf4_m(...) __riscv_vluxseg4ei16_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_f16mf4_m(...) __riscv_vluxseg5ei16_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_f16mf4_m(...) __riscv_vluxseg6ei16_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_f16mf4_m(...) __riscv_vluxseg7ei16_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_f16mf4_m(...) __riscv_vluxseg8ei16_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_f16mf2_m(...) __riscv_vluxseg2ei16_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_f16mf2_m(...) __riscv_vluxseg3ei16_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_f16mf2_m(...) __riscv_vluxseg4ei16_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_f16mf2_m(...) __riscv_vluxseg5ei16_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_f16mf2_m(...) __riscv_vluxseg6ei16_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_f16mf2_m(...) __riscv_vluxseg7ei16_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_f16mf2_m(...) __riscv_vluxseg8ei16_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_f16m1_m(...) __riscv_vluxseg2ei16_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_f16m1_m(...) __riscv_vluxseg3ei16_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_f16m1_m(...) __riscv_vluxseg4ei16_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_f16m1_m(...) __riscv_vluxseg5ei16_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_f16m1_m(...) __riscv_vluxseg6ei16_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_f16m1_m(...) __riscv_vluxseg7ei16_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_f16m1_m(...) __riscv_vluxseg8ei16_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_f16m2_m(...) __riscv_vluxseg2ei16_v_f16m2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_f16m2_m(...) __riscv_vluxseg3ei16_v_f16m2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_f16m2_m(...) __riscv_vluxseg4ei16_v_f16m2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_f16m4_m(...) __riscv_vluxseg2ei16_v_f16m4_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_f16mf4_m(...) __riscv_vluxseg2ei32_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_f16mf4_m(...) __riscv_vluxseg3ei32_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_f16mf4_m(...) __riscv_vluxseg4ei32_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_f16mf4_m(...) __riscv_vluxseg5ei32_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_f16mf4_m(...) __riscv_vluxseg6ei32_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_f16mf4_m(...) __riscv_vluxseg7ei32_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_f16mf4_m(...) __riscv_vluxseg8ei32_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_f16mf2_m(...) __riscv_vluxseg2ei32_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_f16mf2_m(...) __riscv_vluxseg3ei32_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_f16mf2_m(...) __riscv_vluxseg4ei32_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_f16mf2_m(...) __riscv_vluxseg5ei32_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_f16mf2_m(...) __riscv_vluxseg6ei32_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_f16mf2_m(...) __riscv_vluxseg7ei32_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_f16mf2_m(...) __riscv_vluxseg8ei32_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_f16m1_m(...) __riscv_vluxseg2ei32_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_f16m1_m(...) __riscv_vluxseg3ei32_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_f16m1_m(...) __riscv_vluxseg4ei32_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_f16m1_m(...) __riscv_vluxseg5ei32_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_f16m1_m(...) __riscv_vluxseg6ei32_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_f16m1_m(...) __riscv_vluxseg7ei32_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_f16m1_m(...) __riscv_vluxseg8ei32_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_f16m2_m(...) __riscv_vluxseg2ei32_v_f16m2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_f16m2_m(...) __riscv_vluxseg3ei32_v_f16m2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_f16m2_m(...) __riscv_vluxseg4ei32_v_f16m2_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_f16m4_m(...) __riscv_vluxseg2ei32_v_f16m4_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_f16mf4_m(...) __riscv_vluxseg2ei64_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_f16mf4_m(...) __riscv_vluxseg3ei64_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_f16mf4_m(...) __riscv_vluxseg4ei64_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_f16mf4_m(...) __riscv_vluxseg5ei64_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_f16mf4_m(...) __riscv_vluxseg6ei64_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_f16mf4_m(...) __riscv_vluxseg7ei64_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_f16mf4_m(...) __riscv_vluxseg8ei64_v_f16mf4_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_f16mf2_m(...) __riscv_vluxseg2ei64_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_f16mf2_m(...) __riscv_vluxseg3ei64_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_f16mf2_m(...) __riscv_vluxseg4ei64_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_f16mf2_m(...) __riscv_vluxseg5ei64_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_f16mf2_m(...) __riscv_vluxseg6ei64_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_f16mf2_m(...) __riscv_vluxseg7ei64_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_f16mf2_m(...) __riscv_vluxseg8ei64_v_f16mf2_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_f16m1_m(...) __riscv_vluxseg2ei64_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_f16m1_m(...) __riscv_vluxseg3ei64_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_f16m1_m(...) __riscv_vluxseg4ei64_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_f16m1_m(...) __riscv_vluxseg5ei64_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_f16m1_m(...) __riscv_vluxseg6ei64_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_f16m1_m(...) __riscv_vluxseg7ei64_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_f16m1_m(...) __riscv_vluxseg8ei64_v_f16m1_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_f16m2_m(...) __riscv_vluxseg2ei64_v_f16m2_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_f16m2_m(...) __riscv_vluxseg3ei64_v_f16m2_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_f16m2_m(...) __riscv_vluxseg4ei64_v_f16m2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_f32mf2_m(...) __riscv_vluxseg2ei8_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_f32mf2_m(...) __riscv_vluxseg3ei8_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_f32mf2_m(...) __riscv_vluxseg4ei8_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_f32mf2_m(...) __riscv_vluxseg5ei8_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_f32mf2_m(...) __riscv_vluxseg6ei8_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_f32mf2_m(...) __riscv_vluxseg7ei8_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_f32mf2_m(...) __riscv_vluxseg8ei8_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_f32m1_m(...) __riscv_vluxseg2ei8_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_f32m1_m(...) __riscv_vluxseg3ei8_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_f32m1_m(...) __riscv_vluxseg4ei8_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_f32m1_m(...) __riscv_vluxseg5ei8_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_f32m1_m(...) __riscv_vluxseg6ei8_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_f32m1_m(...) __riscv_vluxseg7ei8_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_f32m1_m(...) __riscv_vluxseg8ei8_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_f32m2_m(...) __riscv_vluxseg2ei8_v_f32m2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_f32m2_m(...) __riscv_vluxseg3ei8_v_f32m2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_f32m2_m(...) __riscv_vluxseg4ei8_v_f32m2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_f32m4_m(...) __riscv_vluxseg2ei8_v_f32m4_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_f32mf2_m(...) __riscv_vluxseg2ei16_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_f32mf2_m(...) __riscv_vluxseg3ei16_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_f32mf2_m(...) __riscv_vluxseg4ei16_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_f32mf2_m(...) __riscv_vluxseg5ei16_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_f32mf2_m(...) __riscv_vluxseg6ei16_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_f32mf2_m(...) __riscv_vluxseg7ei16_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_f32mf2_m(...) __riscv_vluxseg8ei16_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_f32m1_m(...) __riscv_vluxseg2ei16_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_f32m1_m(...) __riscv_vluxseg3ei16_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_f32m1_m(...) __riscv_vluxseg4ei16_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_f32m1_m(...) __riscv_vluxseg5ei16_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_f32m1_m(...) __riscv_vluxseg6ei16_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_f32m1_m(...) __riscv_vluxseg7ei16_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_f32m1_m(...) __riscv_vluxseg8ei16_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_f32m2_m(...) __riscv_vluxseg2ei16_v_f32m2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_f32m2_m(...) __riscv_vluxseg3ei16_v_f32m2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_f32m2_m(...) __riscv_vluxseg4ei16_v_f32m2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_f32m4_m(...) __riscv_vluxseg2ei16_v_f32m4_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_f32mf2_m(...) __riscv_vluxseg2ei32_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_f32mf2_m(...) __riscv_vluxseg3ei32_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_f32mf2_m(...) __riscv_vluxseg4ei32_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_f32mf2_m(...) __riscv_vluxseg5ei32_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_f32mf2_m(...) __riscv_vluxseg6ei32_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_f32mf2_m(...) __riscv_vluxseg7ei32_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_f32mf2_m(...) __riscv_vluxseg8ei32_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_f32m1_m(...) __riscv_vluxseg2ei32_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_f32m1_m(...) __riscv_vluxseg3ei32_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_f32m1_m(...) __riscv_vluxseg4ei32_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_f32m1_m(...) __riscv_vluxseg5ei32_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_f32m1_m(...) __riscv_vluxseg6ei32_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_f32m1_m(...) __riscv_vluxseg7ei32_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_f32m1_m(...) __riscv_vluxseg8ei32_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_f32m2_m(...) __riscv_vluxseg2ei32_v_f32m2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_f32m2_m(...) __riscv_vluxseg3ei32_v_f32m2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_f32m2_m(...) __riscv_vluxseg4ei32_v_f32m2_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_f32m4_m(...) __riscv_vluxseg2ei32_v_f32m4_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_f32mf2_m(...) __riscv_vluxseg2ei64_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_f32mf2_m(...) __riscv_vluxseg3ei64_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_f32mf2_m(...) __riscv_vluxseg4ei64_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_f32mf2_m(...) __riscv_vluxseg5ei64_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_f32mf2_m(...) __riscv_vluxseg6ei64_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_f32mf2_m(...) __riscv_vluxseg7ei64_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_f32mf2_m(...) __riscv_vluxseg8ei64_v_f32mf2_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_f32m1_m(...) __riscv_vluxseg2ei64_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_f32m1_m(...) __riscv_vluxseg3ei64_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_f32m1_m(...) __riscv_vluxseg4ei64_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_f32m1_m(...) __riscv_vluxseg5ei64_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_f32m1_m(...) __riscv_vluxseg6ei64_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_f32m1_m(...) __riscv_vluxseg7ei64_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_f32m1_m(...) __riscv_vluxseg8ei64_v_f32m1_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_f32m2_m(...) __riscv_vluxseg2ei64_v_f32m2_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_f32m2_m(...) __riscv_vluxseg3ei64_v_f32m2_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_f32m2_m(...) __riscv_vluxseg4ei64_v_f32m2_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_f32m4_m(...) __riscv_vluxseg2ei64_v_f32m4_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_f64m1_m(...) __riscv_vluxseg2ei8_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_f64m1_m(...) __riscv_vluxseg3ei8_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_f64m1_m(...) __riscv_vluxseg4ei8_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_f64m1_m(...) __riscv_vluxseg5ei8_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_f64m1_m(...) __riscv_vluxseg6ei8_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_f64m1_m(...) __riscv_vluxseg7ei8_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_f64m1_m(...) __riscv_vluxseg8ei8_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_f64m2_m(...) __riscv_vluxseg2ei8_v_f64m2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_f64m2_m(...) __riscv_vluxseg3ei8_v_f64m2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_f64m2_m(...) __riscv_vluxseg4ei8_v_f64m2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_f64m4_m(...) __riscv_vluxseg2ei8_v_f64m4_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_f64m1_m(...) __riscv_vluxseg2ei16_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_f64m1_m(...) __riscv_vluxseg3ei16_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_f64m1_m(...) __riscv_vluxseg4ei16_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_f64m1_m(...) __riscv_vluxseg5ei16_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_f64m1_m(...) __riscv_vluxseg6ei16_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_f64m1_m(...) __riscv_vluxseg7ei16_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_f64m1_m(...) __riscv_vluxseg8ei16_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_f64m2_m(...) __riscv_vluxseg2ei16_v_f64m2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_f64m2_m(...) __riscv_vluxseg3ei16_v_f64m2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_f64m2_m(...) __riscv_vluxseg4ei16_v_f64m2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_f64m4_m(...) __riscv_vluxseg2ei16_v_f64m4_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_f64m1_m(...) __riscv_vluxseg2ei32_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_f64m1_m(...) __riscv_vluxseg3ei32_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_f64m1_m(...) __riscv_vluxseg4ei32_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_f64m1_m(...) __riscv_vluxseg5ei32_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_f64m1_m(...) __riscv_vluxseg6ei32_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_f64m1_m(...) __riscv_vluxseg7ei32_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_f64m1_m(...) __riscv_vluxseg8ei32_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_f64m2_m(...) __riscv_vluxseg2ei32_v_f64m2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_f64m2_m(...) __riscv_vluxseg3ei32_v_f64m2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_f64m2_m(...) __riscv_vluxseg4ei32_v_f64m2_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_f64m4_m(...) __riscv_vluxseg2ei32_v_f64m4_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_f64m1_m(...) __riscv_vluxseg2ei64_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_f64m1_m(...) __riscv_vluxseg3ei64_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_f64m1_m(...) __riscv_vluxseg4ei64_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_f64m1_m(...) __riscv_vluxseg5ei64_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_f64m1_m(...) __riscv_vluxseg6ei64_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_f64m1_m(...) __riscv_vluxseg7ei64_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_f64m1_m(...) __riscv_vluxseg8ei64_v_f64m1_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_f64m2_m(...) __riscv_vluxseg2ei64_v_f64m2_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_f64m2_m(...) __riscv_vluxseg3ei64_v_f64m2_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_f64m2_m(...) __riscv_vluxseg4ei64_v_f64m2_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_f64m4_m(...) __riscv_vluxseg2ei64_v_f64m4_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i8mf8_m(...) __riscv_vloxseg2ei8_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_i8mf8_m(...) __riscv_vloxseg3ei8_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_i8mf8_m(...) __riscv_vloxseg4ei8_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_i8mf8_m(...) __riscv_vloxseg5ei8_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_i8mf8_m(...) __riscv_vloxseg6ei8_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_i8mf8_m(...) __riscv_vloxseg7ei8_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_i8mf8_m(...) __riscv_vloxseg8ei8_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i8mf4_m(...) __riscv_vloxseg2ei8_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_i8mf4_m(...) __riscv_vloxseg3ei8_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_i8mf4_m(...) __riscv_vloxseg4ei8_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_i8mf4_m(...) __riscv_vloxseg5ei8_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_i8mf4_m(...) __riscv_vloxseg6ei8_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_i8mf4_m(...) __riscv_vloxseg7ei8_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_i8mf4_m(...) __riscv_vloxseg8ei8_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i8mf2_m(...) __riscv_vloxseg2ei8_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_i8mf2_m(...) __riscv_vloxseg3ei8_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_i8mf2_m(...) __riscv_vloxseg4ei8_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_i8mf2_m(...) __riscv_vloxseg5ei8_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_i8mf2_m(...) __riscv_vloxseg6ei8_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_i8mf2_m(...) __riscv_vloxseg7ei8_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_i8mf2_m(...) __riscv_vloxseg8ei8_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i8m1_m(...) __riscv_vloxseg2ei8_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_i8m1_m(...) __riscv_vloxseg3ei8_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_i8m1_m(...) __riscv_vloxseg4ei8_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_i8m1_m(...) __riscv_vloxseg5ei8_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_i8m1_m(...) __riscv_vloxseg6ei8_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_i8m1_m(...) __riscv_vloxseg7ei8_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_i8m1_m(...) __riscv_vloxseg8ei8_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i8m2_m(...) __riscv_vloxseg2ei8_v_i8m2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_i8m2_m(...) __riscv_vloxseg3ei8_v_i8m2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_i8m2_m(...) __riscv_vloxseg4ei8_v_i8m2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i8m4_m(...) __riscv_vloxseg2ei8_v_i8m4_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i8mf8_m(...) __riscv_vloxseg2ei16_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_i8mf8_m(...) __riscv_vloxseg3ei16_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_i8mf8_m(...) __riscv_vloxseg4ei16_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_i8mf8_m(...) __riscv_vloxseg5ei16_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_i8mf8_m(...) __riscv_vloxseg6ei16_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_i8mf8_m(...) __riscv_vloxseg7ei16_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_i8mf8_m(...) __riscv_vloxseg8ei16_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i8mf4_m(...) __riscv_vloxseg2ei16_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_i8mf4_m(...) __riscv_vloxseg3ei16_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_i8mf4_m(...) __riscv_vloxseg4ei16_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_i8mf4_m(...) __riscv_vloxseg5ei16_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_i8mf4_m(...) __riscv_vloxseg6ei16_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_i8mf4_m(...) __riscv_vloxseg7ei16_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_i8mf4_m(...) __riscv_vloxseg8ei16_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i8mf2_m(...) __riscv_vloxseg2ei16_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_i8mf2_m(...) __riscv_vloxseg3ei16_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_i8mf2_m(...) __riscv_vloxseg4ei16_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_i8mf2_m(...) __riscv_vloxseg5ei16_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_i8mf2_m(...) __riscv_vloxseg6ei16_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_i8mf2_m(...) __riscv_vloxseg7ei16_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_i8mf2_m(...) __riscv_vloxseg8ei16_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i8m1_m(...) __riscv_vloxseg2ei16_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_i8m1_m(...) __riscv_vloxseg3ei16_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_i8m1_m(...) __riscv_vloxseg4ei16_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_i8m1_m(...) __riscv_vloxseg5ei16_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_i8m1_m(...) __riscv_vloxseg6ei16_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_i8m1_m(...) __riscv_vloxseg7ei16_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_i8m1_m(...) __riscv_vloxseg8ei16_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i8m2_m(...) __riscv_vloxseg2ei16_v_i8m2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_i8m2_m(...) __riscv_vloxseg3ei16_v_i8m2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_i8m2_m(...) __riscv_vloxseg4ei16_v_i8m2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i8m4_m(...) __riscv_vloxseg2ei16_v_i8m4_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_i8mf8_m(...) __riscv_vloxseg2ei32_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_i8mf8_m(...) __riscv_vloxseg3ei32_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_i8mf8_m(...) __riscv_vloxseg4ei32_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_i8mf8_m(...) __riscv_vloxseg5ei32_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_i8mf8_m(...) __riscv_vloxseg6ei32_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_i8mf8_m(...) __riscv_vloxseg7ei32_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_i8mf8_m(...) __riscv_vloxseg8ei32_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_i8mf4_m(...) __riscv_vloxseg2ei32_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_i8mf4_m(...) __riscv_vloxseg3ei32_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_i8mf4_m(...) __riscv_vloxseg4ei32_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_i8mf4_m(...) __riscv_vloxseg5ei32_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_i8mf4_m(...) __riscv_vloxseg6ei32_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_i8mf4_m(...) __riscv_vloxseg7ei32_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_i8mf4_m(...) __riscv_vloxseg8ei32_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_i8mf2_m(...) __riscv_vloxseg2ei32_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_i8mf2_m(...) __riscv_vloxseg3ei32_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_i8mf2_m(...) __riscv_vloxseg4ei32_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_i8mf2_m(...) __riscv_vloxseg5ei32_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_i8mf2_m(...) __riscv_vloxseg6ei32_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_i8mf2_m(...) __riscv_vloxseg7ei32_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_i8mf2_m(...) __riscv_vloxseg8ei32_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_i8m1_m(...) __riscv_vloxseg2ei32_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_i8m1_m(...) __riscv_vloxseg3ei32_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_i8m1_m(...) __riscv_vloxseg4ei32_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_i8m1_m(...) __riscv_vloxseg5ei32_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_i8m1_m(...) __riscv_vloxseg6ei32_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_i8m1_m(...) __riscv_vloxseg7ei32_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_i8m1_m(...) __riscv_vloxseg8ei32_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_i8m2_m(...) __riscv_vloxseg2ei32_v_i8m2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_i8m2_m(...) __riscv_vloxseg3ei32_v_i8m2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_i8m2_m(...) __riscv_vloxseg4ei32_v_i8m2_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_i8mf8_m(...) __riscv_vloxseg2ei64_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_i8mf8_m(...) __riscv_vloxseg3ei64_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_i8mf8_m(...) __riscv_vloxseg4ei64_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_i8mf8_m(...) __riscv_vloxseg5ei64_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_i8mf8_m(...) __riscv_vloxseg6ei64_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_i8mf8_m(...) __riscv_vloxseg7ei64_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_i8mf8_m(...) __riscv_vloxseg8ei64_v_i8mf8_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_i8mf4_m(...) __riscv_vloxseg2ei64_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_i8mf4_m(...) __riscv_vloxseg3ei64_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_i8mf4_m(...) __riscv_vloxseg4ei64_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_i8mf4_m(...) __riscv_vloxseg5ei64_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_i8mf4_m(...) __riscv_vloxseg6ei64_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_i8mf4_m(...) __riscv_vloxseg7ei64_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_i8mf4_m(...) __riscv_vloxseg8ei64_v_i8mf4_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_i8mf2_m(...) __riscv_vloxseg2ei64_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_i8mf2_m(...) __riscv_vloxseg3ei64_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_i8mf2_m(...) __riscv_vloxseg4ei64_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_i8mf2_m(...) __riscv_vloxseg5ei64_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_i8mf2_m(...) __riscv_vloxseg6ei64_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_i8mf2_m(...) __riscv_vloxseg7ei64_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_i8mf2_m(...) __riscv_vloxseg8ei64_v_i8mf2_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_i8m1_m(...) __riscv_vloxseg2ei64_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_i8m1_m(...) __riscv_vloxseg3ei64_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_i8m1_m(...) __riscv_vloxseg4ei64_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_i8m1_m(...) __riscv_vloxseg5ei64_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_i8m1_m(...) __riscv_vloxseg6ei64_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_i8m1_m(...) __riscv_vloxseg7ei64_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_i8m1_m(...) __riscv_vloxseg8ei64_v_i8m1_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i16mf4_m(...) __riscv_vloxseg2ei8_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_i16mf4_m(...) __riscv_vloxseg3ei8_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_i16mf4_m(...) __riscv_vloxseg4ei8_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_i16mf4_m(...) __riscv_vloxseg5ei8_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_i16mf4_m(...) __riscv_vloxseg6ei8_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_i16mf4_m(...) __riscv_vloxseg7ei8_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_i16mf4_m(...) __riscv_vloxseg8ei8_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i16mf2_m(...) __riscv_vloxseg2ei8_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_i16mf2_m(...) __riscv_vloxseg3ei8_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_i16mf2_m(...) __riscv_vloxseg4ei8_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_i16mf2_m(...) __riscv_vloxseg5ei8_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_i16mf2_m(...) __riscv_vloxseg6ei8_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_i16mf2_m(...) __riscv_vloxseg7ei8_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_i16mf2_m(...) __riscv_vloxseg8ei8_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i16m1_m(...) __riscv_vloxseg2ei8_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_i16m1_m(...) __riscv_vloxseg3ei8_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_i16m1_m(...) __riscv_vloxseg4ei8_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_i16m1_m(...) __riscv_vloxseg5ei8_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_i16m1_m(...) __riscv_vloxseg6ei8_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_i16m1_m(...) __riscv_vloxseg7ei8_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_i16m1_m(...) __riscv_vloxseg8ei8_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i16m2_m(...) __riscv_vloxseg2ei8_v_i16m2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_i16m2_m(...) __riscv_vloxseg3ei8_v_i16m2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_i16m2_m(...) __riscv_vloxseg4ei8_v_i16m2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i16m4_m(...) __riscv_vloxseg2ei8_v_i16m4_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i16mf4_m(...) __riscv_vloxseg2ei16_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_i16mf4_m(...) __riscv_vloxseg3ei16_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_i16mf4_m(...) __riscv_vloxseg4ei16_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_i16mf4_m(...) __riscv_vloxseg5ei16_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_i16mf4_m(...) __riscv_vloxseg6ei16_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_i16mf4_m(...) __riscv_vloxseg7ei16_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_i16mf4_m(...) __riscv_vloxseg8ei16_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i16mf2_m(...) __riscv_vloxseg2ei16_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_i16mf2_m(...) __riscv_vloxseg3ei16_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_i16mf2_m(...) __riscv_vloxseg4ei16_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_i16mf2_m(...) __riscv_vloxseg5ei16_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_i16mf2_m(...) __riscv_vloxseg6ei16_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_i16mf2_m(...) __riscv_vloxseg7ei16_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_i16mf2_m(...) __riscv_vloxseg8ei16_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i16m1_m(...) __riscv_vloxseg2ei16_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_i16m1_m(...) __riscv_vloxseg3ei16_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_i16m1_m(...) __riscv_vloxseg4ei16_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_i16m1_m(...) __riscv_vloxseg5ei16_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_i16m1_m(...) __riscv_vloxseg6ei16_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_i16m1_m(...) __riscv_vloxseg7ei16_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_i16m1_m(...) __riscv_vloxseg8ei16_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i16m2_m(...) __riscv_vloxseg2ei16_v_i16m2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_i16m2_m(...) __riscv_vloxseg3ei16_v_i16m2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_i16m2_m(...) __riscv_vloxseg4ei16_v_i16m2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i16m4_m(...) __riscv_vloxseg2ei16_v_i16m4_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_i16mf4_m(...) __riscv_vloxseg2ei32_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_i16mf4_m(...) __riscv_vloxseg3ei32_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_i16mf4_m(...) __riscv_vloxseg4ei32_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_i16mf4_m(...) __riscv_vloxseg5ei32_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_i16mf4_m(...) __riscv_vloxseg6ei32_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_i16mf4_m(...) __riscv_vloxseg7ei32_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_i16mf4_m(...) __riscv_vloxseg8ei32_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_i16mf2_m(...) __riscv_vloxseg2ei32_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_i16mf2_m(...) __riscv_vloxseg3ei32_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_i16mf2_m(...) __riscv_vloxseg4ei32_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_i16mf2_m(...) __riscv_vloxseg5ei32_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_i16mf2_m(...) __riscv_vloxseg6ei32_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_i16mf2_m(...) __riscv_vloxseg7ei32_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_i16mf2_m(...) __riscv_vloxseg8ei32_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_i16m1_m(...) __riscv_vloxseg2ei32_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_i16m1_m(...) __riscv_vloxseg3ei32_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_i16m1_m(...) __riscv_vloxseg4ei32_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_i16m1_m(...) __riscv_vloxseg5ei32_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_i16m1_m(...) __riscv_vloxseg6ei32_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_i16m1_m(...) __riscv_vloxseg7ei32_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_i16m1_m(...) __riscv_vloxseg8ei32_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_i16m2_m(...) __riscv_vloxseg2ei32_v_i16m2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_i16m2_m(...) __riscv_vloxseg3ei32_v_i16m2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_i16m2_m(...) __riscv_vloxseg4ei32_v_i16m2_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_i16m4_m(...) __riscv_vloxseg2ei32_v_i16m4_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_i16mf4_m(...) __riscv_vloxseg2ei64_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_i16mf4_m(...) __riscv_vloxseg3ei64_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_i16mf4_m(...) __riscv_vloxseg4ei64_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_i16mf4_m(...) __riscv_vloxseg5ei64_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_i16mf4_m(...) __riscv_vloxseg6ei64_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_i16mf4_m(...) __riscv_vloxseg7ei64_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_i16mf4_m(...) __riscv_vloxseg8ei64_v_i16mf4_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_i16mf2_m(...) __riscv_vloxseg2ei64_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_i16mf2_m(...) __riscv_vloxseg3ei64_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_i16mf2_m(...) __riscv_vloxseg4ei64_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_i16mf2_m(...) __riscv_vloxseg5ei64_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_i16mf2_m(...) __riscv_vloxseg6ei64_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_i16mf2_m(...) __riscv_vloxseg7ei64_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_i16mf2_m(...) __riscv_vloxseg8ei64_v_i16mf2_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_i16m1_m(...) __riscv_vloxseg2ei64_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_i16m1_m(...) __riscv_vloxseg3ei64_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_i16m1_m(...) __riscv_vloxseg4ei64_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_i16m1_m(...) __riscv_vloxseg5ei64_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_i16m1_m(...) __riscv_vloxseg6ei64_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_i16m1_m(...) __riscv_vloxseg7ei64_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_i16m1_m(...) __riscv_vloxseg8ei64_v_i16m1_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_i16m2_m(...) __riscv_vloxseg2ei64_v_i16m2_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_i16m2_m(...) __riscv_vloxseg3ei64_v_i16m2_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_i16m2_m(...) __riscv_vloxseg4ei64_v_i16m2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i32mf2_m(...) __riscv_vloxseg2ei8_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_i32mf2_m(...) __riscv_vloxseg3ei8_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_i32mf2_m(...) __riscv_vloxseg4ei8_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_i32mf2_m(...) __riscv_vloxseg5ei8_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_i32mf2_m(...) __riscv_vloxseg6ei8_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_i32mf2_m(...) __riscv_vloxseg7ei8_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_i32mf2_m(...) __riscv_vloxseg8ei8_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i32m1_m(...) __riscv_vloxseg2ei8_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_i32m1_m(...) __riscv_vloxseg3ei8_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_i32m1_m(...) __riscv_vloxseg4ei8_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_i32m1_m(...) __riscv_vloxseg5ei8_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_i32m1_m(...) __riscv_vloxseg6ei8_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_i32m1_m(...) __riscv_vloxseg7ei8_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_i32m1_m(...) __riscv_vloxseg8ei8_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i32m2_m(...) __riscv_vloxseg2ei8_v_i32m2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_i32m2_m(...) __riscv_vloxseg3ei8_v_i32m2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_i32m2_m(...) __riscv_vloxseg4ei8_v_i32m2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i32m4_m(...) __riscv_vloxseg2ei8_v_i32m4_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i32mf2_m(...) __riscv_vloxseg2ei16_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_i32mf2_m(...) __riscv_vloxseg3ei16_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_i32mf2_m(...) __riscv_vloxseg4ei16_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_i32mf2_m(...) __riscv_vloxseg5ei16_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_i32mf2_m(...) __riscv_vloxseg6ei16_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_i32mf2_m(...) __riscv_vloxseg7ei16_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_i32mf2_m(...) __riscv_vloxseg8ei16_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i32m1_m(...) __riscv_vloxseg2ei16_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_i32m1_m(...) __riscv_vloxseg3ei16_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_i32m1_m(...) __riscv_vloxseg4ei16_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_i32m1_m(...) __riscv_vloxseg5ei16_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_i32m1_m(...) __riscv_vloxseg6ei16_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_i32m1_m(...) __riscv_vloxseg7ei16_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_i32m1_m(...) __riscv_vloxseg8ei16_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i32m2_m(...) __riscv_vloxseg2ei16_v_i32m2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_i32m2_m(...) __riscv_vloxseg3ei16_v_i32m2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_i32m2_m(...) __riscv_vloxseg4ei16_v_i32m2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i32m4_m(...) __riscv_vloxseg2ei16_v_i32m4_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_i32mf2_m(...) __riscv_vloxseg2ei32_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_i32mf2_m(...) __riscv_vloxseg3ei32_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_i32mf2_m(...) __riscv_vloxseg4ei32_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_i32mf2_m(...) __riscv_vloxseg5ei32_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_i32mf2_m(...) __riscv_vloxseg6ei32_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_i32mf2_m(...) __riscv_vloxseg7ei32_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_i32mf2_m(...) __riscv_vloxseg8ei32_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_i32m1_m(...) __riscv_vloxseg2ei32_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_i32m1_m(...) __riscv_vloxseg3ei32_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_i32m1_m(...) __riscv_vloxseg4ei32_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_i32m1_m(...) __riscv_vloxseg5ei32_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_i32m1_m(...) __riscv_vloxseg6ei32_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_i32m1_m(...) __riscv_vloxseg7ei32_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_i32m1_m(...) __riscv_vloxseg8ei32_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_i32m2_m(...) __riscv_vloxseg2ei32_v_i32m2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_i32m2_m(...) __riscv_vloxseg3ei32_v_i32m2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_i32m2_m(...) __riscv_vloxseg4ei32_v_i32m2_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_i32m4_m(...) __riscv_vloxseg2ei32_v_i32m4_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_i32mf2_m(...) __riscv_vloxseg2ei64_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_i32mf2_m(...) __riscv_vloxseg3ei64_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_i32mf2_m(...) __riscv_vloxseg4ei64_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_i32mf2_m(...) __riscv_vloxseg5ei64_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_i32mf2_m(...) __riscv_vloxseg6ei64_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_i32mf2_m(...) __riscv_vloxseg7ei64_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_i32mf2_m(...) __riscv_vloxseg8ei64_v_i32mf2_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_i32m1_m(...) __riscv_vloxseg2ei64_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_i32m1_m(...) __riscv_vloxseg3ei64_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_i32m1_m(...) __riscv_vloxseg4ei64_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_i32m1_m(...) __riscv_vloxseg5ei64_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_i32m1_m(...) __riscv_vloxseg6ei64_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_i32m1_m(...) __riscv_vloxseg7ei64_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_i32m1_m(...) __riscv_vloxseg8ei64_v_i32m1_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_i32m2_m(...) __riscv_vloxseg2ei64_v_i32m2_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_i32m2_m(...) __riscv_vloxseg3ei64_v_i32m2_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_i32m2_m(...) __riscv_vloxseg4ei64_v_i32m2_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_i32m4_m(...) __riscv_vloxseg2ei64_v_i32m4_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i64m1_m(...) __riscv_vloxseg2ei8_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_i64m1_m(...) __riscv_vloxseg3ei8_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_i64m1_m(...) __riscv_vloxseg4ei8_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_i64m1_m(...) __riscv_vloxseg5ei8_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_i64m1_m(...) __riscv_vloxseg6ei8_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_i64m1_m(...) __riscv_vloxseg7ei8_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_i64m1_m(...) __riscv_vloxseg8ei8_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i64m2_m(...) __riscv_vloxseg2ei8_v_i64m2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_i64m2_m(...) __riscv_vloxseg3ei8_v_i64m2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_i64m2_m(...) __riscv_vloxseg4ei8_v_i64m2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_i64m4_m(...) __riscv_vloxseg2ei8_v_i64m4_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i64m1_m(...) __riscv_vloxseg2ei16_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_i64m1_m(...) __riscv_vloxseg3ei16_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_i64m1_m(...) __riscv_vloxseg4ei16_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_i64m1_m(...) __riscv_vloxseg5ei16_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_i64m1_m(...) __riscv_vloxseg6ei16_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_i64m1_m(...) __riscv_vloxseg7ei16_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_i64m1_m(...) __riscv_vloxseg8ei16_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i64m2_m(...) __riscv_vloxseg2ei16_v_i64m2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_i64m2_m(...) __riscv_vloxseg3ei16_v_i64m2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_i64m2_m(...) __riscv_vloxseg4ei16_v_i64m2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_i64m4_m(...) __riscv_vloxseg2ei16_v_i64m4_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_i64m1_m(...) __riscv_vloxseg2ei32_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_i64m1_m(...) __riscv_vloxseg3ei32_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_i64m1_m(...) __riscv_vloxseg4ei32_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_i64m1_m(...) __riscv_vloxseg5ei32_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_i64m1_m(...) __riscv_vloxseg6ei32_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_i64m1_m(...) __riscv_vloxseg7ei32_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_i64m1_m(...) __riscv_vloxseg8ei32_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_i64m2_m(...) __riscv_vloxseg2ei32_v_i64m2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_i64m2_m(...) __riscv_vloxseg3ei32_v_i64m2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_i64m2_m(...) __riscv_vloxseg4ei32_v_i64m2_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_i64m4_m(...) __riscv_vloxseg2ei32_v_i64m4_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_i64m1_m(...) __riscv_vloxseg2ei64_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_i64m1_m(...) __riscv_vloxseg3ei64_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_i64m1_m(...) __riscv_vloxseg4ei64_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_i64m1_m(...) __riscv_vloxseg5ei64_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_i64m1_m(...) __riscv_vloxseg6ei64_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_i64m1_m(...) __riscv_vloxseg7ei64_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_i64m1_m(...) __riscv_vloxseg8ei64_v_i64m1_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_i64m2_m(...) __riscv_vloxseg2ei64_v_i64m2_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_i64m2_m(...) __riscv_vloxseg3ei64_v_i64m2_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_i64m2_m(...) __riscv_vloxseg4ei64_v_i64m2_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_i64m4_m(...) __riscv_vloxseg2ei64_v_i64m4_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i8mf8_m(...) __riscv_vluxseg2ei8_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_i8mf8_m(...) __riscv_vluxseg3ei8_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_i8mf8_m(...) __riscv_vluxseg4ei8_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_i8mf8_m(...) __riscv_vluxseg5ei8_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_i8mf8_m(...) __riscv_vluxseg6ei8_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_i8mf8_m(...) __riscv_vluxseg7ei8_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_i8mf8_m(...) __riscv_vluxseg8ei8_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i8mf4_m(...) __riscv_vluxseg2ei8_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_i8mf4_m(...) __riscv_vluxseg3ei8_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_i8mf4_m(...) __riscv_vluxseg4ei8_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_i8mf4_m(...) __riscv_vluxseg5ei8_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_i8mf4_m(...) __riscv_vluxseg6ei8_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_i8mf4_m(...) __riscv_vluxseg7ei8_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_i8mf4_m(...) __riscv_vluxseg8ei8_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i8mf2_m(...) __riscv_vluxseg2ei8_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_i8mf2_m(...) __riscv_vluxseg3ei8_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_i8mf2_m(...) __riscv_vluxseg4ei8_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_i8mf2_m(...) __riscv_vluxseg5ei8_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_i8mf2_m(...) __riscv_vluxseg6ei8_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_i8mf2_m(...) __riscv_vluxseg7ei8_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_i8mf2_m(...) __riscv_vluxseg8ei8_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i8m1_m(...) __riscv_vluxseg2ei8_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_i8m1_m(...) __riscv_vluxseg3ei8_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_i8m1_m(...) __riscv_vluxseg4ei8_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_i8m1_m(...) __riscv_vluxseg5ei8_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_i8m1_m(...) __riscv_vluxseg6ei8_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_i8m1_m(...) __riscv_vluxseg7ei8_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_i8m1_m(...) __riscv_vluxseg8ei8_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i8m2_m(...) __riscv_vluxseg2ei8_v_i8m2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_i8m2_m(...) __riscv_vluxseg3ei8_v_i8m2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_i8m2_m(...) __riscv_vluxseg4ei8_v_i8m2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i8m4_m(...) __riscv_vluxseg2ei8_v_i8m4_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i8mf8_m(...) __riscv_vluxseg2ei16_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_i8mf8_m(...) __riscv_vluxseg3ei16_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_i8mf8_m(...) __riscv_vluxseg4ei16_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_i8mf8_m(...) __riscv_vluxseg5ei16_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_i8mf8_m(...) __riscv_vluxseg6ei16_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_i8mf8_m(...) __riscv_vluxseg7ei16_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_i8mf8_m(...) __riscv_vluxseg8ei16_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i8mf4_m(...) __riscv_vluxseg2ei16_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_i8mf4_m(...) __riscv_vluxseg3ei16_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_i8mf4_m(...) __riscv_vluxseg4ei16_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_i8mf4_m(...) __riscv_vluxseg5ei16_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_i8mf4_m(...) __riscv_vluxseg6ei16_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_i8mf4_m(...) __riscv_vluxseg7ei16_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_i8mf4_m(...) __riscv_vluxseg8ei16_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i8mf2_m(...) __riscv_vluxseg2ei16_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_i8mf2_m(...) __riscv_vluxseg3ei16_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_i8mf2_m(...) __riscv_vluxseg4ei16_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_i8mf2_m(...) __riscv_vluxseg5ei16_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_i8mf2_m(...) __riscv_vluxseg6ei16_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_i8mf2_m(...) __riscv_vluxseg7ei16_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_i8mf2_m(...) __riscv_vluxseg8ei16_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i8m1_m(...) __riscv_vluxseg2ei16_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_i8m1_m(...) __riscv_vluxseg3ei16_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_i8m1_m(...) __riscv_vluxseg4ei16_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_i8m1_m(...) __riscv_vluxseg5ei16_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_i8m1_m(...) __riscv_vluxseg6ei16_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_i8m1_m(...) __riscv_vluxseg7ei16_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_i8m1_m(...) __riscv_vluxseg8ei16_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i8m2_m(...) __riscv_vluxseg2ei16_v_i8m2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_i8m2_m(...) __riscv_vluxseg3ei16_v_i8m2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_i8m2_m(...) __riscv_vluxseg4ei16_v_i8m2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i8m4_m(...) __riscv_vluxseg2ei16_v_i8m4_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_i8mf8_m(...) __riscv_vluxseg2ei32_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_i8mf8_m(...) __riscv_vluxseg3ei32_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_i8mf8_m(...) __riscv_vluxseg4ei32_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_i8mf8_m(...) __riscv_vluxseg5ei32_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_i8mf8_m(...) __riscv_vluxseg6ei32_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_i8mf8_m(...) __riscv_vluxseg7ei32_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_i8mf8_m(...) __riscv_vluxseg8ei32_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_i8mf4_m(...) __riscv_vluxseg2ei32_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_i8mf4_m(...) __riscv_vluxseg3ei32_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_i8mf4_m(...) __riscv_vluxseg4ei32_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_i8mf4_m(...) __riscv_vluxseg5ei32_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_i8mf4_m(...) __riscv_vluxseg6ei32_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_i8mf4_m(...) __riscv_vluxseg7ei32_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_i8mf4_m(...) __riscv_vluxseg8ei32_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_i8mf2_m(...) __riscv_vluxseg2ei32_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_i8mf2_m(...) __riscv_vluxseg3ei32_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_i8mf2_m(...) __riscv_vluxseg4ei32_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_i8mf2_m(...) __riscv_vluxseg5ei32_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_i8mf2_m(...) __riscv_vluxseg6ei32_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_i8mf2_m(...) __riscv_vluxseg7ei32_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_i8mf2_m(...) __riscv_vluxseg8ei32_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_i8m1_m(...) __riscv_vluxseg2ei32_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_i8m1_m(...) __riscv_vluxseg3ei32_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_i8m1_m(...) __riscv_vluxseg4ei32_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_i8m1_m(...) __riscv_vluxseg5ei32_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_i8m1_m(...) __riscv_vluxseg6ei32_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_i8m1_m(...) __riscv_vluxseg7ei32_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_i8m1_m(...) __riscv_vluxseg8ei32_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_i8m2_m(...) __riscv_vluxseg2ei32_v_i8m2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_i8m2_m(...) __riscv_vluxseg3ei32_v_i8m2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_i8m2_m(...) __riscv_vluxseg4ei32_v_i8m2_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_i8mf8_m(...) __riscv_vluxseg2ei64_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_i8mf8_m(...) __riscv_vluxseg3ei64_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_i8mf8_m(...) __riscv_vluxseg4ei64_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_i8mf8_m(...) __riscv_vluxseg5ei64_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_i8mf8_m(...) __riscv_vluxseg6ei64_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_i8mf8_m(...) __riscv_vluxseg7ei64_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_i8mf8_m(...) __riscv_vluxseg8ei64_v_i8mf8_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_i8mf4_m(...) __riscv_vluxseg2ei64_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_i8mf4_m(...) __riscv_vluxseg3ei64_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_i8mf4_m(...) __riscv_vluxseg4ei64_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_i8mf4_m(...) __riscv_vluxseg5ei64_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_i8mf4_m(...) __riscv_vluxseg6ei64_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_i8mf4_m(...) __riscv_vluxseg7ei64_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_i8mf4_m(...) __riscv_vluxseg8ei64_v_i8mf4_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_i8mf2_m(...) __riscv_vluxseg2ei64_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_i8mf2_m(...) __riscv_vluxseg3ei64_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_i8mf2_m(...) __riscv_vluxseg4ei64_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_i8mf2_m(...) __riscv_vluxseg5ei64_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_i8mf2_m(...) __riscv_vluxseg6ei64_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_i8mf2_m(...) __riscv_vluxseg7ei64_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_i8mf2_m(...) __riscv_vluxseg8ei64_v_i8mf2_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_i8m1_m(...) __riscv_vluxseg2ei64_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_i8m1_m(...) __riscv_vluxseg3ei64_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_i8m1_m(...) __riscv_vluxseg4ei64_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_i8m1_m(...) __riscv_vluxseg5ei64_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_i8m1_m(...) __riscv_vluxseg6ei64_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_i8m1_m(...) __riscv_vluxseg7ei64_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_i8m1_m(...) __riscv_vluxseg8ei64_v_i8m1_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i16mf4_m(...) __riscv_vluxseg2ei8_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_i16mf4_m(...) __riscv_vluxseg3ei8_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_i16mf4_m(...) __riscv_vluxseg4ei8_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_i16mf4_m(...) __riscv_vluxseg5ei8_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_i16mf4_m(...) __riscv_vluxseg6ei8_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_i16mf4_m(...) __riscv_vluxseg7ei8_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_i16mf4_m(...) __riscv_vluxseg8ei8_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i16mf2_m(...) __riscv_vluxseg2ei8_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_i16mf2_m(...) __riscv_vluxseg3ei8_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_i16mf2_m(...) __riscv_vluxseg4ei8_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_i16mf2_m(...) __riscv_vluxseg5ei8_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_i16mf2_m(...) __riscv_vluxseg6ei8_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_i16mf2_m(...) __riscv_vluxseg7ei8_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_i16mf2_m(...) __riscv_vluxseg8ei8_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i16m1_m(...) __riscv_vluxseg2ei8_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_i16m1_m(...) __riscv_vluxseg3ei8_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_i16m1_m(...) __riscv_vluxseg4ei8_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_i16m1_m(...) __riscv_vluxseg5ei8_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_i16m1_m(...) __riscv_vluxseg6ei8_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_i16m1_m(...) __riscv_vluxseg7ei8_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_i16m1_m(...) __riscv_vluxseg8ei8_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i16m2_m(...) __riscv_vluxseg2ei8_v_i16m2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_i16m2_m(...) __riscv_vluxseg3ei8_v_i16m2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_i16m2_m(...) __riscv_vluxseg4ei8_v_i16m2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i16m4_m(...) __riscv_vluxseg2ei8_v_i16m4_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i16mf4_m(...) __riscv_vluxseg2ei16_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_i16mf4_m(...) __riscv_vluxseg3ei16_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_i16mf4_m(...) __riscv_vluxseg4ei16_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_i16mf4_m(...) __riscv_vluxseg5ei16_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_i16mf4_m(...) __riscv_vluxseg6ei16_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_i16mf4_m(...) __riscv_vluxseg7ei16_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_i16mf4_m(...) __riscv_vluxseg8ei16_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i16mf2_m(...) __riscv_vluxseg2ei16_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_i16mf2_m(...) __riscv_vluxseg3ei16_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_i16mf2_m(...) __riscv_vluxseg4ei16_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_i16mf2_m(...) __riscv_vluxseg5ei16_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_i16mf2_m(...) __riscv_vluxseg6ei16_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_i16mf2_m(...) __riscv_vluxseg7ei16_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_i16mf2_m(...) __riscv_vluxseg8ei16_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i16m1_m(...) __riscv_vluxseg2ei16_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_i16m1_m(...) __riscv_vluxseg3ei16_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_i16m1_m(...) __riscv_vluxseg4ei16_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_i16m1_m(...) __riscv_vluxseg5ei16_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_i16m1_m(...) __riscv_vluxseg6ei16_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_i16m1_m(...) __riscv_vluxseg7ei16_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_i16m1_m(...) __riscv_vluxseg8ei16_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i16m2_m(...) __riscv_vluxseg2ei16_v_i16m2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_i16m2_m(...) __riscv_vluxseg3ei16_v_i16m2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_i16m2_m(...) __riscv_vluxseg4ei16_v_i16m2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i16m4_m(...) __riscv_vluxseg2ei16_v_i16m4_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_i16mf4_m(...) __riscv_vluxseg2ei32_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_i16mf4_m(...) __riscv_vluxseg3ei32_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_i16mf4_m(...) __riscv_vluxseg4ei32_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_i16mf4_m(...) __riscv_vluxseg5ei32_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_i16mf4_m(...) __riscv_vluxseg6ei32_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_i16mf4_m(...) __riscv_vluxseg7ei32_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_i16mf4_m(...) __riscv_vluxseg8ei32_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_i16mf2_m(...) __riscv_vluxseg2ei32_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_i16mf2_m(...) __riscv_vluxseg3ei32_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_i16mf2_m(...) __riscv_vluxseg4ei32_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_i16mf2_m(...) __riscv_vluxseg5ei32_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_i16mf2_m(...) __riscv_vluxseg6ei32_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_i16mf2_m(...) __riscv_vluxseg7ei32_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_i16mf2_m(...) __riscv_vluxseg8ei32_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_i16m1_m(...) __riscv_vluxseg2ei32_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_i16m1_m(...) __riscv_vluxseg3ei32_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_i16m1_m(...) __riscv_vluxseg4ei32_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_i16m1_m(...) __riscv_vluxseg5ei32_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_i16m1_m(...) __riscv_vluxseg6ei32_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_i16m1_m(...) __riscv_vluxseg7ei32_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_i16m1_m(...) __riscv_vluxseg8ei32_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_i16m2_m(...) __riscv_vluxseg2ei32_v_i16m2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_i16m2_m(...) __riscv_vluxseg3ei32_v_i16m2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_i16m2_m(...) __riscv_vluxseg4ei32_v_i16m2_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_i16m4_m(...) __riscv_vluxseg2ei32_v_i16m4_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_i16mf4_m(...) __riscv_vluxseg2ei64_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_i16mf4_m(...) __riscv_vluxseg3ei64_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_i16mf4_m(...) __riscv_vluxseg4ei64_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_i16mf4_m(...) __riscv_vluxseg5ei64_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_i16mf4_m(...) __riscv_vluxseg6ei64_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_i16mf4_m(...) __riscv_vluxseg7ei64_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_i16mf4_m(...) __riscv_vluxseg8ei64_v_i16mf4_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_i16mf2_m(...) __riscv_vluxseg2ei64_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_i16mf2_m(...) __riscv_vluxseg3ei64_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_i16mf2_m(...) __riscv_vluxseg4ei64_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_i16mf2_m(...) __riscv_vluxseg5ei64_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_i16mf2_m(...) __riscv_vluxseg6ei64_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_i16mf2_m(...) __riscv_vluxseg7ei64_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_i16mf2_m(...) __riscv_vluxseg8ei64_v_i16mf2_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_i16m1_m(...) __riscv_vluxseg2ei64_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_i16m1_m(...) __riscv_vluxseg3ei64_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_i16m1_m(...) __riscv_vluxseg4ei64_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_i16m1_m(...) __riscv_vluxseg5ei64_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_i16m1_m(...) __riscv_vluxseg6ei64_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_i16m1_m(...) __riscv_vluxseg7ei64_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_i16m1_m(...) __riscv_vluxseg8ei64_v_i16m1_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_i16m2_m(...) __riscv_vluxseg2ei64_v_i16m2_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_i16m2_m(...) __riscv_vluxseg3ei64_v_i16m2_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_i16m2_m(...) __riscv_vluxseg4ei64_v_i16m2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i32mf2_m(...) __riscv_vluxseg2ei8_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_i32mf2_m(...) __riscv_vluxseg3ei8_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_i32mf2_m(...) __riscv_vluxseg4ei8_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_i32mf2_m(...) __riscv_vluxseg5ei8_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_i32mf2_m(...) __riscv_vluxseg6ei8_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_i32mf2_m(...) __riscv_vluxseg7ei8_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_i32mf2_m(...) __riscv_vluxseg8ei8_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i32m1_m(...) __riscv_vluxseg2ei8_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_i32m1_m(...) __riscv_vluxseg3ei8_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_i32m1_m(...) __riscv_vluxseg4ei8_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_i32m1_m(...) __riscv_vluxseg5ei8_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_i32m1_m(...) __riscv_vluxseg6ei8_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_i32m1_m(...) __riscv_vluxseg7ei8_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_i32m1_m(...) __riscv_vluxseg8ei8_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i32m2_m(...) __riscv_vluxseg2ei8_v_i32m2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_i32m2_m(...) __riscv_vluxseg3ei8_v_i32m2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_i32m2_m(...) __riscv_vluxseg4ei8_v_i32m2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i32m4_m(...) __riscv_vluxseg2ei8_v_i32m4_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i32mf2_m(...) __riscv_vluxseg2ei16_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_i32mf2_m(...) __riscv_vluxseg3ei16_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_i32mf2_m(...) __riscv_vluxseg4ei16_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_i32mf2_m(...) __riscv_vluxseg5ei16_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_i32mf2_m(...) __riscv_vluxseg6ei16_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_i32mf2_m(...) __riscv_vluxseg7ei16_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_i32mf2_m(...) __riscv_vluxseg8ei16_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i32m1_m(...) __riscv_vluxseg2ei16_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_i32m1_m(...) __riscv_vluxseg3ei16_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_i32m1_m(...) __riscv_vluxseg4ei16_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_i32m1_m(...) __riscv_vluxseg5ei16_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_i32m1_m(...) __riscv_vluxseg6ei16_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_i32m1_m(...) __riscv_vluxseg7ei16_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_i32m1_m(...) __riscv_vluxseg8ei16_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i32m2_m(...) __riscv_vluxseg2ei16_v_i32m2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_i32m2_m(...) __riscv_vluxseg3ei16_v_i32m2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_i32m2_m(...) __riscv_vluxseg4ei16_v_i32m2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i32m4_m(...) __riscv_vluxseg2ei16_v_i32m4_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_i32mf2_m(...) __riscv_vluxseg2ei32_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_i32mf2_m(...) __riscv_vluxseg3ei32_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_i32mf2_m(...) __riscv_vluxseg4ei32_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_i32mf2_m(...) __riscv_vluxseg5ei32_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_i32mf2_m(...) __riscv_vluxseg6ei32_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_i32mf2_m(...) __riscv_vluxseg7ei32_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_i32mf2_m(...) __riscv_vluxseg8ei32_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_i32m1_m(...) __riscv_vluxseg2ei32_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_i32m1_m(...) __riscv_vluxseg3ei32_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_i32m1_m(...) __riscv_vluxseg4ei32_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_i32m1_m(...) __riscv_vluxseg5ei32_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_i32m1_m(...) __riscv_vluxseg6ei32_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_i32m1_m(...) __riscv_vluxseg7ei32_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_i32m1_m(...) __riscv_vluxseg8ei32_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_i32m2_m(...) __riscv_vluxseg2ei32_v_i32m2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_i32m2_m(...) __riscv_vluxseg3ei32_v_i32m2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_i32m2_m(...) __riscv_vluxseg4ei32_v_i32m2_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_i32m4_m(...) __riscv_vluxseg2ei32_v_i32m4_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_i32mf2_m(...) __riscv_vluxseg2ei64_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_i32mf2_m(...) __riscv_vluxseg3ei64_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_i32mf2_m(...) __riscv_vluxseg4ei64_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_i32mf2_m(...) __riscv_vluxseg5ei64_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_i32mf2_m(...) __riscv_vluxseg6ei64_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_i32mf2_m(...) __riscv_vluxseg7ei64_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_i32mf2_m(...) __riscv_vluxseg8ei64_v_i32mf2_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_i32m1_m(...) __riscv_vluxseg2ei64_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_i32m1_m(...) __riscv_vluxseg3ei64_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_i32m1_m(...) __riscv_vluxseg4ei64_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_i32m1_m(...) __riscv_vluxseg5ei64_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_i32m1_m(...) __riscv_vluxseg6ei64_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_i32m1_m(...) __riscv_vluxseg7ei64_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_i32m1_m(...) __riscv_vluxseg8ei64_v_i32m1_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_i32m2_m(...) __riscv_vluxseg2ei64_v_i32m2_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_i32m2_m(...) __riscv_vluxseg3ei64_v_i32m2_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_i32m2_m(...) __riscv_vluxseg4ei64_v_i32m2_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_i32m4_m(...) __riscv_vluxseg2ei64_v_i32m4_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i64m1_m(...) __riscv_vluxseg2ei8_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_i64m1_m(...) __riscv_vluxseg3ei8_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_i64m1_m(...) __riscv_vluxseg4ei8_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_i64m1_m(...) __riscv_vluxseg5ei8_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_i64m1_m(...) __riscv_vluxseg6ei8_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_i64m1_m(...) __riscv_vluxseg7ei8_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_i64m1_m(...) __riscv_vluxseg8ei8_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i64m2_m(...) __riscv_vluxseg2ei8_v_i64m2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_i64m2_m(...) __riscv_vluxseg3ei8_v_i64m2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_i64m2_m(...) __riscv_vluxseg4ei8_v_i64m2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_i64m4_m(...) __riscv_vluxseg2ei8_v_i64m4_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i64m1_m(...) __riscv_vluxseg2ei16_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_i64m1_m(...) __riscv_vluxseg3ei16_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_i64m1_m(...) __riscv_vluxseg4ei16_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_i64m1_m(...) __riscv_vluxseg5ei16_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_i64m1_m(...) __riscv_vluxseg6ei16_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_i64m1_m(...) __riscv_vluxseg7ei16_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_i64m1_m(...) __riscv_vluxseg8ei16_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i64m2_m(...) __riscv_vluxseg2ei16_v_i64m2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_i64m2_m(...) __riscv_vluxseg3ei16_v_i64m2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_i64m2_m(...) __riscv_vluxseg4ei16_v_i64m2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_i64m4_m(...) __riscv_vluxseg2ei16_v_i64m4_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_i64m1_m(...) __riscv_vluxseg2ei32_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_i64m1_m(...) __riscv_vluxseg3ei32_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_i64m1_m(...) __riscv_vluxseg4ei32_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_i64m1_m(...) __riscv_vluxseg5ei32_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_i64m1_m(...) __riscv_vluxseg6ei32_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_i64m1_m(...) __riscv_vluxseg7ei32_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_i64m1_m(...) __riscv_vluxseg8ei32_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_i64m2_m(...) __riscv_vluxseg2ei32_v_i64m2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_i64m2_m(...) __riscv_vluxseg3ei32_v_i64m2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_i64m2_m(...) __riscv_vluxseg4ei32_v_i64m2_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_i64m4_m(...) __riscv_vluxseg2ei32_v_i64m4_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_i64m1_m(...) __riscv_vluxseg2ei64_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_i64m1_m(...) __riscv_vluxseg3ei64_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_i64m1_m(...) __riscv_vluxseg4ei64_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_i64m1_m(...) __riscv_vluxseg5ei64_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_i64m1_m(...) __riscv_vluxseg6ei64_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_i64m1_m(...) __riscv_vluxseg7ei64_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_i64m1_m(...) __riscv_vluxseg8ei64_v_i64m1_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_i64m2_m(...) __riscv_vluxseg2ei64_v_i64m2_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_i64m2_m(...) __riscv_vluxseg3ei64_v_i64m2_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_i64m2_m(...) __riscv_vluxseg4ei64_v_i64m2_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_i64m4_m(...) __riscv_vluxseg2ei64_v_i64m4_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u8mf8_m(...) __riscv_vloxseg2ei8_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_u8mf8_m(...) __riscv_vloxseg3ei8_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_u8mf8_m(...) __riscv_vloxseg4ei8_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_u8mf8_m(...) __riscv_vloxseg5ei8_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_u8mf8_m(...) __riscv_vloxseg6ei8_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_u8mf8_m(...) __riscv_vloxseg7ei8_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_u8mf8_m(...) __riscv_vloxseg8ei8_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u8mf4_m(...) __riscv_vloxseg2ei8_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_u8mf4_m(...) __riscv_vloxseg3ei8_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_u8mf4_m(...) __riscv_vloxseg4ei8_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_u8mf4_m(...) __riscv_vloxseg5ei8_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_u8mf4_m(...) __riscv_vloxseg6ei8_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_u8mf4_m(...) __riscv_vloxseg7ei8_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_u8mf4_m(...) __riscv_vloxseg8ei8_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u8mf2_m(...) __riscv_vloxseg2ei8_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_u8mf2_m(...) __riscv_vloxseg3ei8_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_u8mf2_m(...) __riscv_vloxseg4ei8_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_u8mf2_m(...) __riscv_vloxseg5ei8_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_u8mf2_m(...) __riscv_vloxseg6ei8_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_u8mf2_m(...) __riscv_vloxseg7ei8_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_u8mf2_m(...) __riscv_vloxseg8ei8_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u8m1_m(...) __riscv_vloxseg2ei8_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_u8m1_m(...) __riscv_vloxseg3ei8_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_u8m1_m(...) __riscv_vloxseg4ei8_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_u8m1_m(...) __riscv_vloxseg5ei8_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_u8m1_m(...) __riscv_vloxseg6ei8_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_u8m1_m(...) __riscv_vloxseg7ei8_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_u8m1_m(...) __riscv_vloxseg8ei8_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u8m2_m(...) __riscv_vloxseg2ei8_v_u8m2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_u8m2_m(...) __riscv_vloxseg3ei8_v_u8m2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_u8m2_m(...) __riscv_vloxseg4ei8_v_u8m2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u8m4_m(...) __riscv_vloxseg2ei8_v_u8m4_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u8mf8_m(...) __riscv_vloxseg2ei16_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_u8mf8_m(...) __riscv_vloxseg3ei16_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_u8mf8_m(...) __riscv_vloxseg4ei16_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_u8mf8_m(...) __riscv_vloxseg5ei16_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_u8mf8_m(...) __riscv_vloxseg6ei16_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_u8mf8_m(...) __riscv_vloxseg7ei16_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_u8mf8_m(...) __riscv_vloxseg8ei16_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u8mf4_m(...) __riscv_vloxseg2ei16_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_u8mf4_m(...) __riscv_vloxseg3ei16_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_u8mf4_m(...) __riscv_vloxseg4ei16_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_u8mf4_m(...) __riscv_vloxseg5ei16_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_u8mf4_m(...) __riscv_vloxseg6ei16_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_u8mf4_m(...) __riscv_vloxseg7ei16_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_u8mf4_m(...) __riscv_vloxseg8ei16_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u8mf2_m(...) __riscv_vloxseg2ei16_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_u8mf2_m(...) __riscv_vloxseg3ei16_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_u8mf2_m(...) __riscv_vloxseg4ei16_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_u8mf2_m(...) __riscv_vloxseg5ei16_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_u8mf2_m(...) __riscv_vloxseg6ei16_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_u8mf2_m(...) __riscv_vloxseg7ei16_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_u8mf2_m(...) __riscv_vloxseg8ei16_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u8m1_m(...) __riscv_vloxseg2ei16_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_u8m1_m(...) __riscv_vloxseg3ei16_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_u8m1_m(...) __riscv_vloxseg4ei16_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_u8m1_m(...) __riscv_vloxseg5ei16_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_u8m1_m(...) __riscv_vloxseg6ei16_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_u8m1_m(...) __riscv_vloxseg7ei16_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_u8m1_m(...) __riscv_vloxseg8ei16_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u8m2_m(...) __riscv_vloxseg2ei16_v_u8m2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_u8m2_m(...) __riscv_vloxseg3ei16_v_u8m2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_u8m2_m(...) __riscv_vloxseg4ei16_v_u8m2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u8m4_m(...) __riscv_vloxseg2ei16_v_u8m4_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_u8mf8_m(...) __riscv_vloxseg2ei32_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_u8mf8_m(...) __riscv_vloxseg3ei32_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_u8mf8_m(...) __riscv_vloxseg4ei32_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_u8mf8_m(...) __riscv_vloxseg5ei32_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_u8mf8_m(...) __riscv_vloxseg6ei32_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_u8mf8_m(...) __riscv_vloxseg7ei32_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_u8mf8_m(...) __riscv_vloxseg8ei32_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_u8mf4_m(...) __riscv_vloxseg2ei32_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_u8mf4_m(...) __riscv_vloxseg3ei32_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_u8mf4_m(...) __riscv_vloxseg4ei32_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_u8mf4_m(...) __riscv_vloxseg5ei32_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_u8mf4_m(...) __riscv_vloxseg6ei32_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_u8mf4_m(...) __riscv_vloxseg7ei32_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_u8mf4_m(...) __riscv_vloxseg8ei32_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_u8mf2_m(...) __riscv_vloxseg2ei32_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_u8mf2_m(...) __riscv_vloxseg3ei32_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_u8mf2_m(...) __riscv_vloxseg4ei32_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_u8mf2_m(...) __riscv_vloxseg5ei32_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_u8mf2_m(...) __riscv_vloxseg6ei32_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_u8mf2_m(...) __riscv_vloxseg7ei32_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_u8mf2_m(...) __riscv_vloxseg8ei32_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_u8m1_m(...) __riscv_vloxseg2ei32_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_u8m1_m(...) __riscv_vloxseg3ei32_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_u8m1_m(...) __riscv_vloxseg4ei32_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_u8m1_m(...) __riscv_vloxseg5ei32_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_u8m1_m(...) __riscv_vloxseg6ei32_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_u8m1_m(...) __riscv_vloxseg7ei32_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_u8m1_m(...) __riscv_vloxseg8ei32_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_u8m2_m(...) __riscv_vloxseg2ei32_v_u8m2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_u8m2_m(...) __riscv_vloxseg3ei32_v_u8m2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_u8m2_m(...) __riscv_vloxseg4ei32_v_u8m2_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_u8mf8_m(...) __riscv_vloxseg2ei64_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_u8mf8_m(...) __riscv_vloxseg3ei64_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_u8mf8_m(...) __riscv_vloxseg4ei64_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_u8mf8_m(...) __riscv_vloxseg5ei64_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_u8mf8_m(...) __riscv_vloxseg6ei64_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_u8mf8_m(...) __riscv_vloxseg7ei64_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_u8mf8_m(...) __riscv_vloxseg8ei64_v_u8mf8_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_u8mf4_m(...) __riscv_vloxseg2ei64_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_u8mf4_m(...) __riscv_vloxseg3ei64_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_u8mf4_m(...) __riscv_vloxseg4ei64_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_u8mf4_m(...) __riscv_vloxseg5ei64_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_u8mf4_m(...) __riscv_vloxseg6ei64_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_u8mf4_m(...) __riscv_vloxseg7ei64_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_u8mf4_m(...) __riscv_vloxseg8ei64_v_u8mf4_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_u8mf2_m(...) __riscv_vloxseg2ei64_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_u8mf2_m(...) __riscv_vloxseg3ei64_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_u8mf2_m(...) __riscv_vloxseg4ei64_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_u8mf2_m(...) __riscv_vloxseg5ei64_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_u8mf2_m(...) __riscv_vloxseg6ei64_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_u8mf2_m(...) __riscv_vloxseg7ei64_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_u8mf2_m(...) __riscv_vloxseg8ei64_v_u8mf2_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_u8m1_m(...) __riscv_vloxseg2ei64_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_u8m1_m(...) __riscv_vloxseg3ei64_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_u8m1_m(...) __riscv_vloxseg4ei64_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_u8m1_m(...) __riscv_vloxseg5ei64_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_u8m1_m(...) __riscv_vloxseg6ei64_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_u8m1_m(...) __riscv_vloxseg7ei64_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_u8m1_m(...) __riscv_vloxseg8ei64_v_u8m1_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u16mf4_m(...) __riscv_vloxseg2ei8_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_u16mf4_m(...) __riscv_vloxseg3ei8_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_u16mf4_m(...) __riscv_vloxseg4ei8_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_u16mf4_m(...) __riscv_vloxseg5ei8_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_u16mf4_m(...) __riscv_vloxseg6ei8_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_u16mf4_m(...) __riscv_vloxseg7ei8_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_u16mf4_m(...) __riscv_vloxseg8ei8_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u16mf2_m(...) __riscv_vloxseg2ei8_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_u16mf2_m(...) __riscv_vloxseg3ei8_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_u16mf2_m(...) __riscv_vloxseg4ei8_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_u16mf2_m(...) __riscv_vloxseg5ei8_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_u16mf2_m(...) __riscv_vloxseg6ei8_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_u16mf2_m(...) __riscv_vloxseg7ei8_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_u16mf2_m(...) __riscv_vloxseg8ei8_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u16m1_m(...) __riscv_vloxseg2ei8_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_u16m1_m(...) __riscv_vloxseg3ei8_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_u16m1_m(...) __riscv_vloxseg4ei8_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_u16m1_m(...) __riscv_vloxseg5ei8_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_u16m1_m(...) __riscv_vloxseg6ei8_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_u16m1_m(...) __riscv_vloxseg7ei8_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_u16m1_m(...) __riscv_vloxseg8ei8_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u16m2_m(...) __riscv_vloxseg2ei8_v_u16m2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_u16m2_m(...) __riscv_vloxseg3ei8_v_u16m2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_u16m2_m(...) __riscv_vloxseg4ei8_v_u16m2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u16m4_m(...) __riscv_vloxseg2ei8_v_u16m4_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u16mf4_m(...) __riscv_vloxseg2ei16_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_u16mf4_m(...) __riscv_vloxseg3ei16_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_u16mf4_m(...) __riscv_vloxseg4ei16_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_u16mf4_m(...) __riscv_vloxseg5ei16_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_u16mf4_m(...) __riscv_vloxseg6ei16_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_u16mf4_m(...) __riscv_vloxseg7ei16_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_u16mf4_m(...) __riscv_vloxseg8ei16_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u16mf2_m(...) __riscv_vloxseg2ei16_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_u16mf2_m(...) __riscv_vloxseg3ei16_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_u16mf2_m(...) __riscv_vloxseg4ei16_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_u16mf2_m(...) __riscv_vloxseg5ei16_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_u16mf2_m(...) __riscv_vloxseg6ei16_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_u16mf2_m(...) __riscv_vloxseg7ei16_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_u16mf2_m(...) __riscv_vloxseg8ei16_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u16m1_m(...) __riscv_vloxseg2ei16_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_u16m1_m(...) __riscv_vloxseg3ei16_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_u16m1_m(...) __riscv_vloxseg4ei16_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_u16m1_m(...) __riscv_vloxseg5ei16_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_u16m1_m(...) __riscv_vloxseg6ei16_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_u16m1_m(...) __riscv_vloxseg7ei16_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_u16m1_m(...) __riscv_vloxseg8ei16_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u16m2_m(...) __riscv_vloxseg2ei16_v_u16m2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_u16m2_m(...) __riscv_vloxseg3ei16_v_u16m2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_u16m2_m(...) __riscv_vloxseg4ei16_v_u16m2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u16m4_m(...) __riscv_vloxseg2ei16_v_u16m4_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_u16mf4_m(...) __riscv_vloxseg2ei32_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_u16mf4_m(...) __riscv_vloxseg3ei32_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_u16mf4_m(...) __riscv_vloxseg4ei32_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_u16mf4_m(...) __riscv_vloxseg5ei32_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_u16mf4_m(...) __riscv_vloxseg6ei32_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_u16mf4_m(...) __riscv_vloxseg7ei32_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_u16mf4_m(...) __riscv_vloxseg8ei32_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_u16mf2_m(...) __riscv_vloxseg2ei32_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_u16mf2_m(...) __riscv_vloxseg3ei32_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_u16mf2_m(...) __riscv_vloxseg4ei32_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_u16mf2_m(...) __riscv_vloxseg5ei32_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_u16mf2_m(...) __riscv_vloxseg6ei32_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_u16mf2_m(...) __riscv_vloxseg7ei32_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_u16mf2_m(...) __riscv_vloxseg8ei32_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_u16m1_m(...) __riscv_vloxseg2ei32_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_u16m1_m(...) __riscv_vloxseg3ei32_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_u16m1_m(...) __riscv_vloxseg4ei32_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_u16m1_m(...) __riscv_vloxseg5ei32_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_u16m1_m(...) __riscv_vloxseg6ei32_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_u16m1_m(...) __riscv_vloxseg7ei32_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_u16m1_m(...) __riscv_vloxseg8ei32_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_u16m2_m(...) __riscv_vloxseg2ei32_v_u16m2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_u16m2_m(...) __riscv_vloxseg3ei32_v_u16m2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_u16m2_m(...) __riscv_vloxseg4ei32_v_u16m2_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_u16m4_m(...) __riscv_vloxseg2ei32_v_u16m4_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_u16mf4_m(...) __riscv_vloxseg2ei64_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_u16mf4_m(...) __riscv_vloxseg3ei64_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_u16mf4_m(...) __riscv_vloxseg4ei64_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_u16mf4_m(...) __riscv_vloxseg5ei64_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_u16mf4_m(...) __riscv_vloxseg6ei64_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_u16mf4_m(...) __riscv_vloxseg7ei64_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_u16mf4_m(...) __riscv_vloxseg8ei64_v_u16mf4_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_u16mf2_m(...) __riscv_vloxseg2ei64_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_u16mf2_m(...) __riscv_vloxseg3ei64_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_u16mf2_m(...) __riscv_vloxseg4ei64_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_u16mf2_m(...) __riscv_vloxseg5ei64_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_u16mf2_m(...) __riscv_vloxseg6ei64_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_u16mf2_m(...) __riscv_vloxseg7ei64_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_u16mf2_m(...) __riscv_vloxseg8ei64_v_u16mf2_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_u16m1_m(...) __riscv_vloxseg2ei64_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_u16m1_m(...) __riscv_vloxseg3ei64_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_u16m1_m(...) __riscv_vloxseg4ei64_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_u16m1_m(...) __riscv_vloxseg5ei64_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_u16m1_m(...) __riscv_vloxseg6ei64_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_u16m1_m(...) __riscv_vloxseg7ei64_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_u16m1_m(...) __riscv_vloxseg8ei64_v_u16m1_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_u16m2_m(...) __riscv_vloxseg2ei64_v_u16m2_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_u16m2_m(...) __riscv_vloxseg3ei64_v_u16m2_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_u16m2_m(...) __riscv_vloxseg4ei64_v_u16m2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u32mf2_m(...) __riscv_vloxseg2ei8_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_u32mf2_m(...) __riscv_vloxseg3ei8_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_u32mf2_m(...) __riscv_vloxseg4ei8_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_u32mf2_m(...) __riscv_vloxseg5ei8_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_u32mf2_m(...) __riscv_vloxseg6ei8_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_u32mf2_m(...) __riscv_vloxseg7ei8_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_u32mf2_m(...) __riscv_vloxseg8ei8_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u32m1_m(...) __riscv_vloxseg2ei8_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_u32m1_m(...) __riscv_vloxseg3ei8_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_u32m1_m(...) __riscv_vloxseg4ei8_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_u32m1_m(...) __riscv_vloxseg5ei8_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_u32m1_m(...) __riscv_vloxseg6ei8_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_u32m1_m(...) __riscv_vloxseg7ei8_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_u32m1_m(...) __riscv_vloxseg8ei8_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u32m2_m(...) __riscv_vloxseg2ei8_v_u32m2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_u32m2_m(...) __riscv_vloxseg3ei8_v_u32m2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_u32m2_m(...) __riscv_vloxseg4ei8_v_u32m2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u32m4_m(...) __riscv_vloxseg2ei8_v_u32m4_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u32mf2_m(...) __riscv_vloxseg2ei16_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_u32mf2_m(...) __riscv_vloxseg3ei16_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_u32mf2_m(...) __riscv_vloxseg4ei16_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_u32mf2_m(...) __riscv_vloxseg5ei16_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_u32mf2_m(...) __riscv_vloxseg6ei16_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_u32mf2_m(...) __riscv_vloxseg7ei16_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_u32mf2_m(...) __riscv_vloxseg8ei16_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u32m1_m(...) __riscv_vloxseg2ei16_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_u32m1_m(...) __riscv_vloxseg3ei16_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_u32m1_m(...) __riscv_vloxseg4ei16_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_u32m1_m(...) __riscv_vloxseg5ei16_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_u32m1_m(...) __riscv_vloxseg6ei16_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_u32m1_m(...) __riscv_vloxseg7ei16_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_u32m1_m(...) __riscv_vloxseg8ei16_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u32m2_m(...) __riscv_vloxseg2ei16_v_u32m2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_u32m2_m(...) __riscv_vloxseg3ei16_v_u32m2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_u32m2_m(...) __riscv_vloxseg4ei16_v_u32m2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u32m4_m(...) __riscv_vloxseg2ei16_v_u32m4_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_u32mf2_m(...) __riscv_vloxseg2ei32_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_u32mf2_m(...) __riscv_vloxseg3ei32_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_u32mf2_m(...) __riscv_vloxseg4ei32_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_u32mf2_m(...) __riscv_vloxseg5ei32_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_u32mf2_m(...) __riscv_vloxseg6ei32_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_u32mf2_m(...) __riscv_vloxseg7ei32_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_u32mf2_m(...) __riscv_vloxseg8ei32_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_u32m1_m(...) __riscv_vloxseg2ei32_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_u32m1_m(...) __riscv_vloxseg3ei32_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_u32m1_m(...) __riscv_vloxseg4ei32_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_u32m1_m(...) __riscv_vloxseg5ei32_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_u32m1_m(...) __riscv_vloxseg6ei32_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_u32m1_m(...) __riscv_vloxseg7ei32_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_u32m1_m(...) __riscv_vloxseg8ei32_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_u32m2_m(...) __riscv_vloxseg2ei32_v_u32m2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_u32m2_m(...) __riscv_vloxseg3ei32_v_u32m2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_u32m2_m(...) __riscv_vloxseg4ei32_v_u32m2_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_u32m4_m(...) __riscv_vloxseg2ei32_v_u32m4_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_u32mf2_m(...) __riscv_vloxseg2ei64_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_u32mf2_m(...) __riscv_vloxseg3ei64_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_u32mf2_m(...) __riscv_vloxseg4ei64_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_u32mf2_m(...) __riscv_vloxseg5ei64_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_u32mf2_m(...) __riscv_vloxseg6ei64_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_u32mf2_m(...) __riscv_vloxseg7ei64_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_u32mf2_m(...) __riscv_vloxseg8ei64_v_u32mf2_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_u32m1_m(...) __riscv_vloxseg2ei64_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_u32m1_m(...) __riscv_vloxseg3ei64_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_u32m1_m(...) __riscv_vloxseg4ei64_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_u32m1_m(...) __riscv_vloxseg5ei64_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_u32m1_m(...) __riscv_vloxseg6ei64_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_u32m1_m(...) __riscv_vloxseg7ei64_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_u32m1_m(...) __riscv_vloxseg8ei64_v_u32m1_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_u32m2_m(...) __riscv_vloxseg2ei64_v_u32m2_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_u32m2_m(...) __riscv_vloxseg3ei64_v_u32m2_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_u32m2_m(...) __riscv_vloxseg4ei64_v_u32m2_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_u32m4_m(...) __riscv_vloxseg2ei64_v_u32m4_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u64m1_m(...) __riscv_vloxseg2ei8_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_u64m1_m(...) __riscv_vloxseg3ei8_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_u64m1_m(...) __riscv_vloxseg4ei8_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg5ei8_v_u64m1_m(...) __riscv_vloxseg5ei8_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg6ei8_v_u64m1_m(...) __riscv_vloxseg6ei8_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg7ei8_v_u64m1_m(...) __riscv_vloxseg7ei8_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg8ei8_v_u64m1_m(...) __riscv_vloxseg8ei8_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u64m2_m(...) __riscv_vloxseg2ei8_v_u64m2_tumu(__VA_ARGS__) -#define vloxseg3ei8_v_u64m2_m(...) __riscv_vloxseg3ei8_v_u64m2_tumu(__VA_ARGS__) -#define vloxseg4ei8_v_u64m2_m(...) __riscv_vloxseg4ei8_v_u64m2_tumu(__VA_ARGS__) -#define vloxseg2ei8_v_u64m4_m(...) __riscv_vloxseg2ei8_v_u64m4_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u64m1_m(...) __riscv_vloxseg2ei16_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_u64m1_m(...) __riscv_vloxseg3ei16_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_u64m1_m(...) __riscv_vloxseg4ei16_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg5ei16_v_u64m1_m(...) __riscv_vloxseg5ei16_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg6ei16_v_u64m1_m(...) __riscv_vloxseg6ei16_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg7ei16_v_u64m1_m(...) __riscv_vloxseg7ei16_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg8ei16_v_u64m1_m(...) __riscv_vloxseg8ei16_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u64m2_m(...) __riscv_vloxseg2ei16_v_u64m2_tumu(__VA_ARGS__) -#define vloxseg3ei16_v_u64m2_m(...) __riscv_vloxseg3ei16_v_u64m2_tumu(__VA_ARGS__) -#define vloxseg4ei16_v_u64m2_m(...) __riscv_vloxseg4ei16_v_u64m2_tumu(__VA_ARGS__) -#define vloxseg2ei16_v_u64m4_m(...) __riscv_vloxseg2ei16_v_u64m4_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_u64m1_m(...) __riscv_vloxseg2ei32_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_u64m1_m(...) __riscv_vloxseg3ei32_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_u64m1_m(...) __riscv_vloxseg4ei32_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg5ei32_v_u64m1_m(...) __riscv_vloxseg5ei32_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg6ei32_v_u64m1_m(...) __riscv_vloxseg6ei32_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg7ei32_v_u64m1_m(...) __riscv_vloxseg7ei32_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg8ei32_v_u64m1_m(...) __riscv_vloxseg8ei32_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_u64m2_m(...) __riscv_vloxseg2ei32_v_u64m2_tumu(__VA_ARGS__) -#define vloxseg3ei32_v_u64m2_m(...) __riscv_vloxseg3ei32_v_u64m2_tumu(__VA_ARGS__) -#define vloxseg4ei32_v_u64m2_m(...) __riscv_vloxseg4ei32_v_u64m2_tumu(__VA_ARGS__) -#define vloxseg2ei32_v_u64m4_m(...) __riscv_vloxseg2ei32_v_u64m4_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_u64m1_m(...) __riscv_vloxseg2ei64_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_u64m1_m(...) __riscv_vloxseg3ei64_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_u64m1_m(...) __riscv_vloxseg4ei64_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg5ei64_v_u64m1_m(...) __riscv_vloxseg5ei64_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg6ei64_v_u64m1_m(...) __riscv_vloxseg6ei64_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg7ei64_v_u64m1_m(...) __riscv_vloxseg7ei64_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg8ei64_v_u64m1_m(...) __riscv_vloxseg8ei64_v_u64m1_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_u64m2_m(...) __riscv_vloxseg2ei64_v_u64m2_tumu(__VA_ARGS__) -#define vloxseg3ei64_v_u64m2_m(...) __riscv_vloxseg3ei64_v_u64m2_tumu(__VA_ARGS__) -#define vloxseg4ei64_v_u64m2_m(...) __riscv_vloxseg4ei64_v_u64m2_tumu(__VA_ARGS__) -#define vloxseg2ei64_v_u64m4_m(...) __riscv_vloxseg2ei64_v_u64m4_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u8mf8_m(...) __riscv_vluxseg2ei8_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_u8mf8_m(...) __riscv_vluxseg3ei8_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_u8mf8_m(...) __riscv_vluxseg4ei8_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_u8mf8_m(...) __riscv_vluxseg5ei8_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_u8mf8_m(...) __riscv_vluxseg6ei8_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_u8mf8_m(...) __riscv_vluxseg7ei8_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_u8mf8_m(...) __riscv_vluxseg8ei8_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u8mf4_m(...) __riscv_vluxseg2ei8_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_u8mf4_m(...) __riscv_vluxseg3ei8_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_u8mf4_m(...) __riscv_vluxseg4ei8_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_u8mf4_m(...) __riscv_vluxseg5ei8_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_u8mf4_m(...) __riscv_vluxseg6ei8_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_u8mf4_m(...) __riscv_vluxseg7ei8_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_u8mf4_m(...) __riscv_vluxseg8ei8_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u8mf2_m(...) __riscv_vluxseg2ei8_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_u8mf2_m(...) __riscv_vluxseg3ei8_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_u8mf2_m(...) __riscv_vluxseg4ei8_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_u8mf2_m(...) __riscv_vluxseg5ei8_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_u8mf2_m(...) __riscv_vluxseg6ei8_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_u8mf2_m(...) __riscv_vluxseg7ei8_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_u8mf2_m(...) __riscv_vluxseg8ei8_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u8m1_m(...) __riscv_vluxseg2ei8_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_u8m1_m(...) __riscv_vluxseg3ei8_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_u8m1_m(...) __riscv_vluxseg4ei8_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_u8m1_m(...) __riscv_vluxseg5ei8_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_u8m1_m(...) __riscv_vluxseg6ei8_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_u8m1_m(...) __riscv_vluxseg7ei8_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_u8m1_m(...) __riscv_vluxseg8ei8_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u8m2_m(...) __riscv_vluxseg2ei8_v_u8m2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_u8m2_m(...) __riscv_vluxseg3ei8_v_u8m2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_u8m2_m(...) __riscv_vluxseg4ei8_v_u8m2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u8m4_m(...) __riscv_vluxseg2ei8_v_u8m4_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u8mf8_m(...) __riscv_vluxseg2ei16_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_u8mf8_m(...) __riscv_vluxseg3ei16_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_u8mf8_m(...) __riscv_vluxseg4ei16_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_u8mf8_m(...) __riscv_vluxseg5ei16_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_u8mf8_m(...) __riscv_vluxseg6ei16_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_u8mf8_m(...) __riscv_vluxseg7ei16_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_u8mf8_m(...) __riscv_vluxseg8ei16_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u8mf4_m(...) __riscv_vluxseg2ei16_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_u8mf4_m(...) __riscv_vluxseg3ei16_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_u8mf4_m(...) __riscv_vluxseg4ei16_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_u8mf4_m(...) __riscv_vluxseg5ei16_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_u8mf4_m(...) __riscv_vluxseg6ei16_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_u8mf4_m(...) __riscv_vluxseg7ei16_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_u8mf4_m(...) __riscv_vluxseg8ei16_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u8mf2_m(...) __riscv_vluxseg2ei16_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_u8mf2_m(...) __riscv_vluxseg3ei16_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_u8mf2_m(...) __riscv_vluxseg4ei16_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_u8mf2_m(...) __riscv_vluxseg5ei16_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_u8mf2_m(...) __riscv_vluxseg6ei16_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_u8mf2_m(...) __riscv_vluxseg7ei16_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_u8mf2_m(...) __riscv_vluxseg8ei16_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u8m1_m(...) __riscv_vluxseg2ei16_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_u8m1_m(...) __riscv_vluxseg3ei16_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_u8m1_m(...) __riscv_vluxseg4ei16_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_u8m1_m(...) __riscv_vluxseg5ei16_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_u8m1_m(...) __riscv_vluxseg6ei16_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_u8m1_m(...) __riscv_vluxseg7ei16_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_u8m1_m(...) __riscv_vluxseg8ei16_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u8m2_m(...) __riscv_vluxseg2ei16_v_u8m2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_u8m2_m(...) __riscv_vluxseg3ei16_v_u8m2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_u8m2_m(...) __riscv_vluxseg4ei16_v_u8m2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u8m4_m(...) __riscv_vluxseg2ei16_v_u8m4_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_u8mf8_m(...) __riscv_vluxseg2ei32_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_u8mf8_m(...) __riscv_vluxseg3ei32_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_u8mf8_m(...) __riscv_vluxseg4ei32_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_u8mf8_m(...) __riscv_vluxseg5ei32_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_u8mf8_m(...) __riscv_vluxseg6ei32_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_u8mf8_m(...) __riscv_vluxseg7ei32_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_u8mf8_m(...) __riscv_vluxseg8ei32_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_u8mf4_m(...) __riscv_vluxseg2ei32_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_u8mf4_m(...) __riscv_vluxseg3ei32_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_u8mf4_m(...) __riscv_vluxseg4ei32_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_u8mf4_m(...) __riscv_vluxseg5ei32_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_u8mf4_m(...) __riscv_vluxseg6ei32_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_u8mf4_m(...) __riscv_vluxseg7ei32_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_u8mf4_m(...) __riscv_vluxseg8ei32_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_u8mf2_m(...) __riscv_vluxseg2ei32_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_u8mf2_m(...) __riscv_vluxseg3ei32_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_u8mf2_m(...) __riscv_vluxseg4ei32_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_u8mf2_m(...) __riscv_vluxseg5ei32_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_u8mf2_m(...) __riscv_vluxseg6ei32_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_u8mf2_m(...) __riscv_vluxseg7ei32_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_u8mf2_m(...) __riscv_vluxseg8ei32_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_u8m1_m(...) __riscv_vluxseg2ei32_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_u8m1_m(...) __riscv_vluxseg3ei32_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_u8m1_m(...) __riscv_vluxseg4ei32_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_u8m1_m(...) __riscv_vluxseg5ei32_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_u8m1_m(...) __riscv_vluxseg6ei32_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_u8m1_m(...) __riscv_vluxseg7ei32_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_u8m1_m(...) __riscv_vluxseg8ei32_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_u8m2_m(...) __riscv_vluxseg2ei32_v_u8m2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_u8m2_m(...) __riscv_vluxseg3ei32_v_u8m2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_u8m2_m(...) __riscv_vluxseg4ei32_v_u8m2_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_u8mf8_m(...) __riscv_vluxseg2ei64_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_u8mf8_m(...) __riscv_vluxseg3ei64_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_u8mf8_m(...) __riscv_vluxseg4ei64_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_u8mf8_m(...) __riscv_vluxseg5ei64_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_u8mf8_m(...) __riscv_vluxseg6ei64_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_u8mf8_m(...) __riscv_vluxseg7ei64_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_u8mf8_m(...) __riscv_vluxseg8ei64_v_u8mf8_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_u8mf4_m(...) __riscv_vluxseg2ei64_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_u8mf4_m(...) __riscv_vluxseg3ei64_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_u8mf4_m(...) __riscv_vluxseg4ei64_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_u8mf4_m(...) __riscv_vluxseg5ei64_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_u8mf4_m(...) __riscv_vluxseg6ei64_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_u8mf4_m(...) __riscv_vluxseg7ei64_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_u8mf4_m(...) __riscv_vluxseg8ei64_v_u8mf4_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_u8mf2_m(...) __riscv_vluxseg2ei64_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_u8mf2_m(...) __riscv_vluxseg3ei64_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_u8mf2_m(...) __riscv_vluxseg4ei64_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_u8mf2_m(...) __riscv_vluxseg5ei64_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_u8mf2_m(...) __riscv_vluxseg6ei64_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_u8mf2_m(...) __riscv_vluxseg7ei64_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_u8mf2_m(...) __riscv_vluxseg8ei64_v_u8mf2_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_u8m1_m(...) __riscv_vluxseg2ei64_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_u8m1_m(...) __riscv_vluxseg3ei64_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_u8m1_m(...) __riscv_vluxseg4ei64_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_u8m1_m(...) __riscv_vluxseg5ei64_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_u8m1_m(...) __riscv_vluxseg6ei64_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_u8m1_m(...) __riscv_vluxseg7ei64_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_u8m1_m(...) __riscv_vluxseg8ei64_v_u8m1_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u16mf4_m(...) __riscv_vluxseg2ei8_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_u16mf4_m(...) __riscv_vluxseg3ei8_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_u16mf4_m(...) __riscv_vluxseg4ei8_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_u16mf4_m(...) __riscv_vluxseg5ei8_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_u16mf4_m(...) __riscv_vluxseg6ei8_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_u16mf4_m(...) __riscv_vluxseg7ei8_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_u16mf4_m(...) __riscv_vluxseg8ei8_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u16mf2_m(...) __riscv_vluxseg2ei8_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_u16mf2_m(...) __riscv_vluxseg3ei8_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_u16mf2_m(...) __riscv_vluxseg4ei8_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_u16mf2_m(...) __riscv_vluxseg5ei8_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_u16mf2_m(...) __riscv_vluxseg6ei8_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_u16mf2_m(...) __riscv_vluxseg7ei8_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_u16mf2_m(...) __riscv_vluxseg8ei8_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u16m1_m(...) __riscv_vluxseg2ei8_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_u16m1_m(...) __riscv_vluxseg3ei8_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_u16m1_m(...) __riscv_vluxseg4ei8_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_u16m1_m(...) __riscv_vluxseg5ei8_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_u16m1_m(...) __riscv_vluxseg6ei8_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_u16m1_m(...) __riscv_vluxseg7ei8_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_u16m1_m(...) __riscv_vluxseg8ei8_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u16m2_m(...) __riscv_vluxseg2ei8_v_u16m2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_u16m2_m(...) __riscv_vluxseg3ei8_v_u16m2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_u16m2_m(...) __riscv_vluxseg4ei8_v_u16m2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u16m4_m(...) __riscv_vluxseg2ei8_v_u16m4_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u16mf4_m(...) __riscv_vluxseg2ei16_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_u16mf4_m(...) __riscv_vluxseg3ei16_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_u16mf4_m(...) __riscv_vluxseg4ei16_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_u16mf4_m(...) __riscv_vluxseg5ei16_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_u16mf4_m(...) __riscv_vluxseg6ei16_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_u16mf4_m(...) __riscv_vluxseg7ei16_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_u16mf4_m(...) __riscv_vluxseg8ei16_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u16mf2_m(...) __riscv_vluxseg2ei16_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_u16mf2_m(...) __riscv_vluxseg3ei16_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_u16mf2_m(...) __riscv_vluxseg4ei16_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_u16mf2_m(...) __riscv_vluxseg5ei16_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_u16mf2_m(...) __riscv_vluxseg6ei16_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_u16mf2_m(...) __riscv_vluxseg7ei16_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_u16mf2_m(...) __riscv_vluxseg8ei16_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u16m1_m(...) __riscv_vluxseg2ei16_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_u16m1_m(...) __riscv_vluxseg3ei16_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_u16m1_m(...) __riscv_vluxseg4ei16_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_u16m1_m(...) __riscv_vluxseg5ei16_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_u16m1_m(...) __riscv_vluxseg6ei16_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_u16m1_m(...) __riscv_vluxseg7ei16_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_u16m1_m(...) __riscv_vluxseg8ei16_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u16m2_m(...) __riscv_vluxseg2ei16_v_u16m2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_u16m2_m(...) __riscv_vluxseg3ei16_v_u16m2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_u16m2_m(...) __riscv_vluxseg4ei16_v_u16m2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u16m4_m(...) __riscv_vluxseg2ei16_v_u16m4_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_u16mf4_m(...) __riscv_vluxseg2ei32_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_u16mf4_m(...) __riscv_vluxseg3ei32_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_u16mf4_m(...) __riscv_vluxseg4ei32_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_u16mf4_m(...) __riscv_vluxseg5ei32_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_u16mf4_m(...) __riscv_vluxseg6ei32_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_u16mf4_m(...) __riscv_vluxseg7ei32_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_u16mf4_m(...) __riscv_vluxseg8ei32_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_u16mf2_m(...) __riscv_vluxseg2ei32_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_u16mf2_m(...) __riscv_vluxseg3ei32_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_u16mf2_m(...) __riscv_vluxseg4ei32_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_u16mf2_m(...) __riscv_vluxseg5ei32_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_u16mf2_m(...) __riscv_vluxseg6ei32_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_u16mf2_m(...) __riscv_vluxseg7ei32_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_u16mf2_m(...) __riscv_vluxseg8ei32_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_u16m1_m(...) __riscv_vluxseg2ei32_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_u16m1_m(...) __riscv_vluxseg3ei32_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_u16m1_m(...) __riscv_vluxseg4ei32_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_u16m1_m(...) __riscv_vluxseg5ei32_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_u16m1_m(...) __riscv_vluxseg6ei32_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_u16m1_m(...) __riscv_vluxseg7ei32_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_u16m1_m(...) __riscv_vluxseg8ei32_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_u16m2_m(...) __riscv_vluxseg2ei32_v_u16m2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_u16m2_m(...) __riscv_vluxseg3ei32_v_u16m2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_u16m2_m(...) __riscv_vluxseg4ei32_v_u16m2_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_u16m4_m(...) __riscv_vluxseg2ei32_v_u16m4_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_u16mf4_m(...) __riscv_vluxseg2ei64_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_u16mf4_m(...) __riscv_vluxseg3ei64_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_u16mf4_m(...) __riscv_vluxseg4ei64_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_u16mf4_m(...) __riscv_vluxseg5ei64_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_u16mf4_m(...) __riscv_vluxseg6ei64_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_u16mf4_m(...) __riscv_vluxseg7ei64_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_u16mf4_m(...) __riscv_vluxseg8ei64_v_u16mf4_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_u16mf2_m(...) __riscv_vluxseg2ei64_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_u16mf2_m(...) __riscv_vluxseg3ei64_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_u16mf2_m(...) __riscv_vluxseg4ei64_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_u16mf2_m(...) __riscv_vluxseg5ei64_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_u16mf2_m(...) __riscv_vluxseg6ei64_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_u16mf2_m(...) __riscv_vluxseg7ei64_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_u16mf2_m(...) __riscv_vluxseg8ei64_v_u16mf2_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_u16m1_m(...) __riscv_vluxseg2ei64_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_u16m1_m(...) __riscv_vluxseg3ei64_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_u16m1_m(...) __riscv_vluxseg4ei64_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_u16m1_m(...) __riscv_vluxseg5ei64_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_u16m1_m(...) __riscv_vluxseg6ei64_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_u16m1_m(...) __riscv_vluxseg7ei64_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_u16m1_m(...) __riscv_vluxseg8ei64_v_u16m1_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_u16m2_m(...) __riscv_vluxseg2ei64_v_u16m2_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_u16m2_m(...) __riscv_vluxseg3ei64_v_u16m2_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_u16m2_m(...) __riscv_vluxseg4ei64_v_u16m2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u32mf2_m(...) __riscv_vluxseg2ei8_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_u32mf2_m(...) __riscv_vluxseg3ei8_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_u32mf2_m(...) __riscv_vluxseg4ei8_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_u32mf2_m(...) __riscv_vluxseg5ei8_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_u32mf2_m(...) __riscv_vluxseg6ei8_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_u32mf2_m(...) __riscv_vluxseg7ei8_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_u32mf2_m(...) __riscv_vluxseg8ei8_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u32m1_m(...) __riscv_vluxseg2ei8_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_u32m1_m(...) __riscv_vluxseg3ei8_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_u32m1_m(...) __riscv_vluxseg4ei8_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_u32m1_m(...) __riscv_vluxseg5ei8_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_u32m1_m(...) __riscv_vluxseg6ei8_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_u32m1_m(...) __riscv_vluxseg7ei8_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_u32m1_m(...) __riscv_vluxseg8ei8_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u32m2_m(...) __riscv_vluxseg2ei8_v_u32m2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_u32m2_m(...) __riscv_vluxseg3ei8_v_u32m2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_u32m2_m(...) __riscv_vluxseg4ei8_v_u32m2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u32m4_m(...) __riscv_vluxseg2ei8_v_u32m4_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u32mf2_m(...) __riscv_vluxseg2ei16_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_u32mf2_m(...) __riscv_vluxseg3ei16_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_u32mf2_m(...) __riscv_vluxseg4ei16_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_u32mf2_m(...) __riscv_vluxseg5ei16_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_u32mf2_m(...) __riscv_vluxseg6ei16_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_u32mf2_m(...) __riscv_vluxseg7ei16_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_u32mf2_m(...) __riscv_vluxseg8ei16_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u32m1_m(...) __riscv_vluxseg2ei16_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_u32m1_m(...) __riscv_vluxseg3ei16_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_u32m1_m(...) __riscv_vluxseg4ei16_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_u32m1_m(...) __riscv_vluxseg5ei16_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_u32m1_m(...) __riscv_vluxseg6ei16_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_u32m1_m(...) __riscv_vluxseg7ei16_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_u32m1_m(...) __riscv_vluxseg8ei16_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u32m2_m(...) __riscv_vluxseg2ei16_v_u32m2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_u32m2_m(...) __riscv_vluxseg3ei16_v_u32m2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_u32m2_m(...) __riscv_vluxseg4ei16_v_u32m2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u32m4_m(...) __riscv_vluxseg2ei16_v_u32m4_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_u32mf2_m(...) __riscv_vluxseg2ei32_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_u32mf2_m(...) __riscv_vluxseg3ei32_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_u32mf2_m(...) __riscv_vluxseg4ei32_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_u32mf2_m(...) __riscv_vluxseg5ei32_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_u32mf2_m(...) __riscv_vluxseg6ei32_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_u32mf2_m(...) __riscv_vluxseg7ei32_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_u32mf2_m(...) __riscv_vluxseg8ei32_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_u32m1_m(...) __riscv_vluxseg2ei32_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_u32m1_m(...) __riscv_vluxseg3ei32_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_u32m1_m(...) __riscv_vluxseg4ei32_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_u32m1_m(...) __riscv_vluxseg5ei32_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_u32m1_m(...) __riscv_vluxseg6ei32_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_u32m1_m(...) __riscv_vluxseg7ei32_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_u32m1_m(...) __riscv_vluxseg8ei32_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_u32m2_m(...) __riscv_vluxseg2ei32_v_u32m2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_u32m2_m(...) __riscv_vluxseg3ei32_v_u32m2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_u32m2_m(...) __riscv_vluxseg4ei32_v_u32m2_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_u32m4_m(...) __riscv_vluxseg2ei32_v_u32m4_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_u32mf2_m(...) __riscv_vluxseg2ei64_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_u32mf2_m(...) __riscv_vluxseg3ei64_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_u32mf2_m(...) __riscv_vluxseg4ei64_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_u32mf2_m(...) __riscv_vluxseg5ei64_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_u32mf2_m(...) __riscv_vluxseg6ei64_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_u32mf2_m(...) __riscv_vluxseg7ei64_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_u32mf2_m(...) __riscv_vluxseg8ei64_v_u32mf2_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_u32m1_m(...) __riscv_vluxseg2ei64_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_u32m1_m(...) __riscv_vluxseg3ei64_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_u32m1_m(...) __riscv_vluxseg4ei64_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_u32m1_m(...) __riscv_vluxseg5ei64_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_u32m1_m(...) __riscv_vluxseg6ei64_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_u32m1_m(...) __riscv_vluxseg7ei64_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_u32m1_m(...) __riscv_vluxseg8ei64_v_u32m1_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_u32m2_m(...) __riscv_vluxseg2ei64_v_u32m2_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_u32m2_m(...) __riscv_vluxseg3ei64_v_u32m2_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_u32m2_m(...) __riscv_vluxseg4ei64_v_u32m2_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_u32m4_m(...) __riscv_vluxseg2ei64_v_u32m4_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u64m1_m(...) __riscv_vluxseg2ei8_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_u64m1_m(...) __riscv_vluxseg3ei8_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_u64m1_m(...) __riscv_vluxseg4ei8_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg5ei8_v_u64m1_m(...) __riscv_vluxseg5ei8_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg6ei8_v_u64m1_m(...) __riscv_vluxseg6ei8_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg7ei8_v_u64m1_m(...) __riscv_vluxseg7ei8_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg8ei8_v_u64m1_m(...) __riscv_vluxseg8ei8_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u64m2_m(...) __riscv_vluxseg2ei8_v_u64m2_tumu(__VA_ARGS__) -#define vluxseg3ei8_v_u64m2_m(...) __riscv_vluxseg3ei8_v_u64m2_tumu(__VA_ARGS__) -#define vluxseg4ei8_v_u64m2_m(...) __riscv_vluxseg4ei8_v_u64m2_tumu(__VA_ARGS__) -#define vluxseg2ei8_v_u64m4_m(...) __riscv_vluxseg2ei8_v_u64m4_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u64m1_m(...) __riscv_vluxseg2ei16_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_u64m1_m(...) __riscv_vluxseg3ei16_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_u64m1_m(...) __riscv_vluxseg4ei16_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg5ei16_v_u64m1_m(...) __riscv_vluxseg5ei16_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg6ei16_v_u64m1_m(...) __riscv_vluxseg6ei16_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg7ei16_v_u64m1_m(...) __riscv_vluxseg7ei16_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg8ei16_v_u64m1_m(...) __riscv_vluxseg8ei16_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u64m2_m(...) __riscv_vluxseg2ei16_v_u64m2_tumu(__VA_ARGS__) -#define vluxseg3ei16_v_u64m2_m(...) __riscv_vluxseg3ei16_v_u64m2_tumu(__VA_ARGS__) -#define vluxseg4ei16_v_u64m2_m(...) __riscv_vluxseg4ei16_v_u64m2_tumu(__VA_ARGS__) -#define vluxseg2ei16_v_u64m4_m(...) __riscv_vluxseg2ei16_v_u64m4_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_u64m1_m(...) __riscv_vluxseg2ei32_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_u64m1_m(...) __riscv_vluxseg3ei32_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_u64m1_m(...) __riscv_vluxseg4ei32_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg5ei32_v_u64m1_m(...) __riscv_vluxseg5ei32_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg6ei32_v_u64m1_m(...) __riscv_vluxseg6ei32_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg7ei32_v_u64m1_m(...) __riscv_vluxseg7ei32_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg8ei32_v_u64m1_m(...) __riscv_vluxseg8ei32_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_u64m2_m(...) __riscv_vluxseg2ei32_v_u64m2_tumu(__VA_ARGS__) -#define vluxseg3ei32_v_u64m2_m(...) __riscv_vluxseg3ei32_v_u64m2_tumu(__VA_ARGS__) -#define vluxseg4ei32_v_u64m2_m(...) __riscv_vluxseg4ei32_v_u64m2_tumu(__VA_ARGS__) -#define vluxseg2ei32_v_u64m4_m(...) __riscv_vluxseg2ei32_v_u64m4_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_u64m1_m(...) __riscv_vluxseg2ei64_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_u64m1_m(...) __riscv_vluxseg3ei64_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_u64m1_m(...) __riscv_vluxseg4ei64_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg5ei64_v_u64m1_m(...) __riscv_vluxseg5ei64_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg6ei64_v_u64m1_m(...) __riscv_vluxseg6ei64_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg7ei64_v_u64m1_m(...) __riscv_vluxseg7ei64_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg8ei64_v_u64m1_m(...) __riscv_vluxseg8ei64_v_u64m1_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_u64m2_m(...) __riscv_vluxseg2ei64_v_u64m2_tumu(__VA_ARGS__) -#define vluxseg3ei64_v_u64m2_m(...) __riscv_vluxseg3ei64_v_u64m2_tumu(__VA_ARGS__) -#define vluxseg4ei64_v_u64m2_m(...) __riscv_vluxseg4ei64_v_u64m2_tumu(__VA_ARGS__) -#define vluxseg2ei64_v_u64m4_m(...) __riscv_vluxseg2ei64_v_u64m4_tumu(__VA_ARGS__) -#define vsoxseg2ei8_v_f16mf4(...) __riscv_vsoxseg2ei8_v_f16mf4(__VA_ARGS__) -#define vsoxseg3ei8_v_f16mf4(...) __riscv_vsoxseg3ei8_v_f16mf4(__VA_ARGS__) -#define vsoxseg4ei8_v_f16mf4(...) __riscv_vsoxseg4ei8_v_f16mf4(__VA_ARGS__) -#define vsoxseg5ei8_v_f16mf4(...) __riscv_vsoxseg5ei8_v_f16mf4(__VA_ARGS__) -#define vsoxseg6ei8_v_f16mf4(...) __riscv_vsoxseg6ei8_v_f16mf4(__VA_ARGS__) -#define vsoxseg7ei8_v_f16mf4(...) __riscv_vsoxseg7ei8_v_f16mf4(__VA_ARGS__) -#define vsoxseg8ei8_v_f16mf4(...) __riscv_vsoxseg8ei8_v_f16mf4(__VA_ARGS__) -#define vsoxseg2ei8_v_f16mf2(...) __riscv_vsoxseg2ei8_v_f16mf2(__VA_ARGS__) -#define vsoxseg3ei8_v_f16mf2(...) __riscv_vsoxseg3ei8_v_f16mf2(__VA_ARGS__) -#define vsoxseg4ei8_v_f16mf2(...) __riscv_vsoxseg4ei8_v_f16mf2(__VA_ARGS__) -#define vsoxseg5ei8_v_f16mf2(...) __riscv_vsoxseg5ei8_v_f16mf2(__VA_ARGS__) -#define vsoxseg6ei8_v_f16mf2(...) __riscv_vsoxseg6ei8_v_f16mf2(__VA_ARGS__) -#define vsoxseg7ei8_v_f16mf2(...) __riscv_vsoxseg7ei8_v_f16mf2(__VA_ARGS__) -#define vsoxseg8ei8_v_f16mf2(...) __riscv_vsoxseg8ei8_v_f16mf2(__VA_ARGS__) -#define vsoxseg2ei8_v_f16m1(...) __riscv_vsoxseg2ei8_v_f16m1(__VA_ARGS__) -#define vsoxseg3ei8_v_f16m1(...) __riscv_vsoxseg3ei8_v_f16m1(__VA_ARGS__) -#define vsoxseg4ei8_v_f16m1(...) __riscv_vsoxseg4ei8_v_f16m1(__VA_ARGS__) -#define vsoxseg5ei8_v_f16m1(...) __riscv_vsoxseg5ei8_v_f16m1(__VA_ARGS__) -#define vsoxseg6ei8_v_f16m1(...) __riscv_vsoxseg6ei8_v_f16m1(__VA_ARGS__) -#define vsoxseg7ei8_v_f16m1(...) __riscv_vsoxseg7ei8_v_f16m1(__VA_ARGS__) -#define vsoxseg8ei8_v_f16m1(...) __riscv_vsoxseg8ei8_v_f16m1(__VA_ARGS__) -#define vsoxseg2ei8_v_f16m2(...) __riscv_vsoxseg2ei8_v_f16m2(__VA_ARGS__) -#define vsoxseg3ei8_v_f16m2(...) __riscv_vsoxseg3ei8_v_f16m2(__VA_ARGS__) -#define vsoxseg4ei8_v_f16m2(...) __riscv_vsoxseg4ei8_v_f16m2(__VA_ARGS__) -#define vsoxseg2ei8_v_f16m4(...) __riscv_vsoxseg2ei8_v_f16m4(__VA_ARGS__) -#define vsoxseg2ei16_v_f16mf4(...) __riscv_vsoxseg2ei16_v_f16mf4(__VA_ARGS__) -#define vsoxseg3ei16_v_f16mf4(...) __riscv_vsoxseg3ei16_v_f16mf4(__VA_ARGS__) -#define vsoxseg4ei16_v_f16mf4(...) __riscv_vsoxseg4ei16_v_f16mf4(__VA_ARGS__) -#define vsoxseg5ei16_v_f16mf4(...) __riscv_vsoxseg5ei16_v_f16mf4(__VA_ARGS__) -#define vsoxseg6ei16_v_f16mf4(...) __riscv_vsoxseg6ei16_v_f16mf4(__VA_ARGS__) -#define vsoxseg7ei16_v_f16mf4(...) __riscv_vsoxseg7ei16_v_f16mf4(__VA_ARGS__) -#define vsoxseg8ei16_v_f16mf4(...) __riscv_vsoxseg8ei16_v_f16mf4(__VA_ARGS__) -#define vsoxseg2ei16_v_f16mf2(...) __riscv_vsoxseg2ei16_v_f16mf2(__VA_ARGS__) -#define vsoxseg3ei16_v_f16mf2(...) __riscv_vsoxseg3ei16_v_f16mf2(__VA_ARGS__) -#define vsoxseg4ei16_v_f16mf2(...) __riscv_vsoxseg4ei16_v_f16mf2(__VA_ARGS__) -#define vsoxseg5ei16_v_f16mf2(...) __riscv_vsoxseg5ei16_v_f16mf2(__VA_ARGS__) -#define vsoxseg6ei16_v_f16mf2(...) __riscv_vsoxseg6ei16_v_f16mf2(__VA_ARGS__) -#define vsoxseg7ei16_v_f16mf2(...) __riscv_vsoxseg7ei16_v_f16mf2(__VA_ARGS__) -#define vsoxseg8ei16_v_f16mf2(...) __riscv_vsoxseg8ei16_v_f16mf2(__VA_ARGS__) -#define vsoxseg2ei16_v_f16m1(...) __riscv_vsoxseg2ei16_v_f16m1(__VA_ARGS__) -#define vsoxseg3ei16_v_f16m1(...) __riscv_vsoxseg3ei16_v_f16m1(__VA_ARGS__) -#define vsoxseg4ei16_v_f16m1(...) __riscv_vsoxseg4ei16_v_f16m1(__VA_ARGS__) -#define vsoxseg5ei16_v_f16m1(...) __riscv_vsoxseg5ei16_v_f16m1(__VA_ARGS__) -#define vsoxseg6ei16_v_f16m1(...) __riscv_vsoxseg6ei16_v_f16m1(__VA_ARGS__) -#define vsoxseg7ei16_v_f16m1(...) __riscv_vsoxseg7ei16_v_f16m1(__VA_ARGS__) -#define vsoxseg8ei16_v_f16m1(...) __riscv_vsoxseg8ei16_v_f16m1(__VA_ARGS__) -#define vsoxseg2ei16_v_f16m2(...) __riscv_vsoxseg2ei16_v_f16m2(__VA_ARGS__) -#define vsoxseg3ei16_v_f16m2(...) __riscv_vsoxseg3ei16_v_f16m2(__VA_ARGS__) -#define vsoxseg4ei16_v_f16m2(...) __riscv_vsoxseg4ei16_v_f16m2(__VA_ARGS__) -#define vsoxseg2ei16_v_f16m4(...) __riscv_vsoxseg2ei16_v_f16m4(__VA_ARGS__) -#define vsoxseg2ei32_v_f16mf4(...) __riscv_vsoxseg2ei32_v_f16mf4(__VA_ARGS__) -#define vsoxseg3ei32_v_f16mf4(...) __riscv_vsoxseg3ei32_v_f16mf4(__VA_ARGS__) -#define vsoxseg4ei32_v_f16mf4(...) __riscv_vsoxseg4ei32_v_f16mf4(__VA_ARGS__) -#define vsoxseg5ei32_v_f16mf4(...) __riscv_vsoxseg5ei32_v_f16mf4(__VA_ARGS__) -#define vsoxseg6ei32_v_f16mf4(...) __riscv_vsoxseg6ei32_v_f16mf4(__VA_ARGS__) -#define vsoxseg7ei32_v_f16mf4(...) __riscv_vsoxseg7ei32_v_f16mf4(__VA_ARGS__) -#define vsoxseg8ei32_v_f16mf4(...) __riscv_vsoxseg8ei32_v_f16mf4(__VA_ARGS__) -#define vsoxseg2ei32_v_f16mf2(...) __riscv_vsoxseg2ei32_v_f16mf2(__VA_ARGS__) -#define vsoxseg3ei32_v_f16mf2(...) __riscv_vsoxseg3ei32_v_f16mf2(__VA_ARGS__) -#define vsoxseg4ei32_v_f16mf2(...) __riscv_vsoxseg4ei32_v_f16mf2(__VA_ARGS__) -#define vsoxseg5ei32_v_f16mf2(...) __riscv_vsoxseg5ei32_v_f16mf2(__VA_ARGS__) -#define vsoxseg6ei32_v_f16mf2(...) __riscv_vsoxseg6ei32_v_f16mf2(__VA_ARGS__) -#define vsoxseg7ei32_v_f16mf2(...) __riscv_vsoxseg7ei32_v_f16mf2(__VA_ARGS__) -#define vsoxseg8ei32_v_f16mf2(...) __riscv_vsoxseg8ei32_v_f16mf2(__VA_ARGS__) -#define vsoxseg2ei32_v_f16m1(...) __riscv_vsoxseg2ei32_v_f16m1(__VA_ARGS__) -#define vsoxseg3ei32_v_f16m1(...) __riscv_vsoxseg3ei32_v_f16m1(__VA_ARGS__) -#define vsoxseg4ei32_v_f16m1(...) __riscv_vsoxseg4ei32_v_f16m1(__VA_ARGS__) -#define vsoxseg5ei32_v_f16m1(...) __riscv_vsoxseg5ei32_v_f16m1(__VA_ARGS__) -#define vsoxseg6ei32_v_f16m1(...) __riscv_vsoxseg6ei32_v_f16m1(__VA_ARGS__) -#define vsoxseg7ei32_v_f16m1(...) __riscv_vsoxseg7ei32_v_f16m1(__VA_ARGS__) -#define vsoxseg8ei32_v_f16m1(...) __riscv_vsoxseg8ei32_v_f16m1(__VA_ARGS__) -#define vsoxseg2ei32_v_f16m2(...) __riscv_vsoxseg2ei32_v_f16m2(__VA_ARGS__) -#define vsoxseg3ei32_v_f16m2(...) __riscv_vsoxseg3ei32_v_f16m2(__VA_ARGS__) -#define vsoxseg4ei32_v_f16m2(...) __riscv_vsoxseg4ei32_v_f16m2(__VA_ARGS__) -#define vsoxseg2ei32_v_f16m4(...) __riscv_vsoxseg2ei32_v_f16m4(__VA_ARGS__) -#define vsoxseg2ei64_v_f16mf4(...) __riscv_vsoxseg2ei64_v_f16mf4(__VA_ARGS__) -#define vsoxseg3ei64_v_f16mf4(...) __riscv_vsoxseg3ei64_v_f16mf4(__VA_ARGS__) -#define vsoxseg4ei64_v_f16mf4(...) __riscv_vsoxseg4ei64_v_f16mf4(__VA_ARGS__) -#define vsoxseg5ei64_v_f16mf4(...) __riscv_vsoxseg5ei64_v_f16mf4(__VA_ARGS__) -#define vsoxseg6ei64_v_f16mf4(...) __riscv_vsoxseg6ei64_v_f16mf4(__VA_ARGS__) -#define vsoxseg7ei64_v_f16mf4(...) __riscv_vsoxseg7ei64_v_f16mf4(__VA_ARGS__) -#define vsoxseg8ei64_v_f16mf4(...) __riscv_vsoxseg8ei64_v_f16mf4(__VA_ARGS__) -#define vsoxseg2ei64_v_f16mf2(...) __riscv_vsoxseg2ei64_v_f16mf2(__VA_ARGS__) -#define vsoxseg3ei64_v_f16mf2(...) __riscv_vsoxseg3ei64_v_f16mf2(__VA_ARGS__) -#define vsoxseg4ei64_v_f16mf2(...) __riscv_vsoxseg4ei64_v_f16mf2(__VA_ARGS__) -#define vsoxseg5ei64_v_f16mf2(...) __riscv_vsoxseg5ei64_v_f16mf2(__VA_ARGS__) -#define vsoxseg6ei64_v_f16mf2(...) __riscv_vsoxseg6ei64_v_f16mf2(__VA_ARGS__) -#define vsoxseg7ei64_v_f16mf2(...) __riscv_vsoxseg7ei64_v_f16mf2(__VA_ARGS__) -#define vsoxseg8ei64_v_f16mf2(...) __riscv_vsoxseg8ei64_v_f16mf2(__VA_ARGS__) -#define vsoxseg2ei64_v_f16m1(...) __riscv_vsoxseg2ei64_v_f16m1(__VA_ARGS__) -#define vsoxseg3ei64_v_f16m1(...) __riscv_vsoxseg3ei64_v_f16m1(__VA_ARGS__) -#define vsoxseg4ei64_v_f16m1(...) __riscv_vsoxseg4ei64_v_f16m1(__VA_ARGS__) -#define vsoxseg5ei64_v_f16m1(...) __riscv_vsoxseg5ei64_v_f16m1(__VA_ARGS__) -#define vsoxseg6ei64_v_f16m1(...) __riscv_vsoxseg6ei64_v_f16m1(__VA_ARGS__) -#define vsoxseg7ei64_v_f16m1(...) __riscv_vsoxseg7ei64_v_f16m1(__VA_ARGS__) -#define vsoxseg8ei64_v_f16m1(...) __riscv_vsoxseg8ei64_v_f16m1(__VA_ARGS__) -#define vsoxseg2ei64_v_f16m2(...) __riscv_vsoxseg2ei64_v_f16m2(__VA_ARGS__) -#define vsoxseg3ei64_v_f16m2(...) __riscv_vsoxseg3ei64_v_f16m2(__VA_ARGS__) -#define vsoxseg4ei64_v_f16m2(...) __riscv_vsoxseg4ei64_v_f16m2(__VA_ARGS__) -#define vsoxseg2ei8_v_f32mf2(...) __riscv_vsoxseg2ei8_v_f32mf2(__VA_ARGS__) -#define vsoxseg3ei8_v_f32mf2(...) __riscv_vsoxseg3ei8_v_f32mf2(__VA_ARGS__) -#define vsoxseg4ei8_v_f32mf2(...) __riscv_vsoxseg4ei8_v_f32mf2(__VA_ARGS__) -#define vsoxseg5ei8_v_f32mf2(...) __riscv_vsoxseg5ei8_v_f32mf2(__VA_ARGS__) -#define vsoxseg6ei8_v_f32mf2(...) __riscv_vsoxseg6ei8_v_f32mf2(__VA_ARGS__) -#define vsoxseg7ei8_v_f32mf2(...) __riscv_vsoxseg7ei8_v_f32mf2(__VA_ARGS__) -#define vsoxseg8ei8_v_f32mf2(...) __riscv_vsoxseg8ei8_v_f32mf2(__VA_ARGS__) -#define vsoxseg2ei8_v_f32m1(...) __riscv_vsoxseg2ei8_v_f32m1(__VA_ARGS__) -#define vsoxseg3ei8_v_f32m1(...) __riscv_vsoxseg3ei8_v_f32m1(__VA_ARGS__) -#define vsoxseg4ei8_v_f32m1(...) __riscv_vsoxseg4ei8_v_f32m1(__VA_ARGS__) -#define vsoxseg5ei8_v_f32m1(...) __riscv_vsoxseg5ei8_v_f32m1(__VA_ARGS__) -#define vsoxseg6ei8_v_f32m1(...) __riscv_vsoxseg6ei8_v_f32m1(__VA_ARGS__) -#define vsoxseg7ei8_v_f32m1(...) __riscv_vsoxseg7ei8_v_f32m1(__VA_ARGS__) -#define vsoxseg8ei8_v_f32m1(...) __riscv_vsoxseg8ei8_v_f32m1(__VA_ARGS__) -#define vsoxseg2ei8_v_f32m2(...) __riscv_vsoxseg2ei8_v_f32m2(__VA_ARGS__) -#define vsoxseg3ei8_v_f32m2(...) __riscv_vsoxseg3ei8_v_f32m2(__VA_ARGS__) -#define vsoxseg4ei8_v_f32m2(...) __riscv_vsoxseg4ei8_v_f32m2(__VA_ARGS__) -#define vsoxseg2ei8_v_f32m4(...) __riscv_vsoxseg2ei8_v_f32m4(__VA_ARGS__) -#define vsoxseg2ei16_v_f32mf2(...) __riscv_vsoxseg2ei16_v_f32mf2(__VA_ARGS__) -#define vsoxseg3ei16_v_f32mf2(...) __riscv_vsoxseg3ei16_v_f32mf2(__VA_ARGS__) -#define vsoxseg4ei16_v_f32mf2(...) __riscv_vsoxseg4ei16_v_f32mf2(__VA_ARGS__) -#define vsoxseg5ei16_v_f32mf2(...) __riscv_vsoxseg5ei16_v_f32mf2(__VA_ARGS__) -#define vsoxseg6ei16_v_f32mf2(...) __riscv_vsoxseg6ei16_v_f32mf2(__VA_ARGS__) -#define vsoxseg7ei16_v_f32mf2(...) __riscv_vsoxseg7ei16_v_f32mf2(__VA_ARGS__) -#define vsoxseg8ei16_v_f32mf2(...) __riscv_vsoxseg8ei16_v_f32mf2(__VA_ARGS__) -#define vsoxseg2ei16_v_f32m1(...) __riscv_vsoxseg2ei16_v_f32m1(__VA_ARGS__) -#define vsoxseg3ei16_v_f32m1(...) __riscv_vsoxseg3ei16_v_f32m1(__VA_ARGS__) -#define vsoxseg4ei16_v_f32m1(...) __riscv_vsoxseg4ei16_v_f32m1(__VA_ARGS__) -#define vsoxseg5ei16_v_f32m1(...) __riscv_vsoxseg5ei16_v_f32m1(__VA_ARGS__) -#define vsoxseg6ei16_v_f32m1(...) __riscv_vsoxseg6ei16_v_f32m1(__VA_ARGS__) -#define vsoxseg7ei16_v_f32m1(...) __riscv_vsoxseg7ei16_v_f32m1(__VA_ARGS__) -#define vsoxseg8ei16_v_f32m1(...) __riscv_vsoxseg8ei16_v_f32m1(__VA_ARGS__) -#define vsoxseg2ei16_v_f32m2(...) __riscv_vsoxseg2ei16_v_f32m2(__VA_ARGS__) -#define vsoxseg3ei16_v_f32m2(...) __riscv_vsoxseg3ei16_v_f32m2(__VA_ARGS__) -#define vsoxseg4ei16_v_f32m2(...) __riscv_vsoxseg4ei16_v_f32m2(__VA_ARGS__) -#define vsoxseg2ei16_v_f32m4(...) __riscv_vsoxseg2ei16_v_f32m4(__VA_ARGS__) -#define vsoxseg2ei32_v_f32mf2(...) __riscv_vsoxseg2ei32_v_f32mf2(__VA_ARGS__) -#define vsoxseg3ei32_v_f32mf2(...) __riscv_vsoxseg3ei32_v_f32mf2(__VA_ARGS__) -#define vsoxseg4ei32_v_f32mf2(...) __riscv_vsoxseg4ei32_v_f32mf2(__VA_ARGS__) -#define vsoxseg5ei32_v_f32mf2(...) __riscv_vsoxseg5ei32_v_f32mf2(__VA_ARGS__) -#define vsoxseg6ei32_v_f32mf2(...) __riscv_vsoxseg6ei32_v_f32mf2(__VA_ARGS__) -#define vsoxseg7ei32_v_f32mf2(...) __riscv_vsoxseg7ei32_v_f32mf2(__VA_ARGS__) -#define vsoxseg8ei32_v_f32mf2(...) __riscv_vsoxseg8ei32_v_f32mf2(__VA_ARGS__) -#define vsoxseg2ei32_v_f32m1(...) __riscv_vsoxseg2ei32_v_f32m1(__VA_ARGS__) -#define vsoxseg3ei32_v_f32m1(...) __riscv_vsoxseg3ei32_v_f32m1(__VA_ARGS__) -#define vsoxseg4ei32_v_f32m1(...) __riscv_vsoxseg4ei32_v_f32m1(__VA_ARGS__) -#define vsoxseg5ei32_v_f32m1(...) __riscv_vsoxseg5ei32_v_f32m1(__VA_ARGS__) -#define vsoxseg6ei32_v_f32m1(...) __riscv_vsoxseg6ei32_v_f32m1(__VA_ARGS__) -#define vsoxseg7ei32_v_f32m1(...) __riscv_vsoxseg7ei32_v_f32m1(__VA_ARGS__) -#define vsoxseg8ei32_v_f32m1(...) __riscv_vsoxseg8ei32_v_f32m1(__VA_ARGS__) -#define vsoxseg2ei32_v_f32m2(...) __riscv_vsoxseg2ei32_v_f32m2(__VA_ARGS__) -#define vsoxseg3ei32_v_f32m2(...) __riscv_vsoxseg3ei32_v_f32m2(__VA_ARGS__) -#define vsoxseg4ei32_v_f32m2(...) __riscv_vsoxseg4ei32_v_f32m2(__VA_ARGS__) -#define vsoxseg2ei32_v_f32m4(...) __riscv_vsoxseg2ei32_v_f32m4(__VA_ARGS__) -#define vsoxseg2ei64_v_f32mf2(...) __riscv_vsoxseg2ei64_v_f32mf2(__VA_ARGS__) -#define vsoxseg3ei64_v_f32mf2(...) __riscv_vsoxseg3ei64_v_f32mf2(__VA_ARGS__) -#define vsoxseg4ei64_v_f32mf2(...) __riscv_vsoxseg4ei64_v_f32mf2(__VA_ARGS__) -#define vsoxseg5ei64_v_f32mf2(...) __riscv_vsoxseg5ei64_v_f32mf2(__VA_ARGS__) -#define vsoxseg6ei64_v_f32mf2(...) __riscv_vsoxseg6ei64_v_f32mf2(__VA_ARGS__) -#define vsoxseg7ei64_v_f32mf2(...) __riscv_vsoxseg7ei64_v_f32mf2(__VA_ARGS__) -#define vsoxseg8ei64_v_f32mf2(...) __riscv_vsoxseg8ei64_v_f32mf2(__VA_ARGS__) -#define vsoxseg2ei64_v_f32m1(...) __riscv_vsoxseg2ei64_v_f32m1(__VA_ARGS__) -#define vsoxseg3ei64_v_f32m1(...) __riscv_vsoxseg3ei64_v_f32m1(__VA_ARGS__) -#define vsoxseg4ei64_v_f32m1(...) __riscv_vsoxseg4ei64_v_f32m1(__VA_ARGS__) -#define vsoxseg5ei64_v_f32m1(...) __riscv_vsoxseg5ei64_v_f32m1(__VA_ARGS__) -#define vsoxseg6ei64_v_f32m1(...) __riscv_vsoxseg6ei64_v_f32m1(__VA_ARGS__) -#define vsoxseg7ei64_v_f32m1(...) __riscv_vsoxseg7ei64_v_f32m1(__VA_ARGS__) -#define vsoxseg8ei64_v_f32m1(...) __riscv_vsoxseg8ei64_v_f32m1(__VA_ARGS__) -#define vsoxseg2ei64_v_f32m2(...) __riscv_vsoxseg2ei64_v_f32m2(__VA_ARGS__) -#define vsoxseg3ei64_v_f32m2(...) __riscv_vsoxseg3ei64_v_f32m2(__VA_ARGS__) -#define vsoxseg4ei64_v_f32m2(...) __riscv_vsoxseg4ei64_v_f32m2(__VA_ARGS__) -#define vsoxseg2ei64_v_f32m4(...) __riscv_vsoxseg2ei64_v_f32m4(__VA_ARGS__) -#define vsoxseg2ei8_v_f64m1(...) __riscv_vsoxseg2ei8_v_f64m1(__VA_ARGS__) -#define vsoxseg3ei8_v_f64m1(...) __riscv_vsoxseg3ei8_v_f64m1(__VA_ARGS__) -#define vsoxseg4ei8_v_f64m1(...) __riscv_vsoxseg4ei8_v_f64m1(__VA_ARGS__) -#define vsoxseg5ei8_v_f64m1(...) __riscv_vsoxseg5ei8_v_f64m1(__VA_ARGS__) -#define vsoxseg6ei8_v_f64m1(...) __riscv_vsoxseg6ei8_v_f64m1(__VA_ARGS__) -#define vsoxseg7ei8_v_f64m1(...) __riscv_vsoxseg7ei8_v_f64m1(__VA_ARGS__) -#define vsoxseg8ei8_v_f64m1(...) __riscv_vsoxseg8ei8_v_f64m1(__VA_ARGS__) -#define vsoxseg2ei8_v_f64m2(...) __riscv_vsoxseg2ei8_v_f64m2(__VA_ARGS__) -#define vsoxseg3ei8_v_f64m2(...) __riscv_vsoxseg3ei8_v_f64m2(__VA_ARGS__) -#define vsoxseg4ei8_v_f64m2(...) __riscv_vsoxseg4ei8_v_f64m2(__VA_ARGS__) -#define vsoxseg2ei8_v_f64m4(...) __riscv_vsoxseg2ei8_v_f64m4(__VA_ARGS__) -#define vsoxseg2ei16_v_f64m1(...) __riscv_vsoxseg2ei16_v_f64m1(__VA_ARGS__) -#define vsoxseg3ei16_v_f64m1(...) __riscv_vsoxseg3ei16_v_f64m1(__VA_ARGS__) -#define vsoxseg4ei16_v_f64m1(...) __riscv_vsoxseg4ei16_v_f64m1(__VA_ARGS__) -#define vsoxseg5ei16_v_f64m1(...) __riscv_vsoxseg5ei16_v_f64m1(__VA_ARGS__) -#define vsoxseg6ei16_v_f64m1(...) __riscv_vsoxseg6ei16_v_f64m1(__VA_ARGS__) -#define vsoxseg7ei16_v_f64m1(...) __riscv_vsoxseg7ei16_v_f64m1(__VA_ARGS__) -#define vsoxseg8ei16_v_f64m1(...) __riscv_vsoxseg8ei16_v_f64m1(__VA_ARGS__) -#define vsoxseg2ei16_v_f64m2(...) __riscv_vsoxseg2ei16_v_f64m2(__VA_ARGS__) -#define vsoxseg3ei16_v_f64m2(...) __riscv_vsoxseg3ei16_v_f64m2(__VA_ARGS__) -#define vsoxseg4ei16_v_f64m2(...) __riscv_vsoxseg4ei16_v_f64m2(__VA_ARGS__) -#define vsoxseg2ei16_v_f64m4(...) __riscv_vsoxseg2ei16_v_f64m4(__VA_ARGS__) -#define vsoxseg2ei32_v_f64m1(...) __riscv_vsoxseg2ei32_v_f64m1(__VA_ARGS__) -#define vsoxseg3ei32_v_f64m1(...) __riscv_vsoxseg3ei32_v_f64m1(__VA_ARGS__) -#define vsoxseg4ei32_v_f64m1(...) __riscv_vsoxseg4ei32_v_f64m1(__VA_ARGS__) -#define vsoxseg5ei32_v_f64m1(...) __riscv_vsoxseg5ei32_v_f64m1(__VA_ARGS__) -#define vsoxseg6ei32_v_f64m1(...) __riscv_vsoxseg6ei32_v_f64m1(__VA_ARGS__) -#define vsoxseg7ei32_v_f64m1(...) __riscv_vsoxseg7ei32_v_f64m1(__VA_ARGS__) -#define vsoxseg8ei32_v_f64m1(...) __riscv_vsoxseg8ei32_v_f64m1(__VA_ARGS__) -#define vsoxseg2ei32_v_f64m2(...) __riscv_vsoxseg2ei32_v_f64m2(__VA_ARGS__) -#define vsoxseg3ei32_v_f64m2(...) __riscv_vsoxseg3ei32_v_f64m2(__VA_ARGS__) -#define vsoxseg4ei32_v_f64m2(...) __riscv_vsoxseg4ei32_v_f64m2(__VA_ARGS__) -#define vsoxseg2ei32_v_f64m4(...) __riscv_vsoxseg2ei32_v_f64m4(__VA_ARGS__) -#define vsoxseg2ei64_v_f64m1(...) __riscv_vsoxseg2ei64_v_f64m1(__VA_ARGS__) -#define vsoxseg3ei64_v_f64m1(...) __riscv_vsoxseg3ei64_v_f64m1(__VA_ARGS__) -#define vsoxseg4ei64_v_f64m1(...) __riscv_vsoxseg4ei64_v_f64m1(__VA_ARGS__) -#define vsoxseg5ei64_v_f64m1(...) __riscv_vsoxseg5ei64_v_f64m1(__VA_ARGS__) -#define vsoxseg6ei64_v_f64m1(...) __riscv_vsoxseg6ei64_v_f64m1(__VA_ARGS__) -#define vsoxseg7ei64_v_f64m1(...) __riscv_vsoxseg7ei64_v_f64m1(__VA_ARGS__) -#define vsoxseg8ei64_v_f64m1(...) __riscv_vsoxseg8ei64_v_f64m1(__VA_ARGS__) -#define vsoxseg2ei64_v_f64m2(...) __riscv_vsoxseg2ei64_v_f64m2(__VA_ARGS__) -#define vsoxseg3ei64_v_f64m2(...) __riscv_vsoxseg3ei64_v_f64m2(__VA_ARGS__) -#define vsoxseg4ei64_v_f64m2(...) __riscv_vsoxseg4ei64_v_f64m2(__VA_ARGS__) -#define vsoxseg2ei64_v_f64m4(...) __riscv_vsoxseg2ei64_v_f64m4(__VA_ARGS__) -#define vsuxseg2ei8_v_f16mf4(...) __riscv_vsuxseg2ei8_v_f16mf4(__VA_ARGS__) -#define vsuxseg3ei8_v_f16mf4(...) __riscv_vsuxseg3ei8_v_f16mf4(__VA_ARGS__) -#define vsuxseg4ei8_v_f16mf4(...) __riscv_vsuxseg4ei8_v_f16mf4(__VA_ARGS__) -#define vsuxseg5ei8_v_f16mf4(...) __riscv_vsuxseg5ei8_v_f16mf4(__VA_ARGS__) -#define vsuxseg6ei8_v_f16mf4(...) __riscv_vsuxseg6ei8_v_f16mf4(__VA_ARGS__) -#define vsuxseg7ei8_v_f16mf4(...) __riscv_vsuxseg7ei8_v_f16mf4(__VA_ARGS__) -#define vsuxseg8ei8_v_f16mf4(...) __riscv_vsuxseg8ei8_v_f16mf4(__VA_ARGS__) -#define vsuxseg2ei8_v_f16mf2(...) __riscv_vsuxseg2ei8_v_f16mf2(__VA_ARGS__) -#define vsuxseg3ei8_v_f16mf2(...) __riscv_vsuxseg3ei8_v_f16mf2(__VA_ARGS__) -#define vsuxseg4ei8_v_f16mf2(...) __riscv_vsuxseg4ei8_v_f16mf2(__VA_ARGS__) -#define vsuxseg5ei8_v_f16mf2(...) __riscv_vsuxseg5ei8_v_f16mf2(__VA_ARGS__) -#define vsuxseg6ei8_v_f16mf2(...) __riscv_vsuxseg6ei8_v_f16mf2(__VA_ARGS__) -#define vsuxseg7ei8_v_f16mf2(...) __riscv_vsuxseg7ei8_v_f16mf2(__VA_ARGS__) -#define vsuxseg8ei8_v_f16mf2(...) __riscv_vsuxseg8ei8_v_f16mf2(__VA_ARGS__) -#define vsuxseg2ei8_v_f16m1(...) __riscv_vsuxseg2ei8_v_f16m1(__VA_ARGS__) -#define vsuxseg3ei8_v_f16m1(...) __riscv_vsuxseg3ei8_v_f16m1(__VA_ARGS__) -#define vsuxseg4ei8_v_f16m1(...) __riscv_vsuxseg4ei8_v_f16m1(__VA_ARGS__) -#define vsuxseg5ei8_v_f16m1(...) __riscv_vsuxseg5ei8_v_f16m1(__VA_ARGS__) -#define vsuxseg6ei8_v_f16m1(...) __riscv_vsuxseg6ei8_v_f16m1(__VA_ARGS__) -#define vsuxseg7ei8_v_f16m1(...) __riscv_vsuxseg7ei8_v_f16m1(__VA_ARGS__) -#define vsuxseg8ei8_v_f16m1(...) __riscv_vsuxseg8ei8_v_f16m1(__VA_ARGS__) -#define vsuxseg2ei8_v_f16m2(...) __riscv_vsuxseg2ei8_v_f16m2(__VA_ARGS__) -#define vsuxseg3ei8_v_f16m2(...) __riscv_vsuxseg3ei8_v_f16m2(__VA_ARGS__) -#define vsuxseg4ei8_v_f16m2(...) __riscv_vsuxseg4ei8_v_f16m2(__VA_ARGS__) -#define vsuxseg2ei8_v_f16m4(...) __riscv_vsuxseg2ei8_v_f16m4(__VA_ARGS__) -#define vsuxseg2ei16_v_f16mf4(...) __riscv_vsuxseg2ei16_v_f16mf4(__VA_ARGS__) -#define vsuxseg3ei16_v_f16mf4(...) __riscv_vsuxseg3ei16_v_f16mf4(__VA_ARGS__) -#define vsuxseg4ei16_v_f16mf4(...) __riscv_vsuxseg4ei16_v_f16mf4(__VA_ARGS__) -#define vsuxseg5ei16_v_f16mf4(...) __riscv_vsuxseg5ei16_v_f16mf4(__VA_ARGS__) -#define vsuxseg6ei16_v_f16mf4(...) __riscv_vsuxseg6ei16_v_f16mf4(__VA_ARGS__) -#define vsuxseg7ei16_v_f16mf4(...) __riscv_vsuxseg7ei16_v_f16mf4(__VA_ARGS__) -#define vsuxseg8ei16_v_f16mf4(...) __riscv_vsuxseg8ei16_v_f16mf4(__VA_ARGS__) -#define vsuxseg2ei16_v_f16mf2(...) __riscv_vsuxseg2ei16_v_f16mf2(__VA_ARGS__) -#define vsuxseg3ei16_v_f16mf2(...) __riscv_vsuxseg3ei16_v_f16mf2(__VA_ARGS__) -#define vsuxseg4ei16_v_f16mf2(...) __riscv_vsuxseg4ei16_v_f16mf2(__VA_ARGS__) -#define vsuxseg5ei16_v_f16mf2(...) __riscv_vsuxseg5ei16_v_f16mf2(__VA_ARGS__) -#define vsuxseg6ei16_v_f16mf2(...) __riscv_vsuxseg6ei16_v_f16mf2(__VA_ARGS__) -#define vsuxseg7ei16_v_f16mf2(...) __riscv_vsuxseg7ei16_v_f16mf2(__VA_ARGS__) -#define vsuxseg8ei16_v_f16mf2(...) __riscv_vsuxseg8ei16_v_f16mf2(__VA_ARGS__) -#define vsuxseg2ei16_v_f16m1(...) __riscv_vsuxseg2ei16_v_f16m1(__VA_ARGS__) -#define vsuxseg3ei16_v_f16m1(...) __riscv_vsuxseg3ei16_v_f16m1(__VA_ARGS__) -#define vsuxseg4ei16_v_f16m1(...) __riscv_vsuxseg4ei16_v_f16m1(__VA_ARGS__) -#define vsuxseg5ei16_v_f16m1(...) __riscv_vsuxseg5ei16_v_f16m1(__VA_ARGS__) -#define vsuxseg6ei16_v_f16m1(...) __riscv_vsuxseg6ei16_v_f16m1(__VA_ARGS__) -#define vsuxseg7ei16_v_f16m1(...) __riscv_vsuxseg7ei16_v_f16m1(__VA_ARGS__) -#define vsuxseg8ei16_v_f16m1(...) __riscv_vsuxseg8ei16_v_f16m1(__VA_ARGS__) -#define vsuxseg2ei16_v_f16m2(...) __riscv_vsuxseg2ei16_v_f16m2(__VA_ARGS__) -#define vsuxseg3ei16_v_f16m2(...) __riscv_vsuxseg3ei16_v_f16m2(__VA_ARGS__) -#define vsuxseg4ei16_v_f16m2(...) __riscv_vsuxseg4ei16_v_f16m2(__VA_ARGS__) -#define vsuxseg2ei16_v_f16m4(...) __riscv_vsuxseg2ei16_v_f16m4(__VA_ARGS__) -#define vsuxseg2ei32_v_f16mf4(...) __riscv_vsuxseg2ei32_v_f16mf4(__VA_ARGS__) -#define vsuxseg3ei32_v_f16mf4(...) __riscv_vsuxseg3ei32_v_f16mf4(__VA_ARGS__) -#define vsuxseg4ei32_v_f16mf4(...) __riscv_vsuxseg4ei32_v_f16mf4(__VA_ARGS__) -#define vsuxseg5ei32_v_f16mf4(...) __riscv_vsuxseg5ei32_v_f16mf4(__VA_ARGS__) -#define vsuxseg6ei32_v_f16mf4(...) __riscv_vsuxseg6ei32_v_f16mf4(__VA_ARGS__) -#define vsuxseg7ei32_v_f16mf4(...) __riscv_vsuxseg7ei32_v_f16mf4(__VA_ARGS__) -#define vsuxseg8ei32_v_f16mf4(...) __riscv_vsuxseg8ei32_v_f16mf4(__VA_ARGS__) -#define vsuxseg2ei32_v_f16mf2(...) __riscv_vsuxseg2ei32_v_f16mf2(__VA_ARGS__) -#define vsuxseg3ei32_v_f16mf2(...) __riscv_vsuxseg3ei32_v_f16mf2(__VA_ARGS__) -#define vsuxseg4ei32_v_f16mf2(...) __riscv_vsuxseg4ei32_v_f16mf2(__VA_ARGS__) -#define vsuxseg5ei32_v_f16mf2(...) __riscv_vsuxseg5ei32_v_f16mf2(__VA_ARGS__) -#define vsuxseg6ei32_v_f16mf2(...) __riscv_vsuxseg6ei32_v_f16mf2(__VA_ARGS__) -#define vsuxseg7ei32_v_f16mf2(...) __riscv_vsuxseg7ei32_v_f16mf2(__VA_ARGS__) -#define vsuxseg8ei32_v_f16mf2(...) __riscv_vsuxseg8ei32_v_f16mf2(__VA_ARGS__) -#define vsuxseg2ei32_v_f16m1(...) __riscv_vsuxseg2ei32_v_f16m1(__VA_ARGS__) -#define vsuxseg3ei32_v_f16m1(...) __riscv_vsuxseg3ei32_v_f16m1(__VA_ARGS__) -#define vsuxseg4ei32_v_f16m1(...) __riscv_vsuxseg4ei32_v_f16m1(__VA_ARGS__) -#define vsuxseg5ei32_v_f16m1(...) __riscv_vsuxseg5ei32_v_f16m1(__VA_ARGS__) -#define vsuxseg6ei32_v_f16m1(...) __riscv_vsuxseg6ei32_v_f16m1(__VA_ARGS__) -#define vsuxseg7ei32_v_f16m1(...) __riscv_vsuxseg7ei32_v_f16m1(__VA_ARGS__) -#define vsuxseg8ei32_v_f16m1(...) __riscv_vsuxseg8ei32_v_f16m1(__VA_ARGS__) -#define vsuxseg2ei32_v_f16m2(...) __riscv_vsuxseg2ei32_v_f16m2(__VA_ARGS__) -#define vsuxseg3ei32_v_f16m2(...) __riscv_vsuxseg3ei32_v_f16m2(__VA_ARGS__) -#define vsuxseg4ei32_v_f16m2(...) __riscv_vsuxseg4ei32_v_f16m2(__VA_ARGS__) -#define vsuxseg2ei32_v_f16m4(...) __riscv_vsuxseg2ei32_v_f16m4(__VA_ARGS__) -#define vsuxseg2ei64_v_f16mf4(...) __riscv_vsuxseg2ei64_v_f16mf4(__VA_ARGS__) -#define vsuxseg3ei64_v_f16mf4(...) __riscv_vsuxseg3ei64_v_f16mf4(__VA_ARGS__) -#define vsuxseg4ei64_v_f16mf4(...) __riscv_vsuxseg4ei64_v_f16mf4(__VA_ARGS__) -#define vsuxseg5ei64_v_f16mf4(...) __riscv_vsuxseg5ei64_v_f16mf4(__VA_ARGS__) -#define vsuxseg6ei64_v_f16mf4(...) __riscv_vsuxseg6ei64_v_f16mf4(__VA_ARGS__) -#define vsuxseg7ei64_v_f16mf4(...) __riscv_vsuxseg7ei64_v_f16mf4(__VA_ARGS__) -#define vsuxseg8ei64_v_f16mf4(...) __riscv_vsuxseg8ei64_v_f16mf4(__VA_ARGS__) -#define vsuxseg2ei64_v_f16mf2(...) __riscv_vsuxseg2ei64_v_f16mf2(__VA_ARGS__) -#define vsuxseg3ei64_v_f16mf2(...) __riscv_vsuxseg3ei64_v_f16mf2(__VA_ARGS__) -#define vsuxseg4ei64_v_f16mf2(...) __riscv_vsuxseg4ei64_v_f16mf2(__VA_ARGS__) -#define vsuxseg5ei64_v_f16mf2(...) __riscv_vsuxseg5ei64_v_f16mf2(__VA_ARGS__) -#define vsuxseg6ei64_v_f16mf2(...) __riscv_vsuxseg6ei64_v_f16mf2(__VA_ARGS__) -#define vsuxseg7ei64_v_f16mf2(...) __riscv_vsuxseg7ei64_v_f16mf2(__VA_ARGS__) -#define vsuxseg8ei64_v_f16mf2(...) __riscv_vsuxseg8ei64_v_f16mf2(__VA_ARGS__) -#define vsuxseg2ei64_v_f16m1(...) __riscv_vsuxseg2ei64_v_f16m1(__VA_ARGS__) -#define vsuxseg3ei64_v_f16m1(...) __riscv_vsuxseg3ei64_v_f16m1(__VA_ARGS__) -#define vsuxseg4ei64_v_f16m1(...) __riscv_vsuxseg4ei64_v_f16m1(__VA_ARGS__) -#define vsuxseg5ei64_v_f16m1(...) __riscv_vsuxseg5ei64_v_f16m1(__VA_ARGS__) -#define vsuxseg6ei64_v_f16m1(...) __riscv_vsuxseg6ei64_v_f16m1(__VA_ARGS__) -#define vsuxseg7ei64_v_f16m1(...) __riscv_vsuxseg7ei64_v_f16m1(__VA_ARGS__) -#define vsuxseg8ei64_v_f16m1(...) __riscv_vsuxseg8ei64_v_f16m1(__VA_ARGS__) -#define vsuxseg2ei64_v_f16m2(...) __riscv_vsuxseg2ei64_v_f16m2(__VA_ARGS__) -#define vsuxseg3ei64_v_f16m2(...) __riscv_vsuxseg3ei64_v_f16m2(__VA_ARGS__) -#define vsuxseg4ei64_v_f16m2(...) __riscv_vsuxseg4ei64_v_f16m2(__VA_ARGS__) -#define vsuxseg2ei8_v_f32mf2(...) __riscv_vsuxseg2ei8_v_f32mf2(__VA_ARGS__) -#define vsuxseg3ei8_v_f32mf2(...) __riscv_vsuxseg3ei8_v_f32mf2(__VA_ARGS__) -#define vsuxseg4ei8_v_f32mf2(...) __riscv_vsuxseg4ei8_v_f32mf2(__VA_ARGS__) -#define vsuxseg5ei8_v_f32mf2(...) __riscv_vsuxseg5ei8_v_f32mf2(__VA_ARGS__) -#define vsuxseg6ei8_v_f32mf2(...) __riscv_vsuxseg6ei8_v_f32mf2(__VA_ARGS__) -#define vsuxseg7ei8_v_f32mf2(...) __riscv_vsuxseg7ei8_v_f32mf2(__VA_ARGS__) -#define vsuxseg8ei8_v_f32mf2(...) __riscv_vsuxseg8ei8_v_f32mf2(__VA_ARGS__) -#define vsuxseg2ei8_v_f32m1(...) __riscv_vsuxseg2ei8_v_f32m1(__VA_ARGS__) -#define vsuxseg3ei8_v_f32m1(...) __riscv_vsuxseg3ei8_v_f32m1(__VA_ARGS__) -#define vsuxseg4ei8_v_f32m1(...) __riscv_vsuxseg4ei8_v_f32m1(__VA_ARGS__) -#define vsuxseg5ei8_v_f32m1(...) __riscv_vsuxseg5ei8_v_f32m1(__VA_ARGS__) -#define vsuxseg6ei8_v_f32m1(...) __riscv_vsuxseg6ei8_v_f32m1(__VA_ARGS__) -#define vsuxseg7ei8_v_f32m1(...) __riscv_vsuxseg7ei8_v_f32m1(__VA_ARGS__) -#define vsuxseg8ei8_v_f32m1(...) __riscv_vsuxseg8ei8_v_f32m1(__VA_ARGS__) -#define vsuxseg2ei8_v_f32m2(...) __riscv_vsuxseg2ei8_v_f32m2(__VA_ARGS__) -#define vsuxseg3ei8_v_f32m2(...) __riscv_vsuxseg3ei8_v_f32m2(__VA_ARGS__) -#define vsuxseg4ei8_v_f32m2(...) __riscv_vsuxseg4ei8_v_f32m2(__VA_ARGS__) -#define vsuxseg2ei8_v_f32m4(...) __riscv_vsuxseg2ei8_v_f32m4(__VA_ARGS__) -#define vsuxseg2ei16_v_f32mf2(...) __riscv_vsuxseg2ei16_v_f32mf2(__VA_ARGS__) -#define vsuxseg3ei16_v_f32mf2(...) __riscv_vsuxseg3ei16_v_f32mf2(__VA_ARGS__) -#define vsuxseg4ei16_v_f32mf2(...) __riscv_vsuxseg4ei16_v_f32mf2(__VA_ARGS__) -#define vsuxseg5ei16_v_f32mf2(...) __riscv_vsuxseg5ei16_v_f32mf2(__VA_ARGS__) -#define vsuxseg6ei16_v_f32mf2(...) __riscv_vsuxseg6ei16_v_f32mf2(__VA_ARGS__) -#define vsuxseg7ei16_v_f32mf2(...) __riscv_vsuxseg7ei16_v_f32mf2(__VA_ARGS__) -#define vsuxseg8ei16_v_f32mf2(...) __riscv_vsuxseg8ei16_v_f32mf2(__VA_ARGS__) -#define vsuxseg2ei16_v_f32m1(...) __riscv_vsuxseg2ei16_v_f32m1(__VA_ARGS__) -#define vsuxseg3ei16_v_f32m1(...) __riscv_vsuxseg3ei16_v_f32m1(__VA_ARGS__) -#define vsuxseg4ei16_v_f32m1(...) __riscv_vsuxseg4ei16_v_f32m1(__VA_ARGS__) -#define vsuxseg5ei16_v_f32m1(...) __riscv_vsuxseg5ei16_v_f32m1(__VA_ARGS__) -#define vsuxseg6ei16_v_f32m1(...) __riscv_vsuxseg6ei16_v_f32m1(__VA_ARGS__) -#define vsuxseg7ei16_v_f32m1(...) __riscv_vsuxseg7ei16_v_f32m1(__VA_ARGS__) -#define vsuxseg8ei16_v_f32m1(...) __riscv_vsuxseg8ei16_v_f32m1(__VA_ARGS__) -#define vsuxseg2ei16_v_f32m2(...) __riscv_vsuxseg2ei16_v_f32m2(__VA_ARGS__) -#define vsuxseg3ei16_v_f32m2(...) __riscv_vsuxseg3ei16_v_f32m2(__VA_ARGS__) -#define vsuxseg4ei16_v_f32m2(...) __riscv_vsuxseg4ei16_v_f32m2(__VA_ARGS__) -#define vsuxseg2ei16_v_f32m4(...) __riscv_vsuxseg2ei16_v_f32m4(__VA_ARGS__) -#define vsuxseg2ei32_v_f32mf2(...) __riscv_vsuxseg2ei32_v_f32mf2(__VA_ARGS__) -#define vsuxseg3ei32_v_f32mf2(...) __riscv_vsuxseg3ei32_v_f32mf2(__VA_ARGS__) -#define vsuxseg4ei32_v_f32mf2(...) __riscv_vsuxseg4ei32_v_f32mf2(__VA_ARGS__) -#define vsuxseg5ei32_v_f32mf2(...) __riscv_vsuxseg5ei32_v_f32mf2(__VA_ARGS__) -#define vsuxseg6ei32_v_f32mf2(...) __riscv_vsuxseg6ei32_v_f32mf2(__VA_ARGS__) -#define vsuxseg7ei32_v_f32mf2(...) __riscv_vsuxseg7ei32_v_f32mf2(__VA_ARGS__) -#define vsuxseg8ei32_v_f32mf2(...) __riscv_vsuxseg8ei32_v_f32mf2(__VA_ARGS__) -#define vsuxseg2ei32_v_f32m1(...) __riscv_vsuxseg2ei32_v_f32m1(__VA_ARGS__) -#define vsuxseg3ei32_v_f32m1(...) __riscv_vsuxseg3ei32_v_f32m1(__VA_ARGS__) -#define vsuxseg4ei32_v_f32m1(...) __riscv_vsuxseg4ei32_v_f32m1(__VA_ARGS__) -#define vsuxseg5ei32_v_f32m1(...) __riscv_vsuxseg5ei32_v_f32m1(__VA_ARGS__) -#define vsuxseg6ei32_v_f32m1(...) __riscv_vsuxseg6ei32_v_f32m1(__VA_ARGS__) -#define vsuxseg7ei32_v_f32m1(...) __riscv_vsuxseg7ei32_v_f32m1(__VA_ARGS__) -#define vsuxseg8ei32_v_f32m1(...) __riscv_vsuxseg8ei32_v_f32m1(__VA_ARGS__) -#define vsuxseg2ei32_v_f32m2(...) __riscv_vsuxseg2ei32_v_f32m2(__VA_ARGS__) -#define vsuxseg3ei32_v_f32m2(...) __riscv_vsuxseg3ei32_v_f32m2(__VA_ARGS__) -#define vsuxseg4ei32_v_f32m2(...) __riscv_vsuxseg4ei32_v_f32m2(__VA_ARGS__) -#define vsuxseg2ei32_v_f32m4(...) __riscv_vsuxseg2ei32_v_f32m4(__VA_ARGS__) -#define vsuxseg2ei64_v_f32mf2(...) __riscv_vsuxseg2ei64_v_f32mf2(__VA_ARGS__) -#define vsuxseg3ei64_v_f32mf2(...) __riscv_vsuxseg3ei64_v_f32mf2(__VA_ARGS__) -#define vsuxseg4ei64_v_f32mf2(...) __riscv_vsuxseg4ei64_v_f32mf2(__VA_ARGS__) -#define vsuxseg5ei64_v_f32mf2(...) __riscv_vsuxseg5ei64_v_f32mf2(__VA_ARGS__) -#define vsuxseg6ei64_v_f32mf2(...) __riscv_vsuxseg6ei64_v_f32mf2(__VA_ARGS__) -#define vsuxseg7ei64_v_f32mf2(...) __riscv_vsuxseg7ei64_v_f32mf2(__VA_ARGS__) -#define vsuxseg8ei64_v_f32mf2(...) __riscv_vsuxseg8ei64_v_f32mf2(__VA_ARGS__) -#define vsuxseg2ei64_v_f32m1(...) __riscv_vsuxseg2ei64_v_f32m1(__VA_ARGS__) -#define vsuxseg3ei64_v_f32m1(...) __riscv_vsuxseg3ei64_v_f32m1(__VA_ARGS__) -#define vsuxseg4ei64_v_f32m1(...) __riscv_vsuxseg4ei64_v_f32m1(__VA_ARGS__) -#define vsuxseg5ei64_v_f32m1(...) __riscv_vsuxseg5ei64_v_f32m1(__VA_ARGS__) -#define vsuxseg6ei64_v_f32m1(...) __riscv_vsuxseg6ei64_v_f32m1(__VA_ARGS__) -#define vsuxseg7ei64_v_f32m1(...) __riscv_vsuxseg7ei64_v_f32m1(__VA_ARGS__) -#define vsuxseg8ei64_v_f32m1(...) __riscv_vsuxseg8ei64_v_f32m1(__VA_ARGS__) -#define vsuxseg2ei64_v_f32m2(...) __riscv_vsuxseg2ei64_v_f32m2(__VA_ARGS__) -#define vsuxseg3ei64_v_f32m2(...) __riscv_vsuxseg3ei64_v_f32m2(__VA_ARGS__) -#define vsuxseg4ei64_v_f32m2(...) __riscv_vsuxseg4ei64_v_f32m2(__VA_ARGS__) -#define vsuxseg2ei64_v_f32m4(...) __riscv_vsuxseg2ei64_v_f32m4(__VA_ARGS__) -#define vsuxseg2ei8_v_f64m1(...) __riscv_vsuxseg2ei8_v_f64m1(__VA_ARGS__) -#define vsuxseg3ei8_v_f64m1(...) __riscv_vsuxseg3ei8_v_f64m1(__VA_ARGS__) -#define vsuxseg4ei8_v_f64m1(...) __riscv_vsuxseg4ei8_v_f64m1(__VA_ARGS__) -#define vsuxseg5ei8_v_f64m1(...) __riscv_vsuxseg5ei8_v_f64m1(__VA_ARGS__) -#define vsuxseg6ei8_v_f64m1(...) __riscv_vsuxseg6ei8_v_f64m1(__VA_ARGS__) -#define vsuxseg7ei8_v_f64m1(...) __riscv_vsuxseg7ei8_v_f64m1(__VA_ARGS__) -#define vsuxseg8ei8_v_f64m1(...) __riscv_vsuxseg8ei8_v_f64m1(__VA_ARGS__) -#define vsuxseg2ei8_v_f64m2(...) __riscv_vsuxseg2ei8_v_f64m2(__VA_ARGS__) -#define vsuxseg3ei8_v_f64m2(...) __riscv_vsuxseg3ei8_v_f64m2(__VA_ARGS__) -#define vsuxseg4ei8_v_f64m2(...) __riscv_vsuxseg4ei8_v_f64m2(__VA_ARGS__) -#define vsuxseg2ei8_v_f64m4(...) __riscv_vsuxseg2ei8_v_f64m4(__VA_ARGS__) -#define vsuxseg2ei16_v_f64m1(...) __riscv_vsuxseg2ei16_v_f64m1(__VA_ARGS__) -#define vsuxseg3ei16_v_f64m1(...) __riscv_vsuxseg3ei16_v_f64m1(__VA_ARGS__) -#define vsuxseg4ei16_v_f64m1(...) __riscv_vsuxseg4ei16_v_f64m1(__VA_ARGS__) -#define vsuxseg5ei16_v_f64m1(...) __riscv_vsuxseg5ei16_v_f64m1(__VA_ARGS__) -#define vsuxseg6ei16_v_f64m1(...) __riscv_vsuxseg6ei16_v_f64m1(__VA_ARGS__) -#define vsuxseg7ei16_v_f64m1(...) __riscv_vsuxseg7ei16_v_f64m1(__VA_ARGS__) -#define vsuxseg8ei16_v_f64m1(...) __riscv_vsuxseg8ei16_v_f64m1(__VA_ARGS__) -#define vsuxseg2ei16_v_f64m2(...) __riscv_vsuxseg2ei16_v_f64m2(__VA_ARGS__) -#define vsuxseg3ei16_v_f64m2(...) __riscv_vsuxseg3ei16_v_f64m2(__VA_ARGS__) -#define vsuxseg4ei16_v_f64m2(...) __riscv_vsuxseg4ei16_v_f64m2(__VA_ARGS__) -#define vsuxseg2ei16_v_f64m4(...) __riscv_vsuxseg2ei16_v_f64m4(__VA_ARGS__) -#define vsuxseg2ei32_v_f64m1(...) __riscv_vsuxseg2ei32_v_f64m1(__VA_ARGS__) -#define vsuxseg3ei32_v_f64m1(...) __riscv_vsuxseg3ei32_v_f64m1(__VA_ARGS__) -#define vsuxseg4ei32_v_f64m1(...) __riscv_vsuxseg4ei32_v_f64m1(__VA_ARGS__) -#define vsuxseg5ei32_v_f64m1(...) __riscv_vsuxseg5ei32_v_f64m1(__VA_ARGS__) -#define vsuxseg6ei32_v_f64m1(...) __riscv_vsuxseg6ei32_v_f64m1(__VA_ARGS__) -#define vsuxseg7ei32_v_f64m1(...) __riscv_vsuxseg7ei32_v_f64m1(__VA_ARGS__) -#define vsuxseg8ei32_v_f64m1(...) __riscv_vsuxseg8ei32_v_f64m1(__VA_ARGS__) -#define vsuxseg2ei32_v_f64m2(...) __riscv_vsuxseg2ei32_v_f64m2(__VA_ARGS__) -#define vsuxseg3ei32_v_f64m2(...) __riscv_vsuxseg3ei32_v_f64m2(__VA_ARGS__) -#define vsuxseg4ei32_v_f64m2(...) __riscv_vsuxseg4ei32_v_f64m2(__VA_ARGS__) -#define vsuxseg2ei32_v_f64m4(...) __riscv_vsuxseg2ei32_v_f64m4(__VA_ARGS__) -#define vsuxseg2ei64_v_f64m1(...) __riscv_vsuxseg2ei64_v_f64m1(__VA_ARGS__) -#define vsuxseg3ei64_v_f64m1(...) __riscv_vsuxseg3ei64_v_f64m1(__VA_ARGS__) -#define vsuxseg4ei64_v_f64m1(...) __riscv_vsuxseg4ei64_v_f64m1(__VA_ARGS__) -#define vsuxseg5ei64_v_f64m1(...) __riscv_vsuxseg5ei64_v_f64m1(__VA_ARGS__) -#define vsuxseg6ei64_v_f64m1(...) __riscv_vsuxseg6ei64_v_f64m1(__VA_ARGS__) -#define vsuxseg7ei64_v_f64m1(...) __riscv_vsuxseg7ei64_v_f64m1(__VA_ARGS__) -#define vsuxseg8ei64_v_f64m1(...) __riscv_vsuxseg8ei64_v_f64m1(__VA_ARGS__) -#define vsuxseg2ei64_v_f64m2(...) __riscv_vsuxseg2ei64_v_f64m2(__VA_ARGS__) -#define vsuxseg3ei64_v_f64m2(...) __riscv_vsuxseg3ei64_v_f64m2(__VA_ARGS__) -#define vsuxseg4ei64_v_f64m2(...) __riscv_vsuxseg4ei64_v_f64m2(__VA_ARGS__) -#define vsuxseg2ei64_v_f64m4(...) __riscv_vsuxseg2ei64_v_f64m4(__VA_ARGS__) -#define vsoxseg2ei8_v_i8mf8(...) __riscv_vsoxseg2ei8_v_i8mf8(__VA_ARGS__) -#define vsoxseg3ei8_v_i8mf8(...) __riscv_vsoxseg3ei8_v_i8mf8(__VA_ARGS__) -#define vsoxseg4ei8_v_i8mf8(...) __riscv_vsoxseg4ei8_v_i8mf8(__VA_ARGS__) -#define vsoxseg5ei8_v_i8mf8(...) __riscv_vsoxseg5ei8_v_i8mf8(__VA_ARGS__) -#define vsoxseg6ei8_v_i8mf8(...) __riscv_vsoxseg6ei8_v_i8mf8(__VA_ARGS__) -#define vsoxseg7ei8_v_i8mf8(...) __riscv_vsoxseg7ei8_v_i8mf8(__VA_ARGS__) -#define vsoxseg8ei8_v_i8mf8(...) __riscv_vsoxseg8ei8_v_i8mf8(__VA_ARGS__) -#define vsoxseg2ei8_v_i8mf4(...) __riscv_vsoxseg2ei8_v_i8mf4(__VA_ARGS__) -#define vsoxseg3ei8_v_i8mf4(...) __riscv_vsoxseg3ei8_v_i8mf4(__VA_ARGS__) -#define vsoxseg4ei8_v_i8mf4(...) __riscv_vsoxseg4ei8_v_i8mf4(__VA_ARGS__) -#define vsoxseg5ei8_v_i8mf4(...) __riscv_vsoxseg5ei8_v_i8mf4(__VA_ARGS__) -#define vsoxseg6ei8_v_i8mf4(...) __riscv_vsoxseg6ei8_v_i8mf4(__VA_ARGS__) -#define vsoxseg7ei8_v_i8mf4(...) __riscv_vsoxseg7ei8_v_i8mf4(__VA_ARGS__) -#define vsoxseg8ei8_v_i8mf4(...) __riscv_vsoxseg8ei8_v_i8mf4(__VA_ARGS__) -#define vsoxseg2ei8_v_i8mf2(...) __riscv_vsoxseg2ei8_v_i8mf2(__VA_ARGS__) -#define vsoxseg3ei8_v_i8mf2(...) __riscv_vsoxseg3ei8_v_i8mf2(__VA_ARGS__) -#define vsoxseg4ei8_v_i8mf2(...) __riscv_vsoxseg4ei8_v_i8mf2(__VA_ARGS__) -#define vsoxseg5ei8_v_i8mf2(...) __riscv_vsoxseg5ei8_v_i8mf2(__VA_ARGS__) -#define vsoxseg6ei8_v_i8mf2(...) __riscv_vsoxseg6ei8_v_i8mf2(__VA_ARGS__) -#define vsoxseg7ei8_v_i8mf2(...) __riscv_vsoxseg7ei8_v_i8mf2(__VA_ARGS__) -#define vsoxseg8ei8_v_i8mf2(...) __riscv_vsoxseg8ei8_v_i8mf2(__VA_ARGS__) -#define vsoxseg2ei8_v_i8m1(...) __riscv_vsoxseg2ei8_v_i8m1(__VA_ARGS__) -#define vsoxseg3ei8_v_i8m1(...) __riscv_vsoxseg3ei8_v_i8m1(__VA_ARGS__) -#define vsoxseg4ei8_v_i8m1(...) __riscv_vsoxseg4ei8_v_i8m1(__VA_ARGS__) -#define vsoxseg5ei8_v_i8m1(...) __riscv_vsoxseg5ei8_v_i8m1(__VA_ARGS__) -#define vsoxseg6ei8_v_i8m1(...) __riscv_vsoxseg6ei8_v_i8m1(__VA_ARGS__) -#define vsoxseg7ei8_v_i8m1(...) __riscv_vsoxseg7ei8_v_i8m1(__VA_ARGS__) -#define vsoxseg8ei8_v_i8m1(...) __riscv_vsoxseg8ei8_v_i8m1(__VA_ARGS__) -#define vsoxseg2ei8_v_i8m2(...) __riscv_vsoxseg2ei8_v_i8m2(__VA_ARGS__) -#define vsoxseg3ei8_v_i8m2(...) __riscv_vsoxseg3ei8_v_i8m2(__VA_ARGS__) -#define vsoxseg4ei8_v_i8m2(...) __riscv_vsoxseg4ei8_v_i8m2(__VA_ARGS__) -#define vsoxseg2ei8_v_i8m4(...) __riscv_vsoxseg2ei8_v_i8m4(__VA_ARGS__) -#define vsoxseg2ei16_v_i8mf8(...) __riscv_vsoxseg2ei16_v_i8mf8(__VA_ARGS__) -#define vsoxseg3ei16_v_i8mf8(...) __riscv_vsoxseg3ei16_v_i8mf8(__VA_ARGS__) -#define vsoxseg4ei16_v_i8mf8(...) __riscv_vsoxseg4ei16_v_i8mf8(__VA_ARGS__) -#define vsoxseg5ei16_v_i8mf8(...) __riscv_vsoxseg5ei16_v_i8mf8(__VA_ARGS__) -#define vsoxseg6ei16_v_i8mf8(...) __riscv_vsoxseg6ei16_v_i8mf8(__VA_ARGS__) -#define vsoxseg7ei16_v_i8mf8(...) __riscv_vsoxseg7ei16_v_i8mf8(__VA_ARGS__) -#define vsoxseg8ei16_v_i8mf8(...) __riscv_vsoxseg8ei16_v_i8mf8(__VA_ARGS__) -#define vsoxseg2ei16_v_i8mf4(...) __riscv_vsoxseg2ei16_v_i8mf4(__VA_ARGS__) -#define vsoxseg3ei16_v_i8mf4(...) __riscv_vsoxseg3ei16_v_i8mf4(__VA_ARGS__) -#define vsoxseg4ei16_v_i8mf4(...) __riscv_vsoxseg4ei16_v_i8mf4(__VA_ARGS__) -#define vsoxseg5ei16_v_i8mf4(...) __riscv_vsoxseg5ei16_v_i8mf4(__VA_ARGS__) -#define vsoxseg6ei16_v_i8mf4(...) __riscv_vsoxseg6ei16_v_i8mf4(__VA_ARGS__) -#define vsoxseg7ei16_v_i8mf4(...) __riscv_vsoxseg7ei16_v_i8mf4(__VA_ARGS__) -#define vsoxseg8ei16_v_i8mf4(...) __riscv_vsoxseg8ei16_v_i8mf4(__VA_ARGS__) -#define vsoxseg2ei16_v_i8mf2(...) __riscv_vsoxseg2ei16_v_i8mf2(__VA_ARGS__) -#define vsoxseg3ei16_v_i8mf2(...) __riscv_vsoxseg3ei16_v_i8mf2(__VA_ARGS__) -#define vsoxseg4ei16_v_i8mf2(...) __riscv_vsoxseg4ei16_v_i8mf2(__VA_ARGS__) -#define vsoxseg5ei16_v_i8mf2(...) __riscv_vsoxseg5ei16_v_i8mf2(__VA_ARGS__) -#define vsoxseg6ei16_v_i8mf2(...) __riscv_vsoxseg6ei16_v_i8mf2(__VA_ARGS__) -#define vsoxseg7ei16_v_i8mf2(...) __riscv_vsoxseg7ei16_v_i8mf2(__VA_ARGS__) -#define vsoxseg8ei16_v_i8mf2(...) __riscv_vsoxseg8ei16_v_i8mf2(__VA_ARGS__) -#define vsoxseg2ei16_v_i8m1(...) __riscv_vsoxseg2ei16_v_i8m1(__VA_ARGS__) -#define vsoxseg3ei16_v_i8m1(...) __riscv_vsoxseg3ei16_v_i8m1(__VA_ARGS__) -#define vsoxseg4ei16_v_i8m1(...) __riscv_vsoxseg4ei16_v_i8m1(__VA_ARGS__) -#define vsoxseg5ei16_v_i8m1(...) __riscv_vsoxseg5ei16_v_i8m1(__VA_ARGS__) -#define vsoxseg6ei16_v_i8m1(...) __riscv_vsoxseg6ei16_v_i8m1(__VA_ARGS__) -#define vsoxseg7ei16_v_i8m1(...) __riscv_vsoxseg7ei16_v_i8m1(__VA_ARGS__) -#define vsoxseg8ei16_v_i8m1(...) __riscv_vsoxseg8ei16_v_i8m1(__VA_ARGS__) -#define vsoxseg2ei16_v_i8m2(...) __riscv_vsoxseg2ei16_v_i8m2(__VA_ARGS__) -#define vsoxseg3ei16_v_i8m2(...) __riscv_vsoxseg3ei16_v_i8m2(__VA_ARGS__) -#define vsoxseg4ei16_v_i8m2(...) __riscv_vsoxseg4ei16_v_i8m2(__VA_ARGS__) -#define vsoxseg2ei16_v_i8m4(...) __riscv_vsoxseg2ei16_v_i8m4(__VA_ARGS__) -#define vsoxseg2ei32_v_i8mf8(...) __riscv_vsoxseg2ei32_v_i8mf8(__VA_ARGS__) -#define vsoxseg3ei32_v_i8mf8(...) __riscv_vsoxseg3ei32_v_i8mf8(__VA_ARGS__) -#define vsoxseg4ei32_v_i8mf8(...) __riscv_vsoxseg4ei32_v_i8mf8(__VA_ARGS__) -#define vsoxseg5ei32_v_i8mf8(...) __riscv_vsoxseg5ei32_v_i8mf8(__VA_ARGS__) -#define vsoxseg6ei32_v_i8mf8(...) __riscv_vsoxseg6ei32_v_i8mf8(__VA_ARGS__) -#define vsoxseg7ei32_v_i8mf8(...) __riscv_vsoxseg7ei32_v_i8mf8(__VA_ARGS__) -#define vsoxseg8ei32_v_i8mf8(...) __riscv_vsoxseg8ei32_v_i8mf8(__VA_ARGS__) -#define vsoxseg2ei32_v_i8mf4(...) __riscv_vsoxseg2ei32_v_i8mf4(__VA_ARGS__) -#define vsoxseg3ei32_v_i8mf4(...) __riscv_vsoxseg3ei32_v_i8mf4(__VA_ARGS__) -#define vsoxseg4ei32_v_i8mf4(...) __riscv_vsoxseg4ei32_v_i8mf4(__VA_ARGS__) -#define vsoxseg5ei32_v_i8mf4(...) __riscv_vsoxseg5ei32_v_i8mf4(__VA_ARGS__) -#define vsoxseg6ei32_v_i8mf4(...) __riscv_vsoxseg6ei32_v_i8mf4(__VA_ARGS__) -#define vsoxseg7ei32_v_i8mf4(...) __riscv_vsoxseg7ei32_v_i8mf4(__VA_ARGS__) -#define vsoxseg8ei32_v_i8mf4(...) __riscv_vsoxseg8ei32_v_i8mf4(__VA_ARGS__) -#define vsoxseg2ei32_v_i8mf2(...) __riscv_vsoxseg2ei32_v_i8mf2(__VA_ARGS__) -#define vsoxseg3ei32_v_i8mf2(...) __riscv_vsoxseg3ei32_v_i8mf2(__VA_ARGS__) -#define vsoxseg4ei32_v_i8mf2(...) __riscv_vsoxseg4ei32_v_i8mf2(__VA_ARGS__) -#define vsoxseg5ei32_v_i8mf2(...) __riscv_vsoxseg5ei32_v_i8mf2(__VA_ARGS__) -#define vsoxseg6ei32_v_i8mf2(...) __riscv_vsoxseg6ei32_v_i8mf2(__VA_ARGS__) -#define vsoxseg7ei32_v_i8mf2(...) __riscv_vsoxseg7ei32_v_i8mf2(__VA_ARGS__) -#define vsoxseg8ei32_v_i8mf2(...) __riscv_vsoxseg8ei32_v_i8mf2(__VA_ARGS__) -#define vsoxseg2ei32_v_i8m1(...) __riscv_vsoxseg2ei32_v_i8m1(__VA_ARGS__) -#define vsoxseg3ei32_v_i8m1(...) __riscv_vsoxseg3ei32_v_i8m1(__VA_ARGS__) -#define vsoxseg4ei32_v_i8m1(...) __riscv_vsoxseg4ei32_v_i8m1(__VA_ARGS__) -#define vsoxseg5ei32_v_i8m1(...) __riscv_vsoxseg5ei32_v_i8m1(__VA_ARGS__) -#define vsoxseg6ei32_v_i8m1(...) __riscv_vsoxseg6ei32_v_i8m1(__VA_ARGS__) -#define vsoxseg7ei32_v_i8m1(...) __riscv_vsoxseg7ei32_v_i8m1(__VA_ARGS__) -#define vsoxseg8ei32_v_i8m1(...) __riscv_vsoxseg8ei32_v_i8m1(__VA_ARGS__) -#define vsoxseg2ei32_v_i8m2(...) __riscv_vsoxseg2ei32_v_i8m2(__VA_ARGS__) -#define vsoxseg3ei32_v_i8m2(...) __riscv_vsoxseg3ei32_v_i8m2(__VA_ARGS__) -#define vsoxseg4ei32_v_i8m2(...) __riscv_vsoxseg4ei32_v_i8m2(__VA_ARGS__) -#define vsoxseg2ei64_v_i8mf8(...) __riscv_vsoxseg2ei64_v_i8mf8(__VA_ARGS__) -#define vsoxseg3ei64_v_i8mf8(...) __riscv_vsoxseg3ei64_v_i8mf8(__VA_ARGS__) -#define vsoxseg4ei64_v_i8mf8(...) __riscv_vsoxseg4ei64_v_i8mf8(__VA_ARGS__) -#define vsoxseg5ei64_v_i8mf8(...) __riscv_vsoxseg5ei64_v_i8mf8(__VA_ARGS__) -#define vsoxseg6ei64_v_i8mf8(...) __riscv_vsoxseg6ei64_v_i8mf8(__VA_ARGS__) -#define vsoxseg7ei64_v_i8mf8(...) __riscv_vsoxseg7ei64_v_i8mf8(__VA_ARGS__) -#define vsoxseg8ei64_v_i8mf8(...) __riscv_vsoxseg8ei64_v_i8mf8(__VA_ARGS__) -#define vsoxseg2ei64_v_i8mf4(...) __riscv_vsoxseg2ei64_v_i8mf4(__VA_ARGS__) -#define vsoxseg3ei64_v_i8mf4(...) __riscv_vsoxseg3ei64_v_i8mf4(__VA_ARGS__) -#define vsoxseg4ei64_v_i8mf4(...) __riscv_vsoxseg4ei64_v_i8mf4(__VA_ARGS__) -#define vsoxseg5ei64_v_i8mf4(...) __riscv_vsoxseg5ei64_v_i8mf4(__VA_ARGS__) -#define vsoxseg6ei64_v_i8mf4(...) __riscv_vsoxseg6ei64_v_i8mf4(__VA_ARGS__) -#define vsoxseg7ei64_v_i8mf4(...) __riscv_vsoxseg7ei64_v_i8mf4(__VA_ARGS__) -#define vsoxseg8ei64_v_i8mf4(...) __riscv_vsoxseg8ei64_v_i8mf4(__VA_ARGS__) -#define vsoxseg2ei64_v_i8mf2(...) __riscv_vsoxseg2ei64_v_i8mf2(__VA_ARGS__) -#define vsoxseg3ei64_v_i8mf2(...) __riscv_vsoxseg3ei64_v_i8mf2(__VA_ARGS__) -#define vsoxseg4ei64_v_i8mf2(...) __riscv_vsoxseg4ei64_v_i8mf2(__VA_ARGS__) -#define vsoxseg5ei64_v_i8mf2(...) __riscv_vsoxseg5ei64_v_i8mf2(__VA_ARGS__) -#define vsoxseg6ei64_v_i8mf2(...) __riscv_vsoxseg6ei64_v_i8mf2(__VA_ARGS__) -#define vsoxseg7ei64_v_i8mf2(...) __riscv_vsoxseg7ei64_v_i8mf2(__VA_ARGS__) -#define vsoxseg8ei64_v_i8mf2(...) __riscv_vsoxseg8ei64_v_i8mf2(__VA_ARGS__) -#define vsoxseg2ei64_v_i8m1(...) __riscv_vsoxseg2ei64_v_i8m1(__VA_ARGS__) -#define vsoxseg3ei64_v_i8m1(...) __riscv_vsoxseg3ei64_v_i8m1(__VA_ARGS__) -#define vsoxseg4ei64_v_i8m1(...) __riscv_vsoxseg4ei64_v_i8m1(__VA_ARGS__) -#define vsoxseg5ei64_v_i8m1(...) __riscv_vsoxseg5ei64_v_i8m1(__VA_ARGS__) -#define vsoxseg6ei64_v_i8m1(...) __riscv_vsoxseg6ei64_v_i8m1(__VA_ARGS__) -#define vsoxseg7ei64_v_i8m1(...) __riscv_vsoxseg7ei64_v_i8m1(__VA_ARGS__) -#define vsoxseg8ei64_v_i8m1(...) __riscv_vsoxseg8ei64_v_i8m1(__VA_ARGS__) -#define vsoxseg2ei8_v_i16mf4(...) __riscv_vsoxseg2ei8_v_i16mf4(__VA_ARGS__) -#define vsoxseg3ei8_v_i16mf4(...) __riscv_vsoxseg3ei8_v_i16mf4(__VA_ARGS__) -#define vsoxseg4ei8_v_i16mf4(...) __riscv_vsoxseg4ei8_v_i16mf4(__VA_ARGS__) -#define vsoxseg5ei8_v_i16mf4(...) __riscv_vsoxseg5ei8_v_i16mf4(__VA_ARGS__) -#define vsoxseg6ei8_v_i16mf4(...) __riscv_vsoxseg6ei8_v_i16mf4(__VA_ARGS__) -#define vsoxseg7ei8_v_i16mf4(...) __riscv_vsoxseg7ei8_v_i16mf4(__VA_ARGS__) -#define vsoxseg8ei8_v_i16mf4(...) __riscv_vsoxseg8ei8_v_i16mf4(__VA_ARGS__) -#define vsoxseg2ei8_v_i16mf2(...) __riscv_vsoxseg2ei8_v_i16mf2(__VA_ARGS__) -#define vsoxseg3ei8_v_i16mf2(...) __riscv_vsoxseg3ei8_v_i16mf2(__VA_ARGS__) -#define vsoxseg4ei8_v_i16mf2(...) __riscv_vsoxseg4ei8_v_i16mf2(__VA_ARGS__) -#define vsoxseg5ei8_v_i16mf2(...) __riscv_vsoxseg5ei8_v_i16mf2(__VA_ARGS__) -#define vsoxseg6ei8_v_i16mf2(...) __riscv_vsoxseg6ei8_v_i16mf2(__VA_ARGS__) -#define vsoxseg7ei8_v_i16mf2(...) __riscv_vsoxseg7ei8_v_i16mf2(__VA_ARGS__) -#define vsoxseg8ei8_v_i16mf2(...) __riscv_vsoxseg8ei8_v_i16mf2(__VA_ARGS__) -#define vsoxseg2ei8_v_i16m1(...) __riscv_vsoxseg2ei8_v_i16m1(__VA_ARGS__) -#define vsoxseg3ei8_v_i16m1(...) __riscv_vsoxseg3ei8_v_i16m1(__VA_ARGS__) -#define vsoxseg4ei8_v_i16m1(...) __riscv_vsoxseg4ei8_v_i16m1(__VA_ARGS__) -#define vsoxseg5ei8_v_i16m1(...) __riscv_vsoxseg5ei8_v_i16m1(__VA_ARGS__) -#define vsoxseg6ei8_v_i16m1(...) __riscv_vsoxseg6ei8_v_i16m1(__VA_ARGS__) -#define vsoxseg7ei8_v_i16m1(...) __riscv_vsoxseg7ei8_v_i16m1(__VA_ARGS__) -#define vsoxseg8ei8_v_i16m1(...) __riscv_vsoxseg8ei8_v_i16m1(__VA_ARGS__) -#define vsoxseg2ei8_v_i16m2(...) __riscv_vsoxseg2ei8_v_i16m2(__VA_ARGS__) -#define vsoxseg3ei8_v_i16m2(...) __riscv_vsoxseg3ei8_v_i16m2(__VA_ARGS__) -#define vsoxseg4ei8_v_i16m2(...) __riscv_vsoxseg4ei8_v_i16m2(__VA_ARGS__) -#define vsoxseg2ei8_v_i16m4(...) __riscv_vsoxseg2ei8_v_i16m4(__VA_ARGS__) -#define vsoxseg2ei16_v_i16mf4(...) __riscv_vsoxseg2ei16_v_i16mf4(__VA_ARGS__) -#define vsoxseg3ei16_v_i16mf4(...) __riscv_vsoxseg3ei16_v_i16mf4(__VA_ARGS__) -#define vsoxseg4ei16_v_i16mf4(...) __riscv_vsoxseg4ei16_v_i16mf4(__VA_ARGS__) -#define vsoxseg5ei16_v_i16mf4(...) __riscv_vsoxseg5ei16_v_i16mf4(__VA_ARGS__) -#define vsoxseg6ei16_v_i16mf4(...) __riscv_vsoxseg6ei16_v_i16mf4(__VA_ARGS__) -#define vsoxseg7ei16_v_i16mf4(...) __riscv_vsoxseg7ei16_v_i16mf4(__VA_ARGS__) -#define vsoxseg8ei16_v_i16mf4(...) __riscv_vsoxseg8ei16_v_i16mf4(__VA_ARGS__) -#define vsoxseg2ei16_v_i16mf2(...) __riscv_vsoxseg2ei16_v_i16mf2(__VA_ARGS__) -#define vsoxseg3ei16_v_i16mf2(...) __riscv_vsoxseg3ei16_v_i16mf2(__VA_ARGS__) -#define vsoxseg4ei16_v_i16mf2(...) __riscv_vsoxseg4ei16_v_i16mf2(__VA_ARGS__) -#define vsoxseg5ei16_v_i16mf2(...) __riscv_vsoxseg5ei16_v_i16mf2(__VA_ARGS__) -#define vsoxseg6ei16_v_i16mf2(...) __riscv_vsoxseg6ei16_v_i16mf2(__VA_ARGS__) -#define vsoxseg7ei16_v_i16mf2(...) __riscv_vsoxseg7ei16_v_i16mf2(__VA_ARGS__) -#define vsoxseg8ei16_v_i16mf2(...) __riscv_vsoxseg8ei16_v_i16mf2(__VA_ARGS__) -#define vsoxseg2ei16_v_i16m1(...) __riscv_vsoxseg2ei16_v_i16m1(__VA_ARGS__) -#define vsoxseg3ei16_v_i16m1(...) __riscv_vsoxseg3ei16_v_i16m1(__VA_ARGS__) -#define vsoxseg4ei16_v_i16m1(...) __riscv_vsoxseg4ei16_v_i16m1(__VA_ARGS__) -#define vsoxseg5ei16_v_i16m1(...) __riscv_vsoxseg5ei16_v_i16m1(__VA_ARGS__) -#define vsoxseg6ei16_v_i16m1(...) __riscv_vsoxseg6ei16_v_i16m1(__VA_ARGS__) -#define vsoxseg7ei16_v_i16m1(...) __riscv_vsoxseg7ei16_v_i16m1(__VA_ARGS__) -#define vsoxseg8ei16_v_i16m1(...) __riscv_vsoxseg8ei16_v_i16m1(__VA_ARGS__) -#define vsoxseg2ei16_v_i16m2(...) __riscv_vsoxseg2ei16_v_i16m2(__VA_ARGS__) -#define vsoxseg3ei16_v_i16m2(...) __riscv_vsoxseg3ei16_v_i16m2(__VA_ARGS__) -#define vsoxseg4ei16_v_i16m2(...) __riscv_vsoxseg4ei16_v_i16m2(__VA_ARGS__) -#define vsoxseg2ei16_v_i16m4(...) __riscv_vsoxseg2ei16_v_i16m4(__VA_ARGS__) -#define vsoxseg2ei32_v_i16mf4(...) __riscv_vsoxseg2ei32_v_i16mf4(__VA_ARGS__) -#define vsoxseg3ei32_v_i16mf4(...) __riscv_vsoxseg3ei32_v_i16mf4(__VA_ARGS__) -#define vsoxseg4ei32_v_i16mf4(...) __riscv_vsoxseg4ei32_v_i16mf4(__VA_ARGS__) -#define vsoxseg5ei32_v_i16mf4(...) __riscv_vsoxseg5ei32_v_i16mf4(__VA_ARGS__) -#define vsoxseg6ei32_v_i16mf4(...) __riscv_vsoxseg6ei32_v_i16mf4(__VA_ARGS__) -#define vsoxseg7ei32_v_i16mf4(...) __riscv_vsoxseg7ei32_v_i16mf4(__VA_ARGS__) -#define vsoxseg8ei32_v_i16mf4(...) __riscv_vsoxseg8ei32_v_i16mf4(__VA_ARGS__) -#define vsoxseg2ei32_v_i16mf2(...) __riscv_vsoxseg2ei32_v_i16mf2(__VA_ARGS__) -#define vsoxseg3ei32_v_i16mf2(...) __riscv_vsoxseg3ei32_v_i16mf2(__VA_ARGS__) -#define vsoxseg4ei32_v_i16mf2(...) __riscv_vsoxseg4ei32_v_i16mf2(__VA_ARGS__) -#define vsoxseg5ei32_v_i16mf2(...) __riscv_vsoxseg5ei32_v_i16mf2(__VA_ARGS__) -#define vsoxseg6ei32_v_i16mf2(...) __riscv_vsoxseg6ei32_v_i16mf2(__VA_ARGS__) -#define vsoxseg7ei32_v_i16mf2(...) __riscv_vsoxseg7ei32_v_i16mf2(__VA_ARGS__) -#define vsoxseg8ei32_v_i16mf2(...) __riscv_vsoxseg8ei32_v_i16mf2(__VA_ARGS__) -#define vsoxseg2ei32_v_i16m1(...) __riscv_vsoxseg2ei32_v_i16m1(__VA_ARGS__) -#define vsoxseg3ei32_v_i16m1(...) __riscv_vsoxseg3ei32_v_i16m1(__VA_ARGS__) -#define vsoxseg4ei32_v_i16m1(...) __riscv_vsoxseg4ei32_v_i16m1(__VA_ARGS__) -#define vsoxseg5ei32_v_i16m1(...) __riscv_vsoxseg5ei32_v_i16m1(__VA_ARGS__) -#define vsoxseg6ei32_v_i16m1(...) __riscv_vsoxseg6ei32_v_i16m1(__VA_ARGS__) -#define vsoxseg7ei32_v_i16m1(...) __riscv_vsoxseg7ei32_v_i16m1(__VA_ARGS__) -#define vsoxseg8ei32_v_i16m1(...) __riscv_vsoxseg8ei32_v_i16m1(__VA_ARGS__) -#define vsoxseg2ei32_v_i16m2(...) __riscv_vsoxseg2ei32_v_i16m2(__VA_ARGS__) -#define vsoxseg3ei32_v_i16m2(...) __riscv_vsoxseg3ei32_v_i16m2(__VA_ARGS__) -#define vsoxseg4ei32_v_i16m2(...) __riscv_vsoxseg4ei32_v_i16m2(__VA_ARGS__) -#define vsoxseg2ei32_v_i16m4(...) __riscv_vsoxseg2ei32_v_i16m4(__VA_ARGS__) -#define vsoxseg2ei64_v_i16mf4(...) __riscv_vsoxseg2ei64_v_i16mf4(__VA_ARGS__) -#define vsoxseg3ei64_v_i16mf4(...) __riscv_vsoxseg3ei64_v_i16mf4(__VA_ARGS__) -#define vsoxseg4ei64_v_i16mf4(...) __riscv_vsoxseg4ei64_v_i16mf4(__VA_ARGS__) -#define vsoxseg5ei64_v_i16mf4(...) __riscv_vsoxseg5ei64_v_i16mf4(__VA_ARGS__) -#define vsoxseg6ei64_v_i16mf4(...) __riscv_vsoxseg6ei64_v_i16mf4(__VA_ARGS__) -#define vsoxseg7ei64_v_i16mf4(...) __riscv_vsoxseg7ei64_v_i16mf4(__VA_ARGS__) -#define vsoxseg8ei64_v_i16mf4(...) __riscv_vsoxseg8ei64_v_i16mf4(__VA_ARGS__) -#define vsoxseg2ei64_v_i16mf2(...) __riscv_vsoxseg2ei64_v_i16mf2(__VA_ARGS__) -#define vsoxseg3ei64_v_i16mf2(...) __riscv_vsoxseg3ei64_v_i16mf2(__VA_ARGS__) -#define vsoxseg4ei64_v_i16mf2(...) __riscv_vsoxseg4ei64_v_i16mf2(__VA_ARGS__) -#define vsoxseg5ei64_v_i16mf2(...) __riscv_vsoxseg5ei64_v_i16mf2(__VA_ARGS__) -#define vsoxseg6ei64_v_i16mf2(...) __riscv_vsoxseg6ei64_v_i16mf2(__VA_ARGS__) -#define vsoxseg7ei64_v_i16mf2(...) __riscv_vsoxseg7ei64_v_i16mf2(__VA_ARGS__) -#define vsoxseg8ei64_v_i16mf2(...) __riscv_vsoxseg8ei64_v_i16mf2(__VA_ARGS__) -#define vsoxseg2ei64_v_i16m1(...) __riscv_vsoxseg2ei64_v_i16m1(__VA_ARGS__) -#define vsoxseg3ei64_v_i16m1(...) __riscv_vsoxseg3ei64_v_i16m1(__VA_ARGS__) -#define vsoxseg4ei64_v_i16m1(...) __riscv_vsoxseg4ei64_v_i16m1(__VA_ARGS__) -#define vsoxseg5ei64_v_i16m1(...) __riscv_vsoxseg5ei64_v_i16m1(__VA_ARGS__) -#define vsoxseg6ei64_v_i16m1(...) __riscv_vsoxseg6ei64_v_i16m1(__VA_ARGS__) -#define vsoxseg7ei64_v_i16m1(...) __riscv_vsoxseg7ei64_v_i16m1(__VA_ARGS__) -#define vsoxseg8ei64_v_i16m1(...) __riscv_vsoxseg8ei64_v_i16m1(__VA_ARGS__) -#define vsoxseg2ei64_v_i16m2(...) __riscv_vsoxseg2ei64_v_i16m2(__VA_ARGS__) -#define vsoxseg3ei64_v_i16m2(...) __riscv_vsoxseg3ei64_v_i16m2(__VA_ARGS__) -#define vsoxseg4ei64_v_i16m2(...) __riscv_vsoxseg4ei64_v_i16m2(__VA_ARGS__) -#define vsoxseg2ei8_v_i32mf2(...) __riscv_vsoxseg2ei8_v_i32mf2(__VA_ARGS__) -#define vsoxseg3ei8_v_i32mf2(...) __riscv_vsoxseg3ei8_v_i32mf2(__VA_ARGS__) -#define vsoxseg4ei8_v_i32mf2(...) __riscv_vsoxseg4ei8_v_i32mf2(__VA_ARGS__) -#define vsoxseg5ei8_v_i32mf2(...) __riscv_vsoxseg5ei8_v_i32mf2(__VA_ARGS__) -#define vsoxseg6ei8_v_i32mf2(...) __riscv_vsoxseg6ei8_v_i32mf2(__VA_ARGS__) -#define vsoxseg7ei8_v_i32mf2(...) __riscv_vsoxseg7ei8_v_i32mf2(__VA_ARGS__) -#define vsoxseg8ei8_v_i32mf2(...) __riscv_vsoxseg8ei8_v_i32mf2(__VA_ARGS__) -#define vsoxseg2ei8_v_i32m1(...) __riscv_vsoxseg2ei8_v_i32m1(__VA_ARGS__) -#define vsoxseg3ei8_v_i32m1(...) __riscv_vsoxseg3ei8_v_i32m1(__VA_ARGS__) -#define vsoxseg4ei8_v_i32m1(...) __riscv_vsoxseg4ei8_v_i32m1(__VA_ARGS__) -#define vsoxseg5ei8_v_i32m1(...) __riscv_vsoxseg5ei8_v_i32m1(__VA_ARGS__) -#define vsoxseg6ei8_v_i32m1(...) __riscv_vsoxseg6ei8_v_i32m1(__VA_ARGS__) -#define vsoxseg7ei8_v_i32m1(...) __riscv_vsoxseg7ei8_v_i32m1(__VA_ARGS__) -#define vsoxseg8ei8_v_i32m1(...) __riscv_vsoxseg8ei8_v_i32m1(__VA_ARGS__) -#define vsoxseg2ei8_v_i32m2(...) __riscv_vsoxseg2ei8_v_i32m2(__VA_ARGS__) -#define vsoxseg3ei8_v_i32m2(...) __riscv_vsoxseg3ei8_v_i32m2(__VA_ARGS__) -#define vsoxseg4ei8_v_i32m2(...) __riscv_vsoxseg4ei8_v_i32m2(__VA_ARGS__) -#define vsoxseg2ei8_v_i32m4(...) __riscv_vsoxseg2ei8_v_i32m4(__VA_ARGS__) -#define vsoxseg2ei16_v_i32mf2(...) __riscv_vsoxseg2ei16_v_i32mf2(__VA_ARGS__) -#define vsoxseg3ei16_v_i32mf2(...) __riscv_vsoxseg3ei16_v_i32mf2(__VA_ARGS__) -#define vsoxseg4ei16_v_i32mf2(...) __riscv_vsoxseg4ei16_v_i32mf2(__VA_ARGS__) -#define vsoxseg5ei16_v_i32mf2(...) __riscv_vsoxseg5ei16_v_i32mf2(__VA_ARGS__) -#define vsoxseg6ei16_v_i32mf2(...) __riscv_vsoxseg6ei16_v_i32mf2(__VA_ARGS__) -#define vsoxseg7ei16_v_i32mf2(...) __riscv_vsoxseg7ei16_v_i32mf2(__VA_ARGS__) -#define vsoxseg8ei16_v_i32mf2(...) __riscv_vsoxseg8ei16_v_i32mf2(__VA_ARGS__) -#define vsoxseg2ei16_v_i32m1(...) __riscv_vsoxseg2ei16_v_i32m1(__VA_ARGS__) -#define vsoxseg3ei16_v_i32m1(...) __riscv_vsoxseg3ei16_v_i32m1(__VA_ARGS__) -#define vsoxseg4ei16_v_i32m1(...) __riscv_vsoxseg4ei16_v_i32m1(__VA_ARGS__) -#define vsoxseg5ei16_v_i32m1(...) __riscv_vsoxseg5ei16_v_i32m1(__VA_ARGS__) -#define vsoxseg6ei16_v_i32m1(...) __riscv_vsoxseg6ei16_v_i32m1(__VA_ARGS__) -#define vsoxseg7ei16_v_i32m1(...) __riscv_vsoxseg7ei16_v_i32m1(__VA_ARGS__) -#define vsoxseg8ei16_v_i32m1(...) __riscv_vsoxseg8ei16_v_i32m1(__VA_ARGS__) -#define vsoxseg2ei16_v_i32m2(...) __riscv_vsoxseg2ei16_v_i32m2(__VA_ARGS__) -#define vsoxseg3ei16_v_i32m2(...) __riscv_vsoxseg3ei16_v_i32m2(__VA_ARGS__) -#define vsoxseg4ei16_v_i32m2(...) __riscv_vsoxseg4ei16_v_i32m2(__VA_ARGS__) -#define vsoxseg2ei16_v_i32m4(...) __riscv_vsoxseg2ei16_v_i32m4(__VA_ARGS__) -#define vsoxseg2ei32_v_i32mf2(...) __riscv_vsoxseg2ei32_v_i32mf2(__VA_ARGS__) -#define vsoxseg3ei32_v_i32mf2(...) __riscv_vsoxseg3ei32_v_i32mf2(__VA_ARGS__) -#define vsoxseg4ei32_v_i32mf2(...) __riscv_vsoxseg4ei32_v_i32mf2(__VA_ARGS__) -#define vsoxseg5ei32_v_i32mf2(...) __riscv_vsoxseg5ei32_v_i32mf2(__VA_ARGS__) -#define vsoxseg6ei32_v_i32mf2(...) __riscv_vsoxseg6ei32_v_i32mf2(__VA_ARGS__) -#define vsoxseg7ei32_v_i32mf2(...) __riscv_vsoxseg7ei32_v_i32mf2(__VA_ARGS__) -#define vsoxseg8ei32_v_i32mf2(...) __riscv_vsoxseg8ei32_v_i32mf2(__VA_ARGS__) -#define vsoxseg2ei32_v_i32m1(...) __riscv_vsoxseg2ei32_v_i32m1(__VA_ARGS__) -#define vsoxseg3ei32_v_i32m1(...) __riscv_vsoxseg3ei32_v_i32m1(__VA_ARGS__) -#define vsoxseg4ei32_v_i32m1(...) __riscv_vsoxseg4ei32_v_i32m1(__VA_ARGS__) -#define vsoxseg5ei32_v_i32m1(...) __riscv_vsoxseg5ei32_v_i32m1(__VA_ARGS__) -#define vsoxseg6ei32_v_i32m1(...) __riscv_vsoxseg6ei32_v_i32m1(__VA_ARGS__) -#define vsoxseg7ei32_v_i32m1(...) __riscv_vsoxseg7ei32_v_i32m1(__VA_ARGS__) -#define vsoxseg8ei32_v_i32m1(...) __riscv_vsoxseg8ei32_v_i32m1(__VA_ARGS__) -#define vsoxseg2ei32_v_i32m2(...) __riscv_vsoxseg2ei32_v_i32m2(__VA_ARGS__) -#define vsoxseg3ei32_v_i32m2(...) __riscv_vsoxseg3ei32_v_i32m2(__VA_ARGS__) -#define vsoxseg4ei32_v_i32m2(...) __riscv_vsoxseg4ei32_v_i32m2(__VA_ARGS__) -#define vsoxseg2ei32_v_i32m4(...) __riscv_vsoxseg2ei32_v_i32m4(__VA_ARGS__) -#define vsoxseg2ei64_v_i32mf2(...) __riscv_vsoxseg2ei64_v_i32mf2(__VA_ARGS__) -#define vsoxseg3ei64_v_i32mf2(...) __riscv_vsoxseg3ei64_v_i32mf2(__VA_ARGS__) -#define vsoxseg4ei64_v_i32mf2(...) __riscv_vsoxseg4ei64_v_i32mf2(__VA_ARGS__) -#define vsoxseg5ei64_v_i32mf2(...) __riscv_vsoxseg5ei64_v_i32mf2(__VA_ARGS__) -#define vsoxseg6ei64_v_i32mf2(...) __riscv_vsoxseg6ei64_v_i32mf2(__VA_ARGS__) -#define vsoxseg7ei64_v_i32mf2(...) __riscv_vsoxseg7ei64_v_i32mf2(__VA_ARGS__) -#define vsoxseg8ei64_v_i32mf2(...) __riscv_vsoxseg8ei64_v_i32mf2(__VA_ARGS__) -#define vsoxseg2ei64_v_i32m1(...) __riscv_vsoxseg2ei64_v_i32m1(__VA_ARGS__) -#define vsoxseg3ei64_v_i32m1(...) __riscv_vsoxseg3ei64_v_i32m1(__VA_ARGS__) -#define vsoxseg4ei64_v_i32m1(...) __riscv_vsoxseg4ei64_v_i32m1(__VA_ARGS__) -#define vsoxseg5ei64_v_i32m1(...) __riscv_vsoxseg5ei64_v_i32m1(__VA_ARGS__) -#define vsoxseg6ei64_v_i32m1(...) __riscv_vsoxseg6ei64_v_i32m1(__VA_ARGS__) -#define vsoxseg7ei64_v_i32m1(...) __riscv_vsoxseg7ei64_v_i32m1(__VA_ARGS__) -#define vsoxseg8ei64_v_i32m1(...) __riscv_vsoxseg8ei64_v_i32m1(__VA_ARGS__) -#define vsoxseg2ei64_v_i32m2(...) __riscv_vsoxseg2ei64_v_i32m2(__VA_ARGS__) -#define vsoxseg3ei64_v_i32m2(...) __riscv_vsoxseg3ei64_v_i32m2(__VA_ARGS__) -#define vsoxseg4ei64_v_i32m2(...) __riscv_vsoxseg4ei64_v_i32m2(__VA_ARGS__) -#define vsoxseg2ei64_v_i32m4(...) __riscv_vsoxseg2ei64_v_i32m4(__VA_ARGS__) -#define vsoxseg2ei8_v_i64m1(...) __riscv_vsoxseg2ei8_v_i64m1(__VA_ARGS__) -#define vsoxseg3ei8_v_i64m1(...) __riscv_vsoxseg3ei8_v_i64m1(__VA_ARGS__) -#define vsoxseg4ei8_v_i64m1(...) __riscv_vsoxseg4ei8_v_i64m1(__VA_ARGS__) -#define vsoxseg5ei8_v_i64m1(...) __riscv_vsoxseg5ei8_v_i64m1(__VA_ARGS__) -#define vsoxseg6ei8_v_i64m1(...) __riscv_vsoxseg6ei8_v_i64m1(__VA_ARGS__) -#define vsoxseg7ei8_v_i64m1(...) __riscv_vsoxseg7ei8_v_i64m1(__VA_ARGS__) -#define vsoxseg8ei8_v_i64m1(...) __riscv_vsoxseg8ei8_v_i64m1(__VA_ARGS__) -#define vsoxseg2ei8_v_i64m2(...) __riscv_vsoxseg2ei8_v_i64m2(__VA_ARGS__) -#define vsoxseg3ei8_v_i64m2(...) __riscv_vsoxseg3ei8_v_i64m2(__VA_ARGS__) -#define vsoxseg4ei8_v_i64m2(...) __riscv_vsoxseg4ei8_v_i64m2(__VA_ARGS__) -#define vsoxseg2ei8_v_i64m4(...) __riscv_vsoxseg2ei8_v_i64m4(__VA_ARGS__) -#define vsoxseg2ei16_v_i64m1(...) __riscv_vsoxseg2ei16_v_i64m1(__VA_ARGS__) -#define vsoxseg3ei16_v_i64m1(...) __riscv_vsoxseg3ei16_v_i64m1(__VA_ARGS__) -#define vsoxseg4ei16_v_i64m1(...) __riscv_vsoxseg4ei16_v_i64m1(__VA_ARGS__) -#define vsoxseg5ei16_v_i64m1(...) __riscv_vsoxseg5ei16_v_i64m1(__VA_ARGS__) -#define vsoxseg6ei16_v_i64m1(...) __riscv_vsoxseg6ei16_v_i64m1(__VA_ARGS__) -#define vsoxseg7ei16_v_i64m1(...) __riscv_vsoxseg7ei16_v_i64m1(__VA_ARGS__) -#define vsoxseg8ei16_v_i64m1(...) __riscv_vsoxseg8ei16_v_i64m1(__VA_ARGS__) -#define vsoxseg2ei16_v_i64m2(...) __riscv_vsoxseg2ei16_v_i64m2(__VA_ARGS__) -#define vsoxseg3ei16_v_i64m2(...) __riscv_vsoxseg3ei16_v_i64m2(__VA_ARGS__) -#define vsoxseg4ei16_v_i64m2(...) __riscv_vsoxseg4ei16_v_i64m2(__VA_ARGS__) -#define vsoxseg2ei16_v_i64m4(...) __riscv_vsoxseg2ei16_v_i64m4(__VA_ARGS__) -#define vsoxseg2ei32_v_i64m1(...) __riscv_vsoxseg2ei32_v_i64m1(__VA_ARGS__) -#define vsoxseg3ei32_v_i64m1(...) __riscv_vsoxseg3ei32_v_i64m1(__VA_ARGS__) -#define vsoxseg4ei32_v_i64m1(...) __riscv_vsoxseg4ei32_v_i64m1(__VA_ARGS__) -#define vsoxseg5ei32_v_i64m1(...) __riscv_vsoxseg5ei32_v_i64m1(__VA_ARGS__) -#define vsoxseg6ei32_v_i64m1(...) __riscv_vsoxseg6ei32_v_i64m1(__VA_ARGS__) -#define vsoxseg7ei32_v_i64m1(...) __riscv_vsoxseg7ei32_v_i64m1(__VA_ARGS__) -#define vsoxseg8ei32_v_i64m1(...) __riscv_vsoxseg8ei32_v_i64m1(__VA_ARGS__) -#define vsoxseg2ei32_v_i64m2(...) __riscv_vsoxseg2ei32_v_i64m2(__VA_ARGS__) -#define vsoxseg3ei32_v_i64m2(...) __riscv_vsoxseg3ei32_v_i64m2(__VA_ARGS__) -#define vsoxseg4ei32_v_i64m2(...) __riscv_vsoxseg4ei32_v_i64m2(__VA_ARGS__) -#define vsoxseg2ei32_v_i64m4(...) __riscv_vsoxseg2ei32_v_i64m4(__VA_ARGS__) -#define vsoxseg2ei64_v_i64m1(...) __riscv_vsoxseg2ei64_v_i64m1(__VA_ARGS__) -#define vsoxseg3ei64_v_i64m1(...) __riscv_vsoxseg3ei64_v_i64m1(__VA_ARGS__) -#define vsoxseg4ei64_v_i64m1(...) __riscv_vsoxseg4ei64_v_i64m1(__VA_ARGS__) -#define vsoxseg5ei64_v_i64m1(...) __riscv_vsoxseg5ei64_v_i64m1(__VA_ARGS__) -#define vsoxseg6ei64_v_i64m1(...) __riscv_vsoxseg6ei64_v_i64m1(__VA_ARGS__) -#define vsoxseg7ei64_v_i64m1(...) __riscv_vsoxseg7ei64_v_i64m1(__VA_ARGS__) -#define vsoxseg8ei64_v_i64m1(...) __riscv_vsoxseg8ei64_v_i64m1(__VA_ARGS__) -#define vsoxseg2ei64_v_i64m2(...) __riscv_vsoxseg2ei64_v_i64m2(__VA_ARGS__) -#define vsoxseg3ei64_v_i64m2(...) __riscv_vsoxseg3ei64_v_i64m2(__VA_ARGS__) -#define vsoxseg4ei64_v_i64m2(...) __riscv_vsoxseg4ei64_v_i64m2(__VA_ARGS__) -#define vsoxseg2ei64_v_i64m4(...) __riscv_vsoxseg2ei64_v_i64m4(__VA_ARGS__) -#define vsuxseg2ei8_v_i8mf8(...) __riscv_vsuxseg2ei8_v_i8mf8(__VA_ARGS__) -#define vsuxseg3ei8_v_i8mf8(...) __riscv_vsuxseg3ei8_v_i8mf8(__VA_ARGS__) -#define vsuxseg4ei8_v_i8mf8(...) __riscv_vsuxseg4ei8_v_i8mf8(__VA_ARGS__) -#define vsuxseg5ei8_v_i8mf8(...) __riscv_vsuxseg5ei8_v_i8mf8(__VA_ARGS__) -#define vsuxseg6ei8_v_i8mf8(...) __riscv_vsuxseg6ei8_v_i8mf8(__VA_ARGS__) -#define vsuxseg7ei8_v_i8mf8(...) __riscv_vsuxseg7ei8_v_i8mf8(__VA_ARGS__) -#define vsuxseg8ei8_v_i8mf8(...) __riscv_vsuxseg8ei8_v_i8mf8(__VA_ARGS__) -#define vsuxseg2ei8_v_i8mf4(...) __riscv_vsuxseg2ei8_v_i8mf4(__VA_ARGS__) -#define vsuxseg3ei8_v_i8mf4(...) __riscv_vsuxseg3ei8_v_i8mf4(__VA_ARGS__) -#define vsuxseg4ei8_v_i8mf4(...) __riscv_vsuxseg4ei8_v_i8mf4(__VA_ARGS__) -#define vsuxseg5ei8_v_i8mf4(...) __riscv_vsuxseg5ei8_v_i8mf4(__VA_ARGS__) -#define vsuxseg6ei8_v_i8mf4(...) __riscv_vsuxseg6ei8_v_i8mf4(__VA_ARGS__) -#define vsuxseg7ei8_v_i8mf4(...) __riscv_vsuxseg7ei8_v_i8mf4(__VA_ARGS__) -#define vsuxseg8ei8_v_i8mf4(...) __riscv_vsuxseg8ei8_v_i8mf4(__VA_ARGS__) -#define vsuxseg2ei8_v_i8mf2(...) __riscv_vsuxseg2ei8_v_i8mf2(__VA_ARGS__) -#define vsuxseg3ei8_v_i8mf2(...) __riscv_vsuxseg3ei8_v_i8mf2(__VA_ARGS__) -#define vsuxseg4ei8_v_i8mf2(...) __riscv_vsuxseg4ei8_v_i8mf2(__VA_ARGS__) -#define vsuxseg5ei8_v_i8mf2(...) __riscv_vsuxseg5ei8_v_i8mf2(__VA_ARGS__) -#define vsuxseg6ei8_v_i8mf2(...) __riscv_vsuxseg6ei8_v_i8mf2(__VA_ARGS__) -#define vsuxseg7ei8_v_i8mf2(...) __riscv_vsuxseg7ei8_v_i8mf2(__VA_ARGS__) -#define vsuxseg8ei8_v_i8mf2(...) __riscv_vsuxseg8ei8_v_i8mf2(__VA_ARGS__) -#define vsuxseg2ei8_v_i8m1(...) __riscv_vsuxseg2ei8_v_i8m1(__VA_ARGS__) -#define vsuxseg3ei8_v_i8m1(...) __riscv_vsuxseg3ei8_v_i8m1(__VA_ARGS__) -#define vsuxseg4ei8_v_i8m1(...) __riscv_vsuxseg4ei8_v_i8m1(__VA_ARGS__) -#define vsuxseg5ei8_v_i8m1(...) __riscv_vsuxseg5ei8_v_i8m1(__VA_ARGS__) -#define vsuxseg6ei8_v_i8m1(...) __riscv_vsuxseg6ei8_v_i8m1(__VA_ARGS__) -#define vsuxseg7ei8_v_i8m1(...) __riscv_vsuxseg7ei8_v_i8m1(__VA_ARGS__) -#define vsuxseg8ei8_v_i8m1(...) __riscv_vsuxseg8ei8_v_i8m1(__VA_ARGS__) -#define vsuxseg2ei8_v_i8m2(...) __riscv_vsuxseg2ei8_v_i8m2(__VA_ARGS__) -#define vsuxseg3ei8_v_i8m2(...) __riscv_vsuxseg3ei8_v_i8m2(__VA_ARGS__) -#define vsuxseg4ei8_v_i8m2(...) __riscv_vsuxseg4ei8_v_i8m2(__VA_ARGS__) -#define vsuxseg2ei8_v_i8m4(...) __riscv_vsuxseg2ei8_v_i8m4(__VA_ARGS__) -#define vsuxseg2ei16_v_i8mf8(...) __riscv_vsuxseg2ei16_v_i8mf8(__VA_ARGS__) -#define vsuxseg3ei16_v_i8mf8(...) __riscv_vsuxseg3ei16_v_i8mf8(__VA_ARGS__) -#define vsuxseg4ei16_v_i8mf8(...) __riscv_vsuxseg4ei16_v_i8mf8(__VA_ARGS__) -#define vsuxseg5ei16_v_i8mf8(...) __riscv_vsuxseg5ei16_v_i8mf8(__VA_ARGS__) -#define vsuxseg6ei16_v_i8mf8(...) __riscv_vsuxseg6ei16_v_i8mf8(__VA_ARGS__) -#define vsuxseg7ei16_v_i8mf8(...) __riscv_vsuxseg7ei16_v_i8mf8(__VA_ARGS__) -#define vsuxseg8ei16_v_i8mf8(...) __riscv_vsuxseg8ei16_v_i8mf8(__VA_ARGS__) -#define vsuxseg2ei16_v_i8mf4(...) __riscv_vsuxseg2ei16_v_i8mf4(__VA_ARGS__) -#define vsuxseg3ei16_v_i8mf4(...) __riscv_vsuxseg3ei16_v_i8mf4(__VA_ARGS__) -#define vsuxseg4ei16_v_i8mf4(...) __riscv_vsuxseg4ei16_v_i8mf4(__VA_ARGS__) -#define vsuxseg5ei16_v_i8mf4(...) __riscv_vsuxseg5ei16_v_i8mf4(__VA_ARGS__) -#define vsuxseg6ei16_v_i8mf4(...) __riscv_vsuxseg6ei16_v_i8mf4(__VA_ARGS__) -#define vsuxseg7ei16_v_i8mf4(...) __riscv_vsuxseg7ei16_v_i8mf4(__VA_ARGS__) -#define vsuxseg8ei16_v_i8mf4(...) __riscv_vsuxseg8ei16_v_i8mf4(__VA_ARGS__) -#define vsuxseg2ei16_v_i8mf2(...) __riscv_vsuxseg2ei16_v_i8mf2(__VA_ARGS__) -#define vsuxseg3ei16_v_i8mf2(...) __riscv_vsuxseg3ei16_v_i8mf2(__VA_ARGS__) -#define vsuxseg4ei16_v_i8mf2(...) __riscv_vsuxseg4ei16_v_i8mf2(__VA_ARGS__) -#define vsuxseg5ei16_v_i8mf2(...) __riscv_vsuxseg5ei16_v_i8mf2(__VA_ARGS__) -#define vsuxseg6ei16_v_i8mf2(...) __riscv_vsuxseg6ei16_v_i8mf2(__VA_ARGS__) -#define vsuxseg7ei16_v_i8mf2(...) __riscv_vsuxseg7ei16_v_i8mf2(__VA_ARGS__) -#define vsuxseg8ei16_v_i8mf2(...) __riscv_vsuxseg8ei16_v_i8mf2(__VA_ARGS__) -#define vsuxseg2ei16_v_i8m1(...) __riscv_vsuxseg2ei16_v_i8m1(__VA_ARGS__) -#define vsuxseg3ei16_v_i8m1(...) __riscv_vsuxseg3ei16_v_i8m1(__VA_ARGS__) -#define vsuxseg4ei16_v_i8m1(...) __riscv_vsuxseg4ei16_v_i8m1(__VA_ARGS__) -#define vsuxseg5ei16_v_i8m1(...) __riscv_vsuxseg5ei16_v_i8m1(__VA_ARGS__) -#define vsuxseg6ei16_v_i8m1(...) __riscv_vsuxseg6ei16_v_i8m1(__VA_ARGS__) -#define vsuxseg7ei16_v_i8m1(...) __riscv_vsuxseg7ei16_v_i8m1(__VA_ARGS__) -#define vsuxseg8ei16_v_i8m1(...) __riscv_vsuxseg8ei16_v_i8m1(__VA_ARGS__) -#define vsuxseg2ei16_v_i8m2(...) __riscv_vsuxseg2ei16_v_i8m2(__VA_ARGS__) -#define vsuxseg3ei16_v_i8m2(...) __riscv_vsuxseg3ei16_v_i8m2(__VA_ARGS__) -#define vsuxseg4ei16_v_i8m2(...) __riscv_vsuxseg4ei16_v_i8m2(__VA_ARGS__) -#define vsuxseg2ei16_v_i8m4(...) __riscv_vsuxseg2ei16_v_i8m4(__VA_ARGS__) -#define vsuxseg2ei32_v_i8mf8(...) __riscv_vsuxseg2ei32_v_i8mf8(__VA_ARGS__) -#define vsuxseg3ei32_v_i8mf8(...) __riscv_vsuxseg3ei32_v_i8mf8(__VA_ARGS__) -#define vsuxseg4ei32_v_i8mf8(...) __riscv_vsuxseg4ei32_v_i8mf8(__VA_ARGS__) -#define vsuxseg5ei32_v_i8mf8(...) __riscv_vsuxseg5ei32_v_i8mf8(__VA_ARGS__) -#define vsuxseg6ei32_v_i8mf8(...) __riscv_vsuxseg6ei32_v_i8mf8(__VA_ARGS__) -#define vsuxseg7ei32_v_i8mf8(...) __riscv_vsuxseg7ei32_v_i8mf8(__VA_ARGS__) -#define vsuxseg8ei32_v_i8mf8(...) __riscv_vsuxseg8ei32_v_i8mf8(__VA_ARGS__) -#define vsuxseg2ei32_v_i8mf4(...) __riscv_vsuxseg2ei32_v_i8mf4(__VA_ARGS__) -#define vsuxseg3ei32_v_i8mf4(...) __riscv_vsuxseg3ei32_v_i8mf4(__VA_ARGS__) -#define vsuxseg4ei32_v_i8mf4(...) __riscv_vsuxseg4ei32_v_i8mf4(__VA_ARGS__) -#define vsuxseg5ei32_v_i8mf4(...) __riscv_vsuxseg5ei32_v_i8mf4(__VA_ARGS__) -#define vsuxseg6ei32_v_i8mf4(...) __riscv_vsuxseg6ei32_v_i8mf4(__VA_ARGS__) -#define vsuxseg7ei32_v_i8mf4(...) __riscv_vsuxseg7ei32_v_i8mf4(__VA_ARGS__) -#define vsuxseg8ei32_v_i8mf4(...) __riscv_vsuxseg8ei32_v_i8mf4(__VA_ARGS__) -#define vsuxseg2ei32_v_i8mf2(...) __riscv_vsuxseg2ei32_v_i8mf2(__VA_ARGS__) -#define vsuxseg3ei32_v_i8mf2(...) __riscv_vsuxseg3ei32_v_i8mf2(__VA_ARGS__) -#define vsuxseg4ei32_v_i8mf2(...) __riscv_vsuxseg4ei32_v_i8mf2(__VA_ARGS__) -#define vsuxseg5ei32_v_i8mf2(...) __riscv_vsuxseg5ei32_v_i8mf2(__VA_ARGS__) -#define vsuxseg6ei32_v_i8mf2(...) __riscv_vsuxseg6ei32_v_i8mf2(__VA_ARGS__) -#define vsuxseg7ei32_v_i8mf2(...) __riscv_vsuxseg7ei32_v_i8mf2(__VA_ARGS__) -#define vsuxseg8ei32_v_i8mf2(...) __riscv_vsuxseg8ei32_v_i8mf2(__VA_ARGS__) -#define vsuxseg2ei32_v_i8m1(...) __riscv_vsuxseg2ei32_v_i8m1(__VA_ARGS__) -#define vsuxseg3ei32_v_i8m1(...) __riscv_vsuxseg3ei32_v_i8m1(__VA_ARGS__) -#define vsuxseg4ei32_v_i8m1(...) __riscv_vsuxseg4ei32_v_i8m1(__VA_ARGS__) -#define vsuxseg5ei32_v_i8m1(...) __riscv_vsuxseg5ei32_v_i8m1(__VA_ARGS__) -#define vsuxseg6ei32_v_i8m1(...) __riscv_vsuxseg6ei32_v_i8m1(__VA_ARGS__) -#define vsuxseg7ei32_v_i8m1(...) __riscv_vsuxseg7ei32_v_i8m1(__VA_ARGS__) -#define vsuxseg8ei32_v_i8m1(...) __riscv_vsuxseg8ei32_v_i8m1(__VA_ARGS__) -#define vsuxseg2ei32_v_i8m2(...) __riscv_vsuxseg2ei32_v_i8m2(__VA_ARGS__) -#define vsuxseg3ei32_v_i8m2(...) __riscv_vsuxseg3ei32_v_i8m2(__VA_ARGS__) -#define vsuxseg4ei32_v_i8m2(...) __riscv_vsuxseg4ei32_v_i8m2(__VA_ARGS__) -#define vsuxseg2ei64_v_i8mf8(...) __riscv_vsuxseg2ei64_v_i8mf8(__VA_ARGS__) -#define vsuxseg3ei64_v_i8mf8(...) __riscv_vsuxseg3ei64_v_i8mf8(__VA_ARGS__) -#define vsuxseg4ei64_v_i8mf8(...) __riscv_vsuxseg4ei64_v_i8mf8(__VA_ARGS__) -#define vsuxseg5ei64_v_i8mf8(...) __riscv_vsuxseg5ei64_v_i8mf8(__VA_ARGS__) -#define vsuxseg6ei64_v_i8mf8(...) __riscv_vsuxseg6ei64_v_i8mf8(__VA_ARGS__) -#define vsuxseg7ei64_v_i8mf8(...) __riscv_vsuxseg7ei64_v_i8mf8(__VA_ARGS__) -#define vsuxseg8ei64_v_i8mf8(...) __riscv_vsuxseg8ei64_v_i8mf8(__VA_ARGS__) -#define vsuxseg2ei64_v_i8mf4(...) __riscv_vsuxseg2ei64_v_i8mf4(__VA_ARGS__) -#define vsuxseg3ei64_v_i8mf4(...) __riscv_vsuxseg3ei64_v_i8mf4(__VA_ARGS__) -#define vsuxseg4ei64_v_i8mf4(...) __riscv_vsuxseg4ei64_v_i8mf4(__VA_ARGS__) -#define vsuxseg5ei64_v_i8mf4(...) __riscv_vsuxseg5ei64_v_i8mf4(__VA_ARGS__) -#define vsuxseg6ei64_v_i8mf4(...) __riscv_vsuxseg6ei64_v_i8mf4(__VA_ARGS__) -#define vsuxseg7ei64_v_i8mf4(...) __riscv_vsuxseg7ei64_v_i8mf4(__VA_ARGS__) -#define vsuxseg8ei64_v_i8mf4(...) __riscv_vsuxseg8ei64_v_i8mf4(__VA_ARGS__) -#define vsuxseg2ei64_v_i8mf2(...) __riscv_vsuxseg2ei64_v_i8mf2(__VA_ARGS__) -#define vsuxseg3ei64_v_i8mf2(...) __riscv_vsuxseg3ei64_v_i8mf2(__VA_ARGS__) -#define vsuxseg4ei64_v_i8mf2(...) __riscv_vsuxseg4ei64_v_i8mf2(__VA_ARGS__) -#define vsuxseg5ei64_v_i8mf2(...) __riscv_vsuxseg5ei64_v_i8mf2(__VA_ARGS__) -#define vsuxseg6ei64_v_i8mf2(...) __riscv_vsuxseg6ei64_v_i8mf2(__VA_ARGS__) -#define vsuxseg7ei64_v_i8mf2(...) __riscv_vsuxseg7ei64_v_i8mf2(__VA_ARGS__) -#define vsuxseg8ei64_v_i8mf2(...) __riscv_vsuxseg8ei64_v_i8mf2(__VA_ARGS__) -#define vsuxseg2ei64_v_i8m1(...) __riscv_vsuxseg2ei64_v_i8m1(__VA_ARGS__) -#define vsuxseg3ei64_v_i8m1(...) __riscv_vsuxseg3ei64_v_i8m1(__VA_ARGS__) -#define vsuxseg4ei64_v_i8m1(...) __riscv_vsuxseg4ei64_v_i8m1(__VA_ARGS__) -#define vsuxseg5ei64_v_i8m1(...) __riscv_vsuxseg5ei64_v_i8m1(__VA_ARGS__) -#define vsuxseg6ei64_v_i8m1(...) __riscv_vsuxseg6ei64_v_i8m1(__VA_ARGS__) -#define vsuxseg7ei64_v_i8m1(...) __riscv_vsuxseg7ei64_v_i8m1(__VA_ARGS__) -#define vsuxseg8ei64_v_i8m1(...) __riscv_vsuxseg8ei64_v_i8m1(__VA_ARGS__) -#define vsuxseg2ei8_v_i16mf4(...) __riscv_vsuxseg2ei8_v_i16mf4(__VA_ARGS__) -#define vsuxseg3ei8_v_i16mf4(...) __riscv_vsuxseg3ei8_v_i16mf4(__VA_ARGS__) -#define vsuxseg4ei8_v_i16mf4(...) __riscv_vsuxseg4ei8_v_i16mf4(__VA_ARGS__) -#define vsuxseg5ei8_v_i16mf4(...) __riscv_vsuxseg5ei8_v_i16mf4(__VA_ARGS__) -#define vsuxseg6ei8_v_i16mf4(...) __riscv_vsuxseg6ei8_v_i16mf4(__VA_ARGS__) -#define vsuxseg7ei8_v_i16mf4(...) __riscv_vsuxseg7ei8_v_i16mf4(__VA_ARGS__) -#define vsuxseg8ei8_v_i16mf4(...) __riscv_vsuxseg8ei8_v_i16mf4(__VA_ARGS__) -#define vsuxseg2ei8_v_i16mf2(...) __riscv_vsuxseg2ei8_v_i16mf2(__VA_ARGS__) -#define vsuxseg3ei8_v_i16mf2(...) __riscv_vsuxseg3ei8_v_i16mf2(__VA_ARGS__) -#define vsuxseg4ei8_v_i16mf2(...) __riscv_vsuxseg4ei8_v_i16mf2(__VA_ARGS__) -#define vsuxseg5ei8_v_i16mf2(...) __riscv_vsuxseg5ei8_v_i16mf2(__VA_ARGS__) -#define vsuxseg6ei8_v_i16mf2(...) __riscv_vsuxseg6ei8_v_i16mf2(__VA_ARGS__) -#define vsuxseg7ei8_v_i16mf2(...) __riscv_vsuxseg7ei8_v_i16mf2(__VA_ARGS__) -#define vsuxseg8ei8_v_i16mf2(...) __riscv_vsuxseg8ei8_v_i16mf2(__VA_ARGS__) -#define vsuxseg2ei8_v_i16m1(...) __riscv_vsuxseg2ei8_v_i16m1(__VA_ARGS__) -#define vsuxseg3ei8_v_i16m1(...) __riscv_vsuxseg3ei8_v_i16m1(__VA_ARGS__) -#define vsuxseg4ei8_v_i16m1(...) __riscv_vsuxseg4ei8_v_i16m1(__VA_ARGS__) -#define vsuxseg5ei8_v_i16m1(...) __riscv_vsuxseg5ei8_v_i16m1(__VA_ARGS__) -#define vsuxseg6ei8_v_i16m1(...) __riscv_vsuxseg6ei8_v_i16m1(__VA_ARGS__) -#define vsuxseg7ei8_v_i16m1(...) __riscv_vsuxseg7ei8_v_i16m1(__VA_ARGS__) -#define vsuxseg8ei8_v_i16m1(...) __riscv_vsuxseg8ei8_v_i16m1(__VA_ARGS__) -#define vsuxseg2ei8_v_i16m2(...) __riscv_vsuxseg2ei8_v_i16m2(__VA_ARGS__) -#define vsuxseg3ei8_v_i16m2(...) __riscv_vsuxseg3ei8_v_i16m2(__VA_ARGS__) -#define vsuxseg4ei8_v_i16m2(...) __riscv_vsuxseg4ei8_v_i16m2(__VA_ARGS__) -#define vsuxseg2ei8_v_i16m4(...) __riscv_vsuxseg2ei8_v_i16m4(__VA_ARGS__) -#define vsuxseg2ei16_v_i16mf4(...) __riscv_vsuxseg2ei16_v_i16mf4(__VA_ARGS__) -#define vsuxseg3ei16_v_i16mf4(...) __riscv_vsuxseg3ei16_v_i16mf4(__VA_ARGS__) -#define vsuxseg4ei16_v_i16mf4(...) __riscv_vsuxseg4ei16_v_i16mf4(__VA_ARGS__) -#define vsuxseg5ei16_v_i16mf4(...) __riscv_vsuxseg5ei16_v_i16mf4(__VA_ARGS__) -#define vsuxseg6ei16_v_i16mf4(...) __riscv_vsuxseg6ei16_v_i16mf4(__VA_ARGS__) -#define vsuxseg7ei16_v_i16mf4(...) __riscv_vsuxseg7ei16_v_i16mf4(__VA_ARGS__) -#define vsuxseg8ei16_v_i16mf4(...) __riscv_vsuxseg8ei16_v_i16mf4(__VA_ARGS__) -#define vsuxseg2ei16_v_i16mf2(...) __riscv_vsuxseg2ei16_v_i16mf2(__VA_ARGS__) -#define vsuxseg3ei16_v_i16mf2(...) __riscv_vsuxseg3ei16_v_i16mf2(__VA_ARGS__) -#define vsuxseg4ei16_v_i16mf2(...) __riscv_vsuxseg4ei16_v_i16mf2(__VA_ARGS__) -#define vsuxseg5ei16_v_i16mf2(...) __riscv_vsuxseg5ei16_v_i16mf2(__VA_ARGS__) -#define vsuxseg6ei16_v_i16mf2(...) __riscv_vsuxseg6ei16_v_i16mf2(__VA_ARGS__) -#define vsuxseg7ei16_v_i16mf2(...) __riscv_vsuxseg7ei16_v_i16mf2(__VA_ARGS__) -#define vsuxseg8ei16_v_i16mf2(...) __riscv_vsuxseg8ei16_v_i16mf2(__VA_ARGS__) -#define vsuxseg2ei16_v_i16m1(...) __riscv_vsuxseg2ei16_v_i16m1(__VA_ARGS__) -#define vsuxseg3ei16_v_i16m1(...) __riscv_vsuxseg3ei16_v_i16m1(__VA_ARGS__) -#define vsuxseg4ei16_v_i16m1(...) __riscv_vsuxseg4ei16_v_i16m1(__VA_ARGS__) -#define vsuxseg5ei16_v_i16m1(...) __riscv_vsuxseg5ei16_v_i16m1(__VA_ARGS__) -#define vsuxseg6ei16_v_i16m1(...) __riscv_vsuxseg6ei16_v_i16m1(__VA_ARGS__) -#define vsuxseg7ei16_v_i16m1(...) __riscv_vsuxseg7ei16_v_i16m1(__VA_ARGS__) -#define vsuxseg8ei16_v_i16m1(...) __riscv_vsuxseg8ei16_v_i16m1(__VA_ARGS__) -#define vsuxseg2ei16_v_i16m2(...) __riscv_vsuxseg2ei16_v_i16m2(__VA_ARGS__) -#define vsuxseg3ei16_v_i16m2(...) __riscv_vsuxseg3ei16_v_i16m2(__VA_ARGS__) -#define vsuxseg4ei16_v_i16m2(...) __riscv_vsuxseg4ei16_v_i16m2(__VA_ARGS__) -#define vsuxseg2ei16_v_i16m4(...) __riscv_vsuxseg2ei16_v_i16m4(__VA_ARGS__) -#define vsuxseg2ei32_v_i16mf4(...) __riscv_vsuxseg2ei32_v_i16mf4(__VA_ARGS__) -#define vsuxseg3ei32_v_i16mf4(...) __riscv_vsuxseg3ei32_v_i16mf4(__VA_ARGS__) -#define vsuxseg4ei32_v_i16mf4(...) __riscv_vsuxseg4ei32_v_i16mf4(__VA_ARGS__) -#define vsuxseg5ei32_v_i16mf4(...) __riscv_vsuxseg5ei32_v_i16mf4(__VA_ARGS__) -#define vsuxseg6ei32_v_i16mf4(...) __riscv_vsuxseg6ei32_v_i16mf4(__VA_ARGS__) -#define vsuxseg7ei32_v_i16mf4(...) __riscv_vsuxseg7ei32_v_i16mf4(__VA_ARGS__) -#define vsuxseg8ei32_v_i16mf4(...) __riscv_vsuxseg8ei32_v_i16mf4(__VA_ARGS__) -#define vsuxseg2ei32_v_i16mf2(...) __riscv_vsuxseg2ei32_v_i16mf2(__VA_ARGS__) -#define vsuxseg3ei32_v_i16mf2(...) __riscv_vsuxseg3ei32_v_i16mf2(__VA_ARGS__) -#define vsuxseg4ei32_v_i16mf2(...) __riscv_vsuxseg4ei32_v_i16mf2(__VA_ARGS__) -#define vsuxseg5ei32_v_i16mf2(...) __riscv_vsuxseg5ei32_v_i16mf2(__VA_ARGS__) -#define vsuxseg6ei32_v_i16mf2(...) __riscv_vsuxseg6ei32_v_i16mf2(__VA_ARGS__) -#define vsuxseg7ei32_v_i16mf2(...) __riscv_vsuxseg7ei32_v_i16mf2(__VA_ARGS__) -#define vsuxseg8ei32_v_i16mf2(...) __riscv_vsuxseg8ei32_v_i16mf2(__VA_ARGS__) -#define vsuxseg2ei32_v_i16m1(...) __riscv_vsuxseg2ei32_v_i16m1(__VA_ARGS__) -#define vsuxseg3ei32_v_i16m1(...) __riscv_vsuxseg3ei32_v_i16m1(__VA_ARGS__) -#define vsuxseg4ei32_v_i16m1(...) __riscv_vsuxseg4ei32_v_i16m1(__VA_ARGS__) -#define vsuxseg5ei32_v_i16m1(...) __riscv_vsuxseg5ei32_v_i16m1(__VA_ARGS__) -#define vsuxseg6ei32_v_i16m1(...) __riscv_vsuxseg6ei32_v_i16m1(__VA_ARGS__) -#define vsuxseg7ei32_v_i16m1(...) __riscv_vsuxseg7ei32_v_i16m1(__VA_ARGS__) -#define vsuxseg8ei32_v_i16m1(...) __riscv_vsuxseg8ei32_v_i16m1(__VA_ARGS__) -#define vsuxseg2ei32_v_i16m2(...) __riscv_vsuxseg2ei32_v_i16m2(__VA_ARGS__) -#define vsuxseg3ei32_v_i16m2(...) __riscv_vsuxseg3ei32_v_i16m2(__VA_ARGS__) -#define vsuxseg4ei32_v_i16m2(...) __riscv_vsuxseg4ei32_v_i16m2(__VA_ARGS__) -#define vsuxseg2ei32_v_i16m4(...) __riscv_vsuxseg2ei32_v_i16m4(__VA_ARGS__) -#define vsuxseg2ei64_v_i16mf4(...) __riscv_vsuxseg2ei64_v_i16mf4(__VA_ARGS__) -#define vsuxseg3ei64_v_i16mf4(...) __riscv_vsuxseg3ei64_v_i16mf4(__VA_ARGS__) -#define vsuxseg4ei64_v_i16mf4(...) __riscv_vsuxseg4ei64_v_i16mf4(__VA_ARGS__) -#define vsuxseg5ei64_v_i16mf4(...) __riscv_vsuxseg5ei64_v_i16mf4(__VA_ARGS__) -#define vsuxseg6ei64_v_i16mf4(...) __riscv_vsuxseg6ei64_v_i16mf4(__VA_ARGS__) -#define vsuxseg7ei64_v_i16mf4(...) __riscv_vsuxseg7ei64_v_i16mf4(__VA_ARGS__) -#define vsuxseg8ei64_v_i16mf4(...) __riscv_vsuxseg8ei64_v_i16mf4(__VA_ARGS__) -#define vsuxseg2ei64_v_i16mf2(...) __riscv_vsuxseg2ei64_v_i16mf2(__VA_ARGS__) -#define vsuxseg3ei64_v_i16mf2(...) __riscv_vsuxseg3ei64_v_i16mf2(__VA_ARGS__) -#define vsuxseg4ei64_v_i16mf2(...) __riscv_vsuxseg4ei64_v_i16mf2(__VA_ARGS__) -#define vsuxseg5ei64_v_i16mf2(...) __riscv_vsuxseg5ei64_v_i16mf2(__VA_ARGS__) -#define vsuxseg6ei64_v_i16mf2(...) __riscv_vsuxseg6ei64_v_i16mf2(__VA_ARGS__) -#define vsuxseg7ei64_v_i16mf2(...) __riscv_vsuxseg7ei64_v_i16mf2(__VA_ARGS__) -#define vsuxseg8ei64_v_i16mf2(...) __riscv_vsuxseg8ei64_v_i16mf2(__VA_ARGS__) -#define vsuxseg2ei64_v_i16m1(...) __riscv_vsuxseg2ei64_v_i16m1(__VA_ARGS__) -#define vsuxseg3ei64_v_i16m1(...) __riscv_vsuxseg3ei64_v_i16m1(__VA_ARGS__) -#define vsuxseg4ei64_v_i16m1(...) __riscv_vsuxseg4ei64_v_i16m1(__VA_ARGS__) -#define vsuxseg5ei64_v_i16m1(...) __riscv_vsuxseg5ei64_v_i16m1(__VA_ARGS__) -#define vsuxseg6ei64_v_i16m1(...) __riscv_vsuxseg6ei64_v_i16m1(__VA_ARGS__) -#define vsuxseg7ei64_v_i16m1(...) __riscv_vsuxseg7ei64_v_i16m1(__VA_ARGS__) -#define vsuxseg8ei64_v_i16m1(...) __riscv_vsuxseg8ei64_v_i16m1(__VA_ARGS__) -#define vsuxseg2ei64_v_i16m2(...) __riscv_vsuxseg2ei64_v_i16m2(__VA_ARGS__) -#define vsuxseg3ei64_v_i16m2(...) __riscv_vsuxseg3ei64_v_i16m2(__VA_ARGS__) -#define vsuxseg4ei64_v_i16m2(...) __riscv_vsuxseg4ei64_v_i16m2(__VA_ARGS__) -#define vsuxseg2ei8_v_i32mf2(...) __riscv_vsuxseg2ei8_v_i32mf2(__VA_ARGS__) -#define vsuxseg3ei8_v_i32mf2(...) __riscv_vsuxseg3ei8_v_i32mf2(__VA_ARGS__) -#define vsuxseg4ei8_v_i32mf2(...) __riscv_vsuxseg4ei8_v_i32mf2(__VA_ARGS__) -#define vsuxseg5ei8_v_i32mf2(...) __riscv_vsuxseg5ei8_v_i32mf2(__VA_ARGS__) -#define vsuxseg6ei8_v_i32mf2(...) __riscv_vsuxseg6ei8_v_i32mf2(__VA_ARGS__) -#define vsuxseg7ei8_v_i32mf2(...) __riscv_vsuxseg7ei8_v_i32mf2(__VA_ARGS__) -#define vsuxseg8ei8_v_i32mf2(...) __riscv_vsuxseg8ei8_v_i32mf2(__VA_ARGS__) -#define vsuxseg2ei8_v_i32m1(...) __riscv_vsuxseg2ei8_v_i32m1(__VA_ARGS__) -#define vsuxseg3ei8_v_i32m1(...) __riscv_vsuxseg3ei8_v_i32m1(__VA_ARGS__) -#define vsuxseg4ei8_v_i32m1(...) __riscv_vsuxseg4ei8_v_i32m1(__VA_ARGS__) -#define vsuxseg5ei8_v_i32m1(...) __riscv_vsuxseg5ei8_v_i32m1(__VA_ARGS__) -#define vsuxseg6ei8_v_i32m1(...) __riscv_vsuxseg6ei8_v_i32m1(__VA_ARGS__) -#define vsuxseg7ei8_v_i32m1(...) __riscv_vsuxseg7ei8_v_i32m1(__VA_ARGS__) -#define vsuxseg8ei8_v_i32m1(...) __riscv_vsuxseg8ei8_v_i32m1(__VA_ARGS__) -#define vsuxseg2ei8_v_i32m2(...) __riscv_vsuxseg2ei8_v_i32m2(__VA_ARGS__) -#define vsuxseg3ei8_v_i32m2(...) __riscv_vsuxseg3ei8_v_i32m2(__VA_ARGS__) -#define vsuxseg4ei8_v_i32m2(...) __riscv_vsuxseg4ei8_v_i32m2(__VA_ARGS__) -#define vsuxseg2ei8_v_i32m4(...) __riscv_vsuxseg2ei8_v_i32m4(__VA_ARGS__) -#define vsuxseg2ei16_v_i32mf2(...) __riscv_vsuxseg2ei16_v_i32mf2(__VA_ARGS__) -#define vsuxseg3ei16_v_i32mf2(...) __riscv_vsuxseg3ei16_v_i32mf2(__VA_ARGS__) -#define vsuxseg4ei16_v_i32mf2(...) __riscv_vsuxseg4ei16_v_i32mf2(__VA_ARGS__) -#define vsuxseg5ei16_v_i32mf2(...) __riscv_vsuxseg5ei16_v_i32mf2(__VA_ARGS__) -#define vsuxseg6ei16_v_i32mf2(...) __riscv_vsuxseg6ei16_v_i32mf2(__VA_ARGS__) -#define vsuxseg7ei16_v_i32mf2(...) __riscv_vsuxseg7ei16_v_i32mf2(__VA_ARGS__) -#define vsuxseg8ei16_v_i32mf2(...) __riscv_vsuxseg8ei16_v_i32mf2(__VA_ARGS__) -#define vsuxseg2ei16_v_i32m1(...) __riscv_vsuxseg2ei16_v_i32m1(__VA_ARGS__) -#define vsuxseg3ei16_v_i32m1(...) __riscv_vsuxseg3ei16_v_i32m1(__VA_ARGS__) -#define vsuxseg4ei16_v_i32m1(...) __riscv_vsuxseg4ei16_v_i32m1(__VA_ARGS__) -#define vsuxseg5ei16_v_i32m1(...) __riscv_vsuxseg5ei16_v_i32m1(__VA_ARGS__) -#define vsuxseg6ei16_v_i32m1(...) __riscv_vsuxseg6ei16_v_i32m1(__VA_ARGS__) -#define vsuxseg7ei16_v_i32m1(...) __riscv_vsuxseg7ei16_v_i32m1(__VA_ARGS__) -#define vsuxseg8ei16_v_i32m1(...) __riscv_vsuxseg8ei16_v_i32m1(__VA_ARGS__) -#define vsuxseg2ei16_v_i32m2(...) __riscv_vsuxseg2ei16_v_i32m2(__VA_ARGS__) -#define vsuxseg3ei16_v_i32m2(...) __riscv_vsuxseg3ei16_v_i32m2(__VA_ARGS__) -#define vsuxseg4ei16_v_i32m2(...) __riscv_vsuxseg4ei16_v_i32m2(__VA_ARGS__) -#define vsuxseg2ei16_v_i32m4(...) __riscv_vsuxseg2ei16_v_i32m4(__VA_ARGS__) -#define vsuxseg2ei32_v_i32mf2(...) __riscv_vsuxseg2ei32_v_i32mf2(__VA_ARGS__) -#define vsuxseg3ei32_v_i32mf2(...) __riscv_vsuxseg3ei32_v_i32mf2(__VA_ARGS__) -#define vsuxseg4ei32_v_i32mf2(...) __riscv_vsuxseg4ei32_v_i32mf2(__VA_ARGS__) -#define vsuxseg5ei32_v_i32mf2(...) __riscv_vsuxseg5ei32_v_i32mf2(__VA_ARGS__) -#define vsuxseg6ei32_v_i32mf2(...) __riscv_vsuxseg6ei32_v_i32mf2(__VA_ARGS__) -#define vsuxseg7ei32_v_i32mf2(...) __riscv_vsuxseg7ei32_v_i32mf2(__VA_ARGS__) -#define vsuxseg8ei32_v_i32mf2(...) __riscv_vsuxseg8ei32_v_i32mf2(__VA_ARGS__) -#define vsuxseg2ei32_v_i32m1(...) __riscv_vsuxseg2ei32_v_i32m1(__VA_ARGS__) -#define vsuxseg3ei32_v_i32m1(...) __riscv_vsuxseg3ei32_v_i32m1(__VA_ARGS__) -#define vsuxseg4ei32_v_i32m1(...) __riscv_vsuxseg4ei32_v_i32m1(__VA_ARGS__) -#define vsuxseg5ei32_v_i32m1(...) __riscv_vsuxseg5ei32_v_i32m1(__VA_ARGS__) -#define vsuxseg6ei32_v_i32m1(...) __riscv_vsuxseg6ei32_v_i32m1(__VA_ARGS__) -#define vsuxseg7ei32_v_i32m1(...) __riscv_vsuxseg7ei32_v_i32m1(__VA_ARGS__) -#define vsuxseg8ei32_v_i32m1(...) __riscv_vsuxseg8ei32_v_i32m1(__VA_ARGS__) -#define vsuxseg2ei32_v_i32m2(...) __riscv_vsuxseg2ei32_v_i32m2(__VA_ARGS__) -#define vsuxseg3ei32_v_i32m2(...) __riscv_vsuxseg3ei32_v_i32m2(__VA_ARGS__) -#define vsuxseg4ei32_v_i32m2(...) __riscv_vsuxseg4ei32_v_i32m2(__VA_ARGS__) -#define vsuxseg2ei32_v_i32m4(...) __riscv_vsuxseg2ei32_v_i32m4(__VA_ARGS__) -#define vsuxseg2ei64_v_i32mf2(...) __riscv_vsuxseg2ei64_v_i32mf2(__VA_ARGS__) -#define vsuxseg3ei64_v_i32mf2(...) __riscv_vsuxseg3ei64_v_i32mf2(__VA_ARGS__) -#define vsuxseg4ei64_v_i32mf2(...) __riscv_vsuxseg4ei64_v_i32mf2(__VA_ARGS__) -#define vsuxseg5ei64_v_i32mf2(...) __riscv_vsuxseg5ei64_v_i32mf2(__VA_ARGS__) -#define vsuxseg6ei64_v_i32mf2(...) __riscv_vsuxseg6ei64_v_i32mf2(__VA_ARGS__) -#define vsuxseg7ei64_v_i32mf2(...) __riscv_vsuxseg7ei64_v_i32mf2(__VA_ARGS__) -#define vsuxseg8ei64_v_i32mf2(...) __riscv_vsuxseg8ei64_v_i32mf2(__VA_ARGS__) -#define vsuxseg2ei64_v_i32m1(...) __riscv_vsuxseg2ei64_v_i32m1(__VA_ARGS__) -#define vsuxseg3ei64_v_i32m1(...) __riscv_vsuxseg3ei64_v_i32m1(__VA_ARGS__) -#define vsuxseg4ei64_v_i32m1(...) __riscv_vsuxseg4ei64_v_i32m1(__VA_ARGS__) -#define vsuxseg5ei64_v_i32m1(...) __riscv_vsuxseg5ei64_v_i32m1(__VA_ARGS__) -#define vsuxseg6ei64_v_i32m1(...) __riscv_vsuxseg6ei64_v_i32m1(__VA_ARGS__) -#define vsuxseg7ei64_v_i32m1(...) __riscv_vsuxseg7ei64_v_i32m1(__VA_ARGS__) -#define vsuxseg8ei64_v_i32m1(...) __riscv_vsuxseg8ei64_v_i32m1(__VA_ARGS__) -#define vsuxseg2ei64_v_i32m2(...) __riscv_vsuxseg2ei64_v_i32m2(__VA_ARGS__) -#define vsuxseg3ei64_v_i32m2(...) __riscv_vsuxseg3ei64_v_i32m2(__VA_ARGS__) -#define vsuxseg4ei64_v_i32m2(...) __riscv_vsuxseg4ei64_v_i32m2(__VA_ARGS__) -#define vsuxseg2ei64_v_i32m4(...) __riscv_vsuxseg2ei64_v_i32m4(__VA_ARGS__) -#define vsuxseg2ei8_v_i64m1(...) __riscv_vsuxseg2ei8_v_i64m1(__VA_ARGS__) -#define vsuxseg3ei8_v_i64m1(...) __riscv_vsuxseg3ei8_v_i64m1(__VA_ARGS__) -#define vsuxseg4ei8_v_i64m1(...) __riscv_vsuxseg4ei8_v_i64m1(__VA_ARGS__) -#define vsuxseg5ei8_v_i64m1(...) __riscv_vsuxseg5ei8_v_i64m1(__VA_ARGS__) -#define vsuxseg6ei8_v_i64m1(...) __riscv_vsuxseg6ei8_v_i64m1(__VA_ARGS__) -#define vsuxseg7ei8_v_i64m1(...) __riscv_vsuxseg7ei8_v_i64m1(__VA_ARGS__) -#define vsuxseg8ei8_v_i64m1(...) __riscv_vsuxseg8ei8_v_i64m1(__VA_ARGS__) -#define vsuxseg2ei8_v_i64m2(...) __riscv_vsuxseg2ei8_v_i64m2(__VA_ARGS__) -#define vsuxseg3ei8_v_i64m2(...) __riscv_vsuxseg3ei8_v_i64m2(__VA_ARGS__) -#define vsuxseg4ei8_v_i64m2(...) __riscv_vsuxseg4ei8_v_i64m2(__VA_ARGS__) -#define vsuxseg2ei8_v_i64m4(...) __riscv_vsuxseg2ei8_v_i64m4(__VA_ARGS__) -#define vsuxseg2ei16_v_i64m1(...) __riscv_vsuxseg2ei16_v_i64m1(__VA_ARGS__) -#define vsuxseg3ei16_v_i64m1(...) __riscv_vsuxseg3ei16_v_i64m1(__VA_ARGS__) -#define vsuxseg4ei16_v_i64m1(...) __riscv_vsuxseg4ei16_v_i64m1(__VA_ARGS__) -#define vsuxseg5ei16_v_i64m1(...) __riscv_vsuxseg5ei16_v_i64m1(__VA_ARGS__) -#define vsuxseg6ei16_v_i64m1(...) __riscv_vsuxseg6ei16_v_i64m1(__VA_ARGS__) -#define vsuxseg7ei16_v_i64m1(...) __riscv_vsuxseg7ei16_v_i64m1(__VA_ARGS__) -#define vsuxseg8ei16_v_i64m1(...) __riscv_vsuxseg8ei16_v_i64m1(__VA_ARGS__) -#define vsuxseg2ei16_v_i64m2(...) __riscv_vsuxseg2ei16_v_i64m2(__VA_ARGS__) -#define vsuxseg3ei16_v_i64m2(...) __riscv_vsuxseg3ei16_v_i64m2(__VA_ARGS__) -#define vsuxseg4ei16_v_i64m2(...) __riscv_vsuxseg4ei16_v_i64m2(__VA_ARGS__) -#define vsuxseg2ei16_v_i64m4(...) __riscv_vsuxseg2ei16_v_i64m4(__VA_ARGS__) -#define vsuxseg2ei32_v_i64m1(...) __riscv_vsuxseg2ei32_v_i64m1(__VA_ARGS__) -#define vsuxseg3ei32_v_i64m1(...) __riscv_vsuxseg3ei32_v_i64m1(__VA_ARGS__) -#define vsuxseg4ei32_v_i64m1(...) __riscv_vsuxseg4ei32_v_i64m1(__VA_ARGS__) -#define vsuxseg5ei32_v_i64m1(...) __riscv_vsuxseg5ei32_v_i64m1(__VA_ARGS__) -#define vsuxseg6ei32_v_i64m1(...) __riscv_vsuxseg6ei32_v_i64m1(__VA_ARGS__) -#define vsuxseg7ei32_v_i64m1(...) __riscv_vsuxseg7ei32_v_i64m1(__VA_ARGS__) -#define vsuxseg8ei32_v_i64m1(...) __riscv_vsuxseg8ei32_v_i64m1(__VA_ARGS__) -#define vsuxseg2ei32_v_i64m2(...) __riscv_vsuxseg2ei32_v_i64m2(__VA_ARGS__) -#define vsuxseg3ei32_v_i64m2(...) __riscv_vsuxseg3ei32_v_i64m2(__VA_ARGS__) -#define vsuxseg4ei32_v_i64m2(...) __riscv_vsuxseg4ei32_v_i64m2(__VA_ARGS__) -#define vsuxseg2ei32_v_i64m4(...) __riscv_vsuxseg2ei32_v_i64m4(__VA_ARGS__) -#define vsuxseg2ei64_v_i64m1(...) __riscv_vsuxseg2ei64_v_i64m1(__VA_ARGS__) -#define vsuxseg3ei64_v_i64m1(...) __riscv_vsuxseg3ei64_v_i64m1(__VA_ARGS__) -#define vsuxseg4ei64_v_i64m1(...) __riscv_vsuxseg4ei64_v_i64m1(__VA_ARGS__) -#define vsuxseg5ei64_v_i64m1(...) __riscv_vsuxseg5ei64_v_i64m1(__VA_ARGS__) -#define vsuxseg6ei64_v_i64m1(...) __riscv_vsuxseg6ei64_v_i64m1(__VA_ARGS__) -#define vsuxseg7ei64_v_i64m1(...) __riscv_vsuxseg7ei64_v_i64m1(__VA_ARGS__) -#define vsuxseg8ei64_v_i64m1(...) __riscv_vsuxseg8ei64_v_i64m1(__VA_ARGS__) -#define vsuxseg2ei64_v_i64m2(...) __riscv_vsuxseg2ei64_v_i64m2(__VA_ARGS__) -#define vsuxseg3ei64_v_i64m2(...) __riscv_vsuxseg3ei64_v_i64m2(__VA_ARGS__) -#define vsuxseg4ei64_v_i64m2(...) __riscv_vsuxseg4ei64_v_i64m2(__VA_ARGS__) -#define vsuxseg2ei64_v_i64m4(...) __riscv_vsuxseg2ei64_v_i64m4(__VA_ARGS__) -#define vsoxseg2ei8_v_u8mf8(...) __riscv_vsoxseg2ei8_v_u8mf8(__VA_ARGS__) -#define vsoxseg3ei8_v_u8mf8(...) __riscv_vsoxseg3ei8_v_u8mf8(__VA_ARGS__) -#define vsoxseg4ei8_v_u8mf8(...) __riscv_vsoxseg4ei8_v_u8mf8(__VA_ARGS__) -#define vsoxseg5ei8_v_u8mf8(...) __riscv_vsoxseg5ei8_v_u8mf8(__VA_ARGS__) -#define vsoxseg6ei8_v_u8mf8(...) __riscv_vsoxseg6ei8_v_u8mf8(__VA_ARGS__) -#define vsoxseg7ei8_v_u8mf8(...) __riscv_vsoxseg7ei8_v_u8mf8(__VA_ARGS__) -#define vsoxseg8ei8_v_u8mf8(...) __riscv_vsoxseg8ei8_v_u8mf8(__VA_ARGS__) -#define vsoxseg2ei8_v_u8mf4(...) __riscv_vsoxseg2ei8_v_u8mf4(__VA_ARGS__) -#define vsoxseg3ei8_v_u8mf4(...) __riscv_vsoxseg3ei8_v_u8mf4(__VA_ARGS__) -#define vsoxseg4ei8_v_u8mf4(...) __riscv_vsoxseg4ei8_v_u8mf4(__VA_ARGS__) -#define vsoxseg5ei8_v_u8mf4(...) __riscv_vsoxseg5ei8_v_u8mf4(__VA_ARGS__) -#define vsoxseg6ei8_v_u8mf4(...) __riscv_vsoxseg6ei8_v_u8mf4(__VA_ARGS__) -#define vsoxseg7ei8_v_u8mf4(...) __riscv_vsoxseg7ei8_v_u8mf4(__VA_ARGS__) -#define vsoxseg8ei8_v_u8mf4(...) __riscv_vsoxseg8ei8_v_u8mf4(__VA_ARGS__) -#define vsoxseg2ei8_v_u8mf2(...) __riscv_vsoxseg2ei8_v_u8mf2(__VA_ARGS__) -#define vsoxseg3ei8_v_u8mf2(...) __riscv_vsoxseg3ei8_v_u8mf2(__VA_ARGS__) -#define vsoxseg4ei8_v_u8mf2(...) __riscv_vsoxseg4ei8_v_u8mf2(__VA_ARGS__) -#define vsoxseg5ei8_v_u8mf2(...) __riscv_vsoxseg5ei8_v_u8mf2(__VA_ARGS__) -#define vsoxseg6ei8_v_u8mf2(...) __riscv_vsoxseg6ei8_v_u8mf2(__VA_ARGS__) -#define vsoxseg7ei8_v_u8mf2(...) __riscv_vsoxseg7ei8_v_u8mf2(__VA_ARGS__) -#define vsoxseg8ei8_v_u8mf2(...) __riscv_vsoxseg8ei8_v_u8mf2(__VA_ARGS__) -#define vsoxseg2ei8_v_u8m1(...) __riscv_vsoxseg2ei8_v_u8m1(__VA_ARGS__) -#define vsoxseg3ei8_v_u8m1(...) __riscv_vsoxseg3ei8_v_u8m1(__VA_ARGS__) -#define vsoxseg4ei8_v_u8m1(...) __riscv_vsoxseg4ei8_v_u8m1(__VA_ARGS__) -#define vsoxseg5ei8_v_u8m1(...) __riscv_vsoxseg5ei8_v_u8m1(__VA_ARGS__) -#define vsoxseg6ei8_v_u8m1(...) __riscv_vsoxseg6ei8_v_u8m1(__VA_ARGS__) -#define vsoxseg7ei8_v_u8m1(...) __riscv_vsoxseg7ei8_v_u8m1(__VA_ARGS__) -#define vsoxseg8ei8_v_u8m1(...) __riscv_vsoxseg8ei8_v_u8m1(__VA_ARGS__) -#define vsoxseg2ei8_v_u8m2(...) __riscv_vsoxseg2ei8_v_u8m2(__VA_ARGS__) -#define vsoxseg3ei8_v_u8m2(...) __riscv_vsoxseg3ei8_v_u8m2(__VA_ARGS__) -#define vsoxseg4ei8_v_u8m2(...) __riscv_vsoxseg4ei8_v_u8m2(__VA_ARGS__) -#define vsoxseg2ei8_v_u8m4(...) __riscv_vsoxseg2ei8_v_u8m4(__VA_ARGS__) -#define vsoxseg2ei16_v_u8mf8(...) __riscv_vsoxseg2ei16_v_u8mf8(__VA_ARGS__) -#define vsoxseg3ei16_v_u8mf8(...) __riscv_vsoxseg3ei16_v_u8mf8(__VA_ARGS__) -#define vsoxseg4ei16_v_u8mf8(...) __riscv_vsoxseg4ei16_v_u8mf8(__VA_ARGS__) -#define vsoxseg5ei16_v_u8mf8(...) __riscv_vsoxseg5ei16_v_u8mf8(__VA_ARGS__) -#define vsoxseg6ei16_v_u8mf8(...) __riscv_vsoxseg6ei16_v_u8mf8(__VA_ARGS__) -#define vsoxseg7ei16_v_u8mf8(...) __riscv_vsoxseg7ei16_v_u8mf8(__VA_ARGS__) -#define vsoxseg8ei16_v_u8mf8(...) __riscv_vsoxseg8ei16_v_u8mf8(__VA_ARGS__) -#define vsoxseg2ei16_v_u8mf4(...) __riscv_vsoxseg2ei16_v_u8mf4(__VA_ARGS__) -#define vsoxseg3ei16_v_u8mf4(...) __riscv_vsoxseg3ei16_v_u8mf4(__VA_ARGS__) -#define vsoxseg4ei16_v_u8mf4(...) __riscv_vsoxseg4ei16_v_u8mf4(__VA_ARGS__) -#define vsoxseg5ei16_v_u8mf4(...) __riscv_vsoxseg5ei16_v_u8mf4(__VA_ARGS__) -#define vsoxseg6ei16_v_u8mf4(...) __riscv_vsoxseg6ei16_v_u8mf4(__VA_ARGS__) -#define vsoxseg7ei16_v_u8mf4(...) __riscv_vsoxseg7ei16_v_u8mf4(__VA_ARGS__) -#define vsoxseg8ei16_v_u8mf4(...) __riscv_vsoxseg8ei16_v_u8mf4(__VA_ARGS__) -#define vsoxseg2ei16_v_u8mf2(...) __riscv_vsoxseg2ei16_v_u8mf2(__VA_ARGS__) -#define vsoxseg3ei16_v_u8mf2(...) __riscv_vsoxseg3ei16_v_u8mf2(__VA_ARGS__) -#define vsoxseg4ei16_v_u8mf2(...) __riscv_vsoxseg4ei16_v_u8mf2(__VA_ARGS__) -#define vsoxseg5ei16_v_u8mf2(...) __riscv_vsoxseg5ei16_v_u8mf2(__VA_ARGS__) -#define vsoxseg6ei16_v_u8mf2(...) __riscv_vsoxseg6ei16_v_u8mf2(__VA_ARGS__) -#define vsoxseg7ei16_v_u8mf2(...) __riscv_vsoxseg7ei16_v_u8mf2(__VA_ARGS__) -#define vsoxseg8ei16_v_u8mf2(...) __riscv_vsoxseg8ei16_v_u8mf2(__VA_ARGS__) -#define vsoxseg2ei16_v_u8m1(...) __riscv_vsoxseg2ei16_v_u8m1(__VA_ARGS__) -#define vsoxseg3ei16_v_u8m1(...) __riscv_vsoxseg3ei16_v_u8m1(__VA_ARGS__) -#define vsoxseg4ei16_v_u8m1(...) __riscv_vsoxseg4ei16_v_u8m1(__VA_ARGS__) -#define vsoxseg5ei16_v_u8m1(...) __riscv_vsoxseg5ei16_v_u8m1(__VA_ARGS__) -#define vsoxseg6ei16_v_u8m1(...) __riscv_vsoxseg6ei16_v_u8m1(__VA_ARGS__) -#define vsoxseg7ei16_v_u8m1(...) __riscv_vsoxseg7ei16_v_u8m1(__VA_ARGS__) -#define vsoxseg8ei16_v_u8m1(...) __riscv_vsoxseg8ei16_v_u8m1(__VA_ARGS__) -#define vsoxseg2ei16_v_u8m2(...) __riscv_vsoxseg2ei16_v_u8m2(__VA_ARGS__) -#define vsoxseg3ei16_v_u8m2(...) __riscv_vsoxseg3ei16_v_u8m2(__VA_ARGS__) -#define vsoxseg4ei16_v_u8m2(...) __riscv_vsoxseg4ei16_v_u8m2(__VA_ARGS__) -#define vsoxseg2ei16_v_u8m4(...) __riscv_vsoxseg2ei16_v_u8m4(__VA_ARGS__) -#define vsoxseg2ei32_v_u8mf8(...) __riscv_vsoxseg2ei32_v_u8mf8(__VA_ARGS__) -#define vsoxseg3ei32_v_u8mf8(...) __riscv_vsoxseg3ei32_v_u8mf8(__VA_ARGS__) -#define vsoxseg4ei32_v_u8mf8(...) __riscv_vsoxseg4ei32_v_u8mf8(__VA_ARGS__) -#define vsoxseg5ei32_v_u8mf8(...) __riscv_vsoxseg5ei32_v_u8mf8(__VA_ARGS__) -#define vsoxseg6ei32_v_u8mf8(...) __riscv_vsoxseg6ei32_v_u8mf8(__VA_ARGS__) -#define vsoxseg7ei32_v_u8mf8(...) __riscv_vsoxseg7ei32_v_u8mf8(__VA_ARGS__) -#define vsoxseg8ei32_v_u8mf8(...) __riscv_vsoxseg8ei32_v_u8mf8(__VA_ARGS__) -#define vsoxseg2ei32_v_u8mf4(...) __riscv_vsoxseg2ei32_v_u8mf4(__VA_ARGS__) -#define vsoxseg3ei32_v_u8mf4(...) __riscv_vsoxseg3ei32_v_u8mf4(__VA_ARGS__) -#define vsoxseg4ei32_v_u8mf4(...) __riscv_vsoxseg4ei32_v_u8mf4(__VA_ARGS__) -#define vsoxseg5ei32_v_u8mf4(...) __riscv_vsoxseg5ei32_v_u8mf4(__VA_ARGS__) -#define vsoxseg6ei32_v_u8mf4(...) __riscv_vsoxseg6ei32_v_u8mf4(__VA_ARGS__) -#define vsoxseg7ei32_v_u8mf4(...) __riscv_vsoxseg7ei32_v_u8mf4(__VA_ARGS__) -#define vsoxseg8ei32_v_u8mf4(...) __riscv_vsoxseg8ei32_v_u8mf4(__VA_ARGS__) -#define vsoxseg2ei32_v_u8mf2(...) __riscv_vsoxseg2ei32_v_u8mf2(__VA_ARGS__) -#define vsoxseg3ei32_v_u8mf2(...) __riscv_vsoxseg3ei32_v_u8mf2(__VA_ARGS__) -#define vsoxseg4ei32_v_u8mf2(...) __riscv_vsoxseg4ei32_v_u8mf2(__VA_ARGS__) -#define vsoxseg5ei32_v_u8mf2(...) __riscv_vsoxseg5ei32_v_u8mf2(__VA_ARGS__) -#define vsoxseg6ei32_v_u8mf2(...) __riscv_vsoxseg6ei32_v_u8mf2(__VA_ARGS__) -#define vsoxseg7ei32_v_u8mf2(...) __riscv_vsoxseg7ei32_v_u8mf2(__VA_ARGS__) -#define vsoxseg8ei32_v_u8mf2(...) __riscv_vsoxseg8ei32_v_u8mf2(__VA_ARGS__) -#define vsoxseg2ei32_v_u8m1(...) __riscv_vsoxseg2ei32_v_u8m1(__VA_ARGS__) -#define vsoxseg3ei32_v_u8m1(...) __riscv_vsoxseg3ei32_v_u8m1(__VA_ARGS__) -#define vsoxseg4ei32_v_u8m1(...) __riscv_vsoxseg4ei32_v_u8m1(__VA_ARGS__) -#define vsoxseg5ei32_v_u8m1(...) __riscv_vsoxseg5ei32_v_u8m1(__VA_ARGS__) -#define vsoxseg6ei32_v_u8m1(...) __riscv_vsoxseg6ei32_v_u8m1(__VA_ARGS__) -#define vsoxseg7ei32_v_u8m1(...) __riscv_vsoxseg7ei32_v_u8m1(__VA_ARGS__) -#define vsoxseg8ei32_v_u8m1(...) __riscv_vsoxseg8ei32_v_u8m1(__VA_ARGS__) -#define vsoxseg2ei32_v_u8m2(...) __riscv_vsoxseg2ei32_v_u8m2(__VA_ARGS__) -#define vsoxseg3ei32_v_u8m2(...) __riscv_vsoxseg3ei32_v_u8m2(__VA_ARGS__) -#define vsoxseg4ei32_v_u8m2(...) __riscv_vsoxseg4ei32_v_u8m2(__VA_ARGS__) -#define vsoxseg2ei64_v_u8mf8(...) __riscv_vsoxseg2ei64_v_u8mf8(__VA_ARGS__) -#define vsoxseg3ei64_v_u8mf8(...) __riscv_vsoxseg3ei64_v_u8mf8(__VA_ARGS__) -#define vsoxseg4ei64_v_u8mf8(...) __riscv_vsoxseg4ei64_v_u8mf8(__VA_ARGS__) -#define vsoxseg5ei64_v_u8mf8(...) __riscv_vsoxseg5ei64_v_u8mf8(__VA_ARGS__) -#define vsoxseg6ei64_v_u8mf8(...) __riscv_vsoxseg6ei64_v_u8mf8(__VA_ARGS__) -#define vsoxseg7ei64_v_u8mf8(...) __riscv_vsoxseg7ei64_v_u8mf8(__VA_ARGS__) -#define vsoxseg8ei64_v_u8mf8(...) __riscv_vsoxseg8ei64_v_u8mf8(__VA_ARGS__) -#define vsoxseg2ei64_v_u8mf4(...) __riscv_vsoxseg2ei64_v_u8mf4(__VA_ARGS__) -#define vsoxseg3ei64_v_u8mf4(...) __riscv_vsoxseg3ei64_v_u8mf4(__VA_ARGS__) -#define vsoxseg4ei64_v_u8mf4(...) __riscv_vsoxseg4ei64_v_u8mf4(__VA_ARGS__) -#define vsoxseg5ei64_v_u8mf4(...) __riscv_vsoxseg5ei64_v_u8mf4(__VA_ARGS__) -#define vsoxseg6ei64_v_u8mf4(...) __riscv_vsoxseg6ei64_v_u8mf4(__VA_ARGS__) -#define vsoxseg7ei64_v_u8mf4(...) __riscv_vsoxseg7ei64_v_u8mf4(__VA_ARGS__) -#define vsoxseg8ei64_v_u8mf4(...) __riscv_vsoxseg8ei64_v_u8mf4(__VA_ARGS__) -#define vsoxseg2ei64_v_u8mf2(...) __riscv_vsoxseg2ei64_v_u8mf2(__VA_ARGS__) -#define vsoxseg3ei64_v_u8mf2(...) __riscv_vsoxseg3ei64_v_u8mf2(__VA_ARGS__) -#define vsoxseg4ei64_v_u8mf2(...) __riscv_vsoxseg4ei64_v_u8mf2(__VA_ARGS__) -#define vsoxseg5ei64_v_u8mf2(...) __riscv_vsoxseg5ei64_v_u8mf2(__VA_ARGS__) -#define vsoxseg6ei64_v_u8mf2(...) __riscv_vsoxseg6ei64_v_u8mf2(__VA_ARGS__) -#define vsoxseg7ei64_v_u8mf2(...) __riscv_vsoxseg7ei64_v_u8mf2(__VA_ARGS__) -#define vsoxseg8ei64_v_u8mf2(...) __riscv_vsoxseg8ei64_v_u8mf2(__VA_ARGS__) -#define vsoxseg2ei64_v_u8m1(...) __riscv_vsoxseg2ei64_v_u8m1(__VA_ARGS__) -#define vsoxseg3ei64_v_u8m1(...) __riscv_vsoxseg3ei64_v_u8m1(__VA_ARGS__) -#define vsoxseg4ei64_v_u8m1(...) __riscv_vsoxseg4ei64_v_u8m1(__VA_ARGS__) -#define vsoxseg5ei64_v_u8m1(...) __riscv_vsoxseg5ei64_v_u8m1(__VA_ARGS__) -#define vsoxseg6ei64_v_u8m1(...) __riscv_vsoxseg6ei64_v_u8m1(__VA_ARGS__) -#define vsoxseg7ei64_v_u8m1(...) __riscv_vsoxseg7ei64_v_u8m1(__VA_ARGS__) -#define vsoxseg8ei64_v_u8m1(...) __riscv_vsoxseg8ei64_v_u8m1(__VA_ARGS__) -#define vsoxseg2ei8_v_u16mf4(...) __riscv_vsoxseg2ei8_v_u16mf4(__VA_ARGS__) -#define vsoxseg3ei8_v_u16mf4(...) __riscv_vsoxseg3ei8_v_u16mf4(__VA_ARGS__) -#define vsoxseg4ei8_v_u16mf4(...) __riscv_vsoxseg4ei8_v_u16mf4(__VA_ARGS__) -#define vsoxseg5ei8_v_u16mf4(...) __riscv_vsoxseg5ei8_v_u16mf4(__VA_ARGS__) -#define vsoxseg6ei8_v_u16mf4(...) __riscv_vsoxseg6ei8_v_u16mf4(__VA_ARGS__) -#define vsoxseg7ei8_v_u16mf4(...) __riscv_vsoxseg7ei8_v_u16mf4(__VA_ARGS__) -#define vsoxseg8ei8_v_u16mf4(...) __riscv_vsoxseg8ei8_v_u16mf4(__VA_ARGS__) -#define vsoxseg2ei8_v_u16mf2(...) __riscv_vsoxseg2ei8_v_u16mf2(__VA_ARGS__) -#define vsoxseg3ei8_v_u16mf2(...) __riscv_vsoxseg3ei8_v_u16mf2(__VA_ARGS__) -#define vsoxseg4ei8_v_u16mf2(...) __riscv_vsoxseg4ei8_v_u16mf2(__VA_ARGS__) -#define vsoxseg5ei8_v_u16mf2(...) __riscv_vsoxseg5ei8_v_u16mf2(__VA_ARGS__) -#define vsoxseg6ei8_v_u16mf2(...) __riscv_vsoxseg6ei8_v_u16mf2(__VA_ARGS__) -#define vsoxseg7ei8_v_u16mf2(...) __riscv_vsoxseg7ei8_v_u16mf2(__VA_ARGS__) -#define vsoxseg8ei8_v_u16mf2(...) __riscv_vsoxseg8ei8_v_u16mf2(__VA_ARGS__) -#define vsoxseg2ei8_v_u16m1(...) __riscv_vsoxseg2ei8_v_u16m1(__VA_ARGS__) -#define vsoxseg3ei8_v_u16m1(...) __riscv_vsoxseg3ei8_v_u16m1(__VA_ARGS__) -#define vsoxseg4ei8_v_u16m1(...) __riscv_vsoxseg4ei8_v_u16m1(__VA_ARGS__) -#define vsoxseg5ei8_v_u16m1(...) __riscv_vsoxseg5ei8_v_u16m1(__VA_ARGS__) -#define vsoxseg6ei8_v_u16m1(...) __riscv_vsoxseg6ei8_v_u16m1(__VA_ARGS__) -#define vsoxseg7ei8_v_u16m1(...) __riscv_vsoxseg7ei8_v_u16m1(__VA_ARGS__) -#define vsoxseg8ei8_v_u16m1(...) __riscv_vsoxseg8ei8_v_u16m1(__VA_ARGS__) -#define vsoxseg2ei8_v_u16m2(...) __riscv_vsoxseg2ei8_v_u16m2(__VA_ARGS__) -#define vsoxseg3ei8_v_u16m2(...) __riscv_vsoxseg3ei8_v_u16m2(__VA_ARGS__) -#define vsoxseg4ei8_v_u16m2(...) __riscv_vsoxseg4ei8_v_u16m2(__VA_ARGS__) -#define vsoxseg2ei8_v_u16m4(...) __riscv_vsoxseg2ei8_v_u16m4(__VA_ARGS__) -#define vsoxseg2ei16_v_u16mf4(...) __riscv_vsoxseg2ei16_v_u16mf4(__VA_ARGS__) -#define vsoxseg3ei16_v_u16mf4(...) __riscv_vsoxseg3ei16_v_u16mf4(__VA_ARGS__) -#define vsoxseg4ei16_v_u16mf4(...) __riscv_vsoxseg4ei16_v_u16mf4(__VA_ARGS__) -#define vsoxseg5ei16_v_u16mf4(...) __riscv_vsoxseg5ei16_v_u16mf4(__VA_ARGS__) -#define vsoxseg6ei16_v_u16mf4(...) __riscv_vsoxseg6ei16_v_u16mf4(__VA_ARGS__) -#define vsoxseg7ei16_v_u16mf4(...) __riscv_vsoxseg7ei16_v_u16mf4(__VA_ARGS__) -#define vsoxseg8ei16_v_u16mf4(...) __riscv_vsoxseg8ei16_v_u16mf4(__VA_ARGS__) -#define vsoxseg2ei16_v_u16mf2(...) __riscv_vsoxseg2ei16_v_u16mf2(__VA_ARGS__) -#define vsoxseg3ei16_v_u16mf2(...) __riscv_vsoxseg3ei16_v_u16mf2(__VA_ARGS__) -#define vsoxseg4ei16_v_u16mf2(...) __riscv_vsoxseg4ei16_v_u16mf2(__VA_ARGS__) -#define vsoxseg5ei16_v_u16mf2(...) __riscv_vsoxseg5ei16_v_u16mf2(__VA_ARGS__) -#define vsoxseg6ei16_v_u16mf2(...) __riscv_vsoxseg6ei16_v_u16mf2(__VA_ARGS__) -#define vsoxseg7ei16_v_u16mf2(...) __riscv_vsoxseg7ei16_v_u16mf2(__VA_ARGS__) -#define vsoxseg8ei16_v_u16mf2(...) __riscv_vsoxseg8ei16_v_u16mf2(__VA_ARGS__) -#define vsoxseg2ei16_v_u16m1(...) __riscv_vsoxseg2ei16_v_u16m1(__VA_ARGS__) -#define vsoxseg3ei16_v_u16m1(...) __riscv_vsoxseg3ei16_v_u16m1(__VA_ARGS__) -#define vsoxseg4ei16_v_u16m1(...) __riscv_vsoxseg4ei16_v_u16m1(__VA_ARGS__) -#define vsoxseg5ei16_v_u16m1(...) __riscv_vsoxseg5ei16_v_u16m1(__VA_ARGS__) -#define vsoxseg6ei16_v_u16m1(...) __riscv_vsoxseg6ei16_v_u16m1(__VA_ARGS__) -#define vsoxseg7ei16_v_u16m1(...) __riscv_vsoxseg7ei16_v_u16m1(__VA_ARGS__) -#define vsoxseg8ei16_v_u16m1(...) __riscv_vsoxseg8ei16_v_u16m1(__VA_ARGS__) -#define vsoxseg2ei16_v_u16m2(...) __riscv_vsoxseg2ei16_v_u16m2(__VA_ARGS__) -#define vsoxseg3ei16_v_u16m2(...) __riscv_vsoxseg3ei16_v_u16m2(__VA_ARGS__) -#define vsoxseg4ei16_v_u16m2(...) __riscv_vsoxseg4ei16_v_u16m2(__VA_ARGS__) -#define vsoxseg2ei16_v_u16m4(...) __riscv_vsoxseg2ei16_v_u16m4(__VA_ARGS__) -#define vsoxseg2ei32_v_u16mf4(...) __riscv_vsoxseg2ei32_v_u16mf4(__VA_ARGS__) -#define vsoxseg3ei32_v_u16mf4(...) __riscv_vsoxseg3ei32_v_u16mf4(__VA_ARGS__) -#define vsoxseg4ei32_v_u16mf4(...) __riscv_vsoxseg4ei32_v_u16mf4(__VA_ARGS__) -#define vsoxseg5ei32_v_u16mf4(...) __riscv_vsoxseg5ei32_v_u16mf4(__VA_ARGS__) -#define vsoxseg6ei32_v_u16mf4(...) __riscv_vsoxseg6ei32_v_u16mf4(__VA_ARGS__) -#define vsoxseg7ei32_v_u16mf4(...) __riscv_vsoxseg7ei32_v_u16mf4(__VA_ARGS__) -#define vsoxseg8ei32_v_u16mf4(...) __riscv_vsoxseg8ei32_v_u16mf4(__VA_ARGS__) -#define vsoxseg2ei32_v_u16mf2(...) __riscv_vsoxseg2ei32_v_u16mf2(__VA_ARGS__) -#define vsoxseg3ei32_v_u16mf2(...) __riscv_vsoxseg3ei32_v_u16mf2(__VA_ARGS__) -#define vsoxseg4ei32_v_u16mf2(...) __riscv_vsoxseg4ei32_v_u16mf2(__VA_ARGS__) -#define vsoxseg5ei32_v_u16mf2(...) __riscv_vsoxseg5ei32_v_u16mf2(__VA_ARGS__) -#define vsoxseg6ei32_v_u16mf2(...) __riscv_vsoxseg6ei32_v_u16mf2(__VA_ARGS__) -#define vsoxseg7ei32_v_u16mf2(...) __riscv_vsoxseg7ei32_v_u16mf2(__VA_ARGS__) -#define vsoxseg8ei32_v_u16mf2(...) __riscv_vsoxseg8ei32_v_u16mf2(__VA_ARGS__) -#define vsoxseg2ei32_v_u16m1(...) __riscv_vsoxseg2ei32_v_u16m1(__VA_ARGS__) -#define vsoxseg3ei32_v_u16m1(...) __riscv_vsoxseg3ei32_v_u16m1(__VA_ARGS__) -#define vsoxseg4ei32_v_u16m1(...) __riscv_vsoxseg4ei32_v_u16m1(__VA_ARGS__) -#define vsoxseg5ei32_v_u16m1(...) __riscv_vsoxseg5ei32_v_u16m1(__VA_ARGS__) -#define vsoxseg6ei32_v_u16m1(...) __riscv_vsoxseg6ei32_v_u16m1(__VA_ARGS__) -#define vsoxseg7ei32_v_u16m1(...) __riscv_vsoxseg7ei32_v_u16m1(__VA_ARGS__) -#define vsoxseg8ei32_v_u16m1(...) __riscv_vsoxseg8ei32_v_u16m1(__VA_ARGS__) -#define vsoxseg2ei32_v_u16m2(...) __riscv_vsoxseg2ei32_v_u16m2(__VA_ARGS__) -#define vsoxseg3ei32_v_u16m2(...) __riscv_vsoxseg3ei32_v_u16m2(__VA_ARGS__) -#define vsoxseg4ei32_v_u16m2(...) __riscv_vsoxseg4ei32_v_u16m2(__VA_ARGS__) -#define vsoxseg2ei32_v_u16m4(...) __riscv_vsoxseg2ei32_v_u16m4(__VA_ARGS__) -#define vsoxseg2ei64_v_u16mf4(...) __riscv_vsoxseg2ei64_v_u16mf4(__VA_ARGS__) -#define vsoxseg3ei64_v_u16mf4(...) __riscv_vsoxseg3ei64_v_u16mf4(__VA_ARGS__) -#define vsoxseg4ei64_v_u16mf4(...) __riscv_vsoxseg4ei64_v_u16mf4(__VA_ARGS__) -#define vsoxseg5ei64_v_u16mf4(...) __riscv_vsoxseg5ei64_v_u16mf4(__VA_ARGS__) -#define vsoxseg6ei64_v_u16mf4(...) __riscv_vsoxseg6ei64_v_u16mf4(__VA_ARGS__) -#define vsoxseg7ei64_v_u16mf4(...) __riscv_vsoxseg7ei64_v_u16mf4(__VA_ARGS__) -#define vsoxseg8ei64_v_u16mf4(...) __riscv_vsoxseg8ei64_v_u16mf4(__VA_ARGS__) -#define vsoxseg2ei64_v_u16mf2(...) __riscv_vsoxseg2ei64_v_u16mf2(__VA_ARGS__) -#define vsoxseg3ei64_v_u16mf2(...) __riscv_vsoxseg3ei64_v_u16mf2(__VA_ARGS__) -#define vsoxseg4ei64_v_u16mf2(...) __riscv_vsoxseg4ei64_v_u16mf2(__VA_ARGS__) -#define vsoxseg5ei64_v_u16mf2(...) __riscv_vsoxseg5ei64_v_u16mf2(__VA_ARGS__) -#define vsoxseg6ei64_v_u16mf2(...) __riscv_vsoxseg6ei64_v_u16mf2(__VA_ARGS__) -#define vsoxseg7ei64_v_u16mf2(...) __riscv_vsoxseg7ei64_v_u16mf2(__VA_ARGS__) -#define vsoxseg8ei64_v_u16mf2(...) __riscv_vsoxseg8ei64_v_u16mf2(__VA_ARGS__) -#define vsoxseg2ei64_v_u16m1(...) __riscv_vsoxseg2ei64_v_u16m1(__VA_ARGS__) -#define vsoxseg3ei64_v_u16m1(...) __riscv_vsoxseg3ei64_v_u16m1(__VA_ARGS__) -#define vsoxseg4ei64_v_u16m1(...) __riscv_vsoxseg4ei64_v_u16m1(__VA_ARGS__) -#define vsoxseg5ei64_v_u16m1(...) __riscv_vsoxseg5ei64_v_u16m1(__VA_ARGS__) -#define vsoxseg6ei64_v_u16m1(...) __riscv_vsoxseg6ei64_v_u16m1(__VA_ARGS__) -#define vsoxseg7ei64_v_u16m1(...) __riscv_vsoxseg7ei64_v_u16m1(__VA_ARGS__) -#define vsoxseg8ei64_v_u16m1(...) __riscv_vsoxseg8ei64_v_u16m1(__VA_ARGS__) -#define vsoxseg2ei64_v_u16m2(...) __riscv_vsoxseg2ei64_v_u16m2(__VA_ARGS__) -#define vsoxseg3ei64_v_u16m2(...) __riscv_vsoxseg3ei64_v_u16m2(__VA_ARGS__) -#define vsoxseg4ei64_v_u16m2(...) __riscv_vsoxseg4ei64_v_u16m2(__VA_ARGS__) -#define vsoxseg2ei8_v_u32mf2(...) __riscv_vsoxseg2ei8_v_u32mf2(__VA_ARGS__) -#define vsoxseg3ei8_v_u32mf2(...) __riscv_vsoxseg3ei8_v_u32mf2(__VA_ARGS__) -#define vsoxseg4ei8_v_u32mf2(...) __riscv_vsoxseg4ei8_v_u32mf2(__VA_ARGS__) -#define vsoxseg5ei8_v_u32mf2(...) __riscv_vsoxseg5ei8_v_u32mf2(__VA_ARGS__) -#define vsoxseg6ei8_v_u32mf2(...) __riscv_vsoxseg6ei8_v_u32mf2(__VA_ARGS__) -#define vsoxseg7ei8_v_u32mf2(...) __riscv_vsoxseg7ei8_v_u32mf2(__VA_ARGS__) -#define vsoxseg8ei8_v_u32mf2(...) __riscv_vsoxseg8ei8_v_u32mf2(__VA_ARGS__) -#define vsoxseg2ei8_v_u32m1(...) __riscv_vsoxseg2ei8_v_u32m1(__VA_ARGS__) -#define vsoxseg3ei8_v_u32m1(...) __riscv_vsoxseg3ei8_v_u32m1(__VA_ARGS__) -#define vsoxseg4ei8_v_u32m1(...) __riscv_vsoxseg4ei8_v_u32m1(__VA_ARGS__) -#define vsoxseg5ei8_v_u32m1(...) __riscv_vsoxseg5ei8_v_u32m1(__VA_ARGS__) -#define vsoxseg6ei8_v_u32m1(...) __riscv_vsoxseg6ei8_v_u32m1(__VA_ARGS__) -#define vsoxseg7ei8_v_u32m1(...) __riscv_vsoxseg7ei8_v_u32m1(__VA_ARGS__) -#define vsoxseg8ei8_v_u32m1(...) __riscv_vsoxseg8ei8_v_u32m1(__VA_ARGS__) -#define vsoxseg2ei8_v_u32m2(...) __riscv_vsoxseg2ei8_v_u32m2(__VA_ARGS__) -#define vsoxseg3ei8_v_u32m2(...) __riscv_vsoxseg3ei8_v_u32m2(__VA_ARGS__) -#define vsoxseg4ei8_v_u32m2(...) __riscv_vsoxseg4ei8_v_u32m2(__VA_ARGS__) -#define vsoxseg2ei8_v_u32m4(...) __riscv_vsoxseg2ei8_v_u32m4(__VA_ARGS__) -#define vsoxseg2ei16_v_u32mf2(...) __riscv_vsoxseg2ei16_v_u32mf2(__VA_ARGS__) -#define vsoxseg3ei16_v_u32mf2(...) __riscv_vsoxseg3ei16_v_u32mf2(__VA_ARGS__) -#define vsoxseg4ei16_v_u32mf2(...) __riscv_vsoxseg4ei16_v_u32mf2(__VA_ARGS__) -#define vsoxseg5ei16_v_u32mf2(...) __riscv_vsoxseg5ei16_v_u32mf2(__VA_ARGS__) -#define vsoxseg6ei16_v_u32mf2(...) __riscv_vsoxseg6ei16_v_u32mf2(__VA_ARGS__) -#define vsoxseg7ei16_v_u32mf2(...) __riscv_vsoxseg7ei16_v_u32mf2(__VA_ARGS__) -#define vsoxseg8ei16_v_u32mf2(...) __riscv_vsoxseg8ei16_v_u32mf2(__VA_ARGS__) -#define vsoxseg2ei16_v_u32m1(...) __riscv_vsoxseg2ei16_v_u32m1(__VA_ARGS__) -#define vsoxseg3ei16_v_u32m1(...) __riscv_vsoxseg3ei16_v_u32m1(__VA_ARGS__) -#define vsoxseg4ei16_v_u32m1(...) __riscv_vsoxseg4ei16_v_u32m1(__VA_ARGS__) -#define vsoxseg5ei16_v_u32m1(...) __riscv_vsoxseg5ei16_v_u32m1(__VA_ARGS__) -#define vsoxseg6ei16_v_u32m1(...) __riscv_vsoxseg6ei16_v_u32m1(__VA_ARGS__) -#define vsoxseg7ei16_v_u32m1(...) __riscv_vsoxseg7ei16_v_u32m1(__VA_ARGS__) -#define vsoxseg8ei16_v_u32m1(...) __riscv_vsoxseg8ei16_v_u32m1(__VA_ARGS__) -#define vsoxseg2ei16_v_u32m2(...) __riscv_vsoxseg2ei16_v_u32m2(__VA_ARGS__) -#define vsoxseg3ei16_v_u32m2(...) __riscv_vsoxseg3ei16_v_u32m2(__VA_ARGS__) -#define vsoxseg4ei16_v_u32m2(...) __riscv_vsoxseg4ei16_v_u32m2(__VA_ARGS__) -#define vsoxseg2ei16_v_u32m4(...) __riscv_vsoxseg2ei16_v_u32m4(__VA_ARGS__) -#define vsoxseg2ei32_v_u32mf2(...) __riscv_vsoxseg2ei32_v_u32mf2(__VA_ARGS__) -#define vsoxseg3ei32_v_u32mf2(...) __riscv_vsoxseg3ei32_v_u32mf2(__VA_ARGS__) -#define vsoxseg4ei32_v_u32mf2(...) __riscv_vsoxseg4ei32_v_u32mf2(__VA_ARGS__) -#define vsoxseg5ei32_v_u32mf2(...) __riscv_vsoxseg5ei32_v_u32mf2(__VA_ARGS__) -#define vsoxseg6ei32_v_u32mf2(...) __riscv_vsoxseg6ei32_v_u32mf2(__VA_ARGS__) -#define vsoxseg7ei32_v_u32mf2(...) __riscv_vsoxseg7ei32_v_u32mf2(__VA_ARGS__) -#define vsoxseg8ei32_v_u32mf2(...) __riscv_vsoxseg8ei32_v_u32mf2(__VA_ARGS__) -#define vsoxseg2ei32_v_u32m1(...) __riscv_vsoxseg2ei32_v_u32m1(__VA_ARGS__) -#define vsoxseg3ei32_v_u32m1(...) __riscv_vsoxseg3ei32_v_u32m1(__VA_ARGS__) -#define vsoxseg4ei32_v_u32m1(...) __riscv_vsoxseg4ei32_v_u32m1(__VA_ARGS__) -#define vsoxseg5ei32_v_u32m1(...) __riscv_vsoxseg5ei32_v_u32m1(__VA_ARGS__) -#define vsoxseg6ei32_v_u32m1(...) __riscv_vsoxseg6ei32_v_u32m1(__VA_ARGS__) -#define vsoxseg7ei32_v_u32m1(...) __riscv_vsoxseg7ei32_v_u32m1(__VA_ARGS__) -#define vsoxseg8ei32_v_u32m1(...) __riscv_vsoxseg8ei32_v_u32m1(__VA_ARGS__) -#define vsoxseg2ei32_v_u32m2(...) __riscv_vsoxseg2ei32_v_u32m2(__VA_ARGS__) -#define vsoxseg3ei32_v_u32m2(...) __riscv_vsoxseg3ei32_v_u32m2(__VA_ARGS__) -#define vsoxseg4ei32_v_u32m2(...) __riscv_vsoxseg4ei32_v_u32m2(__VA_ARGS__) -#define vsoxseg2ei32_v_u32m4(...) __riscv_vsoxseg2ei32_v_u32m4(__VA_ARGS__) -#define vsoxseg2ei64_v_u32mf2(...) __riscv_vsoxseg2ei64_v_u32mf2(__VA_ARGS__) -#define vsoxseg3ei64_v_u32mf2(...) __riscv_vsoxseg3ei64_v_u32mf2(__VA_ARGS__) -#define vsoxseg4ei64_v_u32mf2(...) __riscv_vsoxseg4ei64_v_u32mf2(__VA_ARGS__) -#define vsoxseg5ei64_v_u32mf2(...) __riscv_vsoxseg5ei64_v_u32mf2(__VA_ARGS__) -#define vsoxseg6ei64_v_u32mf2(...) __riscv_vsoxseg6ei64_v_u32mf2(__VA_ARGS__) -#define vsoxseg7ei64_v_u32mf2(...) __riscv_vsoxseg7ei64_v_u32mf2(__VA_ARGS__) -#define vsoxseg8ei64_v_u32mf2(...) __riscv_vsoxseg8ei64_v_u32mf2(__VA_ARGS__) -#define vsoxseg2ei64_v_u32m1(...) __riscv_vsoxseg2ei64_v_u32m1(__VA_ARGS__) -#define vsoxseg3ei64_v_u32m1(...) __riscv_vsoxseg3ei64_v_u32m1(__VA_ARGS__) -#define vsoxseg4ei64_v_u32m1(...) __riscv_vsoxseg4ei64_v_u32m1(__VA_ARGS__) -#define vsoxseg5ei64_v_u32m1(...) __riscv_vsoxseg5ei64_v_u32m1(__VA_ARGS__) -#define vsoxseg6ei64_v_u32m1(...) __riscv_vsoxseg6ei64_v_u32m1(__VA_ARGS__) -#define vsoxseg7ei64_v_u32m1(...) __riscv_vsoxseg7ei64_v_u32m1(__VA_ARGS__) -#define vsoxseg8ei64_v_u32m1(...) __riscv_vsoxseg8ei64_v_u32m1(__VA_ARGS__) -#define vsoxseg2ei64_v_u32m2(...) __riscv_vsoxseg2ei64_v_u32m2(__VA_ARGS__) -#define vsoxseg3ei64_v_u32m2(...) __riscv_vsoxseg3ei64_v_u32m2(__VA_ARGS__) -#define vsoxseg4ei64_v_u32m2(...) __riscv_vsoxseg4ei64_v_u32m2(__VA_ARGS__) -#define vsoxseg2ei64_v_u32m4(...) __riscv_vsoxseg2ei64_v_u32m4(__VA_ARGS__) -#define vsoxseg2ei8_v_u64m1(...) __riscv_vsoxseg2ei8_v_u64m1(__VA_ARGS__) -#define vsoxseg3ei8_v_u64m1(...) __riscv_vsoxseg3ei8_v_u64m1(__VA_ARGS__) -#define vsoxseg4ei8_v_u64m1(...) __riscv_vsoxseg4ei8_v_u64m1(__VA_ARGS__) -#define vsoxseg5ei8_v_u64m1(...) __riscv_vsoxseg5ei8_v_u64m1(__VA_ARGS__) -#define vsoxseg6ei8_v_u64m1(...) __riscv_vsoxseg6ei8_v_u64m1(__VA_ARGS__) -#define vsoxseg7ei8_v_u64m1(...) __riscv_vsoxseg7ei8_v_u64m1(__VA_ARGS__) -#define vsoxseg8ei8_v_u64m1(...) __riscv_vsoxseg8ei8_v_u64m1(__VA_ARGS__) -#define vsoxseg2ei8_v_u64m2(...) __riscv_vsoxseg2ei8_v_u64m2(__VA_ARGS__) -#define vsoxseg3ei8_v_u64m2(...) __riscv_vsoxseg3ei8_v_u64m2(__VA_ARGS__) -#define vsoxseg4ei8_v_u64m2(...) __riscv_vsoxseg4ei8_v_u64m2(__VA_ARGS__) -#define vsoxseg2ei8_v_u64m4(...) __riscv_vsoxseg2ei8_v_u64m4(__VA_ARGS__) -#define vsoxseg2ei16_v_u64m1(...) __riscv_vsoxseg2ei16_v_u64m1(__VA_ARGS__) -#define vsoxseg3ei16_v_u64m1(...) __riscv_vsoxseg3ei16_v_u64m1(__VA_ARGS__) -#define vsoxseg4ei16_v_u64m1(...) __riscv_vsoxseg4ei16_v_u64m1(__VA_ARGS__) -#define vsoxseg5ei16_v_u64m1(...) __riscv_vsoxseg5ei16_v_u64m1(__VA_ARGS__) -#define vsoxseg6ei16_v_u64m1(...) __riscv_vsoxseg6ei16_v_u64m1(__VA_ARGS__) -#define vsoxseg7ei16_v_u64m1(...) __riscv_vsoxseg7ei16_v_u64m1(__VA_ARGS__) -#define vsoxseg8ei16_v_u64m1(...) __riscv_vsoxseg8ei16_v_u64m1(__VA_ARGS__) -#define vsoxseg2ei16_v_u64m2(...) __riscv_vsoxseg2ei16_v_u64m2(__VA_ARGS__) -#define vsoxseg3ei16_v_u64m2(...) __riscv_vsoxseg3ei16_v_u64m2(__VA_ARGS__) -#define vsoxseg4ei16_v_u64m2(...) __riscv_vsoxseg4ei16_v_u64m2(__VA_ARGS__) -#define vsoxseg2ei16_v_u64m4(...) __riscv_vsoxseg2ei16_v_u64m4(__VA_ARGS__) -#define vsoxseg2ei32_v_u64m1(...) __riscv_vsoxseg2ei32_v_u64m1(__VA_ARGS__) -#define vsoxseg3ei32_v_u64m1(...) __riscv_vsoxseg3ei32_v_u64m1(__VA_ARGS__) -#define vsoxseg4ei32_v_u64m1(...) __riscv_vsoxseg4ei32_v_u64m1(__VA_ARGS__) -#define vsoxseg5ei32_v_u64m1(...) __riscv_vsoxseg5ei32_v_u64m1(__VA_ARGS__) -#define vsoxseg6ei32_v_u64m1(...) __riscv_vsoxseg6ei32_v_u64m1(__VA_ARGS__) -#define vsoxseg7ei32_v_u64m1(...) __riscv_vsoxseg7ei32_v_u64m1(__VA_ARGS__) -#define vsoxseg8ei32_v_u64m1(...) __riscv_vsoxseg8ei32_v_u64m1(__VA_ARGS__) -#define vsoxseg2ei32_v_u64m2(...) __riscv_vsoxseg2ei32_v_u64m2(__VA_ARGS__) -#define vsoxseg3ei32_v_u64m2(...) __riscv_vsoxseg3ei32_v_u64m2(__VA_ARGS__) -#define vsoxseg4ei32_v_u64m2(...) __riscv_vsoxseg4ei32_v_u64m2(__VA_ARGS__) -#define vsoxseg2ei32_v_u64m4(...) __riscv_vsoxseg2ei32_v_u64m4(__VA_ARGS__) -#define vsoxseg2ei64_v_u64m1(...) __riscv_vsoxseg2ei64_v_u64m1(__VA_ARGS__) -#define vsoxseg3ei64_v_u64m1(...) __riscv_vsoxseg3ei64_v_u64m1(__VA_ARGS__) -#define vsoxseg4ei64_v_u64m1(...) __riscv_vsoxseg4ei64_v_u64m1(__VA_ARGS__) -#define vsoxseg5ei64_v_u64m1(...) __riscv_vsoxseg5ei64_v_u64m1(__VA_ARGS__) -#define vsoxseg6ei64_v_u64m1(...) __riscv_vsoxseg6ei64_v_u64m1(__VA_ARGS__) -#define vsoxseg7ei64_v_u64m1(...) __riscv_vsoxseg7ei64_v_u64m1(__VA_ARGS__) -#define vsoxseg8ei64_v_u64m1(...) __riscv_vsoxseg8ei64_v_u64m1(__VA_ARGS__) -#define vsoxseg2ei64_v_u64m2(...) __riscv_vsoxseg2ei64_v_u64m2(__VA_ARGS__) -#define vsoxseg3ei64_v_u64m2(...) __riscv_vsoxseg3ei64_v_u64m2(__VA_ARGS__) -#define vsoxseg4ei64_v_u64m2(...) __riscv_vsoxseg4ei64_v_u64m2(__VA_ARGS__) -#define vsoxseg2ei64_v_u64m4(...) __riscv_vsoxseg2ei64_v_u64m4(__VA_ARGS__) -#define vsuxseg2ei8_v_u8mf8(...) __riscv_vsuxseg2ei8_v_u8mf8(__VA_ARGS__) -#define vsuxseg3ei8_v_u8mf8(...) __riscv_vsuxseg3ei8_v_u8mf8(__VA_ARGS__) -#define vsuxseg4ei8_v_u8mf8(...) __riscv_vsuxseg4ei8_v_u8mf8(__VA_ARGS__) -#define vsuxseg5ei8_v_u8mf8(...) __riscv_vsuxseg5ei8_v_u8mf8(__VA_ARGS__) -#define vsuxseg6ei8_v_u8mf8(...) __riscv_vsuxseg6ei8_v_u8mf8(__VA_ARGS__) -#define vsuxseg7ei8_v_u8mf8(...) __riscv_vsuxseg7ei8_v_u8mf8(__VA_ARGS__) -#define vsuxseg8ei8_v_u8mf8(...) __riscv_vsuxseg8ei8_v_u8mf8(__VA_ARGS__) -#define vsuxseg2ei8_v_u8mf4(...) __riscv_vsuxseg2ei8_v_u8mf4(__VA_ARGS__) -#define vsuxseg3ei8_v_u8mf4(...) __riscv_vsuxseg3ei8_v_u8mf4(__VA_ARGS__) -#define vsuxseg4ei8_v_u8mf4(...) __riscv_vsuxseg4ei8_v_u8mf4(__VA_ARGS__) -#define vsuxseg5ei8_v_u8mf4(...) __riscv_vsuxseg5ei8_v_u8mf4(__VA_ARGS__) -#define vsuxseg6ei8_v_u8mf4(...) __riscv_vsuxseg6ei8_v_u8mf4(__VA_ARGS__) -#define vsuxseg7ei8_v_u8mf4(...) __riscv_vsuxseg7ei8_v_u8mf4(__VA_ARGS__) -#define vsuxseg8ei8_v_u8mf4(...) __riscv_vsuxseg8ei8_v_u8mf4(__VA_ARGS__) -#define vsuxseg2ei8_v_u8mf2(...) __riscv_vsuxseg2ei8_v_u8mf2(__VA_ARGS__) -#define vsuxseg3ei8_v_u8mf2(...) __riscv_vsuxseg3ei8_v_u8mf2(__VA_ARGS__) -#define vsuxseg4ei8_v_u8mf2(...) __riscv_vsuxseg4ei8_v_u8mf2(__VA_ARGS__) -#define vsuxseg5ei8_v_u8mf2(...) __riscv_vsuxseg5ei8_v_u8mf2(__VA_ARGS__) -#define vsuxseg6ei8_v_u8mf2(...) __riscv_vsuxseg6ei8_v_u8mf2(__VA_ARGS__) -#define vsuxseg7ei8_v_u8mf2(...) __riscv_vsuxseg7ei8_v_u8mf2(__VA_ARGS__) -#define vsuxseg8ei8_v_u8mf2(...) __riscv_vsuxseg8ei8_v_u8mf2(__VA_ARGS__) -#define vsuxseg2ei8_v_u8m1(...) __riscv_vsuxseg2ei8_v_u8m1(__VA_ARGS__) -#define vsuxseg3ei8_v_u8m1(...) __riscv_vsuxseg3ei8_v_u8m1(__VA_ARGS__) -#define vsuxseg4ei8_v_u8m1(...) __riscv_vsuxseg4ei8_v_u8m1(__VA_ARGS__) -#define vsuxseg5ei8_v_u8m1(...) __riscv_vsuxseg5ei8_v_u8m1(__VA_ARGS__) -#define vsuxseg6ei8_v_u8m1(...) __riscv_vsuxseg6ei8_v_u8m1(__VA_ARGS__) -#define vsuxseg7ei8_v_u8m1(...) __riscv_vsuxseg7ei8_v_u8m1(__VA_ARGS__) -#define vsuxseg8ei8_v_u8m1(...) __riscv_vsuxseg8ei8_v_u8m1(__VA_ARGS__) -#define vsuxseg2ei8_v_u8m2(...) __riscv_vsuxseg2ei8_v_u8m2(__VA_ARGS__) -#define vsuxseg3ei8_v_u8m2(...) __riscv_vsuxseg3ei8_v_u8m2(__VA_ARGS__) -#define vsuxseg4ei8_v_u8m2(...) __riscv_vsuxseg4ei8_v_u8m2(__VA_ARGS__) -#define vsuxseg2ei8_v_u8m4(...) __riscv_vsuxseg2ei8_v_u8m4(__VA_ARGS__) -#define vsuxseg2ei16_v_u8mf8(...) __riscv_vsuxseg2ei16_v_u8mf8(__VA_ARGS__) -#define vsuxseg3ei16_v_u8mf8(...) __riscv_vsuxseg3ei16_v_u8mf8(__VA_ARGS__) -#define vsuxseg4ei16_v_u8mf8(...) __riscv_vsuxseg4ei16_v_u8mf8(__VA_ARGS__) -#define vsuxseg5ei16_v_u8mf8(...) __riscv_vsuxseg5ei16_v_u8mf8(__VA_ARGS__) -#define vsuxseg6ei16_v_u8mf8(...) __riscv_vsuxseg6ei16_v_u8mf8(__VA_ARGS__) -#define vsuxseg7ei16_v_u8mf8(...) __riscv_vsuxseg7ei16_v_u8mf8(__VA_ARGS__) -#define vsuxseg8ei16_v_u8mf8(...) __riscv_vsuxseg8ei16_v_u8mf8(__VA_ARGS__) -#define vsuxseg2ei16_v_u8mf4(...) __riscv_vsuxseg2ei16_v_u8mf4(__VA_ARGS__) -#define vsuxseg3ei16_v_u8mf4(...) __riscv_vsuxseg3ei16_v_u8mf4(__VA_ARGS__) -#define vsuxseg4ei16_v_u8mf4(...) __riscv_vsuxseg4ei16_v_u8mf4(__VA_ARGS__) -#define vsuxseg5ei16_v_u8mf4(...) __riscv_vsuxseg5ei16_v_u8mf4(__VA_ARGS__) -#define vsuxseg6ei16_v_u8mf4(...) __riscv_vsuxseg6ei16_v_u8mf4(__VA_ARGS__) -#define vsuxseg7ei16_v_u8mf4(...) __riscv_vsuxseg7ei16_v_u8mf4(__VA_ARGS__) -#define vsuxseg8ei16_v_u8mf4(...) __riscv_vsuxseg8ei16_v_u8mf4(__VA_ARGS__) -#define vsuxseg2ei16_v_u8mf2(...) __riscv_vsuxseg2ei16_v_u8mf2(__VA_ARGS__) -#define vsuxseg3ei16_v_u8mf2(...) __riscv_vsuxseg3ei16_v_u8mf2(__VA_ARGS__) -#define vsuxseg4ei16_v_u8mf2(...) __riscv_vsuxseg4ei16_v_u8mf2(__VA_ARGS__) -#define vsuxseg5ei16_v_u8mf2(...) __riscv_vsuxseg5ei16_v_u8mf2(__VA_ARGS__) -#define vsuxseg6ei16_v_u8mf2(...) __riscv_vsuxseg6ei16_v_u8mf2(__VA_ARGS__) -#define vsuxseg7ei16_v_u8mf2(...) __riscv_vsuxseg7ei16_v_u8mf2(__VA_ARGS__) -#define vsuxseg8ei16_v_u8mf2(...) __riscv_vsuxseg8ei16_v_u8mf2(__VA_ARGS__) -#define vsuxseg2ei16_v_u8m1(...) __riscv_vsuxseg2ei16_v_u8m1(__VA_ARGS__) -#define vsuxseg3ei16_v_u8m1(...) __riscv_vsuxseg3ei16_v_u8m1(__VA_ARGS__) -#define vsuxseg4ei16_v_u8m1(...) __riscv_vsuxseg4ei16_v_u8m1(__VA_ARGS__) -#define vsuxseg5ei16_v_u8m1(...) __riscv_vsuxseg5ei16_v_u8m1(__VA_ARGS__) -#define vsuxseg6ei16_v_u8m1(...) __riscv_vsuxseg6ei16_v_u8m1(__VA_ARGS__) -#define vsuxseg7ei16_v_u8m1(...) __riscv_vsuxseg7ei16_v_u8m1(__VA_ARGS__) -#define vsuxseg8ei16_v_u8m1(...) __riscv_vsuxseg8ei16_v_u8m1(__VA_ARGS__) -#define vsuxseg2ei16_v_u8m2(...) __riscv_vsuxseg2ei16_v_u8m2(__VA_ARGS__) -#define vsuxseg3ei16_v_u8m2(...) __riscv_vsuxseg3ei16_v_u8m2(__VA_ARGS__) -#define vsuxseg4ei16_v_u8m2(...) __riscv_vsuxseg4ei16_v_u8m2(__VA_ARGS__) -#define vsuxseg2ei16_v_u8m4(...) __riscv_vsuxseg2ei16_v_u8m4(__VA_ARGS__) -#define vsuxseg2ei32_v_u8mf8(...) __riscv_vsuxseg2ei32_v_u8mf8(__VA_ARGS__) -#define vsuxseg3ei32_v_u8mf8(...) __riscv_vsuxseg3ei32_v_u8mf8(__VA_ARGS__) -#define vsuxseg4ei32_v_u8mf8(...) __riscv_vsuxseg4ei32_v_u8mf8(__VA_ARGS__) -#define vsuxseg5ei32_v_u8mf8(...) __riscv_vsuxseg5ei32_v_u8mf8(__VA_ARGS__) -#define vsuxseg6ei32_v_u8mf8(...) __riscv_vsuxseg6ei32_v_u8mf8(__VA_ARGS__) -#define vsuxseg7ei32_v_u8mf8(...) __riscv_vsuxseg7ei32_v_u8mf8(__VA_ARGS__) -#define vsuxseg8ei32_v_u8mf8(...) __riscv_vsuxseg8ei32_v_u8mf8(__VA_ARGS__) -#define vsuxseg2ei32_v_u8mf4(...) __riscv_vsuxseg2ei32_v_u8mf4(__VA_ARGS__) -#define vsuxseg3ei32_v_u8mf4(...) __riscv_vsuxseg3ei32_v_u8mf4(__VA_ARGS__) -#define vsuxseg4ei32_v_u8mf4(...) __riscv_vsuxseg4ei32_v_u8mf4(__VA_ARGS__) -#define vsuxseg5ei32_v_u8mf4(...) __riscv_vsuxseg5ei32_v_u8mf4(__VA_ARGS__) -#define vsuxseg6ei32_v_u8mf4(...) __riscv_vsuxseg6ei32_v_u8mf4(__VA_ARGS__) -#define vsuxseg7ei32_v_u8mf4(...) __riscv_vsuxseg7ei32_v_u8mf4(__VA_ARGS__) -#define vsuxseg8ei32_v_u8mf4(...) __riscv_vsuxseg8ei32_v_u8mf4(__VA_ARGS__) -#define vsuxseg2ei32_v_u8mf2(...) __riscv_vsuxseg2ei32_v_u8mf2(__VA_ARGS__) -#define vsuxseg3ei32_v_u8mf2(...) __riscv_vsuxseg3ei32_v_u8mf2(__VA_ARGS__) -#define vsuxseg4ei32_v_u8mf2(...) __riscv_vsuxseg4ei32_v_u8mf2(__VA_ARGS__) -#define vsuxseg5ei32_v_u8mf2(...) __riscv_vsuxseg5ei32_v_u8mf2(__VA_ARGS__) -#define vsuxseg6ei32_v_u8mf2(...) __riscv_vsuxseg6ei32_v_u8mf2(__VA_ARGS__) -#define vsuxseg7ei32_v_u8mf2(...) __riscv_vsuxseg7ei32_v_u8mf2(__VA_ARGS__) -#define vsuxseg8ei32_v_u8mf2(...) __riscv_vsuxseg8ei32_v_u8mf2(__VA_ARGS__) -#define vsuxseg2ei32_v_u8m1(...) __riscv_vsuxseg2ei32_v_u8m1(__VA_ARGS__) -#define vsuxseg3ei32_v_u8m1(...) __riscv_vsuxseg3ei32_v_u8m1(__VA_ARGS__) -#define vsuxseg4ei32_v_u8m1(...) __riscv_vsuxseg4ei32_v_u8m1(__VA_ARGS__) -#define vsuxseg5ei32_v_u8m1(...) __riscv_vsuxseg5ei32_v_u8m1(__VA_ARGS__) -#define vsuxseg6ei32_v_u8m1(...) __riscv_vsuxseg6ei32_v_u8m1(__VA_ARGS__) -#define vsuxseg7ei32_v_u8m1(...) __riscv_vsuxseg7ei32_v_u8m1(__VA_ARGS__) -#define vsuxseg8ei32_v_u8m1(...) __riscv_vsuxseg8ei32_v_u8m1(__VA_ARGS__) -#define vsuxseg2ei32_v_u8m2(...) __riscv_vsuxseg2ei32_v_u8m2(__VA_ARGS__) -#define vsuxseg3ei32_v_u8m2(...) __riscv_vsuxseg3ei32_v_u8m2(__VA_ARGS__) -#define vsuxseg4ei32_v_u8m2(...) __riscv_vsuxseg4ei32_v_u8m2(__VA_ARGS__) -#define vsuxseg2ei64_v_u8mf8(...) __riscv_vsuxseg2ei64_v_u8mf8(__VA_ARGS__) -#define vsuxseg3ei64_v_u8mf8(...) __riscv_vsuxseg3ei64_v_u8mf8(__VA_ARGS__) -#define vsuxseg4ei64_v_u8mf8(...) __riscv_vsuxseg4ei64_v_u8mf8(__VA_ARGS__) -#define vsuxseg5ei64_v_u8mf8(...) __riscv_vsuxseg5ei64_v_u8mf8(__VA_ARGS__) -#define vsuxseg6ei64_v_u8mf8(...) __riscv_vsuxseg6ei64_v_u8mf8(__VA_ARGS__) -#define vsuxseg7ei64_v_u8mf8(...) __riscv_vsuxseg7ei64_v_u8mf8(__VA_ARGS__) -#define vsuxseg8ei64_v_u8mf8(...) __riscv_vsuxseg8ei64_v_u8mf8(__VA_ARGS__) -#define vsuxseg2ei64_v_u8mf4(...) __riscv_vsuxseg2ei64_v_u8mf4(__VA_ARGS__) -#define vsuxseg3ei64_v_u8mf4(...) __riscv_vsuxseg3ei64_v_u8mf4(__VA_ARGS__) -#define vsuxseg4ei64_v_u8mf4(...) __riscv_vsuxseg4ei64_v_u8mf4(__VA_ARGS__) -#define vsuxseg5ei64_v_u8mf4(...) __riscv_vsuxseg5ei64_v_u8mf4(__VA_ARGS__) -#define vsuxseg6ei64_v_u8mf4(...) __riscv_vsuxseg6ei64_v_u8mf4(__VA_ARGS__) -#define vsuxseg7ei64_v_u8mf4(...) __riscv_vsuxseg7ei64_v_u8mf4(__VA_ARGS__) -#define vsuxseg8ei64_v_u8mf4(...) __riscv_vsuxseg8ei64_v_u8mf4(__VA_ARGS__) -#define vsuxseg2ei64_v_u8mf2(...) __riscv_vsuxseg2ei64_v_u8mf2(__VA_ARGS__) -#define vsuxseg3ei64_v_u8mf2(...) __riscv_vsuxseg3ei64_v_u8mf2(__VA_ARGS__) -#define vsuxseg4ei64_v_u8mf2(...) __riscv_vsuxseg4ei64_v_u8mf2(__VA_ARGS__) -#define vsuxseg5ei64_v_u8mf2(...) __riscv_vsuxseg5ei64_v_u8mf2(__VA_ARGS__) -#define vsuxseg6ei64_v_u8mf2(...) __riscv_vsuxseg6ei64_v_u8mf2(__VA_ARGS__) -#define vsuxseg7ei64_v_u8mf2(...) __riscv_vsuxseg7ei64_v_u8mf2(__VA_ARGS__) -#define vsuxseg8ei64_v_u8mf2(...) __riscv_vsuxseg8ei64_v_u8mf2(__VA_ARGS__) -#define vsuxseg2ei64_v_u8m1(...) __riscv_vsuxseg2ei64_v_u8m1(__VA_ARGS__) -#define vsuxseg3ei64_v_u8m1(...) __riscv_vsuxseg3ei64_v_u8m1(__VA_ARGS__) -#define vsuxseg4ei64_v_u8m1(...) __riscv_vsuxseg4ei64_v_u8m1(__VA_ARGS__) -#define vsuxseg5ei64_v_u8m1(...) __riscv_vsuxseg5ei64_v_u8m1(__VA_ARGS__) -#define vsuxseg6ei64_v_u8m1(...) __riscv_vsuxseg6ei64_v_u8m1(__VA_ARGS__) -#define vsuxseg7ei64_v_u8m1(...) __riscv_vsuxseg7ei64_v_u8m1(__VA_ARGS__) -#define vsuxseg8ei64_v_u8m1(...) __riscv_vsuxseg8ei64_v_u8m1(__VA_ARGS__) -#define vsuxseg2ei8_v_u16mf4(...) __riscv_vsuxseg2ei8_v_u16mf4(__VA_ARGS__) -#define vsuxseg3ei8_v_u16mf4(...) __riscv_vsuxseg3ei8_v_u16mf4(__VA_ARGS__) -#define vsuxseg4ei8_v_u16mf4(...) __riscv_vsuxseg4ei8_v_u16mf4(__VA_ARGS__) -#define vsuxseg5ei8_v_u16mf4(...) __riscv_vsuxseg5ei8_v_u16mf4(__VA_ARGS__) -#define vsuxseg6ei8_v_u16mf4(...) __riscv_vsuxseg6ei8_v_u16mf4(__VA_ARGS__) -#define vsuxseg7ei8_v_u16mf4(...) __riscv_vsuxseg7ei8_v_u16mf4(__VA_ARGS__) -#define vsuxseg8ei8_v_u16mf4(...) __riscv_vsuxseg8ei8_v_u16mf4(__VA_ARGS__) -#define vsuxseg2ei8_v_u16mf2(...) __riscv_vsuxseg2ei8_v_u16mf2(__VA_ARGS__) -#define vsuxseg3ei8_v_u16mf2(...) __riscv_vsuxseg3ei8_v_u16mf2(__VA_ARGS__) -#define vsuxseg4ei8_v_u16mf2(...) __riscv_vsuxseg4ei8_v_u16mf2(__VA_ARGS__) -#define vsuxseg5ei8_v_u16mf2(...) __riscv_vsuxseg5ei8_v_u16mf2(__VA_ARGS__) -#define vsuxseg6ei8_v_u16mf2(...) __riscv_vsuxseg6ei8_v_u16mf2(__VA_ARGS__) -#define vsuxseg7ei8_v_u16mf2(...) __riscv_vsuxseg7ei8_v_u16mf2(__VA_ARGS__) -#define vsuxseg8ei8_v_u16mf2(...) __riscv_vsuxseg8ei8_v_u16mf2(__VA_ARGS__) -#define vsuxseg2ei8_v_u16m1(...) __riscv_vsuxseg2ei8_v_u16m1(__VA_ARGS__) -#define vsuxseg3ei8_v_u16m1(...) __riscv_vsuxseg3ei8_v_u16m1(__VA_ARGS__) -#define vsuxseg4ei8_v_u16m1(...) __riscv_vsuxseg4ei8_v_u16m1(__VA_ARGS__) -#define vsuxseg5ei8_v_u16m1(...) __riscv_vsuxseg5ei8_v_u16m1(__VA_ARGS__) -#define vsuxseg6ei8_v_u16m1(...) __riscv_vsuxseg6ei8_v_u16m1(__VA_ARGS__) -#define vsuxseg7ei8_v_u16m1(...) __riscv_vsuxseg7ei8_v_u16m1(__VA_ARGS__) -#define vsuxseg8ei8_v_u16m1(...) __riscv_vsuxseg8ei8_v_u16m1(__VA_ARGS__) -#define vsuxseg2ei8_v_u16m2(...) __riscv_vsuxseg2ei8_v_u16m2(__VA_ARGS__) -#define vsuxseg3ei8_v_u16m2(...) __riscv_vsuxseg3ei8_v_u16m2(__VA_ARGS__) -#define vsuxseg4ei8_v_u16m2(...) __riscv_vsuxseg4ei8_v_u16m2(__VA_ARGS__) -#define vsuxseg2ei8_v_u16m4(...) __riscv_vsuxseg2ei8_v_u16m4(__VA_ARGS__) -#define vsuxseg2ei16_v_u16mf4(...) __riscv_vsuxseg2ei16_v_u16mf4(__VA_ARGS__) -#define vsuxseg3ei16_v_u16mf4(...) __riscv_vsuxseg3ei16_v_u16mf4(__VA_ARGS__) -#define vsuxseg4ei16_v_u16mf4(...) __riscv_vsuxseg4ei16_v_u16mf4(__VA_ARGS__) -#define vsuxseg5ei16_v_u16mf4(...) __riscv_vsuxseg5ei16_v_u16mf4(__VA_ARGS__) -#define vsuxseg6ei16_v_u16mf4(...) __riscv_vsuxseg6ei16_v_u16mf4(__VA_ARGS__) -#define vsuxseg7ei16_v_u16mf4(...) __riscv_vsuxseg7ei16_v_u16mf4(__VA_ARGS__) -#define vsuxseg8ei16_v_u16mf4(...) __riscv_vsuxseg8ei16_v_u16mf4(__VA_ARGS__) -#define vsuxseg2ei16_v_u16mf2(...) __riscv_vsuxseg2ei16_v_u16mf2(__VA_ARGS__) -#define vsuxseg3ei16_v_u16mf2(...) __riscv_vsuxseg3ei16_v_u16mf2(__VA_ARGS__) -#define vsuxseg4ei16_v_u16mf2(...) __riscv_vsuxseg4ei16_v_u16mf2(__VA_ARGS__) -#define vsuxseg5ei16_v_u16mf2(...) __riscv_vsuxseg5ei16_v_u16mf2(__VA_ARGS__) -#define vsuxseg6ei16_v_u16mf2(...) __riscv_vsuxseg6ei16_v_u16mf2(__VA_ARGS__) -#define vsuxseg7ei16_v_u16mf2(...) __riscv_vsuxseg7ei16_v_u16mf2(__VA_ARGS__) -#define vsuxseg8ei16_v_u16mf2(...) __riscv_vsuxseg8ei16_v_u16mf2(__VA_ARGS__) -#define vsuxseg2ei16_v_u16m1(...) __riscv_vsuxseg2ei16_v_u16m1(__VA_ARGS__) -#define vsuxseg3ei16_v_u16m1(...) __riscv_vsuxseg3ei16_v_u16m1(__VA_ARGS__) -#define vsuxseg4ei16_v_u16m1(...) __riscv_vsuxseg4ei16_v_u16m1(__VA_ARGS__) -#define vsuxseg5ei16_v_u16m1(...) __riscv_vsuxseg5ei16_v_u16m1(__VA_ARGS__) -#define vsuxseg6ei16_v_u16m1(...) __riscv_vsuxseg6ei16_v_u16m1(__VA_ARGS__) -#define vsuxseg7ei16_v_u16m1(...) __riscv_vsuxseg7ei16_v_u16m1(__VA_ARGS__) -#define vsuxseg8ei16_v_u16m1(...) __riscv_vsuxseg8ei16_v_u16m1(__VA_ARGS__) -#define vsuxseg2ei16_v_u16m2(...) __riscv_vsuxseg2ei16_v_u16m2(__VA_ARGS__) -#define vsuxseg3ei16_v_u16m2(...) __riscv_vsuxseg3ei16_v_u16m2(__VA_ARGS__) -#define vsuxseg4ei16_v_u16m2(...) __riscv_vsuxseg4ei16_v_u16m2(__VA_ARGS__) -#define vsuxseg2ei16_v_u16m4(...) __riscv_vsuxseg2ei16_v_u16m4(__VA_ARGS__) -#define vsuxseg2ei32_v_u16mf4(...) __riscv_vsuxseg2ei32_v_u16mf4(__VA_ARGS__) -#define vsuxseg3ei32_v_u16mf4(...) __riscv_vsuxseg3ei32_v_u16mf4(__VA_ARGS__) -#define vsuxseg4ei32_v_u16mf4(...) __riscv_vsuxseg4ei32_v_u16mf4(__VA_ARGS__) -#define vsuxseg5ei32_v_u16mf4(...) __riscv_vsuxseg5ei32_v_u16mf4(__VA_ARGS__) -#define vsuxseg6ei32_v_u16mf4(...) __riscv_vsuxseg6ei32_v_u16mf4(__VA_ARGS__) -#define vsuxseg7ei32_v_u16mf4(...) __riscv_vsuxseg7ei32_v_u16mf4(__VA_ARGS__) -#define vsuxseg8ei32_v_u16mf4(...) __riscv_vsuxseg8ei32_v_u16mf4(__VA_ARGS__) -#define vsuxseg2ei32_v_u16mf2(...) __riscv_vsuxseg2ei32_v_u16mf2(__VA_ARGS__) -#define vsuxseg3ei32_v_u16mf2(...) __riscv_vsuxseg3ei32_v_u16mf2(__VA_ARGS__) -#define vsuxseg4ei32_v_u16mf2(...) __riscv_vsuxseg4ei32_v_u16mf2(__VA_ARGS__) -#define vsuxseg5ei32_v_u16mf2(...) __riscv_vsuxseg5ei32_v_u16mf2(__VA_ARGS__) -#define vsuxseg6ei32_v_u16mf2(...) __riscv_vsuxseg6ei32_v_u16mf2(__VA_ARGS__) -#define vsuxseg7ei32_v_u16mf2(...) __riscv_vsuxseg7ei32_v_u16mf2(__VA_ARGS__) -#define vsuxseg8ei32_v_u16mf2(...) __riscv_vsuxseg8ei32_v_u16mf2(__VA_ARGS__) -#define vsuxseg2ei32_v_u16m1(...) __riscv_vsuxseg2ei32_v_u16m1(__VA_ARGS__) -#define vsuxseg3ei32_v_u16m1(...) __riscv_vsuxseg3ei32_v_u16m1(__VA_ARGS__) -#define vsuxseg4ei32_v_u16m1(...) __riscv_vsuxseg4ei32_v_u16m1(__VA_ARGS__) -#define vsuxseg5ei32_v_u16m1(...) __riscv_vsuxseg5ei32_v_u16m1(__VA_ARGS__) -#define vsuxseg6ei32_v_u16m1(...) __riscv_vsuxseg6ei32_v_u16m1(__VA_ARGS__) -#define vsuxseg7ei32_v_u16m1(...) __riscv_vsuxseg7ei32_v_u16m1(__VA_ARGS__) -#define vsuxseg8ei32_v_u16m1(...) __riscv_vsuxseg8ei32_v_u16m1(__VA_ARGS__) -#define vsuxseg2ei32_v_u16m2(...) __riscv_vsuxseg2ei32_v_u16m2(__VA_ARGS__) -#define vsuxseg3ei32_v_u16m2(...) __riscv_vsuxseg3ei32_v_u16m2(__VA_ARGS__) -#define vsuxseg4ei32_v_u16m2(...) __riscv_vsuxseg4ei32_v_u16m2(__VA_ARGS__) -#define vsuxseg2ei32_v_u16m4(...) __riscv_vsuxseg2ei32_v_u16m4(__VA_ARGS__) -#define vsuxseg2ei64_v_u16mf4(...) __riscv_vsuxseg2ei64_v_u16mf4(__VA_ARGS__) -#define vsuxseg3ei64_v_u16mf4(...) __riscv_vsuxseg3ei64_v_u16mf4(__VA_ARGS__) -#define vsuxseg4ei64_v_u16mf4(...) __riscv_vsuxseg4ei64_v_u16mf4(__VA_ARGS__) -#define vsuxseg5ei64_v_u16mf4(...) __riscv_vsuxseg5ei64_v_u16mf4(__VA_ARGS__) -#define vsuxseg6ei64_v_u16mf4(...) __riscv_vsuxseg6ei64_v_u16mf4(__VA_ARGS__) -#define vsuxseg7ei64_v_u16mf4(...) __riscv_vsuxseg7ei64_v_u16mf4(__VA_ARGS__) -#define vsuxseg8ei64_v_u16mf4(...) __riscv_vsuxseg8ei64_v_u16mf4(__VA_ARGS__) -#define vsuxseg2ei64_v_u16mf2(...) __riscv_vsuxseg2ei64_v_u16mf2(__VA_ARGS__) -#define vsuxseg3ei64_v_u16mf2(...) __riscv_vsuxseg3ei64_v_u16mf2(__VA_ARGS__) -#define vsuxseg4ei64_v_u16mf2(...) __riscv_vsuxseg4ei64_v_u16mf2(__VA_ARGS__) -#define vsuxseg5ei64_v_u16mf2(...) __riscv_vsuxseg5ei64_v_u16mf2(__VA_ARGS__) -#define vsuxseg6ei64_v_u16mf2(...) __riscv_vsuxseg6ei64_v_u16mf2(__VA_ARGS__) -#define vsuxseg7ei64_v_u16mf2(...) __riscv_vsuxseg7ei64_v_u16mf2(__VA_ARGS__) -#define vsuxseg8ei64_v_u16mf2(...) __riscv_vsuxseg8ei64_v_u16mf2(__VA_ARGS__) -#define vsuxseg2ei64_v_u16m1(...) __riscv_vsuxseg2ei64_v_u16m1(__VA_ARGS__) -#define vsuxseg3ei64_v_u16m1(...) __riscv_vsuxseg3ei64_v_u16m1(__VA_ARGS__) -#define vsuxseg4ei64_v_u16m1(...) __riscv_vsuxseg4ei64_v_u16m1(__VA_ARGS__) -#define vsuxseg5ei64_v_u16m1(...) __riscv_vsuxseg5ei64_v_u16m1(__VA_ARGS__) -#define vsuxseg6ei64_v_u16m1(...) __riscv_vsuxseg6ei64_v_u16m1(__VA_ARGS__) -#define vsuxseg7ei64_v_u16m1(...) __riscv_vsuxseg7ei64_v_u16m1(__VA_ARGS__) -#define vsuxseg8ei64_v_u16m1(...) __riscv_vsuxseg8ei64_v_u16m1(__VA_ARGS__) -#define vsuxseg2ei64_v_u16m2(...) __riscv_vsuxseg2ei64_v_u16m2(__VA_ARGS__) -#define vsuxseg3ei64_v_u16m2(...) __riscv_vsuxseg3ei64_v_u16m2(__VA_ARGS__) -#define vsuxseg4ei64_v_u16m2(...) __riscv_vsuxseg4ei64_v_u16m2(__VA_ARGS__) -#define vsuxseg2ei8_v_u32mf2(...) __riscv_vsuxseg2ei8_v_u32mf2(__VA_ARGS__) -#define vsuxseg3ei8_v_u32mf2(...) __riscv_vsuxseg3ei8_v_u32mf2(__VA_ARGS__) -#define vsuxseg4ei8_v_u32mf2(...) __riscv_vsuxseg4ei8_v_u32mf2(__VA_ARGS__) -#define vsuxseg5ei8_v_u32mf2(...) __riscv_vsuxseg5ei8_v_u32mf2(__VA_ARGS__) -#define vsuxseg6ei8_v_u32mf2(...) __riscv_vsuxseg6ei8_v_u32mf2(__VA_ARGS__) -#define vsuxseg7ei8_v_u32mf2(...) __riscv_vsuxseg7ei8_v_u32mf2(__VA_ARGS__) -#define vsuxseg8ei8_v_u32mf2(...) __riscv_vsuxseg8ei8_v_u32mf2(__VA_ARGS__) -#define vsuxseg2ei8_v_u32m1(...) __riscv_vsuxseg2ei8_v_u32m1(__VA_ARGS__) -#define vsuxseg3ei8_v_u32m1(...) __riscv_vsuxseg3ei8_v_u32m1(__VA_ARGS__) -#define vsuxseg4ei8_v_u32m1(...) __riscv_vsuxseg4ei8_v_u32m1(__VA_ARGS__) -#define vsuxseg5ei8_v_u32m1(...) __riscv_vsuxseg5ei8_v_u32m1(__VA_ARGS__) -#define vsuxseg6ei8_v_u32m1(...) __riscv_vsuxseg6ei8_v_u32m1(__VA_ARGS__) -#define vsuxseg7ei8_v_u32m1(...) __riscv_vsuxseg7ei8_v_u32m1(__VA_ARGS__) -#define vsuxseg8ei8_v_u32m1(...) __riscv_vsuxseg8ei8_v_u32m1(__VA_ARGS__) -#define vsuxseg2ei8_v_u32m2(...) __riscv_vsuxseg2ei8_v_u32m2(__VA_ARGS__) -#define vsuxseg3ei8_v_u32m2(...) __riscv_vsuxseg3ei8_v_u32m2(__VA_ARGS__) -#define vsuxseg4ei8_v_u32m2(...) __riscv_vsuxseg4ei8_v_u32m2(__VA_ARGS__) -#define vsuxseg2ei8_v_u32m4(...) __riscv_vsuxseg2ei8_v_u32m4(__VA_ARGS__) -#define vsuxseg2ei16_v_u32mf2(...) __riscv_vsuxseg2ei16_v_u32mf2(__VA_ARGS__) -#define vsuxseg3ei16_v_u32mf2(...) __riscv_vsuxseg3ei16_v_u32mf2(__VA_ARGS__) -#define vsuxseg4ei16_v_u32mf2(...) __riscv_vsuxseg4ei16_v_u32mf2(__VA_ARGS__) -#define vsuxseg5ei16_v_u32mf2(...) __riscv_vsuxseg5ei16_v_u32mf2(__VA_ARGS__) -#define vsuxseg6ei16_v_u32mf2(...) __riscv_vsuxseg6ei16_v_u32mf2(__VA_ARGS__) -#define vsuxseg7ei16_v_u32mf2(...) __riscv_vsuxseg7ei16_v_u32mf2(__VA_ARGS__) -#define vsuxseg8ei16_v_u32mf2(...) __riscv_vsuxseg8ei16_v_u32mf2(__VA_ARGS__) -#define vsuxseg2ei16_v_u32m1(...) __riscv_vsuxseg2ei16_v_u32m1(__VA_ARGS__) -#define vsuxseg3ei16_v_u32m1(...) __riscv_vsuxseg3ei16_v_u32m1(__VA_ARGS__) -#define vsuxseg4ei16_v_u32m1(...) __riscv_vsuxseg4ei16_v_u32m1(__VA_ARGS__) -#define vsuxseg5ei16_v_u32m1(...) __riscv_vsuxseg5ei16_v_u32m1(__VA_ARGS__) -#define vsuxseg6ei16_v_u32m1(...) __riscv_vsuxseg6ei16_v_u32m1(__VA_ARGS__) -#define vsuxseg7ei16_v_u32m1(...) __riscv_vsuxseg7ei16_v_u32m1(__VA_ARGS__) -#define vsuxseg8ei16_v_u32m1(...) __riscv_vsuxseg8ei16_v_u32m1(__VA_ARGS__) -#define vsuxseg2ei16_v_u32m2(...) __riscv_vsuxseg2ei16_v_u32m2(__VA_ARGS__) -#define vsuxseg3ei16_v_u32m2(...) __riscv_vsuxseg3ei16_v_u32m2(__VA_ARGS__) -#define vsuxseg4ei16_v_u32m2(...) __riscv_vsuxseg4ei16_v_u32m2(__VA_ARGS__) -#define vsuxseg2ei16_v_u32m4(...) __riscv_vsuxseg2ei16_v_u32m4(__VA_ARGS__) -#define vsuxseg2ei32_v_u32mf2(...) __riscv_vsuxseg2ei32_v_u32mf2(__VA_ARGS__) -#define vsuxseg3ei32_v_u32mf2(...) __riscv_vsuxseg3ei32_v_u32mf2(__VA_ARGS__) -#define vsuxseg4ei32_v_u32mf2(...) __riscv_vsuxseg4ei32_v_u32mf2(__VA_ARGS__) -#define vsuxseg5ei32_v_u32mf2(...) __riscv_vsuxseg5ei32_v_u32mf2(__VA_ARGS__) -#define vsuxseg6ei32_v_u32mf2(...) __riscv_vsuxseg6ei32_v_u32mf2(__VA_ARGS__) -#define vsuxseg7ei32_v_u32mf2(...) __riscv_vsuxseg7ei32_v_u32mf2(__VA_ARGS__) -#define vsuxseg8ei32_v_u32mf2(...) __riscv_vsuxseg8ei32_v_u32mf2(__VA_ARGS__) -#define vsuxseg2ei32_v_u32m1(...) __riscv_vsuxseg2ei32_v_u32m1(__VA_ARGS__) -#define vsuxseg3ei32_v_u32m1(...) __riscv_vsuxseg3ei32_v_u32m1(__VA_ARGS__) -#define vsuxseg4ei32_v_u32m1(...) __riscv_vsuxseg4ei32_v_u32m1(__VA_ARGS__) -#define vsuxseg5ei32_v_u32m1(...) __riscv_vsuxseg5ei32_v_u32m1(__VA_ARGS__) -#define vsuxseg6ei32_v_u32m1(...) __riscv_vsuxseg6ei32_v_u32m1(__VA_ARGS__) -#define vsuxseg7ei32_v_u32m1(...) __riscv_vsuxseg7ei32_v_u32m1(__VA_ARGS__) -#define vsuxseg8ei32_v_u32m1(...) __riscv_vsuxseg8ei32_v_u32m1(__VA_ARGS__) -#define vsuxseg2ei32_v_u32m2(...) __riscv_vsuxseg2ei32_v_u32m2(__VA_ARGS__) -#define vsuxseg3ei32_v_u32m2(...) __riscv_vsuxseg3ei32_v_u32m2(__VA_ARGS__) -#define vsuxseg4ei32_v_u32m2(...) __riscv_vsuxseg4ei32_v_u32m2(__VA_ARGS__) -#define vsuxseg2ei32_v_u32m4(...) __riscv_vsuxseg2ei32_v_u32m4(__VA_ARGS__) -#define vsuxseg2ei64_v_u32mf2(...) __riscv_vsuxseg2ei64_v_u32mf2(__VA_ARGS__) -#define vsuxseg3ei64_v_u32mf2(...) __riscv_vsuxseg3ei64_v_u32mf2(__VA_ARGS__) -#define vsuxseg4ei64_v_u32mf2(...) __riscv_vsuxseg4ei64_v_u32mf2(__VA_ARGS__) -#define vsuxseg5ei64_v_u32mf2(...) __riscv_vsuxseg5ei64_v_u32mf2(__VA_ARGS__) -#define vsuxseg6ei64_v_u32mf2(...) __riscv_vsuxseg6ei64_v_u32mf2(__VA_ARGS__) -#define vsuxseg7ei64_v_u32mf2(...) __riscv_vsuxseg7ei64_v_u32mf2(__VA_ARGS__) -#define vsuxseg8ei64_v_u32mf2(...) __riscv_vsuxseg8ei64_v_u32mf2(__VA_ARGS__) -#define vsuxseg2ei64_v_u32m1(...) __riscv_vsuxseg2ei64_v_u32m1(__VA_ARGS__) -#define vsuxseg3ei64_v_u32m1(...) __riscv_vsuxseg3ei64_v_u32m1(__VA_ARGS__) -#define vsuxseg4ei64_v_u32m1(...) __riscv_vsuxseg4ei64_v_u32m1(__VA_ARGS__) -#define vsuxseg5ei64_v_u32m1(...) __riscv_vsuxseg5ei64_v_u32m1(__VA_ARGS__) -#define vsuxseg6ei64_v_u32m1(...) __riscv_vsuxseg6ei64_v_u32m1(__VA_ARGS__) -#define vsuxseg7ei64_v_u32m1(...) __riscv_vsuxseg7ei64_v_u32m1(__VA_ARGS__) -#define vsuxseg8ei64_v_u32m1(...) __riscv_vsuxseg8ei64_v_u32m1(__VA_ARGS__) -#define vsuxseg2ei64_v_u32m2(...) __riscv_vsuxseg2ei64_v_u32m2(__VA_ARGS__) -#define vsuxseg3ei64_v_u32m2(...) __riscv_vsuxseg3ei64_v_u32m2(__VA_ARGS__) -#define vsuxseg4ei64_v_u32m2(...) __riscv_vsuxseg4ei64_v_u32m2(__VA_ARGS__) -#define vsuxseg2ei64_v_u32m4(...) __riscv_vsuxseg2ei64_v_u32m4(__VA_ARGS__) -#define vsuxseg2ei8_v_u64m1(...) __riscv_vsuxseg2ei8_v_u64m1(__VA_ARGS__) -#define vsuxseg3ei8_v_u64m1(...) __riscv_vsuxseg3ei8_v_u64m1(__VA_ARGS__) -#define vsuxseg4ei8_v_u64m1(...) __riscv_vsuxseg4ei8_v_u64m1(__VA_ARGS__) -#define vsuxseg5ei8_v_u64m1(...) __riscv_vsuxseg5ei8_v_u64m1(__VA_ARGS__) -#define vsuxseg6ei8_v_u64m1(...) __riscv_vsuxseg6ei8_v_u64m1(__VA_ARGS__) -#define vsuxseg7ei8_v_u64m1(...) __riscv_vsuxseg7ei8_v_u64m1(__VA_ARGS__) -#define vsuxseg8ei8_v_u64m1(...) __riscv_vsuxseg8ei8_v_u64m1(__VA_ARGS__) -#define vsuxseg2ei8_v_u64m2(...) __riscv_vsuxseg2ei8_v_u64m2(__VA_ARGS__) -#define vsuxseg3ei8_v_u64m2(...) __riscv_vsuxseg3ei8_v_u64m2(__VA_ARGS__) -#define vsuxseg4ei8_v_u64m2(...) __riscv_vsuxseg4ei8_v_u64m2(__VA_ARGS__) -#define vsuxseg2ei8_v_u64m4(...) __riscv_vsuxseg2ei8_v_u64m4(__VA_ARGS__) -#define vsuxseg2ei16_v_u64m1(...) __riscv_vsuxseg2ei16_v_u64m1(__VA_ARGS__) -#define vsuxseg3ei16_v_u64m1(...) __riscv_vsuxseg3ei16_v_u64m1(__VA_ARGS__) -#define vsuxseg4ei16_v_u64m1(...) __riscv_vsuxseg4ei16_v_u64m1(__VA_ARGS__) -#define vsuxseg5ei16_v_u64m1(...) __riscv_vsuxseg5ei16_v_u64m1(__VA_ARGS__) -#define vsuxseg6ei16_v_u64m1(...) __riscv_vsuxseg6ei16_v_u64m1(__VA_ARGS__) -#define vsuxseg7ei16_v_u64m1(...) __riscv_vsuxseg7ei16_v_u64m1(__VA_ARGS__) -#define vsuxseg8ei16_v_u64m1(...) __riscv_vsuxseg8ei16_v_u64m1(__VA_ARGS__) -#define vsuxseg2ei16_v_u64m2(...) __riscv_vsuxseg2ei16_v_u64m2(__VA_ARGS__) -#define vsuxseg3ei16_v_u64m2(...) __riscv_vsuxseg3ei16_v_u64m2(__VA_ARGS__) -#define vsuxseg4ei16_v_u64m2(...) __riscv_vsuxseg4ei16_v_u64m2(__VA_ARGS__) -#define vsuxseg2ei16_v_u64m4(...) __riscv_vsuxseg2ei16_v_u64m4(__VA_ARGS__) -#define vsuxseg2ei32_v_u64m1(...) __riscv_vsuxseg2ei32_v_u64m1(__VA_ARGS__) -#define vsuxseg3ei32_v_u64m1(...) __riscv_vsuxseg3ei32_v_u64m1(__VA_ARGS__) -#define vsuxseg4ei32_v_u64m1(...) __riscv_vsuxseg4ei32_v_u64m1(__VA_ARGS__) -#define vsuxseg5ei32_v_u64m1(...) __riscv_vsuxseg5ei32_v_u64m1(__VA_ARGS__) -#define vsuxseg6ei32_v_u64m1(...) __riscv_vsuxseg6ei32_v_u64m1(__VA_ARGS__) -#define vsuxseg7ei32_v_u64m1(...) __riscv_vsuxseg7ei32_v_u64m1(__VA_ARGS__) -#define vsuxseg8ei32_v_u64m1(...) __riscv_vsuxseg8ei32_v_u64m1(__VA_ARGS__) -#define vsuxseg2ei32_v_u64m2(...) __riscv_vsuxseg2ei32_v_u64m2(__VA_ARGS__) -#define vsuxseg3ei32_v_u64m2(...) __riscv_vsuxseg3ei32_v_u64m2(__VA_ARGS__) -#define vsuxseg4ei32_v_u64m2(...) __riscv_vsuxseg4ei32_v_u64m2(__VA_ARGS__) -#define vsuxseg2ei32_v_u64m4(...) __riscv_vsuxseg2ei32_v_u64m4(__VA_ARGS__) -#define vsuxseg2ei64_v_u64m1(...) __riscv_vsuxseg2ei64_v_u64m1(__VA_ARGS__) -#define vsuxseg3ei64_v_u64m1(...) __riscv_vsuxseg3ei64_v_u64m1(__VA_ARGS__) -#define vsuxseg4ei64_v_u64m1(...) __riscv_vsuxseg4ei64_v_u64m1(__VA_ARGS__) -#define vsuxseg5ei64_v_u64m1(...) __riscv_vsuxseg5ei64_v_u64m1(__VA_ARGS__) -#define vsuxseg6ei64_v_u64m1(...) __riscv_vsuxseg6ei64_v_u64m1(__VA_ARGS__) -#define vsuxseg7ei64_v_u64m1(...) __riscv_vsuxseg7ei64_v_u64m1(__VA_ARGS__) -#define vsuxseg8ei64_v_u64m1(...) __riscv_vsuxseg8ei64_v_u64m1(__VA_ARGS__) -#define vsuxseg2ei64_v_u64m2(...) __riscv_vsuxseg2ei64_v_u64m2(__VA_ARGS__) -#define vsuxseg3ei64_v_u64m2(...) __riscv_vsuxseg3ei64_v_u64m2(__VA_ARGS__) -#define vsuxseg4ei64_v_u64m2(...) __riscv_vsuxseg4ei64_v_u64m2(__VA_ARGS__) -#define vsuxseg2ei64_v_u64m4(...) __riscv_vsuxseg2ei64_v_u64m4(__VA_ARGS__) -// masked functions -#define vsoxseg2ei8_v_f16mf4_m(...) __riscv_vsoxseg2ei8_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg3ei8_v_f16mf4_m(...) __riscv_vsoxseg3ei8_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg4ei8_v_f16mf4_m(...) __riscv_vsoxseg4ei8_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg5ei8_v_f16mf4_m(...) __riscv_vsoxseg5ei8_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg6ei8_v_f16mf4_m(...) __riscv_vsoxseg6ei8_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg7ei8_v_f16mf4_m(...) __riscv_vsoxseg7ei8_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg8ei8_v_f16mf4_m(...) __riscv_vsoxseg8ei8_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg2ei8_v_f16mf2_m(...) __riscv_vsoxseg2ei8_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_f16mf2_m(...) __riscv_vsoxseg3ei8_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_f16mf2_m(...) __riscv_vsoxseg4ei8_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg5ei8_v_f16mf2_m(...) __riscv_vsoxseg5ei8_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg6ei8_v_f16mf2_m(...) __riscv_vsoxseg6ei8_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg7ei8_v_f16mf2_m(...) __riscv_vsoxseg7ei8_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg8ei8_v_f16mf2_m(...) __riscv_vsoxseg8ei8_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_f16m1_m(...) __riscv_vsoxseg2ei8_v_f16m1_m(__VA_ARGS__) -#define vsoxseg3ei8_v_f16m1_m(...) __riscv_vsoxseg3ei8_v_f16m1_m(__VA_ARGS__) -#define vsoxseg4ei8_v_f16m1_m(...) __riscv_vsoxseg4ei8_v_f16m1_m(__VA_ARGS__) -#define vsoxseg5ei8_v_f16m1_m(...) __riscv_vsoxseg5ei8_v_f16m1_m(__VA_ARGS__) -#define vsoxseg6ei8_v_f16m1_m(...) __riscv_vsoxseg6ei8_v_f16m1_m(__VA_ARGS__) -#define vsoxseg7ei8_v_f16m1_m(...) __riscv_vsoxseg7ei8_v_f16m1_m(__VA_ARGS__) -#define vsoxseg8ei8_v_f16m1_m(...) __riscv_vsoxseg8ei8_v_f16m1_m(__VA_ARGS__) -#define vsoxseg2ei8_v_f16m2_m(...) __riscv_vsoxseg2ei8_v_f16m2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_f16m2_m(...) __riscv_vsoxseg3ei8_v_f16m2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_f16m2_m(...) __riscv_vsoxseg4ei8_v_f16m2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_f16m4_m(...) __riscv_vsoxseg2ei8_v_f16m4_m(__VA_ARGS__) -#define vsoxseg2ei16_v_f16mf4_m(...) __riscv_vsoxseg2ei16_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg3ei16_v_f16mf4_m(...) __riscv_vsoxseg3ei16_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg4ei16_v_f16mf4_m(...) __riscv_vsoxseg4ei16_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg5ei16_v_f16mf4_m(...) __riscv_vsoxseg5ei16_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg6ei16_v_f16mf4_m(...) __riscv_vsoxseg6ei16_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg7ei16_v_f16mf4_m(...) __riscv_vsoxseg7ei16_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg8ei16_v_f16mf4_m(...) __riscv_vsoxseg8ei16_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg2ei16_v_f16mf2_m(...) __riscv_vsoxseg2ei16_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_f16mf2_m(...) __riscv_vsoxseg3ei16_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_f16mf2_m(...) __riscv_vsoxseg4ei16_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg5ei16_v_f16mf2_m(...) __riscv_vsoxseg5ei16_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg6ei16_v_f16mf2_m(...) __riscv_vsoxseg6ei16_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg7ei16_v_f16mf2_m(...) __riscv_vsoxseg7ei16_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg8ei16_v_f16mf2_m(...) __riscv_vsoxseg8ei16_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_f16m1_m(...) __riscv_vsoxseg2ei16_v_f16m1_m(__VA_ARGS__) -#define vsoxseg3ei16_v_f16m1_m(...) __riscv_vsoxseg3ei16_v_f16m1_m(__VA_ARGS__) -#define vsoxseg4ei16_v_f16m1_m(...) __riscv_vsoxseg4ei16_v_f16m1_m(__VA_ARGS__) -#define vsoxseg5ei16_v_f16m1_m(...) __riscv_vsoxseg5ei16_v_f16m1_m(__VA_ARGS__) -#define vsoxseg6ei16_v_f16m1_m(...) __riscv_vsoxseg6ei16_v_f16m1_m(__VA_ARGS__) -#define vsoxseg7ei16_v_f16m1_m(...) __riscv_vsoxseg7ei16_v_f16m1_m(__VA_ARGS__) -#define vsoxseg8ei16_v_f16m1_m(...) __riscv_vsoxseg8ei16_v_f16m1_m(__VA_ARGS__) -#define vsoxseg2ei16_v_f16m2_m(...) __riscv_vsoxseg2ei16_v_f16m2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_f16m2_m(...) __riscv_vsoxseg3ei16_v_f16m2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_f16m2_m(...) __riscv_vsoxseg4ei16_v_f16m2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_f16m4_m(...) __riscv_vsoxseg2ei16_v_f16m4_m(__VA_ARGS__) -#define vsoxseg2ei32_v_f16mf4_m(...) __riscv_vsoxseg2ei32_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg3ei32_v_f16mf4_m(...) __riscv_vsoxseg3ei32_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg4ei32_v_f16mf4_m(...) __riscv_vsoxseg4ei32_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg5ei32_v_f16mf4_m(...) __riscv_vsoxseg5ei32_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg6ei32_v_f16mf4_m(...) __riscv_vsoxseg6ei32_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg7ei32_v_f16mf4_m(...) __riscv_vsoxseg7ei32_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg8ei32_v_f16mf4_m(...) __riscv_vsoxseg8ei32_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg2ei32_v_f16mf2_m(...) __riscv_vsoxseg2ei32_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_f16mf2_m(...) __riscv_vsoxseg3ei32_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_f16mf2_m(...) __riscv_vsoxseg4ei32_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg5ei32_v_f16mf2_m(...) __riscv_vsoxseg5ei32_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg6ei32_v_f16mf2_m(...) __riscv_vsoxseg6ei32_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg7ei32_v_f16mf2_m(...) __riscv_vsoxseg7ei32_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg8ei32_v_f16mf2_m(...) __riscv_vsoxseg8ei32_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg2ei32_v_f16m1_m(...) __riscv_vsoxseg2ei32_v_f16m1_m(__VA_ARGS__) -#define vsoxseg3ei32_v_f16m1_m(...) __riscv_vsoxseg3ei32_v_f16m1_m(__VA_ARGS__) -#define vsoxseg4ei32_v_f16m1_m(...) __riscv_vsoxseg4ei32_v_f16m1_m(__VA_ARGS__) -#define vsoxseg5ei32_v_f16m1_m(...) __riscv_vsoxseg5ei32_v_f16m1_m(__VA_ARGS__) -#define vsoxseg6ei32_v_f16m1_m(...) __riscv_vsoxseg6ei32_v_f16m1_m(__VA_ARGS__) -#define vsoxseg7ei32_v_f16m1_m(...) __riscv_vsoxseg7ei32_v_f16m1_m(__VA_ARGS__) -#define vsoxseg8ei32_v_f16m1_m(...) __riscv_vsoxseg8ei32_v_f16m1_m(__VA_ARGS__) -#define vsoxseg2ei32_v_f16m2_m(...) __riscv_vsoxseg2ei32_v_f16m2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_f16m2_m(...) __riscv_vsoxseg3ei32_v_f16m2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_f16m2_m(...) __riscv_vsoxseg4ei32_v_f16m2_m(__VA_ARGS__) -#define vsoxseg2ei32_v_f16m4_m(...) __riscv_vsoxseg2ei32_v_f16m4_m(__VA_ARGS__) -#define vsoxseg2ei64_v_f16mf4_m(...) __riscv_vsoxseg2ei64_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg3ei64_v_f16mf4_m(...) __riscv_vsoxseg3ei64_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg4ei64_v_f16mf4_m(...) __riscv_vsoxseg4ei64_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg5ei64_v_f16mf4_m(...) __riscv_vsoxseg5ei64_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg6ei64_v_f16mf4_m(...) __riscv_vsoxseg6ei64_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg7ei64_v_f16mf4_m(...) __riscv_vsoxseg7ei64_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg8ei64_v_f16mf4_m(...) __riscv_vsoxseg8ei64_v_f16mf4_m(__VA_ARGS__) -#define vsoxseg2ei64_v_f16mf2_m(...) __riscv_vsoxseg2ei64_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg3ei64_v_f16mf2_m(...) __riscv_vsoxseg3ei64_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg4ei64_v_f16mf2_m(...) __riscv_vsoxseg4ei64_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg5ei64_v_f16mf2_m(...) __riscv_vsoxseg5ei64_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg6ei64_v_f16mf2_m(...) __riscv_vsoxseg6ei64_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg7ei64_v_f16mf2_m(...) __riscv_vsoxseg7ei64_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg8ei64_v_f16mf2_m(...) __riscv_vsoxseg8ei64_v_f16mf2_m(__VA_ARGS__) -#define vsoxseg2ei64_v_f16m1_m(...) __riscv_vsoxseg2ei64_v_f16m1_m(__VA_ARGS__) -#define vsoxseg3ei64_v_f16m1_m(...) __riscv_vsoxseg3ei64_v_f16m1_m(__VA_ARGS__) -#define vsoxseg4ei64_v_f16m1_m(...) __riscv_vsoxseg4ei64_v_f16m1_m(__VA_ARGS__) -#define vsoxseg5ei64_v_f16m1_m(...) __riscv_vsoxseg5ei64_v_f16m1_m(__VA_ARGS__) -#define vsoxseg6ei64_v_f16m1_m(...) __riscv_vsoxseg6ei64_v_f16m1_m(__VA_ARGS__) -#define vsoxseg7ei64_v_f16m1_m(...) __riscv_vsoxseg7ei64_v_f16m1_m(__VA_ARGS__) -#define vsoxseg8ei64_v_f16m1_m(...) __riscv_vsoxseg8ei64_v_f16m1_m(__VA_ARGS__) -#define vsoxseg2ei64_v_f16m2_m(...) __riscv_vsoxseg2ei64_v_f16m2_m(__VA_ARGS__) -#define vsoxseg3ei64_v_f16m2_m(...) __riscv_vsoxseg3ei64_v_f16m2_m(__VA_ARGS__) -#define vsoxseg4ei64_v_f16m2_m(...) __riscv_vsoxseg4ei64_v_f16m2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_f32mf2_m(...) __riscv_vsoxseg2ei8_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_f32mf2_m(...) __riscv_vsoxseg3ei8_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_f32mf2_m(...) __riscv_vsoxseg4ei8_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg5ei8_v_f32mf2_m(...) __riscv_vsoxseg5ei8_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg6ei8_v_f32mf2_m(...) __riscv_vsoxseg6ei8_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg7ei8_v_f32mf2_m(...) __riscv_vsoxseg7ei8_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg8ei8_v_f32mf2_m(...) __riscv_vsoxseg8ei8_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_f32m1_m(...) __riscv_vsoxseg2ei8_v_f32m1_m(__VA_ARGS__) -#define vsoxseg3ei8_v_f32m1_m(...) __riscv_vsoxseg3ei8_v_f32m1_m(__VA_ARGS__) -#define vsoxseg4ei8_v_f32m1_m(...) __riscv_vsoxseg4ei8_v_f32m1_m(__VA_ARGS__) -#define vsoxseg5ei8_v_f32m1_m(...) __riscv_vsoxseg5ei8_v_f32m1_m(__VA_ARGS__) -#define vsoxseg6ei8_v_f32m1_m(...) __riscv_vsoxseg6ei8_v_f32m1_m(__VA_ARGS__) -#define vsoxseg7ei8_v_f32m1_m(...) __riscv_vsoxseg7ei8_v_f32m1_m(__VA_ARGS__) -#define vsoxseg8ei8_v_f32m1_m(...) __riscv_vsoxseg8ei8_v_f32m1_m(__VA_ARGS__) -#define vsoxseg2ei8_v_f32m2_m(...) __riscv_vsoxseg2ei8_v_f32m2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_f32m2_m(...) __riscv_vsoxseg3ei8_v_f32m2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_f32m2_m(...) __riscv_vsoxseg4ei8_v_f32m2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_f32m4_m(...) __riscv_vsoxseg2ei8_v_f32m4_m(__VA_ARGS__) -#define vsoxseg2ei16_v_f32mf2_m(...) __riscv_vsoxseg2ei16_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_f32mf2_m(...) __riscv_vsoxseg3ei16_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_f32mf2_m(...) __riscv_vsoxseg4ei16_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg5ei16_v_f32mf2_m(...) __riscv_vsoxseg5ei16_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg6ei16_v_f32mf2_m(...) __riscv_vsoxseg6ei16_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg7ei16_v_f32mf2_m(...) __riscv_vsoxseg7ei16_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg8ei16_v_f32mf2_m(...) __riscv_vsoxseg8ei16_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_f32m1_m(...) __riscv_vsoxseg2ei16_v_f32m1_m(__VA_ARGS__) -#define vsoxseg3ei16_v_f32m1_m(...) __riscv_vsoxseg3ei16_v_f32m1_m(__VA_ARGS__) -#define vsoxseg4ei16_v_f32m1_m(...) __riscv_vsoxseg4ei16_v_f32m1_m(__VA_ARGS__) -#define vsoxseg5ei16_v_f32m1_m(...) __riscv_vsoxseg5ei16_v_f32m1_m(__VA_ARGS__) -#define vsoxseg6ei16_v_f32m1_m(...) __riscv_vsoxseg6ei16_v_f32m1_m(__VA_ARGS__) -#define vsoxseg7ei16_v_f32m1_m(...) __riscv_vsoxseg7ei16_v_f32m1_m(__VA_ARGS__) -#define vsoxseg8ei16_v_f32m1_m(...) __riscv_vsoxseg8ei16_v_f32m1_m(__VA_ARGS__) -#define vsoxseg2ei16_v_f32m2_m(...) __riscv_vsoxseg2ei16_v_f32m2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_f32m2_m(...) __riscv_vsoxseg3ei16_v_f32m2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_f32m2_m(...) __riscv_vsoxseg4ei16_v_f32m2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_f32m4_m(...) __riscv_vsoxseg2ei16_v_f32m4_m(__VA_ARGS__) -#define vsoxseg2ei32_v_f32mf2_m(...) __riscv_vsoxseg2ei32_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_f32mf2_m(...) __riscv_vsoxseg3ei32_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_f32mf2_m(...) __riscv_vsoxseg4ei32_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg5ei32_v_f32mf2_m(...) __riscv_vsoxseg5ei32_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg6ei32_v_f32mf2_m(...) __riscv_vsoxseg6ei32_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg7ei32_v_f32mf2_m(...) __riscv_vsoxseg7ei32_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg8ei32_v_f32mf2_m(...) __riscv_vsoxseg8ei32_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg2ei32_v_f32m1_m(...) __riscv_vsoxseg2ei32_v_f32m1_m(__VA_ARGS__) -#define vsoxseg3ei32_v_f32m1_m(...) __riscv_vsoxseg3ei32_v_f32m1_m(__VA_ARGS__) -#define vsoxseg4ei32_v_f32m1_m(...) __riscv_vsoxseg4ei32_v_f32m1_m(__VA_ARGS__) -#define vsoxseg5ei32_v_f32m1_m(...) __riscv_vsoxseg5ei32_v_f32m1_m(__VA_ARGS__) -#define vsoxseg6ei32_v_f32m1_m(...) __riscv_vsoxseg6ei32_v_f32m1_m(__VA_ARGS__) -#define vsoxseg7ei32_v_f32m1_m(...) __riscv_vsoxseg7ei32_v_f32m1_m(__VA_ARGS__) -#define vsoxseg8ei32_v_f32m1_m(...) __riscv_vsoxseg8ei32_v_f32m1_m(__VA_ARGS__) -#define vsoxseg2ei32_v_f32m2_m(...) __riscv_vsoxseg2ei32_v_f32m2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_f32m2_m(...) __riscv_vsoxseg3ei32_v_f32m2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_f32m2_m(...) __riscv_vsoxseg4ei32_v_f32m2_m(__VA_ARGS__) -#define vsoxseg2ei32_v_f32m4_m(...) __riscv_vsoxseg2ei32_v_f32m4_m(__VA_ARGS__) -#define vsoxseg2ei64_v_f32mf2_m(...) __riscv_vsoxseg2ei64_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg3ei64_v_f32mf2_m(...) __riscv_vsoxseg3ei64_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg4ei64_v_f32mf2_m(...) __riscv_vsoxseg4ei64_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg5ei64_v_f32mf2_m(...) __riscv_vsoxseg5ei64_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg6ei64_v_f32mf2_m(...) __riscv_vsoxseg6ei64_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg7ei64_v_f32mf2_m(...) __riscv_vsoxseg7ei64_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg8ei64_v_f32mf2_m(...) __riscv_vsoxseg8ei64_v_f32mf2_m(__VA_ARGS__) -#define vsoxseg2ei64_v_f32m1_m(...) __riscv_vsoxseg2ei64_v_f32m1_m(__VA_ARGS__) -#define vsoxseg3ei64_v_f32m1_m(...) __riscv_vsoxseg3ei64_v_f32m1_m(__VA_ARGS__) -#define vsoxseg4ei64_v_f32m1_m(...) __riscv_vsoxseg4ei64_v_f32m1_m(__VA_ARGS__) -#define vsoxseg5ei64_v_f32m1_m(...) __riscv_vsoxseg5ei64_v_f32m1_m(__VA_ARGS__) -#define vsoxseg6ei64_v_f32m1_m(...) __riscv_vsoxseg6ei64_v_f32m1_m(__VA_ARGS__) -#define vsoxseg7ei64_v_f32m1_m(...) __riscv_vsoxseg7ei64_v_f32m1_m(__VA_ARGS__) -#define vsoxseg8ei64_v_f32m1_m(...) __riscv_vsoxseg8ei64_v_f32m1_m(__VA_ARGS__) -#define vsoxseg2ei64_v_f32m2_m(...) __riscv_vsoxseg2ei64_v_f32m2_m(__VA_ARGS__) -#define vsoxseg3ei64_v_f32m2_m(...) __riscv_vsoxseg3ei64_v_f32m2_m(__VA_ARGS__) -#define vsoxseg4ei64_v_f32m2_m(...) __riscv_vsoxseg4ei64_v_f32m2_m(__VA_ARGS__) -#define vsoxseg2ei64_v_f32m4_m(...) __riscv_vsoxseg2ei64_v_f32m4_m(__VA_ARGS__) -#define vsoxseg2ei8_v_f64m1_m(...) __riscv_vsoxseg2ei8_v_f64m1_m(__VA_ARGS__) -#define vsoxseg3ei8_v_f64m1_m(...) __riscv_vsoxseg3ei8_v_f64m1_m(__VA_ARGS__) -#define vsoxseg4ei8_v_f64m1_m(...) __riscv_vsoxseg4ei8_v_f64m1_m(__VA_ARGS__) -#define vsoxseg5ei8_v_f64m1_m(...) __riscv_vsoxseg5ei8_v_f64m1_m(__VA_ARGS__) -#define vsoxseg6ei8_v_f64m1_m(...) __riscv_vsoxseg6ei8_v_f64m1_m(__VA_ARGS__) -#define vsoxseg7ei8_v_f64m1_m(...) __riscv_vsoxseg7ei8_v_f64m1_m(__VA_ARGS__) -#define vsoxseg8ei8_v_f64m1_m(...) __riscv_vsoxseg8ei8_v_f64m1_m(__VA_ARGS__) -#define vsoxseg2ei8_v_f64m2_m(...) __riscv_vsoxseg2ei8_v_f64m2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_f64m2_m(...) __riscv_vsoxseg3ei8_v_f64m2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_f64m2_m(...) __riscv_vsoxseg4ei8_v_f64m2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_f64m4_m(...) __riscv_vsoxseg2ei8_v_f64m4_m(__VA_ARGS__) -#define vsoxseg2ei16_v_f64m1_m(...) __riscv_vsoxseg2ei16_v_f64m1_m(__VA_ARGS__) -#define vsoxseg3ei16_v_f64m1_m(...) __riscv_vsoxseg3ei16_v_f64m1_m(__VA_ARGS__) -#define vsoxseg4ei16_v_f64m1_m(...) __riscv_vsoxseg4ei16_v_f64m1_m(__VA_ARGS__) -#define vsoxseg5ei16_v_f64m1_m(...) __riscv_vsoxseg5ei16_v_f64m1_m(__VA_ARGS__) -#define vsoxseg6ei16_v_f64m1_m(...) __riscv_vsoxseg6ei16_v_f64m1_m(__VA_ARGS__) -#define vsoxseg7ei16_v_f64m1_m(...) __riscv_vsoxseg7ei16_v_f64m1_m(__VA_ARGS__) -#define vsoxseg8ei16_v_f64m1_m(...) __riscv_vsoxseg8ei16_v_f64m1_m(__VA_ARGS__) -#define vsoxseg2ei16_v_f64m2_m(...) __riscv_vsoxseg2ei16_v_f64m2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_f64m2_m(...) __riscv_vsoxseg3ei16_v_f64m2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_f64m2_m(...) __riscv_vsoxseg4ei16_v_f64m2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_f64m4_m(...) __riscv_vsoxseg2ei16_v_f64m4_m(__VA_ARGS__) -#define vsoxseg2ei32_v_f64m1_m(...) __riscv_vsoxseg2ei32_v_f64m1_m(__VA_ARGS__) -#define vsoxseg3ei32_v_f64m1_m(...) __riscv_vsoxseg3ei32_v_f64m1_m(__VA_ARGS__) -#define vsoxseg4ei32_v_f64m1_m(...) __riscv_vsoxseg4ei32_v_f64m1_m(__VA_ARGS__) -#define vsoxseg5ei32_v_f64m1_m(...) __riscv_vsoxseg5ei32_v_f64m1_m(__VA_ARGS__) -#define vsoxseg6ei32_v_f64m1_m(...) __riscv_vsoxseg6ei32_v_f64m1_m(__VA_ARGS__) -#define vsoxseg7ei32_v_f64m1_m(...) __riscv_vsoxseg7ei32_v_f64m1_m(__VA_ARGS__) -#define vsoxseg8ei32_v_f64m1_m(...) __riscv_vsoxseg8ei32_v_f64m1_m(__VA_ARGS__) -#define vsoxseg2ei32_v_f64m2_m(...) __riscv_vsoxseg2ei32_v_f64m2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_f64m2_m(...) __riscv_vsoxseg3ei32_v_f64m2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_f64m2_m(...) __riscv_vsoxseg4ei32_v_f64m2_m(__VA_ARGS__) -#define vsoxseg2ei32_v_f64m4_m(...) __riscv_vsoxseg2ei32_v_f64m4_m(__VA_ARGS__) -#define vsoxseg2ei64_v_f64m1_m(...) __riscv_vsoxseg2ei64_v_f64m1_m(__VA_ARGS__) -#define vsoxseg3ei64_v_f64m1_m(...) __riscv_vsoxseg3ei64_v_f64m1_m(__VA_ARGS__) -#define vsoxseg4ei64_v_f64m1_m(...) __riscv_vsoxseg4ei64_v_f64m1_m(__VA_ARGS__) -#define vsoxseg5ei64_v_f64m1_m(...) __riscv_vsoxseg5ei64_v_f64m1_m(__VA_ARGS__) -#define vsoxseg6ei64_v_f64m1_m(...) __riscv_vsoxseg6ei64_v_f64m1_m(__VA_ARGS__) -#define vsoxseg7ei64_v_f64m1_m(...) __riscv_vsoxseg7ei64_v_f64m1_m(__VA_ARGS__) -#define vsoxseg8ei64_v_f64m1_m(...) __riscv_vsoxseg8ei64_v_f64m1_m(__VA_ARGS__) -#define vsoxseg2ei64_v_f64m2_m(...) __riscv_vsoxseg2ei64_v_f64m2_m(__VA_ARGS__) -#define vsoxseg3ei64_v_f64m2_m(...) __riscv_vsoxseg3ei64_v_f64m2_m(__VA_ARGS__) -#define vsoxseg4ei64_v_f64m2_m(...) __riscv_vsoxseg4ei64_v_f64m2_m(__VA_ARGS__) -#define vsoxseg2ei64_v_f64m4_m(...) __riscv_vsoxseg2ei64_v_f64m4_m(__VA_ARGS__) -#define vsuxseg2ei8_v_f16mf4_m(...) __riscv_vsuxseg2ei8_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg3ei8_v_f16mf4_m(...) __riscv_vsuxseg3ei8_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg4ei8_v_f16mf4_m(...) __riscv_vsuxseg4ei8_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg5ei8_v_f16mf4_m(...) __riscv_vsuxseg5ei8_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg6ei8_v_f16mf4_m(...) __riscv_vsuxseg6ei8_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg7ei8_v_f16mf4_m(...) __riscv_vsuxseg7ei8_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg8ei8_v_f16mf4_m(...) __riscv_vsuxseg8ei8_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg2ei8_v_f16mf2_m(...) __riscv_vsuxseg2ei8_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_f16mf2_m(...) __riscv_vsuxseg3ei8_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_f16mf2_m(...) __riscv_vsuxseg4ei8_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg5ei8_v_f16mf2_m(...) __riscv_vsuxseg5ei8_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg6ei8_v_f16mf2_m(...) __riscv_vsuxseg6ei8_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg7ei8_v_f16mf2_m(...) __riscv_vsuxseg7ei8_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg8ei8_v_f16mf2_m(...) __riscv_vsuxseg8ei8_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_f16m1_m(...) __riscv_vsuxseg2ei8_v_f16m1_m(__VA_ARGS__) -#define vsuxseg3ei8_v_f16m1_m(...) __riscv_vsuxseg3ei8_v_f16m1_m(__VA_ARGS__) -#define vsuxseg4ei8_v_f16m1_m(...) __riscv_vsuxseg4ei8_v_f16m1_m(__VA_ARGS__) -#define vsuxseg5ei8_v_f16m1_m(...) __riscv_vsuxseg5ei8_v_f16m1_m(__VA_ARGS__) -#define vsuxseg6ei8_v_f16m1_m(...) __riscv_vsuxseg6ei8_v_f16m1_m(__VA_ARGS__) -#define vsuxseg7ei8_v_f16m1_m(...) __riscv_vsuxseg7ei8_v_f16m1_m(__VA_ARGS__) -#define vsuxseg8ei8_v_f16m1_m(...) __riscv_vsuxseg8ei8_v_f16m1_m(__VA_ARGS__) -#define vsuxseg2ei8_v_f16m2_m(...) __riscv_vsuxseg2ei8_v_f16m2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_f16m2_m(...) __riscv_vsuxseg3ei8_v_f16m2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_f16m2_m(...) __riscv_vsuxseg4ei8_v_f16m2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_f16m4_m(...) __riscv_vsuxseg2ei8_v_f16m4_m(__VA_ARGS__) -#define vsuxseg2ei16_v_f16mf4_m(...) __riscv_vsuxseg2ei16_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg3ei16_v_f16mf4_m(...) __riscv_vsuxseg3ei16_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg4ei16_v_f16mf4_m(...) __riscv_vsuxseg4ei16_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg5ei16_v_f16mf4_m(...) __riscv_vsuxseg5ei16_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg6ei16_v_f16mf4_m(...) __riscv_vsuxseg6ei16_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg7ei16_v_f16mf4_m(...) __riscv_vsuxseg7ei16_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg8ei16_v_f16mf4_m(...) __riscv_vsuxseg8ei16_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg2ei16_v_f16mf2_m(...) __riscv_vsuxseg2ei16_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_f16mf2_m(...) __riscv_vsuxseg3ei16_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_f16mf2_m(...) __riscv_vsuxseg4ei16_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg5ei16_v_f16mf2_m(...) __riscv_vsuxseg5ei16_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg6ei16_v_f16mf2_m(...) __riscv_vsuxseg6ei16_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg7ei16_v_f16mf2_m(...) __riscv_vsuxseg7ei16_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg8ei16_v_f16mf2_m(...) __riscv_vsuxseg8ei16_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_f16m1_m(...) __riscv_vsuxseg2ei16_v_f16m1_m(__VA_ARGS__) -#define vsuxseg3ei16_v_f16m1_m(...) __riscv_vsuxseg3ei16_v_f16m1_m(__VA_ARGS__) -#define vsuxseg4ei16_v_f16m1_m(...) __riscv_vsuxseg4ei16_v_f16m1_m(__VA_ARGS__) -#define vsuxseg5ei16_v_f16m1_m(...) __riscv_vsuxseg5ei16_v_f16m1_m(__VA_ARGS__) -#define vsuxseg6ei16_v_f16m1_m(...) __riscv_vsuxseg6ei16_v_f16m1_m(__VA_ARGS__) -#define vsuxseg7ei16_v_f16m1_m(...) __riscv_vsuxseg7ei16_v_f16m1_m(__VA_ARGS__) -#define vsuxseg8ei16_v_f16m1_m(...) __riscv_vsuxseg8ei16_v_f16m1_m(__VA_ARGS__) -#define vsuxseg2ei16_v_f16m2_m(...) __riscv_vsuxseg2ei16_v_f16m2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_f16m2_m(...) __riscv_vsuxseg3ei16_v_f16m2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_f16m2_m(...) __riscv_vsuxseg4ei16_v_f16m2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_f16m4_m(...) __riscv_vsuxseg2ei16_v_f16m4_m(__VA_ARGS__) -#define vsuxseg2ei32_v_f16mf4_m(...) __riscv_vsuxseg2ei32_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg3ei32_v_f16mf4_m(...) __riscv_vsuxseg3ei32_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg4ei32_v_f16mf4_m(...) __riscv_vsuxseg4ei32_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg5ei32_v_f16mf4_m(...) __riscv_vsuxseg5ei32_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg6ei32_v_f16mf4_m(...) __riscv_vsuxseg6ei32_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg7ei32_v_f16mf4_m(...) __riscv_vsuxseg7ei32_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg8ei32_v_f16mf4_m(...) __riscv_vsuxseg8ei32_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg2ei32_v_f16mf2_m(...) __riscv_vsuxseg2ei32_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_f16mf2_m(...) __riscv_vsuxseg3ei32_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_f16mf2_m(...) __riscv_vsuxseg4ei32_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg5ei32_v_f16mf2_m(...) __riscv_vsuxseg5ei32_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg6ei32_v_f16mf2_m(...) __riscv_vsuxseg6ei32_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg7ei32_v_f16mf2_m(...) __riscv_vsuxseg7ei32_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg8ei32_v_f16mf2_m(...) __riscv_vsuxseg8ei32_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg2ei32_v_f16m1_m(...) __riscv_vsuxseg2ei32_v_f16m1_m(__VA_ARGS__) -#define vsuxseg3ei32_v_f16m1_m(...) __riscv_vsuxseg3ei32_v_f16m1_m(__VA_ARGS__) -#define vsuxseg4ei32_v_f16m1_m(...) __riscv_vsuxseg4ei32_v_f16m1_m(__VA_ARGS__) -#define vsuxseg5ei32_v_f16m1_m(...) __riscv_vsuxseg5ei32_v_f16m1_m(__VA_ARGS__) -#define vsuxseg6ei32_v_f16m1_m(...) __riscv_vsuxseg6ei32_v_f16m1_m(__VA_ARGS__) -#define vsuxseg7ei32_v_f16m1_m(...) __riscv_vsuxseg7ei32_v_f16m1_m(__VA_ARGS__) -#define vsuxseg8ei32_v_f16m1_m(...) __riscv_vsuxseg8ei32_v_f16m1_m(__VA_ARGS__) -#define vsuxseg2ei32_v_f16m2_m(...) __riscv_vsuxseg2ei32_v_f16m2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_f16m2_m(...) __riscv_vsuxseg3ei32_v_f16m2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_f16m2_m(...) __riscv_vsuxseg4ei32_v_f16m2_m(__VA_ARGS__) -#define vsuxseg2ei32_v_f16m4_m(...) __riscv_vsuxseg2ei32_v_f16m4_m(__VA_ARGS__) -#define vsuxseg2ei64_v_f16mf4_m(...) __riscv_vsuxseg2ei64_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg3ei64_v_f16mf4_m(...) __riscv_vsuxseg3ei64_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg4ei64_v_f16mf4_m(...) __riscv_vsuxseg4ei64_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg5ei64_v_f16mf4_m(...) __riscv_vsuxseg5ei64_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg6ei64_v_f16mf4_m(...) __riscv_vsuxseg6ei64_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg7ei64_v_f16mf4_m(...) __riscv_vsuxseg7ei64_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg8ei64_v_f16mf4_m(...) __riscv_vsuxseg8ei64_v_f16mf4_m(__VA_ARGS__) -#define vsuxseg2ei64_v_f16mf2_m(...) __riscv_vsuxseg2ei64_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg3ei64_v_f16mf2_m(...) __riscv_vsuxseg3ei64_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg4ei64_v_f16mf2_m(...) __riscv_vsuxseg4ei64_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg5ei64_v_f16mf2_m(...) __riscv_vsuxseg5ei64_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg6ei64_v_f16mf2_m(...) __riscv_vsuxseg6ei64_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg7ei64_v_f16mf2_m(...) __riscv_vsuxseg7ei64_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg8ei64_v_f16mf2_m(...) __riscv_vsuxseg8ei64_v_f16mf2_m(__VA_ARGS__) -#define vsuxseg2ei64_v_f16m1_m(...) __riscv_vsuxseg2ei64_v_f16m1_m(__VA_ARGS__) -#define vsuxseg3ei64_v_f16m1_m(...) __riscv_vsuxseg3ei64_v_f16m1_m(__VA_ARGS__) -#define vsuxseg4ei64_v_f16m1_m(...) __riscv_vsuxseg4ei64_v_f16m1_m(__VA_ARGS__) -#define vsuxseg5ei64_v_f16m1_m(...) __riscv_vsuxseg5ei64_v_f16m1_m(__VA_ARGS__) -#define vsuxseg6ei64_v_f16m1_m(...) __riscv_vsuxseg6ei64_v_f16m1_m(__VA_ARGS__) -#define vsuxseg7ei64_v_f16m1_m(...) __riscv_vsuxseg7ei64_v_f16m1_m(__VA_ARGS__) -#define vsuxseg8ei64_v_f16m1_m(...) __riscv_vsuxseg8ei64_v_f16m1_m(__VA_ARGS__) -#define vsuxseg2ei64_v_f16m2_m(...) __riscv_vsuxseg2ei64_v_f16m2_m(__VA_ARGS__) -#define vsuxseg3ei64_v_f16m2_m(...) __riscv_vsuxseg3ei64_v_f16m2_m(__VA_ARGS__) -#define vsuxseg4ei64_v_f16m2_m(...) __riscv_vsuxseg4ei64_v_f16m2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_f32mf2_m(...) __riscv_vsuxseg2ei8_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_f32mf2_m(...) __riscv_vsuxseg3ei8_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_f32mf2_m(...) __riscv_vsuxseg4ei8_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg5ei8_v_f32mf2_m(...) __riscv_vsuxseg5ei8_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg6ei8_v_f32mf2_m(...) __riscv_vsuxseg6ei8_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg7ei8_v_f32mf2_m(...) __riscv_vsuxseg7ei8_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg8ei8_v_f32mf2_m(...) __riscv_vsuxseg8ei8_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_f32m1_m(...) __riscv_vsuxseg2ei8_v_f32m1_m(__VA_ARGS__) -#define vsuxseg3ei8_v_f32m1_m(...) __riscv_vsuxseg3ei8_v_f32m1_m(__VA_ARGS__) -#define vsuxseg4ei8_v_f32m1_m(...) __riscv_vsuxseg4ei8_v_f32m1_m(__VA_ARGS__) -#define vsuxseg5ei8_v_f32m1_m(...) __riscv_vsuxseg5ei8_v_f32m1_m(__VA_ARGS__) -#define vsuxseg6ei8_v_f32m1_m(...) __riscv_vsuxseg6ei8_v_f32m1_m(__VA_ARGS__) -#define vsuxseg7ei8_v_f32m1_m(...) __riscv_vsuxseg7ei8_v_f32m1_m(__VA_ARGS__) -#define vsuxseg8ei8_v_f32m1_m(...) __riscv_vsuxseg8ei8_v_f32m1_m(__VA_ARGS__) -#define vsuxseg2ei8_v_f32m2_m(...) __riscv_vsuxseg2ei8_v_f32m2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_f32m2_m(...) __riscv_vsuxseg3ei8_v_f32m2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_f32m2_m(...) __riscv_vsuxseg4ei8_v_f32m2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_f32m4_m(...) __riscv_vsuxseg2ei8_v_f32m4_m(__VA_ARGS__) -#define vsuxseg2ei16_v_f32mf2_m(...) __riscv_vsuxseg2ei16_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_f32mf2_m(...) __riscv_vsuxseg3ei16_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_f32mf2_m(...) __riscv_vsuxseg4ei16_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg5ei16_v_f32mf2_m(...) __riscv_vsuxseg5ei16_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg6ei16_v_f32mf2_m(...) __riscv_vsuxseg6ei16_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg7ei16_v_f32mf2_m(...) __riscv_vsuxseg7ei16_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg8ei16_v_f32mf2_m(...) __riscv_vsuxseg8ei16_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_f32m1_m(...) __riscv_vsuxseg2ei16_v_f32m1_m(__VA_ARGS__) -#define vsuxseg3ei16_v_f32m1_m(...) __riscv_vsuxseg3ei16_v_f32m1_m(__VA_ARGS__) -#define vsuxseg4ei16_v_f32m1_m(...) __riscv_vsuxseg4ei16_v_f32m1_m(__VA_ARGS__) -#define vsuxseg5ei16_v_f32m1_m(...) __riscv_vsuxseg5ei16_v_f32m1_m(__VA_ARGS__) -#define vsuxseg6ei16_v_f32m1_m(...) __riscv_vsuxseg6ei16_v_f32m1_m(__VA_ARGS__) -#define vsuxseg7ei16_v_f32m1_m(...) __riscv_vsuxseg7ei16_v_f32m1_m(__VA_ARGS__) -#define vsuxseg8ei16_v_f32m1_m(...) __riscv_vsuxseg8ei16_v_f32m1_m(__VA_ARGS__) -#define vsuxseg2ei16_v_f32m2_m(...) __riscv_vsuxseg2ei16_v_f32m2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_f32m2_m(...) __riscv_vsuxseg3ei16_v_f32m2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_f32m2_m(...) __riscv_vsuxseg4ei16_v_f32m2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_f32m4_m(...) __riscv_vsuxseg2ei16_v_f32m4_m(__VA_ARGS__) -#define vsuxseg2ei32_v_f32mf2_m(...) __riscv_vsuxseg2ei32_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_f32mf2_m(...) __riscv_vsuxseg3ei32_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_f32mf2_m(...) __riscv_vsuxseg4ei32_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg5ei32_v_f32mf2_m(...) __riscv_vsuxseg5ei32_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg6ei32_v_f32mf2_m(...) __riscv_vsuxseg6ei32_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg7ei32_v_f32mf2_m(...) __riscv_vsuxseg7ei32_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg8ei32_v_f32mf2_m(...) __riscv_vsuxseg8ei32_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg2ei32_v_f32m1_m(...) __riscv_vsuxseg2ei32_v_f32m1_m(__VA_ARGS__) -#define vsuxseg3ei32_v_f32m1_m(...) __riscv_vsuxseg3ei32_v_f32m1_m(__VA_ARGS__) -#define vsuxseg4ei32_v_f32m1_m(...) __riscv_vsuxseg4ei32_v_f32m1_m(__VA_ARGS__) -#define vsuxseg5ei32_v_f32m1_m(...) __riscv_vsuxseg5ei32_v_f32m1_m(__VA_ARGS__) -#define vsuxseg6ei32_v_f32m1_m(...) __riscv_vsuxseg6ei32_v_f32m1_m(__VA_ARGS__) -#define vsuxseg7ei32_v_f32m1_m(...) __riscv_vsuxseg7ei32_v_f32m1_m(__VA_ARGS__) -#define vsuxseg8ei32_v_f32m1_m(...) __riscv_vsuxseg8ei32_v_f32m1_m(__VA_ARGS__) -#define vsuxseg2ei32_v_f32m2_m(...) __riscv_vsuxseg2ei32_v_f32m2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_f32m2_m(...) __riscv_vsuxseg3ei32_v_f32m2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_f32m2_m(...) __riscv_vsuxseg4ei32_v_f32m2_m(__VA_ARGS__) -#define vsuxseg2ei32_v_f32m4_m(...) __riscv_vsuxseg2ei32_v_f32m4_m(__VA_ARGS__) -#define vsuxseg2ei64_v_f32mf2_m(...) __riscv_vsuxseg2ei64_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg3ei64_v_f32mf2_m(...) __riscv_vsuxseg3ei64_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg4ei64_v_f32mf2_m(...) __riscv_vsuxseg4ei64_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg5ei64_v_f32mf2_m(...) __riscv_vsuxseg5ei64_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg6ei64_v_f32mf2_m(...) __riscv_vsuxseg6ei64_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg7ei64_v_f32mf2_m(...) __riscv_vsuxseg7ei64_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg8ei64_v_f32mf2_m(...) __riscv_vsuxseg8ei64_v_f32mf2_m(__VA_ARGS__) -#define vsuxseg2ei64_v_f32m1_m(...) __riscv_vsuxseg2ei64_v_f32m1_m(__VA_ARGS__) -#define vsuxseg3ei64_v_f32m1_m(...) __riscv_vsuxseg3ei64_v_f32m1_m(__VA_ARGS__) -#define vsuxseg4ei64_v_f32m1_m(...) __riscv_vsuxseg4ei64_v_f32m1_m(__VA_ARGS__) -#define vsuxseg5ei64_v_f32m1_m(...) __riscv_vsuxseg5ei64_v_f32m1_m(__VA_ARGS__) -#define vsuxseg6ei64_v_f32m1_m(...) __riscv_vsuxseg6ei64_v_f32m1_m(__VA_ARGS__) -#define vsuxseg7ei64_v_f32m1_m(...) __riscv_vsuxseg7ei64_v_f32m1_m(__VA_ARGS__) -#define vsuxseg8ei64_v_f32m1_m(...) __riscv_vsuxseg8ei64_v_f32m1_m(__VA_ARGS__) -#define vsuxseg2ei64_v_f32m2_m(...) __riscv_vsuxseg2ei64_v_f32m2_m(__VA_ARGS__) -#define vsuxseg3ei64_v_f32m2_m(...) __riscv_vsuxseg3ei64_v_f32m2_m(__VA_ARGS__) -#define vsuxseg4ei64_v_f32m2_m(...) __riscv_vsuxseg4ei64_v_f32m2_m(__VA_ARGS__) -#define vsuxseg2ei64_v_f32m4_m(...) __riscv_vsuxseg2ei64_v_f32m4_m(__VA_ARGS__) -#define vsuxseg2ei8_v_f64m1_m(...) __riscv_vsuxseg2ei8_v_f64m1_m(__VA_ARGS__) -#define vsuxseg3ei8_v_f64m1_m(...) __riscv_vsuxseg3ei8_v_f64m1_m(__VA_ARGS__) -#define vsuxseg4ei8_v_f64m1_m(...) __riscv_vsuxseg4ei8_v_f64m1_m(__VA_ARGS__) -#define vsuxseg5ei8_v_f64m1_m(...) __riscv_vsuxseg5ei8_v_f64m1_m(__VA_ARGS__) -#define vsuxseg6ei8_v_f64m1_m(...) __riscv_vsuxseg6ei8_v_f64m1_m(__VA_ARGS__) -#define vsuxseg7ei8_v_f64m1_m(...) __riscv_vsuxseg7ei8_v_f64m1_m(__VA_ARGS__) -#define vsuxseg8ei8_v_f64m1_m(...) __riscv_vsuxseg8ei8_v_f64m1_m(__VA_ARGS__) -#define vsuxseg2ei8_v_f64m2_m(...) __riscv_vsuxseg2ei8_v_f64m2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_f64m2_m(...) __riscv_vsuxseg3ei8_v_f64m2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_f64m2_m(...) __riscv_vsuxseg4ei8_v_f64m2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_f64m4_m(...) __riscv_vsuxseg2ei8_v_f64m4_m(__VA_ARGS__) -#define vsuxseg2ei16_v_f64m1_m(...) __riscv_vsuxseg2ei16_v_f64m1_m(__VA_ARGS__) -#define vsuxseg3ei16_v_f64m1_m(...) __riscv_vsuxseg3ei16_v_f64m1_m(__VA_ARGS__) -#define vsuxseg4ei16_v_f64m1_m(...) __riscv_vsuxseg4ei16_v_f64m1_m(__VA_ARGS__) -#define vsuxseg5ei16_v_f64m1_m(...) __riscv_vsuxseg5ei16_v_f64m1_m(__VA_ARGS__) -#define vsuxseg6ei16_v_f64m1_m(...) __riscv_vsuxseg6ei16_v_f64m1_m(__VA_ARGS__) -#define vsuxseg7ei16_v_f64m1_m(...) __riscv_vsuxseg7ei16_v_f64m1_m(__VA_ARGS__) -#define vsuxseg8ei16_v_f64m1_m(...) __riscv_vsuxseg8ei16_v_f64m1_m(__VA_ARGS__) -#define vsuxseg2ei16_v_f64m2_m(...) __riscv_vsuxseg2ei16_v_f64m2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_f64m2_m(...) __riscv_vsuxseg3ei16_v_f64m2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_f64m2_m(...) __riscv_vsuxseg4ei16_v_f64m2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_f64m4_m(...) __riscv_vsuxseg2ei16_v_f64m4_m(__VA_ARGS__) -#define vsuxseg2ei32_v_f64m1_m(...) __riscv_vsuxseg2ei32_v_f64m1_m(__VA_ARGS__) -#define vsuxseg3ei32_v_f64m1_m(...) __riscv_vsuxseg3ei32_v_f64m1_m(__VA_ARGS__) -#define vsuxseg4ei32_v_f64m1_m(...) __riscv_vsuxseg4ei32_v_f64m1_m(__VA_ARGS__) -#define vsuxseg5ei32_v_f64m1_m(...) __riscv_vsuxseg5ei32_v_f64m1_m(__VA_ARGS__) -#define vsuxseg6ei32_v_f64m1_m(...) __riscv_vsuxseg6ei32_v_f64m1_m(__VA_ARGS__) -#define vsuxseg7ei32_v_f64m1_m(...) __riscv_vsuxseg7ei32_v_f64m1_m(__VA_ARGS__) -#define vsuxseg8ei32_v_f64m1_m(...) __riscv_vsuxseg8ei32_v_f64m1_m(__VA_ARGS__) -#define vsuxseg2ei32_v_f64m2_m(...) __riscv_vsuxseg2ei32_v_f64m2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_f64m2_m(...) __riscv_vsuxseg3ei32_v_f64m2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_f64m2_m(...) __riscv_vsuxseg4ei32_v_f64m2_m(__VA_ARGS__) -#define vsuxseg2ei32_v_f64m4_m(...) __riscv_vsuxseg2ei32_v_f64m4_m(__VA_ARGS__) -#define vsuxseg2ei64_v_f64m1_m(...) __riscv_vsuxseg2ei64_v_f64m1_m(__VA_ARGS__) -#define vsuxseg3ei64_v_f64m1_m(...) __riscv_vsuxseg3ei64_v_f64m1_m(__VA_ARGS__) -#define vsuxseg4ei64_v_f64m1_m(...) __riscv_vsuxseg4ei64_v_f64m1_m(__VA_ARGS__) -#define vsuxseg5ei64_v_f64m1_m(...) __riscv_vsuxseg5ei64_v_f64m1_m(__VA_ARGS__) -#define vsuxseg6ei64_v_f64m1_m(...) __riscv_vsuxseg6ei64_v_f64m1_m(__VA_ARGS__) -#define vsuxseg7ei64_v_f64m1_m(...) __riscv_vsuxseg7ei64_v_f64m1_m(__VA_ARGS__) -#define vsuxseg8ei64_v_f64m1_m(...) __riscv_vsuxseg8ei64_v_f64m1_m(__VA_ARGS__) -#define vsuxseg2ei64_v_f64m2_m(...) __riscv_vsuxseg2ei64_v_f64m2_m(__VA_ARGS__) -#define vsuxseg3ei64_v_f64m2_m(...) __riscv_vsuxseg3ei64_v_f64m2_m(__VA_ARGS__) -#define vsuxseg4ei64_v_f64m2_m(...) __riscv_vsuxseg4ei64_v_f64m2_m(__VA_ARGS__) -#define vsuxseg2ei64_v_f64m4_m(...) __riscv_vsuxseg2ei64_v_f64m4_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i8mf8_m(...) __riscv_vsoxseg2ei8_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg3ei8_v_i8mf8_m(...) __riscv_vsoxseg3ei8_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg4ei8_v_i8mf8_m(...) __riscv_vsoxseg4ei8_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg5ei8_v_i8mf8_m(...) __riscv_vsoxseg5ei8_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg6ei8_v_i8mf8_m(...) __riscv_vsoxseg6ei8_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg7ei8_v_i8mf8_m(...) __riscv_vsoxseg7ei8_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg8ei8_v_i8mf8_m(...) __riscv_vsoxseg8ei8_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i8mf4_m(...) __riscv_vsoxseg2ei8_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg3ei8_v_i8mf4_m(...) __riscv_vsoxseg3ei8_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg4ei8_v_i8mf4_m(...) __riscv_vsoxseg4ei8_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg5ei8_v_i8mf4_m(...) __riscv_vsoxseg5ei8_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg6ei8_v_i8mf4_m(...) __riscv_vsoxseg6ei8_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg7ei8_v_i8mf4_m(...) __riscv_vsoxseg7ei8_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg8ei8_v_i8mf4_m(...) __riscv_vsoxseg8ei8_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i8mf2_m(...) __riscv_vsoxseg2ei8_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_i8mf2_m(...) __riscv_vsoxseg3ei8_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_i8mf2_m(...) __riscv_vsoxseg4ei8_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg5ei8_v_i8mf2_m(...) __riscv_vsoxseg5ei8_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg6ei8_v_i8mf2_m(...) __riscv_vsoxseg6ei8_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg7ei8_v_i8mf2_m(...) __riscv_vsoxseg7ei8_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg8ei8_v_i8mf2_m(...) __riscv_vsoxseg8ei8_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i8m1_m(...) __riscv_vsoxseg2ei8_v_i8m1_m(__VA_ARGS__) -#define vsoxseg3ei8_v_i8m1_m(...) __riscv_vsoxseg3ei8_v_i8m1_m(__VA_ARGS__) -#define vsoxseg4ei8_v_i8m1_m(...) __riscv_vsoxseg4ei8_v_i8m1_m(__VA_ARGS__) -#define vsoxseg5ei8_v_i8m1_m(...) __riscv_vsoxseg5ei8_v_i8m1_m(__VA_ARGS__) -#define vsoxseg6ei8_v_i8m1_m(...) __riscv_vsoxseg6ei8_v_i8m1_m(__VA_ARGS__) -#define vsoxseg7ei8_v_i8m1_m(...) __riscv_vsoxseg7ei8_v_i8m1_m(__VA_ARGS__) -#define vsoxseg8ei8_v_i8m1_m(...) __riscv_vsoxseg8ei8_v_i8m1_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i8m2_m(...) __riscv_vsoxseg2ei8_v_i8m2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_i8m2_m(...) __riscv_vsoxseg3ei8_v_i8m2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_i8m2_m(...) __riscv_vsoxseg4ei8_v_i8m2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i8m4_m(...) __riscv_vsoxseg2ei8_v_i8m4_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i8mf8_m(...) __riscv_vsoxseg2ei16_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg3ei16_v_i8mf8_m(...) __riscv_vsoxseg3ei16_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg4ei16_v_i8mf8_m(...) __riscv_vsoxseg4ei16_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg5ei16_v_i8mf8_m(...) __riscv_vsoxseg5ei16_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg6ei16_v_i8mf8_m(...) __riscv_vsoxseg6ei16_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg7ei16_v_i8mf8_m(...) __riscv_vsoxseg7ei16_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg8ei16_v_i8mf8_m(...) __riscv_vsoxseg8ei16_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i8mf4_m(...) __riscv_vsoxseg2ei16_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg3ei16_v_i8mf4_m(...) __riscv_vsoxseg3ei16_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg4ei16_v_i8mf4_m(...) __riscv_vsoxseg4ei16_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg5ei16_v_i8mf4_m(...) __riscv_vsoxseg5ei16_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg6ei16_v_i8mf4_m(...) __riscv_vsoxseg6ei16_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg7ei16_v_i8mf4_m(...) __riscv_vsoxseg7ei16_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg8ei16_v_i8mf4_m(...) __riscv_vsoxseg8ei16_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i8mf2_m(...) __riscv_vsoxseg2ei16_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_i8mf2_m(...) __riscv_vsoxseg3ei16_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_i8mf2_m(...) __riscv_vsoxseg4ei16_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg5ei16_v_i8mf2_m(...) __riscv_vsoxseg5ei16_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg6ei16_v_i8mf2_m(...) __riscv_vsoxseg6ei16_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg7ei16_v_i8mf2_m(...) __riscv_vsoxseg7ei16_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg8ei16_v_i8mf2_m(...) __riscv_vsoxseg8ei16_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i8m1_m(...) __riscv_vsoxseg2ei16_v_i8m1_m(__VA_ARGS__) -#define vsoxseg3ei16_v_i8m1_m(...) __riscv_vsoxseg3ei16_v_i8m1_m(__VA_ARGS__) -#define vsoxseg4ei16_v_i8m1_m(...) __riscv_vsoxseg4ei16_v_i8m1_m(__VA_ARGS__) -#define vsoxseg5ei16_v_i8m1_m(...) __riscv_vsoxseg5ei16_v_i8m1_m(__VA_ARGS__) -#define vsoxseg6ei16_v_i8m1_m(...) __riscv_vsoxseg6ei16_v_i8m1_m(__VA_ARGS__) -#define vsoxseg7ei16_v_i8m1_m(...) __riscv_vsoxseg7ei16_v_i8m1_m(__VA_ARGS__) -#define vsoxseg8ei16_v_i8m1_m(...) __riscv_vsoxseg8ei16_v_i8m1_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i8m2_m(...) __riscv_vsoxseg2ei16_v_i8m2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_i8m2_m(...) __riscv_vsoxseg3ei16_v_i8m2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_i8m2_m(...) __riscv_vsoxseg4ei16_v_i8m2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i8m4_m(...) __riscv_vsoxseg2ei16_v_i8m4_m(__VA_ARGS__) -#define vsoxseg2ei32_v_i8mf8_m(...) __riscv_vsoxseg2ei32_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg3ei32_v_i8mf8_m(...) __riscv_vsoxseg3ei32_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg4ei32_v_i8mf8_m(...) __riscv_vsoxseg4ei32_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg5ei32_v_i8mf8_m(...) __riscv_vsoxseg5ei32_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg6ei32_v_i8mf8_m(...) __riscv_vsoxseg6ei32_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg7ei32_v_i8mf8_m(...) __riscv_vsoxseg7ei32_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg8ei32_v_i8mf8_m(...) __riscv_vsoxseg8ei32_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg2ei32_v_i8mf4_m(...) __riscv_vsoxseg2ei32_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg3ei32_v_i8mf4_m(...) __riscv_vsoxseg3ei32_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg4ei32_v_i8mf4_m(...) __riscv_vsoxseg4ei32_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg5ei32_v_i8mf4_m(...) __riscv_vsoxseg5ei32_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg6ei32_v_i8mf4_m(...) __riscv_vsoxseg6ei32_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg7ei32_v_i8mf4_m(...) __riscv_vsoxseg7ei32_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg8ei32_v_i8mf4_m(...) __riscv_vsoxseg8ei32_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg2ei32_v_i8mf2_m(...) __riscv_vsoxseg2ei32_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_i8mf2_m(...) __riscv_vsoxseg3ei32_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_i8mf2_m(...) __riscv_vsoxseg4ei32_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg5ei32_v_i8mf2_m(...) __riscv_vsoxseg5ei32_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg6ei32_v_i8mf2_m(...) __riscv_vsoxseg6ei32_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg7ei32_v_i8mf2_m(...) __riscv_vsoxseg7ei32_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg8ei32_v_i8mf2_m(...) __riscv_vsoxseg8ei32_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg2ei32_v_i8m1_m(...) __riscv_vsoxseg2ei32_v_i8m1_m(__VA_ARGS__) -#define vsoxseg3ei32_v_i8m1_m(...) __riscv_vsoxseg3ei32_v_i8m1_m(__VA_ARGS__) -#define vsoxseg4ei32_v_i8m1_m(...) __riscv_vsoxseg4ei32_v_i8m1_m(__VA_ARGS__) -#define vsoxseg5ei32_v_i8m1_m(...) __riscv_vsoxseg5ei32_v_i8m1_m(__VA_ARGS__) -#define vsoxseg6ei32_v_i8m1_m(...) __riscv_vsoxseg6ei32_v_i8m1_m(__VA_ARGS__) -#define vsoxseg7ei32_v_i8m1_m(...) __riscv_vsoxseg7ei32_v_i8m1_m(__VA_ARGS__) -#define vsoxseg8ei32_v_i8m1_m(...) __riscv_vsoxseg8ei32_v_i8m1_m(__VA_ARGS__) -#define vsoxseg2ei32_v_i8m2_m(...) __riscv_vsoxseg2ei32_v_i8m2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_i8m2_m(...) __riscv_vsoxseg3ei32_v_i8m2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_i8m2_m(...) __riscv_vsoxseg4ei32_v_i8m2_m(__VA_ARGS__) -#define vsoxseg2ei64_v_i8mf8_m(...) __riscv_vsoxseg2ei64_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg3ei64_v_i8mf8_m(...) __riscv_vsoxseg3ei64_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg4ei64_v_i8mf8_m(...) __riscv_vsoxseg4ei64_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg5ei64_v_i8mf8_m(...) __riscv_vsoxseg5ei64_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg6ei64_v_i8mf8_m(...) __riscv_vsoxseg6ei64_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg7ei64_v_i8mf8_m(...) __riscv_vsoxseg7ei64_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg8ei64_v_i8mf8_m(...) __riscv_vsoxseg8ei64_v_i8mf8_m(__VA_ARGS__) -#define vsoxseg2ei64_v_i8mf4_m(...) __riscv_vsoxseg2ei64_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg3ei64_v_i8mf4_m(...) __riscv_vsoxseg3ei64_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg4ei64_v_i8mf4_m(...) __riscv_vsoxseg4ei64_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg5ei64_v_i8mf4_m(...) __riscv_vsoxseg5ei64_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg6ei64_v_i8mf4_m(...) __riscv_vsoxseg6ei64_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg7ei64_v_i8mf4_m(...) __riscv_vsoxseg7ei64_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg8ei64_v_i8mf4_m(...) __riscv_vsoxseg8ei64_v_i8mf4_m(__VA_ARGS__) -#define vsoxseg2ei64_v_i8mf2_m(...) __riscv_vsoxseg2ei64_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg3ei64_v_i8mf2_m(...) __riscv_vsoxseg3ei64_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg4ei64_v_i8mf2_m(...) __riscv_vsoxseg4ei64_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg5ei64_v_i8mf2_m(...) __riscv_vsoxseg5ei64_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg6ei64_v_i8mf2_m(...) __riscv_vsoxseg6ei64_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg7ei64_v_i8mf2_m(...) __riscv_vsoxseg7ei64_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg8ei64_v_i8mf2_m(...) __riscv_vsoxseg8ei64_v_i8mf2_m(__VA_ARGS__) -#define vsoxseg2ei64_v_i8m1_m(...) __riscv_vsoxseg2ei64_v_i8m1_m(__VA_ARGS__) -#define vsoxseg3ei64_v_i8m1_m(...) __riscv_vsoxseg3ei64_v_i8m1_m(__VA_ARGS__) -#define vsoxseg4ei64_v_i8m1_m(...) __riscv_vsoxseg4ei64_v_i8m1_m(__VA_ARGS__) -#define vsoxseg5ei64_v_i8m1_m(...) __riscv_vsoxseg5ei64_v_i8m1_m(__VA_ARGS__) -#define vsoxseg6ei64_v_i8m1_m(...) __riscv_vsoxseg6ei64_v_i8m1_m(__VA_ARGS__) -#define vsoxseg7ei64_v_i8m1_m(...) __riscv_vsoxseg7ei64_v_i8m1_m(__VA_ARGS__) -#define vsoxseg8ei64_v_i8m1_m(...) __riscv_vsoxseg8ei64_v_i8m1_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i16mf4_m(...) __riscv_vsoxseg2ei8_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg3ei8_v_i16mf4_m(...) __riscv_vsoxseg3ei8_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg4ei8_v_i16mf4_m(...) __riscv_vsoxseg4ei8_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg5ei8_v_i16mf4_m(...) __riscv_vsoxseg5ei8_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg6ei8_v_i16mf4_m(...) __riscv_vsoxseg6ei8_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg7ei8_v_i16mf4_m(...) __riscv_vsoxseg7ei8_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg8ei8_v_i16mf4_m(...) __riscv_vsoxseg8ei8_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i16mf2_m(...) __riscv_vsoxseg2ei8_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_i16mf2_m(...) __riscv_vsoxseg3ei8_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_i16mf2_m(...) __riscv_vsoxseg4ei8_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg5ei8_v_i16mf2_m(...) __riscv_vsoxseg5ei8_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg6ei8_v_i16mf2_m(...) __riscv_vsoxseg6ei8_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg7ei8_v_i16mf2_m(...) __riscv_vsoxseg7ei8_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg8ei8_v_i16mf2_m(...) __riscv_vsoxseg8ei8_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i16m1_m(...) __riscv_vsoxseg2ei8_v_i16m1_m(__VA_ARGS__) -#define vsoxseg3ei8_v_i16m1_m(...) __riscv_vsoxseg3ei8_v_i16m1_m(__VA_ARGS__) -#define vsoxseg4ei8_v_i16m1_m(...) __riscv_vsoxseg4ei8_v_i16m1_m(__VA_ARGS__) -#define vsoxseg5ei8_v_i16m1_m(...) __riscv_vsoxseg5ei8_v_i16m1_m(__VA_ARGS__) -#define vsoxseg6ei8_v_i16m1_m(...) __riscv_vsoxseg6ei8_v_i16m1_m(__VA_ARGS__) -#define vsoxseg7ei8_v_i16m1_m(...) __riscv_vsoxseg7ei8_v_i16m1_m(__VA_ARGS__) -#define vsoxseg8ei8_v_i16m1_m(...) __riscv_vsoxseg8ei8_v_i16m1_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i16m2_m(...) __riscv_vsoxseg2ei8_v_i16m2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_i16m2_m(...) __riscv_vsoxseg3ei8_v_i16m2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_i16m2_m(...) __riscv_vsoxseg4ei8_v_i16m2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i16m4_m(...) __riscv_vsoxseg2ei8_v_i16m4_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i16mf4_m(...) __riscv_vsoxseg2ei16_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg3ei16_v_i16mf4_m(...) __riscv_vsoxseg3ei16_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg4ei16_v_i16mf4_m(...) __riscv_vsoxseg4ei16_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg5ei16_v_i16mf4_m(...) __riscv_vsoxseg5ei16_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg6ei16_v_i16mf4_m(...) __riscv_vsoxseg6ei16_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg7ei16_v_i16mf4_m(...) __riscv_vsoxseg7ei16_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg8ei16_v_i16mf4_m(...) __riscv_vsoxseg8ei16_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i16mf2_m(...) __riscv_vsoxseg2ei16_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_i16mf2_m(...) __riscv_vsoxseg3ei16_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_i16mf2_m(...) __riscv_vsoxseg4ei16_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg5ei16_v_i16mf2_m(...) __riscv_vsoxseg5ei16_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg6ei16_v_i16mf2_m(...) __riscv_vsoxseg6ei16_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg7ei16_v_i16mf2_m(...) __riscv_vsoxseg7ei16_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg8ei16_v_i16mf2_m(...) __riscv_vsoxseg8ei16_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i16m1_m(...) __riscv_vsoxseg2ei16_v_i16m1_m(__VA_ARGS__) -#define vsoxseg3ei16_v_i16m1_m(...) __riscv_vsoxseg3ei16_v_i16m1_m(__VA_ARGS__) -#define vsoxseg4ei16_v_i16m1_m(...) __riscv_vsoxseg4ei16_v_i16m1_m(__VA_ARGS__) -#define vsoxseg5ei16_v_i16m1_m(...) __riscv_vsoxseg5ei16_v_i16m1_m(__VA_ARGS__) -#define vsoxseg6ei16_v_i16m1_m(...) __riscv_vsoxseg6ei16_v_i16m1_m(__VA_ARGS__) -#define vsoxseg7ei16_v_i16m1_m(...) __riscv_vsoxseg7ei16_v_i16m1_m(__VA_ARGS__) -#define vsoxseg8ei16_v_i16m1_m(...) __riscv_vsoxseg8ei16_v_i16m1_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i16m2_m(...) __riscv_vsoxseg2ei16_v_i16m2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_i16m2_m(...) __riscv_vsoxseg3ei16_v_i16m2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_i16m2_m(...) __riscv_vsoxseg4ei16_v_i16m2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i16m4_m(...) __riscv_vsoxseg2ei16_v_i16m4_m(__VA_ARGS__) -#define vsoxseg2ei32_v_i16mf4_m(...) __riscv_vsoxseg2ei32_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg3ei32_v_i16mf4_m(...) __riscv_vsoxseg3ei32_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg4ei32_v_i16mf4_m(...) __riscv_vsoxseg4ei32_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg5ei32_v_i16mf4_m(...) __riscv_vsoxseg5ei32_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg6ei32_v_i16mf4_m(...) __riscv_vsoxseg6ei32_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg7ei32_v_i16mf4_m(...) __riscv_vsoxseg7ei32_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg8ei32_v_i16mf4_m(...) __riscv_vsoxseg8ei32_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg2ei32_v_i16mf2_m(...) __riscv_vsoxseg2ei32_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_i16mf2_m(...) __riscv_vsoxseg3ei32_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_i16mf2_m(...) __riscv_vsoxseg4ei32_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg5ei32_v_i16mf2_m(...) __riscv_vsoxseg5ei32_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg6ei32_v_i16mf2_m(...) __riscv_vsoxseg6ei32_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg7ei32_v_i16mf2_m(...) __riscv_vsoxseg7ei32_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg8ei32_v_i16mf2_m(...) __riscv_vsoxseg8ei32_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg2ei32_v_i16m1_m(...) __riscv_vsoxseg2ei32_v_i16m1_m(__VA_ARGS__) -#define vsoxseg3ei32_v_i16m1_m(...) __riscv_vsoxseg3ei32_v_i16m1_m(__VA_ARGS__) -#define vsoxseg4ei32_v_i16m1_m(...) __riscv_vsoxseg4ei32_v_i16m1_m(__VA_ARGS__) -#define vsoxseg5ei32_v_i16m1_m(...) __riscv_vsoxseg5ei32_v_i16m1_m(__VA_ARGS__) -#define vsoxseg6ei32_v_i16m1_m(...) __riscv_vsoxseg6ei32_v_i16m1_m(__VA_ARGS__) -#define vsoxseg7ei32_v_i16m1_m(...) __riscv_vsoxseg7ei32_v_i16m1_m(__VA_ARGS__) -#define vsoxseg8ei32_v_i16m1_m(...) __riscv_vsoxseg8ei32_v_i16m1_m(__VA_ARGS__) -#define vsoxseg2ei32_v_i16m2_m(...) __riscv_vsoxseg2ei32_v_i16m2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_i16m2_m(...) __riscv_vsoxseg3ei32_v_i16m2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_i16m2_m(...) __riscv_vsoxseg4ei32_v_i16m2_m(__VA_ARGS__) -#define vsoxseg2ei32_v_i16m4_m(...) __riscv_vsoxseg2ei32_v_i16m4_m(__VA_ARGS__) -#define vsoxseg2ei64_v_i16mf4_m(...) __riscv_vsoxseg2ei64_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg3ei64_v_i16mf4_m(...) __riscv_vsoxseg3ei64_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg4ei64_v_i16mf4_m(...) __riscv_vsoxseg4ei64_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg5ei64_v_i16mf4_m(...) __riscv_vsoxseg5ei64_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg6ei64_v_i16mf4_m(...) __riscv_vsoxseg6ei64_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg7ei64_v_i16mf4_m(...) __riscv_vsoxseg7ei64_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg8ei64_v_i16mf4_m(...) __riscv_vsoxseg8ei64_v_i16mf4_m(__VA_ARGS__) -#define vsoxseg2ei64_v_i16mf2_m(...) __riscv_vsoxseg2ei64_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg3ei64_v_i16mf2_m(...) __riscv_vsoxseg3ei64_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg4ei64_v_i16mf2_m(...) __riscv_vsoxseg4ei64_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg5ei64_v_i16mf2_m(...) __riscv_vsoxseg5ei64_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg6ei64_v_i16mf2_m(...) __riscv_vsoxseg6ei64_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg7ei64_v_i16mf2_m(...) __riscv_vsoxseg7ei64_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg8ei64_v_i16mf2_m(...) __riscv_vsoxseg8ei64_v_i16mf2_m(__VA_ARGS__) -#define vsoxseg2ei64_v_i16m1_m(...) __riscv_vsoxseg2ei64_v_i16m1_m(__VA_ARGS__) -#define vsoxseg3ei64_v_i16m1_m(...) __riscv_vsoxseg3ei64_v_i16m1_m(__VA_ARGS__) -#define vsoxseg4ei64_v_i16m1_m(...) __riscv_vsoxseg4ei64_v_i16m1_m(__VA_ARGS__) -#define vsoxseg5ei64_v_i16m1_m(...) __riscv_vsoxseg5ei64_v_i16m1_m(__VA_ARGS__) -#define vsoxseg6ei64_v_i16m1_m(...) __riscv_vsoxseg6ei64_v_i16m1_m(__VA_ARGS__) -#define vsoxseg7ei64_v_i16m1_m(...) __riscv_vsoxseg7ei64_v_i16m1_m(__VA_ARGS__) -#define vsoxseg8ei64_v_i16m1_m(...) __riscv_vsoxseg8ei64_v_i16m1_m(__VA_ARGS__) -#define vsoxseg2ei64_v_i16m2_m(...) __riscv_vsoxseg2ei64_v_i16m2_m(__VA_ARGS__) -#define vsoxseg3ei64_v_i16m2_m(...) __riscv_vsoxseg3ei64_v_i16m2_m(__VA_ARGS__) -#define vsoxseg4ei64_v_i16m2_m(...) __riscv_vsoxseg4ei64_v_i16m2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i32mf2_m(...) __riscv_vsoxseg2ei8_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_i32mf2_m(...) __riscv_vsoxseg3ei8_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_i32mf2_m(...) __riscv_vsoxseg4ei8_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg5ei8_v_i32mf2_m(...) __riscv_vsoxseg5ei8_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg6ei8_v_i32mf2_m(...) __riscv_vsoxseg6ei8_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg7ei8_v_i32mf2_m(...) __riscv_vsoxseg7ei8_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg8ei8_v_i32mf2_m(...) __riscv_vsoxseg8ei8_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i32m1_m(...) __riscv_vsoxseg2ei8_v_i32m1_m(__VA_ARGS__) -#define vsoxseg3ei8_v_i32m1_m(...) __riscv_vsoxseg3ei8_v_i32m1_m(__VA_ARGS__) -#define vsoxseg4ei8_v_i32m1_m(...) __riscv_vsoxseg4ei8_v_i32m1_m(__VA_ARGS__) -#define vsoxseg5ei8_v_i32m1_m(...) __riscv_vsoxseg5ei8_v_i32m1_m(__VA_ARGS__) -#define vsoxseg6ei8_v_i32m1_m(...) __riscv_vsoxseg6ei8_v_i32m1_m(__VA_ARGS__) -#define vsoxseg7ei8_v_i32m1_m(...) __riscv_vsoxseg7ei8_v_i32m1_m(__VA_ARGS__) -#define vsoxseg8ei8_v_i32m1_m(...) __riscv_vsoxseg8ei8_v_i32m1_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i32m2_m(...) __riscv_vsoxseg2ei8_v_i32m2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_i32m2_m(...) __riscv_vsoxseg3ei8_v_i32m2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_i32m2_m(...) __riscv_vsoxseg4ei8_v_i32m2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i32m4_m(...) __riscv_vsoxseg2ei8_v_i32m4_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i32mf2_m(...) __riscv_vsoxseg2ei16_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_i32mf2_m(...) __riscv_vsoxseg3ei16_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_i32mf2_m(...) __riscv_vsoxseg4ei16_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg5ei16_v_i32mf2_m(...) __riscv_vsoxseg5ei16_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg6ei16_v_i32mf2_m(...) __riscv_vsoxseg6ei16_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg7ei16_v_i32mf2_m(...) __riscv_vsoxseg7ei16_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg8ei16_v_i32mf2_m(...) __riscv_vsoxseg8ei16_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i32m1_m(...) __riscv_vsoxseg2ei16_v_i32m1_m(__VA_ARGS__) -#define vsoxseg3ei16_v_i32m1_m(...) __riscv_vsoxseg3ei16_v_i32m1_m(__VA_ARGS__) -#define vsoxseg4ei16_v_i32m1_m(...) __riscv_vsoxseg4ei16_v_i32m1_m(__VA_ARGS__) -#define vsoxseg5ei16_v_i32m1_m(...) __riscv_vsoxseg5ei16_v_i32m1_m(__VA_ARGS__) -#define vsoxseg6ei16_v_i32m1_m(...) __riscv_vsoxseg6ei16_v_i32m1_m(__VA_ARGS__) -#define vsoxseg7ei16_v_i32m1_m(...) __riscv_vsoxseg7ei16_v_i32m1_m(__VA_ARGS__) -#define vsoxseg8ei16_v_i32m1_m(...) __riscv_vsoxseg8ei16_v_i32m1_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i32m2_m(...) __riscv_vsoxseg2ei16_v_i32m2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_i32m2_m(...) __riscv_vsoxseg3ei16_v_i32m2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_i32m2_m(...) __riscv_vsoxseg4ei16_v_i32m2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i32m4_m(...) __riscv_vsoxseg2ei16_v_i32m4_m(__VA_ARGS__) -#define vsoxseg2ei32_v_i32mf2_m(...) __riscv_vsoxseg2ei32_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_i32mf2_m(...) __riscv_vsoxseg3ei32_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_i32mf2_m(...) __riscv_vsoxseg4ei32_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg5ei32_v_i32mf2_m(...) __riscv_vsoxseg5ei32_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg6ei32_v_i32mf2_m(...) __riscv_vsoxseg6ei32_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg7ei32_v_i32mf2_m(...) __riscv_vsoxseg7ei32_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg8ei32_v_i32mf2_m(...) __riscv_vsoxseg8ei32_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg2ei32_v_i32m1_m(...) __riscv_vsoxseg2ei32_v_i32m1_m(__VA_ARGS__) -#define vsoxseg3ei32_v_i32m1_m(...) __riscv_vsoxseg3ei32_v_i32m1_m(__VA_ARGS__) -#define vsoxseg4ei32_v_i32m1_m(...) __riscv_vsoxseg4ei32_v_i32m1_m(__VA_ARGS__) -#define vsoxseg5ei32_v_i32m1_m(...) __riscv_vsoxseg5ei32_v_i32m1_m(__VA_ARGS__) -#define vsoxseg6ei32_v_i32m1_m(...) __riscv_vsoxseg6ei32_v_i32m1_m(__VA_ARGS__) -#define vsoxseg7ei32_v_i32m1_m(...) __riscv_vsoxseg7ei32_v_i32m1_m(__VA_ARGS__) -#define vsoxseg8ei32_v_i32m1_m(...) __riscv_vsoxseg8ei32_v_i32m1_m(__VA_ARGS__) -#define vsoxseg2ei32_v_i32m2_m(...) __riscv_vsoxseg2ei32_v_i32m2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_i32m2_m(...) __riscv_vsoxseg3ei32_v_i32m2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_i32m2_m(...) __riscv_vsoxseg4ei32_v_i32m2_m(__VA_ARGS__) -#define vsoxseg2ei32_v_i32m4_m(...) __riscv_vsoxseg2ei32_v_i32m4_m(__VA_ARGS__) -#define vsoxseg2ei64_v_i32mf2_m(...) __riscv_vsoxseg2ei64_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg3ei64_v_i32mf2_m(...) __riscv_vsoxseg3ei64_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg4ei64_v_i32mf2_m(...) __riscv_vsoxseg4ei64_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg5ei64_v_i32mf2_m(...) __riscv_vsoxseg5ei64_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg6ei64_v_i32mf2_m(...) __riscv_vsoxseg6ei64_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg7ei64_v_i32mf2_m(...) __riscv_vsoxseg7ei64_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg8ei64_v_i32mf2_m(...) __riscv_vsoxseg8ei64_v_i32mf2_m(__VA_ARGS__) -#define vsoxseg2ei64_v_i32m1_m(...) __riscv_vsoxseg2ei64_v_i32m1_m(__VA_ARGS__) -#define vsoxseg3ei64_v_i32m1_m(...) __riscv_vsoxseg3ei64_v_i32m1_m(__VA_ARGS__) -#define vsoxseg4ei64_v_i32m1_m(...) __riscv_vsoxseg4ei64_v_i32m1_m(__VA_ARGS__) -#define vsoxseg5ei64_v_i32m1_m(...) __riscv_vsoxseg5ei64_v_i32m1_m(__VA_ARGS__) -#define vsoxseg6ei64_v_i32m1_m(...) __riscv_vsoxseg6ei64_v_i32m1_m(__VA_ARGS__) -#define vsoxseg7ei64_v_i32m1_m(...) __riscv_vsoxseg7ei64_v_i32m1_m(__VA_ARGS__) -#define vsoxseg8ei64_v_i32m1_m(...) __riscv_vsoxseg8ei64_v_i32m1_m(__VA_ARGS__) -#define vsoxseg2ei64_v_i32m2_m(...) __riscv_vsoxseg2ei64_v_i32m2_m(__VA_ARGS__) -#define vsoxseg3ei64_v_i32m2_m(...) __riscv_vsoxseg3ei64_v_i32m2_m(__VA_ARGS__) -#define vsoxseg4ei64_v_i32m2_m(...) __riscv_vsoxseg4ei64_v_i32m2_m(__VA_ARGS__) -#define vsoxseg2ei64_v_i32m4_m(...) __riscv_vsoxseg2ei64_v_i32m4_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i64m1_m(...) __riscv_vsoxseg2ei8_v_i64m1_m(__VA_ARGS__) -#define vsoxseg3ei8_v_i64m1_m(...) __riscv_vsoxseg3ei8_v_i64m1_m(__VA_ARGS__) -#define vsoxseg4ei8_v_i64m1_m(...) __riscv_vsoxseg4ei8_v_i64m1_m(__VA_ARGS__) -#define vsoxseg5ei8_v_i64m1_m(...) __riscv_vsoxseg5ei8_v_i64m1_m(__VA_ARGS__) -#define vsoxseg6ei8_v_i64m1_m(...) __riscv_vsoxseg6ei8_v_i64m1_m(__VA_ARGS__) -#define vsoxseg7ei8_v_i64m1_m(...) __riscv_vsoxseg7ei8_v_i64m1_m(__VA_ARGS__) -#define vsoxseg8ei8_v_i64m1_m(...) __riscv_vsoxseg8ei8_v_i64m1_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i64m2_m(...) __riscv_vsoxseg2ei8_v_i64m2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_i64m2_m(...) __riscv_vsoxseg3ei8_v_i64m2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_i64m2_m(...) __riscv_vsoxseg4ei8_v_i64m2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_i64m4_m(...) __riscv_vsoxseg2ei8_v_i64m4_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i64m1_m(...) __riscv_vsoxseg2ei16_v_i64m1_m(__VA_ARGS__) -#define vsoxseg3ei16_v_i64m1_m(...) __riscv_vsoxseg3ei16_v_i64m1_m(__VA_ARGS__) -#define vsoxseg4ei16_v_i64m1_m(...) __riscv_vsoxseg4ei16_v_i64m1_m(__VA_ARGS__) -#define vsoxseg5ei16_v_i64m1_m(...) __riscv_vsoxseg5ei16_v_i64m1_m(__VA_ARGS__) -#define vsoxseg6ei16_v_i64m1_m(...) __riscv_vsoxseg6ei16_v_i64m1_m(__VA_ARGS__) -#define vsoxseg7ei16_v_i64m1_m(...) __riscv_vsoxseg7ei16_v_i64m1_m(__VA_ARGS__) -#define vsoxseg8ei16_v_i64m1_m(...) __riscv_vsoxseg8ei16_v_i64m1_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i64m2_m(...) __riscv_vsoxseg2ei16_v_i64m2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_i64m2_m(...) __riscv_vsoxseg3ei16_v_i64m2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_i64m2_m(...) __riscv_vsoxseg4ei16_v_i64m2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_i64m4_m(...) __riscv_vsoxseg2ei16_v_i64m4_m(__VA_ARGS__) -#define vsoxseg2ei32_v_i64m1_m(...) __riscv_vsoxseg2ei32_v_i64m1_m(__VA_ARGS__) -#define vsoxseg3ei32_v_i64m1_m(...) __riscv_vsoxseg3ei32_v_i64m1_m(__VA_ARGS__) -#define vsoxseg4ei32_v_i64m1_m(...) __riscv_vsoxseg4ei32_v_i64m1_m(__VA_ARGS__) -#define vsoxseg5ei32_v_i64m1_m(...) __riscv_vsoxseg5ei32_v_i64m1_m(__VA_ARGS__) -#define vsoxseg6ei32_v_i64m1_m(...) __riscv_vsoxseg6ei32_v_i64m1_m(__VA_ARGS__) -#define vsoxseg7ei32_v_i64m1_m(...) __riscv_vsoxseg7ei32_v_i64m1_m(__VA_ARGS__) -#define vsoxseg8ei32_v_i64m1_m(...) __riscv_vsoxseg8ei32_v_i64m1_m(__VA_ARGS__) -#define vsoxseg2ei32_v_i64m2_m(...) __riscv_vsoxseg2ei32_v_i64m2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_i64m2_m(...) __riscv_vsoxseg3ei32_v_i64m2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_i64m2_m(...) __riscv_vsoxseg4ei32_v_i64m2_m(__VA_ARGS__) -#define vsoxseg2ei32_v_i64m4_m(...) __riscv_vsoxseg2ei32_v_i64m4_m(__VA_ARGS__) -#define vsoxseg2ei64_v_i64m1_m(...) __riscv_vsoxseg2ei64_v_i64m1_m(__VA_ARGS__) -#define vsoxseg3ei64_v_i64m1_m(...) __riscv_vsoxseg3ei64_v_i64m1_m(__VA_ARGS__) -#define vsoxseg4ei64_v_i64m1_m(...) __riscv_vsoxseg4ei64_v_i64m1_m(__VA_ARGS__) -#define vsoxseg5ei64_v_i64m1_m(...) __riscv_vsoxseg5ei64_v_i64m1_m(__VA_ARGS__) -#define vsoxseg6ei64_v_i64m1_m(...) __riscv_vsoxseg6ei64_v_i64m1_m(__VA_ARGS__) -#define vsoxseg7ei64_v_i64m1_m(...) __riscv_vsoxseg7ei64_v_i64m1_m(__VA_ARGS__) -#define vsoxseg8ei64_v_i64m1_m(...) __riscv_vsoxseg8ei64_v_i64m1_m(__VA_ARGS__) -#define vsoxseg2ei64_v_i64m2_m(...) __riscv_vsoxseg2ei64_v_i64m2_m(__VA_ARGS__) -#define vsoxseg3ei64_v_i64m2_m(...) __riscv_vsoxseg3ei64_v_i64m2_m(__VA_ARGS__) -#define vsoxseg4ei64_v_i64m2_m(...) __riscv_vsoxseg4ei64_v_i64m2_m(__VA_ARGS__) -#define vsoxseg2ei64_v_i64m4_m(...) __riscv_vsoxseg2ei64_v_i64m4_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i8mf8_m(...) __riscv_vsuxseg2ei8_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg3ei8_v_i8mf8_m(...) __riscv_vsuxseg3ei8_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg4ei8_v_i8mf8_m(...) __riscv_vsuxseg4ei8_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg5ei8_v_i8mf8_m(...) __riscv_vsuxseg5ei8_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg6ei8_v_i8mf8_m(...) __riscv_vsuxseg6ei8_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg7ei8_v_i8mf8_m(...) __riscv_vsuxseg7ei8_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg8ei8_v_i8mf8_m(...) __riscv_vsuxseg8ei8_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i8mf4_m(...) __riscv_vsuxseg2ei8_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg3ei8_v_i8mf4_m(...) __riscv_vsuxseg3ei8_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg4ei8_v_i8mf4_m(...) __riscv_vsuxseg4ei8_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg5ei8_v_i8mf4_m(...) __riscv_vsuxseg5ei8_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg6ei8_v_i8mf4_m(...) __riscv_vsuxseg6ei8_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg7ei8_v_i8mf4_m(...) __riscv_vsuxseg7ei8_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg8ei8_v_i8mf4_m(...) __riscv_vsuxseg8ei8_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i8mf2_m(...) __riscv_vsuxseg2ei8_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_i8mf2_m(...) __riscv_vsuxseg3ei8_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_i8mf2_m(...) __riscv_vsuxseg4ei8_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg5ei8_v_i8mf2_m(...) __riscv_vsuxseg5ei8_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg6ei8_v_i8mf2_m(...) __riscv_vsuxseg6ei8_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg7ei8_v_i8mf2_m(...) __riscv_vsuxseg7ei8_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg8ei8_v_i8mf2_m(...) __riscv_vsuxseg8ei8_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i8m1_m(...) __riscv_vsuxseg2ei8_v_i8m1_m(__VA_ARGS__) -#define vsuxseg3ei8_v_i8m1_m(...) __riscv_vsuxseg3ei8_v_i8m1_m(__VA_ARGS__) -#define vsuxseg4ei8_v_i8m1_m(...) __riscv_vsuxseg4ei8_v_i8m1_m(__VA_ARGS__) -#define vsuxseg5ei8_v_i8m1_m(...) __riscv_vsuxseg5ei8_v_i8m1_m(__VA_ARGS__) -#define vsuxseg6ei8_v_i8m1_m(...) __riscv_vsuxseg6ei8_v_i8m1_m(__VA_ARGS__) -#define vsuxseg7ei8_v_i8m1_m(...) __riscv_vsuxseg7ei8_v_i8m1_m(__VA_ARGS__) -#define vsuxseg8ei8_v_i8m1_m(...) __riscv_vsuxseg8ei8_v_i8m1_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i8m2_m(...) __riscv_vsuxseg2ei8_v_i8m2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_i8m2_m(...) __riscv_vsuxseg3ei8_v_i8m2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_i8m2_m(...) __riscv_vsuxseg4ei8_v_i8m2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i8m4_m(...) __riscv_vsuxseg2ei8_v_i8m4_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i8mf8_m(...) __riscv_vsuxseg2ei16_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg3ei16_v_i8mf8_m(...) __riscv_vsuxseg3ei16_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg4ei16_v_i8mf8_m(...) __riscv_vsuxseg4ei16_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg5ei16_v_i8mf8_m(...) __riscv_vsuxseg5ei16_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg6ei16_v_i8mf8_m(...) __riscv_vsuxseg6ei16_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg7ei16_v_i8mf8_m(...) __riscv_vsuxseg7ei16_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg8ei16_v_i8mf8_m(...) __riscv_vsuxseg8ei16_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i8mf4_m(...) __riscv_vsuxseg2ei16_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg3ei16_v_i8mf4_m(...) __riscv_vsuxseg3ei16_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg4ei16_v_i8mf4_m(...) __riscv_vsuxseg4ei16_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg5ei16_v_i8mf4_m(...) __riscv_vsuxseg5ei16_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg6ei16_v_i8mf4_m(...) __riscv_vsuxseg6ei16_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg7ei16_v_i8mf4_m(...) __riscv_vsuxseg7ei16_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg8ei16_v_i8mf4_m(...) __riscv_vsuxseg8ei16_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i8mf2_m(...) __riscv_vsuxseg2ei16_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_i8mf2_m(...) __riscv_vsuxseg3ei16_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_i8mf2_m(...) __riscv_vsuxseg4ei16_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg5ei16_v_i8mf2_m(...) __riscv_vsuxseg5ei16_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg6ei16_v_i8mf2_m(...) __riscv_vsuxseg6ei16_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg7ei16_v_i8mf2_m(...) __riscv_vsuxseg7ei16_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg8ei16_v_i8mf2_m(...) __riscv_vsuxseg8ei16_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i8m1_m(...) __riscv_vsuxseg2ei16_v_i8m1_m(__VA_ARGS__) -#define vsuxseg3ei16_v_i8m1_m(...) __riscv_vsuxseg3ei16_v_i8m1_m(__VA_ARGS__) -#define vsuxseg4ei16_v_i8m1_m(...) __riscv_vsuxseg4ei16_v_i8m1_m(__VA_ARGS__) -#define vsuxseg5ei16_v_i8m1_m(...) __riscv_vsuxseg5ei16_v_i8m1_m(__VA_ARGS__) -#define vsuxseg6ei16_v_i8m1_m(...) __riscv_vsuxseg6ei16_v_i8m1_m(__VA_ARGS__) -#define vsuxseg7ei16_v_i8m1_m(...) __riscv_vsuxseg7ei16_v_i8m1_m(__VA_ARGS__) -#define vsuxseg8ei16_v_i8m1_m(...) __riscv_vsuxseg8ei16_v_i8m1_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i8m2_m(...) __riscv_vsuxseg2ei16_v_i8m2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_i8m2_m(...) __riscv_vsuxseg3ei16_v_i8m2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_i8m2_m(...) __riscv_vsuxseg4ei16_v_i8m2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i8m4_m(...) __riscv_vsuxseg2ei16_v_i8m4_m(__VA_ARGS__) -#define vsuxseg2ei32_v_i8mf8_m(...) __riscv_vsuxseg2ei32_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg3ei32_v_i8mf8_m(...) __riscv_vsuxseg3ei32_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg4ei32_v_i8mf8_m(...) __riscv_vsuxseg4ei32_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg5ei32_v_i8mf8_m(...) __riscv_vsuxseg5ei32_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg6ei32_v_i8mf8_m(...) __riscv_vsuxseg6ei32_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg7ei32_v_i8mf8_m(...) __riscv_vsuxseg7ei32_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg8ei32_v_i8mf8_m(...) __riscv_vsuxseg8ei32_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg2ei32_v_i8mf4_m(...) __riscv_vsuxseg2ei32_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg3ei32_v_i8mf4_m(...) __riscv_vsuxseg3ei32_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg4ei32_v_i8mf4_m(...) __riscv_vsuxseg4ei32_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg5ei32_v_i8mf4_m(...) __riscv_vsuxseg5ei32_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg6ei32_v_i8mf4_m(...) __riscv_vsuxseg6ei32_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg7ei32_v_i8mf4_m(...) __riscv_vsuxseg7ei32_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg8ei32_v_i8mf4_m(...) __riscv_vsuxseg8ei32_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg2ei32_v_i8mf2_m(...) __riscv_vsuxseg2ei32_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_i8mf2_m(...) __riscv_vsuxseg3ei32_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_i8mf2_m(...) __riscv_vsuxseg4ei32_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg5ei32_v_i8mf2_m(...) __riscv_vsuxseg5ei32_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg6ei32_v_i8mf2_m(...) __riscv_vsuxseg6ei32_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg7ei32_v_i8mf2_m(...) __riscv_vsuxseg7ei32_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg8ei32_v_i8mf2_m(...) __riscv_vsuxseg8ei32_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg2ei32_v_i8m1_m(...) __riscv_vsuxseg2ei32_v_i8m1_m(__VA_ARGS__) -#define vsuxseg3ei32_v_i8m1_m(...) __riscv_vsuxseg3ei32_v_i8m1_m(__VA_ARGS__) -#define vsuxseg4ei32_v_i8m1_m(...) __riscv_vsuxseg4ei32_v_i8m1_m(__VA_ARGS__) -#define vsuxseg5ei32_v_i8m1_m(...) __riscv_vsuxseg5ei32_v_i8m1_m(__VA_ARGS__) -#define vsuxseg6ei32_v_i8m1_m(...) __riscv_vsuxseg6ei32_v_i8m1_m(__VA_ARGS__) -#define vsuxseg7ei32_v_i8m1_m(...) __riscv_vsuxseg7ei32_v_i8m1_m(__VA_ARGS__) -#define vsuxseg8ei32_v_i8m1_m(...) __riscv_vsuxseg8ei32_v_i8m1_m(__VA_ARGS__) -#define vsuxseg2ei32_v_i8m2_m(...) __riscv_vsuxseg2ei32_v_i8m2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_i8m2_m(...) __riscv_vsuxseg3ei32_v_i8m2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_i8m2_m(...) __riscv_vsuxseg4ei32_v_i8m2_m(__VA_ARGS__) -#define vsuxseg2ei64_v_i8mf8_m(...) __riscv_vsuxseg2ei64_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg3ei64_v_i8mf8_m(...) __riscv_vsuxseg3ei64_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg4ei64_v_i8mf8_m(...) __riscv_vsuxseg4ei64_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg5ei64_v_i8mf8_m(...) __riscv_vsuxseg5ei64_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg6ei64_v_i8mf8_m(...) __riscv_vsuxseg6ei64_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg7ei64_v_i8mf8_m(...) __riscv_vsuxseg7ei64_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg8ei64_v_i8mf8_m(...) __riscv_vsuxseg8ei64_v_i8mf8_m(__VA_ARGS__) -#define vsuxseg2ei64_v_i8mf4_m(...) __riscv_vsuxseg2ei64_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg3ei64_v_i8mf4_m(...) __riscv_vsuxseg3ei64_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg4ei64_v_i8mf4_m(...) __riscv_vsuxseg4ei64_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg5ei64_v_i8mf4_m(...) __riscv_vsuxseg5ei64_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg6ei64_v_i8mf4_m(...) __riscv_vsuxseg6ei64_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg7ei64_v_i8mf4_m(...) __riscv_vsuxseg7ei64_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg8ei64_v_i8mf4_m(...) __riscv_vsuxseg8ei64_v_i8mf4_m(__VA_ARGS__) -#define vsuxseg2ei64_v_i8mf2_m(...) __riscv_vsuxseg2ei64_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg3ei64_v_i8mf2_m(...) __riscv_vsuxseg3ei64_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg4ei64_v_i8mf2_m(...) __riscv_vsuxseg4ei64_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg5ei64_v_i8mf2_m(...) __riscv_vsuxseg5ei64_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg6ei64_v_i8mf2_m(...) __riscv_vsuxseg6ei64_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg7ei64_v_i8mf2_m(...) __riscv_vsuxseg7ei64_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg8ei64_v_i8mf2_m(...) __riscv_vsuxseg8ei64_v_i8mf2_m(__VA_ARGS__) -#define vsuxseg2ei64_v_i8m1_m(...) __riscv_vsuxseg2ei64_v_i8m1_m(__VA_ARGS__) -#define vsuxseg3ei64_v_i8m1_m(...) __riscv_vsuxseg3ei64_v_i8m1_m(__VA_ARGS__) -#define vsuxseg4ei64_v_i8m1_m(...) __riscv_vsuxseg4ei64_v_i8m1_m(__VA_ARGS__) -#define vsuxseg5ei64_v_i8m1_m(...) __riscv_vsuxseg5ei64_v_i8m1_m(__VA_ARGS__) -#define vsuxseg6ei64_v_i8m1_m(...) __riscv_vsuxseg6ei64_v_i8m1_m(__VA_ARGS__) -#define vsuxseg7ei64_v_i8m1_m(...) __riscv_vsuxseg7ei64_v_i8m1_m(__VA_ARGS__) -#define vsuxseg8ei64_v_i8m1_m(...) __riscv_vsuxseg8ei64_v_i8m1_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i16mf4_m(...) __riscv_vsuxseg2ei8_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg3ei8_v_i16mf4_m(...) __riscv_vsuxseg3ei8_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg4ei8_v_i16mf4_m(...) __riscv_vsuxseg4ei8_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg5ei8_v_i16mf4_m(...) __riscv_vsuxseg5ei8_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg6ei8_v_i16mf4_m(...) __riscv_vsuxseg6ei8_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg7ei8_v_i16mf4_m(...) __riscv_vsuxseg7ei8_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg8ei8_v_i16mf4_m(...) __riscv_vsuxseg8ei8_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i16mf2_m(...) __riscv_vsuxseg2ei8_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_i16mf2_m(...) __riscv_vsuxseg3ei8_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_i16mf2_m(...) __riscv_vsuxseg4ei8_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg5ei8_v_i16mf2_m(...) __riscv_vsuxseg5ei8_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg6ei8_v_i16mf2_m(...) __riscv_vsuxseg6ei8_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg7ei8_v_i16mf2_m(...) __riscv_vsuxseg7ei8_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg8ei8_v_i16mf2_m(...) __riscv_vsuxseg8ei8_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i16m1_m(...) __riscv_vsuxseg2ei8_v_i16m1_m(__VA_ARGS__) -#define vsuxseg3ei8_v_i16m1_m(...) __riscv_vsuxseg3ei8_v_i16m1_m(__VA_ARGS__) -#define vsuxseg4ei8_v_i16m1_m(...) __riscv_vsuxseg4ei8_v_i16m1_m(__VA_ARGS__) -#define vsuxseg5ei8_v_i16m1_m(...) __riscv_vsuxseg5ei8_v_i16m1_m(__VA_ARGS__) -#define vsuxseg6ei8_v_i16m1_m(...) __riscv_vsuxseg6ei8_v_i16m1_m(__VA_ARGS__) -#define vsuxseg7ei8_v_i16m1_m(...) __riscv_vsuxseg7ei8_v_i16m1_m(__VA_ARGS__) -#define vsuxseg8ei8_v_i16m1_m(...) __riscv_vsuxseg8ei8_v_i16m1_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i16m2_m(...) __riscv_vsuxseg2ei8_v_i16m2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_i16m2_m(...) __riscv_vsuxseg3ei8_v_i16m2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_i16m2_m(...) __riscv_vsuxseg4ei8_v_i16m2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i16m4_m(...) __riscv_vsuxseg2ei8_v_i16m4_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i16mf4_m(...) __riscv_vsuxseg2ei16_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg3ei16_v_i16mf4_m(...) __riscv_vsuxseg3ei16_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg4ei16_v_i16mf4_m(...) __riscv_vsuxseg4ei16_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg5ei16_v_i16mf4_m(...) __riscv_vsuxseg5ei16_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg6ei16_v_i16mf4_m(...) __riscv_vsuxseg6ei16_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg7ei16_v_i16mf4_m(...) __riscv_vsuxseg7ei16_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg8ei16_v_i16mf4_m(...) __riscv_vsuxseg8ei16_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i16mf2_m(...) __riscv_vsuxseg2ei16_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_i16mf2_m(...) __riscv_vsuxseg3ei16_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_i16mf2_m(...) __riscv_vsuxseg4ei16_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg5ei16_v_i16mf2_m(...) __riscv_vsuxseg5ei16_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg6ei16_v_i16mf2_m(...) __riscv_vsuxseg6ei16_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg7ei16_v_i16mf2_m(...) __riscv_vsuxseg7ei16_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg8ei16_v_i16mf2_m(...) __riscv_vsuxseg8ei16_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i16m1_m(...) __riscv_vsuxseg2ei16_v_i16m1_m(__VA_ARGS__) -#define vsuxseg3ei16_v_i16m1_m(...) __riscv_vsuxseg3ei16_v_i16m1_m(__VA_ARGS__) -#define vsuxseg4ei16_v_i16m1_m(...) __riscv_vsuxseg4ei16_v_i16m1_m(__VA_ARGS__) -#define vsuxseg5ei16_v_i16m1_m(...) __riscv_vsuxseg5ei16_v_i16m1_m(__VA_ARGS__) -#define vsuxseg6ei16_v_i16m1_m(...) __riscv_vsuxseg6ei16_v_i16m1_m(__VA_ARGS__) -#define vsuxseg7ei16_v_i16m1_m(...) __riscv_vsuxseg7ei16_v_i16m1_m(__VA_ARGS__) -#define vsuxseg8ei16_v_i16m1_m(...) __riscv_vsuxseg8ei16_v_i16m1_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i16m2_m(...) __riscv_vsuxseg2ei16_v_i16m2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_i16m2_m(...) __riscv_vsuxseg3ei16_v_i16m2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_i16m2_m(...) __riscv_vsuxseg4ei16_v_i16m2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i16m4_m(...) __riscv_vsuxseg2ei16_v_i16m4_m(__VA_ARGS__) -#define vsuxseg2ei32_v_i16mf4_m(...) __riscv_vsuxseg2ei32_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg3ei32_v_i16mf4_m(...) __riscv_vsuxseg3ei32_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg4ei32_v_i16mf4_m(...) __riscv_vsuxseg4ei32_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg5ei32_v_i16mf4_m(...) __riscv_vsuxseg5ei32_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg6ei32_v_i16mf4_m(...) __riscv_vsuxseg6ei32_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg7ei32_v_i16mf4_m(...) __riscv_vsuxseg7ei32_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg8ei32_v_i16mf4_m(...) __riscv_vsuxseg8ei32_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg2ei32_v_i16mf2_m(...) __riscv_vsuxseg2ei32_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_i16mf2_m(...) __riscv_vsuxseg3ei32_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_i16mf2_m(...) __riscv_vsuxseg4ei32_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg5ei32_v_i16mf2_m(...) __riscv_vsuxseg5ei32_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg6ei32_v_i16mf2_m(...) __riscv_vsuxseg6ei32_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg7ei32_v_i16mf2_m(...) __riscv_vsuxseg7ei32_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg8ei32_v_i16mf2_m(...) __riscv_vsuxseg8ei32_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg2ei32_v_i16m1_m(...) __riscv_vsuxseg2ei32_v_i16m1_m(__VA_ARGS__) -#define vsuxseg3ei32_v_i16m1_m(...) __riscv_vsuxseg3ei32_v_i16m1_m(__VA_ARGS__) -#define vsuxseg4ei32_v_i16m1_m(...) __riscv_vsuxseg4ei32_v_i16m1_m(__VA_ARGS__) -#define vsuxseg5ei32_v_i16m1_m(...) __riscv_vsuxseg5ei32_v_i16m1_m(__VA_ARGS__) -#define vsuxseg6ei32_v_i16m1_m(...) __riscv_vsuxseg6ei32_v_i16m1_m(__VA_ARGS__) -#define vsuxseg7ei32_v_i16m1_m(...) __riscv_vsuxseg7ei32_v_i16m1_m(__VA_ARGS__) -#define vsuxseg8ei32_v_i16m1_m(...) __riscv_vsuxseg8ei32_v_i16m1_m(__VA_ARGS__) -#define vsuxseg2ei32_v_i16m2_m(...) __riscv_vsuxseg2ei32_v_i16m2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_i16m2_m(...) __riscv_vsuxseg3ei32_v_i16m2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_i16m2_m(...) __riscv_vsuxseg4ei32_v_i16m2_m(__VA_ARGS__) -#define vsuxseg2ei32_v_i16m4_m(...) __riscv_vsuxseg2ei32_v_i16m4_m(__VA_ARGS__) -#define vsuxseg2ei64_v_i16mf4_m(...) __riscv_vsuxseg2ei64_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg3ei64_v_i16mf4_m(...) __riscv_vsuxseg3ei64_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg4ei64_v_i16mf4_m(...) __riscv_vsuxseg4ei64_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg5ei64_v_i16mf4_m(...) __riscv_vsuxseg5ei64_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg6ei64_v_i16mf4_m(...) __riscv_vsuxseg6ei64_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg7ei64_v_i16mf4_m(...) __riscv_vsuxseg7ei64_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg8ei64_v_i16mf4_m(...) __riscv_vsuxseg8ei64_v_i16mf4_m(__VA_ARGS__) -#define vsuxseg2ei64_v_i16mf2_m(...) __riscv_vsuxseg2ei64_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg3ei64_v_i16mf2_m(...) __riscv_vsuxseg3ei64_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg4ei64_v_i16mf2_m(...) __riscv_vsuxseg4ei64_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg5ei64_v_i16mf2_m(...) __riscv_vsuxseg5ei64_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg6ei64_v_i16mf2_m(...) __riscv_vsuxseg6ei64_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg7ei64_v_i16mf2_m(...) __riscv_vsuxseg7ei64_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg8ei64_v_i16mf2_m(...) __riscv_vsuxseg8ei64_v_i16mf2_m(__VA_ARGS__) -#define vsuxseg2ei64_v_i16m1_m(...) __riscv_vsuxseg2ei64_v_i16m1_m(__VA_ARGS__) -#define vsuxseg3ei64_v_i16m1_m(...) __riscv_vsuxseg3ei64_v_i16m1_m(__VA_ARGS__) -#define vsuxseg4ei64_v_i16m1_m(...) __riscv_vsuxseg4ei64_v_i16m1_m(__VA_ARGS__) -#define vsuxseg5ei64_v_i16m1_m(...) __riscv_vsuxseg5ei64_v_i16m1_m(__VA_ARGS__) -#define vsuxseg6ei64_v_i16m1_m(...) __riscv_vsuxseg6ei64_v_i16m1_m(__VA_ARGS__) -#define vsuxseg7ei64_v_i16m1_m(...) __riscv_vsuxseg7ei64_v_i16m1_m(__VA_ARGS__) -#define vsuxseg8ei64_v_i16m1_m(...) __riscv_vsuxseg8ei64_v_i16m1_m(__VA_ARGS__) -#define vsuxseg2ei64_v_i16m2_m(...) __riscv_vsuxseg2ei64_v_i16m2_m(__VA_ARGS__) -#define vsuxseg3ei64_v_i16m2_m(...) __riscv_vsuxseg3ei64_v_i16m2_m(__VA_ARGS__) -#define vsuxseg4ei64_v_i16m2_m(...) __riscv_vsuxseg4ei64_v_i16m2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i32mf2_m(...) __riscv_vsuxseg2ei8_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_i32mf2_m(...) __riscv_vsuxseg3ei8_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_i32mf2_m(...) __riscv_vsuxseg4ei8_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg5ei8_v_i32mf2_m(...) __riscv_vsuxseg5ei8_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg6ei8_v_i32mf2_m(...) __riscv_vsuxseg6ei8_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg7ei8_v_i32mf2_m(...) __riscv_vsuxseg7ei8_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg8ei8_v_i32mf2_m(...) __riscv_vsuxseg8ei8_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i32m1_m(...) __riscv_vsuxseg2ei8_v_i32m1_m(__VA_ARGS__) -#define vsuxseg3ei8_v_i32m1_m(...) __riscv_vsuxseg3ei8_v_i32m1_m(__VA_ARGS__) -#define vsuxseg4ei8_v_i32m1_m(...) __riscv_vsuxseg4ei8_v_i32m1_m(__VA_ARGS__) -#define vsuxseg5ei8_v_i32m1_m(...) __riscv_vsuxseg5ei8_v_i32m1_m(__VA_ARGS__) -#define vsuxseg6ei8_v_i32m1_m(...) __riscv_vsuxseg6ei8_v_i32m1_m(__VA_ARGS__) -#define vsuxseg7ei8_v_i32m1_m(...) __riscv_vsuxseg7ei8_v_i32m1_m(__VA_ARGS__) -#define vsuxseg8ei8_v_i32m1_m(...) __riscv_vsuxseg8ei8_v_i32m1_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i32m2_m(...) __riscv_vsuxseg2ei8_v_i32m2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_i32m2_m(...) __riscv_vsuxseg3ei8_v_i32m2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_i32m2_m(...) __riscv_vsuxseg4ei8_v_i32m2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i32m4_m(...) __riscv_vsuxseg2ei8_v_i32m4_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i32mf2_m(...) __riscv_vsuxseg2ei16_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_i32mf2_m(...) __riscv_vsuxseg3ei16_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_i32mf2_m(...) __riscv_vsuxseg4ei16_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg5ei16_v_i32mf2_m(...) __riscv_vsuxseg5ei16_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg6ei16_v_i32mf2_m(...) __riscv_vsuxseg6ei16_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg7ei16_v_i32mf2_m(...) __riscv_vsuxseg7ei16_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg8ei16_v_i32mf2_m(...) __riscv_vsuxseg8ei16_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i32m1_m(...) __riscv_vsuxseg2ei16_v_i32m1_m(__VA_ARGS__) -#define vsuxseg3ei16_v_i32m1_m(...) __riscv_vsuxseg3ei16_v_i32m1_m(__VA_ARGS__) -#define vsuxseg4ei16_v_i32m1_m(...) __riscv_vsuxseg4ei16_v_i32m1_m(__VA_ARGS__) -#define vsuxseg5ei16_v_i32m1_m(...) __riscv_vsuxseg5ei16_v_i32m1_m(__VA_ARGS__) -#define vsuxseg6ei16_v_i32m1_m(...) __riscv_vsuxseg6ei16_v_i32m1_m(__VA_ARGS__) -#define vsuxseg7ei16_v_i32m1_m(...) __riscv_vsuxseg7ei16_v_i32m1_m(__VA_ARGS__) -#define vsuxseg8ei16_v_i32m1_m(...) __riscv_vsuxseg8ei16_v_i32m1_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i32m2_m(...) __riscv_vsuxseg2ei16_v_i32m2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_i32m2_m(...) __riscv_vsuxseg3ei16_v_i32m2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_i32m2_m(...) __riscv_vsuxseg4ei16_v_i32m2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i32m4_m(...) __riscv_vsuxseg2ei16_v_i32m4_m(__VA_ARGS__) -#define vsuxseg2ei32_v_i32mf2_m(...) __riscv_vsuxseg2ei32_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_i32mf2_m(...) __riscv_vsuxseg3ei32_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_i32mf2_m(...) __riscv_vsuxseg4ei32_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg5ei32_v_i32mf2_m(...) __riscv_vsuxseg5ei32_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg6ei32_v_i32mf2_m(...) __riscv_vsuxseg6ei32_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg7ei32_v_i32mf2_m(...) __riscv_vsuxseg7ei32_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg8ei32_v_i32mf2_m(...) __riscv_vsuxseg8ei32_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg2ei32_v_i32m1_m(...) __riscv_vsuxseg2ei32_v_i32m1_m(__VA_ARGS__) -#define vsuxseg3ei32_v_i32m1_m(...) __riscv_vsuxseg3ei32_v_i32m1_m(__VA_ARGS__) -#define vsuxseg4ei32_v_i32m1_m(...) __riscv_vsuxseg4ei32_v_i32m1_m(__VA_ARGS__) -#define vsuxseg5ei32_v_i32m1_m(...) __riscv_vsuxseg5ei32_v_i32m1_m(__VA_ARGS__) -#define vsuxseg6ei32_v_i32m1_m(...) __riscv_vsuxseg6ei32_v_i32m1_m(__VA_ARGS__) -#define vsuxseg7ei32_v_i32m1_m(...) __riscv_vsuxseg7ei32_v_i32m1_m(__VA_ARGS__) -#define vsuxseg8ei32_v_i32m1_m(...) __riscv_vsuxseg8ei32_v_i32m1_m(__VA_ARGS__) -#define vsuxseg2ei32_v_i32m2_m(...) __riscv_vsuxseg2ei32_v_i32m2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_i32m2_m(...) __riscv_vsuxseg3ei32_v_i32m2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_i32m2_m(...) __riscv_vsuxseg4ei32_v_i32m2_m(__VA_ARGS__) -#define vsuxseg2ei32_v_i32m4_m(...) __riscv_vsuxseg2ei32_v_i32m4_m(__VA_ARGS__) -#define vsuxseg2ei64_v_i32mf2_m(...) __riscv_vsuxseg2ei64_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg3ei64_v_i32mf2_m(...) __riscv_vsuxseg3ei64_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg4ei64_v_i32mf2_m(...) __riscv_vsuxseg4ei64_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg5ei64_v_i32mf2_m(...) __riscv_vsuxseg5ei64_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg6ei64_v_i32mf2_m(...) __riscv_vsuxseg6ei64_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg7ei64_v_i32mf2_m(...) __riscv_vsuxseg7ei64_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg8ei64_v_i32mf2_m(...) __riscv_vsuxseg8ei64_v_i32mf2_m(__VA_ARGS__) -#define vsuxseg2ei64_v_i32m1_m(...) __riscv_vsuxseg2ei64_v_i32m1_m(__VA_ARGS__) -#define vsuxseg3ei64_v_i32m1_m(...) __riscv_vsuxseg3ei64_v_i32m1_m(__VA_ARGS__) -#define vsuxseg4ei64_v_i32m1_m(...) __riscv_vsuxseg4ei64_v_i32m1_m(__VA_ARGS__) -#define vsuxseg5ei64_v_i32m1_m(...) __riscv_vsuxseg5ei64_v_i32m1_m(__VA_ARGS__) -#define vsuxseg6ei64_v_i32m1_m(...) __riscv_vsuxseg6ei64_v_i32m1_m(__VA_ARGS__) -#define vsuxseg7ei64_v_i32m1_m(...) __riscv_vsuxseg7ei64_v_i32m1_m(__VA_ARGS__) -#define vsuxseg8ei64_v_i32m1_m(...) __riscv_vsuxseg8ei64_v_i32m1_m(__VA_ARGS__) -#define vsuxseg2ei64_v_i32m2_m(...) __riscv_vsuxseg2ei64_v_i32m2_m(__VA_ARGS__) -#define vsuxseg3ei64_v_i32m2_m(...) __riscv_vsuxseg3ei64_v_i32m2_m(__VA_ARGS__) -#define vsuxseg4ei64_v_i32m2_m(...) __riscv_vsuxseg4ei64_v_i32m2_m(__VA_ARGS__) -#define vsuxseg2ei64_v_i32m4_m(...) __riscv_vsuxseg2ei64_v_i32m4_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i64m1_m(...) __riscv_vsuxseg2ei8_v_i64m1_m(__VA_ARGS__) -#define vsuxseg3ei8_v_i64m1_m(...) __riscv_vsuxseg3ei8_v_i64m1_m(__VA_ARGS__) -#define vsuxseg4ei8_v_i64m1_m(...) __riscv_vsuxseg4ei8_v_i64m1_m(__VA_ARGS__) -#define vsuxseg5ei8_v_i64m1_m(...) __riscv_vsuxseg5ei8_v_i64m1_m(__VA_ARGS__) -#define vsuxseg6ei8_v_i64m1_m(...) __riscv_vsuxseg6ei8_v_i64m1_m(__VA_ARGS__) -#define vsuxseg7ei8_v_i64m1_m(...) __riscv_vsuxseg7ei8_v_i64m1_m(__VA_ARGS__) -#define vsuxseg8ei8_v_i64m1_m(...) __riscv_vsuxseg8ei8_v_i64m1_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i64m2_m(...) __riscv_vsuxseg2ei8_v_i64m2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_i64m2_m(...) __riscv_vsuxseg3ei8_v_i64m2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_i64m2_m(...) __riscv_vsuxseg4ei8_v_i64m2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_i64m4_m(...) __riscv_vsuxseg2ei8_v_i64m4_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i64m1_m(...) __riscv_vsuxseg2ei16_v_i64m1_m(__VA_ARGS__) -#define vsuxseg3ei16_v_i64m1_m(...) __riscv_vsuxseg3ei16_v_i64m1_m(__VA_ARGS__) -#define vsuxseg4ei16_v_i64m1_m(...) __riscv_vsuxseg4ei16_v_i64m1_m(__VA_ARGS__) -#define vsuxseg5ei16_v_i64m1_m(...) __riscv_vsuxseg5ei16_v_i64m1_m(__VA_ARGS__) -#define vsuxseg6ei16_v_i64m1_m(...) __riscv_vsuxseg6ei16_v_i64m1_m(__VA_ARGS__) -#define vsuxseg7ei16_v_i64m1_m(...) __riscv_vsuxseg7ei16_v_i64m1_m(__VA_ARGS__) -#define vsuxseg8ei16_v_i64m1_m(...) __riscv_vsuxseg8ei16_v_i64m1_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i64m2_m(...) __riscv_vsuxseg2ei16_v_i64m2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_i64m2_m(...) __riscv_vsuxseg3ei16_v_i64m2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_i64m2_m(...) __riscv_vsuxseg4ei16_v_i64m2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_i64m4_m(...) __riscv_vsuxseg2ei16_v_i64m4_m(__VA_ARGS__) -#define vsuxseg2ei32_v_i64m1_m(...) __riscv_vsuxseg2ei32_v_i64m1_m(__VA_ARGS__) -#define vsuxseg3ei32_v_i64m1_m(...) __riscv_vsuxseg3ei32_v_i64m1_m(__VA_ARGS__) -#define vsuxseg4ei32_v_i64m1_m(...) __riscv_vsuxseg4ei32_v_i64m1_m(__VA_ARGS__) -#define vsuxseg5ei32_v_i64m1_m(...) __riscv_vsuxseg5ei32_v_i64m1_m(__VA_ARGS__) -#define vsuxseg6ei32_v_i64m1_m(...) __riscv_vsuxseg6ei32_v_i64m1_m(__VA_ARGS__) -#define vsuxseg7ei32_v_i64m1_m(...) __riscv_vsuxseg7ei32_v_i64m1_m(__VA_ARGS__) -#define vsuxseg8ei32_v_i64m1_m(...) __riscv_vsuxseg8ei32_v_i64m1_m(__VA_ARGS__) -#define vsuxseg2ei32_v_i64m2_m(...) __riscv_vsuxseg2ei32_v_i64m2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_i64m2_m(...) __riscv_vsuxseg3ei32_v_i64m2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_i64m2_m(...) __riscv_vsuxseg4ei32_v_i64m2_m(__VA_ARGS__) -#define vsuxseg2ei32_v_i64m4_m(...) __riscv_vsuxseg2ei32_v_i64m4_m(__VA_ARGS__) -#define vsuxseg2ei64_v_i64m1_m(...) __riscv_vsuxseg2ei64_v_i64m1_m(__VA_ARGS__) -#define vsuxseg3ei64_v_i64m1_m(...) __riscv_vsuxseg3ei64_v_i64m1_m(__VA_ARGS__) -#define vsuxseg4ei64_v_i64m1_m(...) __riscv_vsuxseg4ei64_v_i64m1_m(__VA_ARGS__) -#define vsuxseg5ei64_v_i64m1_m(...) __riscv_vsuxseg5ei64_v_i64m1_m(__VA_ARGS__) -#define vsuxseg6ei64_v_i64m1_m(...) __riscv_vsuxseg6ei64_v_i64m1_m(__VA_ARGS__) -#define vsuxseg7ei64_v_i64m1_m(...) __riscv_vsuxseg7ei64_v_i64m1_m(__VA_ARGS__) -#define vsuxseg8ei64_v_i64m1_m(...) __riscv_vsuxseg8ei64_v_i64m1_m(__VA_ARGS__) -#define vsuxseg2ei64_v_i64m2_m(...) __riscv_vsuxseg2ei64_v_i64m2_m(__VA_ARGS__) -#define vsuxseg3ei64_v_i64m2_m(...) __riscv_vsuxseg3ei64_v_i64m2_m(__VA_ARGS__) -#define vsuxseg4ei64_v_i64m2_m(...) __riscv_vsuxseg4ei64_v_i64m2_m(__VA_ARGS__) -#define vsuxseg2ei64_v_i64m4_m(...) __riscv_vsuxseg2ei64_v_i64m4_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u8mf8_m(...) __riscv_vsoxseg2ei8_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg3ei8_v_u8mf8_m(...) __riscv_vsoxseg3ei8_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg4ei8_v_u8mf8_m(...) __riscv_vsoxseg4ei8_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg5ei8_v_u8mf8_m(...) __riscv_vsoxseg5ei8_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg6ei8_v_u8mf8_m(...) __riscv_vsoxseg6ei8_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg7ei8_v_u8mf8_m(...) __riscv_vsoxseg7ei8_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg8ei8_v_u8mf8_m(...) __riscv_vsoxseg8ei8_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u8mf4_m(...) __riscv_vsoxseg2ei8_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg3ei8_v_u8mf4_m(...) __riscv_vsoxseg3ei8_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg4ei8_v_u8mf4_m(...) __riscv_vsoxseg4ei8_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg5ei8_v_u8mf4_m(...) __riscv_vsoxseg5ei8_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg6ei8_v_u8mf4_m(...) __riscv_vsoxseg6ei8_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg7ei8_v_u8mf4_m(...) __riscv_vsoxseg7ei8_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg8ei8_v_u8mf4_m(...) __riscv_vsoxseg8ei8_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u8mf2_m(...) __riscv_vsoxseg2ei8_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_u8mf2_m(...) __riscv_vsoxseg3ei8_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_u8mf2_m(...) __riscv_vsoxseg4ei8_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg5ei8_v_u8mf2_m(...) __riscv_vsoxseg5ei8_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg6ei8_v_u8mf2_m(...) __riscv_vsoxseg6ei8_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg7ei8_v_u8mf2_m(...) __riscv_vsoxseg7ei8_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg8ei8_v_u8mf2_m(...) __riscv_vsoxseg8ei8_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u8m1_m(...) __riscv_vsoxseg2ei8_v_u8m1_m(__VA_ARGS__) -#define vsoxseg3ei8_v_u8m1_m(...) __riscv_vsoxseg3ei8_v_u8m1_m(__VA_ARGS__) -#define vsoxseg4ei8_v_u8m1_m(...) __riscv_vsoxseg4ei8_v_u8m1_m(__VA_ARGS__) -#define vsoxseg5ei8_v_u8m1_m(...) __riscv_vsoxseg5ei8_v_u8m1_m(__VA_ARGS__) -#define vsoxseg6ei8_v_u8m1_m(...) __riscv_vsoxseg6ei8_v_u8m1_m(__VA_ARGS__) -#define vsoxseg7ei8_v_u8m1_m(...) __riscv_vsoxseg7ei8_v_u8m1_m(__VA_ARGS__) -#define vsoxseg8ei8_v_u8m1_m(...) __riscv_vsoxseg8ei8_v_u8m1_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u8m2_m(...) __riscv_vsoxseg2ei8_v_u8m2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_u8m2_m(...) __riscv_vsoxseg3ei8_v_u8m2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_u8m2_m(...) __riscv_vsoxseg4ei8_v_u8m2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u8m4_m(...) __riscv_vsoxseg2ei8_v_u8m4_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u8mf8_m(...) __riscv_vsoxseg2ei16_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg3ei16_v_u8mf8_m(...) __riscv_vsoxseg3ei16_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg4ei16_v_u8mf8_m(...) __riscv_vsoxseg4ei16_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg5ei16_v_u8mf8_m(...) __riscv_vsoxseg5ei16_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg6ei16_v_u8mf8_m(...) __riscv_vsoxseg6ei16_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg7ei16_v_u8mf8_m(...) __riscv_vsoxseg7ei16_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg8ei16_v_u8mf8_m(...) __riscv_vsoxseg8ei16_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u8mf4_m(...) __riscv_vsoxseg2ei16_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg3ei16_v_u8mf4_m(...) __riscv_vsoxseg3ei16_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg4ei16_v_u8mf4_m(...) __riscv_vsoxseg4ei16_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg5ei16_v_u8mf4_m(...) __riscv_vsoxseg5ei16_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg6ei16_v_u8mf4_m(...) __riscv_vsoxseg6ei16_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg7ei16_v_u8mf4_m(...) __riscv_vsoxseg7ei16_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg8ei16_v_u8mf4_m(...) __riscv_vsoxseg8ei16_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u8mf2_m(...) __riscv_vsoxseg2ei16_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_u8mf2_m(...) __riscv_vsoxseg3ei16_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_u8mf2_m(...) __riscv_vsoxseg4ei16_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg5ei16_v_u8mf2_m(...) __riscv_vsoxseg5ei16_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg6ei16_v_u8mf2_m(...) __riscv_vsoxseg6ei16_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg7ei16_v_u8mf2_m(...) __riscv_vsoxseg7ei16_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg8ei16_v_u8mf2_m(...) __riscv_vsoxseg8ei16_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u8m1_m(...) __riscv_vsoxseg2ei16_v_u8m1_m(__VA_ARGS__) -#define vsoxseg3ei16_v_u8m1_m(...) __riscv_vsoxseg3ei16_v_u8m1_m(__VA_ARGS__) -#define vsoxseg4ei16_v_u8m1_m(...) __riscv_vsoxseg4ei16_v_u8m1_m(__VA_ARGS__) -#define vsoxseg5ei16_v_u8m1_m(...) __riscv_vsoxseg5ei16_v_u8m1_m(__VA_ARGS__) -#define vsoxseg6ei16_v_u8m1_m(...) __riscv_vsoxseg6ei16_v_u8m1_m(__VA_ARGS__) -#define vsoxseg7ei16_v_u8m1_m(...) __riscv_vsoxseg7ei16_v_u8m1_m(__VA_ARGS__) -#define vsoxseg8ei16_v_u8m1_m(...) __riscv_vsoxseg8ei16_v_u8m1_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u8m2_m(...) __riscv_vsoxseg2ei16_v_u8m2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_u8m2_m(...) __riscv_vsoxseg3ei16_v_u8m2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_u8m2_m(...) __riscv_vsoxseg4ei16_v_u8m2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u8m4_m(...) __riscv_vsoxseg2ei16_v_u8m4_m(__VA_ARGS__) -#define vsoxseg2ei32_v_u8mf8_m(...) __riscv_vsoxseg2ei32_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg3ei32_v_u8mf8_m(...) __riscv_vsoxseg3ei32_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg4ei32_v_u8mf8_m(...) __riscv_vsoxseg4ei32_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg5ei32_v_u8mf8_m(...) __riscv_vsoxseg5ei32_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg6ei32_v_u8mf8_m(...) __riscv_vsoxseg6ei32_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg7ei32_v_u8mf8_m(...) __riscv_vsoxseg7ei32_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg8ei32_v_u8mf8_m(...) __riscv_vsoxseg8ei32_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg2ei32_v_u8mf4_m(...) __riscv_vsoxseg2ei32_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg3ei32_v_u8mf4_m(...) __riscv_vsoxseg3ei32_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg4ei32_v_u8mf4_m(...) __riscv_vsoxseg4ei32_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg5ei32_v_u8mf4_m(...) __riscv_vsoxseg5ei32_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg6ei32_v_u8mf4_m(...) __riscv_vsoxseg6ei32_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg7ei32_v_u8mf4_m(...) __riscv_vsoxseg7ei32_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg8ei32_v_u8mf4_m(...) __riscv_vsoxseg8ei32_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg2ei32_v_u8mf2_m(...) __riscv_vsoxseg2ei32_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_u8mf2_m(...) __riscv_vsoxseg3ei32_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_u8mf2_m(...) __riscv_vsoxseg4ei32_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg5ei32_v_u8mf2_m(...) __riscv_vsoxseg5ei32_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg6ei32_v_u8mf2_m(...) __riscv_vsoxseg6ei32_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg7ei32_v_u8mf2_m(...) __riscv_vsoxseg7ei32_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg8ei32_v_u8mf2_m(...) __riscv_vsoxseg8ei32_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg2ei32_v_u8m1_m(...) __riscv_vsoxseg2ei32_v_u8m1_m(__VA_ARGS__) -#define vsoxseg3ei32_v_u8m1_m(...) __riscv_vsoxseg3ei32_v_u8m1_m(__VA_ARGS__) -#define vsoxseg4ei32_v_u8m1_m(...) __riscv_vsoxseg4ei32_v_u8m1_m(__VA_ARGS__) -#define vsoxseg5ei32_v_u8m1_m(...) __riscv_vsoxseg5ei32_v_u8m1_m(__VA_ARGS__) -#define vsoxseg6ei32_v_u8m1_m(...) __riscv_vsoxseg6ei32_v_u8m1_m(__VA_ARGS__) -#define vsoxseg7ei32_v_u8m1_m(...) __riscv_vsoxseg7ei32_v_u8m1_m(__VA_ARGS__) -#define vsoxseg8ei32_v_u8m1_m(...) __riscv_vsoxseg8ei32_v_u8m1_m(__VA_ARGS__) -#define vsoxseg2ei32_v_u8m2_m(...) __riscv_vsoxseg2ei32_v_u8m2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_u8m2_m(...) __riscv_vsoxseg3ei32_v_u8m2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_u8m2_m(...) __riscv_vsoxseg4ei32_v_u8m2_m(__VA_ARGS__) -#define vsoxseg2ei64_v_u8mf8_m(...) __riscv_vsoxseg2ei64_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg3ei64_v_u8mf8_m(...) __riscv_vsoxseg3ei64_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg4ei64_v_u8mf8_m(...) __riscv_vsoxseg4ei64_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg5ei64_v_u8mf8_m(...) __riscv_vsoxseg5ei64_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg6ei64_v_u8mf8_m(...) __riscv_vsoxseg6ei64_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg7ei64_v_u8mf8_m(...) __riscv_vsoxseg7ei64_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg8ei64_v_u8mf8_m(...) __riscv_vsoxseg8ei64_v_u8mf8_m(__VA_ARGS__) -#define vsoxseg2ei64_v_u8mf4_m(...) __riscv_vsoxseg2ei64_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg3ei64_v_u8mf4_m(...) __riscv_vsoxseg3ei64_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg4ei64_v_u8mf4_m(...) __riscv_vsoxseg4ei64_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg5ei64_v_u8mf4_m(...) __riscv_vsoxseg5ei64_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg6ei64_v_u8mf4_m(...) __riscv_vsoxseg6ei64_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg7ei64_v_u8mf4_m(...) __riscv_vsoxseg7ei64_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg8ei64_v_u8mf4_m(...) __riscv_vsoxseg8ei64_v_u8mf4_m(__VA_ARGS__) -#define vsoxseg2ei64_v_u8mf2_m(...) __riscv_vsoxseg2ei64_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg3ei64_v_u8mf2_m(...) __riscv_vsoxseg3ei64_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg4ei64_v_u8mf2_m(...) __riscv_vsoxseg4ei64_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg5ei64_v_u8mf2_m(...) __riscv_vsoxseg5ei64_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg6ei64_v_u8mf2_m(...) __riscv_vsoxseg6ei64_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg7ei64_v_u8mf2_m(...) __riscv_vsoxseg7ei64_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg8ei64_v_u8mf2_m(...) __riscv_vsoxseg8ei64_v_u8mf2_m(__VA_ARGS__) -#define vsoxseg2ei64_v_u8m1_m(...) __riscv_vsoxseg2ei64_v_u8m1_m(__VA_ARGS__) -#define vsoxseg3ei64_v_u8m1_m(...) __riscv_vsoxseg3ei64_v_u8m1_m(__VA_ARGS__) -#define vsoxseg4ei64_v_u8m1_m(...) __riscv_vsoxseg4ei64_v_u8m1_m(__VA_ARGS__) -#define vsoxseg5ei64_v_u8m1_m(...) __riscv_vsoxseg5ei64_v_u8m1_m(__VA_ARGS__) -#define vsoxseg6ei64_v_u8m1_m(...) __riscv_vsoxseg6ei64_v_u8m1_m(__VA_ARGS__) -#define vsoxseg7ei64_v_u8m1_m(...) __riscv_vsoxseg7ei64_v_u8m1_m(__VA_ARGS__) -#define vsoxseg8ei64_v_u8m1_m(...) __riscv_vsoxseg8ei64_v_u8m1_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u16mf4_m(...) __riscv_vsoxseg2ei8_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg3ei8_v_u16mf4_m(...) __riscv_vsoxseg3ei8_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg4ei8_v_u16mf4_m(...) __riscv_vsoxseg4ei8_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg5ei8_v_u16mf4_m(...) __riscv_vsoxseg5ei8_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg6ei8_v_u16mf4_m(...) __riscv_vsoxseg6ei8_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg7ei8_v_u16mf4_m(...) __riscv_vsoxseg7ei8_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg8ei8_v_u16mf4_m(...) __riscv_vsoxseg8ei8_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u16mf2_m(...) __riscv_vsoxseg2ei8_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_u16mf2_m(...) __riscv_vsoxseg3ei8_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_u16mf2_m(...) __riscv_vsoxseg4ei8_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg5ei8_v_u16mf2_m(...) __riscv_vsoxseg5ei8_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg6ei8_v_u16mf2_m(...) __riscv_vsoxseg6ei8_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg7ei8_v_u16mf2_m(...) __riscv_vsoxseg7ei8_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg8ei8_v_u16mf2_m(...) __riscv_vsoxseg8ei8_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u16m1_m(...) __riscv_vsoxseg2ei8_v_u16m1_m(__VA_ARGS__) -#define vsoxseg3ei8_v_u16m1_m(...) __riscv_vsoxseg3ei8_v_u16m1_m(__VA_ARGS__) -#define vsoxseg4ei8_v_u16m1_m(...) __riscv_vsoxseg4ei8_v_u16m1_m(__VA_ARGS__) -#define vsoxseg5ei8_v_u16m1_m(...) __riscv_vsoxseg5ei8_v_u16m1_m(__VA_ARGS__) -#define vsoxseg6ei8_v_u16m1_m(...) __riscv_vsoxseg6ei8_v_u16m1_m(__VA_ARGS__) -#define vsoxseg7ei8_v_u16m1_m(...) __riscv_vsoxseg7ei8_v_u16m1_m(__VA_ARGS__) -#define vsoxseg8ei8_v_u16m1_m(...) __riscv_vsoxseg8ei8_v_u16m1_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u16m2_m(...) __riscv_vsoxseg2ei8_v_u16m2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_u16m2_m(...) __riscv_vsoxseg3ei8_v_u16m2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_u16m2_m(...) __riscv_vsoxseg4ei8_v_u16m2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u16m4_m(...) __riscv_vsoxseg2ei8_v_u16m4_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u16mf4_m(...) __riscv_vsoxseg2ei16_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg3ei16_v_u16mf4_m(...) __riscv_vsoxseg3ei16_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg4ei16_v_u16mf4_m(...) __riscv_vsoxseg4ei16_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg5ei16_v_u16mf4_m(...) __riscv_vsoxseg5ei16_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg6ei16_v_u16mf4_m(...) __riscv_vsoxseg6ei16_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg7ei16_v_u16mf4_m(...) __riscv_vsoxseg7ei16_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg8ei16_v_u16mf4_m(...) __riscv_vsoxseg8ei16_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u16mf2_m(...) __riscv_vsoxseg2ei16_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_u16mf2_m(...) __riscv_vsoxseg3ei16_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_u16mf2_m(...) __riscv_vsoxseg4ei16_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg5ei16_v_u16mf2_m(...) __riscv_vsoxseg5ei16_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg6ei16_v_u16mf2_m(...) __riscv_vsoxseg6ei16_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg7ei16_v_u16mf2_m(...) __riscv_vsoxseg7ei16_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg8ei16_v_u16mf2_m(...) __riscv_vsoxseg8ei16_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u16m1_m(...) __riscv_vsoxseg2ei16_v_u16m1_m(__VA_ARGS__) -#define vsoxseg3ei16_v_u16m1_m(...) __riscv_vsoxseg3ei16_v_u16m1_m(__VA_ARGS__) -#define vsoxseg4ei16_v_u16m1_m(...) __riscv_vsoxseg4ei16_v_u16m1_m(__VA_ARGS__) -#define vsoxseg5ei16_v_u16m1_m(...) __riscv_vsoxseg5ei16_v_u16m1_m(__VA_ARGS__) -#define vsoxseg6ei16_v_u16m1_m(...) __riscv_vsoxseg6ei16_v_u16m1_m(__VA_ARGS__) -#define vsoxseg7ei16_v_u16m1_m(...) __riscv_vsoxseg7ei16_v_u16m1_m(__VA_ARGS__) -#define vsoxseg8ei16_v_u16m1_m(...) __riscv_vsoxseg8ei16_v_u16m1_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u16m2_m(...) __riscv_vsoxseg2ei16_v_u16m2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_u16m2_m(...) __riscv_vsoxseg3ei16_v_u16m2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_u16m2_m(...) __riscv_vsoxseg4ei16_v_u16m2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u16m4_m(...) __riscv_vsoxseg2ei16_v_u16m4_m(__VA_ARGS__) -#define vsoxseg2ei32_v_u16mf4_m(...) __riscv_vsoxseg2ei32_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg3ei32_v_u16mf4_m(...) __riscv_vsoxseg3ei32_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg4ei32_v_u16mf4_m(...) __riscv_vsoxseg4ei32_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg5ei32_v_u16mf4_m(...) __riscv_vsoxseg5ei32_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg6ei32_v_u16mf4_m(...) __riscv_vsoxseg6ei32_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg7ei32_v_u16mf4_m(...) __riscv_vsoxseg7ei32_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg8ei32_v_u16mf4_m(...) __riscv_vsoxseg8ei32_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg2ei32_v_u16mf2_m(...) __riscv_vsoxseg2ei32_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_u16mf2_m(...) __riscv_vsoxseg3ei32_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_u16mf2_m(...) __riscv_vsoxseg4ei32_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg5ei32_v_u16mf2_m(...) __riscv_vsoxseg5ei32_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg6ei32_v_u16mf2_m(...) __riscv_vsoxseg6ei32_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg7ei32_v_u16mf2_m(...) __riscv_vsoxseg7ei32_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg8ei32_v_u16mf2_m(...) __riscv_vsoxseg8ei32_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg2ei32_v_u16m1_m(...) __riscv_vsoxseg2ei32_v_u16m1_m(__VA_ARGS__) -#define vsoxseg3ei32_v_u16m1_m(...) __riscv_vsoxseg3ei32_v_u16m1_m(__VA_ARGS__) -#define vsoxseg4ei32_v_u16m1_m(...) __riscv_vsoxseg4ei32_v_u16m1_m(__VA_ARGS__) -#define vsoxseg5ei32_v_u16m1_m(...) __riscv_vsoxseg5ei32_v_u16m1_m(__VA_ARGS__) -#define vsoxseg6ei32_v_u16m1_m(...) __riscv_vsoxseg6ei32_v_u16m1_m(__VA_ARGS__) -#define vsoxseg7ei32_v_u16m1_m(...) __riscv_vsoxseg7ei32_v_u16m1_m(__VA_ARGS__) -#define vsoxseg8ei32_v_u16m1_m(...) __riscv_vsoxseg8ei32_v_u16m1_m(__VA_ARGS__) -#define vsoxseg2ei32_v_u16m2_m(...) __riscv_vsoxseg2ei32_v_u16m2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_u16m2_m(...) __riscv_vsoxseg3ei32_v_u16m2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_u16m2_m(...) __riscv_vsoxseg4ei32_v_u16m2_m(__VA_ARGS__) -#define vsoxseg2ei32_v_u16m4_m(...) __riscv_vsoxseg2ei32_v_u16m4_m(__VA_ARGS__) -#define vsoxseg2ei64_v_u16mf4_m(...) __riscv_vsoxseg2ei64_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg3ei64_v_u16mf4_m(...) __riscv_vsoxseg3ei64_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg4ei64_v_u16mf4_m(...) __riscv_vsoxseg4ei64_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg5ei64_v_u16mf4_m(...) __riscv_vsoxseg5ei64_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg6ei64_v_u16mf4_m(...) __riscv_vsoxseg6ei64_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg7ei64_v_u16mf4_m(...) __riscv_vsoxseg7ei64_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg8ei64_v_u16mf4_m(...) __riscv_vsoxseg8ei64_v_u16mf4_m(__VA_ARGS__) -#define vsoxseg2ei64_v_u16mf2_m(...) __riscv_vsoxseg2ei64_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg3ei64_v_u16mf2_m(...) __riscv_vsoxseg3ei64_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg4ei64_v_u16mf2_m(...) __riscv_vsoxseg4ei64_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg5ei64_v_u16mf2_m(...) __riscv_vsoxseg5ei64_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg6ei64_v_u16mf2_m(...) __riscv_vsoxseg6ei64_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg7ei64_v_u16mf2_m(...) __riscv_vsoxseg7ei64_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg8ei64_v_u16mf2_m(...) __riscv_vsoxseg8ei64_v_u16mf2_m(__VA_ARGS__) -#define vsoxseg2ei64_v_u16m1_m(...) __riscv_vsoxseg2ei64_v_u16m1_m(__VA_ARGS__) -#define vsoxseg3ei64_v_u16m1_m(...) __riscv_vsoxseg3ei64_v_u16m1_m(__VA_ARGS__) -#define vsoxseg4ei64_v_u16m1_m(...) __riscv_vsoxseg4ei64_v_u16m1_m(__VA_ARGS__) -#define vsoxseg5ei64_v_u16m1_m(...) __riscv_vsoxseg5ei64_v_u16m1_m(__VA_ARGS__) -#define vsoxseg6ei64_v_u16m1_m(...) __riscv_vsoxseg6ei64_v_u16m1_m(__VA_ARGS__) -#define vsoxseg7ei64_v_u16m1_m(...) __riscv_vsoxseg7ei64_v_u16m1_m(__VA_ARGS__) -#define vsoxseg8ei64_v_u16m1_m(...) __riscv_vsoxseg8ei64_v_u16m1_m(__VA_ARGS__) -#define vsoxseg2ei64_v_u16m2_m(...) __riscv_vsoxseg2ei64_v_u16m2_m(__VA_ARGS__) -#define vsoxseg3ei64_v_u16m2_m(...) __riscv_vsoxseg3ei64_v_u16m2_m(__VA_ARGS__) -#define vsoxseg4ei64_v_u16m2_m(...) __riscv_vsoxseg4ei64_v_u16m2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u32mf2_m(...) __riscv_vsoxseg2ei8_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_u32mf2_m(...) __riscv_vsoxseg3ei8_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_u32mf2_m(...) __riscv_vsoxseg4ei8_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg5ei8_v_u32mf2_m(...) __riscv_vsoxseg5ei8_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg6ei8_v_u32mf2_m(...) __riscv_vsoxseg6ei8_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg7ei8_v_u32mf2_m(...) __riscv_vsoxseg7ei8_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg8ei8_v_u32mf2_m(...) __riscv_vsoxseg8ei8_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u32m1_m(...) __riscv_vsoxseg2ei8_v_u32m1_m(__VA_ARGS__) -#define vsoxseg3ei8_v_u32m1_m(...) __riscv_vsoxseg3ei8_v_u32m1_m(__VA_ARGS__) -#define vsoxseg4ei8_v_u32m1_m(...) __riscv_vsoxseg4ei8_v_u32m1_m(__VA_ARGS__) -#define vsoxseg5ei8_v_u32m1_m(...) __riscv_vsoxseg5ei8_v_u32m1_m(__VA_ARGS__) -#define vsoxseg6ei8_v_u32m1_m(...) __riscv_vsoxseg6ei8_v_u32m1_m(__VA_ARGS__) -#define vsoxseg7ei8_v_u32m1_m(...) __riscv_vsoxseg7ei8_v_u32m1_m(__VA_ARGS__) -#define vsoxseg8ei8_v_u32m1_m(...) __riscv_vsoxseg8ei8_v_u32m1_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u32m2_m(...) __riscv_vsoxseg2ei8_v_u32m2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_u32m2_m(...) __riscv_vsoxseg3ei8_v_u32m2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_u32m2_m(...) __riscv_vsoxseg4ei8_v_u32m2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u32m4_m(...) __riscv_vsoxseg2ei8_v_u32m4_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u32mf2_m(...) __riscv_vsoxseg2ei16_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_u32mf2_m(...) __riscv_vsoxseg3ei16_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_u32mf2_m(...) __riscv_vsoxseg4ei16_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg5ei16_v_u32mf2_m(...) __riscv_vsoxseg5ei16_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg6ei16_v_u32mf2_m(...) __riscv_vsoxseg6ei16_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg7ei16_v_u32mf2_m(...) __riscv_vsoxseg7ei16_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg8ei16_v_u32mf2_m(...) __riscv_vsoxseg8ei16_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u32m1_m(...) __riscv_vsoxseg2ei16_v_u32m1_m(__VA_ARGS__) -#define vsoxseg3ei16_v_u32m1_m(...) __riscv_vsoxseg3ei16_v_u32m1_m(__VA_ARGS__) -#define vsoxseg4ei16_v_u32m1_m(...) __riscv_vsoxseg4ei16_v_u32m1_m(__VA_ARGS__) -#define vsoxseg5ei16_v_u32m1_m(...) __riscv_vsoxseg5ei16_v_u32m1_m(__VA_ARGS__) -#define vsoxseg6ei16_v_u32m1_m(...) __riscv_vsoxseg6ei16_v_u32m1_m(__VA_ARGS__) -#define vsoxseg7ei16_v_u32m1_m(...) __riscv_vsoxseg7ei16_v_u32m1_m(__VA_ARGS__) -#define vsoxseg8ei16_v_u32m1_m(...) __riscv_vsoxseg8ei16_v_u32m1_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u32m2_m(...) __riscv_vsoxseg2ei16_v_u32m2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_u32m2_m(...) __riscv_vsoxseg3ei16_v_u32m2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_u32m2_m(...) __riscv_vsoxseg4ei16_v_u32m2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u32m4_m(...) __riscv_vsoxseg2ei16_v_u32m4_m(__VA_ARGS__) -#define vsoxseg2ei32_v_u32mf2_m(...) __riscv_vsoxseg2ei32_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_u32mf2_m(...) __riscv_vsoxseg3ei32_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_u32mf2_m(...) __riscv_vsoxseg4ei32_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg5ei32_v_u32mf2_m(...) __riscv_vsoxseg5ei32_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg6ei32_v_u32mf2_m(...) __riscv_vsoxseg6ei32_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg7ei32_v_u32mf2_m(...) __riscv_vsoxseg7ei32_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg8ei32_v_u32mf2_m(...) __riscv_vsoxseg8ei32_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg2ei32_v_u32m1_m(...) __riscv_vsoxseg2ei32_v_u32m1_m(__VA_ARGS__) -#define vsoxseg3ei32_v_u32m1_m(...) __riscv_vsoxseg3ei32_v_u32m1_m(__VA_ARGS__) -#define vsoxseg4ei32_v_u32m1_m(...) __riscv_vsoxseg4ei32_v_u32m1_m(__VA_ARGS__) -#define vsoxseg5ei32_v_u32m1_m(...) __riscv_vsoxseg5ei32_v_u32m1_m(__VA_ARGS__) -#define vsoxseg6ei32_v_u32m1_m(...) __riscv_vsoxseg6ei32_v_u32m1_m(__VA_ARGS__) -#define vsoxseg7ei32_v_u32m1_m(...) __riscv_vsoxseg7ei32_v_u32m1_m(__VA_ARGS__) -#define vsoxseg8ei32_v_u32m1_m(...) __riscv_vsoxseg8ei32_v_u32m1_m(__VA_ARGS__) -#define vsoxseg2ei32_v_u32m2_m(...) __riscv_vsoxseg2ei32_v_u32m2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_u32m2_m(...) __riscv_vsoxseg3ei32_v_u32m2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_u32m2_m(...) __riscv_vsoxseg4ei32_v_u32m2_m(__VA_ARGS__) -#define vsoxseg2ei32_v_u32m4_m(...) __riscv_vsoxseg2ei32_v_u32m4_m(__VA_ARGS__) -#define vsoxseg2ei64_v_u32mf2_m(...) __riscv_vsoxseg2ei64_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg3ei64_v_u32mf2_m(...) __riscv_vsoxseg3ei64_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg4ei64_v_u32mf2_m(...) __riscv_vsoxseg4ei64_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg5ei64_v_u32mf2_m(...) __riscv_vsoxseg5ei64_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg6ei64_v_u32mf2_m(...) __riscv_vsoxseg6ei64_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg7ei64_v_u32mf2_m(...) __riscv_vsoxseg7ei64_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg8ei64_v_u32mf2_m(...) __riscv_vsoxseg8ei64_v_u32mf2_m(__VA_ARGS__) -#define vsoxseg2ei64_v_u32m1_m(...) __riscv_vsoxseg2ei64_v_u32m1_m(__VA_ARGS__) -#define vsoxseg3ei64_v_u32m1_m(...) __riscv_vsoxseg3ei64_v_u32m1_m(__VA_ARGS__) -#define vsoxseg4ei64_v_u32m1_m(...) __riscv_vsoxseg4ei64_v_u32m1_m(__VA_ARGS__) -#define vsoxseg5ei64_v_u32m1_m(...) __riscv_vsoxseg5ei64_v_u32m1_m(__VA_ARGS__) -#define vsoxseg6ei64_v_u32m1_m(...) __riscv_vsoxseg6ei64_v_u32m1_m(__VA_ARGS__) -#define vsoxseg7ei64_v_u32m1_m(...) __riscv_vsoxseg7ei64_v_u32m1_m(__VA_ARGS__) -#define vsoxseg8ei64_v_u32m1_m(...) __riscv_vsoxseg8ei64_v_u32m1_m(__VA_ARGS__) -#define vsoxseg2ei64_v_u32m2_m(...) __riscv_vsoxseg2ei64_v_u32m2_m(__VA_ARGS__) -#define vsoxseg3ei64_v_u32m2_m(...) __riscv_vsoxseg3ei64_v_u32m2_m(__VA_ARGS__) -#define vsoxseg4ei64_v_u32m2_m(...) __riscv_vsoxseg4ei64_v_u32m2_m(__VA_ARGS__) -#define vsoxseg2ei64_v_u32m4_m(...) __riscv_vsoxseg2ei64_v_u32m4_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u64m1_m(...) __riscv_vsoxseg2ei8_v_u64m1_m(__VA_ARGS__) -#define vsoxseg3ei8_v_u64m1_m(...) __riscv_vsoxseg3ei8_v_u64m1_m(__VA_ARGS__) -#define vsoxseg4ei8_v_u64m1_m(...) __riscv_vsoxseg4ei8_v_u64m1_m(__VA_ARGS__) -#define vsoxseg5ei8_v_u64m1_m(...) __riscv_vsoxseg5ei8_v_u64m1_m(__VA_ARGS__) -#define vsoxseg6ei8_v_u64m1_m(...) __riscv_vsoxseg6ei8_v_u64m1_m(__VA_ARGS__) -#define vsoxseg7ei8_v_u64m1_m(...) __riscv_vsoxseg7ei8_v_u64m1_m(__VA_ARGS__) -#define vsoxseg8ei8_v_u64m1_m(...) __riscv_vsoxseg8ei8_v_u64m1_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u64m2_m(...) __riscv_vsoxseg2ei8_v_u64m2_m(__VA_ARGS__) -#define vsoxseg3ei8_v_u64m2_m(...) __riscv_vsoxseg3ei8_v_u64m2_m(__VA_ARGS__) -#define vsoxseg4ei8_v_u64m2_m(...) __riscv_vsoxseg4ei8_v_u64m2_m(__VA_ARGS__) -#define vsoxseg2ei8_v_u64m4_m(...) __riscv_vsoxseg2ei8_v_u64m4_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u64m1_m(...) __riscv_vsoxseg2ei16_v_u64m1_m(__VA_ARGS__) -#define vsoxseg3ei16_v_u64m1_m(...) __riscv_vsoxseg3ei16_v_u64m1_m(__VA_ARGS__) -#define vsoxseg4ei16_v_u64m1_m(...) __riscv_vsoxseg4ei16_v_u64m1_m(__VA_ARGS__) -#define vsoxseg5ei16_v_u64m1_m(...) __riscv_vsoxseg5ei16_v_u64m1_m(__VA_ARGS__) -#define vsoxseg6ei16_v_u64m1_m(...) __riscv_vsoxseg6ei16_v_u64m1_m(__VA_ARGS__) -#define vsoxseg7ei16_v_u64m1_m(...) __riscv_vsoxseg7ei16_v_u64m1_m(__VA_ARGS__) -#define vsoxseg8ei16_v_u64m1_m(...) __riscv_vsoxseg8ei16_v_u64m1_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u64m2_m(...) __riscv_vsoxseg2ei16_v_u64m2_m(__VA_ARGS__) -#define vsoxseg3ei16_v_u64m2_m(...) __riscv_vsoxseg3ei16_v_u64m2_m(__VA_ARGS__) -#define vsoxseg4ei16_v_u64m2_m(...) __riscv_vsoxseg4ei16_v_u64m2_m(__VA_ARGS__) -#define vsoxseg2ei16_v_u64m4_m(...) __riscv_vsoxseg2ei16_v_u64m4_m(__VA_ARGS__) -#define vsoxseg2ei32_v_u64m1_m(...) __riscv_vsoxseg2ei32_v_u64m1_m(__VA_ARGS__) -#define vsoxseg3ei32_v_u64m1_m(...) __riscv_vsoxseg3ei32_v_u64m1_m(__VA_ARGS__) -#define vsoxseg4ei32_v_u64m1_m(...) __riscv_vsoxseg4ei32_v_u64m1_m(__VA_ARGS__) -#define vsoxseg5ei32_v_u64m1_m(...) __riscv_vsoxseg5ei32_v_u64m1_m(__VA_ARGS__) -#define vsoxseg6ei32_v_u64m1_m(...) __riscv_vsoxseg6ei32_v_u64m1_m(__VA_ARGS__) -#define vsoxseg7ei32_v_u64m1_m(...) __riscv_vsoxseg7ei32_v_u64m1_m(__VA_ARGS__) -#define vsoxseg8ei32_v_u64m1_m(...) __riscv_vsoxseg8ei32_v_u64m1_m(__VA_ARGS__) -#define vsoxseg2ei32_v_u64m2_m(...) __riscv_vsoxseg2ei32_v_u64m2_m(__VA_ARGS__) -#define vsoxseg3ei32_v_u64m2_m(...) __riscv_vsoxseg3ei32_v_u64m2_m(__VA_ARGS__) -#define vsoxseg4ei32_v_u64m2_m(...) __riscv_vsoxseg4ei32_v_u64m2_m(__VA_ARGS__) -#define vsoxseg2ei32_v_u64m4_m(...) __riscv_vsoxseg2ei32_v_u64m4_m(__VA_ARGS__) -#define vsoxseg2ei64_v_u64m1_m(...) __riscv_vsoxseg2ei64_v_u64m1_m(__VA_ARGS__) -#define vsoxseg3ei64_v_u64m1_m(...) __riscv_vsoxseg3ei64_v_u64m1_m(__VA_ARGS__) -#define vsoxseg4ei64_v_u64m1_m(...) __riscv_vsoxseg4ei64_v_u64m1_m(__VA_ARGS__) -#define vsoxseg5ei64_v_u64m1_m(...) __riscv_vsoxseg5ei64_v_u64m1_m(__VA_ARGS__) -#define vsoxseg6ei64_v_u64m1_m(...) __riscv_vsoxseg6ei64_v_u64m1_m(__VA_ARGS__) -#define vsoxseg7ei64_v_u64m1_m(...) __riscv_vsoxseg7ei64_v_u64m1_m(__VA_ARGS__) -#define vsoxseg8ei64_v_u64m1_m(...) __riscv_vsoxseg8ei64_v_u64m1_m(__VA_ARGS__) -#define vsoxseg2ei64_v_u64m2_m(...) __riscv_vsoxseg2ei64_v_u64m2_m(__VA_ARGS__) -#define vsoxseg3ei64_v_u64m2_m(...) __riscv_vsoxseg3ei64_v_u64m2_m(__VA_ARGS__) -#define vsoxseg4ei64_v_u64m2_m(...) __riscv_vsoxseg4ei64_v_u64m2_m(__VA_ARGS__) -#define vsoxseg2ei64_v_u64m4_m(...) __riscv_vsoxseg2ei64_v_u64m4_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u8mf8_m(...) __riscv_vsuxseg2ei8_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg3ei8_v_u8mf8_m(...) __riscv_vsuxseg3ei8_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg4ei8_v_u8mf8_m(...) __riscv_vsuxseg4ei8_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg5ei8_v_u8mf8_m(...) __riscv_vsuxseg5ei8_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg6ei8_v_u8mf8_m(...) __riscv_vsuxseg6ei8_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg7ei8_v_u8mf8_m(...) __riscv_vsuxseg7ei8_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg8ei8_v_u8mf8_m(...) __riscv_vsuxseg8ei8_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u8mf4_m(...) __riscv_vsuxseg2ei8_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg3ei8_v_u8mf4_m(...) __riscv_vsuxseg3ei8_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg4ei8_v_u8mf4_m(...) __riscv_vsuxseg4ei8_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg5ei8_v_u8mf4_m(...) __riscv_vsuxseg5ei8_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg6ei8_v_u8mf4_m(...) __riscv_vsuxseg6ei8_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg7ei8_v_u8mf4_m(...) __riscv_vsuxseg7ei8_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg8ei8_v_u8mf4_m(...) __riscv_vsuxseg8ei8_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u8mf2_m(...) __riscv_vsuxseg2ei8_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_u8mf2_m(...) __riscv_vsuxseg3ei8_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_u8mf2_m(...) __riscv_vsuxseg4ei8_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg5ei8_v_u8mf2_m(...) __riscv_vsuxseg5ei8_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg6ei8_v_u8mf2_m(...) __riscv_vsuxseg6ei8_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg7ei8_v_u8mf2_m(...) __riscv_vsuxseg7ei8_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg8ei8_v_u8mf2_m(...) __riscv_vsuxseg8ei8_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u8m1_m(...) __riscv_vsuxseg2ei8_v_u8m1_m(__VA_ARGS__) -#define vsuxseg3ei8_v_u8m1_m(...) __riscv_vsuxseg3ei8_v_u8m1_m(__VA_ARGS__) -#define vsuxseg4ei8_v_u8m1_m(...) __riscv_vsuxseg4ei8_v_u8m1_m(__VA_ARGS__) -#define vsuxseg5ei8_v_u8m1_m(...) __riscv_vsuxseg5ei8_v_u8m1_m(__VA_ARGS__) -#define vsuxseg6ei8_v_u8m1_m(...) __riscv_vsuxseg6ei8_v_u8m1_m(__VA_ARGS__) -#define vsuxseg7ei8_v_u8m1_m(...) __riscv_vsuxseg7ei8_v_u8m1_m(__VA_ARGS__) -#define vsuxseg8ei8_v_u8m1_m(...) __riscv_vsuxseg8ei8_v_u8m1_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u8m2_m(...) __riscv_vsuxseg2ei8_v_u8m2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_u8m2_m(...) __riscv_vsuxseg3ei8_v_u8m2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_u8m2_m(...) __riscv_vsuxseg4ei8_v_u8m2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u8m4_m(...) __riscv_vsuxseg2ei8_v_u8m4_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u8mf8_m(...) __riscv_vsuxseg2ei16_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg3ei16_v_u8mf8_m(...) __riscv_vsuxseg3ei16_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg4ei16_v_u8mf8_m(...) __riscv_vsuxseg4ei16_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg5ei16_v_u8mf8_m(...) __riscv_vsuxseg5ei16_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg6ei16_v_u8mf8_m(...) __riscv_vsuxseg6ei16_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg7ei16_v_u8mf8_m(...) __riscv_vsuxseg7ei16_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg8ei16_v_u8mf8_m(...) __riscv_vsuxseg8ei16_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u8mf4_m(...) __riscv_vsuxseg2ei16_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg3ei16_v_u8mf4_m(...) __riscv_vsuxseg3ei16_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg4ei16_v_u8mf4_m(...) __riscv_vsuxseg4ei16_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg5ei16_v_u8mf4_m(...) __riscv_vsuxseg5ei16_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg6ei16_v_u8mf4_m(...) __riscv_vsuxseg6ei16_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg7ei16_v_u8mf4_m(...) __riscv_vsuxseg7ei16_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg8ei16_v_u8mf4_m(...) __riscv_vsuxseg8ei16_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u8mf2_m(...) __riscv_vsuxseg2ei16_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_u8mf2_m(...) __riscv_vsuxseg3ei16_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_u8mf2_m(...) __riscv_vsuxseg4ei16_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg5ei16_v_u8mf2_m(...) __riscv_vsuxseg5ei16_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg6ei16_v_u8mf2_m(...) __riscv_vsuxseg6ei16_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg7ei16_v_u8mf2_m(...) __riscv_vsuxseg7ei16_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg8ei16_v_u8mf2_m(...) __riscv_vsuxseg8ei16_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u8m1_m(...) __riscv_vsuxseg2ei16_v_u8m1_m(__VA_ARGS__) -#define vsuxseg3ei16_v_u8m1_m(...) __riscv_vsuxseg3ei16_v_u8m1_m(__VA_ARGS__) -#define vsuxseg4ei16_v_u8m1_m(...) __riscv_vsuxseg4ei16_v_u8m1_m(__VA_ARGS__) -#define vsuxseg5ei16_v_u8m1_m(...) __riscv_vsuxseg5ei16_v_u8m1_m(__VA_ARGS__) -#define vsuxseg6ei16_v_u8m1_m(...) __riscv_vsuxseg6ei16_v_u8m1_m(__VA_ARGS__) -#define vsuxseg7ei16_v_u8m1_m(...) __riscv_vsuxseg7ei16_v_u8m1_m(__VA_ARGS__) -#define vsuxseg8ei16_v_u8m1_m(...) __riscv_vsuxseg8ei16_v_u8m1_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u8m2_m(...) __riscv_vsuxseg2ei16_v_u8m2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_u8m2_m(...) __riscv_vsuxseg3ei16_v_u8m2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_u8m2_m(...) __riscv_vsuxseg4ei16_v_u8m2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u8m4_m(...) __riscv_vsuxseg2ei16_v_u8m4_m(__VA_ARGS__) -#define vsuxseg2ei32_v_u8mf8_m(...) __riscv_vsuxseg2ei32_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg3ei32_v_u8mf8_m(...) __riscv_vsuxseg3ei32_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg4ei32_v_u8mf8_m(...) __riscv_vsuxseg4ei32_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg5ei32_v_u8mf8_m(...) __riscv_vsuxseg5ei32_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg6ei32_v_u8mf8_m(...) __riscv_vsuxseg6ei32_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg7ei32_v_u8mf8_m(...) __riscv_vsuxseg7ei32_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg8ei32_v_u8mf8_m(...) __riscv_vsuxseg8ei32_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg2ei32_v_u8mf4_m(...) __riscv_vsuxseg2ei32_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg3ei32_v_u8mf4_m(...) __riscv_vsuxseg3ei32_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg4ei32_v_u8mf4_m(...) __riscv_vsuxseg4ei32_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg5ei32_v_u8mf4_m(...) __riscv_vsuxseg5ei32_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg6ei32_v_u8mf4_m(...) __riscv_vsuxseg6ei32_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg7ei32_v_u8mf4_m(...) __riscv_vsuxseg7ei32_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg8ei32_v_u8mf4_m(...) __riscv_vsuxseg8ei32_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg2ei32_v_u8mf2_m(...) __riscv_vsuxseg2ei32_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_u8mf2_m(...) __riscv_vsuxseg3ei32_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_u8mf2_m(...) __riscv_vsuxseg4ei32_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg5ei32_v_u8mf2_m(...) __riscv_vsuxseg5ei32_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg6ei32_v_u8mf2_m(...) __riscv_vsuxseg6ei32_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg7ei32_v_u8mf2_m(...) __riscv_vsuxseg7ei32_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg8ei32_v_u8mf2_m(...) __riscv_vsuxseg8ei32_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg2ei32_v_u8m1_m(...) __riscv_vsuxseg2ei32_v_u8m1_m(__VA_ARGS__) -#define vsuxseg3ei32_v_u8m1_m(...) __riscv_vsuxseg3ei32_v_u8m1_m(__VA_ARGS__) -#define vsuxseg4ei32_v_u8m1_m(...) __riscv_vsuxseg4ei32_v_u8m1_m(__VA_ARGS__) -#define vsuxseg5ei32_v_u8m1_m(...) __riscv_vsuxseg5ei32_v_u8m1_m(__VA_ARGS__) -#define vsuxseg6ei32_v_u8m1_m(...) __riscv_vsuxseg6ei32_v_u8m1_m(__VA_ARGS__) -#define vsuxseg7ei32_v_u8m1_m(...) __riscv_vsuxseg7ei32_v_u8m1_m(__VA_ARGS__) -#define vsuxseg8ei32_v_u8m1_m(...) __riscv_vsuxseg8ei32_v_u8m1_m(__VA_ARGS__) -#define vsuxseg2ei32_v_u8m2_m(...) __riscv_vsuxseg2ei32_v_u8m2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_u8m2_m(...) __riscv_vsuxseg3ei32_v_u8m2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_u8m2_m(...) __riscv_vsuxseg4ei32_v_u8m2_m(__VA_ARGS__) -#define vsuxseg2ei64_v_u8mf8_m(...) __riscv_vsuxseg2ei64_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg3ei64_v_u8mf8_m(...) __riscv_vsuxseg3ei64_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg4ei64_v_u8mf8_m(...) __riscv_vsuxseg4ei64_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg5ei64_v_u8mf8_m(...) __riscv_vsuxseg5ei64_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg6ei64_v_u8mf8_m(...) __riscv_vsuxseg6ei64_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg7ei64_v_u8mf8_m(...) __riscv_vsuxseg7ei64_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg8ei64_v_u8mf8_m(...) __riscv_vsuxseg8ei64_v_u8mf8_m(__VA_ARGS__) -#define vsuxseg2ei64_v_u8mf4_m(...) __riscv_vsuxseg2ei64_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg3ei64_v_u8mf4_m(...) __riscv_vsuxseg3ei64_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg4ei64_v_u8mf4_m(...) __riscv_vsuxseg4ei64_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg5ei64_v_u8mf4_m(...) __riscv_vsuxseg5ei64_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg6ei64_v_u8mf4_m(...) __riscv_vsuxseg6ei64_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg7ei64_v_u8mf4_m(...) __riscv_vsuxseg7ei64_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg8ei64_v_u8mf4_m(...) __riscv_vsuxseg8ei64_v_u8mf4_m(__VA_ARGS__) -#define vsuxseg2ei64_v_u8mf2_m(...) __riscv_vsuxseg2ei64_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg3ei64_v_u8mf2_m(...) __riscv_vsuxseg3ei64_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg4ei64_v_u8mf2_m(...) __riscv_vsuxseg4ei64_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg5ei64_v_u8mf2_m(...) __riscv_vsuxseg5ei64_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg6ei64_v_u8mf2_m(...) __riscv_vsuxseg6ei64_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg7ei64_v_u8mf2_m(...) __riscv_vsuxseg7ei64_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg8ei64_v_u8mf2_m(...) __riscv_vsuxseg8ei64_v_u8mf2_m(__VA_ARGS__) -#define vsuxseg2ei64_v_u8m1_m(...) __riscv_vsuxseg2ei64_v_u8m1_m(__VA_ARGS__) -#define vsuxseg3ei64_v_u8m1_m(...) __riscv_vsuxseg3ei64_v_u8m1_m(__VA_ARGS__) -#define vsuxseg4ei64_v_u8m1_m(...) __riscv_vsuxseg4ei64_v_u8m1_m(__VA_ARGS__) -#define vsuxseg5ei64_v_u8m1_m(...) __riscv_vsuxseg5ei64_v_u8m1_m(__VA_ARGS__) -#define vsuxseg6ei64_v_u8m1_m(...) __riscv_vsuxseg6ei64_v_u8m1_m(__VA_ARGS__) -#define vsuxseg7ei64_v_u8m1_m(...) __riscv_vsuxseg7ei64_v_u8m1_m(__VA_ARGS__) -#define vsuxseg8ei64_v_u8m1_m(...) __riscv_vsuxseg8ei64_v_u8m1_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u16mf4_m(...) __riscv_vsuxseg2ei8_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg3ei8_v_u16mf4_m(...) __riscv_vsuxseg3ei8_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg4ei8_v_u16mf4_m(...) __riscv_vsuxseg4ei8_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg5ei8_v_u16mf4_m(...) __riscv_vsuxseg5ei8_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg6ei8_v_u16mf4_m(...) __riscv_vsuxseg6ei8_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg7ei8_v_u16mf4_m(...) __riscv_vsuxseg7ei8_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg8ei8_v_u16mf4_m(...) __riscv_vsuxseg8ei8_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u16mf2_m(...) __riscv_vsuxseg2ei8_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_u16mf2_m(...) __riscv_vsuxseg3ei8_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_u16mf2_m(...) __riscv_vsuxseg4ei8_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg5ei8_v_u16mf2_m(...) __riscv_vsuxseg5ei8_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg6ei8_v_u16mf2_m(...) __riscv_vsuxseg6ei8_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg7ei8_v_u16mf2_m(...) __riscv_vsuxseg7ei8_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg8ei8_v_u16mf2_m(...) __riscv_vsuxseg8ei8_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u16m1_m(...) __riscv_vsuxseg2ei8_v_u16m1_m(__VA_ARGS__) -#define vsuxseg3ei8_v_u16m1_m(...) __riscv_vsuxseg3ei8_v_u16m1_m(__VA_ARGS__) -#define vsuxseg4ei8_v_u16m1_m(...) __riscv_vsuxseg4ei8_v_u16m1_m(__VA_ARGS__) -#define vsuxseg5ei8_v_u16m1_m(...) __riscv_vsuxseg5ei8_v_u16m1_m(__VA_ARGS__) -#define vsuxseg6ei8_v_u16m1_m(...) __riscv_vsuxseg6ei8_v_u16m1_m(__VA_ARGS__) -#define vsuxseg7ei8_v_u16m1_m(...) __riscv_vsuxseg7ei8_v_u16m1_m(__VA_ARGS__) -#define vsuxseg8ei8_v_u16m1_m(...) __riscv_vsuxseg8ei8_v_u16m1_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u16m2_m(...) __riscv_vsuxseg2ei8_v_u16m2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_u16m2_m(...) __riscv_vsuxseg3ei8_v_u16m2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_u16m2_m(...) __riscv_vsuxseg4ei8_v_u16m2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u16m4_m(...) __riscv_vsuxseg2ei8_v_u16m4_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u16mf4_m(...) __riscv_vsuxseg2ei16_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg3ei16_v_u16mf4_m(...) __riscv_vsuxseg3ei16_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg4ei16_v_u16mf4_m(...) __riscv_vsuxseg4ei16_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg5ei16_v_u16mf4_m(...) __riscv_vsuxseg5ei16_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg6ei16_v_u16mf4_m(...) __riscv_vsuxseg6ei16_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg7ei16_v_u16mf4_m(...) __riscv_vsuxseg7ei16_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg8ei16_v_u16mf4_m(...) __riscv_vsuxseg8ei16_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u16mf2_m(...) __riscv_vsuxseg2ei16_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_u16mf2_m(...) __riscv_vsuxseg3ei16_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_u16mf2_m(...) __riscv_vsuxseg4ei16_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg5ei16_v_u16mf2_m(...) __riscv_vsuxseg5ei16_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg6ei16_v_u16mf2_m(...) __riscv_vsuxseg6ei16_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg7ei16_v_u16mf2_m(...) __riscv_vsuxseg7ei16_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg8ei16_v_u16mf2_m(...) __riscv_vsuxseg8ei16_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u16m1_m(...) __riscv_vsuxseg2ei16_v_u16m1_m(__VA_ARGS__) -#define vsuxseg3ei16_v_u16m1_m(...) __riscv_vsuxseg3ei16_v_u16m1_m(__VA_ARGS__) -#define vsuxseg4ei16_v_u16m1_m(...) __riscv_vsuxseg4ei16_v_u16m1_m(__VA_ARGS__) -#define vsuxseg5ei16_v_u16m1_m(...) __riscv_vsuxseg5ei16_v_u16m1_m(__VA_ARGS__) -#define vsuxseg6ei16_v_u16m1_m(...) __riscv_vsuxseg6ei16_v_u16m1_m(__VA_ARGS__) -#define vsuxseg7ei16_v_u16m1_m(...) __riscv_vsuxseg7ei16_v_u16m1_m(__VA_ARGS__) -#define vsuxseg8ei16_v_u16m1_m(...) __riscv_vsuxseg8ei16_v_u16m1_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u16m2_m(...) __riscv_vsuxseg2ei16_v_u16m2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_u16m2_m(...) __riscv_vsuxseg3ei16_v_u16m2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_u16m2_m(...) __riscv_vsuxseg4ei16_v_u16m2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u16m4_m(...) __riscv_vsuxseg2ei16_v_u16m4_m(__VA_ARGS__) -#define vsuxseg2ei32_v_u16mf4_m(...) __riscv_vsuxseg2ei32_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg3ei32_v_u16mf4_m(...) __riscv_vsuxseg3ei32_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg4ei32_v_u16mf4_m(...) __riscv_vsuxseg4ei32_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg5ei32_v_u16mf4_m(...) __riscv_vsuxseg5ei32_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg6ei32_v_u16mf4_m(...) __riscv_vsuxseg6ei32_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg7ei32_v_u16mf4_m(...) __riscv_vsuxseg7ei32_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg8ei32_v_u16mf4_m(...) __riscv_vsuxseg8ei32_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg2ei32_v_u16mf2_m(...) __riscv_vsuxseg2ei32_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_u16mf2_m(...) __riscv_vsuxseg3ei32_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_u16mf2_m(...) __riscv_vsuxseg4ei32_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg5ei32_v_u16mf2_m(...) __riscv_vsuxseg5ei32_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg6ei32_v_u16mf2_m(...) __riscv_vsuxseg6ei32_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg7ei32_v_u16mf2_m(...) __riscv_vsuxseg7ei32_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg8ei32_v_u16mf2_m(...) __riscv_vsuxseg8ei32_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg2ei32_v_u16m1_m(...) __riscv_vsuxseg2ei32_v_u16m1_m(__VA_ARGS__) -#define vsuxseg3ei32_v_u16m1_m(...) __riscv_vsuxseg3ei32_v_u16m1_m(__VA_ARGS__) -#define vsuxseg4ei32_v_u16m1_m(...) __riscv_vsuxseg4ei32_v_u16m1_m(__VA_ARGS__) -#define vsuxseg5ei32_v_u16m1_m(...) __riscv_vsuxseg5ei32_v_u16m1_m(__VA_ARGS__) -#define vsuxseg6ei32_v_u16m1_m(...) __riscv_vsuxseg6ei32_v_u16m1_m(__VA_ARGS__) -#define vsuxseg7ei32_v_u16m1_m(...) __riscv_vsuxseg7ei32_v_u16m1_m(__VA_ARGS__) -#define vsuxseg8ei32_v_u16m1_m(...) __riscv_vsuxseg8ei32_v_u16m1_m(__VA_ARGS__) -#define vsuxseg2ei32_v_u16m2_m(...) __riscv_vsuxseg2ei32_v_u16m2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_u16m2_m(...) __riscv_vsuxseg3ei32_v_u16m2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_u16m2_m(...) __riscv_vsuxseg4ei32_v_u16m2_m(__VA_ARGS__) -#define vsuxseg2ei32_v_u16m4_m(...) __riscv_vsuxseg2ei32_v_u16m4_m(__VA_ARGS__) -#define vsuxseg2ei64_v_u16mf4_m(...) __riscv_vsuxseg2ei64_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg3ei64_v_u16mf4_m(...) __riscv_vsuxseg3ei64_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg4ei64_v_u16mf4_m(...) __riscv_vsuxseg4ei64_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg5ei64_v_u16mf4_m(...) __riscv_vsuxseg5ei64_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg6ei64_v_u16mf4_m(...) __riscv_vsuxseg6ei64_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg7ei64_v_u16mf4_m(...) __riscv_vsuxseg7ei64_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg8ei64_v_u16mf4_m(...) __riscv_vsuxseg8ei64_v_u16mf4_m(__VA_ARGS__) -#define vsuxseg2ei64_v_u16mf2_m(...) __riscv_vsuxseg2ei64_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg3ei64_v_u16mf2_m(...) __riscv_vsuxseg3ei64_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg4ei64_v_u16mf2_m(...) __riscv_vsuxseg4ei64_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg5ei64_v_u16mf2_m(...) __riscv_vsuxseg5ei64_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg6ei64_v_u16mf2_m(...) __riscv_vsuxseg6ei64_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg7ei64_v_u16mf2_m(...) __riscv_vsuxseg7ei64_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg8ei64_v_u16mf2_m(...) __riscv_vsuxseg8ei64_v_u16mf2_m(__VA_ARGS__) -#define vsuxseg2ei64_v_u16m1_m(...) __riscv_vsuxseg2ei64_v_u16m1_m(__VA_ARGS__) -#define vsuxseg3ei64_v_u16m1_m(...) __riscv_vsuxseg3ei64_v_u16m1_m(__VA_ARGS__) -#define vsuxseg4ei64_v_u16m1_m(...) __riscv_vsuxseg4ei64_v_u16m1_m(__VA_ARGS__) -#define vsuxseg5ei64_v_u16m1_m(...) __riscv_vsuxseg5ei64_v_u16m1_m(__VA_ARGS__) -#define vsuxseg6ei64_v_u16m1_m(...) __riscv_vsuxseg6ei64_v_u16m1_m(__VA_ARGS__) -#define vsuxseg7ei64_v_u16m1_m(...) __riscv_vsuxseg7ei64_v_u16m1_m(__VA_ARGS__) -#define vsuxseg8ei64_v_u16m1_m(...) __riscv_vsuxseg8ei64_v_u16m1_m(__VA_ARGS__) -#define vsuxseg2ei64_v_u16m2_m(...) __riscv_vsuxseg2ei64_v_u16m2_m(__VA_ARGS__) -#define vsuxseg3ei64_v_u16m2_m(...) __riscv_vsuxseg3ei64_v_u16m2_m(__VA_ARGS__) -#define vsuxseg4ei64_v_u16m2_m(...) __riscv_vsuxseg4ei64_v_u16m2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u32mf2_m(...) __riscv_vsuxseg2ei8_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_u32mf2_m(...) __riscv_vsuxseg3ei8_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_u32mf2_m(...) __riscv_vsuxseg4ei8_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg5ei8_v_u32mf2_m(...) __riscv_vsuxseg5ei8_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg6ei8_v_u32mf2_m(...) __riscv_vsuxseg6ei8_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg7ei8_v_u32mf2_m(...) __riscv_vsuxseg7ei8_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg8ei8_v_u32mf2_m(...) __riscv_vsuxseg8ei8_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u32m1_m(...) __riscv_vsuxseg2ei8_v_u32m1_m(__VA_ARGS__) -#define vsuxseg3ei8_v_u32m1_m(...) __riscv_vsuxseg3ei8_v_u32m1_m(__VA_ARGS__) -#define vsuxseg4ei8_v_u32m1_m(...) __riscv_vsuxseg4ei8_v_u32m1_m(__VA_ARGS__) -#define vsuxseg5ei8_v_u32m1_m(...) __riscv_vsuxseg5ei8_v_u32m1_m(__VA_ARGS__) -#define vsuxseg6ei8_v_u32m1_m(...) __riscv_vsuxseg6ei8_v_u32m1_m(__VA_ARGS__) -#define vsuxseg7ei8_v_u32m1_m(...) __riscv_vsuxseg7ei8_v_u32m1_m(__VA_ARGS__) -#define vsuxseg8ei8_v_u32m1_m(...) __riscv_vsuxseg8ei8_v_u32m1_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u32m2_m(...) __riscv_vsuxseg2ei8_v_u32m2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_u32m2_m(...) __riscv_vsuxseg3ei8_v_u32m2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_u32m2_m(...) __riscv_vsuxseg4ei8_v_u32m2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u32m4_m(...) __riscv_vsuxseg2ei8_v_u32m4_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u32mf2_m(...) __riscv_vsuxseg2ei16_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_u32mf2_m(...) __riscv_vsuxseg3ei16_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_u32mf2_m(...) __riscv_vsuxseg4ei16_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg5ei16_v_u32mf2_m(...) __riscv_vsuxseg5ei16_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg6ei16_v_u32mf2_m(...) __riscv_vsuxseg6ei16_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg7ei16_v_u32mf2_m(...) __riscv_vsuxseg7ei16_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg8ei16_v_u32mf2_m(...) __riscv_vsuxseg8ei16_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u32m1_m(...) __riscv_vsuxseg2ei16_v_u32m1_m(__VA_ARGS__) -#define vsuxseg3ei16_v_u32m1_m(...) __riscv_vsuxseg3ei16_v_u32m1_m(__VA_ARGS__) -#define vsuxseg4ei16_v_u32m1_m(...) __riscv_vsuxseg4ei16_v_u32m1_m(__VA_ARGS__) -#define vsuxseg5ei16_v_u32m1_m(...) __riscv_vsuxseg5ei16_v_u32m1_m(__VA_ARGS__) -#define vsuxseg6ei16_v_u32m1_m(...) __riscv_vsuxseg6ei16_v_u32m1_m(__VA_ARGS__) -#define vsuxseg7ei16_v_u32m1_m(...) __riscv_vsuxseg7ei16_v_u32m1_m(__VA_ARGS__) -#define vsuxseg8ei16_v_u32m1_m(...) __riscv_vsuxseg8ei16_v_u32m1_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u32m2_m(...) __riscv_vsuxseg2ei16_v_u32m2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_u32m2_m(...) __riscv_vsuxseg3ei16_v_u32m2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_u32m2_m(...) __riscv_vsuxseg4ei16_v_u32m2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u32m4_m(...) __riscv_vsuxseg2ei16_v_u32m4_m(__VA_ARGS__) -#define vsuxseg2ei32_v_u32mf2_m(...) __riscv_vsuxseg2ei32_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_u32mf2_m(...) __riscv_vsuxseg3ei32_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_u32mf2_m(...) __riscv_vsuxseg4ei32_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg5ei32_v_u32mf2_m(...) __riscv_vsuxseg5ei32_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg6ei32_v_u32mf2_m(...) __riscv_vsuxseg6ei32_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg7ei32_v_u32mf2_m(...) __riscv_vsuxseg7ei32_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg8ei32_v_u32mf2_m(...) __riscv_vsuxseg8ei32_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg2ei32_v_u32m1_m(...) __riscv_vsuxseg2ei32_v_u32m1_m(__VA_ARGS__) -#define vsuxseg3ei32_v_u32m1_m(...) __riscv_vsuxseg3ei32_v_u32m1_m(__VA_ARGS__) -#define vsuxseg4ei32_v_u32m1_m(...) __riscv_vsuxseg4ei32_v_u32m1_m(__VA_ARGS__) -#define vsuxseg5ei32_v_u32m1_m(...) __riscv_vsuxseg5ei32_v_u32m1_m(__VA_ARGS__) -#define vsuxseg6ei32_v_u32m1_m(...) __riscv_vsuxseg6ei32_v_u32m1_m(__VA_ARGS__) -#define vsuxseg7ei32_v_u32m1_m(...) __riscv_vsuxseg7ei32_v_u32m1_m(__VA_ARGS__) -#define vsuxseg8ei32_v_u32m1_m(...) __riscv_vsuxseg8ei32_v_u32m1_m(__VA_ARGS__) -#define vsuxseg2ei32_v_u32m2_m(...) __riscv_vsuxseg2ei32_v_u32m2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_u32m2_m(...) __riscv_vsuxseg3ei32_v_u32m2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_u32m2_m(...) __riscv_vsuxseg4ei32_v_u32m2_m(__VA_ARGS__) -#define vsuxseg2ei32_v_u32m4_m(...) __riscv_vsuxseg2ei32_v_u32m4_m(__VA_ARGS__) -#define vsuxseg2ei64_v_u32mf2_m(...) __riscv_vsuxseg2ei64_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg3ei64_v_u32mf2_m(...) __riscv_vsuxseg3ei64_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg4ei64_v_u32mf2_m(...) __riscv_vsuxseg4ei64_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg5ei64_v_u32mf2_m(...) __riscv_vsuxseg5ei64_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg6ei64_v_u32mf2_m(...) __riscv_vsuxseg6ei64_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg7ei64_v_u32mf2_m(...) __riscv_vsuxseg7ei64_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg8ei64_v_u32mf2_m(...) __riscv_vsuxseg8ei64_v_u32mf2_m(__VA_ARGS__) -#define vsuxseg2ei64_v_u32m1_m(...) __riscv_vsuxseg2ei64_v_u32m1_m(__VA_ARGS__) -#define vsuxseg3ei64_v_u32m1_m(...) __riscv_vsuxseg3ei64_v_u32m1_m(__VA_ARGS__) -#define vsuxseg4ei64_v_u32m1_m(...) __riscv_vsuxseg4ei64_v_u32m1_m(__VA_ARGS__) -#define vsuxseg5ei64_v_u32m1_m(...) __riscv_vsuxseg5ei64_v_u32m1_m(__VA_ARGS__) -#define vsuxseg6ei64_v_u32m1_m(...) __riscv_vsuxseg6ei64_v_u32m1_m(__VA_ARGS__) -#define vsuxseg7ei64_v_u32m1_m(...) __riscv_vsuxseg7ei64_v_u32m1_m(__VA_ARGS__) -#define vsuxseg8ei64_v_u32m1_m(...) __riscv_vsuxseg8ei64_v_u32m1_m(__VA_ARGS__) -#define vsuxseg2ei64_v_u32m2_m(...) __riscv_vsuxseg2ei64_v_u32m2_m(__VA_ARGS__) -#define vsuxseg3ei64_v_u32m2_m(...) __riscv_vsuxseg3ei64_v_u32m2_m(__VA_ARGS__) -#define vsuxseg4ei64_v_u32m2_m(...) __riscv_vsuxseg4ei64_v_u32m2_m(__VA_ARGS__) -#define vsuxseg2ei64_v_u32m4_m(...) __riscv_vsuxseg2ei64_v_u32m4_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u64m1_m(...) __riscv_vsuxseg2ei8_v_u64m1_m(__VA_ARGS__) -#define vsuxseg3ei8_v_u64m1_m(...) __riscv_vsuxseg3ei8_v_u64m1_m(__VA_ARGS__) -#define vsuxseg4ei8_v_u64m1_m(...) __riscv_vsuxseg4ei8_v_u64m1_m(__VA_ARGS__) -#define vsuxseg5ei8_v_u64m1_m(...) __riscv_vsuxseg5ei8_v_u64m1_m(__VA_ARGS__) -#define vsuxseg6ei8_v_u64m1_m(...) __riscv_vsuxseg6ei8_v_u64m1_m(__VA_ARGS__) -#define vsuxseg7ei8_v_u64m1_m(...) __riscv_vsuxseg7ei8_v_u64m1_m(__VA_ARGS__) -#define vsuxseg8ei8_v_u64m1_m(...) __riscv_vsuxseg8ei8_v_u64m1_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u64m2_m(...) __riscv_vsuxseg2ei8_v_u64m2_m(__VA_ARGS__) -#define vsuxseg3ei8_v_u64m2_m(...) __riscv_vsuxseg3ei8_v_u64m2_m(__VA_ARGS__) -#define vsuxseg4ei8_v_u64m2_m(...) __riscv_vsuxseg4ei8_v_u64m2_m(__VA_ARGS__) -#define vsuxseg2ei8_v_u64m4_m(...) __riscv_vsuxseg2ei8_v_u64m4_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u64m1_m(...) __riscv_vsuxseg2ei16_v_u64m1_m(__VA_ARGS__) -#define vsuxseg3ei16_v_u64m1_m(...) __riscv_vsuxseg3ei16_v_u64m1_m(__VA_ARGS__) -#define vsuxseg4ei16_v_u64m1_m(...) __riscv_vsuxseg4ei16_v_u64m1_m(__VA_ARGS__) -#define vsuxseg5ei16_v_u64m1_m(...) __riscv_vsuxseg5ei16_v_u64m1_m(__VA_ARGS__) -#define vsuxseg6ei16_v_u64m1_m(...) __riscv_vsuxseg6ei16_v_u64m1_m(__VA_ARGS__) -#define vsuxseg7ei16_v_u64m1_m(...) __riscv_vsuxseg7ei16_v_u64m1_m(__VA_ARGS__) -#define vsuxseg8ei16_v_u64m1_m(...) __riscv_vsuxseg8ei16_v_u64m1_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u64m2_m(...) __riscv_vsuxseg2ei16_v_u64m2_m(__VA_ARGS__) -#define vsuxseg3ei16_v_u64m2_m(...) __riscv_vsuxseg3ei16_v_u64m2_m(__VA_ARGS__) -#define vsuxseg4ei16_v_u64m2_m(...) __riscv_vsuxseg4ei16_v_u64m2_m(__VA_ARGS__) -#define vsuxseg2ei16_v_u64m4_m(...) __riscv_vsuxseg2ei16_v_u64m4_m(__VA_ARGS__) -#define vsuxseg2ei32_v_u64m1_m(...) __riscv_vsuxseg2ei32_v_u64m1_m(__VA_ARGS__) -#define vsuxseg3ei32_v_u64m1_m(...) __riscv_vsuxseg3ei32_v_u64m1_m(__VA_ARGS__) -#define vsuxseg4ei32_v_u64m1_m(...) __riscv_vsuxseg4ei32_v_u64m1_m(__VA_ARGS__) -#define vsuxseg5ei32_v_u64m1_m(...) __riscv_vsuxseg5ei32_v_u64m1_m(__VA_ARGS__) -#define vsuxseg6ei32_v_u64m1_m(...) __riscv_vsuxseg6ei32_v_u64m1_m(__VA_ARGS__) -#define vsuxseg7ei32_v_u64m1_m(...) __riscv_vsuxseg7ei32_v_u64m1_m(__VA_ARGS__) -#define vsuxseg8ei32_v_u64m1_m(...) __riscv_vsuxseg8ei32_v_u64m1_m(__VA_ARGS__) -#define vsuxseg2ei32_v_u64m2_m(...) __riscv_vsuxseg2ei32_v_u64m2_m(__VA_ARGS__) -#define vsuxseg3ei32_v_u64m2_m(...) __riscv_vsuxseg3ei32_v_u64m2_m(__VA_ARGS__) -#define vsuxseg4ei32_v_u64m2_m(...) __riscv_vsuxseg4ei32_v_u64m2_m(__VA_ARGS__) -#define vsuxseg2ei32_v_u64m4_m(...) __riscv_vsuxseg2ei32_v_u64m4_m(__VA_ARGS__) -#define vsuxseg2ei64_v_u64m1_m(...) __riscv_vsuxseg2ei64_v_u64m1_m(__VA_ARGS__) -#define vsuxseg3ei64_v_u64m1_m(...) __riscv_vsuxseg3ei64_v_u64m1_m(__VA_ARGS__) -#define vsuxseg4ei64_v_u64m1_m(...) __riscv_vsuxseg4ei64_v_u64m1_m(__VA_ARGS__) -#define vsuxseg5ei64_v_u64m1_m(...) __riscv_vsuxseg5ei64_v_u64m1_m(__VA_ARGS__) -#define vsuxseg6ei64_v_u64m1_m(...) __riscv_vsuxseg6ei64_v_u64m1_m(__VA_ARGS__) -#define vsuxseg7ei64_v_u64m1_m(...) __riscv_vsuxseg7ei64_v_u64m1_m(__VA_ARGS__) -#define vsuxseg8ei64_v_u64m1_m(...) __riscv_vsuxseg8ei64_v_u64m1_m(__VA_ARGS__) -#define vsuxseg2ei64_v_u64m2_m(...) __riscv_vsuxseg2ei64_v_u64m2_m(__VA_ARGS__) -#define vsuxseg3ei64_v_u64m2_m(...) __riscv_vsuxseg3ei64_v_u64m2_m(__VA_ARGS__) -#define vsuxseg4ei64_v_u64m2_m(...) __riscv_vsuxseg4ei64_v_u64m2_m(__VA_ARGS__) -#define vsuxseg2ei64_v_u64m4_m(...) __riscv_vsuxseg2ei64_v_u64m4_m(__VA_ARGS__) -#define vadd_vv_i8mf8(...) __riscv_vadd_vv_i8mf8(__VA_ARGS__) -#define vadd_vx_i8mf8(...) __riscv_vadd_vx_i8mf8(__VA_ARGS__) -#define vadd_vv_i8mf4(...) __riscv_vadd_vv_i8mf4(__VA_ARGS__) -#define vadd_vx_i8mf4(...) __riscv_vadd_vx_i8mf4(__VA_ARGS__) -#define vadd_vv_i8mf2(...) __riscv_vadd_vv_i8mf2(__VA_ARGS__) -#define vadd_vx_i8mf2(...) __riscv_vadd_vx_i8mf2(__VA_ARGS__) -#define vadd_vv_i8m1(...) __riscv_vadd_vv_i8m1(__VA_ARGS__) -#define vadd_vx_i8m1(...) __riscv_vadd_vx_i8m1(__VA_ARGS__) -#define vadd_vv_i8m2(...) __riscv_vadd_vv_i8m2(__VA_ARGS__) -#define vadd_vx_i8m2(...) __riscv_vadd_vx_i8m2(__VA_ARGS__) -#define vadd_vv_i8m4(...) __riscv_vadd_vv_i8m4(__VA_ARGS__) -#define vadd_vx_i8m4(...) __riscv_vadd_vx_i8m4(__VA_ARGS__) -#define vadd_vv_i8m8(...) __riscv_vadd_vv_i8m8(__VA_ARGS__) -#define vadd_vx_i8m8(...) __riscv_vadd_vx_i8m8(__VA_ARGS__) -#define vadd_vv_i16mf4(...) __riscv_vadd_vv_i16mf4(__VA_ARGS__) -#define vadd_vx_i16mf4(...) __riscv_vadd_vx_i16mf4(__VA_ARGS__) -#define vadd_vv_i16mf2(...) __riscv_vadd_vv_i16mf2(__VA_ARGS__) -#define vadd_vx_i16mf2(...) __riscv_vadd_vx_i16mf2(__VA_ARGS__) -#define vadd_vv_i16m1(...) __riscv_vadd_vv_i16m1(__VA_ARGS__) -#define vadd_vx_i16m1(...) __riscv_vadd_vx_i16m1(__VA_ARGS__) -#define vadd_vv_i16m2(...) __riscv_vadd_vv_i16m2(__VA_ARGS__) -#define vadd_vx_i16m2(...) __riscv_vadd_vx_i16m2(__VA_ARGS__) -#define vadd_vv_i16m4(...) __riscv_vadd_vv_i16m4(__VA_ARGS__) -#define vadd_vx_i16m4(...) __riscv_vadd_vx_i16m4(__VA_ARGS__) -#define vadd_vv_i16m8(...) __riscv_vadd_vv_i16m8(__VA_ARGS__) -#define vadd_vx_i16m8(...) __riscv_vadd_vx_i16m8(__VA_ARGS__) -#define vadd_vv_i32mf2(...) __riscv_vadd_vv_i32mf2(__VA_ARGS__) -#define vadd_vx_i32mf2(...) __riscv_vadd_vx_i32mf2(__VA_ARGS__) -#define vadd_vv_i32m1(...) __riscv_vadd_vv_i32m1(__VA_ARGS__) -#define vadd_vx_i32m1(...) __riscv_vadd_vx_i32m1(__VA_ARGS__) -#define vadd_vv_i32m2(...) __riscv_vadd_vv_i32m2(__VA_ARGS__) -#define vadd_vx_i32m2(...) __riscv_vadd_vx_i32m2(__VA_ARGS__) -#define vadd_vv_i32m4(...) __riscv_vadd_vv_i32m4(__VA_ARGS__) -#define vadd_vx_i32m4(...) __riscv_vadd_vx_i32m4(__VA_ARGS__) -#define vadd_vv_i32m8(...) __riscv_vadd_vv_i32m8(__VA_ARGS__) -#define vadd_vx_i32m8(...) __riscv_vadd_vx_i32m8(__VA_ARGS__) -#define vadd_vv_i64m1(...) __riscv_vadd_vv_i64m1(__VA_ARGS__) -#define vadd_vx_i64m1(...) __riscv_vadd_vx_i64m1(__VA_ARGS__) -#define vadd_vv_i64m2(...) __riscv_vadd_vv_i64m2(__VA_ARGS__) -#define vadd_vx_i64m2(...) __riscv_vadd_vx_i64m2(__VA_ARGS__) -#define vadd_vv_i64m4(...) __riscv_vadd_vv_i64m4(__VA_ARGS__) -#define vadd_vx_i64m4(...) __riscv_vadd_vx_i64m4(__VA_ARGS__) -#define vadd_vv_i64m8(...) __riscv_vadd_vv_i64m8(__VA_ARGS__) -#define vadd_vx_i64m8(...) __riscv_vadd_vx_i64m8(__VA_ARGS__) -#define vsub_vv_i8mf8(...) __riscv_vsub_vv_i8mf8(__VA_ARGS__) -#define vsub_vx_i8mf8(...) __riscv_vsub_vx_i8mf8(__VA_ARGS__) -#define vsub_vv_i8mf4(...) __riscv_vsub_vv_i8mf4(__VA_ARGS__) -#define vsub_vx_i8mf4(...) __riscv_vsub_vx_i8mf4(__VA_ARGS__) -#define vsub_vv_i8mf2(...) __riscv_vsub_vv_i8mf2(__VA_ARGS__) -#define vsub_vx_i8mf2(...) __riscv_vsub_vx_i8mf2(__VA_ARGS__) -#define vsub_vv_i8m1(...) __riscv_vsub_vv_i8m1(__VA_ARGS__) -#define vsub_vx_i8m1(...) __riscv_vsub_vx_i8m1(__VA_ARGS__) -#define vsub_vv_i8m2(...) __riscv_vsub_vv_i8m2(__VA_ARGS__) -#define vsub_vx_i8m2(...) __riscv_vsub_vx_i8m2(__VA_ARGS__) -#define vsub_vv_i8m4(...) __riscv_vsub_vv_i8m4(__VA_ARGS__) -#define vsub_vx_i8m4(...) __riscv_vsub_vx_i8m4(__VA_ARGS__) -#define vsub_vv_i8m8(...) __riscv_vsub_vv_i8m8(__VA_ARGS__) -#define vsub_vx_i8m8(...) __riscv_vsub_vx_i8m8(__VA_ARGS__) -#define vsub_vv_i16mf4(...) __riscv_vsub_vv_i16mf4(__VA_ARGS__) -#define vsub_vx_i16mf4(...) __riscv_vsub_vx_i16mf4(__VA_ARGS__) -#define vsub_vv_i16mf2(...) __riscv_vsub_vv_i16mf2(__VA_ARGS__) -#define vsub_vx_i16mf2(...) __riscv_vsub_vx_i16mf2(__VA_ARGS__) -#define vsub_vv_i16m1(...) __riscv_vsub_vv_i16m1(__VA_ARGS__) -#define vsub_vx_i16m1(...) __riscv_vsub_vx_i16m1(__VA_ARGS__) -#define vsub_vv_i16m2(...) __riscv_vsub_vv_i16m2(__VA_ARGS__) -#define vsub_vx_i16m2(...) __riscv_vsub_vx_i16m2(__VA_ARGS__) -#define vsub_vv_i16m4(...) __riscv_vsub_vv_i16m4(__VA_ARGS__) -#define vsub_vx_i16m4(...) __riscv_vsub_vx_i16m4(__VA_ARGS__) -#define vsub_vv_i16m8(...) __riscv_vsub_vv_i16m8(__VA_ARGS__) -#define vsub_vx_i16m8(...) __riscv_vsub_vx_i16m8(__VA_ARGS__) -#define vsub_vv_i32mf2(...) __riscv_vsub_vv_i32mf2(__VA_ARGS__) -#define vsub_vx_i32mf2(...) __riscv_vsub_vx_i32mf2(__VA_ARGS__) -#define vsub_vv_i32m1(...) __riscv_vsub_vv_i32m1(__VA_ARGS__) -#define vsub_vx_i32m1(...) __riscv_vsub_vx_i32m1(__VA_ARGS__) -#define vsub_vv_i32m2(...) __riscv_vsub_vv_i32m2(__VA_ARGS__) -#define vsub_vx_i32m2(...) __riscv_vsub_vx_i32m2(__VA_ARGS__) -#define vsub_vv_i32m4(...) __riscv_vsub_vv_i32m4(__VA_ARGS__) -#define vsub_vx_i32m4(...) __riscv_vsub_vx_i32m4(__VA_ARGS__) -#define vsub_vv_i32m8(...) __riscv_vsub_vv_i32m8(__VA_ARGS__) -#define vsub_vx_i32m8(...) __riscv_vsub_vx_i32m8(__VA_ARGS__) -#define vsub_vv_i64m1(...) __riscv_vsub_vv_i64m1(__VA_ARGS__) -#define vsub_vx_i64m1(...) __riscv_vsub_vx_i64m1(__VA_ARGS__) -#define vsub_vv_i64m2(...) __riscv_vsub_vv_i64m2(__VA_ARGS__) -#define vsub_vx_i64m2(...) __riscv_vsub_vx_i64m2(__VA_ARGS__) -#define vsub_vv_i64m4(...) __riscv_vsub_vv_i64m4(__VA_ARGS__) -#define vsub_vx_i64m4(...) __riscv_vsub_vx_i64m4(__VA_ARGS__) -#define vsub_vv_i64m8(...) __riscv_vsub_vv_i64m8(__VA_ARGS__) -#define vsub_vx_i64m8(...) __riscv_vsub_vx_i64m8(__VA_ARGS__) -#define vrsub_vx_i8mf8(...) __riscv_vrsub_vx_i8mf8(__VA_ARGS__) -#define vrsub_vx_i8mf4(...) __riscv_vrsub_vx_i8mf4(__VA_ARGS__) -#define vrsub_vx_i8mf2(...) __riscv_vrsub_vx_i8mf2(__VA_ARGS__) -#define vrsub_vx_i8m1(...) __riscv_vrsub_vx_i8m1(__VA_ARGS__) -#define vrsub_vx_i8m2(...) __riscv_vrsub_vx_i8m2(__VA_ARGS__) -#define vrsub_vx_i8m4(...) __riscv_vrsub_vx_i8m4(__VA_ARGS__) -#define vrsub_vx_i8m8(...) __riscv_vrsub_vx_i8m8(__VA_ARGS__) -#define vrsub_vx_i16mf4(...) __riscv_vrsub_vx_i16mf4(__VA_ARGS__) -#define vrsub_vx_i16mf2(...) __riscv_vrsub_vx_i16mf2(__VA_ARGS__) -#define vrsub_vx_i16m1(...) __riscv_vrsub_vx_i16m1(__VA_ARGS__) -#define vrsub_vx_i16m2(...) __riscv_vrsub_vx_i16m2(__VA_ARGS__) -#define vrsub_vx_i16m4(...) __riscv_vrsub_vx_i16m4(__VA_ARGS__) -#define vrsub_vx_i16m8(...) __riscv_vrsub_vx_i16m8(__VA_ARGS__) -#define vrsub_vx_i32mf2(...) __riscv_vrsub_vx_i32mf2(__VA_ARGS__) -#define vrsub_vx_i32m1(...) __riscv_vrsub_vx_i32m1(__VA_ARGS__) -#define vrsub_vx_i32m2(...) __riscv_vrsub_vx_i32m2(__VA_ARGS__) -#define vrsub_vx_i32m4(...) __riscv_vrsub_vx_i32m4(__VA_ARGS__) -#define vrsub_vx_i32m8(...) __riscv_vrsub_vx_i32m8(__VA_ARGS__) -#define vrsub_vx_i64m1(...) __riscv_vrsub_vx_i64m1(__VA_ARGS__) -#define vrsub_vx_i64m2(...) __riscv_vrsub_vx_i64m2(__VA_ARGS__) -#define vrsub_vx_i64m4(...) __riscv_vrsub_vx_i64m4(__VA_ARGS__) -#define vrsub_vx_i64m8(...) __riscv_vrsub_vx_i64m8(__VA_ARGS__) -#define vneg_v_i8mf8(...) __riscv_vneg_v_i8mf8(__VA_ARGS__) -#define vneg_v_i8mf4(...) __riscv_vneg_v_i8mf4(__VA_ARGS__) -#define vneg_v_i8mf2(...) __riscv_vneg_v_i8mf2(__VA_ARGS__) -#define vneg_v_i8m1(...) __riscv_vneg_v_i8m1(__VA_ARGS__) -#define vneg_v_i8m2(...) __riscv_vneg_v_i8m2(__VA_ARGS__) -#define vneg_v_i8m4(...) __riscv_vneg_v_i8m4(__VA_ARGS__) -#define vneg_v_i8m8(...) __riscv_vneg_v_i8m8(__VA_ARGS__) -#define vneg_v_i16mf4(...) __riscv_vneg_v_i16mf4(__VA_ARGS__) -#define vneg_v_i16mf2(...) __riscv_vneg_v_i16mf2(__VA_ARGS__) -#define vneg_v_i16m1(...) __riscv_vneg_v_i16m1(__VA_ARGS__) -#define vneg_v_i16m2(...) __riscv_vneg_v_i16m2(__VA_ARGS__) -#define vneg_v_i16m4(...) __riscv_vneg_v_i16m4(__VA_ARGS__) -#define vneg_v_i16m8(...) __riscv_vneg_v_i16m8(__VA_ARGS__) -#define vneg_v_i32mf2(...) __riscv_vneg_v_i32mf2(__VA_ARGS__) -#define vneg_v_i32m1(...) __riscv_vneg_v_i32m1(__VA_ARGS__) -#define vneg_v_i32m2(...) __riscv_vneg_v_i32m2(__VA_ARGS__) -#define vneg_v_i32m4(...) __riscv_vneg_v_i32m4(__VA_ARGS__) -#define vneg_v_i32m8(...) __riscv_vneg_v_i32m8(__VA_ARGS__) -#define vneg_v_i64m1(...) __riscv_vneg_v_i64m1(__VA_ARGS__) -#define vneg_v_i64m2(...) __riscv_vneg_v_i64m2(__VA_ARGS__) -#define vneg_v_i64m4(...) __riscv_vneg_v_i64m4(__VA_ARGS__) -#define vneg_v_i64m8(...) __riscv_vneg_v_i64m8(__VA_ARGS__) -#define vadd_vv_u8mf8(...) __riscv_vadd_vv_u8mf8(__VA_ARGS__) -#define vadd_vx_u8mf8(...) __riscv_vadd_vx_u8mf8(__VA_ARGS__) -#define vadd_vv_u8mf4(...) __riscv_vadd_vv_u8mf4(__VA_ARGS__) -#define vadd_vx_u8mf4(...) __riscv_vadd_vx_u8mf4(__VA_ARGS__) -#define vadd_vv_u8mf2(...) __riscv_vadd_vv_u8mf2(__VA_ARGS__) -#define vadd_vx_u8mf2(...) __riscv_vadd_vx_u8mf2(__VA_ARGS__) -#define vadd_vv_u8m1(...) __riscv_vadd_vv_u8m1(__VA_ARGS__) -#define vadd_vx_u8m1(...) __riscv_vadd_vx_u8m1(__VA_ARGS__) -#define vadd_vv_u8m2(...) __riscv_vadd_vv_u8m2(__VA_ARGS__) -#define vadd_vx_u8m2(...) __riscv_vadd_vx_u8m2(__VA_ARGS__) -#define vadd_vv_u8m4(...) __riscv_vadd_vv_u8m4(__VA_ARGS__) -#define vadd_vx_u8m4(...) __riscv_vadd_vx_u8m4(__VA_ARGS__) -#define vadd_vv_u8m8(...) __riscv_vadd_vv_u8m8(__VA_ARGS__) -#define vadd_vx_u8m8(...) __riscv_vadd_vx_u8m8(__VA_ARGS__) -#define vadd_vv_u16mf4(...) __riscv_vadd_vv_u16mf4(__VA_ARGS__) -#define vadd_vx_u16mf4(...) __riscv_vadd_vx_u16mf4(__VA_ARGS__) -#define vadd_vv_u16mf2(...) __riscv_vadd_vv_u16mf2(__VA_ARGS__) -#define vadd_vx_u16mf2(...) __riscv_vadd_vx_u16mf2(__VA_ARGS__) -#define vadd_vv_u16m1(...) __riscv_vadd_vv_u16m1(__VA_ARGS__) -#define vadd_vx_u16m1(...) __riscv_vadd_vx_u16m1(__VA_ARGS__) -#define vadd_vv_u16m2(...) __riscv_vadd_vv_u16m2(__VA_ARGS__) -#define vadd_vx_u16m2(...) __riscv_vadd_vx_u16m2(__VA_ARGS__) -#define vadd_vv_u16m4(...) __riscv_vadd_vv_u16m4(__VA_ARGS__) -#define vadd_vx_u16m4(...) __riscv_vadd_vx_u16m4(__VA_ARGS__) -#define vadd_vv_u16m8(...) __riscv_vadd_vv_u16m8(__VA_ARGS__) -#define vadd_vx_u16m8(...) __riscv_vadd_vx_u16m8(__VA_ARGS__) -#define vadd_vv_u32mf2(...) __riscv_vadd_vv_u32mf2(__VA_ARGS__) -#define vadd_vx_u32mf2(...) __riscv_vadd_vx_u32mf2(__VA_ARGS__) -#define vadd_vv_u32m1(...) __riscv_vadd_vv_u32m1(__VA_ARGS__) -#define vadd_vx_u32m1(...) __riscv_vadd_vx_u32m1(__VA_ARGS__) -#define vadd_vv_u32m2(...) __riscv_vadd_vv_u32m2(__VA_ARGS__) -#define vadd_vx_u32m2(...) __riscv_vadd_vx_u32m2(__VA_ARGS__) -#define vadd_vv_u32m4(...) __riscv_vadd_vv_u32m4(__VA_ARGS__) -#define vadd_vx_u32m4(...) __riscv_vadd_vx_u32m4(__VA_ARGS__) -#define vadd_vv_u32m8(...) __riscv_vadd_vv_u32m8(__VA_ARGS__) -#define vadd_vx_u32m8(...) __riscv_vadd_vx_u32m8(__VA_ARGS__) -#define vadd_vv_u64m1(...) __riscv_vadd_vv_u64m1(__VA_ARGS__) -#define vadd_vx_u64m1(...) __riscv_vadd_vx_u64m1(__VA_ARGS__) -#define vadd_vv_u64m2(...) __riscv_vadd_vv_u64m2(__VA_ARGS__) -#define vadd_vx_u64m2(...) __riscv_vadd_vx_u64m2(__VA_ARGS__) -#define vadd_vv_u64m4(...) __riscv_vadd_vv_u64m4(__VA_ARGS__) -#define vadd_vx_u64m4(...) __riscv_vadd_vx_u64m4(__VA_ARGS__) -#define vadd_vv_u64m8(...) __riscv_vadd_vv_u64m8(__VA_ARGS__) -#define vadd_vx_u64m8(...) __riscv_vadd_vx_u64m8(__VA_ARGS__) -#define vsub_vv_u8mf8(...) __riscv_vsub_vv_u8mf8(__VA_ARGS__) -#define vsub_vx_u8mf8(...) __riscv_vsub_vx_u8mf8(__VA_ARGS__) -#define vsub_vv_u8mf4(...) __riscv_vsub_vv_u8mf4(__VA_ARGS__) -#define vsub_vx_u8mf4(...) __riscv_vsub_vx_u8mf4(__VA_ARGS__) -#define vsub_vv_u8mf2(...) __riscv_vsub_vv_u8mf2(__VA_ARGS__) -#define vsub_vx_u8mf2(...) __riscv_vsub_vx_u8mf2(__VA_ARGS__) -#define vsub_vv_u8m1(...) __riscv_vsub_vv_u8m1(__VA_ARGS__) -#define vsub_vx_u8m1(...) __riscv_vsub_vx_u8m1(__VA_ARGS__) -#define vsub_vv_u8m2(...) __riscv_vsub_vv_u8m2(__VA_ARGS__) -#define vsub_vx_u8m2(...) __riscv_vsub_vx_u8m2(__VA_ARGS__) -#define vsub_vv_u8m4(...) __riscv_vsub_vv_u8m4(__VA_ARGS__) -#define vsub_vx_u8m4(...) __riscv_vsub_vx_u8m4(__VA_ARGS__) -#define vsub_vv_u8m8(...) __riscv_vsub_vv_u8m8(__VA_ARGS__) -#define vsub_vx_u8m8(...) __riscv_vsub_vx_u8m8(__VA_ARGS__) -#define vsub_vv_u16mf4(...) __riscv_vsub_vv_u16mf4(__VA_ARGS__) -#define vsub_vx_u16mf4(...) __riscv_vsub_vx_u16mf4(__VA_ARGS__) -#define vsub_vv_u16mf2(...) __riscv_vsub_vv_u16mf2(__VA_ARGS__) -#define vsub_vx_u16mf2(...) __riscv_vsub_vx_u16mf2(__VA_ARGS__) -#define vsub_vv_u16m1(...) __riscv_vsub_vv_u16m1(__VA_ARGS__) -#define vsub_vx_u16m1(...) __riscv_vsub_vx_u16m1(__VA_ARGS__) -#define vsub_vv_u16m2(...) __riscv_vsub_vv_u16m2(__VA_ARGS__) -#define vsub_vx_u16m2(...) __riscv_vsub_vx_u16m2(__VA_ARGS__) -#define vsub_vv_u16m4(...) __riscv_vsub_vv_u16m4(__VA_ARGS__) -#define vsub_vx_u16m4(...) __riscv_vsub_vx_u16m4(__VA_ARGS__) -#define vsub_vv_u16m8(...) __riscv_vsub_vv_u16m8(__VA_ARGS__) -#define vsub_vx_u16m8(...) __riscv_vsub_vx_u16m8(__VA_ARGS__) -#define vsub_vv_u32mf2(...) __riscv_vsub_vv_u32mf2(__VA_ARGS__) -#define vsub_vx_u32mf2(...) __riscv_vsub_vx_u32mf2(__VA_ARGS__) -#define vsub_vv_u32m1(...) __riscv_vsub_vv_u32m1(__VA_ARGS__) -#define vsub_vx_u32m1(...) __riscv_vsub_vx_u32m1(__VA_ARGS__) -#define vsub_vv_u32m2(...) __riscv_vsub_vv_u32m2(__VA_ARGS__) -#define vsub_vx_u32m2(...) __riscv_vsub_vx_u32m2(__VA_ARGS__) -#define vsub_vv_u32m4(...) __riscv_vsub_vv_u32m4(__VA_ARGS__) -#define vsub_vx_u32m4(...) __riscv_vsub_vx_u32m4(__VA_ARGS__) -#define vsub_vv_u32m8(...) __riscv_vsub_vv_u32m8(__VA_ARGS__) -#define vsub_vx_u32m8(...) __riscv_vsub_vx_u32m8(__VA_ARGS__) -#define vsub_vv_u64m1(...) __riscv_vsub_vv_u64m1(__VA_ARGS__) -#define vsub_vx_u64m1(...) __riscv_vsub_vx_u64m1(__VA_ARGS__) -#define vsub_vv_u64m2(...) __riscv_vsub_vv_u64m2(__VA_ARGS__) -#define vsub_vx_u64m2(...) __riscv_vsub_vx_u64m2(__VA_ARGS__) -#define vsub_vv_u64m4(...) __riscv_vsub_vv_u64m4(__VA_ARGS__) -#define vsub_vx_u64m4(...) __riscv_vsub_vx_u64m4(__VA_ARGS__) -#define vsub_vv_u64m8(...) __riscv_vsub_vv_u64m8(__VA_ARGS__) -#define vsub_vx_u64m8(...) __riscv_vsub_vx_u64m8(__VA_ARGS__) -#define vrsub_vx_u8mf8(...) __riscv_vrsub_vx_u8mf8(__VA_ARGS__) -#define vrsub_vx_u8mf4(...) __riscv_vrsub_vx_u8mf4(__VA_ARGS__) -#define vrsub_vx_u8mf2(...) __riscv_vrsub_vx_u8mf2(__VA_ARGS__) -#define vrsub_vx_u8m1(...) __riscv_vrsub_vx_u8m1(__VA_ARGS__) -#define vrsub_vx_u8m2(...) __riscv_vrsub_vx_u8m2(__VA_ARGS__) -#define vrsub_vx_u8m4(...) __riscv_vrsub_vx_u8m4(__VA_ARGS__) -#define vrsub_vx_u8m8(...) __riscv_vrsub_vx_u8m8(__VA_ARGS__) -#define vrsub_vx_u16mf4(...) __riscv_vrsub_vx_u16mf4(__VA_ARGS__) -#define vrsub_vx_u16mf2(...) __riscv_vrsub_vx_u16mf2(__VA_ARGS__) -#define vrsub_vx_u16m1(...) __riscv_vrsub_vx_u16m1(__VA_ARGS__) -#define vrsub_vx_u16m2(...) __riscv_vrsub_vx_u16m2(__VA_ARGS__) -#define vrsub_vx_u16m4(...) __riscv_vrsub_vx_u16m4(__VA_ARGS__) -#define vrsub_vx_u16m8(...) __riscv_vrsub_vx_u16m8(__VA_ARGS__) -#define vrsub_vx_u32mf2(...) __riscv_vrsub_vx_u32mf2(__VA_ARGS__) -#define vrsub_vx_u32m1(...) __riscv_vrsub_vx_u32m1(__VA_ARGS__) -#define vrsub_vx_u32m2(...) __riscv_vrsub_vx_u32m2(__VA_ARGS__) -#define vrsub_vx_u32m4(...) __riscv_vrsub_vx_u32m4(__VA_ARGS__) -#define vrsub_vx_u32m8(...) __riscv_vrsub_vx_u32m8(__VA_ARGS__) -#define vrsub_vx_u64m1(...) __riscv_vrsub_vx_u64m1(__VA_ARGS__) -#define vrsub_vx_u64m2(...) __riscv_vrsub_vx_u64m2(__VA_ARGS__) -#define vrsub_vx_u64m4(...) __riscv_vrsub_vx_u64m4(__VA_ARGS__) -#define vrsub_vx_u64m8(...) __riscv_vrsub_vx_u64m8(__VA_ARGS__) -// masked functions -#define vadd_vv_i8mf8_m(...) __riscv_vadd_vv_i8mf8_tumu(__VA_ARGS__) -#define vadd_vx_i8mf8_m(...) __riscv_vadd_vx_i8mf8_tumu(__VA_ARGS__) -#define vadd_vv_i8mf4_m(...) __riscv_vadd_vv_i8mf4_tumu(__VA_ARGS__) -#define vadd_vx_i8mf4_m(...) __riscv_vadd_vx_i8mf4_tumu(__VA_ARGS__) -#define vadd_vv_i8mf2_m(...) __riscv_vadd_vv_i8mf2_tumu(__VA_ARGS__) -#define vadd_vx_i8mf2_m(...) __riscv_vadd_vx_i8mf2_tumu(__VA_ARGS__) -#define vadd_vv_i8m1_m(...) __riscv_vadd_vv_i8m1_tumu(__VA_ARGS__) -#define vadd_vx_i8m1_m(...) __riscv_vadd_vx_i8m1_tumu(__VA_ARGS__) -#define vadd_vv_i8m2_m(...) __riscv_vadd_vv_i8m2_tumu(__VA_ARGS__) -#define vadd_vx_i8m2_m(...) __riscv_vadd_vx_i8m2_tumu(__VA_ARGS__) -#define vadd_vv_i8m4_m(...) __riscv_vadd_vv_i8m4_tumu(__VA_ARGS__) -#define vadd_vx_i8m4_m(...) __riscv_vadd_vx_i8m4_tumu(__VA_ARGS__) -#define vadd_vv_i8m8_m(...) __riscv_vadd_vv_i8m8_tumu(__VA_ARGS__) -#define vadd_vx_i8m8_m(...) __riscv_vadd_vx_i8m8_tumu(__VA_ARGS__) -#define vadd_vv_i16mf4_m(...) __riscv_vadd_vv_i16mf4_tumu(__VA_ARGS__) -#define vadd_vx_i16mf4_m(...) __riscv_vadd_vx_i16mf4_tumu(__VA_ARGS__) -#define vadd_vv_i16mf2_m(...) __riscv_vadd_vv_i16mf2_tumu(__VA_ARGS__) -#define vadd_vx_i16mf2_m(...) __riscv_vadd_vx_i16mf2_tumu(__VA_ARGS__) -#define vadd_vv_i16m1_m(...) __riscv_vadd_vv_i16m1_tumu(__VA_ARGS__) -#define vadd_vx_i16m1_m(...) __riscv_vadd_vx_i16m1_tumu(__VA_ARGS__) -#define vadd_vv_i16m2_m(...) __riscv_vadd_vv_i16m2_tumu(__VA_ARGS__) -#define vadd_vx_i16m2_m(...) __riscv_vadd_vx_i16m2_tumu(__VA_ARGS__) -#define vadd_vv_i16m4_m(...) __riscv_vadd_vv_i16m4_tumu(__VA_ARGS__) -#define vadd_vx_i16m4_m(...) __riscv_vadd_vx_i16m4_tumu(__VA_ARGS__) -#define vadd_vv_i16m8_m(...) __riscv_vadd_vv_i16m8_tumu(__VA_ARGS__) -#define vadd_vx_i16m8_m(...) __riscv_vadd_vx_i16m8_tumu(__VA_ARGS__) -#define vadd_vv_i32mf2_m(...) __riscv_vadd_vv_i32mf2_tumu(__VA_ARGS__) -#define vadd_vx_i32mf2_m(...) __riscv_vadd_vx_i32mf2_tumu(__VA_ARGS__) -#define vadd_vv_i32m1_m(...) __riscv_vadd_vv_i32m1_tumu(__VA_ARGS__) -#define vadd_vx_i32m1_m(...) __riscv_vadd_vx_i32m1_tumu(__VA_ARGS__) -#define vadd_vv_i32m2_m(...) __riscv_vadd_vv_i32m2_tumu(__VA_ARGS__) -#define vadd_vx_i32m2_m(...) __riscv_vadd_vx_i32m2_tumu(__VA_ARGS__) -#define vadd_vv_i32m4_m(...) __riscv_vadd_vv_i32m4_tumu(__VA_ARGS__) -#define vadd_vx_i32m4_m(...) __riscv_vadd_vx_i32m4_tumu(__VA_ARGS__) -#define vadd_vv_i32m8_m(...) __riscv_vadd_vv_i32m8_tumu(__VA_ARGS__) -#define vadd_vx_i32m8_m(...) __riscv_vadd_vx_i32m8_tumu(__VA_ARGS__) -#define vadd_vv_i64m1_m(...) __riscv_vadd_vv_i64m1_tumu(__VA_ARGS__) -#define vadd_vx_i64m1_m(...) __riscv_vadd_vx_i64m1_tumu(__VA_ARGS__) -#define vadd_vv_i64m2_m(...) __riscv_vadd_vv_i64m2_tumu(__VA_ARGS__) -#define vadd_vx_i64m2_m(...) __riscv_vadd_vx_i64m2_tumu(__VA_ARGS__) -#define vadd_vv_i64m4_m(...) __riscv_vadd_vv_i64m4_tumu(__VA_ARGS__) -#define vadd_vx_i64m4_m(...) __riscv_vadd_vx_i64m4_tumu(__VA_ARGS__) -#define vadd_vv_i64m8_m(...) __riscv_vadd_vv_i64m8_tumu(__VA_ARGS__) -#define vadd_vx_i64m8_m(...) __riscv_vadd_vx_i64m8_tumu(__VA_ARGS__) -#define vsub_vv_i8mf8_m(...) __riscv_vsub_vv_i8mf8_tumu(__VA_ARGS__) -#define vsub_vx_i8mf8_m(...) __riscv_vsub_vx_i8mf8_tumu(__VA_ARGS__) -#define vsub_vv_i8mf4_m(...) __riscv_vsub_vv_i8mf4_tumu(__VA_ARGS__) -#define vsub_vx_i8mf4_m(...) __riscv_vsub_vx_i8mf4_tumu(__VA_ARGS__) -#define vsub_vv_i8mf2_m(...) __riscv_vsub_vv_i8mf2_tumu(__VA_ARGS__) -#define vsub_vx_i8mf2_m(...) __riscv_vsub_vx_i8mf2_tumu(__VA_ARGS__) -#define vsub_vv_i8m1_m(...) __riscv_vsub_vv_i8m1_tumu(__VA_ARGS__) -#define vsub_vx_i8m1_m(...) __riscv_vsub_vx_i8m1_tumu(__VA_ARGS__) -#define vsub_vv_i8m2_m(...) __riscv_vsub_vv_i8m2_tumu(__VA_ARGS__) -#define vsub_vx_i8m2_m(...) __riscv_vsub_vx_i8m2_tumu(__VA_ARGS__) -#define vsub_vv_i8m4_m(...) __riscv_vsub_vv_i8m4_tumu(__VA_ARGS__) -#define vsub_vx_i8m4_m(...) __riscv_vsub_vx_i8m4_tumu(__VA_ARGS__) -#define vsub_vv_i8m8_m(...) __riscv_vsub_vv_i8m8_tumu(__VA_ARGS__) -#define vsub_vx_i8m8_m(...) __riscv_vsub_vx_i8m8_tumu(__VA_ARGS__) -#define vsub_vv_i16mf4_m(...) __riscv_vsub_vv_i16mf4_tumu(__VA_ARGS__) -#define vsub_vx_i16mf4_m(...) __riscv_vsub_vx_i16mf4_tumu(__VA_ARGS__) -#define vsub_vv_i16mf2_m(...) __riscv_vsub_vv_i16mf2_tumu(__VA_ARGS__) -#define vsub_vx_i16mf2_m(...) __riscv_vsub_vx_i16mf2_tumu(__VA_ARGS__) -#define vsub_vv_i16m1_m(...) __riscv_vsub_vv_i16m1_tumu(__VA_ARGS__) -#define vsub_vx_i16m1_m(...) __riscv_vsub_vx_i16m1_tumu(__VA_ARGS__) -#define vsub_vv_i16m2_m(...) __riscv_vsub_vv_i16m2_tumu(__VA_ARGS__) -#define vsub_vx_i16m2_m(...) __riscv_vsub_vx_i16m2_tumu(__VA_ARGS__) -#define vsub_vv_i16m4_m(...) __riscv_vsub_vv_i16m4_tumu(__VA_ARGS__) -#define vsub_vx_i16m4_m(...) __riscv_vsub_vx_i16m4_tumu(__VA_ARGS__) -#define vsub_vv_i16m8_m(...) __riscv_vsub_vv_i16m8_tumu(__VA_ARGS__) -#define vsub_vx_i16m8_m(...) __riscv_vsub_vx_i16m8_tumu(__VA_ARGS__) -#define vsub_vv_i32mf2_m(...) __riscv_vsub_vv_i32mf2_tumu(__VA_ARGS__) -#define vsub_vx_i32mf2_m(...) __riscv_vsub_vx_i32mf2_tumu(__VA_ARGS__) -#define vsub_vv_i32m1_m(...) __riscv_vsub_vv_i32m1_tumu(__VA_ARGS__) -#define vsub_vx_i32m1_m(...) __riscv_vsub_vx_i32m1_tumu(__VA_ARGS__) -#define vsub_vv_i32m2_m(...) __riscv_vsub_vv_i32m2_tumu(__VA_ARGS__) -#define vsub_vx_i32m2_m(...) __riscv_vsub_vx_i32m2_tumu(__VA_ARGS__) -#define vsub_vv_i32m4_m(...) __riscv_vsub_vv_i32m4_tumu(__VA_ARGS__) -#define vsub_vx_i32m4_m(...) __riscv_vsub_vx_i32m4_tumu(__VA_ARGS__) -#define vsub_vv_i32m8_m(...) __riscv_vsub_vv_i32m8_tumu(__VA_ARGS__) -#define vsub_vx_i32m8_m(...) __riscv_vsub_vx_i32m8_tumu(__VA_ARGS__) -#define vsub_vv_i64m1_m(...) __riscv_vsub_vv_i64m1_tumu(__VA_ARGS__) -#define vsub_vx_i64m1_m(...) __riscv_vsub_vx_i64m1_tumu(__VA_ARGS__) -#define vsub_vv_i64m2_m(...) __riscv_vsub_vv_i64m2_tumu(__VA_ARGS__) -#define vsub_vx_i64m2_m(...) __riscv_vsub_vx_i64m2_tumu(__VA_ARGS__) -#define vsub_vv_i64m4_m(...) __riscv_vsub_vv_i64m4_tumu(__VA_ARGS__) -#define vsub_vx_i64m4_m(...) __riscv_vsub_vx_i64m4_tumu(__VA_ARGS__) -#define vsub_vv_i64m8_m(...) __riscv_vsub_vv_i64m8_tumu(__VA_ARGS__) -#define vsub_vx_i64m8_m(...) __riscv_vsub_vx_i64m8_tumu(__VA_ARGS__) -#define vrsub_vx_i8mf8_m(...) __riscv_vrsub_vx_i8mf8_tumu(__VA_ARGS__) -#define vrsub_vx_i8mf4_m(...) __riscv_vrsub_vx_i8mf4_tumu(__VA_ARGS__) -#define vrsub_vx_i8mf2_m(...) __riscv_vrsub_vx_i8mf2_tumu(__VA_ARGS__) -#define vrsub_vx_i8m1_m(...) __riscv_vrsub_vx_i8m1_tumu(__VA_ARGS__) -#define vrsub_vx_i8m2_m(...) __riscv_vrsub_vx_i8m2_tumu(__VA_ARGS__) -#define vrsub_vx_i8m4_m(...) __riscv_vrsub_vx_i8m4_tumu(__VA_ARGS__) -#define vrsub_vx_i8m8_m(...) __riscv_vrsub_vx_i8m8_tumu(__VA_ARGS__) -#define vrsub_vx_i16mf4_m(...) __riscv_vrsub_vx_i16mf4_tumu(__VA_ARGS__) -#define vrsub_vx_i16mf2_m(...) __riscv_vrsub_vx_i16mf2_tumu(__VA_ARGS__) -#define vrsub_vx_i16m1_m(...) __riscv_vrsub_vx_i16m1_tumu(__VA_ARGS__) -#define vrsub_vx_i16m2_m(...) __riscv_vrsub_vx_i16m2_tumu(__VA_ARGS__) -#define vrsub_vx_i16m4_m(...) __riscv_vrsub_vx_i16m4_tumu(__VA_ARGS__) -#define vrsub_vx_i16m8_m(...) __riscv_vrsub_vx_i16m8_tumu(__VA_ARGS__) -#define vrsub_vx_i32mf2_m(...) __riscv_vrsub_vx_i32mf2_tumu(__VA_ARGS__) -#define vrsub_vx_i32m1_m(...) __riscv_vrsub_vx_i32m1_tumu(__VA_ARGS__) -#define vrsub_vx_i32m2_m(...) __riscv_vrsub_vx_i32m2_tumu(__VA_ARGS__) -#define vrsub_vx_i32m4_m(...) __riscv_vrsub_vx_i32m4_tumu(__VA_ARGS__) -#define vrsub_vx_i32m8_m(...) __riscv_vrsub_vx_i32m8_tumu(__VA_ARGS__) -#define vrsub_vx_i64m1_m(...) __riscv_vrsub_vx_i64m1_tumu(__VA_ARGS__) -#define vrsub_vx_i64m2_m(...) __riscv_vrsub_vx_i64m2_tumu(__VA_ARGS__) -#define vrsub_vx_i64m4_m(...) __riscv_vrsub_vx_i64m4_tumu(__VA_ARGS__) -#define vrsub_vx_i64m8_m(...) __riscv_vrsub_vx_i64m8_tumu(__VA_ARGS__) -#define vneg_v_i8mf8_m(...) __riscv_vneg_v_i8mf8_tumu(__VA_ARGS__) -#define vneg_v_i8mf4_m(...) __riscv_vneg_v_i8mf4_tumu(__VA_ARGS__) -#define vneg_v_i8mf2_m(...) __riscv_vneg_v_i8mf2_tumu(__VA_ARGS__) -#define vneg_v_i8m1_m(...) __riscv_vneg_v_i8m1_tumu(__VA_ARGS__) -#define vneg_v_i8m2_m(...) __riscv_vneg_v_i8m2_tumu(__VA_ARGS__) -#define vneg_v_i8m4_m(...) __riscv_vneg_v_i8m4_tumu(__VA_ARGS__) -#define vneg_v_i8m8_m(...) __riscv_vneg_v_i8m8_tumu(__VA_ARGS__) -#define vneg_v_i16mf4_m(...) __riscv_vneg_v_i16mf4_tumu(__VA_ARGS__) -#define vneg_v_i16mf2_m(...) __riscv_vneg_v_i16mf2_tumu(__VA_ARGS__) -#define vneg_v_i16m1_m(...) __riscv_vneg_v_i16m1_tumu(__VA_ARGS__) -#define vneg_v_i16m2_m(...) __riscv_vneg_v_i16m2_tumu(__VA_ARGS__) -#define vneg_v_i16m4_m(...) __riscv_vneg_v_i16m4_tumu(__VA_ARGS__) -#define vneg_v_i16m8_m(...) __riscv_vneg_v_i16m8_tumu(__VA_ARGS__) -#define vneg_v_i32mf2_m(...) __riscv_vneg_v_i32mf2_tumu(__VA_ARGS__) -#define vneg_v_i32m1_m(...) __riscv_vneg_v_i32m1_tumu(__VA_ARGS__) -#define vneg_v_i32m2_m(...) __riscv_vneg_v_i32m2_tumu(__VA_ARGS__) -#define vneg_v_i32m4_m(...) __riscv_vneg_v_i32m4_tumu(__VA_ARGS__) -#define vneg_v_i32m8_m(...) __riscv_vneg_v_i32m8_tumu(__VA_ARGS__) -#define vneg_v_i64m1_m(...) __riscv_vneg_v_i64m1_tumu(__VA_ARGS__) -#define vneg_v_i64m2_m(...) __riscv_vneg_v_i64m2_tumu(__VA_ARGS__) -#define vneg_v_i64m4_m(...) __riscv_vneg_v_i64m4_tumu(__VA_ARGS__) -#define vneg_v_i64m8_m(...) __riscv_vneg_v_i64m8_tumu(__VA_ARGS__) -#define vadd_vv_u8mf8_m(...) __riscv_vadd_vv_u8mf8_tumu(__VA_ARGS__) -#define vadd_vx_u8mf8_m(...) __riscv_vadd_vx_u8mf8_tumu(__VA_ARGS__) -#define vadd_vv_u8mf4_m(...) __riscv_vadd_vv_u8mf4_tumu(__VA_ARGS__) -#define vadd_vx_u8mf4_m(...) __riscv_vadd_vx_u8mf4_tumu(__VA_ARGS__) -#define vadd_vv_u8mf2_m(...) __riscv_vadd_vv_u8mf2_tumu(__VA_ARGS__) -#define vadd_vx_u8mf2_m(...) __riscv_vadd_vx_u8mf2_tumu(__VA_ARGS__) -#define vadd_vv_u8m1_m(...) __riscv_vadd_vv_u8m1_tumu(__VA_ARGS__) -#define vadd_vx_u8m1_m(...) __riscv_vadd_vx_u8m1_tumu(__VA_ARGS__) -#define vadd_vv_u8m2_m(...) __riscv_vadd_vv_u8m2_tumu(__VA_ARGS__) -#define vadd_vx_u8m2_m(...) __riscv_vadd_vx_u8m2_tumu(__VA_ARGS__) -#define vadd_vv_u8m4_m(...) __riscv_vadd_vv_u8m4_tumu(__VA_ARGS__) -#define vadd_vx_u8m4_m(...) __riscv_vadd_vx_u8m4_tumu(__VA_ARGS__) -#define vadd_vv_u8m8_m(...) __riscv_vadd_vv_u8m8_tumu(__VA_ARGS__) -#define vadd_vx_u8m8_m(...) __riscv_vadd_vx_u8m8_tumu(__VA_ARGS__) -#define vadd_vv_u16mf4_m(...) __riscv_vadd_vv_u16mf4_tumu(__VA_ARGS__) -#define vadd_vx_u16mf4_m(...) __riscv_vadd_vx_u16mf4_tumu(__VA_ARGS__) -#define vadd_vv_u16mf2_m(...) __riscv_vadd_vv_u16mf2_tumu(__VA_ARGS__) -#define vadd_vx_u16mf2_m(...) __riscv_vadd_vx_u16mf2_tumu(__VA_ARGS__) -#define vadd_vv_u16m1_m(...) __riscv_vadd_vv_u16m1_tumu(__VA_ARGS__) -#define vadd_vx_u16m1_m(...) __riscv_vadd_vx_u16m1_tumu(__VA_ARGS__) -#define vadd_vv_u16m2_m(...) __riscv_vadd_vv_u16m2_tumu(__VA_ARGS__) -#define vadd_vx_u16m2_m(...) __riscv_vadd_vx_u16m2_tumu(__VA_ARGS__) -#define vadd_vv_u16m4_m(...) __riscv_vadd_vv_u16m4_tumu(__VA_ARGS__) -#define vadd_vx_u16m4_m(...) __riscv_vadd_vx_u16m4_tumu(__VA_ARGS__) -#define vadd_vv_u16m8_m(...) __riscv_vadd_vv_u16m8_tumu(__VA_ARGS__) -#define vadd_vx_u16m8_m(...) __riscv_vadd_vx_u16m8_tumu(__VA_ARGS__) -#define vadd_vv_u32mf2_m(...) __riscv_vadd_vv_u32mf2_tumu(__VA_ARGS__) -#define vadd_vx_u32mf2_m(...) __riscv_vadd_vx_u32mf2_tumu(__VA_ARGS__) -#define vadd_vv_u32m1_m(...) __riscv_vadd_vv_u32m1_tumu(__VA_ARGS__) -#define vadd_vx_u32m1_m(...) __riscv_vadd_vx_u32m1_tumu(__VA_ARGS__) -#define vadd_vv_u32m2_m(...) __riscv_vadd_vv_u32m2_tumu(__VA_ARGS__) -#define vadd_vx_u32m2_m(...) __riscv_vadd_vx_u32m2_tumu(__VA_ARGS__) -#define vadd_vv_u32m4_m(...) __riscv_vadd_vv_u32m4_tumu(__VA_ARGS__) -#define vadd_vx_u32m4_m(...) __riscv_vadd_vx_u32m4_tumu(__VA_ARGS__) -#define vadd_vv_u32m8_m(...) __riscv_vadd_vv_u32m8_tumu(__VA_ARGS__) -#define vadd_vx_u32m8_m(...) __riscv_vadd_vx_u32m8_tumu(__VA_ARGS__) -#define vadd_vv_u64m1_m(...) __riscv_vadd_vv_u64m1_tumu(__VA_ARGS__) -#define vadd_vx_u64m1_m(...) __riscv_vadd_vx_u64m1_tumu(__VA_ARGS__) -#define vadd_vv_u64m2_m(...) __riscv_vadd_vv_u64m2_tumu(__VA_ARGS__) -#define vadd_vx_u64m2_m(...) __riscv_vadd_vx_u64m2_tumu(__VA_ARGS__) -#define vadd_vv_u64m4_m(...) __riscv_vadd_vv_u64m4_tumu(__VA_ARGS__) -#define vadd_vx_u64m4_m(...) __riscv_vadd_vx_u64m4_tumu(__VA_ARGS__) -#define vadd_vv_u64m8_m(...) __riscv_vadd_vv_u64m8_tumu(__VA_ARGS__) -#define vadd_vx_u64m8_m(...) __riscv_vadd_vx_u64m8_tumu(__VA_ARGS__) -#define vsub_vv_u8mf8_m(...) __riscv_vsub_vv_u8mf8_tumu(__VA_ARGS__) -#define vsub_vx_u8mf8_m(...) __riscv_vsub_vx_u8mf8_tumu(__VA_ARGS__) -#define vsub_vv_u8mf4_m(...) __riscv_vsub_vv_u8mf4_tumu(__VA_ARGS__) -#define vsub_vx_u8mf4_m(...) __riscv_vsub_vx_u8mf4_tumu(__VA_ARGS__) -#define vsub_vv_u8mf2_m(...) __riscv_vsub_vv_u8mf2_tumu(__VA_ARGS__) -#define vsub_vx_u8mf2_m(...) __riscv_vsub_vx_u8mf2_tumu(__VA_ARGS__) -#define vsub_vv_u8m1_m(...) __riscv_vsub_vv_u8m1_tumu(__VA_ARGS__) -#define vsub_vx_u8m1_m(...) __riscv_vsub_vx_u8m1_tumu(__VA_ARGS__) -#define vsub_vv_u8m2_m(...) __riscv_vsub_vv_u8m2_tumu(__VA_ARGS__) -#define vsub_vx_u8m2_m(...) __riscv_vsub_vx_u8m2_tumu(__VA_ARGS__) -#define vsub_vv_u8m4_m(...) __riscv_vsub_vv_u8m4_tumu(__VA_ARGS__) -#define vsub_vx_u8m4_m(...) __riscv_vsub_vx_u8m4_tumu(__VA_ARGS__) -#define vsub_vv_u8m8_m(...) __riscv_vsub_vv_u8m8_tumu(__VA_ARGS__) -#define vsub_vx_u8m8_m(...) __riscv_vsub_vx_u8m8_tumu(__VA_ARGS__) -#define vsub_vv_u16mf4_m(...) __riscv_vsub_vv_u16mf4_tumu(__VA_ARGS__) -#define vsub_vx_u16mf4_m(...) __riscv_vsub_vx_u16mf4_tumu(__VA_ARGS__) -#define vsub_vv_u16mf2_m(...) __riscv_vsub_vv_u16mf2_tumu(__VA_ARGS__) -#define vsub_vx_u16mf2_m(...) __riscv_vsub_vx_u16mf2_tumu(__VA_ARGS__) -#define vsub_vv_u16m1_m(...) __riscv_vsub_vv_u16m1_tumu(__VA_ARGS__) -#define vsub_vx_u16m1_m(...) __riscv_vsub_vx_u16m1_tumu(__VA_ARGS__) -#define vsub_vv_u16m2_m(...) __riscv_vsub_vv_u16m2_tumu(__VA_ARGS__) -#define vsub_vx_u16m2_m(...) __riscv_vsub_vx_u16m2_tumu(__VA_ARGS__) -#define vsub_vv_u16m4_m(...) __riscv_vsub_vv_u16m4_tumu(__VA_ARGS__) -#define vsub_vx_u16m4_m(...) __riscv_vsub_vx_u16m4_tumu(__VA_ARGS__) -#define vsub_vv_u16m8_m(...) __riscv_vsub_vv_u16m8_tumu(__VA_ARGS__) -#define vsub_vx_u16m8_m(...) __riscv_vsub_vx_u16m8_tumu(__VA_ARGS__) -#define vsub_vv_u32mf2_m(...) __riscv_vsub_vv_u32mf2_tumu(__VA_ARGS__) -#define vsub_vx_u32mf2_m(...) __riscv_vsub_vx_u32mf2_tumu(__VA_ARGS__) -#define vsub_vv_u32m1_m(...) __riscv_vsub_vv_u32m1_tumu(__VA_ARGS__) -#define vsub_vx_u32m1_m(...) __riscv_vsub_vx_u32m1_tumu(__VA_ARGS__) -#define vsub_vv_u32m2_m(...) __riscv_vsub_vv_u32m2_tumu(__VA_ARGS__) -#define vsub_vx_u32m2_m(...) __riscv_vsub_vx_u32m2_tumu(__VA_ARGS__) -#define vsub_vv_u32m4_m(...) __riscv_vsub_vv_u32m4_tumu(__VA_ARGS__) -#define vsub_vx_u32m4_m(...) __riscv_vsub_vx_u32m4_tumu(__VA_ARGS__) -#define vsub_vv_u32m8_m(...) __riscv_vsub_vv_u32m8_tumu(__VA_ARGS__) -#define vsub_vx_u32m8_m(...) __riscv_vsub_vx_u32m8_tumu(__VA_ARGS__) -#define vsub_vv_u64m1_m(...) __riscv_vsub_vv_u64m1_tumu(__VA_ARGS__) -#define vsub_vx_u64m1_m(...) __riscv_vsub_vx_u64m1_tumu(__VA_ARGS__) -#define vsub_vv_u64m2_m(...) __riscv_vsub_vv_u64m2_tumu(__VA_ARGS__) -#define vsub_vx_u64m2_m(...) __riscv_vsub_vx_u64m2_tumu(__VA_ARGS__) -#define vsub_vv_u64m4_m(...) __riscv_vsub_vv_u64m4_tumu(__VA_ARGS__) -#define vsub_vx_u64m4_m(...) __riscv_vsub_vx_u64m4_tumu(__VA_ARGS__) -#define vsub_vv_u64m8_m(...) __riscv_vsub_vv_u64m8_tumu(__VA_ARGS__) -#define vsub_vx_u64m8_m(...) __riscv_vsub_vx_u64m8_tumu(__VA_ARGS__) -#define vrsub_vx_u8mf8_m(...) __riscv_vrsub_vx_u8mf8_tumu(__VA_ARGS__) -#define vrsub_vx_u8mf4_m(...) __riscv_vrsub_vx_u8mf4_tumu(__VA_ARGS__) -#define vrsub_vx_u8mf2_m(...) __riscv_vrsub_vx_u8mf2_tumu(__VA_ARGS__) -#define vrsub_vx_u8m1_m(...) __riscv_vrsub_vx_u8m1_tumu(__VA_ARGS__) -#define vrsub_vx_u8m2_m(...) __riscv_vrsub_vx_u8m2_tumu(__VA_ARGS__) -#define vrsub_vx_u8m4_m(...) __riscv_vrsub_vx_u8m4_tumu(__VA_ARGS__) -#define vrsub_vx_u8m8_m(...) __riscv_vrsub_vx_u8m8_tumu(__VA_ARGS__) -#define vrsub_vx_u16mf4_m(...) __riscv_vrsub_vx_u16mf4_tumu(__VA_ARGS__) -#define vrsub_vx_u16mf2_m(...) __riscv_vrsub_vx_u16mf2_tumu(__VA_ARGS__) -#define vrsub_vx_u16m1_m(...) __riscv_vrsub_vx_u16m1_tumu(__VA_ARGS__) -#define vrsub_vx_u16m2_m(...) __riscv_vrsub_vx_u16m2_tumu(__VA_ARGS__) -#define vrsub_vx_u16m4_m(...) __riscv_vrsub_vx_u16m4_tumu(__VA_ARGS__) -#define vrsub_vx_u16m8_m(...) __riscv_vrsub_vx_u16m8_tumu(__VA_ARGS__) -#define vrsub_vx_u32mf2_m(...) __riscv_vrsub_vx_u32mf2_tumu(__VA_ARGS__) -#define vrsub_vx_u32m1_m(...) __riscv_vrsub_vx_u32m1_tumu(__VA_ARGS__) -#define vrsub_vx_u32m2_m(...) __riscv_vrsub_vx_u32m2_tumu(__VA_ARGS__) -#define vrsub_vx_u32m4_m(...) __riscv_vrsub_vx_u32m4_tumu(__VA_ARGS__) -#define vrsub_vx_u32m8_m(...) __riscv_vrsub_vx_u32m8_tumu(__VA_ARGS__) -#define vrsub_vx_u64m1_m(...) __riscv_vrsub_vx_u64m1_tumu(__VA_ARGS__) -#define vrsub_vx_u64m2_m(...) __riscv_vrsub_vx_u64m2_tumu(__VA_ARGS__) -#define vrsub_vx_u64m4_m(...) __riscv_vrsub_vx_u64m4_tumu(__VA_ARGS__) -#define vrsub_vx_u64m8_m(...) __riscv_vrsub_vx_u64m8_tumu(__VA_ARGS__) -#define vwadd_vv_i16mf4(...) __riscv_vwadd_vv_i16mf4(__VA_ARGS__) -#define vwadd_vx_i16mf4(...) __riscv_vwadd_vx_i16mf4(__VA_ARGS__) -#define vwadd_wv_i16mf4(...) __riscv_vwadd_wv_i16mf4(__VA_ARGS__) -#define vwadd_wx_i16mf4(...) __riscv_vwadd_wx_i16mf4(__VA_ARGS__) -#define vwadd_vv_i16mf2(...) __riscv_vwadd_vv_i16mf2(__VA_ARGS__) -#define vwadd_vx_i16mf2(...) __riscv_vwadd_vx_i16mf2(__VA_ARGS__) -#define vwadd_wv_i16mf2(...) __riscv_vwadd_wv_i16mf2(__VA_ARGS__) -#define vwadd_wx_i16mf2(...) __riscv_vwadd_wx_i16mf2(__VA_ARGS__) -#define vwadd_vv_i16m1(...) __riscv_vwadd_vv_i16m1(__VA_ARGS__) -#define vwadd_vx_i16m1(...) __riscv_vwadd_vx_i16m1(__VA_ARGS__) -#define vwadd_wv_i16m1(...) __riscv_vwadd_wv_i16m1(__VA_ARGS__) -#define vwadd_wx_i16m1(...) __riscv_vwadd_wx_i16m1(__VA_ARGS__) -#define vwadd_vv_i16m2(...) __riscv_vwadd_vv_i16m2(__VA_ARGS__) -#define vwadd_vx_i16m2(...) __riscv_vwadd_vx_i16m2(__VA_ARGS__) -#define vwadd_wv_i16m2(...) __riscv_vwadd_wv_i16m2(__VA_ARGS__) -#define vwadd_wx_i16m2(...) __riscv_vwadd_wx_i16m2(__VA_ARGS__) -#define vwadd_vv_i16m4(...) __riscv_vwadd_vv_i16m4(__VA_ARGS__) -#define vwadd_vx_i16m4(...) __riscv_vwadd_vx_i16m4(__VA_ARGS__) -#define vwadd_wv_i16m4(...) __riscv_vwadd_wv_i16m4(__VA_ARGS__) -#define vwadd_wx_i16m4(...) __riscv_vwadd_wx_i16m4(__VA_ARGS__) -#define vwadd_vv_i16m8(...) __riscv_vwadd_vv_i16m8(__VA_ARGS__) -#define vwadd_vx_i16m8(...) __riscv_vwadd_vx_i16m8(__VA_ARGS__) -#define vwadd_wv_i16m8(...) __riscv_vwadd_wv_i16m8(__VA_ARGS__) -#define vwadd_wx_i16m8(...) __riscv_vwadd_wx_i16m8(__VA_ARGS__) -#define vwadd_vv_i32mf2(...) __riscv_vwadd_vv_i32mf2(__VA_ARGS__) -#define vwadd_vx_i32mf2(...) __riscv_vwadd_vx_i32mf2(__VA_ARGS__) -#define vwadd_wv_i32mf2(...) __riscv_vwadd_wv_i32mf2(__VA_ARGS__) -#define vwadd_wx_i32mf2(...) __riscv_vwadd_wx_i32mf2(__VA_ARGS__) -#define vwadd_vv_i32m1(...) __riscv_vwadd_vv_i32m1(__VA_ARGS__) -#define vwadd_vx_i32m1(...) __riscv_vwadd_vx_i32m1(__VA_ARGS__) -#define vwadd_wv_i32m1(...) __riscv_vwadd_wv_i32m1(__VA_ARGS__) -#define vwadd_wx_i32m1(...) __riscv_vwadd_wx_i32m1(__VA_ARGS__) -#define vwadd_vv_i32m2(...) __riscv_vwadd_vv_i32m2(__VA_ARGS__) -#define vwadd_vx_i32m2(...) __riscv_vwadd_vx_i32m2(__VA_ARGS__) -#define vwadd_wv_i32m2(...) __riscv_vwadd_wv_i32m2(__VA_ARGS__) -#define vwadd_wx_i32m2(...) __riscv_vwadd_wx_i32m2(__VA_ARGS__) -#define vwadd_vv_i32m4(...) __riscv_vwadd_vv_i32m4(__VA_ARGS__) -#define vwadd_vx_i32m4(...) __riscv_vwadd_vx_i32m4(__VA_ARGS__) -#define vwadd_wv_i32m4(...) __riscv_vwadd_wv_i32m4(__VA_ARGS__) -#define vwadd_wx_i32m4(...) __riscv_vwadd_wx_i32m4(__VA_ARGS__) -#define vwadd_vv_i32m8(...) __riscv_vwadd_vv_i32m8(__VA_ARGS__) -#define vwadd_vx_i32m8(...) __riscv_vwadd_vx_i32m8(__VA_ARGS__) -#define vwadd_wv_i32m8(...) __riscv_vwadd_wv_i32m8(__VA_ARGS__) -#define vwadd_wx_i32m8(...) __riscv_vwadd_wx_i32m8(__VA_ARGS__) -#define vwadd_vv_i64m1(...) __riscv_vwadd_vv_i64m1(__VA_ARGS__) -#define vwadd_vx_i64m1(...) __riscv_vwadd_vx_i64m1(__VA_ARGS__) -#define vwadd_wv_i64m1(...) __riscv_vwadd_wv_i64m1(__VA_ARGS__) -#define vwadd_wx_i64m1(...) __riscv_vwadd_wx_i64m1(__VA_ARGS__) -#define vwadd_vv_i64m2(...) __riscv_vwadd_vv_i64m2(__VA_ARGS__) -#define vwadd_vx_i64m2(...) __riscv_vwadd_vx_i64m2(__VA_ARGS__) -#define vwadd_wv_i64m2(...) __riscv_vwadd_wv_i64m2(__VA_ARGS__) -#define vwadd_wx_i64m2(...) __riscv_vwadd_wx_i64m2(__VA_ARGS__) -#define vwadd_vv_i64m4(...) __riscv_vwadd_vv_i64m4(__VA_ARGS__) -#define vwadd_vx_i64m4(...) __riscv_vwadd_vx_i64m4(__VA_ARGS__) -#define vwadd_wv_i64m4(...) __riscv_vwadd_wv_i64m4(__VA_ARGS__) -#define vwadd_wx_i64m4(...) __riscv_vwadd_wx_i64m4(__VA_ARGS__) -#define vwadd_vv_i64m8(...) __riscv_vwadd_vv_i64m8(__VA_ARGS__) -#define vwadd_vx_i64m8(...) __riscv_vwadd_vx_i64m8(__VA_ARGS__) -#define vwadd_wv_i64m8(...) __riscv_vwadd_wv_i64m8(__VA_ARGS__) -#define vwadd_wx_i64m8(...) __riscv_vwadd_wx_i64m8(__VA_ARGS__) -#define vwsub_vv_i16mf4(...) __riscv_vwsub_vv_i16mf4(__VA_ARGS__) -#define vwsub_vx_i16mf4(...) __riscv_vwsub_vx_i16mf4(__VA_ARGS__) -#define vwsub_wv_i16mf4(...) __riscv_vwsub_wv_i16mf4(__VA_ARGS__) -#define vwsub_wx_i16mf4(...) __riscv_vwsub_wx_i16mf4(__VA_ARGS__) -#define vwsub_vv_i16mf2(...) __riscv_vwsub_vv_i16mf2(__VA_ARGS__) -#define vwsub_vx_i16mf2(...) __riscv_vwsub_vx_i16mf2(__VA_ARGS__) -#define vwsub_wv_i16mf2(...) __riscv_vwsub_wv_i16mf2(__VA_ARGS__) -#define vwsub_wx_i16mf2(...) __riscv_vwsub_wx_i16mf2(__VA_ARGS__) -#define vwsub_vv_i16m1(...) __riscv_vwsub_vv_i16m1(__VA_ARGS__) -#define vwsub_vx_i16m1(...) __riscv_vwsub_vx_i16m1(__VA_ARGS__) -#define vwsub_wv_i16m1(...) __riscv_vwsub_wv_i16m1(__VA_ARGS__) -#define vwsub_wx_i16m1(...) __riscv_vwsub_wx_i16m1(__VA_ARGS__) -#define vwsub_vv_i16m2(...) __riscv_vwsub_vv_i16m2(__VA_ARGS__) -#define vwsub_vx_i16m2(...) __riscv_vwsub_vx_i16m2(__VA_ARGS__) -#define vwsub_wv_i16m2(...) __riscv_vwsub_wv_i16m2(__VA_ARGS__) -#define vwsub_wx_i16m2(...) __riscv_vwsub_wx_i16m2(__VA_ARGS__) -#define vwsub_vv_i16m4(...) __riscv_vwsub_vv_i16m4(__VA_ARGS__) -#define vwsub_vx_i16m4(...) __riscv_vwsub_vx_i16m4(__VA_ARGS__) -#define vwsub_wv_i16m4(...) __riscv_vwsub_wv_i16m4(__VA_ARGS__) -#define vwsub_wx_i16m4(...) __riscv_vwsub_wx_i16m4(__VA_ARGS__) -#define vwsub_vv_i16m8(...) __riscv_vwsub_vv_i16m8(__VA_ARGS__) -#define vwsub_vx_i16m8(...) __riscv_vwsub_vx_i16m8(__VA_ARGS__) -#define vwsub_wv_i16m8(...) __riscv_vwsub_wv_i16m8(__VA_ARGS__) -#define vwsub_wx_i16m8(...) __riscv_vwsub_wx_i16m8(__VA_ARGS__) -#define vwsub_vv_i32mf2(...) __riscv_vwsub_vv_i32mf2(__VA_ARGS__) -#define vwsub_vx_i32mf2(...) __riscv_vwsub_vx_i32mf2(__VA_ARGS__) -#define vwsub_wv_i32mf2(...) __riscv_vwsub_wv_i32mf2(__VA_ARGS__) -#define vwsub_wx_i32mf2(...) __riscv_vwsub_wx_i32mf2(__VA_ARGS__) -#define vwsub_vv_i32m1(...) __riscv_vwsub_vv_i32m1(__VA_ARGS__) -#define vwsub_vx_i32m1(...) __riscv_vwsub_vx_i32m1(__VA_ARGS__) -#define vwsub_wv_i32m1(...) __riscv_vwsub_wv_i32m1(__VA_ARGS__) -#define vwsub_wx_i32m1(...) __riscv_vwsub_wx_i32m1(__VA_ARGS__) -#define vwsub_vv_i32m2(...) __riscv_vwsub_vv_i32m2(__VA_ARGS__) -#define vwsub_vx_i32m2(...) __riscv_vwsub_vx_i32m2(__VA_ARGS__) -#define vwsub_wv_i32m2(...) __riscv_vwsub_wv_i32m2(__VA_ARGS__) -#define vwsub_wx_i32m2(...) __riscv_vwsub_wx_i32m2(__VA_ARGS__) -#define vwsub_vv_i32m4(...) __riscv_vwsub_vv_i32m4(__VA_ARGS__) -#define vwsub_vx_i32m4(...) __riscv_vwsub_vx_i32m4(__VA_ARGS__) -#define vwsub_wv_i32m4(...) __riscv_vwsub_wv_i32m4(__VA_ARGS__) -#define vwsub_wx_i32m4(...) __riscv_vwsub_wx_i32m4(__VA_ARGS__) -#define vwsub_vv_i32m8(...) __riscv_vwsub_vv_i32m8(__VA_ARGS__) -#define vwsub_vx_i32m8(...) __riscv_vwsub_vx_i32m8(__VA_ARGS__) -#define vwsub_wv_i32m8(...) __riscv_vwsub_wv_i32m8(__VA_ARGS__) -#define vwsub_wx_i32m8(...) __riscv_vwsub_wx_i32m8(__VA_ARGS__) -#define vwsub_vv_i64m1(...) __riscv_vwsub_vv_i64m1(__VA_ARGS__) -#define vwsub_vx_i64m1(...) __riscv_vwsub_vx_i64m1(__VA_ARGS__) -#define vwsub_wv_i64m1(...) __riscv_vwsub_wv_i64m1(__VA_ARGS__) -#define vwsub_wx_i64m1(...) __riscv_vwsub_wx_i64m1(__VA_ARGS__) -#define vwsub_vv_i64m2(...) __riscv_vwsub_vv_i64m2(__VA_ARGS__) -#define vwsub_vx_i64m2(...) __riscv_vwsub_vx_i64m2(__VA_ARGS__) -#define vwsub_wv_i64m2(...) __riscv_vwsub_wv_i64m2(__VA_ARGS__) -#define vwsub_wx_i64m2(...) __riscv_vwsub_wx_i64m2(__VA_ARGS__) -#define vwsub_vv_i64m4(...) __riscv_vwsub_vv_i64m4(__VA_ARGS__) -#define vwsub_vx_i64m4(...) __riscv_vwsub_vx_i64m4(__VA_ARGS__) -#define vwsub_wv_i64m4(...) __riscv_vwsub_wv_i64m4(__VA_ARGS__) -#define vwsub_wx_i64m4(...) __riscv_vwsub_wx_i64m4(__VA_ARGS__) -#define vwsub_vv_i64m8(...) __riscv_vwsub_vv_i64m8(__VA_ARGS__) -#define vwsub_vx_i64m8(...) __riscv_vwsub_vx_i64m8(__VA_ARGS__) -#define vwsub_wv_i64m8(...) __riscv_vwsub_wv_i64m8(__VA_ARGS__) -#define vwsub_wx_i64m8(...) __riscv_vwsub_wx_i64m8(__VA_ARGS__) -#define vwaddu_vv_u16mf4(...) __riscv_vwaddu_vv_u16mf4(__VA_ARGS__) -#define vwaddu_vx_u16mf4(...) __riscv_vwaddu_vx_u16mf4(__VA_ARGS__) -#define vwaddu_wv_u16mf4(...) __riscv_vwaddu_wv_u16mf4(__VA_ARGS__) -#define vwaddu_wx_u16mf4(...) __riscv_vwaddu_wx_u16mf4(__VA_ARGS__) -#define vwaddu_vv_u16mf2(...) __riscv_vwaddu_vv_u16mf2(__VA_ARGS__) -#define vwaddu_vx_u16mf2(...) __riscv_vwaddu_vx_u16mf2(__VA_ARGS__) -#define vwaddu_wv_u16mf2(...) __riscv_vwaddu_wv_u16mf2(__VA_ARGS__) -#define vwaddu_wx_u16mf2(...) __riscv_vwaddu_wx_u16mf2(__VA_ARGS__) -#define vwaddu_vv_u16m1(...) __riscv_vwaddu_vv_u16m1(__VA_ARGS__) -#define vwaddu_vx_u16m1(...) __riscv_vwaddu_vx_u16m1(__VA_ARGS__) -#define vwaddu_wv_u16m1(...) __riscv_vwaddu_wv_u16m1(__VA_ARGS__) -#define vwaddu_wx_u16m1(...) __riscv_vwaddu_wx_u16m1(__VA_ARGS__) -#define vwaddu_vv_u16m2(...) __riscv_vwaddu_vv_u16m2(__VA_ARGS__) -#define vwaddu_vx_u16m2(...) __riscv_vwaddu_vx_u16m2(__VA_ARGS__) -#define vwaddu_wv_u16m2(...) __riscv_vwaddu_wv_u16m2(__VA_ARGS__) -#define vwaddu_wx_u16m2(...) __riscv_vwaddu_wx_u16m2(__VA_ARGS__) -#define vwaddu_vv_u16m4(...) __riscv_vwaddu_vv_u16m4(__VA_ARGS__) -#define vwaddu_vx_u16m4(...) __riscv_vwaddu_vx_u16m4(__VA_ARGS__) -#define vwaddu_wv_u16m4(...) __riscv_vwaddu_wv_u16m4(__VA_ARGS__) -#define vwaddu_wx_u16m4(...) __riscv_vwaddu_wx_u16m4(__VA_ARGS__) -#define vwaddu_vv_u16m8(...) __riscv_vwaddu_vv_u16m8(__VA_ARGS__) -#define vwaddu_vx_u16m8(...) __riscv_vwaddu_vx_u16m8(__VA_ARGS__) -#define vwaddu_wv_u16m8(...) __riscv_vwaddu_wv_u16m8(__VA_ARGS__) -#define vwaddu_wx_u16m8(...) __riscv_vwaddu_wx_u16m8(__VA_ARGS__) -#define vwaddu_vv_u32mf2(...) __riscv_vwaddu_vv_u32mf2(__VA_ARGS__) -#define vwaddu_vx_u32mf2(...) __riscv_vwaddu_vx_u32mf2(__VA_ARGS__) -#define vwaddu_wv_u32mf2(...) __riscv_vwaddu_wv_u32mf2(__VA_ARGS__) -#define vwaddu_wx_u32mf2(...) __riscv_vwaddu_wx_u32mf2(__VA_ARGS__) -#define vwaddu_vv_u32m1(...) __riscv_vwaddu_vv_u32m1(__VA_ARGS__) -#define vwaddu_vx_u32m1(...) __riscv_vwaddu_vx_u32m1(__VA_ARGS__) -#define vwaddu_wv_u32m1(...) __riscv_vwaddu_wv_u32m1(__VA_ARGS__) -#define vwaddu_wx_u32m1(...) __riscv_vwaddu_wx_u32m1(__VA_ARGS__) -#define vwaddu_vv_u32m2(...) __riscv_vwaddu_vv_u32m2(__VA_ARGS__) -#define vwaddu_vx_u32m2(...) __riscv_vwaddu_vx_u32m2(__VA_ARGS__) -#define vwaddu_wv_u32m2(...) __riscv_vwaddu_wv_u32m2(__VA_ARGS__) -#define vwaddu_wx_u32m2(...) __riscv_vwaddu_wx_u32m2(__VA_ARGS__) -#define vwaddu_vv_u32m4(...) __riscv_vwaddu_vv_u32m4(__VA_ARGS__) -#define vwaddu_vx_u32m4(...) __riscv_vwaddu_vx_u32m4(__VA_ARGS__) -#define vwaddu_wv_u32m4(...) __riscv_vwaddu_wv_u32m4(__VA_ARGS__) -#define vwaddu_wx_u32m4(...) __riscv_vwaddu_wx_u32m4(__VA_ARGS__) -#define vwaddu_vv_u32m8(...) __riscv_vwaddu_vv_u32m8(__VA_ARGS__) -#define vwaddu_vx_u32m8(...) __riscv_vwaddu_vx_u32m8(__VA_ARGS__) -#define vwaddu_wv_u32m8(...) __riscv_vwaddu_wv_u32m8(__VA_ARGS__) -#define vwaddu_wx_u32m8(...) __riscv_vwaddu_wx_u32m8(__VA_ARGS__) -#define vwaddu_vv_u64m1(...) __riscv_vwaddu_vv_u64m1(__VA_ARGS__) -#define vwaddu_vx_u64m1(...) __riscv_vwaddu_vx_u64m1(__VA_ARGS__) -#define vwaddu_wv_u64m1(...) __riscv_vwaddu_wv_u64m1(__VA_ARGS__) -#define vwaddu_wx_u64m1(...) __riscv_vwaddu_wx_u64m1(__VA_ARGS__) -#define vwaddu_vv_u64m2(...) __riscv_vwaddu_vv_u64m2(__VA_ARGS__) -#define vwaddu_vx_u64m2(...) __riscv_vwaddu_vx_u64m2(__VA_ARGS__) -#define vwaddu_wv_u64m2(...) __riscv_vwaddu_wv_u64m2(__VA_ARGS__) -#define vwaddu_wx_u64m2(...) __riscv_vwaddu_wx_u64m2(__VA_ARGS__) -#define vwaddu_vv_u64m4(...) __riscv_vwaddu_vv_u64m4(__VA_ARGS__) -#define vwaddu_vx_u64m4(...) __riscv_vwaddu_vx_u64m4(__VA_ARGS__) -#define vwaddu_wv_u64m4(...) __riscv_vwaddu_wv_u64m4(__VA_ARGS__) -#define vwaddu_wx_u64m4(...) __riscv_vwaddu_wx_u64m4(__VA_ARGS__) -#define vwaddu_vv_u64m8(...) __riscv_vwaddu_vv_u64m8(__VA_ARGS__) -#define vwaddu_vx_u64m8(...) __riscv_vwaddu_vx_u64m8(__VA_ARGS__) -#define vwaddu_wv_u64m8(...) __riscv_vwaddu_wv_u64m8(__VA_ARGS__) -#define vwaddu_wx_u64m8(...) __riscv_vwaddu_wx_u64m8(__VA_ARGS__) -#define vwsubu_vv_u16mf4(...) __riscv_vwsubu_vv_u16mf4(__VA_ARGS__) -#define vwsubu_vx_u16mf4(...) __riscv_vwsubu_vx_u16mf4(__VA_ARGS__) -#define vwsubu_wv_u16mf4(...) __riscv_vwsubu_wv_u16mf4(__VA_ARGS__) -#define vwsubu_wx_u16mf4(...) __riscv_vwsubu_wx_u16mf4(__VA_ARGS__) -#define vwsubu_vv_u16mf2(...) __riscv_vwsubu_vv_u16mf2(__VA_ARGS__) -#define vwsubu_vx_u16mf2(...) __riscv_vwsubu_vx_u16mf2(__VA_ARGS__) -#define vwsubu_wv_u16mf2(...) __riscv_vwsubu_wv_u16mf2(__VA_ARGS__) -#define vwsubu_wx_u16mf2(...) __riscv_vwsubu_wx_u16mf2(__VA_ARGS__) -#define vwsubu_vv_u16m1(...) __riscv_vwsubu_vv_u16m1(__VA_ARGS__) -#define vwsubu_vx_u16m1(...) __riscv_vwsubu_vx_u16m1(__VA_ARGS__) -#define vwsubu_wv_u16m1(...) __riscv_vwsubu_wv_u16m1(__VA_ARGS__) -#define vwsubu_wx_u16m1(...) __riscv_vwsubu_wx_u16m1(__VA_ARGS__) -#define vwsubu_vv_u16m2(...) __riscv_vwsubu_vv_u16m2(__VA_ARGS__) -#define vwsubu_vx_u16m2(...) __riscv_vwsubu_vx_u16m2(__VA_ARGS__) -#define vwsubu_wv_u16m2(...) __riscv_vwsubu_wv_u16m2(__VA_ARGS__) -#define vwsubu_wx_u16m2(...) __riscv_vwsubu_wx_u16m2(__VA_ARGS__) -#define vwsubu_vv_u16m4(...) __riscv_vwsubu_vv_u16m4(__VA_ARGS__) -#define vwsubu_vx_u16m4(...) __riscv_vwsubu_vx_u16m4(__VA_ARGS__) -#define vwsubu_wv_u16m4(...) __riscv_vwsubu_wv_u16m4(__VA_ARGS__) -#define vwsubu_wx_u16m4(...) __riscv_vwsubu_wx_u16m4(__VA_ARGS__) -#define vwsubu_vv_u16m8(...) __riscv_vwsubu_vv_u16m8(__VA_ARGS__) -#define vwsubu_vx_u16m8(...) __riscv_vwsubu_vx_u16m8(__VA_ARGS__) -#define vwsubu_wv_u16m8(...) __riscv_vwsubu_wv_u16m8(__VA_ARGS__) -#define vwsubu_wx_u16m8(...) __riscv_vwsubu_wx_u16m8(__VA_ARGS__) -#define vwsubu_vv_u32mf2(...) __riscv_vwsubu_vv_u32mf2(__VA_ARGS__) -#define vwsubu_vx_u32mf2(...) __riscv_vwsubu_vx_u32mf2(__VA_ARGS__) -#define vwsubu_wv_u32mf2(...) __riscv_vwsubu_wv_u32mf2(__VA_ARGS__) -#define vwsubu_wx_u32mf2(...) __riscv_vwsubu_wx_u32mf2(__VA_ARGS__) -#define vwsubu_vv_u32m1(...) __riscv_vwsubu_vv_u32m1(__VA_ARGS__) -#define vwsubu_vx_u32m1(...) __riscv_vwsubu_vx_u32m1(__VA_ARGS__) -#define vwsubu_wv_u32m1(...) __riscv_vwsubu_wv_u32m1(__VA_ARGS__) -#define vwsubu_wx_u32m1(...) __riscv_vwsubu_wx_u32m1(__VA_ARGS__) -#define vwsubu_vv_u32m2(...) __riscv_vwsubu_vv_u32m2(__VA_ARGS__) -#define vwsubu_vx_u32m2(...) __riscv_vwsubu_vx_u32m2(__VA_ARGS__) -#define vwsubu_wv_u32m2(...) __riscv_vwsubu_wv_u32m2(__VA_ARGS__) -#define vwsubu_wx_u32m2(...) __riscv_vwsubu_wx_u32m2(__VA_ARGS__) -#define vwsubu_vv_u32m4(...) __riscv_vwsubu_vv_u32m4(__VA_ARGS__) -#define vwsubu_vx_u32m4(...) __riscv_vwsubu_vx_u32m4(__VA_ARGS__) -#define vwsubu_wv_u32m4(...) __riscv_vwsubu_wv_u32m4(__VA_ARGS__) -#define vwsubu_wx_u32m4(...) __riscv_vwsubu_wx_u32m4(__VA_ARGS__) -#define vwsubu_vv_u32m8(...) __riscv_vwsubu_vv_u32m8(__VA_ARGS__) -#define vwsubu_vx_u32m8(...) __riscv_vwsubu_vx_u32m8(__VA_ARGS__) -#define vwsubu_wv_u32m8(...) __riscv_vwsubu_wv_u32m8(__VA_ARGS__) -#define vwsubu_wx_u32m8(...) __riscv_vwsubu_wx_u32m8(__VA_ARGS__) -#define vwsubu_vv_u64m1(...) __riscv_vwsubu_vv_u64m1(__VA_ARGS__) -#define vwsubu_vx_u64m1(...) __riscv_vwsubu_vx_u64m1(__VA_ARGS__) -#define vwsubu_wv_u64m1(...) __riscv_vwsubu_wv_u64m1(__VA_ARGS__) -#define vwsubu_wx_u64m1(...) __riscv_vwsubu_wx_u64m1(__VA_ARGS__) -#define vwsubu_vv_u64m2(...) __riscv_vwsubu_vv_u64m2(__VA_ARGS__) -#define vwsubu_vx_u64m2(...) __riscv_vwsubu_vx_u64m2(__VA_ARGS__) -#define vwsubu_wv_u64m2(...) __riscv_vwsubu_wv_u64m2(__VA_ARGS__) -#define vwsubu_wx_u64m2(...) __riscv_vwsubu_wx_u64m2(__VA_ARGS__) -#define vwsubu_vv_u64m4(...) __riscv_vwsubu_vv_u64m4(__VA_ARGS__) -#define vwsubu_vx_u64m4(...) __riscv_vwsubu_vx_u64m4(__VA_ARGS__) -#define vwsubu_wv_u64m4(...) __riscv_vwsubu_wv_u64m4(__VA_ARGS__) -#define vwsubu_wx_u64m4(...) __riscv_vwsubu_wx_u64m4(__VA_ARGS__) -#define vwsubu_vv_u64m8(...) __riscv_vwsubu_vv_u64m8(__VA_ARGS__) -#define vwsubu_vx_u64m8(...) __riscv_vwsubu_vx_u64m8(__VA_ARGS__) -#define vwsubu_wv_u64m8(...) __riscv_vwsubu_wv_u64m8(__VA_ARGS__) -#define vwsubu_wx_u64m8(...) __riscv_vwsubu_wx_u64m8(__VA_ARGS__) -// masked functions -#define vwadd_vv_i16mf4_m(...) __riscv_vwadd_vv_i16mf4_tumu(__VA_ARGS__) -#define vwadd_vx_i16mf4_m(...) __riscv_vwadd_vx_i16mf4_tumu(__VA_ARGS__) -#define vwadd_wv_i16mf4_m(...) __riscv_vwadd_wv_i16mf4_tumu(__VA_ARGS__) -#define vwadd_wx_i16mf4_m(...) __riscv_vwadd_wx_i16mf4_tumu(__VA_ARGS__) -#define vwadd_vv_i16mf2_m(...) __riscv_vwadd_vv_i16mf2_tumu(__VA_ARGS__) -#define vwadd_vx_i16mf2_m(...) __riscv_vwadd_vx_i16mf2_tumu(__VA_ARGS__) -#define vwadd_wv_i16mf2_m(...) __riscv_vwadd_wv_i16mf2_tumu(__VA_ARGS__) -#define vwadd_wx_i16mf2_m(...) __riscv_vwadd_wx_i16mf2_tumu(__VA_ARGS__) -#define vwadd_vv_i16m1_m(...) __riscv_vwadd_vv_i16m1_tumu(__VA_ARGS__) -#define vwadd_vx_i16m1_m(...) __riscv_vwadd_vx_i16m1_tumu(__VA_ARGS__) -#define vwadd_wv_i16m1_m(...) __riscv_vwadd_wv_i16m1_tumu(__VA_ARGS__) -#define vwadd_wx_i16m1_m(...) __riscv_vwadd_wx_i16m1_tumu(__VA_ARGS__) -#define vwadd_vv_i16m2_m(...) __riscv_vwadd_vv_i16m2_tumu(__VA_ARGS__) -#define vwadd_vx_i16m2_m(...) __riscv_vwadd_vx_i16m2_tumu(__VA_ARGS__) -#define vwadd_wv_i16m2_m(...) __riscv_vwadd_wv_i16m2_tumu(__VA_ARGS__) -#define vwadd_wx_i16m2_m(...) __riscv_vwadd_wx_i16m2_tumu(__VA_ARGS__) -#define vwadd_vv_i16m4_m(...) __riscv_vwadd_vv_i16m4_tumu(__VA_ARGS__) -#define vwadd_vx_i16m4_m(...) __riscv_vwadd_vx_i16m4_tumu(__VA_ARGS__) -#define vwadd_wv_i16m4_m(...) __riscv_vwadd_wv_i16m4_tumu(__VA_ARGS__) -#define vwadd_wx_i16m4_m(...) __riscv_vwadd_wx_i16m4_tumu(__VA_ARGS__) -#define vwadd_vv_i16m8_m(...) __riscv_vwadd_vv_i16m8_tumu(__VA_ARGS__) -#define vwadd_vx_i16m8_m(...) __riscv_vwadd_vx_i16m8_tumu(__VA_ARGS__) -#define vwadd_wv_i16m8_m(...) __riscv_vwadd_wv_i16m8_tumu(__VA_ARGS__) -#define vwadd_wx_i16m8_m(...) __riscv_vwadd_wx_i16m8_tumu(__VA_ARGS__) -#define vwadd_vv_i32mf2_m(...) __riscv_vwadd_vv_i32mf2_tumu(__VA_ARGS__) -#define vwadd_vx_i32mf2_m(...) __riscv_vwadd_vx_i32mf2_tumu(__VA_ARGS__) -#define vwadd_wv_i32mf2_m(...) __riscv_vwadd_wv_i32mf2_tumu(__VA_ARGS__) -#define vwadd_wx_i32mf2_m(...) __riscv_vwadd_wx_i32mf2_tumu(__VA_ARGS__) -#define vwadd_vv_i32m1_m(...) __riscv_vwadd_vv_i32m1_tumu(__VA_ARGS__) -#define vwadd_vx_i32m1_m(...) __riscv_vwadd_vx_i32m1_tumu(__VA_ARGS__) -#define vwadd_wv_i32m1_m(...) __riscv_vwadd_wv_i32m1_tumu(__VA_ARGS__) -#define vwadd_wx_i32m1_m(...) __riscv_vwadd_wx_i32m1_tumu(__VA_ARGS__) -#define vwadd_vv_i32m2_m(...) __riscv_vwadd_vv_i32m2_tumu(__VA_ARGS__) -#define vwadd_vx_i32m2_m(...) __riscv_vwadd_vx_i32m2_tumu(__VA_ARGS__) -#define vwadd_wv_i32m2_m(...) __riscv_vwadd_wv_i32m2_tumu(__VA_ARGS__) -#define vwadd_wx_i32m2_m(...) __riscv_vwadd_wx_i32m2_tumu(__VA_ARGS__) -#define vwadd_vv_i32m4_m(...) __riscv_vwadd_vv_i32m4_tumu(__VA_ARGS__) -#define vwadd_vx_i32m4_m(...) __riscv_vwadd_vx_i32m4_tumu(__VA_ARGS__) -#define vwadd_wv_i32m4_m(...) __riscv_vwadd_wv_i32m4_tumu(__VA_ARGS__) -#define vwadd_wx_i32m4_m(...) __riscv_vwadd_wx_i32m4_tumu(__VA_ARGS__) -#define vwadd_vv_i32m8_m(...) __riscv_vwadd_vv_i32m8_tumu(__VA_ARGS__) -#define vwadd_vx_i32m8_m(...) __riscv_vwadd_vx_i32m8_tumu(__VA_ARGS__) -#define vwadd_wv_i32m8_m(...) __riscv_vwadd_wv_i32m8_tumu(__VA_ARGS__) -#define vwadd_wx_i32m8_m(...) __riscv_vwadd_wx_i32m8_tumu(__VA_ARGS__) -#define vwadd_vv_i64m1_m(...) __riscv_vwadd_vv_i64m1_tumu(__VA_ARGS__) -#define vwadd_vx_i64m1_m(...) __riscv_vwadd_vx_i64m1_tumu(__VA_ARGS__) -#define vwadd_wv_i64m1_m(...) __riscv_vwadd_wv_i64m1_tumu(__VA_ARGS__) -#define vwadd_wx_i64m1_m(...) __riscv_vwadd_wx_i64m1_tumu(__VA_ARGS__) -#define vwadd_vv_i64m2_m(...) __riscv_vwadd_vv_i64m2_tumu(__VA_ARGS__) -#define vwadd_vx_i64m2_m(...) __riscv_vwadd_vx_i64m2_tumu(__VA_ARGS__) -#define vwadd_wv_i64m2_m(...) __riscv_vwadd_wv_i64m2_tumu(__VA_ARGS__) -#define vwadd_wx_i64m2_m(...) __riscv_vwadd_wx_i64m2_tumu(__VA_ARGS__) -#define vwadd_vv_i64m4_m(...) __riscv_vwadd_vv_i64m4_tumu(__VA_ARGS__) -#define vwadd_vx_i64m4_m(...) __riscv_vwadd_vx_i64m4_tumu(__VA_ARGS__) -#define vwadd_wv_i64m4_m(...) __riscv_vwadd_wv_i64m4_tumu(__VA_ARGS__) -#define vwadd_wx_i64m4_m(...) __riscv_vwadd_wx_i64m4_tumu(__VA_ARGS__) -#define vwadd_vv_i64m8_m(...) __riscv_vwadd_vv_i64m8_tumu(__VA_ARGS__) -#define vwadd_vx_i64m8_m(...) __riscv_vwadd_vx_i64m8_tumu(__VA_ARGS__) -#define vwadd_wv_i64m8_m(...) __riscv_vwadd_wv_i64m8_tumu(__VA_ARGS__) -#define vwadd_wx_i64m8_m(...) __riscv_vwadd_wx_i64m8_tumu(__VA_ARGS__) -#define vwsub_vv_i16mf4_m(...) __riscv_vwsub_vv_i16mf4_tumu(__VA_ARGS__) -#define vwsub_vx_i16mf4_m(...) __riscv_vwsub_vx_i16mf4_tumu(__VA_ARGS__) -#define vwsub_wv_i16mf4_m(...) __riscv_vwsub_wv_i16mf4_tumu(__VA_ARGS__) -#define vwsub_wx_i16mf4_m(...) __riscv_vwsub_wx_i16mf4_tumu(__VA_ARGS__) -#define vwsub_vv_i16mf2_m(...) __riscv_vwsub_vv_i16mf2_tumu(__VA_ARGS__) -#define vwsub_vx_i16mf2_m(...) __riscv_vwsub_vx_i16mf2_tumu(__VA_ARGS__) -#define vwsub_wv_i16mf2_m(...) __riscv_vwsub_wv_i16mf2_tumu(__VA_ARGS__) -#define vwsub_wx_i16mf2_m(...) __riscv_vwsub_wx_i16mf2_tumu(__VA_ARGS__) -#define vwsub_vv_i16m1_m(...) __riscv_vwsub_vv_i16m1_tumu(__VA_ARGS__) -#define vwsub_vx_i16m1_m(...) __riscv_vwsub_vx_i16m1_tumu(__VA_ARGS__) -#define vwsub_wv_i16m1_m(...) __riscv_vwsub_wv_i16m1_tumu(__VA_ARGS__) -#define vwsub_wx_i16m1_m(...) __riscv_vwsub_wx_i16m1_tumu(__VA_ARGS__) -#define vwsub_vv_i16m2_m(...) __riscv_vwsub_vv_i16m2_tumu(__VA_ARGS__) -#define vwsub_vx_i16m2_m(...) __riscv_vwsub_vx_i16m2_tumu(__VA_ARGS__) -#define vwsub_wv_i16m2_m(...) __riscv_vwsub_wv_i16m2_tumu(__VA_ARGS__) -#define vwsub_wx_i16m2_m(...) __riscv_vwsub_wx_i16m2_tumu(__VA_ARGS__) -#define vwsub_vv_i16m4_m(...) __riscv_vwsub_vv_i16m4_tumu(__VA_ARGS__) -#define vwsub_vx_i16m4_m(...) __riscv_vwsub_vx_i16m4_tumu(__VA_ARGS__) -#define vwsub_wv_i16m4_m(...) __riscv_vwsub_wv_i16m4_tumu(__VA_ARGS__) -#define vwsub_wx_i16m4_m(...) __riscv_vwsub_wx_i16m4_tumu(__VA_ARGS__) -#define vwsub_vv_i16m8_m(...) __riscv_vwsub_vv_i16m8_tumu(__VA_ARGS__) -#define vwsub_vx_i16m8_m(...) __riscv_vwsub_vx_i16m8_tumu(__VA_ARGS__) -#define vwsub_wv_i16m8_m(...) __riscv_vwsub_wv_i16m8_tumu(__VA_ARGS__) -#define vwsub_wx_i16m8_m(...) __riscv_vwsub_wx_i16m8_tumu(__VA_ARGS__) -#define vwsub_vv_i32mf2_m(...) __riscv_vwsub_vv_i32mf2_tumu(__VA_ARGS__) -#define vwsub_vx_i32mf2_m(...) __riscv_vwsub_vx_i32mf2_tumu(__VA_ARGS__) -#define vwsub_wv_i32mf2_m(...) __riscv_vwsub_wv_i32mf2_tumu(__VA_ARGS__) -#define vwsub_wx_i32mf2_m(...) __riscv_vwsub_wx_i32mf2_tumu(__VA_ARGS__) -#define vwsub_vv_i32m1_m(...) __riscv_vwsub_vv_i32m1_tumu(__VA_ARGS__) -#define vwsub_vx_i32m1_m(...) __riscv_vwsub_vx_i32m1_tumu(__VA_ARGS__) -#define vwsub_wv_i32m1_m(...) __riscv_vwsub_wv_i32m1_tumu(__VA_ARGS__) -#define vwsub_wx_i32m1_m(...) __riscv_vwsub_wx_i32m1_tumu(__VA_ARGS__) -#define vwsub_vv_i32m2_m(...) __riscv_vwsub_vv_i32m2_tumu(__VA_ARGS__) -#define vwsub_vx_i32m2_m(...) __riscv_vwsub_vx_i32m2_tumu(__VA_ARGS__) -#define vwsub_wv_i32m2_m(...) __riscv_vwsub_wv_i32m2_tumu(__VA_ARGS__) -#define vwsub_wx_i32m2_m(...) __riscv_vwsub_wx_i32m2_tumu(__VA_ARGS__) -#define vwsub_vv_i32m4_m(...) __riscv_vwsub_vv_i32m4_tumu(__VA_ARGS__) -#define vwsub_vx_i32m4_m(...) __riscv_vwsub_vx_i32m4_tumu(__VA_ARGS__) -#define vwsub_wv_i32m4_m(...) __riscv_vwsub_wv_i32m4_tumu(__VA_ARGS__) -#define vwsub_wx_i32m4_m(...) __riscv_vwsub_wx_i32m4_tumu(__VA_ARGS__) -#define vwsub_vv_i32m8_m(...) __riscv_vwsub_vv_i32m8_tumu(__VA_ARGS__) -#define vwsub_vx_i32m8_m(...) __riscv_vwsub_vx_i32m8_tumu(__VA_ARGS__) -#define vwsub_wv_i32m8_m(...) __riscv_vwsub_wv_i32m8_tumu(__VA_ARGS__) -#define vwsub_wx_i32m8_m(...) __riscv_vwsub_wx_i32m8_tumu(__VA_ARGS__) -#define vwsub_vv_i64m1_m(...) __riscv_vwsub_vv_i64m1_tumu(__VA_ARGS__) -#define vwsub_vx_i64m1_m(...) __riscv_vwsub_vx_i64m1_tumu(__VA_ARGS__) -#define vwsub_wv_i64m1_m(...) __riscv_vwsub_wv_i64m1_tumu(__VA_ARGS__) -#define vwsub_wx_i64m1_m(...) __riscv_vwsub_wx_i64m1_tumu(__VA_ARGS__) -#define vwsub_vv_i64m2_m(...) __riscv_vwsub_vv_i64m2_tumu(__VA_ARGS__) -#define vwsub_vx_i64m2_m(...) __riscv_vwsub_vx_i64m2_tumu(__VA_ARGS__) -#define vwsub_wv_i64m2_m(...) __riscv_vwsub_wv_i64m2_tumu(__VA_ARGS__) -#define vwsub_wx_i64m2_m(...) __riscv_vwsub_wx_i64m2_tumu(__VA_ARGS__) -#define vwsub_vv_i64m4_m(...) __riscv_vwsub_vv_i64m4_tumu(__VA_ARGS__) -#define vwsub_vx_i64m4_m(...) __riscv_vwsub_vx_i64m4_tumu(__VA_ARGS__) -#define vwsub_wv_i64m4_m(...) __riscv_vwsub_wv_i64m4_tumu(__VA_ARGS__) -#define vwsub_wx_i64m4_m(...) __riscv_vwsub_wx_i64m4_tumu(__VA_ARGS__) -#define vwsub_vv_i64m8_m(...) __riscv_vwsub_vv_i64m8_tumu(__VA_ARGS__) -#define vwsub_vx_i64m8_m(...) __riscv_vwsub_vx_i64m8_tumu(__VA_ARGS__) -#define vwsub_wv_i64m8_m(...) __riscv_vwsub_wv_i64m8_tumu(__VA_ARGS__) -#define vwsub_wx_i64m8_m(...) __riscv_vwsub_wx_i64m8_tumu(__VA_ARGS__) -#define vwaddu_vv_u16mf4_m(...) __riscv_vwaddu_vv_u16mf4_tumu(__VA_ARGS__) -#define vwaddu_vx_u16mf4_m(...) __riscv_vwaddu_vx_u16mf4_tumu(__VA_ARGS__) -#define vwaddu_wv_u16mf4_m(...) __riscv_vwaddu_wv_u16mf4_tumu(__VA_ARGS__) -#define vwaddu_wx_u16mf4_m(...) __riscv_vwaddu_wx_u16mf4_tumu(__VA_ARGS__) -#define vwaddu_vv_u16mf2_m(...) __riscv_vwaddu_vv_u16mf2_tumu(__VA_ARGS__) -#define vwaddu_vx_u16mf2_m(...) __riscv_vwaddu_vx_u16mf2_tumu(__VA_ARGS__) -#define vwaddu_wv_u16mf2_m(...) __riscv_vwaddu_wv_u16mf2_tumu(__VA_ARGS__) -#define vwaddu_wx_u16mf2_m(...) __riscv_vwaddu_wx_u16mf2_tumu(__VA_ARGS__) -#define vwaddu_vv_u16m1_m(...) __riscv_vwaddu_vv_u16m1_tumu(__VA_ARGS__) -#define vwaddu_vx_u16m1_m(...) __riscv_vwaddu_vx_u16m1_tumu(__VA_ARGS__) -#define vwaddu_wv_u16m1_m(...) __riscv_vwaddu_wv_u16m1_tumu(__VA_ARGS__) -#define vwaddu_wx_u16m1_m(...) __riscv_vwaddu_wx_u16m1_tumu(__VA_ARGS__) -#define vwaddu_vv_u16m2_m(...) __riscv_vwaddu_vv_u16m2_tumu(__VA_ARGS__) -#define vwaddu_vx_u16m2_m(...) __riscv_vwaddu_vx_u16m2_tumu(__VA_ARGS__) -#define vwaddu_wv_u16m2_m(...) __riscv_vwaddu_wv_u16m2_tumu(__VA_ARGS__) -#define vwaddu_wx_u16m2_m(...) __riscv_vwaddu_wx_u16m2_tumu(__VA_ARGS__) -#define vwaddu_vv_u16m4_m(...) __riscv_vwaddu_vv_u16m4_tumu(__VA_ARGS__) -#define vwaddu_vx_u16m4_m(...) __riscv_vwaddu_vx_u16m4_tumu(__VA_ARGS__) -#define vwaddu_wv_u16m4_m(...) __riscv_vwaddu_wv_u16m4_tumu(__VA_ARGS__) -#define vwaddu_wx_u16m4_m(...) __riscv_vwaddu_wx_u16m4_tumu(__VA_ARGS__) -#define vwaddu_vv_u16m8_m(...) __riscv_vwaddu_vv_u16m8_tumu(__VA_ARGS__) -#define vwaddu_vx_u16m8_m(...) __riscv_vwaddu_vx_u16m8_tumu(__VA_ARGS__) -#define vwaddu_wv_u16m8_m(...) __riscv_vwaddu_wv_u16m8_tumu(__VA_ARGS__) -#define vwaddu_wx_u16m8_m(...) __riscv_vwaddu_wx_u16m8_tumu(__VA_ARGS__) -#define vwaddu_vv_u32mf2_m(...) __riscv_vwaddu_vv_u32mf2_tumu(__VA_ARGS__) -#define vwaddu_vx_u32mf2_m(...) __riscv_vwaddu_vx_u32mf2_tumu(__VA_ARGS__) -#define vwaddu_wv_u32mf2_m(...) __riscv_vwaddu_wv_u32mf2_tumu(__VA_ARGS__) -#define vwaddu_wx_u32mf2_m(...) __riscv_vwaddu_wx_u32mf2_tumu(__VA_ARGS__) -#define vwaddu_vv_u32m1_m(...) __riscv_vwaddu_vv_u32m1_tumu(__VA_ARGS__) -#define vwaddu_vx_u32m1_m(...) __riscv_vwaddu_vx_u32m1_tumu(__VA_ARGS__) -#define vwaddu_wv_u32m1_m(...) __riscv_vwaddu_wv_u32m1_tumu(__VA_ARGS__) -#define vwaddu_wx_u32m1_m(...) __riscv_vwaddu_wx_u32m1_tumu(__VA_ARGS__) -#define vwaddu_vv_u32m2_m(...) __riscv_vwaddu_vv_u32m2_tumu(__VA_ARGS__) -#define vwaddu_vx_u32m2_m(...) __riscv_vwaddu_vx_u32m2_tumu(__VA_ARGS__) -#define vwaddu_wv_u32m2_m(...) __riscv_vwaddu_wv_u32m2_tumu(__VA_ARGS__) -#define vwaddu_wx_u32m2_m(...) __riscv_vwaddu_wx_u32m2_tumu(__VA_ARGS__) -#define vwaddu_vv_u32m4_m(...) __riscv_vwaddu_vv_u32m4_tumu(__VA_ARGS__) -#define vwaddu_vx_u32m4_m(...) __riscv_vwaddu_vx_u32m4_tumu(__VA_ARGS__) -#define vwaddu_wv_u32m4_m(...) __riscv_vwaddu_wv_u32m4_tumu(__VA_ARGS__) -#define vwaddu_wx_u32m4_m(...) __riscv_vwaddu_wx_u32m4_tumu(__VA_ARGS__) -#define vwaddu_vv_u32m8_m(...) __riscv_vwaddu_vv_u32m8_tumu(__VA_ARGS__) -#define vwaddu_vx_u32m8_m(...) __riscv_vwaddu_vx_u32m8_tumu(__VA_ARGS__) -#define vwaddu_wv_u32m8_m(...) __riscv_vwaddu_wv_u32m8_tumu(__VA_ARGS__) -#define vwaddu_wx_u32m8_m(...) __riscv_vwaddu_wx_u32m8_tumu(__VA_ARGS__) -#define vwaddu_vv_u64m1_m(...) __riscv_vwaddu_vv_u64m1_tumu(__VA_ARGS__) -#define vwaddu_vx_u64m1_m(...) __riscv_vwaddu_vx_u64m1_tumu(__VA_ARGS__) -#define vwaddu_wv_u64m1_m(...) __riscv_vwaddu_wv_u64m1_tumu(__VA_ARGS__) -#define vwaddu_wx_u64m1_m(...) __riscv_vwaddu_wx_u64m1_tumu(__VA_ARGS__) -#define vwaddu_vv_u64m2_m(...) __riscv_vwaddu_vv_u64m2_tumu(__VA_ARGS__) -#define vwaddu_vx_u64m2_m(...) __riscv_vwaddu_vx_u64m2_tumu(__VA_ARGS__) -#define vwaddu_wv_u64m2_m(...) __riscv_vwaddu_wv_u64m2_tumu(__VA_ARGS__) -#define vwaddu_wx_u64m2_m(...) __riscv_vwaddu_wx_u64m2_tumu(__VA_ARGS__) -#define vwaddu_vv_u64m4_m(...) __riscv_vwaddu_vv_u64m4_tumu(__VA_ARGS__) -#define vwaddu_vx_u64m4_m(...) __riscv_vwaddu_vx_u64m4_tumu(__VA_ARGS__) -#define vwaddu_wv_u64m4_m(...) __riscv_vwaddu_wv_u64m4_tumu(__VA_ARGS__) -#define vwaddu_wx_u64m4_m(...) __riscv_vwaddu_wx_u64m4_tumu(__VA_ARGS__) -#define vwaddu_vv_u64m8_m(...) __riscv_vwaddu_vv_u64m8_tumu(__VA_ARGS__) -#define vwaddu_vx_u64m8_m(...) __riscv_vwaddu_vx_u64m8_tumu(__VA_ARGS__) -#define vwaddu_wv_u64m8_m(...) __riscv_vwaddu_wv_u64m8_tumu(__VA_ARGS__) -#define vwaddu_wx_u64m8_m(...) __riscv_vwaddu_wx_u64m8_tumu(__VA_ARGS__) -#define vwsubu_vv_u16mf4_m(...) __riscv_vwsubu_vv_u16mf4_tumu(__VA_ARGS__) -#define vwsubu_vx_u16mf4_m(...) __riscv_vwsubu_vx_u16mf4_tumu(__VA_ARGS__) -#define vwsubu_wv_u16mf4_m(...) __riscv_vwsubu_wv_u16mf4_tumu(__VA_ARGS__) -#define vwsubu_wx_u16mf4_m(...) __riscv_vwsubu_wx_u16mf4_tumu(__VA_ARGS__) -#define vwsubu_vv_u16mf2_m(...) __riscv_vwsubu_vv_u16mf2_tumu(__VA_ARGS__) -#define vwsubu_vx_u16mf2_m(...) __riscv_vwsubu_vx_u16mf2_tumu(__VA_ARGS__) -#define vwsubu_wv_u16mf2_m(...) __riscv_vwsubu_wv_u16mf2_tumu(__VA_ARGS__) -#define vwsubu_wx_u16mf2_m(...) __riscv_vwsubu_wx_u16mf2_tumu(__VA_ARGS__) -#define vwsubu_vv_u16m1_m(...) __riscv_vwsubu_vv_u16m1_tumu(__VA_ARGS__) -#define vwsubu_vx_u16m1_m(...) __riscv_vwsubu_vx_u16m1_tumu(__VA_ARGS__) -#define vwsubu_wv_u16m1_m(...) __riscv_vwsubu_wv_u16m1_tumu(__VA_ARGS__) -#define vwsubu_wx_u16m1_m(...) __riscv_vwsubu_wx_u16m1_tumu(__VA_ARGS__) -#define vwsubu_vv_u16m2_m(...) __riscv_vwsubu_vv_u16m2_tumu(__VA_ARGS__) -#define vwsubu_vx_u16m2_m(...) __riscv_vwsubu_vx_u16m2_tumu(__VA_ARGS__) -#define vwsubu_wv_u16m2_m(...) __riscv_vwsubu_wv_u16m2_tumu(__VA_ARGS__) -#define vwsubu_wx_u16m2_m(...) __riscv_vwsubu_wx_u16m2_tumu(__VA_ARGS__) -#define vwsubu_vv_u16m4_m(...) __riscv_vwsubu_vv_u16m4_tumu(__VA_ARGS__) -#define vwsubu_vx_u16m4_m(...) __riscv_vwsubu_vx_u16m4_tumu(__VA_ARGS__) -#define vwsubu_wv_u16m4_m(...) __riscv_vwsubu_wv_u16m4_tumu(__VA_ARGS__) -#define vwsubu_wx_u16m4_m(...) __riscv_vwsubu_wx_u16m4_tumu(__VA_ARGS__) -#define vwsubu_vv_u16m8_m(...) __riscv_vwsubu_vv_u16m8_tumu(__VA_ARGS__) -#define vwsubu_vx_u16m8_m(...) __riscv_vwsubu_vx_u16m8_tumu(__VA_ARGS__) -#define vwsubu_wv_u16m8_m(...) __riscv_vwsubu_wv_u16m8_tumu(__VA_ARGS__) -#define vwsubu_wx_u16m8_m(...) __riscv_vwsubu_wx_u16m8_tumu(__VA_ARGS__) -#define vwsubu_vv_u32mf2_m(...) __riscv_vwsubu_vv_u32mf2_tumu(__VA_ARGS__) -#define vwsubu_vx_u32mf2_m(...) __riscv_vwsubu_vx_u32mf2_tumu(__VA_ARGS__) -#define vwsubu_wv_u32mf2_m(...) __riscv_vwsubu_wv_u32mf2_tumu(__VA_ARGS__) -#define vwsubu_wx_u32mf2_m(...) __riscv_vwsubu_wx_u32mf2_tumu(__VA_ARGS__) -#define vwsubu_vv_u32m1_m(...) __riscv_vwsubu_vv_u32m1_tumu(__VA_ARGS__) -#define vwsubu_vx_u32m1_m(...) __riscv_vwsubu_vx_u32m1_tumu(__VA_ARGS__) -#define vwsubu_wv_u32m1_m(...) __riscv_vwsubu_wv_u32m1_tumu(__VA_ARGS__) -#define vwsubu_wx_u32m1_m(...) __riscv_vwsubu_wx_u32m1_tumu(__VA_ARGS__) -#define vwsubu_vv_u32m2_m(...) __riscv_vwsubu_vv_u32m2_tumu(__VA_ARGS__) -#define vwsubu_vx_u32m2_m(...) __riscv_vwsubu_vx_u32m2_tumu(__VA_ARGS__) -#define vwsubu_wv_u32m2_m(...) __riscv_vwsubu_wv_u32m2_tumu(__VA_ARGS__) -#define vwsubu_wx_u32m2_m(...) __riscv_vwsubu_wx_u32m2_tumu(__VA_ARGS__) -#define vwsubu_vv_u32m4_m(...) __riscv_vwsubu_vv_u32m4_tumu(__VA_ARGS__) -#define vwsubu_vx_u32m4_m(...) __riscv_vwsubu_vx_u32m4_tumu(__VA_ARGS__) -#define vwsubu_wv_u32m4_m(...) __riscv_vwsubu_wv_u32m4_tumu(__VA_ARGS__) -#define vwsubu_wx_u32m4_m(...) __riscv_vwsubu_wx_u32m4_tumu(__VA_ARGS__) -#define vwsubu_vv_u32m8_m(...) __riscv_vwsubu_vv_u32m8_tumu(__VA_ARGS__) -#define vwsubu_vx_u32m8_m(...) __riscv_vwsubu_vx_u32m8_tumu(__VA_ARGS__) -#define vwsubu_wv_u32m8_m(...) __riscv_vwsubu_wv_u32m8_tumu(__VA_ARGS__) -#define vwsubu_wx_u32m8_m(...) __riscv_vwsubu_wx_u32m8_tumu(__VA_ARGS__) -#define vwsubu_vv_u64m1_m(...) __riscv_vwsubu_vv_u64m1_tumu(__VA_ARGS__) -#define vwsubu_vx_u64m1_m(...) __riscv_vwsubu_vx_u64m1_tumu(__VA_ARGS__) -#define vwsubu_wv_u64m1_m(...) __riscv_vwsubu_wv_u64m1_tumu(__VA_ARGS__) -#define vwsubu_wx_u64m1_m(...) __riscv_vwsubu_wx_u64m1_tumu(__VA_ARGS__) -#define vwsubu_vv_u64m2_m(...) __riscv_vwsubu_vv_u64m2_tumu(__VA_ARGS__) -#define vwsubu_vx_u64m2_m(...) __riscv_vwsubu_vx_u64m2_tumu(__VA_ARGS__) -#define vwsubu_wv_u64m2_m(...) __riscv_vwsubu_wv_u64m2_tumu(__VA_ARGS__) -#define vwsubu_wx_u64m2_m(...) __riscv_vwsubu_wx_u64m2_tumu(__VA_ARGS__) -#define vwsubu_vv_u64m4_m(...) __riscv_vwsubu_vv_u64m4_tumu(__VA_ARGS__) -#define vwsubu_vx_u64m4_m(...) __riscv_vwsubu_vx_u64m4_tumu(__VA_ARGS__) -#define vwsubu_wv_u64m4_m(...) __riscv_vwsubu_wv_u64m4_tumu(__VA_ARGS__) -#define vwsubu_wx_u64m4_m(...) __riscv_vwsubu_wx_u64m4_tumu(__VA_ARGS__) -#define vwsubu_vv_u64m8_m(...) __riscv_vwsubu_vv_u64m8_tumu(__VA_ARGS__) -#define vwsubu_vx_u64m8_m(...) __riscv_vwsubu_vx_u64m8_tumu(__VA_ARGS__) -#define vwsubu_wv_u64m8_m(...) __riscv_vwsubu_wv_u64m8_tumu(__VA_ARGS__) -#define vwsubu_wx_u64m8_m(...) __riscv_vwsubu_wx_u64m8_tumu(__VA_ARGS__) -#define vsext_vf2_i16mf4(...) __riscv_vsext_vf2_i16mf4(__VA_ARGS__) -#define vsext_vf2_i16mf2(...) __riscv_vsext_vf2_i16mf2(__VA_ARGS__) -#define vsext_vf2_i16m1(...) __riscv_vsext_vf2_i16m1(__VA_ARGS__) -#define vsext_vf2_i16m2(...) __riscv_vsext_vf2_i16m2(__VA_ARGS__) -#define vsext_vf2_i16m4(...) __riscv_vsext_vf2_i16m4(__VA_ARGS__) -#define vsext_vf2_i16m8(...) __riscv_vsext_vf2_i16m8(__VA_ARGS__) -#define vsext_vf4_i32mf2(...) __riscv_vsext_vf4_i32mf2(__VA_ARGS__) -#define vsext_vf4_i32m1(...) __riscv_vsext_vf4_i32m1(__VA_ARGS__) -#define vsext_vf4_i32m2(...) __riscv_vsext_vf4_i32m2(__VA_ARGS__) -#define vsext_vf4_i32m4(...) __riscv_vsext_vf4_i32m4(__VA_ARGS__) -#define vsext_vf4_i32m8(...) __riscv_vsext_vf4_i32m8(__VA_ARGS__) -#define vsext_vf8_i64m1(...) __riscv_vsext_vf8_i64m1(__VA_ARGS__) -#define vsext_vf8_i64m2(...) __riscv_vsext_vf8_i64m2(__VA_ARGS__) -#define vsext_vf8_i64m4(...) __riscv_vsext_vf8_i64m4(__VA_ARGS__) -#define vsext_vf8_i64m8(...) __riscv_vsext_vf8_i64m8(__VA_ARGS__) -#define vsext_vf2_i32mf2(...) __riscv_vsext_vf2_i32mf2(__VA_ARGS__) -#define vsext_vf2_i32m1(...) __riscv_vsext_vf2_i32m1(__VA_ARGS__) -#define vsext_vf2_i32m2(...) __riscv_vsext_vf2_i32m2(__VA_ARGS__) -#define vsext_vf2_i32m4(...) __riscv_vsext_vf2_i32m4(__VA_ARGS__) -#define vsext_vf2_i32m8(...) __riscv_vsext_vf2_i32m8(__VA_ARGS__) -#define vsext_vf4_i64m1(...) __riscv_vsext_vf4_i64m1(__VA_ARGS__) -#define vsext_vf4_i64m2(...) __riscv_vsext_vf4_i64m2(__VA_ARGS__) -#define vsext_vf4_i64m4(...) __riscv_vsext_vf4_i64m4(__VA_ARGS__) -#define vsext_vf4_i64m8(...) __riscv_vsext_vf4_i64m8(__VA_ARGS__) -#define vsext_vf2_i64m1(...) __riscv_vsext_vf2_i64m1(__VA_ARGS__) -#define vsext_vf2_i64m2(...) __riscv_vsext_vf2_i64m2(__VA_ARGS__) -#define vsext_vf2_i64m4(...) __riscv_vsext_vf2_i64m4(__VA_ARGS__) -#define vsext_vf2_i64m8(...) __riscv_vsext_vf2_i64m8(__VA_ARGS__) -#define vzext_vf2_u16mf4(...) __riscv_vzext_vf2_u16mf4(__VA_ARGS__) -#define vzext_vf2_u16mf2(...) __riscv_vzext_vf2_u16mf2(__VA_ARGS__) -#define vzext_vf2_u16m1(...) __riscv_vzext_vf2_u16m1(__VA_ARGS__) -#define vzext_vf2_u16m2(...) __riscv_vzext_vf2_u16m2(__VA_ARGS__) -#define vzext_vf2_u16m4(...) __riscv_vzext_vf2_u16m4(__VA_ARGS__) -#define vzext_vf2_u16m8(...) __riscv_vzext_vf2_u16m8(__VA_ARGS__) -#define vzext_vf4_u32mf2(...) __riscv_vzext_vf4_u32mf2(__VA_ARGS__) -#define vzext_vf4_u32m1(...) __riscv_vzext_vf4_u32m1(__VA_ARGS__) -#define vzext_vf4_u32m2(...) __riscv_vzext_vf4_u32m2(__VA_ARGS__) -#define vzext_vf4_u32m4(...) __riscv_vzext_vf4_u32m4(__VA_ARGS__) -#define vzext_vf4_u32m8(...) __riscv_vzext_vf4_u32m8(__VA_ARGS__) -#define vzext_vf8_u64m1(...) __riscv_vzext_vf8_u64m1(__VA_ARGS__) -#define vzext_vf8_u64m2(...) __riscv_vzext_vf8_u64m2(__VA_ARGS__) -#define vzext_vf8_u64m4(...) __riscv_vzext_vf8_u64m4(__VA_ARGS__) -#define vzext_vf8_u64m8(...) __riscv_vzext_vf8_u64m8(__VA_ARGS__) -#define vzext_vf2_u32mf2(...) __riscv_vzext_vf2_u32mf2(__VA_ARGS__) -#define vzext_vf2_u32m1(...) __riscv_vzext_vf2_u32m1(__VA_ARGS__) -#define vzext_vf2_u32m2(...) __riscv_vzext_vf2_u32m2(__VA_ARGS__) -#define vzext_vf2_u32m4(...) __riscv_vzext_vf2_u32m4(__VA_ARGS__) -#define vzext_vf2_u32m8(...) __riscv_vzext_vf2_u32m8(__VA_ARGS__) -#define vzext_vf4_u64m1(...) __riscv_vzext_vf4_u64m1(__VA_ARGS__) -#define vzext_vf4_u64m2(...) __riscv_vzext_vf4_u64m2(__VA_ARGS__) -#define vzext_vf4_u64m4(...) __riscv_vzext_vf4_u64m4(__VA_ARGS__) -#define vzext_vf4_u64m8(...) __riscv_vzext_vf4_u64m8(__VA_ARGS__) -#define vzext_vf2_u64m1(...) __riscv_vzext_vf2_u64m1(__VA_ARGS__) -#define vzext_vf2_u64m2(...) __riscv_vzext_vf2_u64m2(__VA_ARGS__) -#define vzext_vf2_u64m4(...) __riscv_vzext_vf2_u64m4(__VA_ARGS__) -#define vzext_vf2_u64m8(...) __riscv_vzext_vf2_u64m8(__VA_ARGS__) -// masked functions -#define vsext_vf2_i16mf4_m(...) __riscv_vsext_vf2_i16mf4_tumu(__VA_ARGS__) -#define vsext_vf2_i16mf2_m(...) __riscv_vsext_vf2_i16mf2_tumu(__VA_ARGS__) -#define vsext_vf2_i16m1_m(...) __riscv_vsext_vf2_i16m1_tumu(__VA_ARGS__) -#define vsext_vf2_i16m2_m(...) __riscv_vsext_vf2_i16m2_tumu(__VA_ARGS__) -#define vsext_vf2_i16m4_m(...) __riscv_vsext_vf2_i16m4_tumu(__VA_ARGS__) -#define vsext_vf2_i16m8_m(...) __riscv_vsext_vf2_i16m8_tumu(__VA_ARGS__) -#define vsext_vf4_i32mf2_m(...) __riscv_vsext_vf4_i32mf2_tumu(__VA_ARGS__) -#define vsext_vf4_i32m1_m(...) __riscv_vsext_vf4_i32m1_tumu(__VA_ARGS__) -#define vsext_vf4_i32m2_m(...) __riscv_vsext_vf4_i32m2_tumu(__VA_ARGS__) -#define vsext_vf4_i32m4_m(...) __riscv_vsext_vf4_i32m4_tumu(__VA_ARGS__) -#define vsext_vf4_i32m8_m(...) __riscv_vsext_vf4_i32m8_tumu(__VA_ARGS__) -#define vsext_vf8_i64m1_m(...) __riscv_vsext_vf8_i64m1_tumu(__VA_ARGS__) -#define vsext_vf8_i64m2_m(...) __riscv_vsext_vf8_i64m2_tumu(__VA_ARGS__) -#define vsext_vf8_i64m4_m(...) __riscv_vsext_vf8_i64m4_tumu(__VA_ARGS__) -#define vsext_vf8_i64m8_m(...) __riscv_vsext_vf8_i64m8_tumu(__VA_ARGS__) -#define vsext_vf2_i32mf2_m(...) __riscv_vsext_vf2_i32mf2_tumu(__VA_ARGS__) -#define vsext_vf2_i32m1_m(...) __riscv_vsext_vf2_i32m1_tumu(__VA_ARGS__) -#define vsext_vf2_i32m2_m(...) __riscv_vsext_vf2_i32m2_tumu(__VA_ARGS__) -#define vsext_vf2_i32m4_m(...) __riscv_vsext_vf2_i32m4_tumu(__VA_ARGS__) -#define vsext_vf2_i32m8_m(...) __riscv_vsext_vf2_i32m8_tumu(__VA_ARGS__) -#define vsext_vf4_i64m1_m(...) __riscv_vsext_vf4_i64m1_tumu(__VA_ARGS__) -#define vsext_vf4_i64m2_m(...) __riscv_vsext_vf4_i64m2_tumu(__VA_ARGS__) -#define vsext_vf4_i64m4_m(...) __riscv_vsext_vf4_i64m4_tumu(__VA_ARGS__) -#define vsext_vf4_i64m8_m(...) __riscv_vsext_vf4_i64m8_tumu(__VA_ARGS__) -#define vsext_vf2_i64m1_m(...) __riscv_vsext_vf2_i64m1_tumu(__VA_ARGS__) -#define vsext_vf2_i64m2_m(...) __riscv_vsext_vf2_i64m2_tumu(__VA_ARGS__) -#define vsext_vf2_i64m4_m(...) __riscv_vsext_vf2_i64m4_tumu(__VA_ARGS__) -#define vsext_vf2_i64m8_m(...) __riscv_vsext_vf2_i64m8_tumu(__VA_ARGS__) -#define vzext_vf2_u16mf4_m(...) __riscv_vzext_vf2_u16mf4_tumu(__VA_ARGS__) -#define vzext_vf2_u16mf2_m(...) __riscv_vzext_vf2_u16mf2_tumu(__VA_ARGS__) -#define vzext_vf2_u16m1_m(...) __riscv_vzext_vf2_u16m1_tumu(__VA_ARGS__) -#define vzext_vf2_u16m2_m(...) __riscv_vzext_vf2_u16m2_tumu(__VA_ARGS__) -#define vzext_vf2_u16m4_m(...) __riscv_vzext_vf2_u16m4_tumu(__VA_ARGS__) -#define vzext_vf2_u16m8_m(...) __riscv_vzext_vf2_u16m8_tumu(__VA_ARGS__) -#define vzext_vf4_u32mf2_m(...) __riscv_vzext_vf4_u32mf2_tumu(__VA_ARGS__) -#define vzext_vf4_u32m1_m(...) __riscv_vzext_vf4_u32m1_tumu(__VA_ARGS__) -#define vzext_vf4_u32m2_m(...) __riscv_vzext_vf4_u32m2_tumu(__VA_ARGS__) -#define vzext_vf4_u32m4_m(...) __riscv_vzext_vf4_u32m4_tumu(__VA_ARGS__) -#define vzext_vf4_u32m8_m(...) __riscv_vzext_vf4_u32m8_tumu(__VA_ARGS__) -#define vzext_vf8_u64m1_m(...) __riscv_vzext_vf8_u64m1_tumu(__VA_ARGS__) -#define vzext_vf8_u64m2_m(...) __riscv_vzext_vf8_u64m2_tumu(__VA_ARGS__) -#define vzext_vf8_u64m4_m(...) __riscv_vzext_vf8_u64m4_tumu(__VA_ARGS__) -#define vzext_vf8_u64m8_m(...) __riscv_vzext_vf8_u64m8_tumu(__VA_ARGS__) -#define vzext_vf2_u32mf2_m(...) __riscv_vzext_vf2_u32mf2_tumu(__VA_ARGS__) -#define vzext_vf2_u32m1_m(...) __riscv_vzext_vf2_u32m1_tumu(__VA_ARGS__) -#define vzext_vf2_u32m2_m(...) __riscv_vzext_vf2_u32m2_tumu(__VA_ARGS__) -#define vzext_vf2_u32m4_m(...) __riscv_vzext_vf2_u32m4_tumu(__VA_ARGS__) -#define vzext_vf2_u32m8_m(...) __riscv_vzext_vf2_u32m8_tumu(__VA_ARGS__) -#define vzext_vf4_u64m1_m(...) __riscv_vzext_vf4_u64m1_tumu(__VA_ARGS__) -#define vzext_vf4_u64m2_m(...) __riscv_vzext_vf4_u64m2_tumu(__VA_ARGS__) -#define vzext_vf4_u64m4_m(...) __riscv_vzext_vf4_u64m4_tumu(__VA_ARGS__) -#define vzext_vf4_u64m8_m(...) __riscv_vzext_vf4_u64m8_tumu(__VA_ARGS__) -#define vzext_vf2_u64m1_m(...) __riscv_vzext_vf2_u64m1_tumu(__VA_ARGS__) -#define vzext_vf2_u64m2_m(...) __riscv_vzext_vf2_u64m2_tumu(__VA_ARGS__) -#define vzext_vf2_u64m4_m(...) __riscv_vzext_vf2_u64m4_tumu(__VA_ARGS__) -#define vzext_vf2_u64m8_m(...) __riscv_vzext_vf2_u64m8_tumu(__VA_ARGS__) -#define vadc_vvm_i8mf8(...) __riscv_vadc_vvm_i8mf8(__VA_ARGS__) -#define vadc_vxm_i8mf8(...) __riscv_vadc_vxm_i8mf8(__VA_ARGS__) -#define vadc_vvm_i8mf4(...) __riscv_vadc_vvm_i8mf4(__VA_ARGS__) -#define vadc_vxm_i8mf4(...) __riscv_vadc_vxm_i8mf4(__VA_ARGS__) -#define vadc_vvm_i8mf2(...) __riscv_vadc_vvm_i8mf2(__VA_ARGS__) -#define vadc_vxm_i8mf2(...) __riscv_vadc_vxm_i8mf2(__VA_ARGS__) -#define vadc_vvm_i8m1(...) __riscv_vadc_vvm_i8m1(__VA_ARGS__) -#define vadc_vxm_i8m1(...) __riscv_vadc_vxm_i8m1(__VA_ARGS__) -#define vadc_vvm_i8m2(...) __riscv_vadc_vvm_i8m2(__VA_ARGS__) -#define vadc_vxm_i8m2(...) __riscv_vadc_vxm_i8m2(__VA_ARGS__) -#define vadc_vvm_i8m4(...) __riscv_vadc_vvm_i8m4(__VA_ARGS__) -#define vadc_vxm_i8m4(...) __riscv_vadc_vxm_i8m4(__VA_ARGS__) -#define vadc_vvm_i8m8(...) __riscv_vadc_vvm_i8m8(__VA_ARGS__) -#define vadc_vxm_i8m8(...) __riscv_vadc_vxm_i8m8(__VA_ARGS__) -#define vadc_vvm_i16mf4(...) __riscv_vadc_vvm_i16mf4(__VA_ARGS__) -#define vadc_vxm_i16mf4(...) __riscv_vadc_vxm_i16mf4(__VA_ARGS__) -#define vadc_vvm_i16mf2(...) __riscv_vadc_vvm_i16mf2(__VA_ARGS__) -#define vadc_vxm_i16mf2(...) __riscv_vadc_vxm_i16mf2(__VA_ARGS__) -#define vadc_vvm_i16m1(...) __riscv_vadc_vvm_i16m1(__VA_ARGS__) -#define vadc_vxm_i16m1(...) __riscv_vadc_vxm_i16m1(__VA_ARGS__) -#define vadc_vvm_i16m2(...) __riscv_vadc_vvm_i16m2(__VA_ARGS__) -#define vadc_vxm_i16m2(...) __riscv_vadc_vxm_i16m2(__VA_ARGS__) -#define vadc_vvm_i16m4(...) __riscv_vadc_vvm_i16m4(__VA_ARGS__) -#define vadc_vxm_i16m4(...) __riscv_vadc_vxm_i16m4(__VA_ARGS__) -#define vadc_vvm_i16m8(...) __riscv_vadc_vvm_i16m8(__VA_ARGS__) -#define vadc_vxm_i16m8(...) __riscv_vadc_vxm_i16m8(__VA_ARGS__) -#define vadc_vvm_i32mf2(...) __riscv_vadc_vvm_i32mf2(__VA_ARGS__) -#define vadc_vxm_i32mf2(...) __riscv_vadc_vxm_i32mf2(__VA_ARGS__) -#define vadc_vvm_i32m1(...) __riscv_vadc_vvm_i32m1(__VA_ARGS__) -#define vadc_vxm_i32m1(...) __riscv_vadc_vxm_i32m1(__VA_ARGS__) -#define vadc_vvm_i32m2(...) __riscv_vadc_vvm_i32m2(__VA_ARGS__) -#define vadc_vxm_i32m2(...) __riscv_vadc_vxm_i32m2(__VA_ARGS__) -#define vadc_vvm_i32m4(...) __riscv_vadc_vvm_i32m4(__VA_ARGS__) -#define vadc_vxm_i32m4(...) __riscv_vadc_vxm_i32m4(__VA_ARGS__) -#define vadc_vvm_i32m8(...) __riscv_vadc_vvm_i32m8(__VA_ARGS__) -#define vadc_vxm_i32m8(...) __riscv_vadc_vxm_i32m8(__VA_ARGS__) -#define vadc_vvm_i64m1(...) __riscv_vadc_vvm_i64m1(__VA_ARGS__) -#define vadc_vxm_i64m1(...) __riscv_vadc_vxm_i64m1(__VA_ARGS__) -#define vadc_vvm_i64m2(...) __riscv_vadc_vvm_i64m2(__VA_ARGS__) -#define vadc_vxm_i64m2(...) __riscv_vadc_vxm_i64m2(__VA_ARGS__) -#define vadc_vvm_i64m4(...) __riscv_vadc_vvm_i64m4(__VA_ARGS__) -#define vadc_vxm_i64m4(...) __riscv_vadc_vxm_i64m4(__VA_ARGS__) -#define vadc_vvm_i64m8(...) __riscv_vadc_vvm_i64m8(__VA_ARGS__) -#define vadc_vxm_i64m8(...) __riscv_vadc_vxm_i64m8(__VA_ARGS__) -#define vsbc_vvm_i8mf8(...) __riscv_vsbc_vvm_i8mf8(__VA_ARGS__) -#define vsbc_vxm_i8mf8(...) __riscv_vsbc_vxm_i8mf8(__VA_ARGS__) -#define vsbc_vvm_i8mf4(...) __riscv_vsbc_vvm_i8mf4(__VA_ARGS__) -#define vsbc_vxm_i8mf4(...) __riscv_vsbc_vxm_i8mf4(__VA_ARGS__) -#define vsbc_vvm_i8mf2(...) __riscv_vsbc_vvm_i8mf2(__VA_ARGS__) -#define vsbc_vxm_i8mf2(...) __riscv_vsbc_vxm_i8mf2(__VA_ARGS__) -#define vsbc_vvm_i8m1(...) __riscv_vsbc_vvm_i8m1(__VA_ARGS__) -#define vsbc_vxm_i8m1(...) __riscv_vsbc_vxm_i8m1(__VA_ARGS__) -#define vsbc_vvm_i8m2(...) __riscv_vsbc_vvm_i8m2(__VA_ARGS__) -#define vsbc_vxm_i8m2(...) __riscv_vsbc_vxm_i8m2(__VA_ARGS__) -#define vsbc_vvm_i8m4(...) __riscv_vsbc_vvm_i8m4(__VA_ARGS__) -#define vsbc_vxm_i8m4(...) __riscv_vsbc_vxm_i8m4(__VA_ARGS__) -#define vsbc_vvm_i8m8(...) __riscv_vsbc_vvm_i8m8(__VA_ARGS__) -#define vsbc_vxm_i8m8(...) __riscv_vsbc_vxm_i8m8(__VA_ARGS__) -#define vsbc_vvm_i16mf4(...) __riscv_vsbc_vvm_i16mf4(__VA_ARGS__) -#define vsbc_vxm_i16mf4(...) __riscv_vsbc_vxm_i16mf4(__VA_ARGS__) -#define vsbc_vvm_i16mf2(...) __riscv_vsbc_vvm_i16mf2(__VA_ARGS__) -#define vsbc_vxm_i16mf2(...) __riscv_vsbc_vxm_i16mf2(__VA_ARGS__) -#define vsbc_vvm_i16m1(...) __riscv_vsbc_vvm_i16m1(__VA_ARGS__) -#define vsbc_vxm_i16m1(...) __riscv_vsbc_vxm_i16m1(__VA_ARGS__) -#define vsbc_vvm_i16m2(...) __riscv_vsbc_vvm_i16m2(__VA_ARGS__) -#define vsbc_vxm_i16m2(...) __riscv_vsbc_vxm_i16m2(__VA_ARGS__) -#define vsbc_vvm_i16m4(...) __riscv_vsbc_vvm_i16m4(__VA_ARGS__) -#define vsbc_vxm_i16m4(...) __riscv_vsbc_vxm_i16m4(__VA_ARGS__) -#define vsbc_vvm_i16m8(...) __riscv_vsbc_vvm_i16m8(__VA_ARGS__) -#define vsbc_vxm_i16m8(...) __riscv_vsbc_vxm_i16m8(__VA_ARGS__) -#define vsbc_vvm_i32mf2(...) __riscv_vsbc_vvm_i32mf2(__VA_ARGS__) -#define vsbc_vxm_i32mf2(...) __riscv_vsbc_vxm_i32mf2(__VA_ARGS__) -#define vsbc_vvm_i32m1(...) __riscv_vsbc_vvm_i32m1(__VA_ARGS__) -#define vsbc_vxm_i32m1(...) __riscv_vsbc_vxm_i32m1(__VA_ARGS__) -#define vsbc_vvm_i32m2(...) __riscv_vsbc_vvm_i32m2(__VA_ARGS__) -#define vsbc_vxm_i32m2(...) __riscv_vsbc_vxm_i32m2(__VA_ARGS__) -#define vsbc_vvm_i32m4(...) __riscv_vsbc_vvm_i32m4(__VA_ARGS__) -#define vsbc_vxm_i32m4(...) __riscv_vsbc_vxm_i32m4(__VA_ARGS__) -#define vsbc_vvm_i32m8(...) __riscv_vsbc_vvm_i32m8(__VA_ARGS__) -#define vsbc_vxm_i32m8(...) __riscv_vsbc_vxm_i32m8(__VA_ARGS__) -#define vsbc_vvm_i64m1(...) __riscv_vsbc_vvm_i64m1(__VA_ARGS__) -#define vsbc_vxm_i64m1(...) __riscv_vsbc_vxm_i64m1(__VA_ARGS__) -#define vsbc_vvm_i64m2(...) __riscv_vsbc_vvm_i64m2(__VA_ARGS__) -#define vsbc_vxm_i64m2(...) __riscv_vsbc_vxm_i64m2(__VA_ARGS__) -#define vsbc_vvm_i64m4(...) __riscv_vsbc_vvm_i64m4(__VA_ARGS__) -#define vsbc_vxm_i64m4(...) __riscv_vsbc_vxm_i64m4(__VA_ARGS__) -#define vsbc_vvm_i64m8(...) __riscv_vsbc_vvm_i64m8(__VA_ARGS__) -#define vsbc_vxm_i64m8(...) __riscv_vsbc_vxm_i64m8(__VA_ARGS__) -#define vadc_vvm_u8mf8(...) __riscv_vadc_vvm_u8mf8(__VA_ARGS__) -#define vadc_vxm_u8mf8(...) __riscv_vadc_vxm_u8mf8(__VA_ARGS__) -#define vadc_vvm_u8mf4(...) __riscv_vadc_vvm_u8mf4(__VA_ARGS__) -#define vadc_vxm_u8mf4(...) __riscv_vadc_vxm_u8mf4(__VA_ARGS__) -#define vadc_vvm_u8mf2(...) __riscv_vadc_vvm_u8mf2(__VA_ARGS__) -#define vadc_vxm_u8mf2(...) __riscv_vadc_vxm_u8mf2(__VA_ARGS__) -#define vadc_vvm_u8m1(...) __riscv_vadc_vvm_u8m1(__VA_ARGS__) -#define vadc_vxm_u8m1(...) __riscv_vadc_vxm_u8m1(__VA_ARGS__) -#define vadc_vvm_u8m2(...) __riscv_vadc_vvm_u8m2(__VA_ARGS__) -#define vadc_vxm_u8m2(...) __riscv_vadc_vxm_u8m2(__VA_ARGS__) -#define vadc_vvm_u8m4(...) __riscv_vadc_vvm_u8m4(__VA_ARGS__) -#define vadc_vxm_u8m4(...) __riscv_vadc_vxm_u8m4(__VA_ARGS__) -#define vadc_vvm_u8m8(...) __riscv_vadc_vvm_u8m8(__VA_ARGS__) -#define vadc_vxm_u8m8(...) __riscv_vadc_vxm_u8m8(__VA_ARGS__) -#define vadc_vvm_u16mf4(...) __riscv_vadc_vvm_u16mf4(__VA_ARGS__) -#define vadc_vxm_u16mf4(...) __riscv_vadc_vxm_u16mf4(__VA_ARGS__) -#define vadc_vvm_u16mf2(...) __riscv_vadc_vvm_u16mf2(__VA_ARGS__) -#define vadc_vxm_u16mf2(...) __riscv_vadc_vxm_u16mf2(__VA_ARGS__) -#define vadc_vvm_u16m1(...) __riscv_vadc_vvm_u16m1(__VA_ARGS__) -#define vadc_vxm_u16m1(...) __riscv_vadc_vxm_u16m1(__VA_ARGS__) -#define vadc_vvm_u16m2(...) __riscv_vadc_vvm_u16m2(__VA_ARGS__) -#define vadc_vxm_u16m2(...) __riscv_vadc_vxm_u16m2(__VA_ARGS__) -#define vadc_vvm_u16m4(...) __riscv_vadc_vvm_u16m4(__VA_ARGS__) -#define vadc_vxm_u16m4(...) __riscv_vadc_vxm_u16m4(__VA_ARGS__) -#define vadc_vvm_u16m8(...) __riscv_vadc_vvm_u16m8(__VA_ARGS__) -#define vadc_vxm_u16m8(...) __riscv_vadc_vxm_u16m8(__VA_ARGS__) -#define vadc_vvm_u32mf2(...) __riscv_vadc_vvm_u32mf2(__VA_ARGS__) -#define vadc_vxm_u32mf2(...) __riscv_vadc_vxm_u32mf2(__VA_ARGS__) -#define vadc_vvm_u32m1(...) __riscv_vadc_vvm_u32m1(__VA_ARGS__) -#define vadc_vxm_u32m1(...) __riscv_vadc_vxm_u32m1(__VA_ARGS__) -#define vadc_vvm_u32m2(...) __riscv_vadc_vvm_u32m2(__VA_ARGS__) -#define vadc_vxm_u32m2(...) __riscv_vadc_vxm_u32m2(__VA_ARGS__) -#define vadc_vvm_u32m4(...) __riscv_vadc_vvm_u32m4(__VA_ARGS__) -#define vadc_vxm_u32m4(...) __riscv_vadc_vxm_u32m4(__VA_ARGS__) -#define vadc_vvm_u32m8(...) __riscv_vadc_vvm_u32m8(__VA_ARGS__) -#define vadc_vxm_u32m8(...) __riscv_vadc_vxm_u32m8(__VA_ARGS__) -#define vadc_vvm_u64m1(...) __riscv_vadc_vvm_u64m1(__VA_ARGS__) -#define vadc_vxm_u64m1(...) __riscv_vadc_vxm_u64m1(__VA_ARGS__) -#define vadc_vvm_u64m2(...) __riscv_vadc_vvm_u64m2(__VA_ARGS__) -#define vadc_vxm_u64m2(...) __riscv_vadc_vxm_u64m2(__VA_ARGS__) -#define vadc_vvm_u64m4(...) __riscv_vadc_vvm_u64m4(__VA_ARGS__) -#define vadc_vxm_u64m4(...) __riscv_vadc_vxm_u64m4(__VA_ARGS__) -#define vadc_vvm_u64m8(...) __riscv_vadc_vvm_u64m8(__VA_ARGS__) -#define vadc_vxm_u64m8(...) __riscv_vadc_vxm_u64m8(__VA_ARGS__) -#define vsbc_vvm_u8mf8(...) __riscv_vsbc_vvm_u8mf8(__VA_ARGS__) -#define vsbc_vxm_u8mf8(...) __riscv_vsbc_vxm_u8mf8(__VA_ARGS__) -#define vsbc_vvm_u8mf4(...) __riscv_vsbc_vvm_u8mf4(__VA_ARGS__) -#define vsbc_vxm_u8mf4(...) __riscv_vsbc_vxm_u8mf4(__VA_ARGS__) -#define vsbc_vvm_u8mf2(...) __riscv_vsbc_vvm_u8mf2(__VA_ARGS__) -#define vsbc_vxm_u8mf2(...) __riscv_vsbc_vxm_u8mf2(__VA_ARGS__) -#define vsbc_vvm_u8m1(...) __riscv_vsbc_vvm_u8m1(__VA_ARGS__) -#define vsbc_vxm_u8m1(...) __riscv_vsbc_vxm_u8m1(__VA_ARGS__) -#define vsbc_vvm_u8m2(...) __riscv_vsbc_vvm_u8m2(__VA_ARGS__) -#define vsbc_vxm_u8m2(...) __riscv_vsbc_vxm_u8m2(__VA_ARGS__) -#define vsbc_vvm_u8m4(...) __riscv_vsbc_vvm_u8m4(__VA_ARGS__) -#define vsbc_vxm_u8m4(...) __riscv_vsbc_vxm_u8m4(__VA_ARGS__) -#define vsbc_vvm_u8m8(...) __riscv_vsbc_vvm_u8m8(__VA_ARGS__) -#define vsbc_vxm_u8m8(...) __riscv_vsbc_vxm_u8m8(__VA_ARGS__) -#define vsbc_vvm_u16mf4(...) __riscv_vsbc_vvm_u16mf4(__VA_ARGS__) -#define vsbc_vxm_u16mf4(...) __riscv_vsbc_vxm_u16mf4(__VA_ARGS__) -#define vsbc_vvm_u16mf2(...) __riscv_vsbc_vvm_u16mf2(__VA_ARGS__) -#define vsbc_vxm_u16mf2(...) __riscv_vsbc_vxm_u16mf2(__VA_ARGS__) -#define vsbc_vvm_u16m1(...) __riscv_vsbc_vvm_u16m1(__VA_ARGS__) -#define vsbc_vxm_u16m1(...) __riscv_vsbc_vxm_u16m1(__VA_ARGS__) -#define vsbc_vvm_u16m2(...) __riscv_vsbc_vvm_u16m2(__VA_ARGS__) -#define vsbc_vxm_u16m2(...) __riscv_vsbc_vxm_u16m2(__VA_ARGS__) -#define vsbc_vvm_u16m4(...) __riscv_vsbc_vvm_u16m4(__VA_ARGS__) -#define vsbc_vxm_u16m4(...) __riscv_vsbc_vxm_u16m4(__VA_ARGS__) -#define vsbc_vvm_u16m8(...) __riscv_vsbc_vvm_u16m8(__VA_ARGS__) -#define vsbc_vxm_u16m8(...) __riscv_vsbc_vxm_u16m8(__VA_ARGS__) -#define vsbc_vvm_u32mf2(...) __riscv_vsbc_vvm_u32mf2(__VA_ARGS__) -#define vsbc_vxm_u32mf2(...) __riscv_vsbc_vxm_u32mf2(__VA_ARGS__) -#define vsbc_vvm_u32m1(...) __riscv_vsbc_vvm_u32m1(__VA_ARGS__) -#define vsbc_vxm_u32m1(...) __riscv_vsbc_vxm_u32m1(__VA_ARGS__) -#define vsbc_vvm_u32m2(...) __riscv_vsbc_vvm_u32m2(__VA_ARGS__) -#define vsbc_vxm_u32m2(...) __riscv_vsbc_vxm_u32m2(__VA_ARGS__) -#define vsbc_vvm_u32m4(...) __riscv_vsbc_vvm_u32m4(__VA_ARGS__) -#define vsbc_vxm_u32m4(...) __riscv_vsbc_vxm_u32m4(__VA_ARGS__) -#define vsbc_vvm_u32m8(...) __riscv_vsbc_vvm_u32m8(__VA_ARGS__) -#define vsbc_vxm_u32m8(...) __riscv_vsbc_vxm_u32m8(__VA_ARGS__) -#define vsbc_vvm_u64m1(...) __riscv_vsbc_vvm_u64m1(__VA_ARGS__) -#define vsbc_vxm_u64m1(...) __riscv_vsbc_vxm_u64m1(__VA_ARGS__) -#define vsbc_vvm_u64m2(...) __riscv_vsbc_vvm_u64m2(__VA_ARGS__) -#define vsbc_vxm_u64m2(...) __riscv_vsbc_vxm_u64m2(__VA_ARGS__) -#define vsbc_vvm_u64m4(...) __riscv_vsbc_vvm_u64m4(__VA_ARGS__) -#define vsbc_vxm_u64m4(...) __riscv_vsbc_vxm_u64m4(__VA_ARGS__) -#define vsbc_vvm_u64m8(...) __riscv_vsbc_vvm_u64m8(__VA_ARGS__) -#define vsbc_vxm_u64m8(...) __riscv_vsbc_vxm_u64m8(__VA_ARGS__) -#define vmadc_vvm_i8mf8_b64(...) __riscv_vmadc_vvm_i8mf8_b64(__VA_ARGS__) -#define vmadc_vxm_i8mf8_b64(...) __riscv_vmadc_vxm_i8mf8_b64(__VA_ARGS__) -#define vmadc_vv_i8mf8_b64(...) __riscv_vmadc_vv_i8mf8_b64(__VA_ARGS__) -#define vmadc_vx_i8mf8_b64(...) __riscv_vmadc_vx_i8mf8_b64(__VA_ARGS__) -#define vmadc_vvm_i8mf4_b32(...) __riscv_vmadc_vvm_i8mf4_b32(__VA_ARGS__) -#define vmadc_vxm_i8mf4_b32(...) __riscv_vmadc_vxm_i8mf4_b32(__VA_ARGS__) -#define vmadc_vv_i8mf4_b32(...) __riscv_vmadc_vv_i8mf4_b32(__VA_ARGS__) -#define vmadc_vx_i8mf4_b32(...) __riscv_vmadc_vx_i8mf4_b32(__VA_ARGS__) -#define vmadc_vvm_i8mf2_b16(...) __riscv_vmadc_vvm_i8mf2_b16(__VA_ARGS__) -#define vmadc_vxm_i8mf2_b16(...) __riscv_vmadc_vxm_i8mf2_b16(__VA_ARGS__) -#define vmadc_vv_i8mf2_b16(...) __riscv_vmadc_vv_i8mf2_b16(__VA_ARGS__) -#define vmadc_vx_i8mf2_b16(...) __riscv_vmadc_vx_i8mf2_b16(__VA_ARGS__) -#define vmadc_vvm_i8m1_b8(...) __riscv_vmadc_vvm_i8m1_b8(__VA_ARGS__) -#define vmadc_vxm_i8m1_b8(...) __riscv_vmadc_vxm_i8m1_b8(__VA_ARGS__) -#define vmadc_vv_i8m1_b8(...) __riscv_vmadc_vv_i8m1_b8(__VA_ARGS__) -#define vmadc_vx_i8m1_b8(...) __riscv_vmadc_vx_i8m1_b8(__VA_ARGS__) -#define vmadc_vvm_i8m2_b4(...) __riscv_vmadc_vvm_i8m2_b4(__VA_ARGS__) -#define vmadc_vxm_i8m2_b4(...) __riscv_vmadc_vxm_i8m2_b4(__VA_ARGS__) -#define vmadc_vv_i8m2_b4(...) __riscv_vmadc_vv_i8m2_b4(__VA_ARGS__) -#define vmadc_vx_i8m2_b4(...) __riscv_vmadc_vx_i8m2_b4(__VA_ARGS__) -#define vmadc_vvm_i8m4_b2(...) __riscv_vmadc_vvm_i8m4_b2(__VA_ARGS__) -#define vmadc_vxm_i8m4_b2(...) __riscv_vmadc_vxm_i8m4_b2(__VA_ARGS__) -#define vmadc_vv_i8m4_b2(...) __riscv_vmadc_vv_i8m4_b2(__VA_ARGS__) -#define vmadc_vx_i8m4_b2(...) __riscv_vmadc_vx_i8m4_b2(__VA_ARGS__) -#define vmadc_vvm_i8m8_b1(...) __riscv_vmadc_vvm_i8m8_b1(__VA_ARGS__) -#define vmadc_vxm_i8m8_b1(...) __riscv_vmadc_vxm_i8m8_b1(__VA_ARGS__) -#define vmadc_vv_i8m8_b1(...) __riscv_vmadc_vv_i8m8_b1(__VA_ARGS__) -#define vmadc_vx_i8m8_b1(...) __riscv_vmadc_vx_i8m8_b1(__VA_ARGS__) -#define vmadc_vvm_i16mf4_b64(...) __riscv_vmadc_vvm_i16mf4_b64(__VA_ARGS__) -#define vmadc_vxm_i16mf4_b64(...) __riscv_vmadc_vxm_i16mf4_b64(__VA_ARGS__) -#define vmadc_vv_i16mf4_b64(...) __riscv_vmadc_vv_i16mf4_b64(__VA_ARGS__) -#define vmadc_vx_i16mf4_b64(...) __riscv_vmadc_vx_i16mf4_b64(__VA_ARGS__) -#define vmadc_vvm_i16mf2_b32(...) __riscv_vmadc_vvm_i16mf2_b32(__VA_ARGS__) -#define vmadc_vxm_i16mf2_b32(...) __riscv_vmadc_vxm_i16mf2_b32(__VA_ARGS__) -#define vmadc_vv_i16mf2_b32(...) __riscv_vmadc_vv_i16mf2_b32(__VA_ARGS__) -#define vmadc_vx_i16mf2_b32(...) __riscv_vmadc_vx_i16mf2_b32(__VA_ARGS__) -#define vmadc_vvm_i16m1_b16(...) __riscv_vmadc_vvm_i16m1_b16(__VA_ARGS__) -#define vmadc_vxm_i16m1_b16(...) __riscv_vmadc_vxm_i16m1_b16(__VA_ARGS__) -#define vmadc_vv_i16m1_b16(...) __riscv_vmadc_vv_i16m1_b16(__VA_ARGS__) -#define vmadc_vx_i16m1_b16(...) __riscv_vmadc_vx_i16m1_b16(__VA_ARGS__) -#define vmadc_vvm_i16m2_b8(...) __riscv_vmadc_vvm_i16m2_b8(__VA_ARGS__) -#define vmadc_vxm_i16m2_b8(...) __riscv_vmadc_vxm_i16m2_b8(__VA_ARGS__) -#define vmadc_vv_i16m2_b8(...) __riscv_vmadc_vv_i16m2_b8(__VA_ARGS__) -#define vmadc_vx_i16m2_b8(...) __riscv_vmadc_vx_i16m2_b8(__VA_ARGS__) -#define vmadc_vvm_i16m4_b4(...) __riscv_vmadc_vvm_i16m4_b4(__VA_ARGS__) -#define vmadc_vxm_i16m4_b4(...) __riscv_vmadc_vxm_i16m4_b4(__VA_ARGS__) -#define vmadc_vv_i16m4_b4(...) __riscv_vmadc_vv_i16m4_b4(__VA_ARGS__) -#define vmadc_vx_i16m4_b4(...) __riscv_vmadc_vx_i16m4_b4(__VA_ARGS__) -#define vmadc_vvm_i16m8_b2(...) __riscv_vmadc_vvm_i16m8_b2(__VA_ARGS__) -#define vmadc_vxm_i16m8_b2(...) __riscv_vmadc_vxm_i16m8_b2(__VA_ARGS__) -#define vmadc_vv_i16m8_b2(...) __riscv_vmadc_vv_i16m8_b2(__VA_ARGS__) -#define vmadc_vx_i16m8_b2(...) __riscv_vmadc_vx_i16m8_b2(__VA_ARGS__) -#define vmadc_vvm_i32mf2_b64(...) __riscv_vmadc_vvm_i32mf2_b64(__VA_ARGS__) -#define vmadc_vxm_i32mf2_b64(...) __riscv_vmadc_vxm_i32mf2_b64(__VA_ARGS__) -#define vmadc_vv_i32mf2_b64(...) __riscv_vmadc_vv_i32mf2_b64(__VA_ARGS__) -#define vmadc_vx_i32mf2_b64(...) __riscv_vmadc_vx_i32mf2_b64(__VA_ARGS__) -#define vmadc_vvm_i32m1_b32(...) __riscv_vmadc_vvm_i32m1_b32(__VA_ARGS__) -#define vmadc_vxm_i32m1_b32(...) __riscv_vmadc_vxm_i32m1_b32(__VA_ARGS__) -#define vmadc_vv_i32m1_b32(...) __riscv_vmadc_vv_i32m1_b32(__VA_ARGS__) -#define vmadc_vx_i32m1_b32(...) __riscv_vmadc_vx_i32m1_b32(__VA_ARGS__) -#define vmadc_vvm_i32m2_b16(...) __riscv_vmadc_vvm_i32m2_b16(__VA_ARGS__) -#define vmadc_vxm_i32m2_b16(...) __riscv_vmadc_vxm_i32m2_b16(__VA_ARGS__) -#define vmadc_vv_i32m2_b16(...) __riscv_vmadc_vv_i32m2_b16(__VA_ARGS__) -#define vmadc_vx_i32m2_b16(...) __riscv_vmadc_vx_i32m2_b16(__VA_ARGS__) -#define vmadc_vvm_i32m4_b8(...) __riscv_vmadc_vvm_i32m4_b8(__VA_ARGS__) -#define vmadc_vxm_i32m4_b8(...) __riscv_vmadc_vxm_i32m4_b8(__VA_ARGS__) -#define vmadc_vv_i32m4_b8(...) __riscv_vmadc_vv_i32m4_b8(__VA_ARGS__) -#define vmadc_vx_i32m4_b8(...) __riscv_vmadc_vx_i32m4_b8(__VA_ARGS__) -#define vmadc_vvm_i32m8_b4(...) __riscv_vmadc_vvm_i32m8_b4(__VA_ARGS__) -#define vmadc_vxm_i32m8_b4(...) __riscv_vmadc_vxm_i32m8_b4(__VA_ARGS__) -#define vmadc_vv_i32m8_b4(...) __riscv_vmadc_vv_i32m8_b4(__VA_ARGS__) -#define vmadc_vx_i32m8_b4(...) __riscv_vmadc_vx_i32m8_b4(__VA_ARGS__) -#define vmadc_vvm_i64m1_b64(...) __riscv_vmadc_vvm_i64m1_b64(__VA_ARGS__) -#define vmadc_vxm_i64m1_b64(...) __riscv_vmadc_vxm_i64m1_b64(__VA_ARGS__) -#define vmadc_vv_i64m1_b64(...) __riscv_vmadc_vv_i64m1_b64(__VA_ARGS__) -#define vmadc_vx_i64m1_b64(...) __riscv_vmadc_vx_i64m1_b64(__VA_ARGS__) -#define vmadc_vvm_i64m2_b32(...) __riscv_vmadc_vvm_i64m2_b32(__VA_ARGS__) -#define vmadc_vxm_i64m2_b32(...) __riscv_vmadc_vxm_i64m2_b32(__VA_ARGS__) -#define vmadc_vv_i64m2_b32(...) __riscv_vmadc_vv_i64m2_b32(__VA_ARGS__) -#define vmadc_vx_i64m2_b32(...) __riscv_vmadc_vx_i64m2_b32(__VA_ARGS__) -#define vmadc_vvm_i64m4_b16(...) __riscv_vmadc_vvm_i64m4_b16(__VA_ARGS__) -#define vmadc_vxm_i64m4_b16(...) __riscv_vmadc_vxm_i64m4_b16(__VA_ARGS__) -#define vmadc_vv_i64m4_b16(...) __riscv_vmadc_vv_i64m4_b16(__VA_ARGS__) -#define vmadc_vx_i64m4_b16(...) __riscv_vmadc_vx_i64m4_b16(__VA_ARGS__) -#define vmadc_vvm_i64m8_b8(...) __riscv_vmadc_vvm_i64m8_b8(__VA_ARGS__) -#define vmadc_vxm_i64m8_b8(...) __riscv_vmadc_vxm_i64m8_b8(__VA_ARGS__) -#define vmadc_vv_i64m8_b8(...) __riscv_vmadc_vv_i64m8_b8(__VA_ARGS__) -#define vmadc_vx_i64m8_b8(...) __riscv_vmadc_vx_i64m8_b8(__VA_ARGS__) -#define vmsbc_vvm_i8mf8_b64(...) __riscv_vmsbc_vvm_i8mf8_b64(__VA_ARGS__) -#define vmsbc_vxm_i8mf8_b64(...) __riscv_vmsbc_vxm_i8mf8_b64(__VA_ARGS__) -#define vmsbc_vv_i8mf8_b64(...) __riscv_vmsbc_vv_i8mf8_b64(__VA_ARGS__) -#define vmsbc_vx_i8mf8_b64(...) __riscv_vmsbc_vx_i8mf8_b64(__VA_ARGS__) -#define vmsbc_vvm_i8mf4_b32(...) __riscv_vmsbc_vvm_i8mf4_b32(__VA_ARGS__) -#define vmsbc_vxm_i8mf4_b32(...) __riscv_vmsbc_vxm_i8mf4_b32(__VA_ARGS__) -#define vmsbc_vv_i8mf4_b32(...) __riscv_vmsbc_vv_i8mf4_b32(__VA_ARGS__) -#define vmsbc_vx_i8mf4_b32(...) __riscv_vmsbc_vx_i8mf4_b32(__VA_ARGS__) -#define vmsbc_vvm_i8mf2_b16(...) __riscv_vmsbc_vvm_i8mf2_b16(__VA_ARGS__) -#define vmsbc_vxm_i8mf2_b16(...) __riscv_vmsbc_vxm_i8mf2_b16(__VA_ARGS__) -#define vmsbc_vv_i8mf2_b16(...) __riscv_vmsbc_vv_i8mf2_b16(__VA_ARGS__) -#define vmsbc_vx_i8mf2_b16(...) __riscv_vmsbc_vx_i8mf2_b16(__VA_ARGS__) -#define vmsbc_vvm_i8m1_b8(...) __riscv_vmsbc_vvm_i8m1_b8(__VA_ARGS__) -#define vmsbc_vxm_i8m1_b8(...) __riscv_vmsbc_vxm_i8m1_b8(__VA_ARGS__) -#define vmsbc_vv_i8m1_b8(...) __riscv_vmsbc_vv_i8m1_b8(__VA_ARGS__) -#define vmsbc_vx_i8m1_b8(...) __riscv_vmsbc_vx_i8m1_b8(__VA_ARGS__) -#define vmsbc_vvm_i8m2_b4(...) __riscv_vmsbc_vvm_i8m2_b4(__VA_ARGS__) -#define vmsbc_vxm_i8m2_b4(...) __riscv_vmsbc_vxm_i8m2_b4(__VA_ARGS__) -#define vmsbc_vv_i8m2_b4(...) __riscv_vmsbc_vv_i8m2_b4(__VA_ARGS__) -#define vmsbc_vx_i8m2_b4(...) __riscv_vmsbc_vx_i8m2_b4(__VA_ARGS__) -#define vmsbc_vvm_i8m4_b2(...) __riscv_vmsbc_vvm_i8m4_b2(__VA_ARGS__) -#define vmsbc_vxm_i8m4_b2(...) __riscv_vmsbc_vxm_i8m4_b2(__VA_ARGS__) -#define vmsbc_vv_i8m4_b2(...) __riscv_vmsbc_vv_i8m4_b2(__VA_ARGS__) -#define vmsbc_vx_i8m4_b2(...) __riscv_vmsbc_vx_i8m4_b2(__VA_ARGS__) -#define vmsbc_vvm_i8m8_b1(...) __riscv_vmsbc_vvm_i8m8_b1(__VA_ARGS__) -#define vmsbc_vxm_i8m8_b1(...) __riscv_vmsbc_vxm_i8m8_b1(__VA_ARGS__) -#define vmsbc_vv_i8m8_b1(...) __riscv_vmsbc_vv_i8m8_b1(__VA_ARGS__) -#define vmsbc_vx_i8m8_b1(...) __riscv_vmsbc_vx_i8m8_b1(__VA_ARGS__) -#define vmsbc_vvm_i16mf4_b64(...) __riscv_vmsbc_vvm_i16mf4_b64(__VA_ARGS__) -#define vmsbc_vxm_i16mf4_b64(...) __riscv_vmsbc_vxm_i16mf4_b64(__VA_ARGS__) -#define vmsbc_vv_i16mf4_b64(...) __riscv_vmsbc_vv_i16mf4_b64(__VA_ARGS__) -#define vmsbc_vx_i16mf4_b64(...) __riscv_vmsbc_vx_i16mf4_b64(__VA_ARGS__) -#define vmsbc_vvm_i16mf2_b32(...) __riscv_vmsbc_vvm_i16mf2_b32(__VA_ARGS__) -#define vmsbc_vxm_i16mf2_b32(...) __riscv_vmsbc_vxm_i16mf2_b32(__VA_ARGS__) -#define vmsbc_vv_i16mf2_b32(...) __riscv_vmsbc_vv_i16mf2_b32(__VA_ARGS__) -#define vmsbc_vx_i16mf2_b32(...) __riscv_vmsbc_vx_i16mf2_b32(__VA_ARGS__) -#define vmsbc_vvm_i16m1_b16(...) __riscv_vmsbc_vvm_i16m1_b16(__VA_ARGS__) -#define vmsbc_vxm_i16m1_b16(...) __riscv_vmsbc_vxm_i16m1_b16(__VA_ARGS__) -#define vmsbc_vv_i16m1_b16(...) __riscv_vmsbc_vv_i16m1_b16(__VA_ARGS__) -#define vmsbc_vx_i16m1_b16(...) __riscv_vmsbc_vx_i16m1_b16(__VA_ARGS__) -#define vmsbc_vvm_i16m2_b8(...) __riscv_vmsbc_vvm_i16m2_b8(__VA_ARGS__) -#define vmsbc_vxm_i16m2_b8(...) __riscv_vmsbc_vxm_i16m2_b8(__VA_ARGS__) -#define vmsbc_vv_i16m2_b8(...) __riscv_vmsbc_vv_i16m2_b8(__VA_ARGS__) -#define vmsbc_vx_i16m2_b8(...) __riscv_vmsbc_vx_i16m2_b8(__VA_ARGS__) -#define vmsbc_vvm_i16m4_b4(...) __riscv_vmsbc_vvm_i16m4_b4(__VA_ARGS__) -#define vmsbc_vxm_i16m4_b4(...) __riscv_vmsbc_vxm_i16m4_b4(__VA_ARGS__) -#define vmsbc_vv_i16m4_b4(...) __riscv_vmsbc_vv_i16m4_b4(__VA_ARGS__) -#define vmsbc_vx_i16m4_b4(...) __riscv_vmsbc_vx_i16m4_b4(__VA_ARGS__) -#define vmsbc_vvm_i16m8_b2(...) __riscv_vmsbc_vvm_i16m8_b2(__VA_ARGS__) -#define vmsbc_vxm_i16m8_b2(...) __riscv_vmsbc_vxm_i16m8_b2(__VA_ARGS__) -#define vmsbc_vv_i16m8_b2(...) __riscv_vmsbc_vv_i16m8_b2(__VA_ARGS__) -#define vmsbc_vx_i16m8_b2(...) __riscv_vmsbc_vx_i16m8_b2(__VA_ARGS__) -#define vmsbc_vvm_i32mf2_b64(...) __riscv_vmsbc_vvm_i32mf2_b64(__VA_ARGS__) -#define vmsbc_vxm_i32mf2_b64(...) __riscv_vmsbc_vxm_i32mf2_b64(__VA_ARGS__) -#define vmsbc_vv_i32mf2_b64(...) __riscv_vmsbc_vv_i32mf2_b64(__VA_ARGS__) -#define vmsbc_vx_i32mf2_b64(...) __riscv_vmsbc_vx_i32mf2_b64(__VA_ARGS__) -#define vmsbc_vvm_i32m1_b32(...) __riscv_vmsbc_vvm_i32m1_b32(__VA_ARGS__) -#define vmsbc_vxm_i32m1_b32(...) __riscv_vmsbc_vxm_i32m1_b32(__VA_ARGS__) -#define vmsbc_vv_i32m1_b32(...) __riscv_vmsbc_vv_i32m1_b32(__VA_ARGS__) -#define vmsbc_vx_i32m1_b32(...) __riscv_vmsbc_vx_i32m1_b32(__VA_ARGS__) -#define vmsbc_vvm_i32m2_b16(...) __riscv_vmsbc_vvm_i32m2_b16(__VA_ARGS__) -#define vmsbc_vxm_i32m2_b16(...) __riscv_vmsbc_vxm_i32m2_b16(__VA_ARGS__) -#define vmsbc_vv_i32m2_b16(...) __riscv_vmsbc_vv_i32m2_b16(__VA_ARGS__) -#define vmsbc_vx_i32m2_b16(...) __riscv_vmsbc_vx_i32m2_b16(__VA_ARGS__) -#define vmsbc_vvm_i32m4_b8(...) __riscv_vmsbc_vvm_i32m4_b8(__VA_ARGS__) -#define vmsbc_vxm_i32m4_b8(...) __riscv_vmsbc_vxm_i32m4_b8(__VA_ARGS__) -#define vmsbc_vv_i32m4_b8(...) __riscv_vmsbc_vv_i32m4_b8(__VA_ARGS__) -#define vmsbc_vx_i32m4_b8(...) __riscv_vmsbc_vx_i32m4_b8(__VA_ARGS__) -#define vmsbc_vvm_i32m8_b4(...) __riscv_vmsbc_vvm_i32m8_b4(__VA_ARGS__) -#define vmsbc_vxm_i32m8_b4(...) __riscv_vmsbc_vxm_i32m8_b4(__VA_ARGS__) -#define vmsbc_vv_i32m8_b4(...) __riscv_vmsbc_vv_i32m8_b4(__VA_ARGS__) -#define vmsbc_vx_i32m8_b4(...) __riscv_vmsbc_vx_i32m8_b4(__VA_ARGS__) -#define vmsbc_vvm_i64m1_b64(...) __riscv_vmsbc_vvm_i64m1_b64(__VA_ARGS__) -#define vmsbc_vxm_i64m1_b64(...) __riscv_vmsbc_vxm_i64m1_b64(__VA_ARGS__) -#define vmsbc_vv_i64m1_b64(...) __riscv_vmsbc_vv_i64m1_b64(__VA_ARGS__) -#define vmsbc_vx_i64m1_b64(...) __riscv_vmsbc_vx_i64m1_b64(__VA_ARGS__) -#define vmsbc_vvm_i64m2_b32(...) __riscv_vmsbc_vvm_i64m2_b32(__VA_ARGS__) -#define vmsbc_vxm_i64m2_b32(...) __riscv_vmsbc_vxm_i64m2_b32(__VA_ARGS__) -#define vmsbc_vv_i64m2_b32(...) __riscv_vmsbc_vv_i64m2_b32(__VA_ARGS__) -#define vmsbc_vx_i64m2_b32(...) __riscv_vmsbc_vx_i64m2_b32(__VA_ARGS__) -#define vmsbc_vvm_i64m4_b16(...) __riscv_vmsbc_vvm_i64m4_b16(__VA_ARGS__) -#define vmsbc_vxm_i64m4_b16(...) __riscv_vmsbc_vxm_i64m4_b16(__VA_ARGS__) -#define vmsbc_vv_i64m4_b16(...) __riscv_vmsbc_vv_i64m4_b16(__VA_ARGS__) -#define vmsbc_vx_i64m4_b16(...) __riscv_vmsbc_vx_i64m4_b16(__VA_ARGS__) -#define vmsbc_vvm_i64m8_b8(...) __riscv_vmsbc_vvm_i64m8_b8(__VA_ARGS__) -#define vmsbc_vxm_i64m8_b8(...) __riscv_vmsbc_vxm_i64m8_b8(__VA_ARGS__) -#define vmsbc_vv_i64m8_b8(...) __riscv_vmsbc_vv_i64m8_b8(__VA_ARGS__) -#define vmsbc_vx_i64m8_b8(...) __riscv_vmsbc_vx_i64m8_b8(__VA_ARGS__) -#define vmadc_vvm_u8mf8_b64(...) __riscv_vmadc_vvm_u8mf8_b64(__VA_ARGS__) -#define vmadc_vxm_u8mf8_b64(...) __riscv_vmadc_vxm_u8mf8_b64(__VA_ARGS__) -#define vmadc_vv_u8mf8_b64(...) __riscv_vmadc_vv_u8mf8_b64(__VA_ARGS__) -#define vmadc_vx_u8mf8_b64(...) __riscv_vmadc_vx_u8mf8_b64(__VA_ARGS__) -#define vmadc_vvm_u8mf4_b32(...) __riscv_vmadc_vvm_u8mf4_b32(__VA_ARGS__) -#define vmadc_vxm_u8mf4_b32(...) __riscv_vmadc_vxm_u8mf4_b32(__VA_ARGS__) -#define vmadc_vv_u8mf4_b32(...) __riscv_vmadc_vv_u8mf4_b32(__VA_ARGS__) -#define vmadc_vx_u8mf4_b32(...) __riscv_vmadc_vx_u8mf4_b32(__VA_ARGS__) -#define vmadc_vvm_u8mf2_b16(...) __riscv_vmadc_vvm_u8mf2_b16(__VA_ARGS__) -#define vmadc_vxm_u8mf2_b16(...) __riscv_vmadc_vxm_u8mf2_b16(__VA_ARGS__) -#define vmadc_vv_u8mf2_b16(...) __riscv_vmadc_vv_u8mf2_b16(__VA_ARGS__) -#define vmadc_vx_u8mf2_b16(...) __riscv_vmadc_vx_u8mf2_b16(__VA_ARGS__) -#define vmadc_vvm_u8m1_b8(...) __riscv_vmadc_vvm_u8m1_b8(__VA_ARGS__) -#define vmadc_vxm_u8m1_b8(...) __riscv_vmadc_vxm_u8m1_b8(__VA_ARGS__) -#define vmadc_vv_u8m1_b8(...) __riscv_vmadc_vv_u8m1_b8(__VA_ARGS__) -#define vmadc_vx_u8m1_b8(...) __riscv_vmadc_vx_u8m1_b8(__VA_ARGS__) -#define vmadc_vvm_u8m2_b4(...) __riscv_vmadc_vvm_u8m2_b4(__VA_ARGS__) -#define vmadc_vxm_u8m2_b4(...) __riscv_vmadc_vxm_u8m2_b4(__VA_ARGS__) -#define vmadc_vv_u8m2_b4(...) __riscv_vmadc_vv_u8m2_b4(__VA_ARGS__) -#define vmadc_vx_u8m2_b4(...) __riscv_vmadc_vx_u8m2_b4(__VA_ARGS__) -#define vmadc_vvm_u8m4_b2(...) __riscv_vmadc_vvm_u8m4_b2(__VA_ARGS__) -#define vmadc_vxm_u8m4_b2(...) __riscv_vmadc_vxm_u8m4_b2(__VA_ARGS__) -#define vmadc_vv_u8m4_b2(...) __riscv_vmadc_vv_u8m4_b2(__VA_ARGS__) -#define vmadc_vx_u8m4_b2(...) __riscv_vmadc_vx_u8m4_b2(__VA_ARGS__) -#define vmadc_vvm_u8m8_b1(...) __riscv_vmadc_vvm_u8m8_b1(__VA_ARGS__) -#define vmadc_vxm_u8m8_b1(...) __riscv_vmadc_vxm_u8m8_b1(__VA_ARGS__) -#define vmadc_vv_u8m8_b1(...) __riscv_vmadc_vv_u8m8_b1(__VA_ARGS__) -#define vmadc_vx_u8m8_b1(...) __riscv_vmadc_vx_u8m8_b1(__VA_ARGS__) -#define vmadc_vvm_u16mf4_b64(...) __riscv_vmadc_vvm_u16mf4_b64(__VA_ARGS__) -#define vmadc_vxm_u16mf4_b64(...) __riscv_vmadc_vxm_u16mf4_b64(__VA_ARGS__) -#define vmadc_vv_u16mf4_b64(...) __riscv_vmadc_vv_u16mf4_b64(__VA_ARGS__) -#define vmadc_vx_u16mf4_b64(...) __riscv_vmadc_vx_u16mf4_b64(__VA_ARGS__) -#define vmadc_vvm_u16mf2_b32(...) __riscv_vmadc_vvm_u16mf2_b32(__VA_ARGS__) -#define vmadc_vxm_u16mf2_b32(...) __riscv_vmadc_vxm_u16mf2_b32(__VA_ARGS__) -#define vmadc_vv_u16mf2_b32(...) __riscv_vmadc_vv_u16mf2_b32(__VA_ARGS__) -#define vmadc_vx_u16mf2_b32(...) __riscv_vmadc_vx_u16mf2_b32(__VA_ARGS__) -#define vmadc_vvm_u16m1_b16(...) __riscv_vmadc_vvm_u16m1_b16(__VA_ARGS__) -#define vmadc_vxm_u16m1_b16(...) __riscv_vmadc_vxm_u16m1_b16(__VA_ARGS__) -#define vmadc_vv_u16m1_b16(...) __riscv_vmadc_vv_u16m1_b16(__VA_ARGS__) -#define vmadc_vx_u16m1_b16(...) __riscv_vmadc_vx_u16m1_b16(__VA_ARGS__) -#define vmadc_vvm_u16m2_b8(...) __riscv_vmadc_vvm_u16m2_b8(__VA_ARGS__) -#define vmadc_vxm_u16m2_b8(...) __riscv_vmadc_vxm_u16m2_b8(__VA_ARGS__) -#define vmadc_vv_u16m2_b8(...) __riscv_vmadc_vv_u16m2_b8(__VA_ARGS__) -#define vmadc_vx_u16m2_b8(...) __riscv_vmadc_vx_u16m2_b8(__VA_ARGS__) -#define vmadc_vvm_u16m4_b4(...) __riscv_vmadc_vvm_u16m4_b4(__VA_ARGS__) -#define vmadc_vxm_u16m4_b4(...) __riscv_vmadc_vxm_u16m4_b4(__VA_ARGS__) -#define vmadc_vv_u16m4_b4(...) __riscv_vmadc_vv_u16m4_b4(__VA_ARGS__) -#define vmadc_vx_u16m4_b4(...) __riscv_vmadc_vx_u16m4_b4(__VA_ARGS__) -#define vmadc_vvm_u16m8_b2(...) __riscv_vmadc_vvm_u16m8_b2(__VA_ARGS__) -#define vmadc_vxm_u16m8_b2(...) __riscv_vmadc_vxm_u16m8_b2(__VA_ARGS__) -#define vmadc_vv_u16m8_b2(...) __riscv_vmadc_vv_u16m8_b2(__VA_ARGS__) -#define vmadc_vx_u16m8_b2(...) __riscv_vmadc_vx_u16m8_b2(__VA_ARGS__) -#define vmadc_vvm_u32mf2_b64(...) __riscv_vmadc_vvm_u32mf2_b64(__VA_ARGS__) -#define vmadc_vxm_u32mf2_b64(...) __riscv_vmadc_vxm_u32mf2_b64(__VA_ARGS__) -#define vmadc_vv_u32mf2_b64(...) __riscv_vmadc_vv_u32mf2_b64(__VA_ARGS__) -#define vmadc_vx_u32mf2_b64(...) __riscv_vmadc_vx_u32mf2_b64(__VA_ARGS__) -#define vmadc_vvm_u32m1_b32(...) __riscv_vmadc_vvm_u32m1_b32(__VA_ARGS__) -#define vmadc_vxm_u32m1_b32(...) __riscv_vmadc_vxm_u32m1_b32(__VA_ARGS__) -#define vmadc_vv_u32m1_b32(...) __riscv_vmadc_vv_u32m1_b32(__VA_ARGS__) -#define vmadc_vx_u32m1_b32(...) __riscv_vmadc_vx_u32m1_b32(__VA_ARGS__) -#define vmadc_vvm_u32m2_b16(...) __riscv_vmadc_vvm_u32m2_b16(__VA_ARGS__) -#define vmadc_vxm_u32m2_b16(...) __riscv_vmadc_vxm_u32m2_b16(__VA_ARGS__) -#define vmadc_vv_u32m2_b16(...) __riscv_vmadc_vv_u32m2_b16(__VA_ARGS__) -#define vmadc_vx_u32m2_b16(...) __riscv_vmadc_vx_u32m2_b16(__VA_ARGS__) -#define vmadc_vvm_u32m4_b8(...) __riscv_vmadc_vvm_u32m4_b8(__VA_ARGS__) -#define vmadc_vxm_u32m4_b8(...) __riscv_vmadc_vxm_u32m4_b8(__VA_ARGS__) -#define vmadc_vv_u32m4_b8(...) __riscv_vmadc_vv_u32m4_b8(__VA_ARGS__) -#define vmadc_vx_u32m4_b8(...) __riscv_vmadc_vx_u32m4_b8(__VA_ARGS__) -#define vmadc_vvm_u32m8_b4(...) __riscv_vmadc_vvm_u32m8_b4(__VA_ARGS__) -#define vmadc_vxm_u32m8_b4(...) __riscv_vmadc_vxm_u32m8_b4(__VA_ARGS__) -#define vmadc_vv_u32m8_b4(...) __riscv_vmadc_vv_u32m8_b4(__VA_ARGS__) -#define vmadc_vx_u32m8_b4(...) __riscv_vmadc_vx_u32m8_b4(__VA_ARGS__) -#define vmadc_vvm_u64m1_b64(...) __riscv_vmadc_vvm_u64m1_b64(__VA_ARGS__) -#define vmadc_vxm_u64m1_b64(...) __riscv_vmadc_vxm_u64m1_b64(__VA_ARGS__) -#define vmadc_vv_u64m1_b64(...) __riscv_vmadc_vv_u64m1_b64(__VA_ARGS__) -#define vmadc_vx_u64m1_b64(...) __riscv_vmadc_vx_u64m1_b64(__VA_ARGS__) -#define vmadc_vvm_u64m2_b32(...) __riscv_vmadc_vvm_u64m2_b32(__VA_ARGS__) -#define vmadc_vxm_u64m2_b32(...) __riscv_vmadc_vxm_u64m2_b32(__VA_ARGS__) -#define vmadc_vv_u64m2_b32(...) __riscv_vmadc_vv_u64m2_b32(__VA_ARGS__) -#define vmadc_vx_u64m2_b32(...) __riscv_vmadc_vx_u64m2_b32(__VA_ARGS__) -#define vmadc_vvm_u64m4_b16(...) __riscv_vmadc_vvm_u64m4_b16(__VA_ARGS__) -#define vmadc_vxm_u64m4_b16(...) __riscv_vmadc_vxm_u64m4_b16(__VA_ARGS__) -#define vmadc_vv_u64m4_b16(...) __riscv_vmadc_vv_u64m4_b16(__VA_ARGS__) -#define vmadc_vx_u64m4_b16(...) __riscv_vmadc_vx_u64m4_b16(__VA_ARGS__) -#define vmadc_vvm_u64m8_b8(...) __riscv_vmadc_vvm_u64m8_b8(__VA_ARGS__) -#define vmadc_vxm_u64m8_b8(...) __riscv_vmadc_vxm_u64m8_b8(__VA_ARGS__) -#define vmadc_vv_u64m8_b8(...) __riscv_vmadc_vv_u64m8_b8(__VA_ARGS__) -#define vmadc_vx_u64m8_b8(...) __riscv_vmadc_vx_u64m8_b8(__VA_ARGS__) -#define vmsbc_vvm_u8mf8_b64(...) __riscv_vmsbc_vvm_u8mf8_b64(__VA_ARGS__) -#define vmsbc_vxm_u8mf8_b64(...) __riscv_vmsbc_vxm_u8mf8_b64(__VA_ARGS__) -#define vmsbc_vv_u8mf8_b64(...) __riscv_vmsbc_vv_u8mf8_b64(__VA_ARGS__) -#define vmsbc_vx_u8mf8_b64(...) __riscv_vmsbc_vx_u8mf8_b64(__VA_ARGS__) -#define vmsbc_vvm_u8mf4_b32(...) __riscv_vmsbc_vvm_u8mf4_b32(__VA_ARGS__) -#define vmsbc_vxm_u8mf4_b32(...) __riscv_vmsbc_vxm_u8mf4_b32(__VA_ARGS__) -#define vmsbc_vv_u8mf4_b32(...) __riscv_vmsbc_vv_u8mf4_b32(__VA_ARGS__) -#define vmsbc_vx_u8mf4_b32(...) __riscv_vmsbc_vx_u8mf4_b32(__VA_ARGS__) -#define vmsbc_vvm_u8mf2_b16(...) __riscv_vmsbc_vvm_u8mf2_b16(__VA_ARGS__) -#define vmsbc_vxm_u8mf2_b16(...) __riscv_vmsbc_vxm_u8mf2_b16(__VA_ARGS__) -#define vmsbc_vv_u8mf2_b16(...) __riscv_vmsbc_vv_u8mf2_b16(__VA_ARGS__) -#define vmsbc_vx_u8mf2_b16(...) __riscv_vmsbc_vx_u8mf2_b16(__VA_ARGS__) -#define vmsbc_vvm_u8m1_b8(...) __riscv_vmsbc_vvm_u8m1_b8(__VA_ARGS__) -#define vmsbc_vxm_u8m1_b8(...) __riscv_vmsbc_vxm_u8m1_b8(__VA_ARGS__) -#define vmsbc_vv_u8m1_b8(...) __riscv_vmsbc_vv_u8m1_b8(__VA_ARGS__) -#define vmsbc_vx_u8m1_b8(...) __riscv_vmsbc_vx_u8m1_b8(__VA_ARGS__) -#define vmsbc_vvm_u8m2_b4(...) __riscv_vmsbc_vvm_u8m2_b4(__VA_ARGS__) -#define vmsbc_vxm_u8m2_b4(...) __riscv_vmsbc_vxm_u8m2_b4(__VA_ARGS__) -#define vmsbc_vv_u8m2_b4(...) __riscv_vmsbc_vv_u8m2_b4(__VA_ARGS__) -#define vmsbc_vx_u8m2_b4(...) __riscv_vmsbc_vx_u8m2_b4(__VA_ARGS__) -#define vmsbc_vvm_u8m4_b2(...) __riscv_vmsbc_vvm_u8m4_b2(__VA_ARGS__) -#define vmsbc_vxm_u8m4_b2(...) __riscv_vmsbc_vxm_u8m4_b2(__VA_ARGS__) -#define vmsbc_vv_u8m4_b2(...) __riscv_vmsbc_vv_u8m4_b2(__VA_ARGS__) -#define vmsbc_vx_u8m4_b2(...) __riscv_vmsbc_vx_u8m4_b2(__VA_ARGS__) -#define vmsbc_vvm_u8m8_b1(...) __riscv_vmsbc_vvm_u8m8_b1(__VA_ARGS__) -#define vmsbc_vxm_u8m8_b1(...) __riscv_vmsbc_vxm_u8m8_b1(__VA_ARGS__) -#define vmsbc_vv_u8m8_b1(...) __riscv_vmsbc_vv_u8m8_b1(__VA_ARGS__) -#define vmsbc_vx_u8m8_b1(...) __riscv_vmsbc_vx_u8m8_b1(__VA_ARGS__) -#define vmsbc_vvm_u16mf4_b64(...) __riscv_vmsbc_vvm_u16mf4_b64(__VA_ARGS__) -#define vmsbc_vxm_u16mf4_b64(...) __riscv_vmsbc_vxm_u16mf4_b64(__VA_ARGS__) -#define vmsbc_vv_u16mf4_b64(...) __riscv_vmsbc_vv_u16mf4_b64(__VA_ARGS__) -#define vmsbc_vx_u16mf4_b64(...) __riscv_vmsbc_vx_u16mf4_b64(__VA_ARGS__) -#define vmsbc_vvm_u16mf2_b32(...) __riscv_vmsbc_vvm_u16mf2_b32(__VA_ARGS__) -#define vmsbc_vxm_u16mf2_b32(...) __riscv_vmsbc_vxm_u16mf2_b32(__VA_ARGS__) -#define vmsbc_vv_u16mf2_b32(...) __riscv_vmsbc_vv_u16mf2_b32(__VA_ARGS__) -#define vmsbc_vx_u16mf2_b32(...) __riscv_vmsbc_vx_u16mf2_b32(__VA_ARGS__) -#define vmsbc_vvm_u16m1_b16(...) __riscv_vmsbc_vvm_u16m1_b16(__VA_ARGS__) -#define vmsbc_vxm_u16m1_b16(...) __riscv_vmsbc_vxm_u16m1_b16(__VA_ARGS__) -#define vmsbc_vv_u16m1_b16(...) __riscv_vmsbc_vv_u16m1_b16(__VA_ARGS__) -#define vmsbc_vx_u16m1_b16(...) __riscv_vmsbc_vx_u16m1_b16(__VA_ARGS__) -#define vmsbc_vvm_u16m2_b8(...) __riscv_vmsbc_vvm_u16m2_b8(__VA_ARGS__) -#define vmsbc_vxm_u16m2_b8(...) __riscv_vmsbc_vxm_u16m2_b8(__VA_ARGS__) -#define vmsbc_vv_u16m2_b8(...) __riscv_vmsbc_vv_u16m2_b8(__VA_ARGS__) -#define vmsbc_vx_u16m2_b8(...) __riscv_vmsbc_vx_u16m2_b8(__VA_ARGS__) -#define vmsbc_vvm_u16m4_b4(...) __riscv_vmsbc_vvm_u16m4_b4(__VA_ARGS__) -#define vmsbc_vxm_u16m4_b4(...) __riscv_vmsbc_vxm_u16m4_b4(__VA_ARGS__) -#define vmsbc_vv_u16m4_b4(...) __riscv_vmsbc_vv_u16m4_b4(__VA_ARGS__) -#define vmsbc_vx_u16m4_b4(...) __riscv_vmsbc_vx_u16m4_b4(__VA_ARGS__) -#define vmsbc_vvm_u16m8_b2(...) __riscv_vmsbc_vvm_u16m8_b2(__VA_ARGS__) -#define vmsbc_vxm_u16m8_b2(...) __riscv_vmsbc_vxm_u16m8_b2(__VA_ARGS__) -#define vmsbc_vv_u16m8_b2(...) __riscv_vmsbc_vv_u16m8_b2(__VA_ARGS__) -#define vmsbc_vx_u16m8_b2(...) __riscv_vmsbc_vx_u16m8_b2(__VA_ARGS__) -#define vmsbc_vvm_u32mf2_b64(...) __riscv_vmsbc_vvm_u32mf2_b64(__VA_ARGS__) -#define vmsbc_vxm_u32mf2_b64(...) __riscv_vmsbc_vxm_u32mf2_b64(__VA_ARGS__) -#define vmsbc_vv_u32mf2_b64(...) __riscv_vmsbc_vv_u32mf2_b64(__VA_ARGS__) -#define vmsbc_vx_u32mf2_b64(...) __riscv_vmsbc_vx_u32mf2_b64(__VA_ARGS__) -#define vmsbc_vvm_u32m1_b32(...) __riscv_vmsbc_vvm_u32m1_b32(__VA_ARGS__) -#define vmsbc_vxm_u32m1_b32(...) __riscv_vmsbc_vxm_u32m1_b32(__VA_ARGS__) -#define vmsbc_vv_u32m1_b32(...) __riscv_vmsbc_vv_u32m1_b32(__VA_ARGS__) -#define vmsbc_vx_u32m1_b32(...) __riscv_vmsbc_vx_u32m1_b32(__VA_ARGS__) -#define vmsbc_vvm_u32m2_b16(...) __riscv_vmsbc_vvm_u32m2_b16(__VA_ARGS__) -#define vmsbc_vxm_u32m2_b16(...) __riscv_vmsbc_vxm_u32m2_b16(__VA_ARGS__) -#define vmsbc_vv_u32m2_b16(...) __riscv_vmsbc_vv_u32m2_b16(__VA_ARGS__) -#define vmsbc_vx_u32m2_b16(...) __riscv_vmsbc_vx_u32m2_b16(__VA_ARGS__) -#define vmsbc_vvm_u32m4_b8(...) __riscv_vmsbc_vvm_u32m4_b8(__VA_ARGS__) -#define vmsbc_vxm_u32m4_b8(...) __riscv_vmsbc_vxm_u32m4_b8(__VA_ARGS__) -#define vmsbc_vv_u32m4_b8(...) __riscv_vmsbc_vv_u32m4_b8(__VA_ARGS__) -#define vmsbc_vx_u32m4_b8(...) __riscv_vmsbc_vx_u32m4_b8(__VA_ARGS__) -#define vmsbc_vvm_u32m8_b4(...) __riscv_vmsbc_vvm_u32m8_b4(__VA_ARGS__) -#define vmsbc_vxm_u32m8_b4(...) __riscv_vmsbc_vxm_u32m8_b4(__VA_ARGS__) -#define vmsbc_vv_u32m8_b4(...) __riscv_vmsbc_vv_u32m8_b4(__VA_ARGS__) -#define vmsbc_vx_u32m8_b4(...) __riscv_vmsbc_vx_u32m8_b4(__VA_ARGS__) -#define vmsbc_vvm_u64m1_b64(...) __riscv_vmsbc_vvm_u64m1_b64(__VA_ARGS__) -#define vmsbc_vxm_u64m1_b64(...) __riscv_vmsbc_vxm_u64m1_b64(__VA_ARGS__) -#define vmsbc_vv_u64m1_b64(...) __riscv_vmsbc_vv_u64m1_b64(__VA_ARGS__) -#define vmsbc_vx_u64m1_b64(...) __riscv_vmsbc_vx_u64m1_b64(__VA_ARGS__) -#define vmsbc_vvm_u64m2_b32(...) __riscv_vmsbc_vvm_u64m2_b32(__VA_ARGS__) -#define vmsbc_vxm_u64m2_b32(...) __riscv_vmsbc_vxm_u64m2_b32(__VA_ARGS__) -#define vmsbc_vv_u64m2_b32(...) __riscv_vmsbc_vv_u64m2_b32(__VA_ARGS__) -#define vmsbc_vx_u64m2_b32(...) __riscv_vmsbc_vx_u64m2_b32(__VA_ARGS__) -#define vmsbc_vvm_u64m4_b16(...) __riscv_vmsbc_vvm_u64m4_b16(__VA_ARGS__) -#define vmsbc_vxm_u64m4_b16(...) __riscv_vmsbc_vxm_u64m4_b16(__VA_ARGS__) -#define vmsbc_vv_u64m4_b16(...) __riscv_vmsbc_vv_u64m4_b16(__VA_ARGS__) -#define vmsbc_vx_u64m4_b16(...) __riscv_vmsbc_vx_u64m4_b16(__VA_ARGS__) -#define vmsbc_vvm_u64m8_b8(...) __riscv_vmsbc_vvm_u64m8_b8(__VA_ARGS__) -#define vmsbc_vxm_u64m8_b8(...) __riscv_vmsbc_vxm_u64m8_b8(__VA_ARGS__) -#define vmsbc_vv_u64m8_b8(...) __riscv_vmsbc_vv_u64m8_b8(__VA_ARGS__) -#define vmsbc_vx_u64m8_b8(...) __riscv_vmsbc_vx_u64m8_b8(__VA_ARGS__) -#define vand_vv_i8mf8(...) __riscv_vand_vv_i8mf8(__VA_ARGS__) -#define vand_vx_i8mf8(...) __riscv_vand_vx_i8mf8(__VA_ARGS__) -#define vand_vv_i8mf4(...) __riscv_vand_vv_i8mf4(__VA_ARGS__) -#define vand_vx_i8mf4(...) __riscv_vand_vx_i8mf4(__VA_ARGS__) -#define vand_vv_i8mf2(...) __riscv_vand_vv_i8mf2(__VA_ARGS__) -#define vand_vx_i8mf2(...) __riscv_vand_vx_i8mf2(__VA_ARGS__) -#define vand_vv_i8m1(...) __riscv_vand_vv_i8m1(__VA_ARGS__) -#define vand_vx_i8m1(...) __riscv_vand_vx_i8m1(__VA_ARGS__) -#define vand_vv_i8m2(...) __riscv_vand_vv_i8m2(__VA_ARGS__) -#define vand_vx_i8m2(...) __riscv_vand_vx_i8m2(__VA_ARGS__) -#define vand_vv_i8m4(...) __riscv_vand_vv_i8m4(__VA_ARGS__) -#define vand_vx_i8m4(...) __riscv_vand_vx_i8m4(__VA_ARGS__) -#define vand_vv_i8m8(...) __riscv_vand_vv_i8m8(__VA_ARGS__) -#define vand_vx_i8m8(...) __riscv_vand_vx_i8m8(__VA_ARGS__) -#define vand_vv_i16mf4(...) __riscv_vand_vv_i16mf4(__VA_ARGS__) -#define vand_vx_i16mf4(...) __riscv_vand_vx_i16mf4(__VA_ARGS__) -#define vand_vv_i16mf2(...) __riscv_vand_vv_i16mf2(__VA_ARGS__) -#define vand_vx_i16mf2(...) __riscv_vand_vx_i16mf2(__VA_ARGS__) -#define vand_vv_i16m1(...) __riscv_vand_vv_i16m1(__VA_ARGS__) -#define vand_vx_i16m1(...) __riscv_vand_vx_i16m1(__VA_ARGS__) -#define vand_vv_i16m2(...) __riscv_vand_vv_i16m2(__VA_ARGS__) -#define vand_vx_i16m2(...) __riscv_vand_vx_i16m2(__VA_ARGS__) -#define vand_vv_i16m4(...) __riscv_vand_vv_i16m4(__VA_ARGS__) -#define vand_vx_i16m4(...) __riscv_vand_vx_i16m4(__VA_ARGS__) -#define vand_vv_i16m8(...) __riscv_vand_vv_i16m8(__VA_ARGS__) -#define vand_vx_i16m8(...) __riscv_vand_vx_i16m8(__VA_ARGS__) -#define vand_vv_i32mf2(...) __riscv_vand_vv_i32mf2(__VA_ARGS__) -#define vand_vx_i32mf2(...) __riscv_vand_vx_i32mf2(__VA_ARGS__) -#define vand_vv_i32m1(...) __riscv_vand_vv_i32m1(__VA_ARGS__) -#define vand_vx_i32m1(...) __riscv_vand_vx_i32m1(__VA_ARGS__) -#define vand_vv_i32m2(...) __riscv_vand_vv_i32m2(__VA_ARGS__) -#define vand_vx_i32m2(...) __riscv_vand_vx_i32m2(__VA_ARGS__) -#define vand_vv_i32m4(...) __riscv_vand_vv_i32m4(__VA_ARGS__) -#define vand_vx_i32m4(...) __riscv_vand_vx_i32m4(__VA_ARGS__) -#define vand_vv_i32m8(...) __riscv_vand_vv_i32m8(__VA_ARGS__) -#define vand_vx_i32m8(...) __riscv_vand_vx_i32m8(__VA_ARGS__) -#define vand_vv_i64m1(...) __riscv_vand_vv_i64m1(__VA_ARGS__) -#define vand_vx_i64m1(...) __riscv_vand_vx_i64m1(__VA_ARGS__) -#define vand_vv_i64m2(...) __riscv_vand_vv_i64m2(__VA_ARGS__) -#define vand_vx_i64m2(...) __riscv_vand_vx_i64m2(__VA_ARGS__) -#define vand_vv_i64m4(...) __riscv_vand_vv_i64m4(__VA_ARGS__) -#define vand_vx_i64m4(...) __riscv_vand_vx_i64m4(__VA_ARGS__) -#define vand_vv_i64m8(...) __riscv_vand_vv_i64m8(__VA_ARGS__) -#define vand_vx_i64m8(...) __riscv_vand_vx_i64m8(__VA_ARGS__) -#define vor_vv_i8mf8(...) __riscv_vor_vv_i8mf8(__VA_ARGS__) -#define vor_vx_i8mf8(...) __riscv_vor_vx_i8mf8(__VA_ARGS__) -#define vor_vv_i8mf4(...) __riscv_vor_vv_i8mf4(__VA_ARGS__) -#define vor_vx_i8mf4(...) __riscv_vor_vx_i8mf4(__VA_ARGS__) -#define vor_vv_i8mf2(...) __riscv_vor_vv_i8mf2(__VA_ARGS__) -#define vor_vx_i8mf2(...) __riscv_vor_vx_i8mf2(__VA_ARGS__) -#define vor_vv_i8m1(...) __riscv_vor_vv_i8m1(__VA_ARGS__) -#define vor_vx_i8m1(...) __riscv_vor_vx_i8m1(__VA_ARGS__) -#define vor_vv_i8m2(...) __riscv_vor_vv_i8m2(__VA_ARGS__) -#define vor_vx_i8m2(...) __riscv_vor_vx_i8m2(__VA_ARGS__) -#define vor_vv_i8m4(...) __riscv_vor_vv_i8m4(__VA_ARGS__) -#define vor_vx_i8m4(...) __riscv_vor_vx_i8m4(__VA_ARGS__) -#define vor_vv_i8m8(...) __riscv_vor_vv_i8m8(__VA_ARGS__) -#define vor_vx_i8m8(...) __riscv_vor_vx_i8m8(__VA_ARGS__) -#define vor_vv_i16mf4(...) __riscv_vor_vv_i16mf4(__VA_ARGS__) -#define vor_vx_i16mf4(...) __riscv_vor_vx_i16mf4(__VA_ARGS__) -#define vor_vv_i16mf2(...) __riscv_vor_vv_i16mf2(__VA_ARGS__) -#define vor_vx_i16mf2(...) __riscv_vor_vx_i16mf2(__VA_ARGS__) -#define vor_vv_i16m1(...) __riscv_vor_vv_i16m1(__VA_ARGS__) -#define vor_vx_i16m1(...) __riscv_vor_vx_i16m1(__VA_ARGS__) -#define vor_vv_i16m2(...) __riscv_vor_vv_i16m2(__VA_ARGS__) -#define vor_vx_i16m2(...) __riscv_vor_vx_i16m2(__VA_ARGS__) -#define vor_vv_i16m4(...) __riscv_vor_vv_i16m4(__VA_ARGS__) -#define vor_vx_i16m4(...) __riscv_vor_vx_i16m4(__VA_ARGS__) -#define vor_vv_i16m8(...) __riscv_vor_vv_i16m8(__VA_ARGS__) -#define vor_vx_i16m8(...) __riscv_vor_vx_i16m8(__VA_ARGS__) -#define vor_vv_i32mf2(...) __riscv_vor_vv_i32mf2(__VA_ARGS__) -#define vor_vx_i32mf2(...) __riscv_vor_vx_i32mf2(__VA_ARGS__) -#define vor_vv_i32m1(...) __riscv_vor_vv_i32m1(__VA_ARGS__) -#define vor_vx_i32m1(...) __riscv_vor_vx_i32m1(__VA_ARGS__) -#define vor_vv_i32m2(...) __riscv_vor_vv_i32m2(__VA_ARGS__) -#define vor_vx_i32m2(...) __riscv_vor_vx_i32m2(__VA_ARGS__) -#define vor_vv_i32m4(...) __riscv_vor_vv_i32m4(__VA_ARGS__) -#define vor_vx_i32m4(...) __riscv_vor_vx_i32m4(__VA_ARGS__) -#define vor_vv_i32m8(...) __riscv_vor_vv_i32m8(__VA_ARGS__) -#define vor_vx_i32m8(...) __riscv_vor_vx_i32m8(__VA_ARGS__) -#define vor_vv_i64m1(...) __riscv_vor_vv_i64m1(__VA_ARGS__) -#define vor_vx_i64m1(...) __riscv_vor_vx_i64m1(__VA_ARGS__) -#define vor_vv_i64m2(...) __riscv_vor_vv_i64m2(__VA_ARGS__) -#define vor_vx_i64m2(...) __riscv_vor_vx_i64m2(__VA_ARGS__) -#define vor_vv_i64m4(...) __riscv_vor_vv_i64m4(__VA_ARGS__) -#define vor_vx_i64m4(...) __riscv_vor_vx_i64m4(__VA_ARGS__) -#define vor_vv_i64m8(...) __riscv_vor_vv_i64m8(__VA_ARGS__) -#define vor_vx_i64m8(...) __riscv_vor_vx_i64m8(__VA_ARGS__) -#define vxor_vv_i8mf8(...) __riscv_vxor_vv_i8mf8(__VA_ARGS__) -#define vxor_vx_i8mf8(...) __riscv_vxor_vx_i8mf8(__VA_ARGS__) -#define vxor_vv_i8mf4(...) __riscv_vxor_vv_i8mf4(__VA_ARGS__) -#define vxor_vx_i8mf4(...) __riscv_vxor_vx_i8mf4(__VA_ARGS__) -#define vxor_vv_i8mf2(...) __riscv_vxor_vv_i8mf2(__VA_ARGS__) -#define vxor_vx_i8mf2(...) __riscv_vxor_vx_i8mf2(__VA_ARGS__) -#define vxor_vv_i8m1(...) __riscv_vxor_vv_i8m1(__VA_ARGS__) -#define vxor_vx_i8m1(...) __riscv_vxor_vx_i8m1(__VA_ARGS__) -#define vxor_vv_i8m2(...) __riscv_vxor_vv_i8m2(__VA_ARGS__) -#define vxor_vx_i8m2(...) __riscv_vxor_vx_i8m2(__VA_ARGS__) -#define vxor_vv_i8m4(...) __riscv_vxor_vv_i8m4(__VA_ARGS__) -#define vxor_vx_i8m4(...) __riscv_vxor_vx_i8m4(__VA_ARGS__) -#define vxor_vv_i8m8(...) __riscv_vxor_vv_i8m8(__VA_ARGS__) -#define vxor_vx_i8m8(...) __riscv_vxor_vx_i8m8(__VA_ARGS__) -#define vxor_vv_i16mf4(...) __riscv_vxor_vv_i16mf4(__VA_ARGS__) -#define vxor_vx_i16mf4(...) __riscv_vxor_vx_i16mf4(__VA_ARGS__) -#define vxor_vv_i16mf2(...) __riscv_vxor_vv_i16mf2(__VA_ARGS__) -#define vxor_vx_i16mf2(...) __riscv_vxor_vx_i16mf2(__VA_ARGS__) -#define vxor_vv_i16m1(...) __riscv_vxor_vv_i16m1(__VA_ARGS__) -#define vxor_vx_i16m1(...) __riscv_vxor_vx_i16m1(__VA_ARGS__) -#define vxor_vv_i16m2(...) __riscv_vxor_vv_i16m2(__VA_ARGS__) -#define vxor_vx_i16m2(...) __riscv_vxor_vx_i16m2(__VA_ARGS__) -#define vxor_vv_i16m4(...) __riscv_vxor_vv_i16m4(__VA_ARGS__) -#define vxor_vx_i16m4(...) __riscv_vxor_vx_i16m4(__VA_ARGS__) -#define vxor_vv_i16m8(...) __riscv_vxor_vv_i16m8(__VA_ARGS__) -#define vxor_vx_i16m8(...) __riscv_vxor_vx_i16m8(__VA_ARGS__) -#define vxor_vv_i32mf2(...) __riscv_vxor_vv_i32mf2(__VA_ARGS__) -#define vxor_vx_i32mf2(...) __riscv_vxor_vx_i32mf2(__VA_ARGS__) -#define vxor_vv_i32m1(...) __riscv_vxor_vv_i32m1(__VA_ARGS__) -#define vxor_vx_i32m1(...) __riscv_vxor_vx_i32m1(__VA_ARGS__) -#define vxor_vv_i32m2(...) __riscv_vxor_vv_i32m2(__VA_ARGS__) -#define vxor_vx_i32m2(...) __riscv_vxor_vx_i32m2(__VA_ARGS__) -#define vxor_vv_i32m4(...) __riscv_vxor_vv_i32m4(__VA_ARGS__) -#define vxor_vx_i32m4(...) __riscv_vxor_vx_i32m4(__VA_ARGS__) -#define vxor_vv_i32m8(...) __riscv_vxor_vv_i32m8(__VA_ARGS__) -#define vxor_vx_i32m8(...) __riscv_vxor_vx_i32m8(__VA_ARGS__) -#define vxor_vv_i64m1(...) __riscv_vxor_vv_i64m1(__VA_ARGS__) -#define vxor_vx_i64m1(...) __riscv_vxor_vx_i64m1(__VA_ARGS__) -#define vxor_vv_i64m2(...) __riscv_vxor_vv_i64m2(__VA_ARGS__) -#define vxor_vx_i64m2(...) __riscv_vxor_vx_i64m2(__VA_ARGS__) -#define vxor_vv_i64m4(...) __riscv_vxor_vv_i64m4(__VA_ARGS__) -#define vxor_vx_i64m4(...) __riscv_vxor_vx_i64m4(__VA_ARGS__) -#define vxor_vv_i64m8(...) __riscv_vxor_vv_i64m8(__VA_ARGS__) -#define vxor_vx_i64m8(...) __riscv_vxor_vx_i64m8(__VA_ARGS__) -#define vand_vv_u8mf8(...) __riscv_vand_vv_u8mf8(__VA_ARGS__) -#define vand_vx_u8mf8(...) __riscv_vand_vx_u8mf8(__VA_ARGS__) -#define vand_vv_u8mf4(...) __riscv_vand_vv_u8mf4(__VA_ARGS__) -#define vand_vx_u8mf4(...) __riscv_vand_vx_u8mf4(__VA_ARGS__) -#define vand_vv_u8mf2(...) __riscv_vand_vv_u8mf2(__VA_ARGS__) -#define vand_vx_u8mf2(...) __riscv_vand_vx_u8mf2(__VA_ARGS__) -#define vand_vv_u8m1(...) __riscv_vand_vv_u8m1(__VA_ARGS__) -#define vand_vx_u8m1(...) __riscv_vand_vx_u8m1(__VA_ARGS__) -#define vand_vv_u8m2(...) __riscv_vand_vv_u8m2(__VA_ARGS__) -#define vand_vx_u8m2(...) __riscv_vand_vx_u8m2(__VA_ARGS__) -#define vand_vv_u8m4(...) __riscv_vand_vv_u8m4(__VA_ARGS__) -#define vand_vx_u8m4(...) __riscv_vand_vx_u8m4(__VA_ARGS__) -#define vand_vv_u8m8(...) __riscv_vand_vv_u8m8(__VA_ARGS__) -#define vand_vx_u8m8(...) __riscv_vand_vx_u8m8(__VA_ARGS__) -#define vand_vv_u16mf4(...) __riscv_vand_vv_u16mf4(__VA_ARGS__) -#define vand_vx_u16mf4(...) __riscv_vand_vx_u16mf4(__VA_ARGS__) -#define vand_vv_u16mf2(...) __riscv_vand_vv_u16mf2(__VA_ARGS__) -#define vand_vx_u16mf2(...) __riscv_vand_vx_u16mf2(__VA_ARGS__) -#define vand_vv_u16m1(...) __riscv_vand_vv_u16m1(__VA_ARGS__) -#define vand_vx_u16m1(...) __riscv_vand_vx_u16m1(__VA_ARGS__) -#define vand_vv_u16m2(...) __riscv_vand_vv_u16m2(__VA_ARGS__) -#define vand_vx_u16m2(...) __riscv_vand_vx_u16m2(__VA_ARGS__) -#define vand_vv_u16m4(...) __riscv_vand_vv_u16m4(__VA_ARGS__) -#define vand_vx_u16m4(...) __riscv_vand_vx_u16m4(__VA_ARGS__) -#define vand_vv_u16m8(...) __riscv_vand_vv_u16m8(__VA_ARGS__) -#define vand_vx_u16m8(...) __riscv_vand_vx_u16m8(__VA_ARGS__) -#define vand_vv_u32mf2(...) __riscv_vand_vv_u32mf2(__VA_ARGS__) -#define vand_vx_u32mf2(...) __riscv_vand_vx_u32mf2(__VA_ARGS__) -#define vand_vv_u32m1(...) __riscv_vand_vv_u32m1(__VA_ARGS__) -#define vand_vx_u32m1(...) __riscv_vand_vx_u32m1(__VA_ARGS__) -#define vand_vv_u32m2(...) __riscv_vand_vv_u32m2(__VA_ARGS__) -#define vand_vx_u32m2(...) __riscv_vand_vx_u32m2(__VA_ARGS__) -#define vand_vv_u32m4(...) __riscv_vand_vv_u32m4(__VA_ARGS__) -#define vand_vx_u32m4(...) __riscv_vand_vx_u32m4(__VA_ARGS__) -#define vand_vv_u32m8(...) __riscv_vand_vv_u32m8(__VA_ARGS__) -#define vand_vx_u32m8(...) __riscv_vand_vx_u32m8(__VA_ARGS__) -#define vand_vv_u64m1(...) __riscv_vand_vv_u64m1(__VA_ARGS__) -#define vand_vx_u64m1(...) __riscv_vand_vx_u64m1(__VA_ARGS__) -#define vand_vv_u64m2(...) __riscv_vand_vv_u64m2(__VA_ARGS__) -#define vand_vx_u64m2(...) __riscv_vand_vx_u64m2(__VA_ARGS__) -#define vand_vv_u64m4(...) __riscv_vand_vv_u64m4(__VA_ARGS__) -#define vand_vx_u64m4(...) __riscv_vand_vx_u64m4(__VA_ARGS__) -#define vand_vv_u64m8(...) __riscv_vand_vv_u64m8(__VA_ARGS__) -#define vand_vx_u64m8(...) __riscv_vand_vx_u64m8(__VA_ARGS__) -#define vor_vv_u8mf8(...) __riscv_vor_vv_u8mf8(__VA_ARGS__) -#define vor_vx_u8mf8(...) __riscv_vor_vx_u8mf8(__VA_ARGS__) -#define vor_vv_u8mf4(...) __riscv_vor_vv_u8mf4(__VA_ARGS__) -#define vor_vx_u8mf4(...) __riscv_vor_vx_u8mf4(__VA_ARGS__) -#define vor_vv_u8mf2(...) __riscv_vor_vv_u8mf2(__VA_ARGS__) -#define vor_vx_u8mf2(...) __riscv_vor_vx_u8mf2(__VA_ARGS__) -#define vor_vv_u8m1(...) __riscv_vor_vv_u8m1(__VA_ARGS__) -#define vor_vx_u8m1(...) __riscv_vor_vx_u8m1(__VA_ARGS__) -#define vor_vv_u8m2(...) __riscv_vor_vv_u8m2(__VA_ARGS__) -#define vor_vx_u8m2(...) __riscv_vor_vx_u8m2(__VA_ARGS__) -#define vor_vv_u8m4(...) __riscv_vor_vv_u8m4(__VA_ARGS__) -#define vor_vx_u8m4(...) __riscv_vor_vx_u8m4(__VA_ARGS__) -#define vor_vv_u8m8(...) __riscv_vor_vv_u8m8(__VA_ARGS__) -#define vor_vx_u8m8(...) __riscv_vor_vx_u8m8(__VA_ARGS__) -#define vor_vv_u16mf4(...) __riscv_vor_vv_u16mf4(__VA_ARGS__) -#define vor_vx_u16mf4(...) __riscv_vor_vx_u16mf4(__VA_ARGS__) -#define vor_vv_u16mf2(...) __riscv_vor_vv_u16mf2(__VA_ARGS__) -#define vor_vx_u16mf2(...) __riscv_vor_vx_u16mf2(__VA_ARGS__) -#define vor_vv_u16m1(...) __riscv_vor_vv_u16m1(__VA_ARGS__) -#define vor_vx_u16m1(...) __riscv_vor_vx_u16m1(__VA_ARGS__) -#define vor_vv_u16m2(...) __riscv_vor_vv_u16m2(__VA_ARGS__) -#define vor_vx_u16m2(...) __riscv_vor_vx_u16m2(__VA_ARGS__) -#define vor_vv_u16m4(...) __riscv_vor_vv_u16m4(__VA_ARGS__) -#define vor_vx_u16m4(...) __riscv_vor_vx_u16m4(__VA_ARGS__) -#define vor_vv_u16m8(...) __riscv_vor_vv_u16m8(__VA_ARGS__) -#define vor_vx_u16m8(...) __riscv_vor_vx_u16m8(__VA_ARGS__) -#define vor_vv_u32mf2(...) __riscv_vor_vv_u32mf2(__VA_ARGS__) -#define vor_vx_u32mf2(...) __riscv_vor_vx_u32mf2(__VA_ARGS__) -#define vor_vv_u32m1(...) __riscv_vor_vv_u32m1(__VA_ARGS__) -#define vor_vx_u32m1(...) __riscv_vor_vx_u32m1(__VA_ARGS__) -#define vor_vv_u32m2(...) __riscv_vor_vv_u32m2(__VA_ARGS__) -#define vor_vx_u32m2(...) __riscv_vor_vx_u32m2(__VA_ARGS__) -#define vor_vv_u32m4(...) __riscv_vor_vv_u32m4(__VA_ARGS__) -#define vor_vx_u32m4(...) __riscv_vor_vx_u32m4(__VA_ARGS__) -#define vor_vv_u32m8(...) __riscv_vor_vv_u32m8(__VA_ARGS__) -#define vor_vx_u32m8(...) __riscv_vor_vx_u32m8(__VA_ARGS__) -#define vor_vv_u64m1(...) __riscv_vor_vv_u64m1(__VA_ARGS__) -#define vor_vx_u64m1(...) __riscv_vor_vx_u64m1(__VA_ARGS__) -#define vor_vv_u64m2(...) __riscv_vor_vv_u64m2(__VA_ARGS__) -#define vor_vx_u64m2(...) __riscv_vor_vx_u64m2(__VA_ARGS__) -#define vor_vv_u64m4(...) __riscv_vor_vv_u64m4(__VA_ARGS__) -#define vor_vx_u64m4(...) __riscv_vor_vx_u64m4(__VA_ARGS__) -#define vor_vv_u64m8(...) __riscv_vor_vv_u64m8(__VA_ARGS__) -#define vor_vx_u64m8(...) __riscv_vor_vx_u64m8(__VA_ARGS__) -#define vxor_vv_u8mf8(...) __riscv_vxor_vv_u8mf8(__VA_ARGS__) -#define vxor_vx_u8mf8(...) __riscv_vxor_vx_u8mf8(__VA_ARGS__) -#define vxor_vv_u8mf4(...) __riscv_vxor_vv_u8mf4(__VA_ARGS__) -#define vxor_vx_u8mf4(...) __riscv_vxor_vx_u8mf4(__VA_ARGS__) -#define vxor_vv_u8mf2(...) __riscv_vxor_vv_u8mf2(__VA_ARGS__) -#define vxor_vx_u8mf2(...) __riscv_vxor_vx_u8mf2(__VA_ARGS__) -#define vxor_vv_u8m1(...) __riscv_vxor_vv_u8m1(__VA_ARGS__) -#define vxor_vx_u8m1(...) __riscv_vxor_vx_u8m1(__VA_ARGS__) -#define vxor_vv_u8m2(...) __riscv_vxor_vv_u8m2(__VA_ARGS__) -#define vxor_vx_u8m2(...) __riscv_vxor_vx_u8m2(__VA_ARGS__) -#define vxor_vv_u8m4(...) __riscv_vxor_vv_u8m4(__VA_ARGS__) -#define vxor_vx_u8m4(...) __riscv_vxor_vx_u8m4(__VA_ARGS__) -#define vxor_vv_u8m8(...) __riscv_vxor_vv_u8m8(__VA_ARGS__) -#define vxor_vx_u8m8(...) __riscv_vxor_vx_u8m8(__VA_ARGS__) -#define vxor_vv_u16mf4(...) __riscv_vxor_vv_u16mf4(__VA_ARGS__) -#define vxor_vx_u16mf4(...) __riscv_vxor_vx_u16mf4(__VA_ARGS__) -#define vxor_vv_u16mf2(...) __riscv_vxor_vv_u16mf2(__VA_ARGS__) -#define vxor_vx_u16mf2(...) __riscv_vxor_vx_u16mf2(__VA_ARGS__) -#define vxor_vv_u16m1(...) __riscv_vxor_vv_u16m1(__VA_ARGS__) -#define vxor_vx_u16m1(...) __riscv_vxor_vx_u16m1(__VA_ARGS__) -#define vxor_vv_u16m2(...) __riscv_vxor_vv_u16m2(__VA_ARGS__) -#define vxor_vx_u16m2(...) __riscv_vxor_vx_u16m2(__VA_ARGS__) -#define vxor_vv_u16m4(...) __riscv_vxor_vv_u16m4(__VA_ARGS__) -#define vxor_vx_u16m4(...) __riscv_vxor_vx_u16m4(__VA_ARGS__) -#define vxor_vv_u16m8(...) __riscv_vxor_vv_u16m8(__VA_ARGS__) -#define vxor_vx_u16m8(...) __riscv_vxor_vx_u16m8(__VA_ARGS__) -#define vxor_vv_u32mf2(...) __riscv_vxor_vv_u32mf2(__VA_ARGS__) -#define vxor_vx_u32mf2(...) __riscv_vxor_vx_u32mf2(__VA_ARGS__) -#define vxor_vv_u32m1(...) __riscv_vxor_vv_u32m1(__VA_ARGS__) -#define vxor_vx_u32m1(...) __riscv_vxor_vx_u32m1(__VA_ARGS__) -#define vxor_vv_u32m2(...) __riscv_vxor_vv_u32m2(__VA_ARGS__) -#define vxor_vx_u32m2(...) __riscv_vxor_vx_u32m2(__VA_ARGS__) -#define vxor_vv_u32m4(...) __riscv_vxor_vv_u32m4(__VA_ARGS__) -#define vxor_vx_u32m4(...) __riscv_vxor_vx_u32m4(__VA_ARGS__) -#define vxor_vv_u32m8(...) __riscv_vxor_vv_u32m8(__VA_ARGS__) -#define vxor_vx_u32m8(...) __riscv_vxor_vx_u32m8(__VA_ARGS__) -#define vxor_vv_u64m1(...) __riscv_vxor_vv_u64m1(__VA_ARGS__) -#define vxor_vx_u64m1(...) __riscv_vxor_vx_u64m1(__VA_ARGS__) -#define vxor_vv_u64m2(...) __riscv_vxor_vv_u64m2(__VA_ARGS__) -#define vxor_vx_u64m2(...) __riscv_vxor_vx_u64m2(__VA_ARGS__) -#define vxor_vv_u64m4(...) __riscv_vxor_vv_u64m4(__VA_ARGS__) -#define vxor_vx_u64m4(...) __riscv_vxor_vx_u64m4(__VA_ARGS__) -#define vxor_vv_u64m8(...) __riscv_vxor_vv_u64m8(__VA_ARGS__) -#define vxor_vx_u64m8(...) __riscv_vxor_vx_u64m8(__VA_ARGS__) -// masked functions -#define vand_vv_i8mf8_m(...) __riscv_vand_vv_i8mf8_tumu(__VA_ARGS__) -#define vand_vx_i8mf8_m(...) __riscv_vand_vx_i8mf8_tumu(__VA_ARGS__) -#define vand_vv_i8mf4_m(...) __riscv_vand_vv_i8mf4_tumu(__VA_ARGS__) -#define vand_vx_i8mf4_m(...) __riscv_vand_vx_i8mf4_tumu(__VA_ARGS__) -#define vand_vv_i8mf2_m(...) __riscv_vand_vv_i8mf2_tumu(__VA_ARGS__) -#define vand_vx_i8mf2_m(...) __riscv_vand_vx_i8mf2_tumu(__VA_ARGS__) -#define vand_vv_i8m1_m(...) __riscv_vand_vv_i8m1_tumu(__VA_ARGS__) -#define vand_vx_i8m1_m(...) __riscv_vand_vx_i8m1_tumu(__VA_ARGS__) -#define vand_vv_i8m2_m(...) __riscv_vand_vv_i8m2_tumu(__VA_ARGS__) -#define vand_vx_i8m2_m(...) __riscv_vand_vx_i8m2_tumu(__VA_ARGS__) -#define vand_vv_i8m4_m(...) __riscv_vand_vv_i8m4_tumu(__VA_ARGS__) -#define vand_vx_i8m4_m(...) __riscv_vand_vx_i8m4_tumu(__VA_ARGS__) -#define vand_vv_i8m8_m(...) __riscv_vand_vv_i8m8_tumu(__VA_ARGS__) -#define vand_vx_i8m8_m(...) __riscv_vand_vx_i8m8_tumu(__VA_ARGS__) -#define vand_vv_i16mf4_m(...) __riscv_vand_vv_i16mf4_tumu(__VA_ARGS__) -#define vand_vx_i16mf4_m(...) __riscv_vand_vx_i16mf4_tumu(__VA_ARGS__) -#define vand_vv_i16mf2_m(...) __riscv_vand_vv_i16mf2_tumu(__VA_ARGS__) -#define vand_vx_i16mf2_m(...) __riscv_vand_vx_i16mf2_tumu(__VA_ARGS__) -#define vand_vv_i16m1_m(...) __riscv_vand_vv_i16m1_tumu(__VA_ARGS__) -#define vand_vx_i16m1_m(...) __riscv_vand_vx_i16m1_tumu(__VA_ARGS__) -#define vand_vv_i16m2_m(...) __riscv_vand_vv_i16m2_tumu(__VA_ARGS__) -#define vand_vx_i16m2_m(...) __riscv_vand_vx_i16m2_tumu(__VA_ARGS__) -#define vand_vv_i16m4_m(...) __riscv_vand_vv_i16m4_tumu(__VA_ARGS__) -#define vand_vx_i16m4_m(...) __riscv_vand_vx_i16m4_tumu(__VA_ARGS__) -#define vand_vv_i16m8_m(...) __riscv_vand_vv_i16m8_tumu(__VA_ARGS__) -#define vand_vx_i16m8_m(...) __riscv_vand_vx_i16m8_tumu(__VA_ARGS__) -#define vand_vv_i32mf2_m(...) __riscv_vand_vv_i32mf2_tumu(__VA_ARGS__) -#define vand_vx_i32mf2_m(...) __riscv_vand_vx_i32mf2_tumu(__VA_ARGS__) -#define vand_vv_i32m1_m(...) __riscv_vand_vv_i32m1_tumu(__VA_ARGS__) -#define vand_vx_i32m1_m(...) __riscv_vand_vx_i32m1_tumu(__VA_ARGS__) -#define vand_vv_i32m2_m(...) __riscv_vand_vv_i32m2_tumu(__VA_ARGS__) -#define vand_vx_i32m2_m(...) __riscv_vand_vx_i32m2_tumu(__VA_ARGS__) -#define vand_vv_i32m4_m(...) __riscv_vand_vv_i32m4_tumu(__VA_ARGS__) -#define vand_vx_i32m4_m(...) __riscv_vand_vx_i32m4_tumu(__VA_ARGS__) -#define vand_vv_i32m8_m(...) __riscv_vand_vv_i32m8_tumu(__VA_ARGS__) -#define vand_vx_i32m8_m(...) __riscv_vand_vx_i32m8_tumu(__VA_ARGS__) -#define vand_vv_i64m1_m(...) __riscv_vand_vv_i64m1_tumu(__VA_ARGS__) -#define vand_vx_i64m1_m(...) __riscv_vand_vx_i64m1_tumu(__VA_ARGS__) -#define vand_vv_i64m2_m(...) __riscv_vand_vv_i64m2_tumu(__VA_ARGS__) -#define vand_vx_i64m2_m(...) __riscv_vand_vx_i64m2_tumu(__VA_ARGS__) -#define vand_vv_i64m4_m(...) __riscv_vand_vv_i64m4_tumu(__VA_ARGS__) -#define vand_vx_i64m4_m(...) __riscv_vand_vx_i64m4_tumu(__VA_ARGS__) -#define vand_vv_i64m8_m(...) __riscv_vand_vv_i64m8_tumu(__VA_ARGS__) -#define vand_vx_i64m8_m(...) __riscv_vand_vx_i64m8_tumu(__VA_ARGS__) -#define vor_vv_i8mf8_m(...) __riscv_vor_vv_i8mf8_tumu(__VA_ARGS__) -#define vor_vx_i8mf8_m(...) __riscv_vor_vx_i8mf8_tumu(__VA_ARGS__) -#define vor_vv_i8mf4_m(...) __riscv_vor_vv_i8mf4_tumu(__VA_ARGS__) -#define vor_vx_i8mf4_m(...) __riscv_vor_vx_i8mf4_tumu(__VA_ARGS__) -#define vor_vv_i8mf2_m(...) __riscv_vor_vv_i8mf2_tumu(__VA_ARGS__) -#define vor_vx_i8mf2_m(...) __riscv_vor_vx_i8mf2_tumu(__VA_ARGS__) -#define vor_vv_i8m1_m(...) __riscv_vor_vv_i8m1_tumu(__VA_ARGS__) -#define vor_vx_i8m1_m(...) __riscv_vor_vx_i8m1_tumu(__VA_ARGS__) -#define vor_vv_i8m2_m(...) __riscv_vor_vv_i8m2_tumu(__VA_ARGS__) -#define vor_vx_i8m2_m(...) __riscv_vor_vx_i8m2_tumu(__VA_ARGS__) -#define vor_vv_i8m4_m(...) __riscv_vor_vv_i8m4_tumu(__VA_ARGS__) -#define vor_vx_i8m4_m(...) __riscv_vor_vx_i8m4_tumu(__VA_ARGS__) -#define vor_vv_i8m8_m(...) __riscv_vor_vv_i8m8_tumu(__VA_ARGS__) -#define vor_vx_i8m8_m(...) __riscv_vor_vx_i8m8_tumu(__VA_ARGS__) -#define vor_vv_i16mf4_m(...) __riscv_vor_vv_i16mf4_tumu(__VA_ARGS__) -#define vor_vx_i16mf4_m(...) __riscv_vor_vx_i16mf4_tumu(__VA_ARGS__) -#define vor_vv_i16mf2_m(...) __riscv_vor_vv_i16mf2_tumu(__VA_ARGS__) -#define vor_vx_i16mf2_m(...) __riscv_vor_vx_i16mf2_tumu(__VA_ARGS__) -#define vor_vv_i16m1_m(...) __riscv_vor_vv_i16m1_tumu(__VA_ARGS__) -#define vor_vx_i16m1_m(...) __riscv_vor_vx_i16m1_tumu(__VA_ARGS__) -#define vor_vv_i16m2_m(...) __riscv_vor_vv_i16m2_tumu(__VA_ARGS__) -#define vor_vx_i16m2_m(...) __riscv_vor_vx_i16m2_tumu(__VA_ARGS__) -#define vor_vv_i16m4_m(...) __riscv_vor_vv_i16m4_tumu(__VA_ARGS__) -#define vor_vx_i16m4_m(...) __riscv_vor_vx_i16m4_tumu(__VA_ARGS__) -#define vor_vv_i16m8_m(...) __riscv_vor_vv_i16m8_tumu(__VA_ARGS__) -#define vor_vx_i16m8_m(...) __riscv_vor_vx_i16m8_tumu(__VA_ARGS__) -#define vor_vv_i32mf2_m(...) __riscv_vor_vv_i32mf2_tumu(__VA_ARGS__) -#define vor_vx_i32mf2_m(...) __riscv_vor_vx_i32mf2_tumu(__VA_ARGS__) -#define vor_vv_i32m1_m(...) __riscv_vor_vv_i32m1_tumu(__VA_ARGS__) -#define vor_vx_i32m1_m(...) __riscv_vor_vx_i32m1_tumu(__VA_ARGS__) -#define vor_vv_i32m2_m(...) __riscv_vor_vv_i32m2_tumu(__VA_ARGS__) -#define vor_vx_i32m2_m(...) __riscv_vor_vx_i32m2_tumu(__VA_ARGS__) -#define vor_vv_i32m4_m(...) __riscv_vor_vv_i32m4_tumu(__VA_ARGS__) -#define vor_vx_i32m4_m(...) __riscv_vor_vx_i32m4_tumu(__VA_ARGS__) -#define vor_vv_i32m8_m(...) __riscv_vor_vv_i32m8_tumu(__VA_ARGS__) -#define vor_vx_i32m8_m(...) __riscv_vor_vx_i32m8_tumu(__VA_ARGS__) -#define vor_vv_i64m1_m(...) __riscv_vor_vv_i64m1_tumu(__VA_ARGS__) -#define vor_vx_i64m1_m(...) __riscv_vor_vx_i64m1_tumu(__VA_ARGS__) -#define vor_vv_i64m2_m(...) __riscv_vor_vv_i64m2_tumu(__VA_ARGS__) -#define vor_vx_i64m2_m(...) __riscv_vor_vx_i64m2_tumu(__VA_ARGS__) -#define vor_vv_i64m4_m(...) __riscv_vor_vv_i64m4_tumu(__VA_ARGS__) -#define vor_vx_i64m4_m(...) __riscv_vor_vx_i64m4_tumu(__VA_ARGS__) -#define vor_vv_i64m8_m(...) __riscv_vor_vv_i64m8_tumu(__VA_ARGS__) -#define vor_vx_i64m8_m(...) __riscv_vor_vx_i64m8_tumu(__VA_ARGS__) -#define vxor_vv_i8mf8_m(...) __riscv_vxor_vv_i8mf8_tumu(__VA_ARGS__) -#define vxor_vx_i8mf8_m(...) __riscv_vxor_vx_i8mf8_tumu(__VA_ARGS__) -#define vxor_vv_i8mf4_m(...) __riscv_vxor_vv_i8mf4_tumu(__VA_ARGS__) -#define vxor_vx_i8mf4_m(...) __riscv_vxor_vx_i8mf4_tumu(__VA_ARGS__) -#define vxor_vv_i8mf2_m(...) __riscv_vxor_vv_i8mf2_tumu(__VA_ARGS__) -#define vxor_vx_i8mf2_m(...) __riscv_vxor_vx_i8mf2_tumu(__VA_ARGS__) -#define vxor_vv_i8m1_m(...) __riscv_vxor_vv_i8m1_tumu(__VA_ARGS__) -#define vxor_vx_i8m1_m(...) __riscv_vxor_vx_i8m1_tumu(__VA_ARGS__) -#define vxor_vv_i8m2_m(...) __riscv_vxor_vv_i8m2_tumu(__VA_ARGS__) -#define vxor_vx_i8m2_m(...) __riscv_vxor_vx_i8m2_tumu(__VA_ARGS__) -#define vxor_vv_i8m4_m(...) __riscv_vxor_vv_i8m4_tumu(__VA_ARGS__) -#define vxor_vx_i8m4_m(...) __riscv_vxor_vx_i8m4_tumu(__VA_ARGS__) -#define vxor_vv_i8m8_m(...) __riscv_vxor_vv_i8m8_tumu(__VA_ARGS__) -#define vxor_vx_i8m8_m(...) __riscv_vxor_vx_i8m8_tumu(__VA_ARGS__) -#define vxor_vv_i16mf4_m(...) __riscv_vxor_vv_i16mf4_tumu(__VA_ARGS__) -#define vxor_vx_i16mf4_m(...) __riscv_vxor_vx_i16mf4_tumu(__VA_ARGS__) -#define vxor_vv_i16mf2_m(...) __riscv_vxor_vv_i16mf2_tumu(__VA_ARGS__) -#define vxor_vx_i16mf2_m(...) __riscv_vxor_vx_i16mf2_tumu(__VA_ARGS__) -#define vxor_vv_i16m1_m(...) __riscv_vxor_vv_i16m1_tumu(__VA_ARGS__) -#define vxor_vx_i16m1_m(...) __riscv_vxor_vx_i16m1_tumu(__VA_ARGS__) -#define vxor_vv_i16m2_m(...) __riscv_vxor_vv_i16m2_tumu(__VA_ARGS__) -#define vxor_vx_i16m2_m(...) __riscv_vxor_vx_i16m2_tumu(__VA_ARGS__) -#define vxor_vv_i16m4_m(...) __riscv_vxor_vv_i16m4_tumu(__VA_ARGS__) -#define vxor_vx_i16m4_m(...) __riscv_vxor_vx_i16m4_tumu(__VA_ARGS__) -#define vxor_vv_i16m8_m(...) __riscv_vxor_vv_i16m8_tumu(__VA_ARGS__) -#define vxor_vx_i16m8_m(...) __riscv_vxor_vx_i16m8_tumu(__VA_ARGS__) -#define vxor_vv_i32mf2_m(...) __riscv_vxor_vv_i32mf2_tumu(__VA_ARGS__) -#define vxor_vx_i32mf2_m(...) __riscv_vxor_vx_i32mf2_tumu(__VA_ARGS__) -#define vxor_vv_i32m1_m(...) __riscv_vxor_vv_i32m1_tumu(__VA_ARGS__) -#define vxor_vx_i32m1_m(...) __riscv_vxor_vx_i32m1_tumu(__VA_ARGS__) -#define vxor_vv_i32m2_m(...) __riscv_vxor_vv_i32m2_tumu(__VA_ARGS__) -#define vxor_vx_i32m2_m(...) __riscv_vxor_vx_i32m2_tumu(__VA_ARGS__) -#define vxor_vv_i32m4_m(...) __riscv_vxor_vv_i32m4_tumu(__VA_ARGS__) -#define vxor_vx_i32m4_m(...) __riscv_vxor_vx_i32m4_tumu(__VA_ARGS__) -#define vxor_vv_i32m8_m(...) __riscv_vxor_vv_i32m8_tumu(__VA_ARGS__) -#define vxor_vx_i32m8_m(...) __riscv_vxor_vx_i32m8_tumu(__VA_ARGS__) -#define vxor_vv_i64m1_m(...) __riscv_vxor_vv_i64m1_tumu(__VA_ARGS__) -#define vxor_vx_i64m1_m(...) __riscv_vxor_vx_i64m1_tumu(__VA_ARGS__) -#define vxor_vv_i64m2_m(...) __riscv_vxor_vv_i64m2_tumu(__VA_ARGS__) -#define vxor_vx_i64m2_m(...) __riscv_vxor_vx_i64m2_tumu(__VA_ARGS__) -#define vxor_vv_i64m4_m(...) __riscv_vxor_vv_i64m4_tumu(__VA_ARGS__) -#define vxor_vx_i64m4_m(...) __riscv_vxor_vx_i64m4_tumu(__VA_ARGS__) -#define vxor_vv_i64m8_m(...) __riscv_vxor_vv_i64m8_tumu(__VA_ARGS__) -#define vxor_vx_i64m8_m(...) __riscv_vxor_vx_i64m8_tumu(__VA_ARGS__) -#define vand_vv_u8mf8_m(...) __riscv_vand_vv_u8mf8_tumu(__VA_ARGS__) -#define vand_vx_u8mf8_m(...) __riscv_vand_vx_u8mf8_tumu(__VA_ARGS__) -#define vand_vv_u8mf4_m(...) __riscv_vand_vv_u8mf4_tumu(__VA_ARGS__) -#define vand_vx_u8mf4_m(...) __riscv_vand_vx_u8mf4_tumu(__VA_ARGS__) -#define vand_vv_u8mf2_m(...) __riscv_vand_vv_u8mf2_tumu(__VA_ARGS__) -#define vand_vx_u8mf2_m(...) __riscv_vand_vx_u8mf2_tumu(__VA_ARGS__) -#define vand_vv_u8m1_m(...) __riscv_vand_vv_u8m1_tumu(__VA_ARGS__) -#define vand_vx_u8m1_m(...) __riscv_vand_vx_u8m1_tumu(__VA_ARGS__) -#define vand_vv_u8m2_m(...) __riscv_vand_vv_u8m2_tumu(__VA_ARGS__) -#define vand_vx_u8m2_m(...) __riscv_vand_vx_u8m2_tumu(__VA_ARGS__) -#define vand_vv_u8m4_m(...) __riscv_vand_vv_u8m4_tumu(__VA_ARGS__) -#define vand_vx_u8m4_m(...) __riscv_vand_vx_u8m4_tumu(__VA_ARGS__) -#define vand_vv_u8m8_m(...) __riscv_vand_vv_u8m8_tumu(__VA_ARGS__) -#define vand_vx_u8m8_m(...) __riscv_vand_vx_u8m8_tumu(__VA_ARGS__) -#define vand_vv_u16mf4_m(...) __riscv_vand_vv_u16mf4_tumu(__VA_ARGS__) -#define vand_vx_u16mf4_m(...) __riscv_vand_vx_u16mf4_tumu(__VA_ARGS__) -#define vand_vv_u16mf2_m(...) __riscv_vand_vv_u16mf2_tumu(__VA_ARGS__) -#define vand_vx_u16mf2_m(...) __riscv_vand_vx_u16mf2_tumu(__VA_ARGS__) -#define vand_vv_u16m1_m(...) __riscv_vand_vv_u16m1_tumu(__VA_ARGS__) -#define vand_vx_u16m1_m(...) __riscv_vand_vx_u16m1_tumu(__VA_ARGS__) -#define vand_vv_u16m2_m(...) __riscv_vand_vv_u16m2_tumu(__VA_ARGS__) -#define vand_vx_u16m2_m(...) __riscv_vand_vx_u16m2_tumu(__VA_ARGS__) -#define vand_vv_u16m4_m(...) __riscv_vand_vv_u16m4_tumu(__VA_ARGS__) -#define vand_vx_u16m4_m(...) __riscv_vand_vx_u16m4_tumu(__VA_ARGS__) -#define vand_vv_u16m8_m(...) __riscv_vand_vv_u16m8_tumu(__VA_ARGS__) -#define vand_vx_u16m8_m(...) __riscv_vand_vx_u16m8_tumu(__VA_ARGS__) -#define vand_vv_u32mf2_m(...) __riscv_vand_vv_u32mf2_tumu(__VA_ARGS__) -#define vand_vx_u32mf2_m(...) __riscv_vand_vx_u32mf2_tumu(__VA_ARGS__) -#define vand_vv_u32m1_m(...) __riscv_vand_vv_u32m1_tumu(__VA_ARGS__) -#define vand_vx_u32m1_m(...) __riscv_vand_vx_u32m1_tumu(__VA_ARGS__) -#define vand_vv_u32m2_m(...) __riscv_vand_vv_u32m2_tumu(__VA_ARGS__) -#define vand_vx_u32m2_m(...) __riscv_vand_vx_u32m2_tumu(__VA_ARGS__) -#define vand_vv_u32m4_m(...) __riscv_vand_vv_u32m4_tumu(__VA_ARGS__) -#define vand_vx_u32m4_m(...) __riscv_vand_vx_u32m4_tumu(__VA_ARGS__) -#define vand_vv_u32m8_m(...) __riscv_vand_vv_u32m8_tumu(__VA_ARGS__) -#define vand_vx_u32m8_m(...) __riscv_vand_vx_u32m8_tumu(__VA_ARGS__) -#define vand_vv_u64m1_m(...) __riscv_vand_vv_u64m1_tumu(__VA_ARGS__) -#define vand_vx_u64m1_m(...) __riscv_vand_vx_u64m1_tumu(__VA_ARGS__) -#define vand_vv_u64m2_m(...) __riscv_vand_vv_u64m2_tumu(__VA_ARGS__) -#define vand_vx_u64m2_m(...) __riscv_vand_vx_u64m2_tumu(__VA_ARGS__) -#define vand_vv_u64m4_m(...) __riscv_vand_vv_u64m4_tumu(__VA_ARGS__) -#define vand_vx_u64m4_m(...) __riscv_vand_vx_u64m4_tumu(__VA_ARGS__) -#define vand_vv_u64m8_m(...) __riscv_vand_vv_u64m8_tumu(__VA_ARGS__) -#define vand_vx_u64m8_m(...) __riscv_vand_vx_u64m8_tumu(__VA_ARGS__) -#define vor_vv_u8mf8_m(...) __riscv_vor_vv_u8mf8_tumu(__VA_ARGS__) -#define vor_vx_u8mf8_m(...) __riscv_vor_vx_u8mf8_tumu(__VA_ARGS__) -#define vor_vv_u8mf4_m(...) __riscv_vor_vv_u8mf4_tumu(__VA_ARGS__) -#define vor_vx_u8mf4_m(...) __riscv_vor_vx_u8mf4_tumu(__VA_ARGS__) -#define vor_vv_u8mf2_m(...) __riscv_vor_vv_u8mf2_tumu(__VA_ARGS__) -#define vor_vx_u8mf2_m(...) __riscv_vor_vx_u8mf2_tumu(__VA_ARGS__) -#define vor_vv_u8m1_m(...) __riscv_vor_vv_u8m1_tumu(__VA_ARGS__) -#define vor_vx_u8m1_m(...) __riscv_vor_vx_u8m1_tumu(__VA_ARGS__) -#define vor_vv_u8m2_m(...) __riscv_vor_vv_u8m2_tumu(__VA_ARGS__) -#define vor_vx_u8m2_m(...) __riscv_vor_vx_u8m2_tumu(__VA_ARGS__) -#define vor_vv_u8m4_m(...) __riscv_vor_vv_u8m4_tumu(__VA_ARGS__) -#define vor_vx_u8m4_m(...) __riscv_vor_vx_u8m4_tumu(__VA_ARGS__) -#define vor_vv_u8m8_m(...) __riscv_vor_vv_u8m8_tumu(__VA_ARGS__) -#define vor_vx_u8m8_m(...) __riscv_vor_vx_u8m8_tumu(__VA_ARGS__) -#define vor_vv_u16mf4_m(...) __riscv_vor_vv_u16mf4_tumu(__VA_ARGS__) -#define vor_vx_u16mf4_m(...) __riscv_vor_vx_u16mf4_tumu(__VA_ARGS__) -#define vor_vv_u16mf2_m(...) __riscv_vor_vv_u16mf2_tumu(__VA_ARGS__) -#define vor_vx_u16mf2_m(...) __riscv_vor_vx_u16mf2_tumu(__VA_ARGS__) -#define vor_vv_u16m1_m(...) __riscv_vor_vv_u16m1_tumu(__VA_ARGS__) -#define vor_vx_u16m1_m(...) __riscv_vor_vx_u16m1_tumu(__VA_ARGS__) -#define vor_vv_u16m2_m(...) __riscv_vor_vv_u16m2_tumu(__VA_ARGS__) -#define vor_vx_u16m2_m(...) __riscv_vor_vx_u16m2_tumu(__VA_ARGS__) -#define vor_vv_u16m4_m(...) __riscv_vor_vv_u16m4_tumu(__VA_ARGS__) -#define vor_vx_u16m4_m(...) __riscv_vor_vx_u16m4_tumu(__VA_ARGS__) -#define vor_vv_u16m8_m(...) __riscv_vor_vv_u16m8_tumu(__VA_ARGS__) -#define vor_vx_u16m8_m(...) __riscv_vor_vx_u16m8_tumu(__VA_ARGS__) -#define vor_vv_u32mf2_m(...) __riscv_vor_vv_u32mf2_tumu(__VA_ARGS__) -#define vor_vx_u32mf2_m(...) __riscv_vor_vx_u32mf2_tumu(__VA_ARGS__) -#define vor_vv_u32m1_m(...) __riscv_vor_vv_u32m1_tumu(__VA_ARGS__) -#define vor_vx_u32m1_m(...) __riscv_vor_vx_u32m1_tumu(__VA_ARGS__) -#define vor_vv_u32m2_m(...) __riscv_vor_vv_u32m2_tumu(__VA_ARGS__) -#define vor_vx_u32m2_m(...) __riscv_vor_vx_u32m2_tumu(__VA_ARGS__) -#define vor_vv_u32m4_m(...) __riscv_vor_vv_u32m4_tumu(__VA_ARGS__) -#define vor_vx_u32m4_m(...) __riscv_vor_vx_u32m4_tumu(__VA_ARGS__) -#define vor_vv_u32m8_m(...) __riscv_vor_vv_u32m8_tumu(__VA_ARGS__) -#define vor_vx_u32m8_m(...) __riscv_vor_vx_u32m8_tumu(__VA_ARGS__) -#define vor_vv_u64m1_m(...) __riscv_vor_vv_u64m1_tumu(__VA_ARGS__) -#define vor_vx_u64m1_m(...) __riscv_vor_vx_u64m1_tumu(__VA_ARGS__) -#define vor_vv_u64m2_m(...) __riscv_vor_vv_u64m2_tumu(__VA_ARGS__) -#define vor_vx_u64m2_m(...) __riscv_vor_vx_u64m2_tumu(__VA_ARGS__) -#define vor_vv_u64m4_m(...) __riscv_vor_vv_u64m4_tumu(__VA_ARGS__) -#define vor_vx_u64m4_m(...) __riscv_vor_vx_u64m4_tumu(__VA_ARGS__) -#define vor_vv_u64m8_m(...) __riscv_vor_vv_u64m8_tumu(__VA_ARGS__) -#define vor_vx_u64m8_m(...) __riscv_vor_vx_u64m8_tumu(__VA_ARGS__) -#define vxor_vv_u8mf8_m(...) __riscv_vxor_vv_u8mf8_tumu(__VA_ARGS__) -#define vxor_vx_u8mf8_m(...) __riscv_vxor_vx_u8mf8_tumu(__VA_ARGS__) -#define vxor_vv_u8mf4_m(...) __riscv_vxor_vv_u8mf4_tumu(__VA_ARGS__) -#define vxor_vx_u8mf4_m(...) __riscv_vxor_vx_u8mf4_tumu(__VA_ARGS__) -#define vxor_vv_u8mf2_m(...) __riscv_vxor_vv_u8mf2_tumu(__VA_ARGS__) -#define vxor_vx_u8mf2_m(...) __riscv_vxor_vx_u8mf2_tumu(__VA_ARGS__) -#define vxor_vv_u8m1_m(...) __riscv_vxor_vv_u8m1_tumu(__VA_ARGS__) -#define vxor_vx_u8m1_m(...) __riscv_vxor_vx_u8m1_tumu(__VA_ARGS__) -#define vxor_vv_u8m2_m(...) __riscv_vxor_vv_u8m2_tumu(__VA_ARGS__) -#define vxor_vx_u8m2_m(...) __riscv_vxor_vx_u8m2_tumu(__VA_ARGS__) -#define vxor_vv_u8m4_m(...) __riscv_vxor_vv_u8m4_tumu(__VA_ARGS__) -#define vxor_vx_u8m4_m(...) __riscv_vxor_vx_u8m4_tumu(__VA_ARGS__) -#define vxor_vv_u8m8_m(...) __riscv_vxor_vv_u8m8_tumu(__VA_ARGS__) -#define vxor_vx_u8m8_m(...) __riscv_vxor_vx_u8m8_tumu(__VA_ARGS__) -#define vxor_vv_u16mf4_m(...) __riscv_vxor_vv_u16mf4_tumu(__VA_ARGS__) -#define vxor_vx_u16mf4_m(...) __riscv_vxor_vx_u16mf4_tumu(__VA_ARGS__) -#define vxor_vv_u16mf2_m(...) __riscv_vxor_vv_u16mf2_tumu(__VA_ARGS__) -#define vxor_vx_u16mf2_m(...) __riscv_vxor_vx_u16mf2_tumu(__VA_ARGS__) -#define vxor_vv_u16m1_m(...) __riscv_vxor_vv_u16m1_tumu(__VA_ARGS__) -#define vxor_vx_u16m1_m(...) __riscv_vxor_vx_u16m1_tumu(__VA_ARGS__) -#define vxor_vv_u16m2_m(...) __riscv_vxor_vv_u16m2_tumu(__VA_ARGS__) -#define vxor_vx_u16m2_m(...) __riscv_vxor_vx_u16m2_tumu(__VA_ARGS__) -#define vxor_vv_u16m4_m(...) __riscv_vxor_vv_u16m4_tumu(__VA_ARGS__) -#define vxor_vx_u16m4_m(...) __riscv_vxor_vx_u16m4_tumu(__VA_ARGS__) -#define vxor_vv_u16m8_m(...) __riscv_vxor_vv_u16m8_tumu(__VA_ARGS__) -#define vxor_vx_u16m8_m(...) __riscv_vxor_vx_u16m8_tumu(__VA_ARGS__) -#define vxor_vv_u32mf2_m(...) __riscv_vxor_vv_u32mf2_tumu(__VA_ARGS__) -#define vxor_vx_u32mf2_m(...) __riscv_vxor_vx_u32mf2_tumu(__VA_ARGS__) -#define vxor_vv_u32m1_m(...) __riscv_vxor_vv_u32m1_tumu(__VA_ARGS__) -#define vxor_vx_u32m1_m(...) __riscv_vxor_vx_u32m1_tumu(__VA_ARGS__) -#define vxor_vv_u32m2_m(...) __riscv_vxor_vv_u32m2_tumu(__VA_ARGS__) -#define vxor_vx_u32m2_m(...) __riscv_vxor_vx_u32m2_tumu(__VA_ARGS__) -#define vxor_vv_u32m4_m(...) __riscv_vxor_vv_u32m4_tumu(__VA_ARGS__) -#define vxor_vx_u32m4_m(...) __riscv_vxor_vx_u32m4_tumu(__VA_ARGS__) -#define vxor_vv_u32m8_m(...) __riscv_vxor_vv_u32m8_tumu(__VA_ARGS__) -#define vxor_vx_u32m8_m(...) __riscv_vxor_vx_u32m8_tumu(__VA_ARGS__) -#define vxor_vv_u64m1_m(...) __riscv_vxor_vv_u64m1_tumu(__VA_ARGS__) -#define vxor_vx_u64m1_m(...) __riscv_vxor_vx_u64m1_tumu(__VA_ARGS__) -#define vxor_vv_u64m2_m(...) __riscv_vxor_vv_u64m2_tumu(__VA_ARGS__) -#define vxor_vx_u64m2_m(...) __riscv_vxor_vx_u64m2_tumu(__VA_ARGS__) -#define vxor_vv_u64m4_m(...) __riscv_vxor_vv_u64m4_tumu(__VA_ARGS__) -#define vxor_vx_u64m4_m(...) __riscv_vxor_vx_u64m4_tumu(__VA_ARGS__) -#define vxor_vv_u64m8_m(...) __riscv_vxor_vv_u64m8_tumu(__VA_ARGS__) -#define vxor_vx_u64m8_m(...) __riscv_vxor_vx_u64m8_tumu(__VA_ARGS__) -#define vnot_v_i8mf8(...) __riscv_vnot_v_i8mf8(__VA_ARGS__) -#define vnot_v_i8mf4(...) __riscv_vnot_v_i8mf4(__VA_ARGS__) -#define vnot_v_i8mf2(...) __riscv_vnot_v_i8mf2(__VA_ARGS__) -#define vnot_v_i8m1(...) __riscv_vnot_v_i8m1(__VA_ARGS__) -#define vnot_v_i8m2(...) __riscv_vnot_v_i8m2(__VA_ARGS__) -#define vnot_v_i8m4(...) __riscv_vnot_v_i8m4(__VA_ARGS__) -#define vnot_v_i8m8(...) __riscv_vnot_v_i8m8(__VA_ARGS__) -#define vnot_v_i16mf4(...) __riscv_vnot_v_i16mf4(__VA_ARGS__) -#define vnot_v_i16mf2(...) __riscv_vnot_v_i16mf2(__VA_ARGS__) -#define vnot_v_i16m1(...) __riscv_vnot_v_i16m1(__VA_ARGS__) -#define vnot_v_i16m2(...) __riscv_vnot_v_i16m2(__VA_ARGS__) -#define vnot_v_i16m4(...) __riscv_vnot_v_i16m4(__VA_ARGS__) -#define vnot_v_i16m8(...) __riscv_vnot_v_i16m8(__VA_ARGS__) -#define vnot_v_i32mf2(...) __riscv_vnot_v_i32mf2(__VA_ARGS__) -#define vnot_v_i32m1(...) __riscv_vnot_v_i32m1(__VA_ARGS__) -#define vnot_v_i32m2(...) __riscv_vnot_v_i32m2(__VA_ARGS__) -#define vnot_v_i32m4(...) __riscv_vnot_v_i32m4(__VA_ARGS__) -#define vnot_v_i32m8(...) __riscv_vnot_v_i32m8(__VA_ARGS__) -#define vnot_v_i64m1(...) __riscv_vnot_v_i64m1(__VA_ARGS__) -#define vnot_v_i64m2(...) __riscv_vnot_v_i64m2(__VA_ARGS__) -#define vnot_v_i64m4(...) __riscv_vnot_v_i64m4(__VA_ARGS__) -#define vnot_v_i64m8(...) __riscv_vnot_v_i64m8(__VA_ARGS__) -#define vnot_v_u8mf8(...) __riscv_vnot_v_u8mf8(__VA_ARGS__) -#define vnot_v_u8mf4(...) __riscv_vnot_v_u8mf4(__VA_ARGS__) -#define vnot_v_u8mf2(...) __riscv_vnot_v_u8mf2(__VA_ARGS__) -#define vnot_v_u8m1(...) __riscv_vnot_v_u8m1(__VA_ARGS__) -#define vnot_v_u8m2(...) __riscv_vnot_v_u8m2(__VA_ARGS__) -#define vnot_v_u8m4(...) __riscv_vnot_v_u8m4(__VA_ARGS__) -#define vnot_v_u8m8(...) __riscv_vnot_v_u8m8(__VA_ARGS__) -#define vnot_v_u16mf4(...) __riscv_vnot_v_u16mf4(__VA_ARGS__) -#define vnot_v_u16mf2(...) __riscv_vnot_v_u16mf2(__VA_ARGS__) -#define vnot_v_u16m1(...) __riscv_vnot_v_u16m1(__VA_ARGS__) -#define vnot_v_u16m2(...) __riscv_vnot_v_u16m2(__VA_ARGS__) -#define vnot_v_u16m4(...) __riscv_vnot_v_u16m4(__VA_ARGS__) -#define vnot_v_u16m8(...) __riscv_vnot_v_u16m8(__VA_ARGS__) -#define vnot_v_u32mf2(...) __riscv_vnot_v_u32mf2(__VA_ARGS__) -#define vnot_v_u32m1(...) __riscv_vnot_v_u32m1(__VA_ARGS__) -#define vnot_v_u32m2(...) __riscv_vnot_v_u32m2(__VA_ARGS__) -#define vnot_v_u32m4(...) __riscv_vnot_v_u32m4(__VA_ARGS__) -#define vnot_v_u32m8(...) __riscv_vnot_v_u32m8(__VA_ARGS__) -#define vnot_v_u64m1(...) __riscv_vnot_v_u64m1(__VA_ARGS__) -#define vnot_v_u64m2(...) __riscv_vnot_v_u64m2(__VA_ARGS__) -#define vnot_v_u64m4(...) __riscv_vnot_v_u64m4(__VA_ARGS__) -#define vnot_v_u64m8(...) __riscv_vnot_v_u64m8(__VA_ARGS__) -// masked functions -#define vnot_v_i8mf8_m(...) __riscv_vnot_v_i8mf8_tumu(__VA_ARGS__) -#define vnot_v_i8mf4_m(...) __riscv_vnot_v_i8mf4_tumu(__VA_ARGS__) -#define vnot_v_i8mf2_m(...) __riscv_vnot_v_i8mf2_tumu(__VA_ARGS__) -#define vnot_v_i8m1_m(...) __riscv_vnot_v_i8m1_tumu(__VA_ARGS__) -#define vnot_v_i8m2_m(...) __riscv_vnot_v_i8m2_tumu(__VA_ARGS__) -#define vnot_v_i8m4_m(...) __riscv_vnot_v_i8m4_tumu(__VA_ARGS__) -#define vnot_v_i8m8_m(...) __riscv_vnot_v_i8m8_tumu(__VA_ARGS__) -#define vnot_v_i16mf4_m(...) __riscv_vnot_v_i16mf4_tumu(__VA_ARGS__) -#define vnot_v_i16mf2_m(...) __riscv_vnot_v_i16mf2_tumu(__VA_ARGS__) -#define vnot_v_i16m1_m(...) __riscv_vnot_v_i16m1_tumu(__VA_ARGS__) -#define vnot_v_i16m2_m(...) __riscv_vnot_v_i16m2_tumu(__VA_ARGS__) -#define vnot_v_i16m4_m(...) __riscv_vnot_v_i16m4_tumu(__VA_ARGS__) -#define vnot_v_i16m8_m(...) __riscv_vnot_v_i16m8_tumu(__VA_ARGS__) -#define vnot_v_i32mf2_m(...) __riscv_vnot_v_i32mf2_tumu(__VA_ARGS__) -#define vnot_v_i32m1_m(...) __riscv_vnot_v_i32m1_tumu(__VA_ARGS__) -#define vnot_v_i32m2_m(...) __riscv_vnot_v_i32m2_tumu(__VA_ARGS__) -#define vnot_v_i32m4_m(...) __riscv_vnot_v_i32m4_tumu(__VA_ARGS__) -#define vnot_v_i32m8_m(...) __riscv_vnot_v_i32m8_tumu(__VA_ARGS__) -#define vnot_v_i64m1_m(...) __riscv_vnot_v_i64m1_tumu(__VA_ARGS__) -#define vnot_v_i64m2_m(...) __riscv_vnot_v_i64m2_tumu(__VA_ARGS__) -#define vnot_v_i64m4_m(...) __riscv_vnot_v_i64m4_tumu(__VA_ARGS__) -#define vnot_v_i64m8_m(...) __riscv_vnot_v_i64m8_tumu(__VA_ARGS__) -#define vnot_v_u8mf8_m(...) __riscv_vnot_v_u8mf8_tumu(__VA_ARGS__) -#define vnot_v_u8mf4_m(...) __riscv_vnot_v_u8mf4_tumu(__VA_ARGS__) -#define vnot_v_u8mf2_m(...) __riscv_vnot_v_u8mf2_tumu(__VA_ARGS__) -#define vnot_v_u8m1_m(...) __riscv_vnot_v_u8m1_tumu(__VA_ARGS__) -#define vnot_v_u8m2_m(...) __riscv_vnot_v_u8m2_tumu(__VA_ARGS__) -#define vnot_v_u8m4_m(...) __riscv_vnot_v_u8m4_tumu(__VA_ARGS__) -#define vnot_v_u8m8_m(...) __riscv_vnot_v_u8m8_tumu(__VA_ARGS__) -#define vnot_v_u16mf4_m(...) __riscv_vnot_v_u16mf4_tumu(__VA_ARGS__) -#define vnot_v_u16mf2_m(...) __riscv_vnot_v_u16mf2_tumu(__VA_ARGS__) -#define vnot_v_u16m1_m(...) __riscv_vnot_v_u16m1_tumu(__VA_ARGS__) -#define vnot_v_u16m2_m(...) __riscv_vnot_v_u16m2_tumu(__VA_ARGS__) -#define vnot_v_u16m4_m(...) __riscv_vnot_v_u16m4_tumu(__VA_ARGS__) -#define vnot_v_u16m8_m(...) __riscv_vnot_v_u16m8_tumu(__VA_ARGS__) -#define vnot_v_u32mf2_m(...) __riscv_vnot_v_u32mf2_tumu(__VA_ARGS__) -#define vnot_v_u32m1_m(...) __riscv_vnot_v_u32m1_tumu(__VA_ARGS__) -#define vnot_v_u32m2_m(...) __riscv_vnot_v_u32m2_tumu(__VA_ARGS__) -#define vnot_v_u32m4_m(...) __riscv_vnot_v_u32m4_tumu(__VA_ARGS__) -#define vnot_v_u32m8_m(...) __riscv_vnot_v_u32m8_tumu(__VA_ARGS__) -#define vnot_v_u64m1_m(...) __riscv_vnot_v_u64m1_tumu(__VA_ARGS__) -#define vnot_v_u64m2_m(...) __riscv_vnot_v_u64m2_tumu(__VA_ARGS__) -#define vnot_v_u64m4_m(...) __riscv_vnot_v_u64m4_tumu(__VA_ARGS__) -#define vnot_v_u64m8_m(...) __riscv_vnot_v_u64m8_tumu(__VA_ARGS__) -#define vsll_vv_i8mf8(...) __riscv_vsll_vv_i8mf8(__VA_ARGS__) -#define vsll_vx_i8mf8(...) __riscv_vsll_vx_i8mf8(__VA_ARGS__) -#define vsll_vv_i8mf4(...) __riscv_vsll_vv_i8mf4(__VA_ARGS__) -#define vsll_vx_i8mf4(...) __riscv_vsll_vx_i8mf4(__VA_ARGS__) -#define vsll_vv_i8mf2(...) __riscv_vsll_vv_i8mf2(__VA_ARGS__) -#define vsll_vx_i8mf2(...) __riscv_vsll_vx_i8mf2(__VA_ARGS__) -#define vsll_vv_i8m1(...) __riscv_vsll_vv_i8m1(__VA_ARGS__) -#define vsll_vx_i8m1(...) __riscv_vsll_vx_i8m1(__VA_ARGS__) -#define vsll_vv_i8m2(...) __riscv_vsll_vv_i8m2(__VA_ARGS__) -#define vsll_vx_i8m2(...) __riscv_vsll_vx_i8m2(__VA_ARGS__) -#define vsll_vv_i8m4(...) __riscv_vsll_vv_i8m4(__VA_ARGS__) -#define vsll_vx_i8m4(...) __riscv_vsll_vx_i8m4(__VA_ARGS__) -#define vsll_vv_i8m8(...) __riscv_vsll_vv_i8m8(__VA_ARGS__) -#define vsll_vx_i8m8(...) __riscv_vsll_vx_i8m8(__VA_ARGS__) -#define vsll_vv_i16mf4(...) __riscv_vsll_vv_i16mf4(__VA_ARGS__) -#define vsll_vx_i16mf4(...) __riscv_vsll_vx_i16mf4(__VA_ARGS__) -#define vsll_vv_i16mf2(...) __riscv_vsll_vv_i16mf2(__VA_ARGS__) -#define vsll_vx_i16mf2(...) __riscv_vsll_vx_i16mf2(__VA_ARGS__) -#define vsll_vv_i16m1(...) __riscv_vsll_vv_i16m1(__VA_ARGS__) -#define vsll_vx_i16m1(...) __riscv_vsll_vx_i16m1(__VA_ARGS__) -#define vsll_vv_i16m2(...) __riscv_vsll_vv_i16m2(__VA_ARGS__) -#define vsll_vx_i16m2(...) __riscv_vsll_vx_i16m2(__VA_ARGS__) -#define vsll_vv_i16m4(...) __riscv_vsll_vv_i16m4(__VA_ARGS__) -#define vsll_vx_i16m4(...) __riscv_vsll_vx_i16m4(__VA_ARGS__) -#define vsll_vv_i16m8(...) __riscv_vsll_vv_i16m8(__VA_ARGS__) -#define vsll_vx_i16m8(...) __riscv_vsll_vx_i16m8(__VA_ARGS__) -#define vsll_vv_i32mf2(...) __riscv_vsll_vv_i32mf2(__VA_ARGS__) -#define vsll_vx_i32mf2(...) __riscv_vsll_vx_i32mf2(__VA_ARGS__) -#define vsll_vv_i32m1(...) __riscv_vsll_vv_i32m1(__VA_ARGS__) -#define vsll_vx_i32m1(...) __riscv_vsll_vx_i32m1(__VA_ARGS__) -#define vsll_vv_i32m2(...) __riscv_vsll_vv_i32m2(__VA_ARGS__) -#define vsll_vx_i32m2(...) __riscv_vsll_vx_i32m2(__VA_ARGS__) -#define vsll_vv_i32m4(...) __riscv_vsll_vv_i32m4(__VA_ARGS__) -#define vsll_vx_i32m4(...) __riscv_vsll_vx_i32m4(__VA_ARGS__) -#define vsll_vv_i32m8(...) __riscv_vsll_vv_i32m8(__VA_ARGS__) -#define vsll_vx_i32m8(...) __riscv_vsll_vx_i32m8(__VA_ARGS__) -#define vsll_vv_i64m1(...) __riscv_vsll_vv_i64m1(__VA_ARGS__) -#define vsll_vx_i64m1(...) __riscv_vsll_vx_i64m1(__VA_ARGS__) -#define vsll_vv_i64m2(...) __riscv_vsll_vv_i64m2(__VA_ARGS__) -#define vsll_vx_i64m2(...) __riscv_vsll_vx_i64m2(__VA_ARGS__) -#define vsll_vv_i64m4(...) __riscv_vsll_vv_i64m4(__VA_ARGS__) -#define vsll_vx_i64m4(...) __riscv_vsll_vx_i64m4(__VA_ARGS__) -#define vsll_vv_i64m8(...) __riscv_vsll_vv_i64m8(__VA_ARGS__) -#define vsll_vx_i64m8(...) __riscv_vsll_vx_i64m8(__VA_ARGS__) -#define vsra_vv_i8mf8(...) __riscv_vsra_vv_i8mf8(__VA_ARGS__) -#define vsra_vx_i8mf8(...) __riscv_vsra_vx_i8mf8(__VA_ARGS__) -#define vsra_vv_i8mf4(...) __riscv_vsra_vv_i8mf4(__VA_ARGS__) -#define vsra_vx_i8mf4(...) __riscv_vsra_vx_i8mf4(__VA_ARGS__) -#define vsra_vv_i8mf2(...) __riscv_vsra_vv_i8mf2(__VA_ARGS__) -#define vsra_vx_i8mf2(...) __riscv_vsra_vx_i8mf2(__VA_ARGS__) -#define vsra_vv_i8m1(...) __riscv_vsra_vv_i8m1(__VA_ARGS__) -#define vsra_vx_i8m1(...) __riscv_vsra_vx_i8m1(__VA_ARGS__) -#define vsra_vv_i8m2(...) __riscv_vsra_vv_i8m2(__VA_ARGS__) -#define vsra_vx_i8m2(...) __riscv_vsra_vx_i8m2(__VA_ARGS__) -#define vsra_vv_i8m4(...) __riscv_vsra_vv_i8m4(__VA_ARGS__) -#define vsra_vx_i8m4(...) __riscv_vsra_vx_i8m4(__VA_ARGS__) -#define vsra_vv_i8m8(...) __riscv_vsra_vv_i8m8(__VA_ARGS__) -#define vsra_vx_i8m8(...) __riscv_vsra_vx_i8m8(__VA_ARGS__) -#define vsra_vv_i16mf4(...) __riscv_vsra_vv_i16mf4(__VA_ARGS__) -#define vsra_vx_i16mf4(...) __riscv_vsra_vx_i16mf4(__VA_ARGS__) -#define vsra_vv_i16mf2(...) __riscv_vsra_vv_i16mf2(__VA_ARGS__) -#define vsra_vx_i16mf2(...) __riscv_vsra_vx_i16mf2(__VA_ARGS__) -#define vsra_vv_i16m1(...) __riscv_vsra_vv_i16m1(__VA_ARGS__) -#define vsra_vx_i16m1(...) __riscv_vsra_vx_i16m1(__VA_ARGS__) -#define vsra_vv_i16m2(...) __riscv_vsra_vv_i16m2(__VA_ARGS__) -#define vsra_vx_i16m2(...) __riscv_vsra_vx_i16m2(__VA_ARGS__) -#define vsra_vv_i16m4(...) __riscv_vsra_vv_i16m4(__VA_ARGS__) -#define vsra_vx_i16m4(...) __riscv_vsra_vx_i16m4(__VA_ARGS__) -#define vsra_vv_i16m8(...) __riscv_vsra_vv_i16m8(__VA_ARGS__) -#define vsra_vx_i16m8(...) __riscv_vsra_vx_i16m8(__VA_ARGS__) -#define vsra_vv_i32mf2(...) __riscv_vsra_vv_i32mf2(__VA_ARGS__) -#define vsra_vx_i32mf2(...) __riscv_vsra_vx_i32mf2(__VA_ARGS__) -#define vsra_vv_i32m1(...) __riscv_vsra_vv_i32m1(__VA_ARGS__) -#define vsra_vx_i32m1(...) __riscv_vsra_vx_i32m1(__VA_ARGS__) -#define vsra_vv_i32m2(...) __riscv_vsra_vv_i32m2(__VA_ARGS__) -#define vsra_vx_i32m2(...) __riscv_vsra_vx_i32m2(__VA_ARGS__) -#define vsra_vv_i32m4(...) __riscv_vsra_vv_i32m4(__VA_ARGS__) -#define vsra_vx_i32m4(...) __riscv_vsra_vx_i32m4(__VA_ARGS__) -#define vsra_vv_i32m8(...) __riscv_vsra_vv_i32m8(__VA_ARGS__) -#define vsra_vx_i32m8(...) __riscv_vsra_vx_i32m8(__VA_ARGS__) -#define vsra_vv_i64m1(...) __riscv_vsra_vv_i64m1(__VA_ARGS__) -#define vsra_vx_i64m1(...) __riscv_vsra_vx_i64m1(__VA_ARGS__) -#define vsra_vv_i64m2(...) __riscv_vsra_vv_i64m2(__VA_ARGS__) -#define vsra_vx_i64m2(...) __riscv_vsra_vx_i64m2(__VA_ARGS__) -#define vsra_vv_i64m4(...) __riscv_vsra_vv_i64m4(__VA_ARGS__) -#define vsra_vx_i64m4(...) __riscv_vsra_vx_i64m4(__VA_ARGS__) -#define vsra_vv_i64m8(...) __riscv_vsra_vv_i64m8(__VA_ARGS__) -#define vsra_vx_i64m8(...) __riscv_vsra_vx_i64m8(__VA_ARGS__) -#define vsll_vv_u8mf8(...) __riscv_vsll_vv_u8mf8(__VA_ARGS__) -#define vsll_vx_u8mf8(...) __riscv_vsll_vx_u8mf8(__VA_ARGS__) -#define vsll_vv_u8mf4(...) __riscv_vsll_vv_u8mf4(__VA_ARGS__) -#define vsll_vx_u8mf4(...) __riscv_vsll_vx_u8mf4(__VA_ARGS__) -#define vsll_vv_u8mf2(...) __riscv_vsll_vv_u8mf2(__VA_ARGS__) -#define vsll_vx_u8mf2(...) __riscv_vsll_vx_u8mf2(__VA_ARGS__) -#define vsll_vv_u8m1(...) __riscv_vsll_vv_u8m1(__VA_ARGS__) -#define vsll_vx_u8m1(...) __riscv_vsll_vx_u8m1(__VA_ARGS__) -#define vsll_vv_u8m2(...) __riscv_vsll_vv_u8m2(__VA_ARGS__) -#define vsll_vx_u8m2(...) __riscv_vsll_vx_u8m2(__VA_ARGS__) -#define vsll_vv_u8m4(...) __riscv_vsll_vv_u8m4(__VA_ARGS__) -#define vsll_vx_u8m4(...) __riscv_vsll_vx_u8m4(__VA_ARGS__) -#define vsll_vv_u8m8(...) __riscv_vsll_vv_u8m8(__VA_ARGS__) -#define vsll_vx_u8m8(...) __riscv_vsll_vx_u8m8(__VA_ARGS__) -#define vsll_vv_u16mf4(...) __riscv_vsll_vv_u16mf4(__VA_ARGS__) -#define vsll_vx_u16mf4(...) __riscv_vsll_vx_u16mf4(__VA_ARGS__) -#define vsll_vv_u16mf2(...) __riscv_vsll_vv_u16mf2(__VA_ARGS__) -#define vsll_vx_u16mf2(...) __riscv_vsll_vx_u16mf2(__VA_ARGS__) -#define vsll_vv_u16m1(...) __riscv_vsll_vv_u16m1(__VA_ARGS__) -#define vsll_vx_u16m1(...) __riscv_vsll_vx_u16m1(__VA_ARGS__) -#define vsll_vv_u16m2(...) __riscv_vsll_vv_u16m2(__VA_ARGS__) -#define vsll_vx_u16m2(...) __riscv_vsll_vx_u16m2(__VA_ARGS__) -#define vsll_vv_u16m4(...) __riscv_vsll_vv_u16m4(__VA_ARGS__) -#define vsll_vx_u16m4(...) __riscv_vsll_vx_u16m4(__VA_ARGS__) -#define vsll_vv_u16m8(...) __riscv_vsll_vv_u16m8(__VA_ARGS__) -#define vsll_vx_u16m8(...) __riscv_vsll_vx_u16m8(__VA_ARGS__) -#define vsll_vv_u32mf2(...) __riscv_vsll_vv_u32mf2(__VA_ARGS__) -#define vsll_vx_u32mf2(...) __riscv_vsll_vx_u32mf2(__VA_ARGS__) -#define vsll_vv_u32m1(...) __riscv_vsll_vv_u32m1(__VA_ARGS__) -#define vsll_vx_u32m1(...) __riscv_vsll_vx_u32m1(__VA_ARGS__) -#define vsll_vv_u32m2(...) __riscv_vsll_vv_u32m2(__VA_ARGS__) -#define vsll_vx_u32m2(...) __riscv_vsll_vx_u32m2(__VA_ARGS__) -#define vsll_vv_u32m4(...) __riscv_vsll_vv_u32m4(__VA_ARGS__) -#define vsll_vx_u32m4(...) __riscv_vsll_vx_u32m4(__VA_ARGS__) -#define vsll_vv_u32m8(...) __riscv_vsll_vv_u32m8(__VA_ARGS__) -#define vsll_vx_u32m8(...) __riscv_vsll_vx_u32m8(__VA_ARGS__) -#define vsll_vv_u64m1(...) __riscv_vsll_vv_u64m1(__VA_ARGS__) -#define vsll_vx_u64m1(...) __riscv_vsll_vx_u64m1(__VA_ARGS__) -#define vsll_vv_u64m2(...) __riscv_vsll_vv_u64m2(__VA_ARGS__) -#define vsll_vx_u64m2(...) __riscv_vsll_vx_u64m2(__VA_ARGS__) -#define vsll_vv_u64m4(...) __riscv_vsll_vv_u64m4(__VA_ARGS__) -#define vsll_vx_u64m4(...) __riscv_vsll_vx_u64m4(__VA_ARGS__) -#define vsll_vv_u64m8(...) __riscv_vsll_vv_u64m8(__VA_ARGS__) -#define vsll_vx_u64m8(...) __riscv_vsll_vx_u64m8(__VA_ARGS__) -#define vsrl_vv_u8mf8(...) __riscv_vsrl_vv_u8mf8(__VA_ARGS__) -#define vsrl_vx_u8mf8(...) __riscv_vsrl_vx_u8mf8(__VA_ARGS__) -#define vsrl_vv_u8mf4(...) __riscv_vsrl_vv_u8mf4(__VA_ARGS__) -#define vsrl_vx_u8mf4(...) __riscv_vsrl_vx_u8mf4(__VA_ARGS__) -#define vsrl_vv_u8mf2(...) __riscv_vsrl_vv_u8mf2(__VA_ARGS__) -#define vsrl_vx_u8mf2(...) __riscv_vsrl_vx_u8mf2(__VA_ARGS__) -#define vsrl_vv_u8m1(...) __riscv_vsrl_vv_u8m1(__VA_ARGS__) -#define vsrl_vx_u8m1(...) __riscv_vsrl_vx_u8m1(__VA_ARGS__) -#define vsrl_vv_u8m2(...) __riscv_vsrl_vv_u8m2(__VA_ARGS__) -#define vsrl_vx_u8m2(...) __riscv_vsrl_vx_u8m2(__VA_ARGS__) -#define vsrl_vv_u8m4(...) __riscv_vsrl_vv_u8m4(__VA_ARGS__) -#define vsrl_vx_u8m4(...) __riscv_vsrl_vx_u8m4(__VA_ARGS__) -#define vsrl_vv_u8m8(...) __riscv_vsrl_vv_u8m8(__VA_ARGS__) -#define vsrl_vx_u8m8(...) __riscv_vsrl_vx_u8m8(__VA_ARGS__) -#define vsrl_vv_u16mf4(...) __riscv_vsrl_vv_u16mf4(__VA_ARGS__) -#define vsrl_vx_u16mf4(...) __riscv_vsrl_vx_u16mf4(__VA_ARGS__) -#define vsrl_vv_u16mf2(...) __riscv_vsrl_vv_u16mf2(__VA_ARGS__) -#define vsrl_vx_u16mf2(...) __riscv_vsrl_vx_u16mf2(__VA_ARGS__) -#define vsrl_vv_u16m1(...) __riscv_vsrl_vv_u16m1(__VA_ARGS__) -#define vsrl_vx_u16m1(...) __riscv_vsrl_vx_u16m1(__VA_ARGS__) -#define vsrl_vv_u16m2(...) __riscv_vsrl_vv_u16m2(__VA_ARGS__) -#define vsrl_vx_u16m2(...) __riscv_vsrl_vx_u16m2(__VA_ARGS__) -#define vsrl_vv_u16m4(...) __riscv_vsrl_vv_u16m4(__VA_ARGS__) -#define vsrl_vx_u16m4(...) __riscv_vsrl_vx_u16m4(__VA_ARGS__) -#define vsrl_vv_u16m8(...) __riscv_vsrl_vv_u16m8(__VA_ARGS__) -#define vsrl_vx_u16m8(...) __riscv_vsrl_vx_u16m8(__VA_ARGS__) -#define vsrl_vv_u32mf2(...) __riscv_vsrl_vv_u32mf2(__VA_ARGS__) -#define vsrl_vx_u32mf2(...) __riscv_vsrl_vx_u32mf2(__VA_ARGS__) -#define vsrl_vv_u32m1(...) __riscv_vsrl_vv_u32m1(__VA_ARGS__) -#define vsrl_vx_u32m1(...) __riscv_vsrl_vx_u32m1(__VA_ARGS__) -#define vsrl_vv_u32m2(...) __riscv_vsrl_vv_u32m2(__VA_ARGS__) -#define vsrl_vx_u32m2(...) __riscv_vsrl_vx_u32m2(__VA_ARGS__) -#define vsrl_vv_u32m4(...) __riscv_vsrl_vv_u32m4(__VA_ARGS__) -#define vsrl_vx_u32m4(...) __riscv_vsrl_vx_u32m4(__VA_ARGS__) -#define vsrl_vv_u32m8(...) __riscv_vsrl_vv_u32m8(__VA_ARGS__) -#define vsrl_vx_u32m8(...) __riscv_vsrl_vx_u32m8(__VA_ARGS__) -#define vsrl_vv_u64m1(...) __riscv_vsrl_vv_u64m1(__VA_ARGS__) -#define vsrl_vx_u64m1(...) __riscv_vsrl_vx_u64m1(__VA_ARGS__) -#define vsrl_vv_u64m2(...) __riscv_vsrl_vv_u64m2(__VA_ARGS__) -#define vsrl_vx_u64m2(...) __riscv_vsrl_vx_u64m2(__VA_ARGS__) -#define vsrl_vv_u64m4(...) __riscv_vsrl_vv_u64m4(__VA_ARGS__) -#define vsrl_vx_u64m4(...) __riscv_vsrl_vx_u64m4(__VA_ARGS__) -#define vsrl_vv_u64m8(...) __riscv_vsrl_vv_u64m8(__VA_ARGS__) -#define vsrl_vx_u64m8(...) __riscv_vsrl_vx_u64m8(__VA_ARGS__) -// masked functions -#define vsll_vv_i8mf8_m(...) __riscv_vsll_vv_i8mf8_tumu(__VA_ARGS__) -#define vsll_vx_i8mf8_m(...) __riscv_vsll_vx_i8mf8_tumu(__VA_ARGS__) -#define vsll_vv_i8mf4_m(...) __riscv_vsll_vv_i8mf4_tumu(__VA_ARGS__) -#define vsll_vx_i8mf4_m(...) __riscv_vsll_vx_i8mf4_tumu(__VA_ARGS__) -#define vsll_vv_i8mf2_m(...) __riscv_vsll_vv_i8mf2_tumu(__VA_ARGS__) -#define vsll_vx_i8mf2_m(...) __riscv_vsll_vx_i8mf2_tumu(__VA_ARGS__) -#define vsll_vv_i8m1_m(...) __riscv_vsll_vv_i8m1_tumu(__VA_ARGS__) -#define vsll_vx_i8m1_m(...) __riscv_vsll_vx_i8m1_tumu(__VA_ARGS__) -#define vsll_vv_i8m2_m(...) __riscv_vsll_vv_i8m2_tumu(__VA_ARGS__) -#define vsll_vx_i8m2_m(...) __riscv_vsll_vx_i8m2_tumu(__VA_ARGS__) -#define vsll_vv_i8m4_m(...) __riscv_vsll_vv_i8m4_tumu(__VA_ARGS__) -#define vsll_vx_i8m4_m(...) __riscv_vsll_vx_i8m4_tumu(__VA_ARGS__) -#define vsll_vv_i8m8_m(...) __riscv_vsll_vv_i8m8_tumu(__VA_ARGS__) -#define vsll_vx_i8m8_m(...) __riscv_vsll_vx_i8m8_tumu(__VA_ARGS__) -#define vsll_vv_i16mf4_m(...) __riscv_vsll_vv_i16mf4_tumu(__VA_ARGS__) -#define vsll_vx_i16mf4_m(...) __riscv_vsll_vx_i16mf4_tumu(__VA_ARGS__) -#define vsll_vv_i16mf2_m(...) __riscv_vsll_vv_i16mf2_tumu(__VA_ARGS__) -#define vsll_vx_i16mf2_m(...) __riscv_vsll_vx_i16mf2_tumu(__VA_ARGS__) -#define vsll_vv_i16m1_m(...) __riscv_vsll_vv_i16m1_tumu(__VA_ARGS__) -#define vsll_vx_i16m1_m(...) __riscv_vsll_vx_i16m1_tumu(__VA_ARGS__) -#define vsll_vv_i16m2_m(...) __riscv_vsll_vv_i16m2_tumu(__VA_ARGS__) -#define vsll_vx_i16m2_m(...) __riscv_vsll_vx_i16m2_tumu(__VA_ARGS__) -#define vsll_vv_i16m4_m(...) __riscv_vsll_vv_i16m4_tumu(__VA_ARGS__) -#define vsll_vx_i16m4_m(...) __riscv_vsll_vx_i16m4_tumu(__VA_ARGS__) -#define vsll_vv_i16m8_m(...) __riscv_vsll_vv_i16m8_tumu(__VA_ARGS__) -#define vsll_vx_i16m8_m(...) __riscv_vsll_vx_i16m8_tumu(__VA_ARGS__) -#define vsll_vv_i32mf2_m(...) __riscv_vsll_vv_i32mf2_tumu(__VA_ARGS__) -#define vsll_vx_i32mf2_m(...) __riscv_vsll_vx_i32mf2_tumu(__VA_ARGS__) -#define vsll_vv_i32m1_m(...) __riscv_vsll_vv_i32m1_tumu(__VA_ARGS__) -#define vsll_vx_i32m1_m(...) __riscv_vsll_vx_i32m1_tumu(__VA_ARGS__) -#define vsll_vv_i32m2_m(...) __riscv_vsll_vv_i32m2_tumu(__VA_ARGS__) -#define vsll_vx_i32m2_m(...) __riscv_vsll_vx_i32m2_tumu(__VA_ARGS__) -#define vsll_vv_i32m4_m(...) __riscv_vsll_vv_i32m4_tumu(__VA_ARGS__) -#define vsll_vx_i32m4_m(...) __riscv_vsll_vx_i32m4_tumu(__VA_ARGS__) -#define vsll_vv_i32m8_m(...) __riscv_vsll_vv_i32m8_tumu(__VA_ARGS__) -#define vsll_vx_i32m8_m(...) __riscv_vsll_vx_i32m8_tumu(__VA_ARGS__) -#define vsll_vv_i64m1_m(...) __riscv_vsll_vv_i64m1_tumu(__VA_ARGS__) -#define vsll_vx_i64m1_m(...) __riscv_vsll_vx_i64m1_tumu(__VA_ARGS__) -#define vsll_vv_i64m2_m(...) __riscv_vsll_vv_i64m2_tumu(__VA_ARGS__) -#define vsll_vx_i64m2_m(...) __riscv_vsll_vx_i64m2_tumu(__VA_ARGS__) -#define vsll_vv_i64m4_m(...) __riscv_vsll_vv_i64m4_tumu(__VA_ARGS__) -#define vsll_vx_i64m4_m(...) __riscv_vsll_vx_i64m4_tumu(__VA_ARGS__) -#define vsll_vv_i64m8_m(...) __riscv_vsll_vv_i64m8_tumu(__VA_ARGS__) -#define vsll_vx_i64m8_m(...) __riscv_vsll_vx_i64m8_tumu(__VA_ARGS__) -#define vsra_vv_i8mf8_m(...) __riscv_vsra_vv_i8mf8_tumu(__VA_ARGS__) -#define vsra_vx_i8mf8_m(...) __riscv_vsra_vx_i8mf8_tumu(__VA_ARGS__) -#define vsra_vv_i8mf4_m(...) __riscv_vsra_vv_i8mf4_tumu(__VA_ARGS__) -#define vsra_vx_i8mf4_m(...) __riscv_vsra_vx_i8mf4_tumu(__VA_ARGS__) -#define vsra_vv_i8mf2_m(...) __riscv_vsra_vv_i8mf2_tumu(__VA_ARGS__) -#define vsra_vx_i8mf2_m(...) __riscv_vsra_vx_i8mf2_tumu(__VA_ARGS__) -#define vsra_vv_i8m1_m(...) __riscv_vsra_vv_i8m1_tumu(__VA_ARGS__) -#define vsra_vx_i8m1_m(...) __riscv_vsra_vx_i8m1_tumu(__VA_ARGS__) -#define vsra_vv_i8m2_m(...) __riscv_vsra_vv_i8m2_tumu(__VA_ARGS__) -#define vsra_vx_i8m2_m(...) __riscv_vsra_vx_i8m2_tumu(__VA_ARGS__) -#define vsra_vv_i8m4_m(...) __riscv_vsra_vv_i8m4_tumu(__VA_ARGS__) -#define vsra_vx_i8m4_m(...) __riscv_vsra_vx_i8m4_tumu(__VA_ARGS__) -#define vsra_vv_i8m8_m(...) __riscv_vsra_vv_i8m8_tumu(__VA_ARGS__) -#define vsra_vx_i8m8_m(...) __riscv_vsra_vx_i8m8_tumu(__VA_ARGS__) -#define vsra_vv_i16mf4_m(...) __riscv_vsra_vv_i16mf4_tumu(__VA_ARGS__) -#define vsra_vx_i16mf4_m(...) __riscv_vsra_vx_i16mf4_tumu(__VA_ARGS__) -#define vsra_vv_i16mf2_m(...) __riscv_vsra_vv_i16mf2_tumu(__VA_ARGS__) -#define vsra_vx_i16mf2_m(...) __riscv_vsra_vx_i16mf2_tumu(__VA_ARGS__) -#define vsra_vv_i16m1_m(...) __riscv_vsra_vv_i16m1_tumu(__VA_ARGS__) -#define vsra_vx_i16m1_m(...) __riscv_vsra_vx_i16m1_tumu(__VA_ARGS__) -#define vsra_vv_i16m2_m(...) __riscv_vsra_vv_i16m2_tumu(__VA_ARGS__) -#define vsra_vx_i16m2_m(...) __riscv_vsra_vx_i16m2_tumu(__VA_ARGS__) -#define vsra_vv_i16m4_m(...) __riscv_vsra_vv_i16m4_tumu(__VA_ARGS__) -#define vsra_vx_i16m4_m(...) __riscv_vsra_vx_i16m4_tumu(__VA_ARGS__) -#define vsra_vv_i16m8_m(...) __riscv_vsra_vv_i16m8_tumu(__VA_ARGS__) -#define vsra_vx_i16m8_m(...) __riscv_vsra_vx_i16m8_tumu(__VA_ARGS__) -#define vsra_vv_i32mf2_m(...) __riscv_vsra_vv_i32mf2_tumu(__VA_ARGS__) -#define vsra_vx_i32mf2_m(...) __riscv_vsra_vx_i32mf2_tumu(__VA_ARGS__) -#define vsra_vv_i32m1_m(...) __riscv_vsra_vv_i32m1_tumu(__VA_ARGS__) -#define vsra_vx_i32m1_m(...) __riscv_vsra_vx_i32m1_tumu(__VA_ARGS__) -#define vsra_vv_i32m2_m(...) __riscv_vsra_vv_i32m2_tumu(__VA_ARGS__) -#define vsra_vx_i32m2_m(...) __riscv_vsra_vx_i32m2_tumu(__VA_ARGS__) -#define vsra_vv_i32m4_m(...) __riscv_vsra_vv_i32m4_tumu(__VA_ARGS__) -#define vsra_vx_i32m4_m(...) __riscv_vsra_vx_i32m4_tumu(__VA_ARGS__) -#define vsra_vv_i32m8_m(...) __riscv_vsra_vv_i32m8_tumu(__VA_ARGS__) -#define vsra_vx_i32m8_m(...) __riscv_vsra_vx_i32m8_tumu(__VA_ARGS__) -#define vsra_vv_i64m1_m(...) __riscv_vsra_vv_i64m1_tumu(__VA_ARGS__) -#define vsra_vx_i64m1_m(...) __riscv_vsra_vx_i64m1_tumu(__VA_ARGS__) -#define vsra_vv_i64m2_m(...) __riscv_vsra_vv_i64m2_tumu(__VA_ARGS__) -#define vsra_vx_i64m2_m(...) __riscv_vsra_vx_i64m2_tumu(__VA_ARGS__) -#define vsra_vv_i64m4_m(...) __riscv_vsra_vv_i64m4_tumu(__VA_ARGS__) -#define vsra_vx_i64m4_m(...) __riscv_vsra_vx_i64m4_tumu(__VA_ARGS__) -#define vsra_vv_i64m8_m(...) __riscv_vsra_vv_i64m8_tumu(__VA_ARGS__) -#define vsra_vx_i64m8_m(...) __riscv_vsra_vx_i64m8_tumu(__VA_ARGS__) -#define vsll_vv_u8mf8_m(...) __riscv_vsll_vv_u8mf8_tumu(__VA_ARGS__) -#define vsll_vx_u8mf8_m(...) __riscv_vsll_vx_u8mf8_tumu(__VA_ARGS__) -#define vsll_vv_u8mf4_m(...) __riscv_vsll_vv_u8mf4_tumu(__VA_ARGS__) -#define vsll_vx_u8mf4_m(...) __riscv_vsll_vx_u8mf4_tumu(__VA_ARGS__) -#define vsll_vv_u8mf2_m(...) __riscv_vsll_vv_u8mf2_tumu(__VA_ARGS__) -#define vsll_vx_u8mf2_m(...) __riscv_vsll_vx_u8mf2_tumu(__VA_ARGS__) -#define vsll_vv_u8m1_m(...) __riscv_vsll_vv_u8m1_tumu(__VA_ARGS__) -#define vsll_vx_u8m1_m(...) __riscv_vsll_vx_u8m1_tumu(__VA_ARGS__) -#define vsll_vv_u8m2_m(...) __riscv_vsll_vv_u8m2_tumu(__VA_ARGS__) -#define vsll_vx_u8m2_m(...) __riscv_vsll_vx_u8m2_tumu(__VA_ARGS__) -#define vsll_vv_u8m4_m(...) __riscv_vsll_vv_u8m4_tumu(__VA_ARGS__) -#define vsll_vx_u8m4_m(...) __riscv_vsll_vx_u8m4_tumu(__VA_ARGS__) -#define vsll_vv_u8m8_m(...) __riscv_vsll_vv_u8m8_tumu(__VA_ARGS__) -#define vsll_vx_u8m8_m(...) __riscv_vsll_vx_u8m8_tumu(__VA_ARGS__) -#define vsll_vv_u16mf4_m(...) __riscv_vsll_vv_u16mf4_tumu(__VA_ARGS__) -#define vsll_vx_u16mf4_m(...) __riscv_vsll_vx_u16mf4_tumu(__VA_ARGS__) -#define vsll_vv_u16mf2_m(...) __riscv_vsll_vv_u16mf2_tumu(__VA_ARGS__) -#define vsll_vx_u16mf2_m(...) __riscv_vsll_vx_u16mf2_tumu(__VA_ARGS__) -#define vsll_vv_u16m1_m(...) __riscv_vsll_vv_u16m1_tumu(__VA_ARGS__) -#define vsll_vx_u16m1_m(...) __riscv_vsll_vx_u16m1_tumu(__VA_ARGS__) -#define vsll_vv_u16m2_m(...) __riscv_vsll_vv_u16m2_tumu(__VA_ARGS__) -#define vsll_vx_u16m2_m(...) __riscv_vsll_vx_u16m2_tumu(__VA_ARGS__) -#define vsll_vv_u16m4_m(...) __riscv_vsll_vv_u16m4_tumu(__VA_ARGS__) -#define vsll_vx_u16m4_m(...) __riscv_vsll_vx_u16m4_tumu(__VA_ARGS__) -#define vsll_vv_u16m8_m(...) __riscv_vsll_vv_u16m8_tumu(__VA_ARGS__) -#define vsll_vx_u16m8_m(...) __riscv_vsll_vx_u16m8_tumu(__VA_ARGS__) -#define vsll_vv_u32mf2_m(...) __riscv_vsll_vv_u32mf2_tumu(__VA_ARGS__) -#define vsll_vx_u32mf2_m(...) __riscv_vsll_vx_u32mf2_tumu(__VA_ARGS__) -#define vsll_vv_u32m1_m(...) __riscv_vsll_vv_u32m1_tumu(__VA_ARGS__) -#define vsll_vx_u32m1_m(...) __riscv_vsll_vx_u32m1_tumu(__VA_ARGS__) -#define vsll_vv_u32m2_m(...) __riscv_vsll_vv_u32m2_tumu(__VA_ARGS__) -#define vsll_vx_u32m2_m(...) __riscv_vsll_vx_u32m2_tumu(__VA_ARGS__) -#define vsll_vv_u32m4_m(...) __riscv_vsll_vv_u32m4_tumu(__VA_ARGS__) -#define vsll_vx_u32m4_m(...) __riscv_vsll_vx_u32m4_tumu(__VA_ARGS__) -#define vsll_vv_u32m8_m(...) __riscv_vsll_vv_u32m8_tumu(__VA_ARGS__) -#define vsll_vx_u32m8_m(...) __riscv_vsll_vx_u32m8_tumu(__VA_ARGS__) -#define vsll_vv_u64m1_m(...) __riscv_vsll_vv_u64m1_tumu(__VA_ARGS__) -#define vsll_vx_u64m1_m(...) __riscv_vsll_vx_u64m1_tumu(__VA_ARGS__) -#define vsll_vv_u64m2_m(...) __riscv_vsll_vv_u64m2_tumu(__VA_ARGS__) -#define vsll_vx_u64m2_m(...) __riscv_vsll_vx_u64m2_tumu(__VA_ARGS__) -#define vsll_vv_u64m4_m(...) __riscv_vsll_vv_u64m4_tumu(__VA_ARGS__) -#define vsll_vx_u64m4_m(...) __riscv_vsll_vx_u64m4_tumu(__VA_ARGS__) -#define vsll_vv_u64m8_m(...) __riscv_vsll_vv_u64m8_tumu(__VA_ARGS__) -#define vsll_vx_u64m8_m(...) __riscv_vsll_vx_u64m8_tumu(__VA_ARGS__) -#define vsrl_vv_u8mf8_m(...) __riscv_vsrl_vv_u8mf8_tumu(__VA_ARGS__) -#define vsrl_vx_u8mf8_m(...) __riscv_vsrl_vx_u8mf8_tumu(__VA_ARGS__) -#define vsrl_vv_u8mf4_m(...) __riscv_vsrl_vv_u8mf4_tumu(__VA_ARGS__) -#define vsrl_vx_u8mf4_m(...) __riscv_vsrl_vx_u8mf4_tumu(__VA_ARGS__) -#define vsrl_vv_u8mf2_m(...) __riscv_vsrl_vv_u8mf2_tumu(__VA_ARGS__) -#define vsrl_vx_u8mf2_m(...) __riscv_vsrl_vx_u8mf2_tumu(__VA_ARGS__) -#define vsrl_vv_u8m1_m(...) __riscv_vsrl_vv_u8m1_tumu(__VA_ARGS__) -#define vsrl_vx_u8m1_m(...) __riscv_vsrl_vx_u8m1_tumu(__VA_ARGS__) -#define vsrl_vv_u8m2_m(...) __riscv_vsrl_vv_u8m2_tumu(__VA_ARGS__) -#define vsrl_vx_u8m2_m(...) __riscv_vsrl_vx_u8m2_tumu(__VA_ARGS__) -#define vsrl_vv_u8m4_m(...) __riscv_vsrl_vv_u8m4_tumu(__VA_ARGS__) -#define vsrl_vx_u8m4_m(...) __riscv_vsrl_vx_u8m4_tumu(__VA_ARGS__) -#define vsrl_vv_u8m8_m(...) __riscv_vsrl_vv_u8m8_tumu(__VA_ARGS__) -#define vsrl_vx_u8m8_m(...) __riscv_vsrl_vx_u8m8_tumu(__VA_ARGS__) -#define vsrl_vv_u16mf4_m(...) __riscv_vsrl_vv_u16mf4_tumu(__VA_ARGS__) -#define vsrl_vx_u16mf4_m(...) __riscv_vsrl_vx_u16mf4_tumu(__VA_ARGS__) -#define vsrl_vv_u16mf2_m(...) __riscv_vsrl_vv_u16mf2_tumu(__VA_ARGS__) -#define vsrl_vx_u16mf2_m(...) __riscv_vsrl_vx_u16mf2_tumu(__VA_ARGS__) -#define vsrl_vv_u16m1_m(...) __riscv_vsrl_vv_u16m1_tumu(__VA_ARGS__) -#define vsrl_vx_u16m1_m(...) __riscv_vsrl_vx_u16m1_tumu(__VA_ARGS__) -#define vsrl_vv_u16m2_m(...) __riscv_vsrl_vv_u16m2_tumu(__VA_ARGS__) -#define vsrl_vx_u16m2_m(...) __riscv_vsrl_vx_u16m2_tumu(__VA_ARGS__) -#define vsrl_vv_u16m4_m(...) __riscv_vsrl_vv_u16m4_tumu(__VA_ARGS__) -#define vsrl_vx_u16m4_m(...) __riscv_vsrl_vx_u16m4_tumu(__VA_ARGS__) -#define vsrl_vv_u16m8_m(...) __riscv_vsrl_vv_u16m8_tumu(__VA_ARGS__) -#define vsrl_vx_u16m8_m(...) __riscv_vsrl_vx_u16m8_tumu(__VA_ARGS__) -#define vsrl_vv_u32mf2_m(...) __riscv_vsrl_vv_u32mf2_tumu(__VA_ARGS__) -#define vsrl_vx_u32mf2_m(...) __riscv_vsrl_vx_u32mf2_tumu(__VA_ARGS__) -#define vsrl_vv_u32m1_m(...) __riscv_vsrl_vv_u32m1_tumu(__VA_ARGS__) -#define vsrl_vx_u32m1_m(...) __riscv_vsrl_vx_u32m1_tumu(__VA_ARGS__) -#define vsrl_vv_u32m2_m(...) __riscv_vsrl_vv_u32m2_tumu(__VA_ARGS__) -#define vsrl_vx_u32m2_m(...) __riscv_vsrl_vx_u32m2_tumu(__VA_ARGS__) -#define vsrl_vv_u32m4_m(...) __riscv_vsrl_vv_u32m4_tumu(__VA_ARGS__) -#define vsrl_vx_u32m4_m(...) __riscv_vsrl_vx_u32m4_tumu(__VA_ARGS__) -#define vsrl_vv_u32m8_m(...) __riscv_vsrl_vv_u32m8_tumu(__VA_ARGS__) -#define vsrl_vx_u32m8_m(...) __riscv_vsrl_vx_u32m8_tumu(__VA_ARGS__) -#define vsrl_vv_u64m1_m(...) __riscv_vsrl_vv_u64m1_tumu(__VA_ARGS__) -#define vsrl_vx_u64m1_m(...) __riscv_vsrl_vx_u64m1_tumu(__VA_ARGS__) -#define vsrl_vv_u64m2_m(...) __riscv_vsrl_vv_u64m2_tumu(__VA_ARGS__) -#define vsrl_vx_u64m2_m(...) __riscv_vsrl_vx_u64m2_tumu(__VA_ARGS__) -#define vsrl_vv_u64m4_m(...) __riscv_vsrl_vv_u64m4_tumu(__VA_ARGS__) -#define vsrl_vx_u64m4_m(...) __riscv_vsrl_vx_u64m4_tumu(__VA_ARGS__) -#define vsrl_vv_u64m8_m(...) __riscv_vsrl_vv_u64m8_tumu(__VA_ARGS__) -#define vsrl_vx_u64m8_m(...) __riscv_vsrl_vx_u64m8_tumu(__VA_ARGS__) -#define vnsra_wv_i8mf8(...) __riscv_vnsra_wv_i8mf8(__VA_ARGS__) -#define vnsra_wx_i8mf8(...) __riscv_vnsra_wx_i8mf8(__VA_ARGS__) -#define vnsra_wv_i8mf4(...) __riscv_vnsra_wv_i8mf4(__VA_ARGS__) -#define vnsra_wx_i8mf4(...) __riscv_vnsra_wx_i8mf4(__VA_ARGS__) -#define vnsra_wv_i8mf2(...) __riscv_vnsra_wv_i8mf2(__VA_ARGS__) -#define vnsra_wx_i8mf2(...) __riscv_vnsra_wx_i8mf2(__VA_ARGS__) -#define vnsra_wv_i8m1(...) __riscv_vnsra_wv_i8m1(__VA_ARGS__) -#define vnsra_wx_i8m1(...) __riscv_vnsra_wx_i8m1(__VA_ARGS__) -#define vnsra_wv_i8m2(...) __riscv_vnsra_wv_i8m2(__VA_ARGS__) -#define vnsra_wx_i8m2(...) __riscv_vnsra_wx_i8m2(__VA_ARGS__) -#define vnsra_wv_i8m4(...) __riscv_vnsra_wv_i8m4(__VA_ARGS__) -#define vnsra_wx_i8m4(...) __riscv_vnsra_wx_i8m4(__VA_ARGS__) -#define vnsra_wv_i16mf4(...) __riscv_vnsra_wv_i16mf4(__VA_ARGS__) -#define vnsra_wx_i16mf4(...) __riscv_vnsra_wx_i16mf4(__VA_ARGS__) -#define vnsra_wv_i16mf2(...) __riscv_vnsra_wv_i16mf2(__VA_ARGS__) -#define vnsra_wx_i16mf2(...) __riscv_vnsra_wx_i16mf2(__VA_ARGS__) -#define vnsra_wv_i16m1(...) __riscv_vnsra_wv_i16m1(__VA_ARGS__) -#define vnsra_wx_i16m1(...) __riscv_vnsra_wx_i16m1(__VA_ARGS__) -#define vnsra_wv_i16m2(...) __riscv_vnsra_wv_i16m2(__VA_ARGS__) -#define vnsra_wx_i16m2(...) __riscv_vnsra_wx_i16m2(__VA_ARGS__) -#define vnsra_wv_i16m4(...) __riscv_vnsra_wv_i16m4(__VA_ARGS__) -#define vnsra_wx_i16m4(...) __riscv_vnsra_wx_i16m4(__VA_ARGS__) -#define vnsra_wv_i32mf2(...) __riscv_vnsra_wv_i32mf2(__VA_ARGS__) -#define vnsra_wx_i32mf2(...) __riscv_vnsra_wx_i32mf2(__VA_ARGS__) -#define vnsra_wv_i32m1(...) __riscv_vnsra_wv_i32m1(__VA_ARGS__) -#define vnsra_wx_i32m1(...) __riscv_vnsra_wx_i32m1(__VA_ARGS__) -#define vnsra_wv_i32m2(...) __riscv_vnsra_wv_i32m2(__VA_ARGS__) -#define vnsra_wx_i32m2(...) __riscv_vnsra_wx_i32m2(__VA_ARGS__) -#define vnsra_wv_i32m4(...) __riscv_vnsra_wv_i32m4(__VA_ARGS__) -#define vnsra_wx_i32m4(...) __riscv_vnsra_wx_i32m4(__VA_ARGS__) -#define vnsrl_wv_u8mf8(...) __riscv_vnsrl_wv_u8mf8(__VA_ARGS__) -#define vnsrl_wx_u8mf8(...) __riscv_vnsrl_wx_u8mf8(__VA_ARGS__) -#define vnsrl_wv_u8mf4(...) __riscv_vnsrl_wv_u8mf4(__VA_ARGS__) -#define vnsrl_wx_u8mf4(...) __riscv_vnsrl_wx_u8mf4(__VA_ARGS__) -#define vnsrl_wv_u8mf2(...) __riscv_vnsrl_wv_u8mf2(__VA_ARGS__) -#define vnsrl_wx_u8mf2(...) __riscv_vnsrl_wx_u8mf2(__VA_ARGS__) -#define vnsrl_wv_u8m1(...) __riscv_vnsrl_wv_u8m1(__VA_ARGS__) -#define vnsrl_wx_u8m1(...) __riscv_vnsrl_wx_u8m1(__VA_ARGS__) -#define vnsrl_wv_u8m2(...) __riscv_vnsrl_wv_u8m2(__VA_ARGS__) -#define vnsrl_wx_u8m2(...) __riscv_vnsrl_wx_u8m2(__VA_ARGS__) -#define vnsrl_wv_u8m4(...) __riscv_vnsrl_wv_u8m4(__VA_ARGS__) -#define vnsrl_wx_u8m4(...) __riscv_vnsrl_wx_u8m4(__VA_ARGS__) -#define vnsrl_wv_u16mf4(...) __riscv_vnsrl_wv_u16mf4(__VA_ARGS__) -#define vnsrl_wx_u16mf4(...) __riscv_vnsrl_wx_u16mf4(__VA_ARGS__) -#define vnsrl_wv_u16mf2(...) __riscv_vnsrl_wv_u16mf2(__VA_ARGS__) -#define vnsrl_wx_u16mf2(...) __riscv_vnsrl_wx_u16mf2(__VA_ARGS__) -#define vnsrl_wv_u16m1(...) __riscv_vnsrl_wv_u16m1(__VA_ARGS__) -#define vnsrl_wx_u16m1(...) __riscv_vnsrl_wx_u16m1(__VA_ARGS__) -#define vnsrl_wv_u16m2(...) __riscv_vnsrl_wv_u16m2(__VA_ARGS__) -#define vnsrl_wx_u16m2(...) __riscv_vnsrl_wx_u16m2(__VA_ARGS__) -#define vnsrl_wv_u16m4(...) __riscv_vnsrl_wv_u16m4(__VA_ARGS__) -#define vnsrl_wx_u16m4(...) __riscv_vnsrl_wx_u16m4(__VA_ARGS__) -#define vnsrl_wv_u32mf2(...) __riscv_vnsrl_wv_u32mf2(__VA_ARGS__) -#define vnsrl_wx_u32mf2(...) __riscv_vnsrl_wx_u32mf2(__VA_ARGS__) -#define vnsrl_wv_u32m1(...) __riscv_vnsrl_wv_u32m1(__VA_ARGS__) -#define vnsrl_wx_u32m1(...) __riscv_vnsrl_wx_u32m1(__VA_ARGS__) -#define vnsrl_wv_u32m2(...) __riscv_vnsrl_wv_u32m2(__VA_ARGS__) -#define vnsrl_wx_u32m2(...) __riscv_vnsrl_wx_u32m2(__VA_ARGS__) -#define vnsrl_wv_u32m4(...) __riscv_vnsrl_wv_u32m4(__VA_ARGS__) -#define vnsrl_wx_u32m4(...) __riscv_vnsrl_wx_u32m4(__VA_ARGS__) -// masked functions -#define vnsra_wv_i8mf8_m(...) __riscv_vnsra_wv_i8mf8_tumu(__VA_ARGS__) -#define vnsra_wx_i8mf8_m(...) __riscv_vnsra_wx_i8mf8_tumu(__VA_ARGS__) -#define vnsra_wv_i8mf4_m(...) __riscv_vnsra_wv_i8mf4_tumu(__VA_ARGS__) -#define vnsra_wx_i8mf4_m(...) __riscv_vnsra_wx_i8mf4_tumu(__VA_ARGS__) -#define vnsra_wv_i8mf2_m(...) __riscv_vnsra_wv_i8mf2_tumu(__VA_ARGS__) -#define vnsra_wx_i8mf2_m(...) __riscv_vnsra_wx_i8mf2_tumu(__VA_ARGS__) -#define vnsra_wv_i8m1_m(...) __riscv_vnsra_wv_i8m1_tumu(__VA_ARGS__) -#define vnsra_wx_i8m1_m(...) __riscv_vnsra_wx_i8m1_tumu(__VA_ARGS__) -#define vnsra_wv_i8m2_m(...) __riscv_vnsra_wv_i8m2_tumu(__VA_ARGS__) -#define vnsra_wx_i8m2_m(...) __riscv_vnsra_wx_i8m2_tumu(__VA_ARGS__) -#define vnsra_wv_i8m4_m(...) __riscv_vnsra_wv_i8m4_tumu(__VA_ARGS__) -#define vnsra_wx_i8m4_m(...) __riscv_vnsra_wx_i8m4_tumu(__VA_ARGS__) -#define vnsra_wv_i16mf4_m(...) __riscv_vnsra_wv_i16mf4_tumu(__VA_ARGS__) -#define vnsra_wx_i16mf4_m(...) __riscv_vnsra_wx_i16mf4_tumu(__VA_ARGS__) -#define vnsra_wv_i16mf2_m(...) __riscv_vnsra_wv_i16mf2_tumu(__VA_ARGS__) -#define vnsra_wx_i16mf2_m(...) __riscv_vnsra_wx_i16mf2_tumu(__VA_ARGS__) -#define vnsra_wv_i16m1_m(...) __riscv_vnsra_wv_i16m1_tumu(__VA_ARGS__) -#define vnsra_wx_i16m1_m(...) __riscv_vnsra_wx_i16m1_tumu(__VA_ARGS__) -#define vnsra_wv_i16m2_m(...) __riscv_vnsra_wv_i16m2_tumu(__VA_ARGS__) -#define vnsra_wx_i16m2_m(...) __riscv_vnsra_wx_i16m2_tumu(__VA_ARGS__) -#define vnsra_wv_i16m4_m(...) __riscv_vnsra_wv_i16m4_tumu(__VA_ARGS__) -#define vnsra_wx_i16m4_m(...) __riscv_vnsra_wx_i16m4_tumu(__VA_ARGS__) -#define vnsra_wv_i32mf2_m(...) __riscv_vnsra_wv_i32mf2_tumu(__VA_ARGS__) -#define vnsra_wx_i32mf2_m(...) __riscv_vnsra_wx_i32mf2_tumu(__VA_ARGS__) -#define vnsra_wv_i32m1_m(...) __riscv_vnsra_wv_i32m1_tumu(__VA_ARGS__) -#define vnsra_wx_i32m1_m(...) __riscv_vnsra_wx_i32m1_tumu(__VA_ARGS__) -#define vnsra_wv_i32m2_m(...) __riscv_vnsra_wv_i32m2_tumu(__VA_ARGS__) -#define vnsra_wx_i32m2_m(...) __riscv_vnsra_wx_i32m2_tumu(__VA_ARGS__) -#define vnsra_wv_i32m4_m(...) __riscv_vnsra_wv_i32m4_tumu(__VA_ARGS__) -#define vnsra_wx_i32m4_m(...) __riscv_vnsra_wx_i32m4_tumu(__VA_ARGS__) -#define vnsrl_wv_u8mf8_m(...) __riscv_vnsrl_wv_u8mf8_tumu(__VA_ARGS__) -#define vnsrl_wx_u8mf8_m(...) __riscv_vnsrl_wx_u8mf8_tumu(__VA_ARGS__) -#define vnsrl_wv_u8mf4_m(...) __riscv_vnsrl_wv_u8mf4_tumu(__VA_ARGS__) -#define vnsrl_wx_u8mf4_m(...) __riscv_vnsrl_wx_u8mf4_tumu(__VA_ARGS__) -#define vnsrl_wv_u8mf2_m(...) __riscv_vnsrl_wv_u8mf2_tumu(__VA_ARGS__) -#define vnsrl_wx_u8mf2_m(...) __riscv_vnsrl_wx_u8mf2_tumu(__VA_ARGS__) -#define vnsrl_wv_u8m1_m(...) __riscv_vnsrl_wv_u8m1_tumu(__VA_ARGS__) -#define vnsrl_wx_u8m1_m(...) __riscv_vnsrl_wx_u8m1_tumu(__VA_ARGS__) -#define vnsrl_wv_u8m2_m(...) __riscv_vnsrl_wv_u8m2_tumu(__VA_ARGS__) -#define vnsrl_wx_u8m2_m(...) __riscv_vnsrl_wx_u8m2_tumu(__VA_ARGS__) -#define vnsrl_wv_u8m4_m(...) __riscv_vnsrl_wv_u8m4_tumu(__VA_ARGS__) -#define vnsrl_wx_u8m4_m(...) __riscv_vnsrl_wx_u8m4_tumu(__VA_ARGS__) -#define vnsrl_wv_u16mf4_m(...) __riscv_vnsrl_wv_u16mf4_tumu(__VA_ARGS__) -#define vnsrl_wx_u16mf4_m(...) __riscv_vnsrl_wx_u16mf4_tumu(__VA_ARGS__) -#define vnsrl_wv_u16mf2_m(...) __riscv_vnsrl_wv_u16mf2_tumu(__VA_ARGS__) -#define vnsrl_wx_u16mf2_m(...) __riscv_vnsrl_wx_u16mf2_tumu(__VA_ARGS__) -#define vnsrl_wv_u16m1_m(...) __riscv_vnsrl_wv_u16m1_tumu(__VA_ARGS__) -#define vnsrl_wx_u16m1_m(...) __riscv_vnsrl_wx_u16m1_tumu(__VA_ARGS__) -#define vnsrl_wv_u16m2_m(...) __riscv_vnsrl_wv_u16m2_tumu(__VA_ARGS__) -#define vnsrl_wx_u16m2_m(...) __riscv_vnsrl_wx_u16m2_tumu(__VA_ARGS__) -#define vnsrl_wv_u16m4_m(...) __riscv_vnsrl_wv_u16m4_tumu(__VA_ARGS__) -#define vnsrl_wx_u16m4_m(...) __riscv_vnsrl_wx_u16m4_tumu(__VA_ARGS__) -#define vnsrl_wv_u32mf2_m(...) __riscv_vnsrl_wv_u32mf2_tumu(__VA_ARGS__) -#define vnsrl_wx_u32mf2_m(...) __riscv_vnsrl_wx_u32mf2_tumu(__VA_ARGS__) -#define vnsrl_wv_u32m1_m(...) __riscv_vnsrl_wv_u32m1_tumu(__VA_ARGS__) -#define vnsrl_wx_u32m1_m(...) __riscv_vnsrl_wx_u32m1_tumu(__VA_ARGS__) -#define vnsrl_wv_u32m2_m(...) __riscv_vnsrl_wv_u32m2_tumu(__VA_ARGS__) -#define vnsrl_wx_u32m2_m(...) __riscv_vnsrl_wx_u32m2_tumu(__VA_ARGS__) -#define vnsrl_wv_u32m4_m(...) __riscv_vnsrl_wv_u32m4_tumu(__VA_ARGS__) -#define vnsrl_wx_u32m4_m(...) __riscv_vnsrl_wx_u32m4_tumu(__VA_ARGS__) -#define vmseq_vv_i8mf8_b64(...) __riscv_vmseq_vv_i8mf8_b64(__VA_ARGS__) -#define vmseq_vx_i8mf8_b64(...) __riscv_vmseq_vx_i8mf8_b64(__VA_ARGS__) -#define vmseq_vv_i8mf4_b32(...) __riscv_vmseq_vv_i8mf4_b32(__VA_ARGS__) -#define vmseq_vx_i8mf4_b32(...) __riscv_vmseq_vx_i8mf4_b32(__VA_ARGS__) -#define vmseq_vv_i8mf2_b16(...) __riscv_vmseq_vv_i8mf2_b16(__VA_ARGS__) -#define vmseq_vx_i8mf2_b16(...) __riscv_vmseq_vx_i8mf2_b16(__VA_ARGS__) -#define vmseq_vv_i8m1_b8(...) __riscv_vmseq_vv_i8m1_b8(__VA_ARGS__) -#define vmseq_vx_i8m1_b8(...) __riscv_vmseq_vx_i8m1_b8(__VA_ARGS__) -#define vmseq_vv_i8m2_b4(...) __riscv_vmseq_vv_i8m2_b4(__VA_ARGS__) -#define vmseq_vx_i8m2_b4(...) __riscv_vmseq_vx_i8m2_b4(__VA_ARGS__) -#define vmseq_vv_i8m4_b2(...) __riscv_vmseq_vv_i8m4_b2(__VA_ARGS__) -#define vmseq_vx_i8m4_b2(...) __riscv_vmseq_vx_i8m4_b2(__VA_ARGS__) -#define vmseq_vv_i8m8_b1(...) __riscv_vmseq_vv_i8m8_b1(__VA_ARGS__) -#define vmseq_vx_i8m8_b1(...) __riscv_vmseq_vx_i8m8_b1(__VA_ARGS__) -#define vmseq_vv_i16mf4_b64(...) __riscv_vmseq_vv_i16mf4_b64(__VA_ARGS__) -#define vmseq_vx_i16mf4_b64(...) __riscv_vmseq_vx_i16mf4_b64(__VA_ARGS__) -#define vmseq_vv_i16mf2_b32(...) __riscv_vmseq_vv_i16mf2_b32(__VA_ARGS__) -#define vmseq_vx_i16mf2_b32(...) __riscv_vmseq_vx_i16mf2_b32(__VA_ARGS__) -#define vmseq_vv_i16m1_b16(...) __riscv_vmseq_vv_i16m1_b16(__VA_ARGS__) -#define vmseq_vx_i16m1_b16(...) __riscv_vmseq_vx_i16m1_b16(__VA_ARGS__) -#define vmseq_vv_i16m2_b8(...) __riscv_vmseq_vv_i16m2_b8(__VA_ARGS__) -#define vmseq_vx_i16m2_b8(...) __riscv_vmseq_vx_i16m2_b8(__VA_ARGS__) -#define vmseq_vv_i16m4_b4(...) __riscv_vmseq_vv_i16m4_b4(__VA_ARGS__) -#define vmseq_vx_i16m4_b4(...) __riscv_vmseq_vx_i16m4_b4(__VA_ARGS__) -#define vmseq_vv_i16m8_b2(...) __riscv_vmseq_vv_i16m8_b2(__VA_ARGS__) -#define vmseq_vx_i16m8_b2(...) __riscv_vmseq_vx_i16m8_b2(__VA_ARGS__) -#define vmseq_vv_i32mf2_b64(...) __riscv_vmseq_vv_i32mf2_b64(__VA_ARGS__) -#define vmseq_vx_i32mf2_b64(...) __riscv_vmseq_vx_i32mf2_b64(__VA_ARGS__) -#define vmseq_vv_i32m1_b32(...) __riscv_vmseq_vv_i32m1_b32(__VA_ARGS__) -#define vmseq_vx_i32m1_b32(...) __riscv_vmseq_vx_i32m1_b32(__VA_ARGS__) -#define vmseq_vv_i32m2_b16(...) __riscv_vmseq_vv_i32m2_b16(__VA_ARGS__) -#define vmseq_vx_i32m2_b16(...) __riscv_vmseq_vx_i32m2_b16(__VA_ARGS__) -#define vmseq_vv_i32m4_b8(...) __riscv_vmseq_vv_i32m4_b8(__VA_ARGS__) -#define vmseq_vx_i32m4_b8(...) __riscv_vmseq_vx_i32m4_b8(__VA_ARGS__) -#define vmseq_vv_i32m8_b4(...) __riscv_vmseq_vv_i32m8_b4(__VA_ARGS__) -#define vmseq_vx_i32m8_b4(...) __riscv_vmseq_vx_i32m8_b4(__VA_ARGS__) -#define vmseq_vv_i64m1_b64(...) __riscv_vmseq_vv_i64m1_b64(__VA_ARGS__) -#define vmseq_vx_i64m1_b64(...) __riscv_vmseq_vx_i64m1_b64(__VA_ARGS__) -#define vmseq_vv_i64m2_b32(...) __riscv_vmseq_vv_i64m2_b32(__VA_ARGS__) -#define vmseq_vx_i64m2_b32(...) __riscv_vmseq_vx_i64m2_b32(__VA_ARGS__) -#define vmseq_vv_i64m4_b16(...) __riscv_vmseq_vv_i64m4_b16(__VA_ARGS__) -#define vmseq_vx_i64m4_b16(...) __riscv_vmseq_vx_i64m4_b16(__VA_ARGS__) -#define vmseq_vv_i64m8_b8(...) __riscv_vmseq_vv_i64m8_b8(__VA_ARGS__) -#define vmseq_vx_i64m8_b8(...) __riscv_vmseq_vx_i64m8_b8(__VA_ARGS__) -#define vmsne_vv_i8mf8_b64(...) __riscv_vmsne_vv_i8mf8_b64(__VA_ARGS__) -#define vmsne_vx_i8mf8_b64(...) __riscv_vmsne_vx_i8mf8_b64(__VA_ARGS__) -#define vmsne_vv_i8mf4_b32(...) __riscv_vmsne_vv_i8mf4_b32(__VA_ARGS__) -#define vmsne_vx_i8mf4_b32(...) __riscv_vmsne_vx_i8mf4_b32(__VA_ARGS__) -#define vmsne_vv_i8mf2_b16(...) __riscv_vmsne_vv_i8mf2_b16(__VA_ARGS__) -#define vmsne_vx_i8mf2_b16(...) __riscv_vmsne_vx_i8mf2_b16(__VA_ARGS__) -#define vmsne_vv_i8m1_b8(...) __riscv_vmsne_vv_i8m1_b8(__VA_ARGS__) -#define vmsne_vx_i8m1_b8(...) __riscv_vmsne_vx_i8m1_b8(__VA_ARGS__) -#define vmsne_vv_i8m2_b4(...) __riscv_vmsne_vv_i8m2_b4(__VA_ARGS__) -#define vmsne_vx_i8m2_b4(...) __riscv_vmsne_vx_i8m2_b4(__VA_ARGS__) -#define vmsne_vv_i8m4_b2(...) __riscv_vmsne_vv_i8m4_b2(__VA_ARGS__) -#define vmsne_vx_i8m4_b2(...) __riscv_vmsne_vx_i8m4_b2(__VA_ARGS__) -#define vmsne_vv_i8m8_b1(...) __riscv_vmsne_vv_i8m8_b1(__VA_ARGS__) -#define vmsne_vx_i8m8_b1(...) __riscv_vmsne_vx_i8m8_b1(__VA_ARGS__) -#define vmsne_vv_i16mf4_b64(...) __riscv_vmsne_vv_i16mf4_b64(__VA_ARGS__) -#define vmsne_vx_i16mf4_b64(...) __riscv_vmsne_vx_i16mf4_b64(__VA_ARGS__) -#define vmsne_vv_i16mf2_b32(...) __riscv_vmsne_vv_i16mf2_b32(__VA_ARGS__) -#define vmsne_vx_i16mf2_b32(...) __riscv_vmsne_vx_i16mf2_b32(__VA_ARGS__) -#define vmsne_vv_i16m1_b16(...) __riscv_vmsne_vv_i16m1_b16(__VA_ARGS__) -#define vmsne_vx_i16m1_b16(...) __riscv_vmsne_vx_i16m1_b16(__VA_ARGS__) -#define vmsne_vv_i16m2_b8(...) __riscv_vmsne_vv_i16m2_b8(__VA_ARGS__) -#define vmsne_vx_i16m2_b8(...) __riscv_vmsne_vx_i16m2_b8(__VA_ARGS__) -#define vmsne_vv_i16m4_b4(...) __riscv_vmsne_vv_i16m4_b4(__VA_ARGS__) -#define vmsne_vx_i16m4_b4(...) __riscv_vmsne_vx_i16m4_b4(__VA_ARGS__) -#define vmsne_vv_i16m8_b2(...) __riscv_vmsne_vv_i16m8_b2(__VA_ARGS__) -#define vmsne_vx_i16m8_b2(...) __riscv_vmsne_vx_i16m8_b2(__VA_ARGS__) -#define vmsne_vv_i32mf2_b64(...) __riscv_vmsne_vv_i32mf2_b64(__VA_ARGS__) -#define vmsne_vx_i32mf2_b64(...) __riscv_vmsne_vx_i32mf2_b64(__VA_ARGS__) -#define vmsne_vv_i32m1_b32(...) __riscv_vmsne_vv_i32m1_b32(__VA_ARGS__) -#define vmsne_vx_i32m1_b32(...) __riscv_vmsne_vx_i32m1_b32(__VA_ARGS__) -#define vmsne_vv_i32m2_b16(...) __riscv_vmsne_vv_i32m2_b16(__VA_ARGS__) -#define vmsne_vx_i32m2_b16(...) __riscv_vmsne_vx_i32m2_b16(__VA_ARGS__) -#define vmsne_vv_i32m4_b8(...) __riscv_vmsne_vv_i32m4_b8(__VA_ARGS__) -#define vmsne_vx_i32m4_b8(...) __riscv_vmsne_vx_i32m4_b8(__VA_ARGS__) -#define vmsne_vv_i32m8_b4(...) __riscv_vmsne_vv_i32m8_b4(__VA_ARGS__) -#define vmsne_vx_i32m8_b4(...) __riscv_vmsne_vx_i32m8_b4(__VA_ARGS__) -#define vmsne_vv_i64m1_b64(...) __riscv_vmsne_vv_i64m1_b64(__VA_ARGS__) -#define vmsne_vx_i64m1_b64(...) __riscv_vmsne_vx_i64m1_b64(__VA_ARGS__) -#define vmsne_vv_i64m2_b32(...) __riscv_vmsne_vv_i64m2_b32(__VA_ARGS__) -#define vmsne_vx_i64m2_b32(...) __riscv_vmsne_vx_i64m2_b32(__VA_ARGS__) -#define vmsne_vv_i64m4_b16(...) __riscv_vmsne_vv_i64m4_b16(__VA_ARGS__) -#define vmsne_vx_i64m4_b16(...) __riscv_vmsne_vx_i64m4_b16(__VA_ARGS__) -#define vmsne_vv_i64m8_b8(...) __riscv_vmsne_vv_i64m8_b8(__VA_ARGS__) -#define vmsne_vx_i64m8_b8(...) __riscv_vmsne_vx_i64m8_b8(__VA_ARGS__) -#define vmslt_vv_i8mf8_b64(...) __riscv_vmslt_vv_i8mf8_b64(__VA_ARGS__) -#define vmslt_vx_i8mf8_b64(...) __riscv_vmslt_vx_i8mf8_b64(__VA_ARGS__) -#define vmslt_vv_i8mf4_b32(...) __riscv_vmslt_vv_i8mf4_b32(__VA_ARGS__) -#define vmslt_vx_i8mf4_b32(...) __riscv_vmslt_vx_i8mf4_b32(__VA_ARGS__) -#define vmslt_vv_i8mf2_b16(...) __riscv_vmslt_vv_i8mf2_b16(__VA_ARGS__) -#define vmslt_vx_i8mf2_b16(...) __riscv_vmslt_vx_i8mf2_b16(__VA_ARGS__) -#define vmslt_vv_i8m1_b8(...) __riscv_vmslt_vv_i8m1_b8(__VA_ARGS__) -#define vmslt_vx_i8m1_b8(...) __riscv_vmslt_vx_i8m1_b8(__VA_ARGS__) -#define vmslt_vv_i8m2_b4(...) __riscv_vmslt_vv_i8m2_b4(__VA_ARGS__) -#define vmslt_vx_i8m2_b4(...) __riscv_vmslt_vx_i8m2_b4(__VA_ARGS__) -#define vmslt_vv_i8m4_b2(...) __riscv_vmslt_vv_i8m4_b2(__VA_ARGS__) -#define vmslt_vx_i8m4_b2(...) __riscv_vmslt_vx_i8m4_b2(__VA_ARGS__) -#define vmslt_vv_i8m8_b1(...) __riscv_vmslt_vv_i8m8_b1(__VA_ARGS__) -#define vmslt_vx_i8m8_b1(...) __riscv_vmslt_vx_i8m8_b1(__VA_ARGS__) -#define vmslt_vv_i16mf4_b64(...) __riscv_vmslt_vv_i16mf4_b64(__VA_ARGS__) -#define vmslt_vx_i16mf4_b64(...) __riscv_vmslt_vx_i16mf4_b64(__VA_ARGS__) -#define vmslt_vv_i16mf2_b32(...) __riscv_vmslt_vv_i16mf2_b32(__VA_ARGS__) -#define vmslt_vx_i16mf2_b32(...) __riscv_vmslt_vx_i16mf2_b32(__VA_ARGS__) -#define vmslt_vv_i16m1_b16(...) __riscv_vmslt_vv_i16m1_b16(__VA_ARGS__) -#define vmslt_vx_i16m1_b16(...) __riscv_vmslt_vx_i16m1_b16(__VA_ARGS__) -#define vmslt_vv_i16m2_b8(...) __riscv_vmslt_vv_i16m2_b8(__VA_ARGS__) -#define vmslt_vx_i16m2_b8(...) __riscv_vmslt_vx_i16m2_b8(__VA_ARGS__) -#define vmslt_vv_i16m4_b4(...) __riscv_vmslt_vv_i16m4_b4(__VA_ARGS__) -#define vmslt_vx_i16m4_b4(...) __riscv_vmslt_vx_i16m4_b4(__VA_ARGS__) -#define vmslt_vv_i16m8_b2(...) __riscv_vmslt_vv_i16m8_b2(__VA_ARGS__) -#define vmslt_vx_i16m8_b2(...) __riscv_vmslt_vx_i16m8_b2(__VA_ARGS__) -#define vmslt_vv_i32mf2_b64(...) __riscv_vmslt_vv_i32mf2_b64(__VA_ARGS__) -#define vmslt_vx_i32mf2_b64(...) __riscv_vmslt_vx_i32mf2_b64(__VA_ARGS__) -#define vmslt_vv_i32m1_b32(...) __riscv_vmslt_vv_i32m1_b32(__VA_ARGS__) -#define vmslt_vx_i32m1_b32(...) __riscv_vmslt_vx_i32m1_b32(__VA_ARGS__) -#define vmslt_vv_i32m2_b16(...) __riscv_vmslt_vv_i32m2_b16(__VA_ARGS__) -#define vmslt_vx_i32m2_b16(...) __riscv_vmslt_vx_i32m2_b16(__VA_ARGS__) -#define vmslt_vv_i32m4_b8(...) __riscv_vmslt_vv_i32m4_b8(__VA_ARGS__) -#define vmslt_vx_i32m4_b8(...) __riscv_vmslt_vx_i32m4_b8(__VA_ARGS__) -#define vmslt_vv_i32m8_b4(...) __riscv_vmslt_vv_i32m8_b4(__VA_ARGS__) -#define vmslt_vx_i32m8_b4(...) __riscv_vmslt_vx_i32m8_b4(__VA_ARGS__) -#define vmslt_vv_i64m1_b64(...) __riscv_vmslt_vv_i64m1_b64(__VA_ARGS__) -#define vmslt_vx_i64m1_b64(...) __riscv_vmslt_vx_i64m1_b64(__VA_ARGS__) -#define vmslt_vv_i64m2_b32(...) __riscv_vmslt_vv_i64m2_b32(__VA_ARGS__) -#define vmslt_vx_i64m2_b32(...) __riscv_vmslt_vx_i64m2_b32(__VA_ARGS__) -#define vmslt_vv_i64m4_b16(...) __riscv_vmslt_vv_i64m4_b16(__VA_ARGS__) -#define vmslt_vx_i64m4_b16(...) __riscv_vmslt_vx_i64m4_b16(__VA_ARGS__) -#define vmslt_vv_i64m8_b8(...) __riscv_vmslt_vv_i64m8_b8(__VA_ARGS__) -#define vmslt_vx_i64m8_b8(...) __riscv_vmslt_vx_i64m8_b8(__VA_ARGS__) -#define vmsle_vv_i8mf8_b64(...) __riscv_vmsle_vv_i8mf8_b64(__VA_ARGS__) -#define vmsle_vx_i8mf8_b64(...) __riscv_vmsle_vx_i8mf8_b64(__VA_ARGS__) -#define vmsle_vv_i8mf4_b32(...) __riscv_vmsle_vv_i8mf4_b32(__VA_ARGS__) -#define vmsle_vx_i8mf4_b32(...) __riscv_vmsle_vx_i8mf4_b32(__VA_ARGS__) -#define vmsle_vv_i8mf2_b16(...) __riscv_vmsle_vv_i8mf2_b16(__VA_ARGS__) -#define vmsle_vx_i8mf2_b16(...) __riscv_vmsle_vx_i8mf2_b16(__VA_ARGS__) -#define vmsle_vv_i8m1_b8(...) __riscv_vmsle_vv_i8m1_b8(__VA_ARGS__) -#define vmsle_vx_i8m1_b8(...) __riscv_vmsle_vx_i8m1_b8(__VA_ARGS__) -#define vmsle_vv_i8m2_b4(...) __riscv_vmsle_vv_i8m2_b4(__VA_ARGS__) -#define vmsle_vx_i8m2_b4(...) __riscv_vmsle_vx_i8m2_b4(__VA_ARGS__) -#define vmsle_vv_i8m4_b2(...) __riscv_vmsle_vv_i8m4_b2(__VA_ARGS__) -#define vmsle_vx_i8m4_b2(...) __riscv_vmsle_vx_i8m4_b2(__VA_ARGS__) -#define vmsle_vv_i8m8_b1(...) __riscv_vmsle_vv_i8m8_b1(__VA_ARGS__) -#define vmsle_vx_i8m8_b1(...) __riscv_vmsle_vx_i8m8_b1(__VA_ARGS__) -#define vmsle_vv_i16mf4_b64(...) __riscv_vmsle_vv_i16mf4_b64(__VA_ARGS__) -#define vmsle_vx_i16mf4_b64(...) __riscv_vmsle_vx_i16mf4_b64(__VA_ARGS__) -#define vmsle_vv_i16mf2_b32(...) __riscv_vmsle_vv_i16mf2_b32(__VA_ARGS__) -#define vmsle_vx_i16mf2_b32(...) __riscv_vmsle_vx_i16mf2_b32(__VA_ARGS__) -#define vmsle_vv_i16m1_b16(...) __riscv_vmsle_vv_i16m1_b16(__VA_ARGS__) -#define vmsle_vx_i16m1_b16(...) __riscv_vmsle_vx_i16m1_b16(__VA_ARGS__) -#define vmsle_vv_i16m2_b8(...) __riscv_vmsle_vv_i16m2_b8(__VA_ARGS__) -#define vmsle_vx_i16m2_b8(...) __riscv_vmsle_vx_i16m2_b8(__VA_ARGS__) -#define vmsle_vv_i16m4_b4(...) __riscv_vmsle_vv_i16m4_b4(__VA_ARGS__) -#define vmsle_vx_i16m4_b4(...) __riscv_vmsle_vx_i16m4_b4(__VA_ARGS__) -#define vmsle_vv_i16m8_b2(...) __riscv_vmsle_vv_i16m8_b2(__VA_ARGS__) -#define vmsle_vx_i16m8_b2(...) __riscv_vmsle_vx_i16m8_b2(__VA_ARGS__) -#define vmsle_vv_i32mf2_b64(...) __riscv_vmsle_vv_i32mf2_b64(__VA_ARGS__) -#define vmsle_vx_i32mf2_b64(...) __riscv_vmsle_vx_i32mf2_b64(__VA_ARGS__) -#define vmsle_vv_i32m1_b32(...) __riscv_vmsle_vv_i32m1_b32(__VA_ARGS__) -#define vmsle_vx_i32m1_b32(...) __riscv_vmsle_vx_i32m1_b32(__VA_ARGS__) -#define vmsle_vv_i32m2_b16(...) __riscv_vmsle_vv_i32m2_b16(__VA_ARGS__) -#define vmsle_vx_i32m2_b16(...) __riscv_vmsle_vx_i32m2_b16(__VA_ARGS__) -#define vmsle_vv_i32m4_b8(...) __riscv_vmsle_vv_i32m4_b8(__VA_ARGS__) -#define vmsle_vx_i32m4_b8(...) __riscv_vmsle_vx_i32m4_b8(__VA_ARGS__) -#define vmsle_vv_i32m8_b4(...) __riscv_vmsle_vv_i32m8_b4(__VA_ARGS__) -#define vmsle_vx_i32m8_b4(...) __riscv_vmsle_vx_i32m8_b4(__VA_ARGS__) -#define vmsle_vv_i64m1_b64(...) __riscv_vmsle_vv_i64m1_b64(__VA_ARGS__) -#define vmsle_vx_i64m1_b64(...) __riscv_vmsle_vx_i64m1_b64(__VA_ARGS__) -#define vmsle_vv_i64m2_b32(...) __riscv_vmsle_vv_i64m2_b32(__VA_ARGS__) -#define vmsle_vx_i64m2_b32(...) __riscv_vmsle_vx_i64m2_b32(__VA_ARGS__) -#define vmsle_vv_i64m4_b16(...) __riscv_vmsle_vv_i64m4_b16(__VA_ARGS__) -#define vmsle_vx_i64m4_b16(...) __riscv_vmsle_vx_i64m4_b16(__VA_ARGS__) -#define vmsle_vv_i64m8_b8(...) __riscv_vmsle_vv_i64m8_b8(__VA_ARGS__) -#define vmsle_vx_i64m8_b8(...) __riscv_vmsle_vx_i64m8_b8(__VA_ARGS__) -#define vmsgt_vv_i8mf8_b64(...) __riscv_vmsgt_vv_i8mf8_b64(__VA_ARGS__) -#define vmsgt_vx_i8mf8_b64(...) __riscv_vmsgt_vx_i8mf8_b64(__VA_ARGS__) -#define vmsgt_vv_i8mf4_b32(...) __riscv_vmsgt_vv_i8mf4_b32(__VA_ARGS__) -#define vmsgt_vx_i8mf4_b32(...) __riscv_vmsgt_vx_i8mf4_b32(__VA_ARGS__) -#define vmsgt_vv_i8mf2_b16(...) __riscv_vmsgt_vv_i8mf2_b16(__VA_ARGS__) -#define vmsgt_vx_i8mf2_b16(...) __riscv_vmsgt_vx_i8mf2_b16(__VA_ARGS__) -#define vmsgt_vv_i8m1_b8(...) __riscv_vmsgt_vv_i8m1_b8(__VA_ARGS__) -#define vmsgt_vx_i8m1_b8(...) __riscv_vmsgt_vx_i8m1_b8(__VA_ARGS__) -#define vmsgt_vv_i8m2_b4(...) __riscv_vmsgt_vv_i8m2_b4(__VA_ARGS__) -#define vmsgt_vx_i8m2_b4(...) __riscv_vmsgt_vx_i8m2_b4(__VA_ARGS__) -#define vmsgt_vv_i8m4_b2(...) __riscv_vmsgt_vv_i8m4_b2(__VA_ARGS__) -#define vmsgt_vx_i8m4_b2(...) __riscv_vmsgt_vx_i8m4_b2(__VA_ARGS__) -#define vmsgt_vv_i8m8_b1(...) __riscv_vmsgt_vv_i8m8_b1(__VA_ARGS__) -#define vmsgt_vx_i8m8_b1(...) __riscv_vmsgt_vx_i8m8_b1(__VA_ARGS__) -#define vmsgt_vv_i16mf4_b64(...) __riscv_vmsgt_vv_i16mf4_b64(__VA_ARGS__) -#define vmsgt_vx_i16mf4_b64(...) __riscv_vmsgt_vx_i16mf4_b64(__VA_ARGS__) -#define vmsgt_vv_i16mf2_b32(...) __riscv_vmsgt_vv_i16mf2_b32(__VA_ARGS__) -#define vmsgt_vx_i16mf2_b32(...) __riscv_vmsgt_vx_i16mf2_b32(__VA_ARGS__) -#define vmsgt_vv_i16m1_b16(...) __riscv_vmsgt_vv_i16m1_b16(__VA_ARGS__) -#define vmsgt_vx_i16m1_b16(...) __riscv_vmsgt_vx_i16m1_b16(__VA_ARGS__) -#define vmsgt_vv_i16m2_b8(...) __riscv_vmsgt_vv_i16m2_b8(__VA_ARGS__) -#define vmsgt_vx_i16m2_b8(...) __riscv_vmsgt_vx_i16m2_b8(__VA_ARGS__) -#define vmsgt_vv_i16m4_b4(...) __riscv_vmsgt_vv_i16m4_b4(__VA_ARGS__) -#define vmsgt_vx_i16m4_b4(...) __riscv_vmsgt_vx_i16m4_b4(__VA_ARGS__) -#define vmsgt_vv_i16m8_b2(...) __riscv_vmsgt_vv_i16m8_b2(__VA_ARGS__) -#define vmsgt_vx_i16m8_b2(...) __riscv_vmsgt_vx_i16m8_b2(__VA_ARGS__) -#define vmsgt_vv_i32mf2_b64(...) __riscv_vmsgt_vv_i32mf2_b64(__VA_ARGS__) -#define vmsgt_vx_i32mf2_b64(...) __riscv_vmsgt_vx_i32mf2_b64(__VA_ARGS__) -#define vmsgt_vv_i32m1_b32(...) __riscv_vmsgt_vv_i32m1_b32(__VA_ARGS__) -#define vmsgt_vx_i32m1_b32(...) __riscv_vmsgt_vx_i32m1_b32(__VA_ARGS__) -#define vmsgt_vv_i32m2_b16(...) __riscv_vmsgt_vv_i32m2_b16(__VA_ARGS__) -#define vmsgt_vx_i32m2_b16(...) __riscv_vmsgt_vx_i32m2_b16(__VA_ARGS__) -#define vmsgt_vv_i32m4_b8(...) __riscv_vmsgt_vv_i32m4_b8(__VA_ARGS__) -#define vmsgt_vx_i32m4_b8(...) __riscv_vmsgt_vx_i32m4_b8(__VA_ARGS__) -#define vmsgt_vv_i32m8_b4(...) __riscv_vmsgt_vv_i32m8_b4(__VA_ARGS__) -#define vmsgt_vx_i32m8_b4(...) __riscv_vmsgt_vx_i32m8_b4(__VA_ARGS__) -#define vmsgt_vv_i64m1_b64(...) __riscv_vmsgt_vv_i64m1_b64(__VA_ARGS__) -#define vmsgt_vx_i64m1_b64(...) __riscv_vmsgt_vx_i64m1_b64(__VA_ARGS__) -#define vmsgt_vv_i64m2_b32(...) __riscv_vmsgt_vv_i64m2_b32(__VA_ARGS__) -#define vmsgt_vx_i64m2_b32(...) __riscv_vmsgt_vx_i64m2_b32(__VA_ARGS__) -#define vmsgt_vv_i64m4_b16(...) __riscv_vmsgt_vv_i64m4_b16(__VA_ARGS__) -#define vmsgt_vx_i64m4_b16(...) __riscv_vmsgt_vx_i64m4_b16(__VA_ARGS__) -#define vmsgt_vv_i64m8_b8(...) __riscv_vmsgt_vv_i64m8_b8(__VA_ARGS__) -#define vmsgt_vx_i64m8_b8(...) __riscv_vmsgt_vx_i64m8_b8(__VA_ARGS__) -#define vmsge_vv_i8mf8_b64(...) __riscv_vmsge_vv_i8mf8_b64(__VA_ARGS__) -#define vmsge_vx_i8mf8_b64(...) __riscv_vmsge_vx_i8mf8_b64(__VA_ARGS__) -#define vmsge_vv_i8mf4_b32(...) __riscv_vmsge_vv_i8mf4_b32(__VA_ARGS__) -#define vmsge_vx_i8mf4_b32(...) __riscv_vmsge_vx_i8mf4_b32(__VA_ARGS__) -#define vmsge_vv_i8mf2_b16(...) __riscv_vmsge_vv_i8mf2_b16(__VA_ARGS__) -#define vmsge_vx_i8mf2_b16(...) __riscv_vmsge_vx_i8mf2_b16(__VA_ARGS__) -#define vmsge_vv_i8m1_b8(...) __riscv_vmsge_vv_i8m1_b8(__VA_ARGS__) -#define vmsge_vx_i8m1_b8(...) __riscv_vmsge_vx_i8m1_b8(__VA_ARGS__) -#define vmsge_vv_i8m2_b4(...) __riscv_vmsge_vv_i8m2_b4(__VA_ARGS__) -#define vmsge_vx_i8m2_b4(...) __riscv_vmsge_vx_i8m2_b4(__VA_ARGS__) -#define vmsge_vv_i8m4_b2(...) __riscv_vmsge_vv_i8m4_b2(__VA_ARGS__) -#define vmsge_vx_i8m4_b2(...) __riscv_vmsge_vx_i8m4_b2(__VA_ARGS__) -#define vmsge_vv_i8m8_b1(...) __riscv_vmsge_vv_i8m8_b1(__VA_ARGS__) -#define vmsge_vx_i8m8_b1(...) __riscv_vmsge_vx_i8m8_b1(__VA_ARGS__) -#define vmsge_vv_i16mf4_b64(...) __riscv_vmsge_vv_i16mf4_b64(__VA_ARGS__) -#define vmsge_vx_i16mf4_b64(...) __riscv_vmsge_vx_i16mf4_b64(__VA_ARGS__) -#define vmsge_vv_i16mf2_b32(...) __riscv_vmsge_vv_i16mf2_b32(__VA_ARGS__) -#define vmsge_vx_i16mf2_b32(...) __riscv_vmsge_vx_i16mf2_b32(__VA_ARGS__) -#define vmsge_vv_i16m1_b16(...) __riscv_vmsge_vv_i16m1_b16(__VA_ARGS__) -#define vmsge_vx_i16m1_b16(...) __riscv_vmsge_vx_i16m1_b16(__VA_ARGS__) -#define vmsge_vv_i16m2_b8(...) __riscv_vmsge_vv_i16m2_b8(__VA_ARGS__) -#define vmsge_vx_i16m2_b8(...) __riscv_vmsge_vx_i16m2_b8(__VA_ARGS__) -#define vmsge_vv_i16m4_b4(...) __riscv_vmsge_vv_i16m4_b4(__VA_ARGS__) -#define vmsge_vx_i16m4_b4(...) __riscv_vmsge_vx_i16m4_b4(__VA_ARGS__) -#define vmsge_vv_i16m8_b2(...) __riscv_vmsge_vv_i16m8_b2(__VA_ARGS__) -#define vmsge_vx_i16m8_b2(...) __riscv_vmsge_vx_i16m8_b2(__VA_ARGS__) -#define vmsge_vv_i32mf2_b64(...) __riscv_vmsge_vv_i32mf2_b64(__VA_ARGS__) -#define vmsge_vx_i32mf2_b64(...) __riscv_vmsge_vx_i32mf2_b64(__VA_ARGS__) -#define vmsge_vv_i32m1_b32(...) __riscv_vmsge_vv_i32m1_b32(__VA_ARGS__) -#define vmsge_vx_i32m1_b32(...) __riscv_vmsge_vx_i32m1_b32(__VA_ARGS__) -#define vmsge_vv_i32m2_b16(...) __riscv_vmsge_vv_i32m2_b16(__VA_ARGS__) -#define vmsge_vx_i32m2_b16(...) __riscv_vmsge_vx_i32m2_b16(__VA_ARGS__) -#define vmsge_vv_i32m4_b8(...) __riscv_vmsge_vv_i32m4_b8(__VA_ARGS__) -#define vmsge_vx_i32m4_b8(...) __riscv_vmsge_vx_i32m4_b8(__VA_ARGS__) -#define vmsge_vv_i32m8_b4(...) __riscv_vmsge_vv_i32m8_b4(__VA_ARGS__) -#define vmsge_vx_i32m8_b4(...) __riscv_vmsge_vx_i32m8_b4(__VA_ARGS__) -#define vmsge_vv_i64m1_b64(...) __riscv_vmsge_vv_i64m1_b64(__VA_ARGS__) -#define vmsge_vx_i64m1_b64(...) __riscv_vmsge_vx_i64m1_b64(__VA_ARGS__) -#define vmsge_vv_i64m2_b32(...) __riscv_vmsge_vv_i64m2_b32(__VA_ARGS__) -#define vmsge_vx_i64m2_b32(...) __riscv_vmsge_vx_i64m2_b32(__VA_ARGS__) -#define vmsge_vv_i64m4_b16(...) __riscv_vmsge_vv_i64m4_b16(__VA_ARGS__) -#define vmsge_vx_i64m4_b16(...) __riscv_vmsge_vx_i64m4_b16(__VA_ARGS__) -#define vmsge_vv_i64m8_b8(...) __riscv_vmsge_vv_i64m8_b8(__VA_ARGS__) -#define vmsge_vx_i64m8_b8(...) __riscv_vmsge_vx_i64m8_b8(__VA_ARGS__) -#define vmseq_vv_u8mf8_b64(...) __riscv_vmseq_vv_u8mf8_b64(__VA_ARGS__) -#define vmseq_vx_u8mf8_b64(...) __riscv_vmseq_vx_u8mf8_b64(__VA_ARGS__) -#define vmseq_vv_u8mf4_b32(...) __riscv_vmseq_vv_u8mf4_b32(__VA_ARGS__) -#define vmseq_vx_u8mf4_b32(...) __riscv_vmseq_vx_u8mf4_b32(__VA_ARGS__) -#define vmseq_vv_u8mf2_b16(...) __riscv_vmseq_vv_u8mf2_b16(__VA_ARGS__) -#define vmseq_vx_u8mf2_b16(...) __riscv_vmseq_vx_u8mf2_b16(__VA_ARGS__) -#define vmseq_vv_u8m1_b8(...) __riscv_vmseq_vv_u8m1_b8(__VA_ARGS__) -#define vmseq_vx_u8m1_b8(...) __riscv_vmseq_vx_u8m1_b8(__VA_ARGS__) -#define vmseq_vv_u8m2_b4(...) __riscv_vmseq_vv_u8m2_b4(__VA_ARGS__) -#define vmseq_vx_u8m2_b4(...) __riscv_vmseq_vx_u8m2_b4(__VA_ARGS__) -#define vmseq_vv_u8m4_b2(...) __riscv_vmseq_vv_u8m4_b2(__VA_ARGS__) -#define vmseq_vx_u8m4_b2(...) __riscv_vmseq_vx_u8m4_b2(__VA_ARGS__) -#define vmseq_vv_u8m8_b1(...) __riscv_vmseq_vv_u8m8_b1(__VA_ARGS__) -#define vmseq_vx_u8m8_b1(...) __riscv_vmseq_vx_u8m8_b1(__VA_ARGS__) -#define vmseq_vv_u16mf4_b64(...) __riscv_vmseq_vv_u16mf4_b64(__VA_ARGS__) -#define vmseq_vx_u16mf4_b64(...) __riscv_vmseq_vx_u16mf4_b64(__VA_ARGS__) -#define vmseq_vv_u16mf2_b32(...) __riscv_vmseq_vv_u16mf2_b32(__VA_ARGS__) -#define vmseq_vx_u16mf2_b32(...) __riscv_vmseq_vx_u16mf2_b32(__VA_ARGS__) -#define vmseq_vv_u16m1_b16(...) __riscv_vmseq_vv_u16m1_b16(__VA_ARGS__) -#define vmseq_vx_u16m1_b16(...) __riscv_vmseq_vx_u16m1_b16(__VA_ARGS__) -#define vmseq_vv_u16m2_b8(...) __riscv_vmseq_vv_u16m2_b8(__VA_ARGS__) -#define vmseq_vx_u16m2_b8(...) __riscv_vmseq_vx_u16m2_b8(__VA_ARGS__) -#define vmseq_vv_u16m4_b4(...) __riscv_vmseq_vv_u16m4_b4(__VA_ARGS__) -#define vmseq_vx_u16m4_b4(...) __riscv_vmseq_vx_u16m4_b4(__VA_ARGS__) -#define vmseq_vv_u16m8_b2(...) __riscv_vmseq_vv_u16m8_b2(__VA_ARGS__) -#define vmseq_vx_u16m8_b2(...) __riscv_vmseq_vx_u16m8_b2(__VA_ARGS__) -#define vmseq_vv_u32mf2_b64(...) __riscv_vmseq_vv_u32mf2_b64(__VA_ARGS__) -#define vmseq_vx_u32mf2_b64(...) __riscv_vmseq_vx_u32mf2_b64(__VA_ARGS__) -#define vmseq_vv_u32m1_b32(...) __riscv_vmseq_vv_u32m1_b32(__VA_ARGS__) -#define vmseq_vx_u32m1_b32(...) __riscv_vmseq_vx_u32m1_b32(__VA_ARGS__) -#define vmseq_vv_u32m2_b16(...) __riscv_vmseq_vv_u32m2_b16(__VA_ARGS__) -#define vmseq_vx_u32m2_b16(...) __riscv_vmseq_vx_u32m2_b16(__VA_ARGS__) -#define vmseq_vv_u32m4_b8(...) __riscv_vmseq_vv_u32m4_b8(__VA_ARGS__) -#define vmseq_vx_u32m4_b8(...) __riscv_vmseq_vx_u32m4_b8(__VA_ARGS__) -#define vmseq_vv_u32m8_b4(...) __riscv_vmseq_vv_u32m8_b4(__VA_ARGS__) -#define vmseq_vx_u32m8_b4(...) __riscv_vmseq_vx_u32m8_b4(__VA_ARGS__) -#define vmseq_vv_u64m1_b64(...) __riscv_vmseq_vv_u64m1_b64(__VA_ARGS__) -#define vmseq_vx_u64m1_b64(...) __riscv_vmseq_vx_u64m1_b64(__VA_ARGS__) -#define vmseq_vv_u64m2_b32(...) __riscv_vmseq_vv_u64m2_b32(__VA_ARGS__) -#define vmseq_vx_u64m2_b32(...) __riscv_vmseq_vx_u64m2_b32(__VA_ARGS__) -#define vmseq_vv_u64m4_b16(...) __riscv_vmseq_vv_u64m4_b16(__VA_ARGS__) -#define vmseq_vx_u64m4_b16(...) __riscv_vmseq_vx_u64m4_b16(__VA_ARGS__) -#define vmseq_vv_u64m8_b8(...) __riscv_vmseq_vv_u64m8_b8(__VA_ARGS__) -#define vmseq_vx_u64m8_b8(...) __riscv_vmseq_vx_u64m8_b8(__VA_ARGS__) -#define vmsne_vv_u8mf8_b64(...) __riscv_vmsne_vv_u8mf8_b64(__VA_ARGS__) -#define vmsne_vx_u8mf8_b64(...) __riscv_vmsne_vx_u8mf8_b64(__VA_ARGS__) -#define vmsne_vv_u8mf4_b32(...) __riscv_vmsne_vv_u8mf4_b32(__VA_ARGS__) -#define vmsne_vx_u8mf4_b32(...) __riscv_vmsne_vx_u8mf4_b32(__VA_ARGS__) -#define vmsne_vv_u8mf2_b16(...) __riscv_vmsne_vv_u8mf2_b16(__VA_ARGS__) -#define vmsne_vx_u8mf2_b16(...) __riscv_vmsne_vx_u8mf2_b16(__VA_ARGS__) -#define vmsne_vv_u8m1_b8(...) __riscv_vmsne_vv_u8m1_b8(__VA_ARGS__) -#define vmsne_vx_u8m1_b8(...) __riscv_vmsne_vx_u8m1_b8(__VA_ARGS__) -#define vmsne_vv_u8m2_b4(...) __riscv_vmsne_vv_u8m2_b4(__VA_ARGS__) -#define vmsne_vx_u8m2_b4(...) __riscv_vmsne_vx_u8m2_b4(__VA_ARGS__) -#define vmsne_vv_u8m4_b2(...) __riscv_vmsne_vv_u8m4_b2(__VA_ARGS__) -#define vmsne_vx_u8m4_b2(...) __riscv_vmsne_vx_u8m4_b2(__VA_ARGS__) -#define vmsne_vv_u8m8_b1(...) __riscv_vmsne_vv_u8m8_b1(__VA_ARGS__) -#define vmsne_vx_u8m8_b1(...) __riscv_vmsne_vx_u8m8_b1(__VA_ARGS__) -#define vmsne_vv_u16mf4_b64(...) __riscv_vmsne_vv_u16mf4_b64(__VA_ARGS__) -#define vmsne_vx_u16mf4_b64(...) __riscv_vmsne_vx_u16mf4_b64(__VA_ARGS__) -#define vmsne_vv_u16mf2_b32(...) __riscv_vmsne_vv_u16mf2_b32(__VA_ARGS__) -#define vmsne_vx_u16mf2_b32(...) __riscv_vmsne_vx_u16mf2_b32(__VA_ARGS__) -#define vmsne_vv_u16m1_b16(...) __riscv_vmsne_vv_u16m1_b16(__VA_ARGS__) -#define vmsne_vx_u16m1_b16(...) __riscv_vmsne_vx_u16m1_b16(__VA_ARGS__) -#define vmsne_vv_u16m2_b8(...) __riscv_vmsne_vv_u16m2_b8(__VA_ARGS__) -#define vmsne_vx_u16m2_b8(...) __riscv_vmsne_vx_u16m2_b8(__VA_ARGS__) -#define vmsne_vv_u16m4_b4(...) __riscv_vmsne_vv_u16m4_b4(__VA_ARGS__) -#define vmsne_vx_u16m4_b4(...) __riscv_vmsne_vx_u16m4_b4(__VA_ARGS__) -#define vmsne_vv_u16m8_b2(...) __riscv_vmsne_vv_u16m8_b2(__VA_ARGS__) -#define vmsne_vx_u16m8_b2(...) __riscv_vmsne_vx_u16m8_b2(__VA_ARGS__) -#define vmsne_vv_u32mf2_b64(...) __riscv_vmsne_vv_u32mf2_b64(__VA_ARGS__) -#define vmsne_vx_u32mf2_b64(...) __riscv_vmsne_vx_u32mf2_b64(__VA_ARGS__) -#define vmsne_vv_u32m1_b32(...) __riscv_vmsne_vv_u32m1_b32(__VA_ARGS__) -#define vmsne_vx_u32m1_b32(...) __riscv_vmsne_vx_u32m1_b32(__VA_ARGS__) -#define vmsne_vv_u32m2_b16(...) __riscv_vmsne_vv_u32m2_b16(__VA_ARGS__) -#define vmsne_vx_u32m2_b16(...) __riscv_vmsne_vx_u32m2_b16(__VA_ARGS__) -#define vmsne_vv_u32m4_b8(...) __riscv_vmsne_vv_u32m4_b8(__VA_ARGS__) -#define vmsne_vx_u32m4_b8(...) __riscv_vmsne_vx_u32m4_b8(__VA_ARGS__) -#define vmsne_vv_u32m8_b4(...) __riscv_vmsne_vv_u32m8_b4(__VA_ARGS__) -#define vmsne_vx_u32m8_b4(...) __riscv_vmsne_vx_u32m8_b4(__VA_ARGS__) -#define vmsne_vv_u64m1_b64(...) __riscv_vmsne_vv_u64m1_b64(__VA_ARGS__) -#define vmsne_vx_u64m1_b64(...) __riscv_vmsne_vx_u64m1_b64(__VA_ARGS__) -#define vmsne_vv_u64m2_b32(...) __riscv_vmsne_vv_u64m2_b32(__VA_ARGS__) -#define vmsne_vx_u64m2_b32(...) __riscv_vmsne_vx_u64m2_b32(__VA_ARGS__) -#define vmsne_vv_u64m4_b16(...) __riscv_vmsne_vv_u64m4_b16(__VA_ARGS__) -#define vmsne_vx_u64m4_b16(...) __riscv_vmsne_vx_u64m4_b16(__VA_ARGS__) -#define vmsne_vv_u64m8_b8(...) __riscv_vmsne_vv_u64m8_b8(__VA_ARGS__) -#define vmsne_vx_u64m8_b8(...) __riscv_vmsne_vx_u64m8_b8(__VA_ARGS__) -#define vmsltu_vv_u8mf8_b64(...) __riscv_vmsltu_vv_u8mf8_b64(__VA_ARGS__) -#define vmsltu_vx_u8mf8_b64(...) __riscv_vmsltu_vx_u8mf8_b64(__VA_ARGS__) -#define vmsltu_vv_u8mf4_b32(...) __riscv_vmsltu_vv_u8mf4_b32(__VA_ARGS__) -#define vmsltu_vx_u8mf4_b32(...) __riscv_vmsltu_vx_u8mf4_b32(__VA_ARGS__) -#define vmsltu_vv_u8mf2_b16(...) __riscv_vmsltu_vv_u8mf2_b16(__VA_ARGS__) -#define vmsltu_vx_u8mf2_b16(...) __riscv_vmsltu_vx_u8mf2_b16(__VA_ARGS__) -#define vmsltu_vv_u8m1_b8(...) __riscv_vmsltu_vv_u8m1_b8(__VA_ARGS__) -#define vmsltu_vx_u8m1_b8(...) __riscv_vmsltu_vx_u8m1_b8(__VA_ARGS__) -#define vmsltu_vv_u8m2_b4(...) __riscv_vmsltu_vv_u8m2_b4(__VA_ARGS__) -#define vmsltu_vx_u8m2_b4(...) __riscv_vmsltu_vx_u8m2_b4(__VA_ARGS__) -#define vmsltu_vv_u8m4_b2(...) __riscv_vmsltu_vv_u8m4_b2(__VA_ARGS__) -#define vmsltu_vx_u8m4_b2(...) __riscv_vmsltu_vx_u8m4_b2(__VA_ARGS__) -#define vmsltu_vv_u8m8_b1(...) __riscv_vmsltu_vv_u8m8_b1(__VA_ARGS__) -#define vmsltu_vx_u8m8_b1(...) __riscv_vmsltu_vx_u8m8_b1(__VA_ARGS__) -#define vmsltu_vv_u16mf4_b64(...) __riscv_vmsltu_vv_u16mf4_b64(__VA_ARGS__) -#define vmsltu_vx_u16mf4_b64(...) __riscv_vmsltu_vx_u16mf4_b64(__VA_ARGS__) -#define vmsltu_vv_u16mf2_b32(...) __riscv_vmsltu_vv_u16mf2_b32(__VA_ARGS__) -#define vmsltu_vx_u16mf2_b32(...) __riscv_vmsltu_vx_u16mf2_b32(__VA_ARGS__) -#define vmsltu_vv_u16m1_b16(...) __riscv_vmsltu_vv_u16m1_b16(__VA_ARGS__) -#define vmsltu_vx_u16m1_b16(...) __riscv_vmsltu_vx_u16m1_b16(__VA_ARGS__) -#define vmsltu_vv_u16m2_b8(...) __riscv_vmsltu_vv_u16m2_b8(__VA_ARGS__) -#define vmsltu_vx_u16m2_b8(...) __riscv_vmsltu_vx_u16m2_b8(__VA_ARGS__) -#define vmsltu_vv_u16m4_b4(...) __riscv_vmsltu_vv_u16m4_b4(__VA_ARGS__) -#define vmsltu_vx_u16m4_b4(...) __riscv_vmsltu_vx_u16m4_b4(__VA_ARGS__) -#define vmsltu_vv_u16m8_b2(...) __riscv_vmsltu_vv_u16m8_b2(__VA_ARGS__) -#define vmsltu_vx_u16m8_b2(...) __riscv_vmsltu_vx_u16m8_b2(__VA_ARGS__) -#define vmsltu_vv_u32mf2_b64(...) __riscv_vmsltu_vv_u32mf2_b64(__VA_ARGS__) -#define vmsltu_vx_u32mf2_b64(...) __riscv_vmsltu_vx_u32mf2_b64(__VA_ARGS__) -#define vmsltu_vv_u32m1_b32(...) __riscv_vmsltu_vv_u32m1_b32(__VA_ARGS__) -#define vmsltu_vx_u32m1_b32(...) __riscv_vmsltu_vx_u32m1_b32(__VA_ARGS__) -#define vmsltu_vv_u32m2_b16(...) __riscv_vmsltu_vv_u32m2_b16(__VA_ARGS__) -#define vmsltu_vx_u32m2_b16(...) __riscv_vmsltu_vx_u32m2_b16(__VA_ARGS__) -#define vmsltu_vv_u32m4_b8(...) __riscv_vmsltu_vv_u32m4_b8(__VA_ARGS__) -#define vmsltu_vx_u32m4_b8(...) __riscv_vmsltu_vx_u32m4_b8(__VA_ARGS__) -#define vmsltu_vv_u32m8_b4(...) __riscv_vmsltu_vv_u32m8_b4(__VA_ARGS__) -#define vmsltu_vx_u32m8_b4(...) __riscv_vmsltu_vx_u32m8_b4(__VA_ARGS__) -#define vmsltu_vv_u64m1_b64(...) __riscv_vmsltu_vv_u64m1_b64(__VA_ARGS__) -#define vmsltu_vx_u64m1_b64(...) __riscv_vmsltu_vx_u64m1_b64(__VA_ARGS__) -#define vmsltu_vv_u64m2_b32(...) __riscv_vmsltu_vv_u64m2_b32(__VA_ARGS__) -#define vmsltu_vx_u64m2_b32(...) __riscv_vmsltu_vx_u64m2_b32(__VA_ARGS__) -#define vmsltu_vv_u64m4_b16(...) __riscv_vmsltu_vv_u64m4_b16(__VA_ARGS__) -#define vmsltu_vx_u64m4_b16(...) __riscv_vmsltu_vx_u64m4_b16(__VA_ARGS__) -#define vmsltu_vv_u64m8_b8(...) __riscv_vmsltu_vv_u64m8_b8(__VA_ARGS__) -#define vmsltu_vx_u64m8_b8(...) __riscv_vmsltu_vx_u64m8_b8(__VA_ARGS__) -#define vmsleu_vv_u8mf8_b64(...) __riscv_vmsleu_vv_u8mf8_b64(__VA_ARGS__) -#define vmsleu_vx_u8mf8_b64(...) __riscv_vmsleu_vx_u8mf8_b64(__VA_ARGS__) -#define vmsleu_vv_u8mf4_b32(...) __riscv_vmsleu_vv_u8mf4_b32(__VA_ARGS__) -#define vmsleu_vx_u8mf4_b32(...) __riscv_vmsleu_vx_u8mf4_b32(__VA_ARGS__) -#define vmsleu_vv_u8mf2_b16(...) __riscv_vmsleu_vv_u8mf2_b16(__VA_ARGS__) -#define vmsleu_vx_u8mf2_b16(...) __riscv_vmsleu_vx_u8mf2_b16(__VA_ARGS__) -#define vmsleu_vv_u8m1_b8(...) __riscv_vmsleu_vv_u8m1_b8(__VA_ARGS__) -#define vmsleu_vx_u8m1_b8(...) __riscv_vmsleu_vx_u8m1_b8(__VA_ARGS__) -#define vmsleu_vv_u8m2_b4(...) __riscv_vmsleu_vv_u8m2_b4(__VA_ARGS__) -#define vmsleu_vx_u8m2_b4(...) __riscv_vmsleu_vx_u8m2_b4(__VA_ARGS__) -#define vmsleu_vv_u8m4_b2(...) __riscv_vmsleu_vv_u8m4_b2(__VA_ARGS__) -#define vmsleu_vx_u8m4_b2(...) __riscv_vmsleu_vx_u8m4_b2(__VA_ARGS__) -#define vmsleu_vv_u8m8_b1(...) __riscv_vmsleu_vv_u8m8_b1(__VA_ARGS__) -#define vmsleu_vx_u8m8_b1(...) __riscv_vmsleu_vx_u8m8_b1(__VA_ARGS__) -#define vmsleu_vv_u16mf4_b64(...) __riscv_vmsleu_vv_u16mf4_b64(__VA_ARGS__) -#define vmsleu_vx_u16mf4_b64(...) __riscv_vmsleu_vx_u16mf4_b64(__VA_ARGS__) -#define vmsleu_vv_u16mf2_b32(...) __riscv_vmsleu_vv_u16mf2_b32(__VA_ARGS__) -#define vmsleu_vx_u16mf2_b32(...) __riscv_vmsleu_vx_u16mf2_b32(__VA_ARGS__) -#define vmsleu_vv_u16m1_b16(...) __riscv_vmsleu_vv_u16m1_b16(__VA_ARGS__) -#define vmsleu_vx_u16m1_b16(...) __riscv_vmsleu_vx_u16m1_b16(__VA_ARGS__) -#define vmsleu_vv_u16m2_b8(...) __riscv_vmsleu_vv_u16m2_b8(__VA_ARGS__) -#define vmsleu_vx_u16m2_b8(...) __riscv_vmsleu_vx_u16m2_b8(__VA_ARGS__) -#define vmsleu_vv_u16m4_b4(...) __riscv_vmsleu_vv_u16m4_b4(__VA_ARGS__) -#define vmsleu_vx_u16m4_b4(...) __riscv_vmsleu_vx_u16m4_b4(__VA_ARGS__) -#define vmsleu_vv_u16m8_b2(...) __riscv_vmsleu_vv_u16m8_b2(__VA_ARGS__) -#define vmsleu_vx_u16m8_b2(...) __riscv_vmsleu_vx_u16m8_b2(__VA_ARGS__) -#define vmsleu_vv_u32mf2_b64(...) __riscv_vmsleu_vv_u32mf2_b64(__VA_ARGS__) -#define vmsleu_vx_u32mf2_b64(...) __riscv_vmsleu_vx_u32mf2_b64(__VA_ARGS__) -#define vmsleu_vv_u32m1_b32(...) __riscv_vmsleu_vv_u32m1_b32(__VA_ARGS__) -#define vmsleu_vx_u32m1_b32(...) __riscv_vmsleu_vx_u32m1_b32(__VA_ARGS__) -#define vmsleu_vv_u32m2_b16(...) __riscv_vmsleu_vv_u32m2_b16(__VA_ARGS__) -#define vmsleu_vx_u32m2_b16(...) __riscv_vmsleu_vx_u32m2_b16(__VA_ARGS__) -#define vmsleu_vv_u32m4_b8(...) __riscv_vmsleu_vv_u32m4_b8(__VA_ARGS__) -#define vmsleu_vx_u32m4_b8(...) __riscv_vmsleu_vx_u32m4_b8(__VA_ARGS__) -#define vmsleu_vv_u32m8_b4(...) __riscv_vmsleu_vv_u32m8_b4(__VA_ARGS__) -#define vmsleu_vx_u32m8_b4(...) __riscv_vmsleu_vx_u32m8_b4(__VA_ARGS__) -#define vmsleu_vv_u64m1_b64(...) __riscv_vmsleu_vv_u64m1_b64(__VA_ARGS__) -#define vmsleu_vx_u64m1_b64(...) __riscv_vmsleu_vx_u64m1_b64(__VA_ARGS__) -#define vmsleu_vv_u64m2_b32(...) __riscv_vmsleu_vv_u64m2_b32(__VA_ARGS__) -#define vmsleu_vx_u64m2_b32(...) __riscv_vmsleu_vx_u64m2_b32(__VA_ARGS__) -#define vmsleu_vv_u64m4_b16(...) __riscv_vmsleu_vv_u64m4_b16(__VA_ARGS__) -#define vmsleu_vx_u64m4_b16(...) __riscv_vmsleu_vx_u64m4_b16(__VA_ARGS__) -#define vmsleu_vv_u64m8_b8(...) __riscv_vmsleu_vv_u64m8_b8(__VA_ARGS__) -#define vmsleu_vx_u64m8_b8(...) __riscv_vmsleu_vx_u64m8_b8(__VA_ARGS__) -#define vmsgtu_vv_u8mf8_b64(...) __riscv_vmsgtu_vv_u8mf8_b64(__VA_ARGS__) -#define vmsgtu_vx_u8mf8_b64(...) __riscv_vmsgtu_vx_u8mf8_b64(__VA_ARGS__) -#define vmsgtu_vv_u8mf4_b32(...) __riscv_vmsgtu_vv_u8mf4_b32(__VA_ARGS__) -#define vmsgtu_vx_u8mf4_b32(...) __riscv_vmsgtu_vx_u8mf4_b32(__VA_ARGS__) -#define vmsgtu_vv_u8mf2_b16(...) __riscv_vmsgtu_vv_u8mf2_b16(__VA_ARGS__) -#define vmsgtu_vx_u8mf2_b16(...) __riscv_vmsgtu_vx_u8mf2_b16(__VA_ARGS__) -#define vmsgtu_vv_u8m1_b8(...) __riscv_vmsgtu_vv_u8m1_b8(__VA_ARGS__) -#define vmsgtu_vx_u8m1_b8(...) __riscv_vmsgtu_vx_u8m1_b8(__VA_ARGS__) -#define vmsgtu_vv_u8m2_b4(...) __riscv_vmsgtu_vv_u8m2_b4(__VA_ARGS__) -#define vmsgtu_vx_u8m2_b4(...) __riscv_vmsgtu_vx_u8m2_b4(__VA_ARGS__) -#define vmsgtu_vv_u8m4_b2(...) __riscv_vmsgtu_vv_u8m4_b2(__VA_ARGS__) -#define vmsgtu_vx_u8m4_b2(...) __riscv_vmsgtu_vx_u8m4_b2(__VA_ARGS__) -#define vmsgtu_vv_u8m8_b1(...) __riscv_vmsgtu_vv_u8m8_b1(__VA_ARGS__) -#define vmsgtu_vx_u8m8_b1(...) __riscv_vmsgtu_vx_u8m8_b1(__VA_ARGS__) -#define vmsgtu_vv_u16mf4_b64(...) __riscv_vmsgtu_vv_u16mf4_b64(__VA_ARGS__) -#define vmsgtu_vx_u16mf4_b64(...) __riscv_vmsgtu_vx_u16mf4_b64(__VA_ARGS__) -#define vmsgtu_vv_u16mf2_b32(...) __riscv_vmsgtu_vv_u16mf2_b32(__VA_ARGS__) -#define vmsgtu_vx_u16mf2_b32(...) __riscv_vmsgtu_vx_u16mf2_b32(__VA_ARGS__) -#define vmsgtu_vv_u16m1_b16(...) __riscv_vmsgtu_vv_u16m1_b16(__VA_ARGS__) -#define vmsgtu_vx_u16m1_b16(...) __riscv_vmsgtu_vx_u16m1_b16(__VA_ARGS__) -#define vmsgtu_vv_u16m2_b8(...) __riscv_vmsgtu_vv_u16m2_b8(__VA_ARGS__) -#define vmsgtu_vx_u16m2_b8(...) __riscv_vmsgtu_vx_u16m2_b8(__VA_ARGS__) -#define vmsgtu_vv_u16m4_b4(...) __riscv_vmsgtu_vv_u16m4_b4(__VA_ARGS__) -#define vmsgtu_vx_u16m4_b4(...) __riscv_vmsgtu_vx_u16m4_b4(__VA_ARGS__) -#define vmsgtu_vv_u16m8_b2(...) __riscv_vmsgtu_vv_u16m8_b2(__VA_ARGS__) -#define vmsgtu_vx_u16m8_b2(...) __riscv_vmsgtu_vx_u16m8_b2(__VA_ARGS__) -#define vmsgtu_vv_u32mf2_b64(...) __riscv_vmsgtu_vv_u32mf2_b64(__VA_ARGS__) -#define vmsgtu_vx_u32mf2_b64(...) __riscv_vmsgtu_vx_u32mf2_b64(__VA_ARGS__) -#define vmsgtu_vv_u32m1_b32(...) __riscv_vmsgtu_vv_u32m1_b32(__VA_ARGS__) -#define vmsgtu_vx_u32m1_b32(...) __riscv_vmsgtu_vx_u32m1_b32(__VA_ARGS__) -#define vmsgtu_vv_u32m2_b16(...) __riscv_vmsgtu_vv_u32m2_b16(__VA_ARGS__) -#define vmsgtu_vx_u32m2_b16(...) __riscv_vmsgtu_vx_u32m2_b16(__VA_ARGS__) -#define vmsgtu_vv_u32m4_b8(...) __riscv_vmsgtu_vv_u32m4_b8(__VA_ARGS__) -#define vmsgtu_vx_u32m4_b8(...) __riscv_vmsgtu_vx_u32m4_b8(__VA_ARGS__) -#define vmsgtu_vv_u32m8_b4(...) __riscv_vmsgtu_vv_u32m8_b4(__VA_ARGS__) -#define vmsgtu_vx_u32m8_b4(...) __riscv_vmsgtu_vx_u32m8_b4(__VA_ARGS__) -#define vmsgtu_vv_u64m1_b64(...) __riscv_vmsgtu_vv_u64m1_b64(__VA_ARGS__) -#define vmsgtu_vx_u64m1_b64(...) __riscv_vmsgtu_vx_u64m1_b64(__VA_ARGS__) -#define vmsgtu_vv_u64m2_b32(...) __riscv_vmsgtu_vv_u64m2_b32(__VA_ARGS__) -#define vmsgtu_vx_u64m2_b32(...) __riscv_vmsgtu_vx_u64m2_b32(__VA_ARGS__) -#define vmsgtu_vv_u64m4_b16(...) __riscv_vmsgtu_vv_u64m4_b16(__VA_ARGS__) -#define vmsgtu_vx_u64m4_b16(...) __riscv_vmsgtu_vx_u64m4_b16(__VA_ARGS__) -#define vmsgtu_vv_u64m8_b8(...) __riscv_vmsgtu_vv_u64m8_b8(__VA_ARGS__) -#define vmsgtu_vx_u64m8_b8(...) __riscv_vmsgtu_vx_u64m8_b8(__VA_ARGS__) -#define vmsgeu_vv_u8mf8_b64(...) __riscv_vmsgeu_vv_u8mf8_b64(__VA_ARGS__) -#define vmsgeu_vx_u8mf8_b64(...) __riscv_vmsgeu_vx_u8mf8_b64(__VA_ARGS__) -#define vmsgeu_vv_u8mf4_b32(...) __riscv_vmsgeu_vv_u8mf4_b32(__VA_ARGS__) -#define vmsgeu_vx_u8mf4_b32(...) __riscv_vmsgeu_vx_u8mf4_b32(__VA_ARGS__) -#define vmsgeu_vv_u8mf2_b16(...) __riscv_vmsgeu_vv_u8mf2_b16(__VA_ARGS__) -#define vmsgeu_vx_u8mf2_b16(...) __riscv_vmsgeu_vx_u8mf2_b16(__VA_ARGS__) -#define vmsgeu_vv_u8m1_b8(...) __riscv_vmsgeu_vv_u8m1_b8(__VA_ARGS__) -#define vmsgeu_vx_u8m1_b8(...) __riscv_vmsgeu_vx_u8m1_b8(__VA_ARGS__) -#define vmsgeu_vv_u8m2_b4(...) __riscv_vmsgeu_vv_u8m2_b4(__VA_ARGS__) -#define vmsgeu_vx_u8m2_b4(...) __riscv_vmsgeu_vx_u8m2_b4(__VA_ARGS__) -#define vmsgeu_vv_u8m4_b2(...) __riscv_vmsgeu_vv_u8m4_b2(__VA_ARGS__) -#define vmsgeu_vx_u8m4_b2(...) __riscv_vmsgeu_vx_u8m4_b2(__VA_ARGS__) -#define vmsgeu_vv_u8m8_b1(...) __riscv_vmsgeu_vv_u8m8_b1(__VA_ARGS__) -#define vmsgeu_vx_u8m8_b1(...) __riscv_vmsgeu_vx_u8m8_b1(__VA_ARGS__) -#define vmsgeu_vv_u16mf4_b64(...) __riscv_vmsgeu_vv_u16mf4_b64(__VA_ARGS__) -#define vmsgeu_vx_u16mf4_b64(...) __riscv_vmsgeu_vx_u16mf4_b64(__VA_ARGS__) -#define vmsgeu_vv_u16mf2_b32(...) __riscv_vmsgeu_vv_u16mf2_b32(__VA_ARGS__) -#define vmsgeu_vx_u16mf2_b32(...) __riscv_vmsgeu_vx_u16mf2_b32(__VA_ARGS__) -#define vmsgeu_vv_u16m1_b16(...) __riscv_vmsgeu_vv_u16m1_b16(__VA_ARGS__) -#define vmsgeu_vx_u16m1_b16(...) __riscv_vmsgeu_vx_u16m1_b16(__VA_ARGS__) -#define vmsgeu_vv_u16m2_b8(...) __riscv_vmsgeu_vv_u16m2_b8(__VA_ARGS__) -#define vmsgeu_vx_u16m2_b8(...) __riscv_vmsgeu_vx_u16m2_b8(__VA_ARGS__) -#define vmsgeu_vv_u16m4_b4(...) __riscv_vmsgeu_vv_u16m4_b4(__VA_ARGS__) -#define vmsgeu_vx_u16m4_b4(...) __riscv_vmsgeu_vx_u16m4_b4(__VA_ARGS__) -#define vmsgeu_vv_u16m8_b2(...) __riscv_vmsgeu_vv_u16m8_b2(__VA_ARGS__) -#define vmsgeu_vx_u16m8_b2(...) __riscv_vmsgeu_vx_u16m8_b2(__VA_ARGS__) -#define vmsgeu_vv_u32mf2_b64(...) __riscv_vmsgeu_vv_u32mf2_b64(__VA_ARGS__) -#define vmsgeu_vx_u32mf2_b64(...) __riscv_vmsgeu_vx_u32mf2_b64(__VA_ARGS__) -#define vmsgeu_vv_u32m1_b32(...) __riscv_vmsgeu_vv_u32m1_b32(__VA_ARGS__) -#define vmsgeu_vx_u32m1_b32(...) __riscv_vmsgeu_vx_u32m1_b32(__VA_ARGS__) -#define vmsgeu_vv_u32m2_b16(...) __riscv_vmsgeu_vv_u32m2_b16(__VA_ARGS__) -#define vmsgeu_vx_u32m2_b16(...) __riscv_vmsgeu_vx_u32m2_b16(__VA_ARGS__) -#define vmsgeu_vv_u32m4_b8(...) __riscv_vmsgeu_vv_u32m4_b8(__VA_ARGS__) -#define vmsgeu_vx_u32m4_b8(...) __riscv_vmsgeu_vx_u32m4_b8(__VA_ARGS__) -#define vmsgeu_vv_u32m8_b4(...) __riscv_vmsgeu_vv_u32m8_b4(__VA_ARGS__) -#define vmsgeu_vx_u32m8_b4(...) __riscv_vmsgeu_vx_u32m8_b4(__VA_ARGS__) -#define vmsgeu_vv_u64m1_b64(...) __riscv_vmsgeu_vv_u64m1_b64(__VA_ARGS__) -#define vmsgeu_vx_u64m1_b64(...) __riscv_vmsgeu_vx_u64m1_b64(__VA_ARGS__) -#define vmsgeu_vv_u64m2_b32(...) __riscv_vmsgeu_vv_u64m2_b32(__VA_ARGS__) -#define vmsgeu_vx_u64m2_b32(...) __riscv_vmsgeu_vx_u64m2_b32(__VA_ARGS__) -#define vmsgeu_vv_u64m4_b16(...) __riscv_vmsgeu_vv_u64m4_b16(__VA_ARGS__) -#define vmsgeu_vx_u64m4_b16(...) __riscv_vmsgeu_vx_u64m4_b16(__VA_ARGS__) -#define vmsgeu_vv_u64m8_b8(...) __riscv_vmsgeu_vv_u64m8_b8(__VA_ARGS__) -#define vmsgeu_vx_u64m8_b8(...) __riscv_vmsgeu_vx_u64m8_b8(__VA_ARGS__) -// masked functions -#define vmseq_vv_i8mf8_b64_m(...) __riscv_vmseq_vv_i8mf8_b64_mu(__VA_ARGS__) -#define vmseq_vx_i8mf8_b64_m(...) __riscv_vmseq_vx_i8mf8_b64_mu(__VA_ARGS__) -#define vmseq_vv_i8mf4_b32_m(...) __riscv_vmseq_vv_i8mf4_b32_mu(__VA_ARGS__) -#define vmseq_vx_i8mf4_b32_m(...) __riscv_vmseq_vx_i8mf4_b32_mu(__VA_ARGS__) -#define vmseq_vv_i8mf2_b16_m(...) __riscv_vmseq_vv_i8mf2_b16_mu(__VA_ARGS__) -#define vmseq_vx_i8mf2_b16_m(...) __riscv_vmseq_vx_i8mf2_b16_mu(__VA_ARGS__) -#define vmseq_vv_i8m1_b8_m(...) __riscv_vmseq_vv_i8m1_b8_mu(__VA_ARGS__) -#define vmseq_vx_i8m1_b8_m(...) __riscv_vmseq_vx_i8m1_b8_mu(__VA_ARGS__) -#define vmseq_vv_i8m2_b4_m(...) __riscv_vmseq_vv_i8m2_b4_mu(__VA_ARGS__) -#define vmseq_vx_i8m2_b4_m(...) __riscv_vmseq_vx_i8m2_b4_mu(__VA_ARGS__) -#define vmseq_vv_i8m4_b2_m(...) __riscv_vmseq_vv_i8m4_b2_mu(__VA_ARGS__) -#define vmseq_vx_i8m4_b2_m(...) __riscv_vmseq_vx_i8m4_b2_mu(__VA_ARGS__) -#define vmseq_vv_i8m8_b1_m(...) __riscv_vmseq_vv_i8m8_b1_mu(__VA_ARGS__) -#define vmseq_vx_i8m8_b1_m(...) __riscv_vmseq_vx_i8m8_b1_mu(__VA_ARGS__) -#define vmseq_vv_i16mf4_b64_m(...) __riscv_vmseq_vv_i16mf4_b64_mu(__VA_ARGS__) -#define vmseq_vx_i16mf4_b64_m(...) __riscv_vmseq_vx_i16mf4_b64_mu(__VA_ARGS__) -#define vmseq_vv_i16mf2_b32_m(...) __riscv_vmseq_vv_i16mf2_b32_mu(__VA_ARGS__) -#define vmseq_vx_i16mf2_b32_m(...) __riscv_vmseq_vx_i16mf2_b32_mu(__VA_ARGS__) -#define vmseq_vv_i16m1_b16_m(...) __riscv_vmseq_vv_i16m1_b16_mu(__VA_ARGS__) -#define vmseq_vx_i16m1_b16_m(...) __riscv_vmseq_vx_i16m1_b16_mu(__VA_ARGS__) -#define vmseq_vv_i16m2_b8_m(...) __riscv_vmseq_vv_i16m2_b8_mu(__VA_ARGS__) -#define vmseq_vx_i16m2_b8_m(...) __riscv_vmseq_vx_i16m2_b8_mu(__VA_ARGS__) -#define vmseq_vv_i16m4_b4_m(...) __riscv_vmseq_vv_i16m4_b4_mu(__VA_ARGS__) -#define vmseq_vx_i16m4_b4_m(...) __riscv_vmseq_vx_i16m4_b4_mu(__VA_ARGS__) -#define vmseq_vv_i16m8_b2_m(...) __riscv_vmseq_vv_i16m8_b2_mu(__VA_ARGS__) -#define vmseq_vx_i16m8_b2_m(...) __riscv_vmseq_vx_i16m8_b2_mu(__VA_ARGS__) -#define vmseq_vv_i32mf2_b64_m(...) __riscv_vmseq_vv_i32mf2_b64_mu(__VA_ARGS__) -#define vmseq_vx_i32mf2_b64_m(...) __riscv_vmseq_vx_i32mf2_b64_mu(__VA_ARGS__) -#define vmseq_vv_i32m1_b32_m(...) __riscv_vmseq_vv_i32m1_b32_mu(__VA_ARGS__) -#define vmseq_vx_i32m1_b32_m(...) __riscv_vmseq_vx_i32m1_b32_mu(__VA_ARGS__) -#define vmseq_vv_i32m2_b16_m(...) __riscv_vmseq_vv_i32m2_b16_mu(__VA_ARGS__) -#define vmseq_vx_i32m2_b16_m(...) __riscv_vmseq_vx_i32m2_b16_mu(__VA_ARGS__) -#define vmseq_vv_i32m4_b8_m(...) __riscv_vmseq_vv_i32m4_b8_mu(__VA_ARGS__) -#define vmseq_vx_i32m4_b8_m(...) __riscv_vmseq_vx_i32m4_b8_mu(__VA_ARGS__) -#define vmseq_vv_i32m8_b4_m(...) __riscv_vmseq_vv_i32m8_b4_mu(__VA_ARGS__) -#define vmseq_vx_i32m8_b4_m(...) __riscv_vmseq_vx_i32m8_b4_mu(__VA_ARGS__) -#define vmseq_vv_i64m1_b64_m(...) __riscv_vmseq_vv_i64m1_b64_mu(__VA_ARGS__) -#define vmseq_vx_i64m1_b64_m(...) __riscv_vmseq_vx_i64m1_b64_mu(__VA_ARGS__) -#define vmseq_vv_i64m2_b32_m(...) __riscv_vmseq_vv_i64m2_b32_mu(__VA_ARGS__) -#define vmseq_vx_i64m2_b32_m(...) __riscv_vmseq_vx_i64m2_b32_mu(__VA_ARGS__) -#define vmseq_vv_i64m4_b16_m(...) __riscv_vmseq_vv_i64m4_b16_mu(__VA_ARGS__) -#define vmseq_vx_i64m4_b16_m(...) __riscv_vmseq_vx_i64m4_b16_mu(__VA_ARGS__) -#define vmseq_vv_i64m8_b8_m(...) __riscv_vmseq_vv_i64m8_b8_mu(__VA_ARGS__) -#define vmseq_vx_i64m8_b8_m(...) __riscv_vmseq_vx_i64m8_b8_mu(__VA_ARGS__) -#define vmsne_vv_i8mf8_b64_m(...) __riscv_vmsne_vv_i8mf8_b64_mu(__VA_ARGS__) -#define vmsne_vx_i8mf8_b64_m(...) __riscv_vmsne_vx_i8mf8_b64_mu(__VA_ARGS__) -#define vmsne_vv_i8mf4_b32_m(...) __riscv_vmsne_vv_i8mf4_b32_mu(__VA_ARGS__) -#define vmsne_vx_i8mf4_b32_m(...) __riscv_vmsne_vx_i8mf4_b32_mu(__VA_ARGS__) -#define vmsne_vv_i8mf2_b16_m(...) __riscv_vmsne_vv_i8mf2_b16_mu(__VA_ARGS__) -#define vmsne_vx_i8mf2_b16_m(...) __riscv_vmsne_vx_i8mf2_b16_mu(__VA_ARGS__) -#define vmsne_vv_i8m1_b8_m(...) __riscv_vmsne_vv_i8m1_b8_mu(__VA_ARGS__) -#define vmsne_vx_i8m1_b8_m(...) __riscv_vmsne_vx_i8m1_b8_mu(__VA_ARGS__) -#define vmsne_vv_i8m2_b4_m(...) __riscv_vmsne_vv_i8m2_b4_mu(__VA_ARGS__) -#define vmsne_vx_i8m2_b4_m(...) __riscv_vmsne_vx_i8m2_b4_mu(__VA_ARGS__) -#define vmsne_vv_i8m4_b2_m(...) __riscv_vmsne_vv_i8m4_b2_mu(__VA_ARGS__) -#define vmsne_vx_i8m4_b2_m(...) __riscv_vmsne_vx_i8m4_b2_mu(__VA_ARGS__) -#define vmsne_vv_i8m8_b1_m(...) __riscv_vmsne_vv_i8m8_b1_mu(__VA_ARGS__) -#define vmsne_vx_i8m8_b1_m(...) __riscv_vmsne_vx_i8m8_b1_mu(__VA_ARGS__) -#define vmsne_vv_i16mf4_b64_m(...) __riscv_vmsne_vv_i16mf4_b64_mu(__VA_ARGS__) -#define vmsne_vx_i16mf4_b64_m(...) __riscv_vmsne_vx_i16mf4_b64_mu(__VA_ARGS__) -#define vmsne_vv_i16mf2_b32_m(...) __riscv_vmsne_vv_i16mf2_b32_mu(__VA_ARGS__) -#define vmsne_vx_i16mf2_b32_m(...) __riscv_vmsne_vx_i16mf2_b32_mu(__VA_ARGS__) -#define vmsne_vv_i16m1_b16_m(...) __riscv_vmsne_vv_i16m1_b16_mu(__VA_ARGS__) -#define vmsne_vx_i16m1_b16_m(...) __riscv_vmsne_vx_i16m1_b16_mu(__VA_ARGS__) -#define vmsne_vv_i16m2_b8_m(...) __riscv_vmsne_vv_i16m2_b8_mu(__VA_ARGS__) -#define vmsne_vx_i16m2_b8_m(...) __riscv_vmsne_vx_i16m2_b8_mu(__VA_ARGS__) -#define vmsne_vv_i16m4_b4_m(...) __riscv_vmsne_vv_i16m4_b4_mu(__VA_ARGS__) -#define vmsne_vx_i16m4_b4_m(...) __riscv_vmsne_vx_i16m4_b4_mu(__VA_ARGS__) -#define vmsne_vv_i16m8_b2_m(...) __riscv_vmsne_vv_i16m8_b2_mu(__VA_ARGS__) -#define vmsne_vx_i16m8_b2_m(...) __riscv_vmsne_vx_i16m8_b2_mu(__VA_ARGS__) -#define vmsne_vv_i32mf2_b64_m(...) __riscv_vmsne_vv_i32mf2_b64_mu(__VA_ARGS__) -#define vmsne_vx_i32mf2_b64_m(...) __riscv_vmsne_vx_i32mf2_b64_mu(__VA_ARGS__) -#define vmsne_vv_i32m1_b32_m(...) __riscv_vmsne_vv_i32m1_b32_mu(__VA_ARGS__) -#define vmsne_vx_i32m1_b32_m(...) __riscv_vmsne_vx_i32m1_b32_mu(__VA_ARGS__) -#define vmsne_vv_i32m2_b16_m(...) __riscv_vmsne_vv_i32m2_b16_mu(__VA_ARGS__) -#define vmsne_vx_i32m2_b16_m(...) __riscv_vmsne_vx_i32m2_b16_mu(__VA_ARGS__) -#define vmsne_vv_i32m4_b8_m(...) __riscv_vmsne_vv_i32m4_b8_mu(__VA_ARGS__) -#define vmsne_vx_i32m4_b8_m(...) __riscv_vmsne_vx_i32m4_b8_mu(__VA_ARGS__) -#define vmsne_vv_i32m8_b4_m(...) __riscv_vmsne_vv_i32m8_b4_mu(__VA_ARGS__) -#define vmsne_vx_i32m8_b4_m(...) __riscv_vmsne_vx_i32m8_b4_mu(__VA_ARGS__) -#define vmsne_vv_i64m1_b64_m(...) __riscv_vmsne_vv_i64m1_b64_mu(__VA_ARGS__) -#define vmsne_vx_i64m1_b64_m(...) __riscv_vmsne_vx_i64m1_b64_mu(__VA_ARGS__) -#define vmsne_vv_i64m2_b32_m(...) __riscv_vmsne_vv_i64m2_b32_mu(__VA_ARGS__) -#define vmsne_vx_i64m2_b32_m(...) __riscv_vmsne_vx_i64m2_b32_mu(__VA_ARGS__) -#define vmsne_vv_i64m4_b16_m(...) __riscv_vmsne_vv_i64m4_b16_mu(__VA_ARGS__) -#define vmsne_vx_i64m4_b16_m(...) __riscv_vmsne_vx_i64m4_b16_mu(__VA_ARGS__) -#define vmsne_vv_i64m8_b8_m(...) __riscv_vmsne_vv_i64m8_b8_mu(__VA_ARGS__) -#define vmsne_vx_i64m8_b8_m(...) __riscv_vmsne_vx_i64m8_b8_mu(__VA_ARGS__) -#define vmslt_vv_i8mf8_b64_m(...) __riscv_vmslt_vv_i8mf8_b64_mu(__VA_ARGS__) -#define vmslt_vx_i8mf8_b64_m(...) __riscv_vmslt_vx_i8mf8_b64_mu(__VA_ARGS__) -#define vmslt_vv_i8mf4_b32_m(...) __riscv_vmslt_vv_i8mf4_b32_mu(__VA_ARGS__) -#define vmslt_vx_i8mf4_b32_m(...) __riscv_vmslt_vx_i8mf4_b32_mu(__VA_ARGS__) -#define vmslt_vv_i8mf2_b16_m(...) __riscv_vmslt_vv_i8mf2_b16_mu(__VA_ARGS__) -#define vmslt_vx_i8mf2_b16_m(...) __riscv_vmslt_vx_i8mf2_b16_mu(__VA_ARGS__) -#define vmslt_vv_i8m1_b8_m(...) __riscv_vmslt_vv_i8m1_b8_mu(__VA_ARGS__) -#define vmslt_vx_i8m1_b8_m(...) __riscv_vmslt_vx_i8m1_b8_mu(__VA_ARGS__) -#define vmslt_vv_i8m2_b4_m(...) __riscv_vmslt_vv_i8m2_b4_mu(__VA_ARGS__) -#define vmslt_vx_i8m2_b4_m(...) __riscv_vmslt_vx_i8m2_b4_mu(__VA_ARGS__) -#define vmslt_vv_i8m4_b2_m(...) __riscv_vmslt_vv_i8m4_b2_mu(__VA_ARGS__) -#define vmslt_vx_i8m4_b2_m(...) __riscv_vmslt_vx_i8m4_b2_mu(__VA_ARGS__) -#define vmslt_vv_i8m8_b1_m(...) __riscv_vmslt_vv_i8m8_b1_mu(__VA_ARGS__) -#define vmslt_vx_i8m8_b1_m(...) __riscv_vmslt_vx_i8m8_b1_mu(__VA_ARGS__) -#define vmslt_vv_i16mf4_b64_m(...) __riscv_vmslt_vv_i16mf4_b64_mu(__VA_ARGS__) -#define vmslt_vx_i16mf4_b64_m(...) __riscv_vmslt_vx_i16mf4_b64_mu(__VA_ARGS__) -#define vmslt_vv_i16mf2_b32_m(...) __riscv_vmslt_vv_i16mf2_b32_mu(__VA_ARGS__) -#define vmslt_vx_i16mf2_b32_m(...) __riscv_vmslt_vx_i16mf2_b32_mu(__VA_ARGS__) -#define vmslt_vv_i16m1_b16_m(...) __riscv_vmslt_vv_i16m1_b16_mu(__VA_ARGS__) -#define vmslt_vx_i16m1_b16_m(...) __riscv_vmslt_vx_i16m1_b16_mu(__VA_ARGS__) -#define vmslt_vv_i16m2_b8_m(...) __riscv_vmslt_vv_i16m2_b8_mu(__VA_ARGS__) -#define vmslt_vx_i16m2_b8_m(...) __riscv_vmslt_vx_i16m2_b8_mu(__VA_ARGS__) -#define vmslt_vv_i16m4_b4_m(...) __riscv_vmslt_vv_i16m4_b4_mu(__VA_ARGS__) -#define vmslt_vx_i16m4_b4_m(...) __riscv_vmslt_vx_i16m4_b4_mu(__VA_ARGS__) -#define vmslt_vv_i16m8_b2_m(...) __riscv_vmslt_vv_i16m8_b2_mu(__VA_ARGS__) -#define vmslt_vx_i16m8_b2_m(...) __riscv_vmslt_vx_i16m8_b2_mu(__VA_ARGS__) -#define vmslt_vv_i32mf2_b64_m(...) __riscv_vmslt_vv_i32mf2_b64_mu(__VA_ARGS__) -#define vmslt_vx_i32mf2_b64_m(...) __riscv_vmslt_vx_i32mf2_b64_mu(__VA_ARGS__) -#define vmslt_vv_i32m1_b32_m(...) __riscv_vmslt_vv_i32m1_b32_mu(__VA_ARGS__) -#define vmslt_vx_i32m1_b32_m(...) __riscv_vmslt_vx_i32m1_b32_mu(__VA_ARGS__) -#define vmslt_vv_i32m2_b16_m(...) __riscv_vmslt_vv_i32m2_b16_mu(__VA_ARGS__) -#define vmslt_vx_i32m2_b16_m(...) __riscv_vmslt_vx_i32m2_b16_mu(__VA_ARGS__) -#define vmslt_vv_i32m4_b8_m(...) __riscv_vmslt_vv_i32m4_b8_mu(__VA_ARGS__) -#define vmslt_vx_i32m4_b8_m(...) __riscv_vmslt_vx_i32m4_b8_mu(__VA_ARGS__) -#define vmslt_vv_i32m8_b4_m(...) __riscv_vmslt_vv_i32m8_b4_mu(__VA_ARGS__) -#define vmslt_vx_i32m8_b4_m(...) __riscv_vmslt_vx_i32m8_b4_mu(__VA_ARGS__) -#define vmslt_vv_i64m1_b64_m(...) __riscv_vmslt_vv_i64m1_b64_mu(__VA_ARGS__) -#define vmslt_vx_i64m1_b64_m(...) __riscv_vmslt_vx_i64m1_b64_mu(__VA_ARGS__) -#define vmslt_vv_i64m2_b32_m(...) __riscv_vmslt_vv_i64m2_b32_mu(__VA_ARGS__) -#define vmslt_vx_i64m2_b32_m(...) __riscv_vmslt_vx_i64m2_b32_mu(__VA_ARGS__) -#define vmslt_vv_i64m4_b16_m(...) __riscv_vmslt_vv_i64m4_b16_mu(__VA_ARGS__) -#define vmslt_vx_i64m4_b16_m(...) __riscv_vmslt_vx_i64m4_b16_mu(__VA_ARGS__) -#define vmslt_vv_i64m8_b8_m(...) __riscv_vmslt_vv_i64m8_b8_mu(__VA_ARGS__) -#define vmslt_vx_i64m8_b8_m(...) __riscv_vmslt_vx_i64m8_b8_mu(__VA_ARGS__) -#define vmsle_vv_i8mf8_b64_m(...) __riscv_vmsle_vv_i8mf8_b64_mu(__VA_ARGS__) -#define vmsle_vx_i8mf8_b64_m(...) __riscv_vmsle_vx_i8mf8_b64_mu(__VA_ARGS__) -#define vmsle_vv_i8mf4_b32_m(...) __riscv_vmsle_vv_i8mf4_b32_mu(__VA_ARGS__) -#define vmsle_vx_i8mf4_b32_m(...) __riscv_vmsle_vx_i8mf4_b32_mu(__VA_ARGS__) -#define vmsle_vv_i8mf2_b16_m(...) __riscv_vmsle_vv_i8mf2_b16_mu(__VA_ARGS__) -#define vmsle_vx_i8mf2_b16_m(...) __riscv_vmsle_vx_i8mf2_b16_mu(__VA_ARGS__) -#define vmsle_vv_i8m1_b8_m(...) __riscv_vmsle_vv_i8m1_b8_mu(__VA_ARGS__) -#define vmsle_vx_i8m1_b8_m(...) __riscv_vmsle_vx_i8m1_b8_mu(__VA_ARGS__) -#define vmsle_vv_i8m2_b4_m(...) __riscv_vmsle_vv_i8m2_b4_mu(__VA_ARGS__) -#define vmsle_vx_i8m2_b4_m(...) __riscv_vmsle_vx_i8m2_b4_mu(__VA_ARGS__) -#define vmsle_vv_i8m4_b2_m(...) __riscv_vmsle_vv_i8m4_b2_mu(__VA_ARGS__) -#define vmsle_vx_i8m4_b2_m(...) __riscv_vmsle_vx_i8m4_b2_mu(__VA_ARGS__) -#define vmsle_vv_i8m8_b1_m(...) __riscv_vmsle_vv_i8m8_b1_mu(__VA_ARGS__) -#define vmsle_vx_i8m8_b1_m(...) __riscv_vmsle_vx_i8m8_b1_mu(__VA_ARGS__) -#define vmsle_vv_i16mf4_b64_m(...) __riscv_vmsle_vv_i16mf4_b64_mu(__VA_ARGS__) -#define vmsle_vx_i16mf4_b64_m(...) __riscv_vmsle_vx_i16mf4_b64_mu(__VA_ARGS__) -#define vmsle_vv_i16mf2_b32_m(...) __riscv_vmsle_vv_i16mf2_b32_mu(__VA_ARGS__) -#define vmsle_vx_i16mf2_b32_m(...) __riscv_vmsle_vx_i16mf2_b32_mu(__VA_ARGS__) -#define vmsle_vv_i16m1_b16_m(...) __riscv_vmsle_vv_i16m1_b16_mu(__VA_ARGS__) -#define vmsle_vx_i16m1_b16_m(...) __riscv_vmsle_vx_i16m1_b16_mu(__VA_ARGS__) -#define vmsle_vv_i16m2_b8_m(...) __riscv_vmsle_vv_i16m2_b8_mu(__VA_ARGS__) -#define vmsle_vx_i16m2_b8_m(...) __riscv_vmsle_vx_i16m2_b8_mu(__VA_ARGS__) -#define vmsle_vv_i16m4_b4_m(...) __riscv_vmsle_vv_i16m4_b4_mu(__VA_ARGS__) -#define vmsle_vx_i16m4_b4_m(...) __riscv_vmsle_vx_i16m4_b4_mu(__VA_ARGS__) -#define vmsle_vv_i16m8_b2_m(...) __riscv_vmsle_vv_i16m8_b2_mu(__VA_ARGS__) -#define vmsle_vx_i16m8_b2_m(...) __riscv_vmsle_vx_i16m8_b2_mu(__VA_ARGS__) -#define vmsle_vv_i32mf2_b64_m(...) __riscv_vmsle_vv_i32mf2_b64_mu(__VA_ARGS__) -#define vmsle_vx_i32mf2_b64_m(...) __riscv_vmsle_vx_i32mf2_b64_mu(__VA_ARGS__) -#define vmsle_vv_i32m1_b32_m(...) __riscv_vmsle_vv_i32m1_b32_mu(__VA_ARGS__) -#define vmsle_vx_i32m1_b32_m(...) __riscv_vmsle_vx_i32m1_b32_mu(__VA_ARGS__) -#define vmsle_vv_i32m2_b16_m(...) __riscv_vmsle_vv_i32m2_b16_mu(__VA_ARGS__) -#define vmsle_vx_i32m2_b16_m(...) __riscv_vmsle_vx_i32m2_b16_mu(__VA_ARGS__) -#define vmsle_vv_i32m4_b8_m(...) __riscv_vmsle_vv_i32m4_b8_mu(__VA_ARGS__) -#define vmsle_vx_i32m4_b8_m(...) __riscv_vmsle_vx_i32m4_b8_mu(__VA_ARGS__) -#define vmsle_vv_i32m8_b4_m(...) __riscv_vmsle_vv_i32m8_b4_mu(__VA_ARGS__) -#define vmsle_vx_i32m8_b4_m(...) __riscv_vmsle_vx_i32m8_b4_mu(__VA_ARGS__) -#define vmsle_vv_i64m1_b64_m(...) __riscv_vmsle_vv_i64m1_b64_mu(__VA_ARGS__) -#define vmsle_vx_i64m1_b64_m(...) __riscv_vmsle_vx_i64m1_b64_mu(__VA_ARGS__) -#define vmsle_vv_i64m2_b32_m(...) __riscv_vmsle_vv_i64m2_b32_mu(__VA_ARGS__) -#define vmsle_vx_i64m2_b32_m(...) __riscv_vmsle_vx_i64m2_b32_mu(__VA_ARGS__) -#define vmsle_vv_i64m4_b16_m(...) __riscv_vmsle_vv_i64m4_b16_mu(__VA_ARGS__) -#define vmsle_vx_i64m4_b16_m(...) __riscv_vmsle_vx_i64m4_b16_mu(__VA_ARGS__) -#define vmsle_vv_i64m8_b8_m(...) __riscv_vmsle_vv_i64m8_b8_mu(__VA_ARGS__) -#define vmsle_vx_i64m8_b8_m(...) __riscv_vmsle_vx_i64m8_b8_mu(__VA_ARGS__) -#define vmsgt_vv_i8mf8_b64_m(...) __riscv_vmsgt_vv_i8mf8_b64_mu(__VA_ARGS__) -#define vmsgt_vx_i8mf8_b64_m(...) __riscv_vmsgt_vx_i8mf8_b64_mu(__VA_ARGS__) -#define vmsgt_vv_i8mf4_b32_m(...) __riscv_vmsgt_vv_i8mf4_b32_mu(__VA_ARGS__) -#define vmsgt_vx_i8mf4_b32_m(...) __riscv_vmsgt_vx_i8mf4_b32_mu(__VA_ARGS__) -#define vmsgt_vv_i8mf2_b16_m(...) __riscv_vmsgt_vv_i8mf2_b16_mu(__VA_ARGS__) -#define vmsgt_vx_i8mf2_b16_m(...) __riscv_vmsgt_vx_i8mf2_b16_mu(__VA_ARGS__) -#define vmsgt_vv_i8m1_b8_m(...) __riscv_vmsgt_vv_i8m1_b8_mu(__VA_ARGS__) -#define vmsgt_vx_i8m1_b8_m(...) __riscv_vmsgt_vx_i8m1_b8_mu(__VA_ARGS__) -#define vmsgt_vv_i8m2_b4_m(...) __riscv_vmsgt_vv_i8m2_b4_mu(__VA_ARGS__) -#define vmsgt_vx_i8m2_b4_m(...) __riscv_vmsgt_vx_i8m2_b4_mu(__VA_ARGS__) -#define vmsgt_vv_i8m4_b2_m(...) __riscv_vmsgt_vv_i8m4_b2_mu(__VA_ARGS__) -#define vmsgt_vx_i8m4_b2_m(...) __riscv_vmsgt_vx_i8m4_b2_mu(__VA_ARGS__) -#define vmsgt_vv_i8m8_b1_m(...) __riscv_vmsgt_vv_i8m8_b1_mu(__VA_ARGS__) -#define vmsgt_vx_i8m8_b1_m(...) __riscv_vmsgt_vx_i8m8_b1_mu(__VA_ARGS__) -#define vmsgt_vv_i16mf4_b64_m(...) __riscv_vmsgt_vv_i16mf4_b64_mu(__VA_ARGS__) -#define vmsgt_vx_i16mf4_b64_m(...) __riscv_vmsgt_vx_i16mf4_b64_mu(__VA_ARGS__) -#define vmsgt_vv_i16mf2_b32_m(...) __riscv_vmsgt_vv_i16mf2_b32_mu(__VA_ARGS__) -#define vmsgt_vx_i16mf2_b32_m(...) __riscv_vmsgt_vx_i16mf2_b32_mu(__VA_ARGS__) -#define vmsgt_vv_i16m1_b16_m(...) __riscv_vmsgt_vv_i16m1_b16_mu(__VA_ARGS__) -#define vmsgt_vx_i16m1_b16_m(...) __riscv_vmsgt_vx_i16m1_b16_mu(__VA_ARGS__) -#define vmsgt_vv_i16m2_b8_m(...) __riscv_vmsgt_vv_i16m2_b8_mu(__VA_ARGS__) -#define vmsgt_vx_i16m2_b8_m(...) __riscv_vmsgt_vx_i16m2_b8_mu(__VA_ARGS__) -#define vmsgt_vv_i16m4_b4_m(...) __riscv_vmsgt_vv_i16m4_b4_mu(__VA_ARGS__) -#define vmsgt_vx_i16m4_b4_m(...) __riscv_vmsgt_vx_i16m4_b4_mu(__VA_ARGS__) -#define vmsgt_vv_i16m8_b2_m(...) __riscv_vmsgt_vv_i16m8_b2_mu(__VA_ARGS__) -#define vmsgt_vx_i16m8_b2_m(...) __riscv_vmsgt_vx_i16m8_b2_mu(__VA_ARGS__) -#define vmsgt_vv_i32mf2_b64_m(...) __riscv_vmsgt_vv_i32mf2_b64_mu(__VA_ARGS__) -#define vmsgt_vx_i32mf2_b64_m(...) __riscv_vmsgt_vx_i32mf2_b64_mu(__VA_ARGS__) -#define vmsgt_vv_i32m1_b32_m(...) __riscv_vmsgt_vv_i32m1_b32_mu(__VA_ARGS__) -#define vmsgt_vx_i32m1_b32_m(...) __riscv_vmsgt_vx_i32m1_b32_mu(__VA_ARGS__) -#define vmsgt_vv_i32m2_b16_m(...) __riscv_vmsgt_vv_i32m2_b16_mu(__VA_ARGS__) -#define vmsgt_vx_i32m2_b16_m(...) __riscv_vmsgt_vx_i32m2_b16_mu(__VA_ARGS__) -#define vmsgt_vv_i32m4_b8_m(...) __riscv_vmsgt_vv_i32m4_b8_mu(__VA_ARGS__) -#define vmsgt_vx_i32m4_b8_m(...) __riscv_vmsgt_vx_i32m4_b8_mu(__VA_ARGS__) -#define vmsgt_vv_i32m8_b4_m(...) __riscv_vmsgt_vv_i32m8_b4_mu(__VA_ARGS__) -#define vmsgt_vx_i32m8_b4_m(...) __riscv_vmsgt_vx_i32m8_b4_mu(__VA_ARGS__) -#define vmsgt_vv_i64m1_b64_m(...) __riscv_vmsgt_vv_i64m1_b64_mu(__VA_ARGS__) -#define vmsgt_vx_i64m1_b64_m(...) __riscv_vmsgt_vx_i64m1_b64_mu(__VA_ARGS__) -#define vmsgt_vv_i64m2_b32_m(...) __riscv_vmsgt_vv_i64m2_b32_mu(__VA_ARGS__) -#define vmsgt_vx_i64m2_b32_m(...) __riscv_vmsgt_vx_i64m2_b32_mu(__VA_ARGS__) -#define vmsgt_vv_i64m4_b16_m(...) __riscv_vmsgt_vv_i64m4_b16_mu(__VA_ARGS__) -#define vmsgt_vx_i64m4_b16_m(...) __riscv_vmsgt_vx_i64m4_b16_mu(__VA_ARGS__) -#define vmsgt_vv_i64m8_b8_m(...) __riscv_vmsgt_vv_i64m8_b8_mu(__VA_ARGS__) -#define vmsgt_vx_i64m8_b8_m(...) __riscv_vmsgt_vx_i64m8_b8_mu(__VA_ARGS__) -#define vmsge_vv_i8mf8_b64_m(...) __riscv_vmsge_vv_i8mf8_b64_mu(__VA_ARGS__) -#define vmsge_vx_i8mf8_b64_m(...) __riscv_vmsge_vx_i8mf8_b64_mu(__VA_ARGS__) -#define vmsge_vv_i8mf4_b32_m(...) __riscv_vmsge_vv_i8mf4_b32_mu(__VA_ARGS__) -#define vmsge_vx_i8mf4_b32_m(...) __riscv_vmsge_vx_i8mf4_b32_mu(__VA_ARGS__) -#define vmsge_vv_i8mf2_b16_m(...) __riscv_vmsge_vv_i8mf2_b16_mu(__VA_ARGS__) -#define vmsge_vx_i8mf2_b16_m(...) __riscv_vmsge_vx_i8mf2_b16_mu(__VA_ARGS__) -#define vmsge_vv_i8m1_b8_m(...) __riscv_vmsge_vv_i8m1_b8_mu(__VA_ARGS__) -#define vmsge_vx_i8m1_b8_m(...) __riscv_vmsge_vx_i8m1_b8_mu(__VA_ARGS__) -#define vmsge_vv_i8m2_b4_m(...) __riscv_vmsge_vv_i8m2_b4_mu(__VA_ARGS__) -#define vmsge_vx_i8m2_b4_m(...) __riscv_vmsge_vx_i8m2_b4_mu(__VA_ARGS__) -#define vmsge_vv_i8m4_b2_m(...) __riscv_vmsge_vv_i8m4_b2_mu(__VA_ARGS__) -#define vmsge_vx_i8m4_b2_m(...) __riscv_vmsge_vx_i8m4_b2_mu(__VA_ARGS__) -#define vmsge_vv_i8m8_b1_m(...) __riscv_vmsge_vv_i8m8_b1_mu(__VA_ARGS__) -#define vmsge_vx_i8m8_b1_m(...) __riscv_vmsge_vx_i8m8_b1_mu(__VA_ARGS__) -#define vmsge_vv_i16mf4_b64_m(...) __riscv_vmsge_vv_i16mf4_b64_mu(__VA_ARGS__) -#define vmsge_vx_i16mf4_b64_m(...) __riscv_vmsge_vx_i16mf4_b64_mu(__VA_ARGS__) -#define vmsge_vv_i16mf2_b32_m(...) __riscv_vmsge_vv_i16mf2_b32_mu(__VA_ARGS__) -#define vmsge_vx_i16mf2_b32_m(...) __riscv_vmsge_vx_i16mf2_b32_mu(__VA_ARGS__) -#define vmsge_vv_i16m1_b16_m(...) __riscv_vmsge_vv_i16m1_b16_mu(__VA_ARGS__) -#define vmsge_vx_i16m1_b16_m(...) __riscv_vmsge_vx_i16m1_b16_mu(__VA_ARGS__) -#define vmsge_vv_i16m2_b8_m(...) __riscv_vmsge_vv_i16m2_b8_mu(__VA_ARGS__) -#define vmsge_vx_i16m2_b8_m(...) __riscv_vmsge_vx_i16m2_b8_mu(__VA_ARGS__) -#define vmsge_vv_i16m4_b4_m(...) __riscv_vmsge_vv_i16m4_b4_mu(__VA_ARGS__) -#define vmsge_vx_i16m4_b4_m(...) __riscv_vmsge_vx_i16m4_b4_mu(__VA_ARGS__) -#define vmsge_vv_i16m8_b2_m(...) __riscv_vmsge_vv_i16m8_b2_mu(__VA_ARGS__) -#define vmsge_vx_i16m8_b2_m(...) __riscv_vmsge_vx_i16m8_b2_mu(__VA_ARGS__) -#define vmsge_vv_i32mf2_b64_m(...) __riscv_vmsge_vv_i32mf2_b64_mu(__VA_ARGS__) -#define vmsge_vx_i32mf2_b64_m(...) __riscv_vmsge_vx_i32mf2_b64_mu(__VA_ARGS__) -#define vmsge_vv_i32m1_b32_m(...) __riscv_vmsge_vv_i32m1_b32_mu(__VA_ARGS__) -#define vmsge_vx_i32m1_b32_m(...) __riscv_vmsge_vx_i32m1_b32_mu(__VA_ARGS__) -#define vmsge_vv_i32m2_b16_m(...) __riscv_vmsge_vv_i32m2_b16_mu(__VA_ARGS__) -#define vmsge_vx_i32m2_b16_m(...) __riscv_vmsge_vx_i32m2_b16_mu(__VA_ARGS__) -#define vmsge_vv_i32m4_b8_m(...) __riscv_vmsge_vv_i32m4_b8_mu(__VA_ARGS__) -#define vmsge_vx_i32m4_b8_m(...) __riscv_vmsge_vx_i32m4_b8_mu(__VA_ARGS__) -#define vmsge_vv_i32m8_b4_m(...) __riscv_vmsge_vv_i32m8_b4_mu(__VA_ARGS__) -#define vmsge_vx_i32m8_b4_m(...) __riscv_vmsge_vx_i32m8_b4_mu(__VA_ARGS__) -#define vmsge_vv_i64m1_b64_m(...) __riscv_vmsge_vv_i64m1_b64_mu(__VA_ARGS__) -#define vmsge_vx_i64m1_b64_m(...) __riscv_vmsge_vx_i64m1_b64_mu(__VA_ARGS__) -#define vmsge_vv_i64m2_b32_m(...) __riscv_vmsge_vv_i64m2_b32_mu(__VA_ARGS__) -#define vmsge_vx_i64m2_b32_m(...) __riscv_vmsge_vx_i64m2_b32_mu(__VA_ARGS__) -#define vmsge_vv_i64m4_b16_m(...) __riscv_vmsge_vv_i64m4_b16_mu(__VA_ARGS__) -#define vmsge_vx_i64m4_b16_m(...) __riscv_vmsge_vx_i64m4_b16_mu(__VA_ARGS__) -#define vmsge_vv_i64m8_b8_m(...) __riscv_vmsge_vv_i64m8_b8_mu(__VA_ARGS__) -#define vmsge_vx_i64m8_b8_m(...) __riscv_vmsge_vx_i64m8_b8_mu(__VA_ARGS__) -#define vmseq_vv_u8mf8_b64_m(...) __riscv_vmseq_vv_u8mf8_b64_mu(__VA_ARGS__) -#define vmseq_vx_u8mf8_b64_m(...) __riscv_vmseq_vx_u8mf8_b64_mu(__VA_ARGS__) -#define vmseq_vv_u8mf4_b32_m(...) __riscv_vmseq_vv_u8mf4_b32_mu(__VA_ARGS__) -#define vmseq_vx_u8mf4_b32_m(...) __riscv_vmseq_vx_u8mf4_b32_mu(__VA_ARGS__) -#define vmseq_vv_u8mf2_b16_m(...) __riscv_vmseq_vv_u8mf2_b16_mu(__VA_ARGS__) -#define vmseq_vx_u8mf2_b16_m(...) __riscv_vmseq_vx_u8mf2_b16_mu(__VA_ARGS__) -#define vmseq_vv_u8m1_b8_m(...) __riscv_vmseq_vv_u8m1_b8_mu(__VA_ARGS__) -#define vmseq_vx_u8m1_b8_m(...) __riscv_vmseq_vx_u8m1_b8_mu(__VA_ARGS__) -#define vmseq_vv_u8m2_b4_m(...) __riscv_vmseq_vv_u8m2_b4_mu(__VA_ARGS__) -#define vmseq_vx_u8m2_b4_m(...) __riscv_vmseq_vx_u8m2_b4_mu(__VA_ARGS__) -#define vmseq_vv_u8m4_b2_m(...) __riscv_vmseq_vv_u8m4_b2_mu(__VA_ARGS__) -#define vmseq_vx_u8m4_b2_m(...) __riscv_vmseq_vx_u8m4_b2_mu(__VA_ARGS__) -#define vmseq_vv_u8m8_b1_m(...) __riscv_vmseq_vv_u8m8_b1_mu(__VA_ARGS__) -#define vmseq_vx_u8m8_b1_m(...) __riscv_vmseq_vx_u8m8_b1_mu(__VA_ARGS__) -#define vmseq_vv_u16mf4_b64_m(...) __riscv_vmseq_vv_u16mf4_b64_mu(__VA_ARGS__) -#define vmseq_vx_u16mf4_b64_m(...) __riscv_vmseq_vx_u16mf4_b64_mu(__VA_ARGS__) -#define vmseq_vv_u16mf2_b32_m(...) __riscv_vmseq_vv_u16mf2_b32_mu(__VA_ARGS__) -#define vmseq_vx_u16mf2_b32_m(...) __riscv_vmseq_vx_u16mf2_b32_mu(__VA_ARGS__) -#define vmseq_vv_u16m1_b16_m(...) __riscv_vmseq_vv_u16m1_b16_mu(__VA_ARGS__) -#define vmseq_vx_u16m1_b16_m(...) __riscv_vmseq_vx_u16m1_b16_mu(__VA_ARGS__) -#define vmseq_vv_u16m2_b8_m(...) __riscv_vmseq_vv_u16m2_b8_mu(__VA_ARGS__) -#define vmseq_vx_u16m2_b8_m(...) __riscv_vmseq_vx_u16m2_b8_mu(__VA_ARGS__) -#define vmseq_vv_u16m4_b4_m(...) __riscv_vmseq_vv_u16m4_b4_mu(__VA_ARGS__) -#define vmseq_vx_u16m4_b4_m(...) __riscv_vmseq_vx_u16m4_b4_mu(__VA_ARGS__) -#define vmseq_vv_u16m8_b2_m(...) __riscv_vmseq_vv_u16m8_b2_mu(__VA_ARGS__) -#define vmseq_vx_u16m8_b2_m(...) __riscv_vmseq_vx_u16m8_b2_mu(__VA_ARGS__) -#define vmseq_vv_u32mf2_b64_m(...) __riscv_vmseq_vv_u32mf2_b64_mu(__VA_ARGS__) -#define vmseq_vx_u32mf2_b64_m(...) __riscv_vmseq_vx_u32mf2_b64_mu(__VA_ARGS__) -#define vmseq_vv_u32m1_b32_m(...) __riscv_vmseq_vv_u32m1_b32_mu(__VA_ARGS__) -#define vmseq_vx_u32m1_b32_m(...) __riscv_vmseq_vx_u32m1_b32_mu(__VA_ARGS__) -#define vmseq_vv_u32m2_b16_m(...) __riscv_vmseq_vv_u32m2_b16_mu(__VA_ARGS__) -#define vmseq_vx_u32m2_b16_m(...) __riscv_vmseq_vx_u32m2_b16_mu(__VA_ARGS__) -#define vmseq_vv_u32m4_b8_m(...) __riscv_vmseq_vv_u32m4_b8_mu(__VA_ARGS__) -#define vmseq_vx_u32m4_b8_m(...) __riscv_vmseq_vx_u32m4_b8_mu(__VA_ARGS__) -#define vmseq_vv_u32m8_b4_m(...) __riscv_vmseq_vv_u32m8_b4_mu(__VA_ARGS__) -#define vmseq_vx_u32m8_b4_m(...) __riscv_vmseq_vx_u32m8_b4_mu(__VA_ARGS__) -#define vmseq_vv_u64m1_b64_m(...) __riscv_vmseq_vv_u64m1_b64_mu(__VA_ARGS__) -#define vmseq_vx_u64m1_b64_m(...) __riscv_vmseq_vx_u64m1_b64_mu(__VA_ARGS__) -#define vmseq_vv_u64m2_b32_m(...) __riscv_vmseq_vv_u64m2_b32_mu(__VA_ARGS__) -#define vmseq_vx_u64m2_b32_m(...) __riscv_vmseq_vx_u64m2_b32_mu(__VA_ARGS__) -#define vmseq_vv_u64m4_b16_m(...) __riscv_vmseq_vv_u64m4_b16_mu(__VA_ARGS__) -#define vmseq_vx_u64m4_b16_m(...) __riscv_vmseq_vx_u64m4_b16_mu(__VA_ARGS__) -#define vmseq_vv_u64m8_b8_m(...) __riscv_vmseq_vv_u64m8_b8_mu(__VA_ARGS__) -#define vmseq_vx_u64m8_b8_m(...) __riscv_vmseq_vx_u64m8_b8_mu(__VA_ARGS__) -#define vmsne_vv_u8mf8_b64_m(...) __riscv_vmsne_vv_u8mf8_b64_mu(__VA_ARGS__) -#define vmsne_vx_u8mf8_b64_m(...) __riscv_vmsne_vx_u8mf8_b64_mu(__VA_ARGS__) -#define vmsne_vv_u8mf4_b32_m(...) __riscv_vmsne_vv_u8mf4_b32_mu(__VA_ARGS__) -#define vmsne_vx_u8mf4_b32_m(...) __riscv_vmsne_vx_u8mf4_b32_mu(__VA_ARGS__) -#define vmsne_vv_u8mf2_b16_m(...) __riscv_vmsne_vv_u8mf2_b16_mu(__VA_ARGS__) -#define vmsne_vx_u8mf2_b16_m(...) __riscv_vmsne_vx_u8mf2_b16_mu(__VA_ARGS__) -#define vmsne_vv_u8m1_b8_m(...) __riscv_vmsne_vv_u8m1_b8_mu(__VA_ARGS__) -#define vmsne_vx_u8m1_b8_m(...) __riscv_vmsne_vx_u8m1_b8_mu(__VA_ARGS__) -#define vmsne_vv_u8m2_b4_m(...) __riscv_vmsne_vv_u8m2_b4_mu(__VA_ARGS__) -#define vmsne_vx_u8m2_b4_m(...) __riscv_vmsne_vx_u8m2_b4_mu(__VA_ARGS__) -#define vmsne_vv_u8m4_b2_m(...) __riscv_vmsne_vv_u8m4_b2_mu(__VA_ARGS__) -#define vmsne_vx_u8m4_b2_m(...) __riscv_vmsne_vx_u8m4_b2_mu(__VA_ARGS__) -#define vmsne_vv_u8m8_b1_m(...) __riscv_vmsne_vv_u8m8_b1_mu(__VA_ARGS__) -#define vmsne_vx_u8m8_b1_m(...) __riscv_vmsne_vx_u8m8_b1_mu(__VA_ARGS__) -#define vmsne_vv_u16mf4_b64_m(...) __riscv_vmsne_vv_u16mf4_b64_mu(__VA_ARGS__) -#define vmsne_vx_u16mf4_b64_m(...) __riscv_vmsne_vx_u16mf4_b64_mu(__VA_ARGS__) -#define vmsne_vv_u16mf2_b32_m(...) __riscv_vmsne_vv_u16mf2_b32_mu(__VA_ARGS__) -#define vmsne_vx_u16mf2_b32_m(...) __riscv_vmsne_vx_u16mf2_b32_mu(__VA_ARGS__) -#define vmsne_vv_u16m1_b16_m(...) __riscv_vmsne_vv_u16m1_b16_mu(__VA_ARGS__) -#define vmsne_vx_u16m1_b16_m(...) __riscv_vmsne_vx_u16m1_b16_mu(__VA_ARGS__) -#define vmsne_vv_u16m2_b8_m(...) __riscv_vmsne_vv_u16m2_b8_mu(__VA_ARGS__) -#define vmsne_vx_u16m2_b8_m(...) __riscv_vmsne_vx_u16m2_b8_mu(__VA_ARGS__) -#define vmsne_vv_u16m4_b4_m(...) __riscv_vmsne_vv_u16m4_b4_mu(__VA_ARGS__) -#define vmsne_vx_u16m4_b4_m(...) __riscv_vmsne_vx_u16m4_b4_mu(__VA_ARGS__) -#define vmsne_vv_u16m8_b2_m(...) __riscv_vmsne_vv_u16m8_b2_mu(__VA_ARGS__) -#define vmsne_vx_u16m8_b2_m(...) __riscv_vmsne_vx_u16m8_b2_mu(__VA_ARGS__) -#define vmsne_vv_u32mf2_b64_m(...) __riscv_vmsne_vv_u32mf2_b64_mu(__VA_ARGS__) -#define vmsne_vx_u32mf2_b64_m(...) __riscv_vmsne_vx_u32mf2_b64_mu(__VA_ARGS__) -#define vmsne_vv_u32m1_b32_m(...) __riscv_vmsne_vv_u32m1_b32_mu(__VA_ARGS__) -#define vmsne_vx_u32m1_b32_m(...) __riscv_vmsne_vx_u32m1_b32_mu(__VA_ARGS__) -#define vmsne_vv_u32m2_b16_m(...) __riscv_vmsne_vv_u32m2_b16_mu(__VA_ARGS__) -#define vmsne_vx_u32m2_b16_m(...) __riscv_vmsne_vx_u32m2_b16_mu(__VA_ARGS__) -#define vmsne_vv_u32m4_b8_m(...) __riscv_vmsne_vv_u32m4_b8_mu(__VA_ARGS__) -#define vmsne_vx_u32m4_b8_m(...) __riscv_vmsne_vx_u32m4_b8_mu(__VA_ARGS__) -#define vmsne_vv_u32m8_b4_m(...) __riscv_vmsne_vv_u32m8_b4_mu(__VA_ARGS__) -#define vmsne_vx_u32m8_b4_m(...) __riscv_vmsne_vx_u32m8_b4_mu(__VA_ARGS__) -#define vmsne_vv_u64m1_b64_m(...) __riscv_vmsne_vv_u64m1_b64_mu(__VA_ARGS__) -#define vmsne_vx_u64m1_b64_m(...) __riscv_vmsne_vx_u64m1_b64_mu(__VA_ARGS__) -#define vmsne_vv_u64m2_b32_m(...) __riscv_vmsne_vv_u64m2_b32_mu(__VA_ARGS__) -#define vmsne_vx_u64m2_b32_m(...) __riscv_vmsne_vx_u64m2_b32_mu(__VA_ARGS__) -#define vmsne_vv_u64m4_b16_m(...) __riscv_vmsne_vv_u64m4_b16_mu(__VA_ARGS__) -#define vmsne_vx_u64m4_b16_m(...) __riscv_vmsne_vx_u64m4_b16_mu(__VA_ARGS__) -#define vmsne_vv_u64m8_b8_m(...) __riscv_vmsne_vv_u64m8_b8_mu(__VA_ARGS__) -#define vmsne_vx_u64m8_b8_m(...) __riscv_vmsne_vx_u64m8_b8_mu(__VA_ARGS__) -#define vmsltu_vv_u8mf8_b64_m(...) __riscv_vmsltu_vv_u8mf8_b64_mu(__VA_ARGS__) -#define vmsltu_vx_u8mf8_b64_m(...) __riscv_vmsltu_vx_u8mf8_b64_mu(__VA_ARGS__) -#define vmsltu_vv_u8mf4_b32_m(...) __riscv_vmsltu_vv_u8mf4_b32_mu(__VA_ARGS__) -#define vmsltu_vx_u8mf4_b32_m(...) __riscv_vmsltu_vx_u8mf4_b32_mu(__VA_ARGS__) -#define vmsltu_vv_u8mf2_b16_m(...) __riscv_vmsltu_vv_u8mf2_b16_mu(__VA_ARGS__) -#define vmsltu_vx_u8mf2_b16_m(...) __riscv_vmsltu_vx_u8mf2_b16_mu(__VA_ARGS__) -#define vmsltu_vv_u8m1_b8_m(...) __riscv_vmsltu_vv_u8m1_b8_mu(__VA_ARGS__) -#define vmsltu_vx_u8m1_b8_m(...) __riscv_vmsltu_vx_u8m1_b8_mu(__VA_ARGS__) -#define vmsltu_vv_u8m2_b4_m(...) __riscv_vmsltu_vv_u8m2_b4_mu(__VA_ARGS__) -#define vmsltu_vx_u8m2_b4_m(...) __riscv_vmsltu_vx_u8m2_b4_mu(__VA_ARGS__) -#define vmsltu_vv_u8m4_b2_m(...) __riscv_vmsltu_vv_u8m4_b2_mu(__VA_ARGS__) -#define vmsltu_vx_u8m4_b2_m(...) __riscv_vmsltu_vx_u8m4_b2_mu(__VA_ARGS__) -#define vmsltu_vv_u8m8_b1_m(...) __riscv_vmsltu_vv_u8m8_b1_mu(__VA_ARGS__) -#define vmsltu_vx_u8m8_b1_m(...) __riscv_vmsltu_vx_u8m8_b1_mu(__VA_ARGS__) -#define vmsltu_vv_u16mf4_b64_m(...) __riscv_vmsltu_vv_u16mf4_b64_mu(__VA_ARGS__) -#define vmsltu_vx_u16mf4_b64_m(...) __riscv_vmsltu_vx_u16mf4_b64_mu(__VA_ARGS__) -#define vmsltu_vv_u16mf2_b32_m(...) __riscv_vmsltu_vv_u16mf2_b32_mu(__VA_ARGS__) -#define vmsltu_vx_u16mf2_b32_m(...) __riscv_vmsltu_vx_u16mf2_b32_mu(__VA_ARGS__) -#define vmsltu_vv_u16m1_b16_m(...) __riscv_vmsltu_vv_u16m1_b16_mu(__VA_ARGS__) -#define vmsltu_vx_u16m1_b16_m(...) __riscv_vmsltu_vx_u16m1_b16_mu(__VA_ARGS__) -#define vmsltu_vv_u16m2_b8_m(...) __riscv_vmsltu_vv_u16m2_b8_mu(__VA_ARGS__) -#define vmsltu_vx_u16m2_b8_m(...) __riscv_vmsltu_vx_u16m2_b8_mu(__VA_ARGS__) -#define vmsltu_vv_u16m4_b4_m(...) __riscv_vmsltu_vv_u16m4_b4_mu(__VA_ARGS__) -#define vmsltu_vx_u16m4_b4_m(...) __riscv_vmsltu_vx_u16m4_b4_mu(__VA_ARGS__) -#define vmsltu_vv_u16m8_b2_m(...) __riscv_vmsltu_vv_u16m8_b2_mu(__VA_ARGS__) -#define vmsltu_vx_u16m8_b2_m(...) __riscv_vmsltu_vx_u16m8_b2_mu(__VA_ARGS__) -#define vmsltu_vv_u32mf2_b64_m(...) __riscv_vmsltu_vv_u32mf2_b64_mu(__VA_ARGS__) -#define vmsltu_vx_u32mf2_b64_m(...) __riscv_vmsltu_vx_u32mf2_b64_mu(__VA_ARGS__) -#define vmsltu_vv_u32m1_b32_m(...) __riscv_vmsltu_vv_u32m1_b32_mu(__VA_ARGS__) -#define vmsltu_vx_u32m1_b32_m(...) __riscv_vmsltu_vx_u32m1_b32_mu(__VA_ARGS__) -#define vmsltu_vv_u32m2_b16_m(...) __riscv_vmsltu_vv_u32m2_b16_mu(__VA_ARGS__) -#define vmsltu_vx_u32m2_b16_m(...) __riscv_vmsltu_vx_u32m2_b16_mu(__VA_ARGS__) -#define vmsltu_vv_u32m4_b8_m(...) __riscv_vmsltu_vv_u32m4_b8_mu(__VA_ARGS__) -#define vmsltu_vx_u32m4_b8_m(...) __riscv_vmsltu_vx_u32m4_b8_mu(__VA_ARGS__) -#define vmsltu_vv_u32m8_b4_m(...) __riscv_vmsltu_vv_u32m8_b4_mu(__VA_ARGS__) -#define vmsltu_vx_u32m8_b4_m(...) __riscv_vmsltu_vx_u32m8_b4_mu(__VA_ARGS__) -#define vmsltu_vv_u64m1_b64_m(...) __riscv_vmsltu_vv_u64m1_b64_mu(__VA_ARGS__) -#define vmsltu_vx_u64m1_b64_m(...) __riscv_vmsltu_vx_u64m1_b64_mu(__VA_ARGS__) -#define vmsltu_vv_u64m2_b32_m(...) __riscv_vmsltu_vv_u64m2_b32_mu(__VA_ARGS__) -#define vmsltu_vx_u64m2_b32_m(...) __riscv_vmsltu_vx_u64m2_b32_mu(__VA_ARGS__) -#define vmsltu_vv_u64m4_b16_m(...) __riscv_vmsltu_vv_u64m4_b16_mu(__VA_ARGS__) -#define vmsltu_vx_u64m4_b16_m(...) __riscv_vmsltu_vx_u64m4_b16_mu(__VA_ARGS__) -#define vmsltu_vv_u64m8_b8_m(...) __riscv_vmsltu_vv_u64m8_b8_mu(__VA_ARGS__) -#define vmsltu_vx_u64m8_b8_m(...) __riscv_vmsltu_vx_u64m8_b8_mu(__VA_ARGS__) -#define vmsleu_vv_u8mf8_b64_m(...) __riscv_vmsleu_vv_u8mf8_b64_mu(__VA_ARGS__) -#define vmsleu_vx_u8mf8_b64_m(...) __riscv_vmsleu_vx_u8mf8_b64_mu(__VA_ARGS__) -#define vmsleu_vv_u8mf4_b32_m(...) __riscv_vmsleu_vv_u8mf4_b32_mu(__VA_ARGS__) -#define vmsleu_vx_u8mf4_b32_m(...) __riscv_vmsleu_vx_u8mf4_b32_mu(__VA_ARGS__) -#define vmsleu_vv_u8mf2_b16_m(...) __riscv_vmsleu_vv_u8mf2_b16_mu(__VA_ARGS__) -#define vmsleu_vx_u8mf2_b16_m(...) __riscv_vmsleu_vx_u8mf2_b16_mu(__VA_ARGS__) -#define vmsleu_vv_u8m1_b8_m(...) __riscv_vmsleu_vv_u8m1_b8_mu(__VA_ARGS__) -#define vmsleu_vx_u8m1_b8_m(...) __riscv_vmsleu_vx_u8m1_b8_mu(__VA_ARGS__) -#define vmsleu_vv_u8m2_b4_m(...) __riscv_vmsleu_vv_u8m2_b4_mu(__VA_ARGS__) -#define vmsleu_vx_u8m2_b4_m(...) __riscv_vmsleu_vx_u8m2_b4_mu(__VA_ARGS__) -#define vmsleu_vv_u8m4_b2_m(...) __riscv_vmsleu_vv_u8m4_b2_mu(__VA_ARGS__) -#define vmsleu_vx_u8m4_b2_m(...) __riscv_vmsleu_vx_u8m4_b2_mu(__VA_ARGS__) -#define vmsleu_vv_u8m8_b1_m(...) __riscv_vmsleu_vv_u8m8_b1_mu(__VA_ARGS__) -#define vmsleu_vx_u8m8_b1_m(...) __riscv_vmsleu_vx_u8m8_b1_mu(__VA_ARGS__) -#define vmsleu_vv_u16mf4_b64_m(...) __riscv_vmsleu_vv_u16mf4_b64_mu(__VA_ARGS__) -#define vmsleu_vx_u16mf4_b64_m(...) __riscv_vmsleu_vx_u16mf4_b64_mu(__VA_ARGS__) -#define vmsleu_vv_u16mf2_b32_m(...) __riscv_vmsleu_vv_u16mf2_b32_mu(__VA_ARGS__) -#define vmsleu_vx_u16mf2_b32_m(...) __riscv_vmsleu_vx_u16mf2_b32_mu(__VA_ARGS__) -#define vmsleu_vv_u16m1_b16_m(...) __riscv_vmsleu_vv_u16m1_b16_mu(__VA_ARGS__) -#define vmsleu_vx_u16m1_b16_m(...) __riscv_vmsleu_vx_u16m1_b16_mu(__VA_ARGS__) -#define vmsleu_vv_u16m2_b8_m(...) __riscv_vmsleu_vv_u16m2_b8_mu(__VA_ARGS__) -#define vmsleu_vx_u16m2_b8_m(...) __riscv_vmsleu_vx_u16m2_b8_mu(__VA_ARGS__) -#define vmsleu_vv_u16m4_b4_m(...) __riscv_vmsleu_vv_u16m4_b4_mu(__VA_ARGS__) -#define vmsleu_vx_u16m4_b4_m(...) __riscv_vmsleu_vx_u16m4_b4_mu(__VA_ARGS__) -#define vmsleu_vv_u16m8_b2_m(...) __riscv_vmsleu_vv_u16m8_b2_mu(__VA_ARGS__) -#define vmsleu_vx_u16m8_b2_m(...) __riscv_vmsleu_vx_u16m8_b2_mu(__VA_ARGS__) -#define vmsleu_vv_u32mf2_b64_m(...) __riscv_vmsleu_vv_u32mf2_b64_mu(__VA_ARGS__) -#define vmsleu_vx_u32mf2_b64_m(...) __riscv_vmsleu_vx_u32mf2_b64_mu(__VA_ARGS__) -#define vmsleu_vv_u32m1_b32_m(...) __riscv_vmsleu_vv_u32m1_b32_mu(__VA_ARGS__) -#define vmsleu_vx_u32m1_b32_m(...) __riscv_vmsleu_vx_u32m1_b32_mu(__VA_ARGS__) -#define vmsleu_vv_u32m2_b16_m(...) __riscv_vmsleu_vv_u32m2_b16_mu(__VA_ARGS__) -#define vmsleu_vx_u32m2_b16_m(...) __riscv_vmsleu_vx_u32m2_b16_mu(__VA_ARGS__) -#define vmsleu_vv_u32m4_b8_m(...) __riscv_vmsleu_vv_u32m4_b8_mu(__VA_ARGS__) -#define vmsleu_vx_u32m4_b8_m(...) __riscv_vmsleu_vx_u32m4_b8_mu(__VA_ARGS__) -#define vmsleu_vv_u32m8_b4_m(...) __riscv_vmsleu_vv_u32m8_b4_mu(__VA_ARGS__) -#define vmsleu_vx_u32m8_b4_m(...) __riscv_vmsleu_vx_u32m8_b4_mu(__VA_ARGS__) -#define vmsleu_vv_u64m1_b64_m(...) __riscv_vmsleu_vv_u64m1_b64_mu(__VA_ARGS__) -#define vmsleu_vx_u64m1_b64_m(...) __riscv_vmsleu_vx_u64m1_b64_mu(__VA_ARGS__) -#define vmsleu_vv_u64m2_b32_m(...) __riscv_vmsleu_vv_u64m2_b32_mu(__VA_ARGS__) -#define vmsleu_vx_u64m2_b32_m(...) __riscv_vmsleu_vx_u64m2_b32_mu(__VA_ARGS__) -#define vmsleu_vv_u64m4_b16_m(...) __riscv_vmsleu_vv_u64m4_b16_mu(__VA_ARGS__) -#define vmsleu_vx_u64m4_b16_m(...) __riscv_vmsleu_vx_u64m4_b16_mu(__VA_ARGS__) -#define vmsleu_vv_u64m8_b8_m(...) __riscv_vmsleu_vv_u64m8_b8_mu(__VA_ARGS__) -#define vmsleu_vx_u64m8_b8_m(...) __riscv_vmsleu_vx_u64m8_b8_mu(__VA_ARGS__) -#define vmsgtu_vv_u8mf8_b64_m(...) __riscv_vmsgtu_vv_u8mf8_b64_mu(__VA_ARGS__) -#define vmsgtu_vx_u8mf8_b64_m(...) __riscv_vmsgtu_vx_u8mf8_b64_mu(__VA_ARGS__) -#define vmsgtu_vv_u8mf4_b32_m(...) __riscv_vmsgtu_vv_u8mf4_b32_mu(__VA_ARGS__) -#define vmsgtu_vx_u8mf4_b32_m(...) __riscv_vmsgtu_vx_u8mf4_b32_mu(__VA_ARGS__) -#define vmsgtu_vv_u8mf2_b16_m(...) __riscv_vmsgtu_vv_u8mf2_b16_mu(__VA_ARGS__) -#define vmsgtu_vx_u8mf2_b16_m(...) __riscv_vmsgtu_vx_u8mf2_b16_mu(__VA_ARGS__) -#define vmsgtu_vv_u8m1_b8_m(...) __riscv_vmsgtu_vv_u8m1_b8_mu(__VA_ARGS__) -#define vmsgtu_vx_u8m1_b8_m(...) __riscv_vmsgtu_vx_u8m1_b8_mu(__VA_ARGS__) -#define vmsgtu_vv_u8m2_b4_m(...) __riscv_vmsgtu_vv_u8m2_b4_mu(__VA_ARGS__) -#define vmsgtu_vx_u8m2_b4_m(...) __riscv_vmsgtu_vx_u8m2_b4_mu(__VA_ARGS__) -#define vmsgtu_vv_u8m4_b2_m(...) __riscv_vmsgtu_vv_u8m4_b2_mu(__VA_ARGS__) -#define vmsgtu_vx_u8m4_b2_m(...) __riscv_vmsgtu_vx_u8m4_b2_mu(__VA_ARGS__) -#define vmsgtu_vv_u8m8_b1_m(...) __riscv_vmsgtu_vv_u8m8_b1_mu(__VA_ARGS__) -#define vmsgtu_vx_u8m8_b1_m(...) __riscv_vmsgtu_vx_u8m8_b1_mu(__VA_ARGS__) -#define vmsgtu_vv_u16mf4_b64_m(...) __riscv_vmsgtu_vv_u16mf4_b64_mu(__VA_ARGS__) -#define vmsgtu_vx_u16mf4_b64_m(...) __riscv_vmsgtu_vx_u16mf4_b64_mu(__VA_ARGS__) -#define vmsgtu_vv_u16mf2_b32_m(...) __riscv_vmsgtu_vv_u16mf2_b32_mu(__VA_ARGS__) -#define vmsgtu_vx_u16mf2_b32_m(...) __riscv_vmsgtu_vx_u16mf2_b32_mu(__VA_ARGS__) -#define vmsgtu_vv_u16m1_b16_m(...) __riscv_vmsgtu_vv_u16m1_b16_mu(__VA_ARGS__) -#define vmsgtu_vx_u16m1_b16_m(...) __riscv_vmsgtu_vx_u16m1_b16_mu(__VA_ARGS__) -#define vmsgtu_vv_u16m2_b8_m(...) __riscv_vmsgtu_vv_u16m2_b8_mu(__VA_ARGS__) -#define vmsgtu_vx_u16m2_b8_m(...) __riscv_vmsgtu_vx_u16m2_b8_mu(__VA_ARGS__) -#define vmsgtu_vv_u16m4_b4_m(...) __riscv_vmsgtu_vv_u16m4_b4_mu(__VA_ARGS__) -#define vmsgtu_vx_u16m4_b4_m(...) __riscv_vmsgtu_vx_u16m4_b4_mu(__VA_ARGS__) -#define vmsgtu_vv_u16m8_b2_m(...) __riscv_vmsgtu_vv_u16m8_b2_mu(__VA_ARGS__) -#define vmsgtu_vx_u16m8_b2_m(...) __riscv_vmsgtu_vx_u16m8_b2_mu(__VA_ARGS__) -#define vmsgtu_vv_u32mf2_b64_m(...) __riscv_vmsgtu_vv_u32mf2_b64_mu(__VA_ARGS__) -#define vmsgtu_vx_u32mf2_b64_m(...) __riscv_vmsgtu_vx_u32mf2_b64_mu(__VA_ARGS__) -#define vmsgtu_vv_u32m1_b32_m(...) __riscv_vmsgtu_vv_u32m1_b32_mu(__VA_ARGS__) -#define vmsgtu_vx_u32m1_b32_m(...) __riscv_vmsgtu_vx_u32m1_b32_mu(__VA_ARGS__) -#define vmsgtu_vv_u32m2_b16_m(...) __riscv_vmsgtu_vv_u32m2_b16_mu(__VA_ARGS__) -#define vmsgtu_vx_u32m2_b16_m(...) __riscv_vmsgtu_vx_u32m2_b16_mu(__VA_ARGS__) -#define vmsgtu_vv_u32m4_b8_m(...) __riscv_vmsgtu_vv_u32m4_b8_mu(__VA_ARGS__) -#define vmsgtu_vx_u32m4_b8_m(...) __riscv_vmsgtu_vx_u32m4_b8_mu(__VA_ARGS__) -#define vmsgtu_vv_u32m8_b4_m(...) __riscv_vmsgtu_vv_u32m8_b4_mu(__VA_ARGS__) -#define vmsgtu_vx_u32m8_b4_m(...) __riscv_vmsgtu_vx_u32m8_b4_mu(__VA_ARGS__) -#define vmsgtu_vv_u64m1_b64_m(...) __riscv_vmsgtu_vv_u64m1_b64_mu(__VA_ARGS__) -#define vmsgtu_vx_u64m1_b64_m(...) __riscv_vmsgtu_vx_u64m1_b64_mu(__VA_ARGS__) -#define vmsgtu_vv_u64m2_b32_m(...) __riscv_vmsgtu_vv_u64m2_b32_mu(__VA_ARGS__) -#define vmsgtu_vx_u64m2_b32_m(...) __riscv_vmsgtu_vx_u64m2_b32_mu(__VA_ARGS__) -#define vmsgtu_vv_u64m4_b16_m(...) __riscv_vmsgtu_vv_u64m4_b16_mu(__VA_ARGS__) -#define vmsgtu_vx_u64m4_b16_m(...) __riscv_vmsgtu_vx_u64m4_b16_mu(__VA_ARGS__) -#define vmsgtu_vv_u64m8_b8_m(...) __riscv_vmsgtu_vv_u64m8_b8_mu(__VA_ARGS__) -#define vmsgtu_vx_u64m8_b8_m(...) __riscv_vmsgtu_vx_u64m8_b8_mu(__VA_ARGS__) -#define vmsgeu_vv_u8mf8_b64_m(...) __riscv_vmsgeu_vv_u8mf8_b64_mu(__VA_ARGS__) -#define vmsgeu_vx_u8mf8_b64_m(...) __riscv_vmsgeu_vx_u8mf8_b64_mu(__VA_ARGS__) -#define vmsgeu_vv_u8mf4_b32_m(...) __riscv_vmsgeu_vv_u8mf4_b32_mu(__VA_ARGS__) -#define vmsgeu_vx_u8mf4_b32_m(...) __riscv_vmsgeu_vx_u8mf4_b32_mu(__VA_ARGS__) -#define vmsgeu_vv_u8mf2_b16_m(...) __riscv_vmsgeu_vv_u8mf2_b16_mu(__VA_ARGS__) -#define vmsgeu_vx_u8mf2_b16_m(...) __riscv_vmsgeu_vx_u8mf2_b16_mu(__VA_ARGS__) -#define vmsgeu_vv_u8m1_b8_m(...) __riscv_vmsgeu_vv_u8m1_b8_mu(__VA_ARGS__) -#define vmsgeu_vx_u8m1_b8_m(...) __riscv_vmsgeu_vx_u8m1_b8_mu(__VA_ARGS__) -#define vmsgeu_vv_u8m2_b4_m(...) __riscv_vmsgeu_vv_u8m2_b4_mu(__VA_ARGS__) -#define vmsgeu_vx_u8m2_b4_m(...) __riscv_vmsgeu_vx_u8m2_b4_mu(__VA_ARGS__) -#define vmsgeu_vv_u8m4_b2_m(...) __riscv_vmsgeu_vv_u8m4_b2_mu(__VA_ARGS__) -#define vmsgeu_vx_u8m4_b2_m(...) __riscv_vmsgeu_vx_u8m4_b2_mu(__VA_ARGS__) -#define vmsgeu_vv_u8m8_b1_m(...) __riscv_vmsgeu_vv_u8m8_b1_mu(__VA_ARGS__) -#define vmsgeu_vx_u8m8_b1_m(...) __riscv_vmsgeu_vx_u8m8_b1_mu(__VA_ARGS__) -#define vmsgeu_vv_u16mf4_b64_m(...) __riscv_vmsgeu_vv_u16mf4_b64_mu(__VA_ARGS__) -#define vmsgeu_vx_u16mf4_b64_m(...) __riscv_vmsgeu_vx_u16mf4_b64_mu(__VA_ARGS__) -#define vmsgeu_vv_u16mf2_b32_m(...) __riscv_vmsgeu_vv_u16mf2_b32_mu(__VA_ARGS__) -#define vmsgeu_vx_u16mf2_b32_m(...) __riscv_vmsgeu_vx_u16mf2_b32_mu(__VA_ARGS__) -#define vmsgeu_vv_u16m1_b16_m(...) __riscv_vmsgeu_vv_u16m1_b16_mu(__VA_ARGS__) -#define vmsgeu_vx_u16m1_b16_m(...) __riscv_vmsgeu_vx_u16m1_b16_mu(__VA_ARGS__) -#define vmsgeu_vv_u16m2_b8_m(...) __riscv_vmsgeu_vv_u16m2_b8_mu(__VA_ARGS__) -#define vmsgeu_vx_u16m2_b8_m(...) __riscv_vmsgeu_vx_u16m2_b8_mu(__VA_ARGS__) -#define vmsgeu_vv_u16m4_b4_m(...) __riscv_vmsgeu_vv_u16m4_b4_mu(__VA_ARGS__) -#define vmsgeu_vx_u16m4_b4_m(...) __riscv_vmsgeu_vx_u16m4_b4_mu(__VA_ARGS__) -#define vmsgeu_vv_u16m8_b2_m(...) __riscv_vmsgeu_vv_u16m8_b2_mu(__VA_ARGS__) -#define vmsgeu_vx_u16m8_b2_m(...) __riscv_vmsgeu_vx_u16m8_b2_mu(__VA_ARGS__) -#define vmsgeu_vv_u32mf2_b64_m(...) __riscv_vmsgeu_vv_u32mf2_b64_mu(__VA_ARGS__) -#define vmsgeu_vx_u32mf2_b64_m(...) __riscv_vmsgeu_vx_u32mf2_b64_mu(__VA_ARGS__) -#define vmsgeu_vv_u32m1_b32_m(...) __riscv_vmsgeu_vv_u32m1_b32_mu(__VA_ARGS__) -#define vmsgeu_vx_u32m1_b32_m(...) __riscv_vmsgeu_vx_u32m1_b32_mu(__VA_ARGS__) -#define vmsgeu_vv_u32m2_b16_m(...) __riscv_vmsgeu_vv_u32m2_b16_mu(__VA_ARGS__) -#define vmsgeu_vx_u32m2_b16_m(...) __riscv_vmsgeu_vx_u32m2_b16_mu(__VA_ARGS__) -#define vmsgeu_vv_u32m4_b8_m(...) __riscv_vmsgeu_vv_u32m4_b8_mu(__VA_ARGS__) -#define vmsgeu_vx_u32m4_b8_m(...) __riscv_vmsgeu_vx_u32m4_b8_mu(__VA_ARGS__) -#define vmsgeu_vv_u32m8_b4_m(...) __riscv_vmsgeu_vv_u32m8_b4_mu(__VA_ARGS__) -#define vmsgeu_vx_u32m8_b4_m(...) __riscv_vmsgeu_vx_u32m8_b4_mu(__VA_ARGS__) -#define vmsgeu_vv_u64m1_b64_m(...) __riscv_vmsgeu_vv_u64m1_b64_mu(__VA_ARGS__) -#define vmsgeu_vx_u64m1_b64_m(...) __riscv_vmsgeu_vx_u64m1_b64_mu(__VA_ARGS__) -#define vmsgeu_vv_u64m2_b32_m(...) __riscv_vmsgeu_vv_u64m2_b32_mu(__VA_ARGS__) -#define vmsgeu_vx_u64m2_b32_m(...) __riscv_vmsgeu_vx_u64m2_b32_mu(__VA_ARGS__) -#define vmsgeu_vv_u64m4_b16_m(...) __riscv_vmsgeu_vv_u64m4_b16_mu(__VA_ARGS__) -#define vmsgeu_vx_u64m4_b16_m(...) __riscv_vmsgeu_vx_u64m4_b16_mu(__VA_ARGS__) -#define vmsgeu_vv_u64m8_b8_m(...) __riscv_vmsgeu_vv_u64m8_b8_mu(__VA_ARGS__) -#define vmsgeu_vx_u64m8_b8_m(...) __riscv_vmsgeu_vx_u64m8_b8_mu(__VA_ARGS__) -#define vmin_vv_i8mf8(...) __riscv_vmin_vv_i8mf8(__VA_ARGS__) -#define vmin_vx_i8mf8(...) __riscv_vmin_vx_i8mf8(__VA_ARGS__) -#define vmin_vv_i8mf4(...) __riscv_vmin_vv_i8mf4(__VA_ARGS__) -#define vmin_vx_i8mf4(...) __riscv_vmin_vx_i8mf4(__VA_ARGS__) -#define vmin_vv_i8mf2(...) __riscv_vmin_vv_i8mf2(__VA_ARGS__) -#define vmin_vx_i8mf2(...) __riscv_vmin_vx_i8mf2(__VA_ARGS__) -#define vmin_vv_i8m1(...) __riscv_vmin_vv_i8m1(__VA_ARGS__) -#define vmin_vx_i8m1(...) __riscv_vmin_vx_i8m1(__VA_ARGS__) -#define vmin_vv_i8m2(...) __riscv_vmin_vv_i8m2(__VA_ARGS__) -#define vmin_vx_i8m2(...) __riscv_vmin_vx_i8m2(__VA_ARGS__) -#define vmin_vv_i8m4(...) __riscv_vmin_vv_i8m4(__VA_ARGS__) -#define vmin_vx_i8m4(...) __riscv_vmin_vx_i8m4(__VA_ARGS__) -#define vmin_vv_i8m8(...) __riscv_vmin_vv_i8m8(__VA_ARGS__) -#define vmin_vx_i8m8(...) __riscv_vmin_vx_i8m8(__VA_ARGS__) -#define vmin_vv_i16mf4(...) __riscv_vmin_vv_i16mf4(__VA_ARGS__) -#define vmin_vx_i16mf4(...) __riscv_vmin_vx_i16mf4(__VA_ARGS__) -#define vmin_vv_i16mf2(...) __riscv_vmin_vv_i16mf2(__VA_ARGS__) -#define vmin_vx_i16mf2(...) __riscv_vmin_vx_i16mf2(__VA_ARGS__) -#define vmin_vv_i16m1(...) __riscv_vmin_vv_i16m1(__VA_ARGS__) -#define vmin_vx_i16m1(...) __riscv_vmin_vx_i16m1(__VA_ARGS__) -#define vmin_vv_i16m2(...) __riscv_vmin_vv_i16m2(__VA_ARGS__) -#define vmin_vx_i16m2(...) __riscv_vmin_vx_i16m2(__VA_ARGS__) -#define vmin_vv_i16m4(...) __riscv_vmin_vv_i16m4(__VA_ARGS__) -#define vmin_vx_i16m4(...) __riscv_vmin_vx_i16m4(__VA_ARGS__) -#define vmin_vv_i16m8(...) __riscv_vmin_vv_i16m8(__VA_ARGS__) -#define vmin_vx_i16m8(...) __riscv_vmin_vx_i16m8(__VA_ARGS__) -#define vmin_vv_i32mf2(...) __riscv_vmin_vv_i32mf2(__VA_ARGS__) -#define vmin_vx_i32mf2(...) __riscv_vmin_vx_i32mf2(__VA_ARGS__) -#define vmin_vv_i32m1(...) __riscv_vmin_vv_i32m1(__VA_ARGS__) -#define vmin_vx_i32m1(...) __riscv_vmin_vx_i32m1(__VA_ARGS__) -#define vmin_vv_i32m2(...) __riscv_vmin_vv_i32m2(__VA_ARGS__) -#define vmin_vx_i32m2(...) __riscv_vmin_vx_i32m2(__VA_ARGS__) -#define vmin_vv_i32m4(...) __riscv_vmin_vv_i32m4(__VA_ARGS__) -#define vmin_vx_i32m4(...) __riscv_vmin_vx_i32m4(__VA_ARGS__) -#define vmin_vv_i32m8(...) __riscv_vmin_vv_i32m8(__VA_ARGS__) -#define vmin_vx_i32m8(...) __riscv_vmin_vx_i32m8(__VA_ARGS__) -#define vmin_vv_i64m1(...) __riscv_vmin_vv_i64m1(__VA_ARGS__) -#define vmin_vx_i64m1(...) __riscv_vmin_vx_i64m1(__VA_ARGS__) -#define vmin_vv_i64m2(...) __riscv_vmin_vv_i64m2(__VA_ARGS__) -#define vmin_vx_i64m2(...) __riscv_vmin_vx_i64m2(__VA_ARGS__) -#define vmin_vv_i64m4(...) __riscv_vmin_vv_i64m4(__VA_ARGS__) -#define vmin_vx_i64m4(...) __riscv_vmin_vx_i64m4(__VA_ARGS__) -#define vmin_vv_i64m8(...) __riscv_vmin_vv_i64m8(__VA_ARGS__) -#define vmin_vx_i64m8(...) __riscv_vmin_vx_i64m8(__VA_ARGS__) -#define vmax_vv_i8mf8(...) __riscv_vmax_vv_i8mf8(__VA_ARGS__) -#define vmax_vx_i8mf8(...) __riscv_vmax_vx_i8mf8(__VA_ARGS__) -#define vmax_vv_i8mf4(...) __riscv_vmax_vv_i8mf4(__VA_ARGS__) -#define vmax_vx_i8mf4(...) __riscv_vmax_vx_i8mf4(__VA_ARGS__) -#define vmax_vv_i8mf2(...) __riscv_vmax_vv_i8mf2(__VA_ARGS__) -#define vmax_vx_i8mf2(...) __riscv_vmax_vx_i8mf2(__VA_ARGS__) -#define vmax_vv_i8m1(...) __riscv_vmax_vv_i8m1(__VA_ARGS__) -#define vmax_vx_i8m1(...) __riscv_vmax_vx_i8m1(__VA_ARGS__) -#define vmax_vv_i8m2(...) __riscv_vmax_vv_i8m2(__VA_ARGS__) -#define vmax_vx_i8m2(...) __riscv_vmax_vx_i8m2(__VA_ARGS__) -#define vmax_vv_i8m4(...) __riscv_vmax_vv_i8m4(__VA_ARGS__) -#define vmax_vx_i8m4(...) __riscv_vmax_vx_i8m4(__VA_ARGS__) -#define vmax_vv_i8m8(...) __riscv_vmax_vv_i8m8(__VA_ARGS__) -#define vmax_vx_i8m8(...) __riscv_vmax_vx_i8m8(__VA_ARGS__) -#define vmax_vv_i16mf4(...) __riscv_vmax_vv_i16mf4(__VA_ARGS__) -#define vmax_vx_i16mf4(...) __riscv_vmax_vx_i16mf4(__VA_ARGS__) -#define vmax_vv_i16mf2(...) __riscv_vmax_vv_i16mf2(__VA_ARGS__) -#define vmax_vx_i16mf2(...) __riscv_vmax_vx_i16mf2(__VA_ARGS__) -#define vmax_vv_i16m1(...) __riscv_vmax_vv_i16m1(__VA_ARGS__) -#define vmax_vx_i16m1(...) __riscv_vmax_vx_i16m1(__VA_ARGS__) -#define vmax_vv_i16m2(...) __riscv_vmax_vv_i16m2(__VA_ARGS__) -#define vmax_vx_i16m2(...) __riscv_vmax_vx_i16m2(__VA_ARGS__) -#define vmax_vv_i16m4(...) __riscv_vmax_vv_i16m4(__VA_ARGS__) -#define vmax_vx_i16m4(...) __riscv_vmax_vx_i16m4(__VA_ARGS__) -#define vmax_vv_i16m8(...) __riscv_vmax_vv_i16m8(__VA_ARGS__) -#define vmax_vx_i16m8(...) __riscv_vmax_vx_i16m8(__VA_ARGS__) -#define vmax_vv_i32mf2(...) __riscv_vmax_vv_i32mf2(__VA_ARGS__) -#define vmax_vx_i32mf2(...) __riscv_vmax_vx_i32mf2(__VA_ARGS__) -#define vmax_vv_i32m1(...) __riscv_vmax_vv_i32m1(__VA_ARGS__) -#define vmax_vx_i32m1(...) __riscv_vmax_vx_i32m1(__VA_ARGS__) -#define vmax_vv_i32m2(...) __riscv_vmax_vv_i32m2(__VA_ARGS__) -#define vmax_vx_i32m2(...) __riscv_vmax_vx_i32m2(__VA_ARGS__) -#define vmax_vv_i32m4(...) __riscv_vmax_vv_i32m4(__VA_ARGS__) -#define vmax_vx_i32m4(...) __riscv_vmax_vx_i32m4(__VA_ARGS__) -#define vmax_vv_i32m8(...) __riscv_vmax_vv_i32m8(__VA_ARGS__) -#define vmax_vx_i32m8(...) __riscv_vmax_vx_i32m8(__VA_ARGS__) -#define vmax_vv_i64m1(...) __riscv_vmax_vv_i64m1(__VA_ARGS__) -#define vmax_vx_i64m1(...) __riscv_vmax_vx_i64m1(__VA_ARGS__) -#define vmax_vv_i64m2(...) __riscv_vmax_vv_i64m2(__VA_ARGS__) -#define vmax_vx_i64m2(...) __riscv_vmax_vx_i64m2(__VA_ARGS__) -#define vmax_vv_i64m4(...) __riscv_vmax_vv_i64m4(__VA_ARGS__) -#define vmax_vx_i64m4(...) __riscv_vmax_vx_i64m4(__VA_ARGS__) -#define vmax_vv_i64m8(...) __riscv_vmax_vv_i64m8(__VA_ARGS__) -#define vmax_vx_i64m8(...) __riscv_vmax_vx_i64m8(__VA_ARGS__) -#define vminu_vv_u8mf8(...) __riscv_vminu_vv_u8mf8(__VA_ARGS__) -#define vminu_vx_u8mf8(...) __riscv_vminu_vx_u8mf8(__VA_ARGS__) -#define vminu_vv_u8mf4(...) __riscv_vminu_vv_u8mf4(__VA_ARGS__) -#define vminu_vx_u8mf4(...) __riscv_vminu_vx_u8mf4(__VA_ARGS__) -#define vminu_vv_u8mf2(...) __riscv_vminu_vv_u8mf2(__VA_ARGS__) -#define vminu_vx_u8mf2(...) __riscv_vminu_vx_u8mf2(__VA_ARGS__) -#define vminu_vv_u8m1(...) __riscv_vminu_vv_u8m1(__VA_ARGS__) -#define vminu_vx_u8m1(...) __riscv_vminu_vx_u8m1(__VA_ARGS__) -#define vminu_vv_u8m2(...) __riscv_vminu_vv_u8m2(__VA_ARGS__) -#define vminu_vx_u8m2(...) __riscv_vminu_vx_u8m2(__VA_ARGS__) -#define vminu_vv_u8m4(...) __riscv_vminu_vv_u8m4(__VA_ARGS__) -#define vminu_vx_u8m4(...) __riscv_vminu_vx_u8m4(__VA_ARGS__) -#define vminu_vv_u8m8(...) __riscv_vminu_vv_u8m8(__VA_ARGS__) -#define vminu_vx_u8m8(...) __riscv_vminu_vx_u8m8(__VA_ARGS__) -#define vminu_vv_u16mf4(...) __riscv_vminu_vv_u16mf4(__VA_ARGS__) -#define vminu_vx_u16mf4(...) __riscv_vminu_vx_u16mf4(__VA_ARGS__) -#define vminu_vv_u16mf2(...) __riscv_vminu_vv_u16mf2(__VA_ARGS__) -#define vminu_vx_u16mf2(...) __riscv_vminu_vx_u16mf2(__VA_ARGS__) -#define vminu_vv_u16m1(...) __riscv_vminu_vv_u16m1(__VA_ARGS__) -#define vminu_vx_u16m1(...) __riscv_vminu_vx_u16m1(__VA_ARGS__) -#define vminu_vv_u16m2(...) __riscv_vminu_vv_u16m2(__VA_ARGS__) -#define vminu_vx_u16m2(...) __riscv_vminu_vx_u16m2(__VA_ARGS__) -#define vminu_vv_u16m4(...) __riscv_vminu_vv_u16m4(__VA_ARGS__) -#define vminu_vx_u16m4(...) __riscv_vminu_vx_u16m4(__VA_ARGS__) -#define vminu_vv_u16m8(...) __riscv_vminu_vv_u16m8(__VA_ARGS__) -#define vminu_vx_u16m8(...) __riscv_vminu_vx_u16m8(__VA_ARGS__) -#define vminu_vv_u32mf2(...) __riscv_vminu_vv_u32mf2(__VA_ARGS__) -#define vminu_vx_u32mf2(...) __riscv_vminu_vx_u32mf2(__VA_ARGS__) -#define vminu_vv_u32m1(...) __riscv_vminu_vv_u32m1(__VA_ARGS__) -#define vminu_vx_u32m1(...) __riscv_vminu_vx_u32m1(__VA_ARGS__) -#define vminu_vv_u32m2(...) __riscv_vminu_vv_u32m2(__VA_ARGS__) -#define vminu_vx_u32m2(...) __riscv_vminu_vx_u32m2(__VA_ARGS__) -#define vminu_vv_u32m4(...) __riscv_vminu_vv_u32m4(__VA_ARGS__) -#define vminu_vx_u32m4(...) __riscv_vminu_vx_u32m4(__VA_ARGS__) -#define vminu_vv_u32m8(...) __riscv_vminu_vv_u32m8(__VA_ARGS__) -#define vminu_vx_u32m8(...) __riscv_vminu_vx_u32m8(__VA_ARGS__) -#define vminu_vv_u64m1(...) __riscv_vminu_vv_u64m1(__VA_ARGS__) -#define vminu_vx_u64m1(...) __riscv_vminu_vx_u64m1(__VA_ARGS__) -#define vminu_vv_u64m2(...) __riscv_vminu_vv_u64m2(__VA_ARGS__) -#define vminu_vx_u64m2(...) __riscv_vminu_vx_u64m2(__VA_ARGS__) -#define vminu_vv_u64m4(...) __riscv_vminu_vv_u64m4(__VA_ARGS__) -#define vminu_vx_u64m4(...) __riscv_vminu_vx_u64m4(__VA_ARGS__) -#define vminu_vv_u64m8(...) __riscv_vminu_vv_u64m8(__VA_ARGS__) -#define vminu_vx_u64m8(...) __riscv_vminu_vx_u64m8(__VA_ARGS__) -#define vmaxu_vv_u8mf8(...) __riscv_vmaxu_vv_u8mf8(__VA_ARGS__) -#define vmaxu_vx_u8mf8(...) __riscv_vmaxu_vx_u8mf8(__VA_ARGS__) -#define vmaxu_vv_u8mf4(...) __riscv_vmaxu_vv_u8mf4(__VA_ARGS__) -#define vmaxu_vx_u8mf4(...) __riscv_vmaxu_vx_u8mf4(__VA_ARGS__) -#define vmaxu_vv_u8mf2(...) __riscv_vmaxu_vv_u8mf2(__VA_ARGS__) -#define vmaxu_vx_u8mf2(...) __riscv_vmaxu_vx_u8mf2(__VA_ARGS__) -#define vmaxu_vv_u8m1(...) __riscv_vmaxu_vv_u8m1(__VA_ARGS__) -#define vmaxu_vx_u8m1(...) __riscv_vmaxu_vx_u8m1(__VA_ARGS__) -#define vmaxu_vv_u8m2(...) __riscv_vmaxu_vv_u8m2(__VA_ARGS__) -#define vmaxu_vx_u8m2(...) __riscv_vmaxu_vx_u8m2(__VA_ARGS__) -#define vmaxu_vv_u8m4(...) __riscv_vmaxu_vv_u8m4(__VA_ARGS__) -#define vmaxu_vx_u8m4(...) __riscv_vmaxu_vx_u8m4(__VA_ARGS__) -#define vmaxu_vv_u8m8(...) __riscv_vmaxu_vv_u8m8(__VA_ARGS__) -#define vmaxu_vx_u8m8(...) __riscv_vmaxu_vx_u8m8(__VA_ARGS__) -#define vmaxu_vv_u16mf4(...) __riscv_vmaxu_vv_u16mf4(__VA_ARGS__) -#define vmaxu_vx_u16mf4(...) __riscv_vmaxu_vx_u16mf4(__VA_ARGS__) -#define vmaxu_vv_u16mf2(...) __riscv_vmaxu_vv_u16mf2(__VA_ARGS__) -#define vmaxu_vx_u16mf2(...) __riscv_vmaxu_vx_u16mf2(__VA_ARGS__) -#define vmaxu_vv_u16m1(...) __riscv_vmaxu_vv_u16m1(__VA_ARGS__) -#define vmaxu_vx_u16m1(...) __riscv_vmaxu_vx_u16m1(__VA_ARGS__) -#define vmaxu_vv_u16m2(...) __riscv_vmaxu_vv_u16m2(__VA_ARGS__) -#define vmaxu_vx_u16m2(...) __riscv_vmaxu_vx_u16m2(__VA_ARGS__) -#define vmaxu_vv_u16m4(...) __riscv_vmaxu_vv_u16m4(__VA_ARGS__) -#define vmaxu_vx_u16m4(...) __riscv_vmaxu_vx_u16m4(__VA_ARGS__) -#define vmaxu_vv_u16m8(...) __riscv_vmaxu_vv_u16m8(__VA_ARGS__) -#define vmaxu_vx_u16m8(...) __riscv_vmaxu_vx_u16m8(__VA_ARGS__) -#define vmaxu_vv_u32mf2(...) __riscv_vmaxu_vv_u32mf2(__VA_ARGS__) -#define vmaxu_vx_u32mf2(...) __riscv_vmaxu_vx_u32mf2(__VA_ARGS__) -#define vmaxu_vv_u32m1(...) __riscv_vmaxu_vv_u32m1(__VA_ARGS__) -#define vmaxu_vx_u32m1(...) __riscv_vmaxu_vx_u32m1(__VA_ARGS__) -#define vmaxu_vv_u32m2(...) __riscv_vmaxu_vv_u32m2(__VA_ARGS__) -#define vmaxu_vx_u32m2(...) __riscv_vmaxu_vx_u32m2(__VA_ARGS__) -#define vmaxu_vv_u32m4(...) __riscv_vmaxu_vv_u32m4(__VA_ARGS__) -#define vmaxu_vx_u32m4(...) __riscv_vmaxu_vx_u32m4(__VA_ARGS__) -#define vmaxu_vv_u32m8(...) __riscv_vmaxu_vv_u32m8(__VA_ARGS__) -#define vmaxu_vx_u32m8(...) __riscv_vmaxu_vx_u32m8(__VA_ARGS__) -#define vmaxu_vv_u64m1(...) __riscv_vmaxu_vv_u64m1(__VA_ARGS__) -#define vmaxu_vx_u64m1(...) __riscv_vmaxu_vx_u64m1(__VA_ARGS__) -#define vmaxu_vv_u64m2(...) __riscv_vmaxu_vv_u64m2(__VA_ARGS__) -#define vmaxu_vx_u64m2(...) __riscv_vmaxu_vx_u64m2(__VA_ARGS__) -#define vmaxu_vv_u64m4(...) __riscv_vmaxu_vv_u64m4(__VA_ARGS__) -#define vmaxu_vx_u64m4(...) __riscv_vmaxu_vx_u64m4(__VA_ARGS__) -#define vmaxu_vv_u64m8(...) __riscv_vmaxu_vv_u64m8(__VA_ARGS__) -#define vmaxu_vx_u64m8(...) __riscv_vmaxu_vx_u64m8(__VA_ARGS__) -// masked functions -#define vmin_vv_i8mf8_m(...) __riscv_vmin_vv_i8mf8_tumu(__VA_ARGS__) -#define vmin_vx_i8mf8_m(...) __riscv_vmin_vx_i8mf8_tumu(__VA_ARGS__) -#define vmin_vv_i8mf4_m(...) __riscv_vmin_vv_i8mf4_tumu(__VA_ARGS__) -#define vmin_vx_i8mf4_m(...) __riscv_vmin_vx_i8mf4_tumu(__VA_ARGS__) -#define vmin_vv_i8mf2_m(...) __riscv_vmin_vv_i8mf2_tumu(__VA_ARGS__) -#define vmin_vx_i8mf2_m(...) __riscv_vmin_vx_i8mf2_tumu(__VA_ARGS__) -#define vmin_vv_i8m1_m(...) __riscv_vmin_vv_i8m1_tumu(__VA_ARGS__) -#define vmin_vx_i8m1_m(...) __riscv_vmin_vx_i8m1_tumu(__VA_ARGS__) -#define vmin_vv_i8m2_m(...) __riscv_vmin_vv_i8m2_tumu(__VA_ARGS__) -#define vmin_vx_i8m2_m(...) __riscv_vmin_vx_i8m2_tumu(__VA_ARGS__) -#define vmin_vv_i8m4_m(...) __riscv_vmin_vv_i8m4_tumu(__VA_ARGS__) -#define vmin_vx_i8m4_m(...) __riscv_vmin_vx_i8m4_tumu(__VA_ARGS__) -#define vmin_vv_i8m8_m(...) __riscv_vmin_vv_i8m8_tumu(__VA_ARGS__) -#define vmin_vx_i8m8_m(...) __riscv_vmin_vx_i8m8_tumu(__VA_ARGS__) -#define vmin_vv_i16mf4_m(...) __riscv_vmin_vv_i16mf4_tumu(__VA_ARGS__) -#define vmin_vx_i16mf4_m(...) __riscv_vmin_vx_i16mf4_tumu(__VA_ARGS__) -#define vmin_vv_i16mf2_m(...) __riscv_vmin_vv_i16mf2_tumu(__VA_ARGS__) -#define vmin_vx_i16mf2_m(...) __riscv_vmin_vx_i16mf2_tumu(__VA_ARGS__) -#define vmin_vv_i16m1_m(...) __riscv_vmin_vv_i16m1_tumu(__VA_ARGS__) -#define vmin_vx_i16m1_m(...) __riscv_vmin_vx_i16m1_tumu(__VA_ARGS__) -#define vmin_vv_i16m2_m(...) __riscv_vmin_vv_i16m2_tumu(__VA_ARGS__) -#define vmin_vx_i16m2_m(...) __riscv_vmin_vx_i16m2_tumu(__VA_ARGS__) -#define vmin_vv_i16m4_m(...) __riscv_vmin_vv_i16m4_tumu(__VA_ARGS__) -#define vmin_vx_i16m4_m(...) __riscv_vmin_vx_i16m4_tumu(__VA_ARGS__) -#define vmin_vv_i16m8_m(...) __riscv_vmin_vv_i16m8_tumu(__VA_ARGS__) -#define vmin_vx_i16m8_m(...) __riscv_vmin_vx_i16m8_tumu(__VA_ARGS__) -#define vmin_vv_i32mf2_m(...) __riscv_vmin_vv_i32mf2_tumu(__VA_ARGS__) -#define vmin_vx_i32mf2_m(...) __riscv_vmin_vx_i32mf2_tumu(__VA_ARGS__) -#define vmin_vv_i32m1_m(...) __riscv_vmin_vv_i32m1_tumu(__VA_ARGS__) -#define vmin_vx_i32m1_m(...) __riscv_vmin_vx_i32m1_tumu(__VA_ARGS__) -#define vmin_vv_i32m2_m(...) __riscv_vmin_vv_i32m2_tumu(__VA_ARGS__) -#define vmin_vx_i32m2_m(...) __riscv_vmin_vx_i32m2_tumu(__VA_ARGS__) -#define vmin_vv_i32m4_m(...) __riscv_vmin_vv_i32m4_tumu(__VA_ARGS__) -#define vmin_vx_i32m4_m(...) __riscv_vmin_vx_i32m4_tumu(__VA_ARGS__) -#define vmin_vv_i32m8_m(...) __riscv_vmin_vv_i32m8_tumu(__VA_ARGS__) -#define vmin_vx_i32m8_m(...) __riscv_vmin_vx_i32m8_tumu(__VA_ARGS__) -#define vmin_vv_i64m1_m(...) __riscv_vmin_vv_i64m1_tumu(__VA_ARGS__) -#define vmin_vx_i64m1_m(...) __riscv_vmin_vx_i64m1_tumu(__VA_ARGS__) -#define vmin_vv_i64m2_m(...) __riscv_vmin_vv_i64m2_tumu(__VA_ARGS__) -#define vmin_vx_i64m2_m(...) __riscv_vmin_vx_i64m2_tumu(__VA_ARGS__) -#define vmin_vv_i64m4_m(...) __riscv_vmin_vv_i64m4_tumu(__VA_ARGS__) -#define vmin_vx_i64m4_m(...) __riscv_vmin_vx_i64m4_tumu(__VA_ARGS__) -#define vmin_vv_i64m8_m(...) __riscv_vmin_vv_i64m8_tumu(__VA_ARGS__) -#define vmin_vx_i64m8_m(...) __riscv_vmin_vx_i64m8_tumu(__VA_ARGS__) -#define vmax_vv_i8mf8_m(...) __riscv_vmax_vv_i8mf8_tumu(__VA_ARGS__) -#define vmax_vx_i8mf8_m(...) __riscv_vmax_vx_i8mf8_tumu(__VA_ARGS__) -#define vmax_vv_i8mf4_m(...) __riscv_vmax_vv_i8mf4_tumu(__VA_ARGS__) -#define vmax_vx_i8mf4_m(...) __riscv_vmax_vx_i8mf4_tumu(__VA_ARGS__) -#define vmax_vv_i8mf2_m(...) __riscv_vmax_vv_i8mf2_tumu(__VA_ARGS__) -#define vmax_vx_i8mf2_m(...) __riscv_vmax_vx_i8mf2_tumu(__VA_ARGS__) -#define vmax_vv_i8m1_m(...) __riscv_vmax_vv_i8m1_tumu(__VA_ARGS__) -#define vmax_vx_i8m1_m(...) __riscv_vmax_vx_i8m1_tumu(__VA_ARGS__) -#define vmax_vv_i8m2_m(...) __riscv_vmax_vv_i8m2_tumu(__VA_ARGS__) -#define vmax_vx_i8m2_m(...) __riscv_vmax_vx_i8m2_tumu(__VA_ARGS__) -#define vmax_vv_i8m4_m(...) __riscv_vmax_vv_i8m4_tumu(__VA_ARGS__) -#define vmax_vx_i8m4_m(...) __riscv_vmax_vx_i8m4_tumu(__VA_ARGS__) -#define vmax_vv_i8m8_m(...) __riscv_vmax_vv_i8m8_tumu(__VA_ARGS__) -#define vmax_vx_i8m8_m(...) __riscv_vmax_vx_i8m8_tumu(__VA_ARGS__) -#define vmax_vv_i16mf4_m(...) __riscv_vmax_vv_i16mf4_tumu(__VA_ARGS__) -#define vmax_vx_i16mf4_m(...) __riscv_vmax_vx_i16mf4_tumu(__VA_ARGS__) -#define vmax_vv_i16mf2_m(...) __riscv_vmax_vv_i16mf2_tumu(__VA_ARGS__) -#define vmax_vx_i16mf2_m(...) __riscv_vmax_vx_i16mf2_tumu(__VA_ARGS__) -#define vmax_vv_i16m1_m(...) __riscv_vmax_vv_i16m1_tumu(__VA_ARGS__) -#define vmax_vx_i16m1_m(...) __riscv_vmax_vx_i16m1_tumu(__VA_ARGS__) -#define vmax_vv_i16m2_m(...) __riscv_vmax_vv_i16m2_tumu(__VA_ARGS__) -#define vmax_vx_i16m2_m(...) __riscv_vmax_vx_i16m2_tumu(__VA_ARGS__) -#define vmax_vv_i16m4_m(...) __riscv_vmax_vv_i16m4_tumu(__VA_ARGS__) -#define vmax_vx_i16m4_m(...) __riscv_vmax_vx_i16m4_tumu(__VA_ARGS__) -#define vmax_vv_i16m8_m(...) __riscv_vmax_vv_i16m8_tumu(__VA_ARGS__) -#define vmax_vx_i16m8_m(...) __riscv_vmax_vx_i16m8_tumu(__VA_ARGS__) -#define vmax_vv_i32mf2_m(...) __riscv_vmax_vv_i32mf2_tumu(__VA_ARGS__) -#define vmax_vx_i32mf2_m(...) __riscv_vmax_vx_i32mf2_tumu(__VA_ARGS__) -#define vmax_vv_i32m1_m(...) __riscv_vmax_vv_i32m1_tumu(__VA_ARGS__) -#define vmax_vx_i32m1_m(...) __riscv_vmax_vx_i32m1_tumu(__VA_ARGS__) -#define vmax_vv_i32m2_m(...) __riscv_vmax_vv_i32m2_tumu(__VA_ARGS__) -#define vmax_vx_i32m2_m(...) __riscv_vmax_vx_i32m2_tumu(__VA_ARGS__) -#define vmax_vv_i32m4_m(...) __riscv_vmax_vv_i32m4_tumu(__VA_ARGS__) -#define vmax_vx_i32m4_m(...) __riscv_vmax_vx_i32m4_tumu(__VA_ARGS__) -#define vmax_vv_i32m8_m(...) __riscv_vmax_vv_i32m8_tumu(__VA_ARGS__) -#define vmax_vx_i32m8_m(...) __riscv_vmax_vx_i32m8_tumu(__VA_ARGS__) -#define vmax_vv_i64m1_m(...) __riscv_vmax_vv_i64m1_tumu(__VA_ARGS__) -#define vmax_vx_i64m1_m(...) __riscv_vmax_vx_i64m1_tumu(__VA_ARGS__) -#define vmax_vv_i64m2_m(...) __riscv_vmax_vv_i64m2_tumu(__VA_ARGS__) -#define vmax_vx_i64m2_m(...) __riscv_vmax_vx_i64m2_tumu(__VA_ARGS__) -#define vmax_vv_i64m4_m(...) __riscv_vmax_vv_i64m4_tumu(__VA_ARGS__) -#define vmax_vx_i64m4_m(...) __riscv_vmax_vx_i64m4_tumu(__VA_ARGS__) -#define vmax_vv_i64m8_m(...) __riscv_vmax_vv_i64m8_tumu(__VA_ARGS__) -#define vmax_vx_i64m8_m(...) __riscv_vmax_vx_i64m8_tumu(__VA_ARGS__) -#define vminu_vv_u8mf8_m(...) __riscv_vminu_vv_u8mf8_tumu(__VA_ARGS__) -#define vminu_vx_u8mf8_m(...) __riscv_vminu_vx_u8mf8_tumu(__VA_ARGS__) -#define vminu_vv_u8mf4_m(...) __riscv_vminu_vv_u8mf4_tumu(__VA_ARGS__) -#define vminu_vx_u8mf4_m(...) __riscv_vminu_vx_u8mf4_tumu(__VA_ARGS__) -#define vminu_vv_u8mf2_m(...) __riscv_vminu_vv_u8mf2_tumu(__VA_ARGS__) -#define vminu_vx_u8mf2_m(...) __riscv_vminu_vx_u8mf2_tumu(__VA_ARGS__) -#define vminu_vv_u8m1_m(...) __riscv_vminu_vv_u8m1_tumu(__VA_ARGS__) -#define vminu_vx_u8m1_m(...) __riscv_vminu_vx_u8m1_tumu(__VA_ARGS__) -#define vminu_vv_u8m2_m(...) __riscv_vminu_vv_u8m2_tumu(__VA_ARGS__) -#define vminu_vx_u8m2_m(...) __riscv_vminu_vx_u8m2_tumu(__VA_ARGS__) -#define vminu_vv_u8m4_m(...) __riscv_vminu_vv_u8m4_tumu(__VA_ARGS__) -#define vminu_vx_u8m4_m(...) __riscv_vminu_vx_u8m4_tumu(__VA_ARGS__) -#define vminu_vv_u8m8_m(...) __riscv_vminu_vv_u8m8_tumu(__VA_ARGS__) -#define vminu_vx_u8m8_m(...) __riscv_vminu_vx_u8m8_tumu(__VA_ARGS__) -#define vminu_vv_u16mf4_m(...) __riscv_vminu_vv_u16mf4_tumu(__VA_ARGS__) -#define vminu_vx_u16mf4_m(...) __riscv_vminu_vx_u16mf4_tumu(__VA_ARGS__) -#define vminu_vv_u16mf2_m(...) __riscv_vminu_vv_u16mf2_tumu(__VA_ARGS__) -#define vminu_vx_u16mf2_m(...) __riscv_vminu_vx_u16mf2_tumu(__VA_ARGS__) -#define vminu_vv_u16m1_m(...) __riscv_vminu_vv_u16m1_tumu(__VA_ARGS__) -#define vminu_vx_u16m1_m(...) __riscv_vminu_vx_u16m1_tumu(__VA_ARGS__) -#define vminu_vv_u16m2_m(...) __riscv_vminu_vv_u16m2_tumu(__VA_ARGS__) -#define vminu_vx_u16m2_m(...) __riscv_vminu_vx_u16m2_tumu(__VA_ARGS__) -#define vminu_vv_u16m4_m(...) __riscv_vminu_vv_u16m4_tumu(__VA_ARGS__) -#define vminu_vx_u16m4_m(...) __riscv_vminu_vx_u16m4_tumu(__VA_ARGS__) -#define vminu_vv_u16m8_m(...) __riscv_vminu_vv_u16m8_tumu(__VA_ARGS__) -#define vminu_vx_u16m8_m(...) __riscv_vminu_vx_u16m8_tumu(__VA_ARGS__) -#define vminu_vv_u32mf2_m(...) __riscv_vminu_vv_u32mf2_tumu(__VA_ARGS__) -#define vminu_vx_u32mf2_m(...) __riscv_vminu_vx_u32mf2_tumu(__VA_ARGS__) -#define vminu_vv_u32m1_m(...) __riscv_vminu_vv_u32m1_tumu(__VA_ARGS__) -#define vminu_vx_u32m1_m(...) __riscv_vminu_vx_u32m1_tumu(__VA_ARGS__) -#define vminu_vv_u32m2_m(...) __riscv_vminu_vv_u32m2_tumu(__VA_ARGS__) -#define vminu_vx_u32m2_m(...) __riscv_vminu_vx_u32m2_tumu(__VA_ARGS__) -#define vminu_vv_u32m4_m(...) __riscv_vminu_vv_u32m4_tumu(__VA_ARGS__) -#define vminu_vx_u32m4_m(...) __riscv_vminu_vx_u32m4_tumu(__VA_ARGS__) -#define vminu_vv_u32m8_m(...) __riscv_vminu_vv_u32m8_tumu(__VA_ARGS__) -#define vminu_vx_u32m8_m(...) __riscv_vminu_vx_u32m8_tumu(__VA_ARGS__) -#define vminu_vv_u64m1_m(...) __riscv_vminu_vv_u64m1_tumu(__VA_ARGS__) -#define vminu_vx_u64m1_m(...) __riscv_vminu_vx_u64m1_tumu(__VA_ARGS__) -#define vminu_vv_u64m2_m(...) __riscv_vminu_vv_u64m2_tumu(__VA_ARGS__) -#define vminu_vx_u64m2_m(...) __riscv_vminu_vx_u64m2_tumu(__VA_ARGS__) -#define vminu_vv_u64m4_m(...) __riscv_vminu_vv_u64m4_tumu(__VA_ARGS__) -#define vminu_vx_u64m4_m(...) __riscv_vminu_vx_u64m4_tumu(__VA_ARGS__) -#define vminu_vv_u64m8_m(...) __riscv_vminu_vv_u64m8_tumu(__VA_ARGS__) -#define vminu_vx_u64m8_m(...) __riscv_vminu_vx_u64m8_tumu(__VA_ARGS__) -#define vmaxu_vv_u8mf8_m(...) __riscv_vmaxu_vv_u8mf8_tumu(__VA_ARGS__) -#define vmaxu_vx_u8mf8_m(...) __riscv_vmaxu_vx_u8mf8_tumu(__VA_ARGS__) -#define vmaxu_vv_u8mf4_m(...) __riscv_vmaxu_vv_u8mf4_tumu(__VA_ARGS__) -#define vmaxu_vx_u8mf4_m(...) __riscv_vmaxu_vx_u8mf4_tumu(__VA_ARGS__) -#define vmaxu_vv_u8mf2_m(...) __riscv_vmaxu_vv_u8mf2_tumu(__VA_ARGS__) -#define vmaxu_vx_u8mf2_m(...) __riscv_vmaxu_vx_u8mf2_tumu(__VA_ARGS__) -#define vmaxu_vv_u8m1_m(...) __riscv_vmaxu_vv_u8m1_tumu(__VA_ARGS__) -#define vmaxu_vx_u8m1_m(...) __riscv_vmaxu_vx_u8m1_tumu(__VA_ARGS__) -#define vmaxu_vv_u8m2_m(...) __riscv_vmaxu_vv_u8m2_tumu(__VA_ARGS__) -#define vmaxu_vx_u8m2_m(...) __riscv_vmaxu_vx_u8m2_tumu(__VA_ARGS__) -#define vmaxu_vv_u8m4_m(...) __riscv_vmaxu_vv_u8m4_tumu(__VA_ARGS__) -#define vmaxu_vx_u8m4_m(...) __riscv_vmaxu_vx_u8m4_tumu(__VA_ARGS__) -#define vmaxu_vv_u8m8_m(...) __riscv_vmaxu_vv_u8m8_tumu(__VA_ARGS__) -#define vmaxu_vx_u8m8_m(...) __riscv_vmaxu_vx_u8m8_tumu(__VA_ARGS__) -#define vmaxu_vv_u16mf4_m(...) __riscv_vmaxu_vv_u16mf4_tumu(__VA_ARGS__) -#define vmaxu_vx_u16mf4_m(...) __riscv_vmaxu_vx_u16mf4_tumu(__VA_ARGS__) -#define vmaxu_vv_u16mf2_m(...) __riscv_vmaxu_vv_u16mf2_tumu(__VA_ARGS__) -#define vmaxu_vx_u16mf2_m(...) __riscv_vmaxu_vx_u16mf2_tumu(__VA_ARGS__) -#define vmaxu_vv_u16m1_m(...) __riscv_vmaxu_vv_u16m1_tumu(__VA_ARGS__) -#define vmaxu_vx_u16m1_m(...) __riscv_vmaxu_vx_u16m1_tumu(__VA_ARGS__) -#define vmaxu_vv_u16m2_m(...) __riscv_vmaxu_vv_u16m2_tumu(__VA_ARGS__) -#define vmaxu_vx_u16m2_m(...) __riscv_vmaxu_vx_u16m2_tumu(__VA_ARGS__) -#define vmaxu_vv_u16m4_m(...) __riscv_vmaxu_vv_u16m4_tumu(__VA_ARGS__) -#define vmaxu_vx_u16m4_m(...) __riscv_vmaxu_vx_u16m4_tumu(__VA_ARGS__) -#define vmaxu_vv_u16m8_m(...) __riscv_vmaxu_vv_u16m8_tumu(__VA_ARGS__) -#define vmaxu_vx_u16m8_m(...) __riscv_vmaxu_vx_u16m8_tumu(__VA_ARGS__) -#define vmaxu_vv_u32mf2_m(...) __riscv_vmaxu_vv_u32mf2_tumu(__VA_ARGS__) -#define vmaxu_vx_u32mf2_m(...) __riscv_vmaxu_vx_u32mf2_tumu(__VA_ARGS__) -#define vmaxu_vv_u32m1_m(...) __riscv_vmaxu_vv_u32m1_tumu(__VA_ARGS__) -#define vmaxu_vx_u32m1_m(...) __riscv_vmaxu_vx_u32m1_tumu(__VA_ARGS__) -#define vmaxu_vv_u32m2_m(...) __riscv_vmaxu_vv_u32m2_tumu(__VA_ARGS__) -#define vmaxu_vx_u32m2_m(...) __riscv_vmaxu_vx_u32m2_tumu(__VA_ARGS__) -#define vmaxu_vv_u32m4_m(...) __riscv_vmaxu_vv_u32m4_tumu(__VA_ARGS__) -#define vmaxu_vx_u32m4_m(...) __riscv_vmaxu_vx_u32m4_tumu(__VA_ARGS__) -#define vmaxu_vv_u32m8_m(...) __riscv_vmaxu_vv_u32m8_tumu(__VA_ARGS__) -#define vmaxu_vx_u32m8_m(...) __riscv_vmaxu_vx_u32m8_tumu(__VA_ARGS__) -#define vmaxu_vv_u64m1_m(...) __riscv_vmaxu_vv_u64m1_tumu(__VA_ARGS__) -#define vmaxu_vx_u64m1_m(...) __riscv_vmaxu_vx_u64m1_tumu(__VA_ARGS__) -#define vmaxu_vv_u64m2_m(...) __riscv_vmaxu_vv_u64m2_tumu(__VA_ARGS__) -#define vmaxu_vx_u64m2_m(...) __riscv_vmaxu_vx_u64m2_tumu(__VA_ARGS__) -#define vmaxu_vv_u64m4_m(...) __riscv_vmaxu_vv_u64m4_tumu(__VA_ARGS__) -#define vmaxu_vx_u64m4_m(...) __riscv_vmaxu_vx_u64m4_tumu(__VA_ARGS__) -#define vmaxu_vv_u64m8_m(...) __riscv_vmaxu_vv_u64m8_tumu(__VA_ARGS__) -#define vmaxu_vx_u64m8_m(...) __riscv_vmaxu_vx_u64m8_tumu(__VA_ARGS__) -#define vmul_vv_i8mf8(...) __riscv_vmul_vv_i8mf8(__VA_ARGS__) -#define vmul_vx_i8mf8(...) __riscv_vmul_vx_i8mf8(__VA_ARGS__) -#define vmul_vv_i8mf4(...) __riscv_vmul_vv_i8mf4(__VA_ARGS__) -#define vmul_vx_i8mf4(...) __riscv_vmul_vx_i8mf4(__VA_ARGS__) -#define vmul_vv_i8mf2(...) __riscv_vmul_vv_i8mf2(__VA_ARGS__) -#define vmul_vx_i8mf2(...) __riscv_vmul_vx_i8mf2(__VA_ARGS__) -#define vmul_vv_i8m1(...) __riscv_vmul_vv_i8m1(__VA_ARGS__) -#define vmul_vx_i8m1(...) __riscv_vmul_vx_i8m1(__VA_ARGS__) -#define vmul_vv_i8m2(...) __riscv_vmul_vv_i8m2(__VA_ARGS__) -#define vmul_vx_i8m2(...) __riscv_vmul_vx_i8m2(__VA_ARGS__) -#define vmul_vv_i8m4(...) __riscv_vmul_vv_i8m4(__VA_ARGS__) -#define vmul_vx_i8m4(...) __riscv_vmul_vx_i8m4(__VA_ARGS__) -#define vmul_vv_i8m8(...) __riscv_vmul_vv_i8m8(__VA_ARGS__) -#define vmul_vx_i8m8(...) __riscv_vmul_vx_i8m8(__VA_ARGS__) -#define vmul_vv_i16mf4(...) __riscv_vmul_vv_i16mf4(__VA_ARGS__) -#define vmul_vx_i16mf4(...) __riscv_vmul_vx_i16mf4(__VA_ARGS__) -#define vmul_vv_i16mf2(...) __riscv_vmul_vv_i16mf2(__VA_ARGS__) -#define vmul_vx_i16mf2(...) __riscv_vmul_vx_i16mf2(__VA_ARGS__) -#define vmul_vv_i16m1(...) __riscv_vmul_vv_i16m1(__VA_ARGS__) -#define vmul_vx_i16m1(...) __riscv_vmul_vx_i16m1(__VA_ARGS__) -#define vmul_vv_i16m2(...) __riscv_vmul_vv_i16m2(__VA_ARGS__) -#define vmul_vx_i16m2(...) __riscv_vmul_vx_i16m2(__VA_ARGS__) -#define vmul_vv_i16m4(...) __riscv_vmul_vv_i16m4(__VA_ARGS__) -#define vmul_vx_i16m4(...) __riscv_vmul_vx_i16m4(__VA_ARGS__) -#define vmul_vv_i16m8(...) __riscv_vmul_vv_i16m8(__VA_ARGS__) -#define vmul_vx_i16m8(...) __riscv_vmul_vx_i16m8(__VA_ARGS__) -#define vmul_vv_i32mf2(...) __riscv_vmul_vv_i32mf2(__VA_ARGS__) -#define vmul_vx_i32mf2(...) __riscv_vmul_vx_i32mf2(__VA_ARGS__) -#define vmul_vv_i32m1(...) __riscv_vmul_vv_i32m1(__VA_ARGS__) -#define vmul_vx_i32m1(...) __riscv_vmul_vx_i32m1(__VA_ARGS__) -#define vmul_vv_i32m2(...) __riscv_vmul_vv_i32m2(__VA_ARGS__) -#define vmul_vx_i32m2(...) __riscv_vmul_vx_i32m2(__VA_ARGS__) -#define vmul_vv_i32m4(...) __riscv_vmul_vv_i32m4(__VA_ARGS__) -#define vmul_vx_i32m4(...) __riscv_vmul_vx_i32m4(__VA_ARGS__) -#define vmul_vv_i32m8(...) __riscv_vmul_vv_i32m8(__VA_ARGS__) -#define vmul_vx_i32m8(...) __riscv_vmul_vx_i32m8(__VA_ARGS__) -#define vmul_vv_i64m1(...) __riscv_vmul_vv_i64m1(__VA_ARGS__) -#define vmul_vx_i64m1(...) __riscv_vmul_vx_i64m1(__VA_ARGS__) -#define vmul_vv_i64m2(...) __riscv_vmul_vv_i64m2(__VA_ARGS__) -#define vmul_vx_i64m2(...) __riscv_vmul_vx_i64m2(__VA_ARGS__) -#define vmul_vv_i64m4(...) __riscv_vmul_vv_i64m4(__VA_ARGS__) -#define vmul_vx_i64m4(...) __riscv_vmul_vx_i64m4(__VA_ARGS__) -#define vmul_vv_i64m8(...) __riscv_vmul_vv_i64m8(__VA_ARGS__) -#define vmul_vx_i64m8(...) __riscv_vmul_vx_i64m8(__VA_ARGS__) -#define vmulh_vv_i8mf8(...) __riscv_vmulh_vv_i8mf8(__VA_ARGS__) -#define vmulh_vx_i8mf8(...) __riscv_vmulh_vx_i8mf8(__VA_ARGS__) -#define vmulh_vv_i8mf4(...) __riscv_vmulh_vv_i8mf4(__VA_ARGS__) -#define vmulh_vx_i8mf4(...) __riscv_vmulh_vx_i8mf4(__VA_ARGS__) -#define vmulh_vv_i8mf2(...) __riscv_vmulh_vv_i8mf2(__VA_ARGS__) -#define vmulh_vx_i8mf2(...) __riscv_vmulh_vx_i8mf2(__VA_ARGS__) -#define vmulh_vv_i8m1(...) __riscv_vmulh_vv_i8m1(__VA_ARGS__) -#define vmulh_vx_i8m1(...) __riscv_vmulh_vx_i8m1(__VA_ARGS__) -#define vmulh_vv_i8m2(...) __riscv_vmulh_vv_i8m2(__VA_ARGS__) -#define vmulh_vx_i8m2(...) __riscv_vmulh_vx_i8m2(__VA_ARGS__) -#define vmulh_vv_i8m4(...) __riscv_vmulh_vv_i8m4(__VA_ARGS__) -#define vmulh_vx_i8m4(...) __riscv_vmulh_vx_i8m4(__VA_ARGS__) -#define vmulh_vv_i8m8(...) __riscv_vmulh_vv_i8m8(__VA_ARGS__) -#define vmulh_vx_i8m8(...) __riscv_vmulh_vx_i8m8(__VA_ARGS__) -#define vmulh_vv_i16mf4(...) __riscv_vmulh_vv_i16mf4(__VA_ARGS__) -#define vmulh_vx_i16mf4(...) __riscv_vmulh_vx_i16mf4(__VA_ARGS__) -#define vmulh_vv_i16mf2(...) __riscv_vmulh_vv_i16mf2(__VA_ARGS__) -#define vmulh_vx_i16mf2(...) __riscv_vmulh_vx_i16mf2(__VA_ARGS__) -#define vmulh_vv_i16m1(...) __riscv_vmulh_vv_i16m1(__VA_ARGS__) -#define vmulh_vx_i16m1(...) __riscv_vmulh_vx_i16m1(__VA_ARGS__) -#define vmulh_vv_i16m2(...) __riscv_vmulh_vv_i16m2(__VA_ARGS__) -#define vmulh_vx_i16m2(...) __riscv_vmulh_vx_i16m2(__VA_ARGS__) -#define vmulh_vv_i16m4(...) __riscv_vmulh_vv_i16m4(__VA_ARGS__) -#define vmulh_vx_i16m4(...) __riscv_vmulh_vx_i16m4(__VA_ARGS__) -#define vmulh_vv_i16m8(...) __riscv_vmulh_vv_i16m8(__VA_ARGS__) -#define vmulh_vx_i16m8(...) __riscv_vmulh_vx_i16m8(__VA_ARGS__) -#define vmulh_vv_i32mf2(...) __riscv_vmulh_vv_i32mf2(__VA_ARGS__) -#define vmulh_vx_i32mf2(...) __riscv_vmulh_vx_i32mf2(__VA_ARGS__) -#define vmulh_vv_i32m1(...) __riscv_vmulh_vv_i32m1(__VA_ARGS__) -#define vmulh_vx_i32m1(...) __riscv_vmulh_vx_i32m1(__VA_ARGS__) -#define vmulh_vv_i32m2(...) __riscv_vmulh_vv_i32m2(__VA_ARGS__) -#define vmulh_vx_i32m2(...) __riscv_vmulh_vx_i32m2(__VA_ARGS__) -#define vmulh_vv_i32m4(...) __riscv_vmulh_vv_i32m4(__VA_ARGS__) -#define vmulh_vx_i32m4(...) __riscv_vmulh_vx_i32m4(__VA_ARGS__) -#define vmulh_vv_i32m8(...) __riscv_vmulh_vv_i32m8(__VA_ARGS__) -#define vmulh_vx_i32m8(...) __riscv_vmulh_vx_i32m8(__VA_ARGS__) -#define vmulh_vv_i64m1(...) __riscv_vmulh_vv_i64m1(__VA_ARGS__) -#define vmulh_vx_i64m1(...) __riscv_vmulh_vx_i64m1(__VA_ARGS__) -#define vmulh_vv_i64m2(...) __riscv_vmulh_vv_i64m2(__VA_ARGS__) -#define vmulh_vx_i64m2(...) __riscv_vmulh_vx_i64m2(__VA_ARGS__) -#define vmulh_vv_i64m4(...) __riscv_vmulh_vv_i64m4(__VA_ARGS__) -#define vmulh_vx_i64m4(...) __riscv_vmulh_vx_i64m4(__VA_ARGS__) -#define vmulh_vv_i64m8(...) __riscv_vmulh_vv_i64m8(__VA_ARGS__) -#define vmulh_vx_i64m8(...) __riscv_vmulh_vx_i64m8(__VA_ARGS__) -#define vmulhsu_vv_i8mf8(...) __riscv_vmulhsu_vv_i8mf8(__VA_ARGS__) -#define vmulhsu_vx_i8mf8(...) __riscv_vmulhsu_vx_i8mf8(__VA_ARGS__) -#define vmulhsu_vv_i8mf4(...) __riscv_vmulhsu_vv_i8mf4(__VA_ARGS__) -#define vmulhsu_vx_i8mf4(...) __riscv_vmulhsu_vx_i8mf4(__VA_ARGS__) -#define vmulhsu_vv_i8mf2(...) __riscv_vmulhsu_vv_i8mf2(__VA_ARGS__) -#define vmulhsu_vx_i8mf2(...) __riscv_vmulhsu_vx_i8mf2(__VA_ARGS__) -#define vmulhsu_vv_i8m1(...) __riscv_vmulhsu_vv_i8m1(__VA_ARGS__) -#define vmulhsu_vx_i8m1(...) __riscv_vmulhsu_vx_i8m1(__VA_ARGS__) -#define vmulhsu_vv_i8m2(...) __riscv_vmulhsu_vv_i8m2(__VA_ARGS__) -#define vmulhsu_vx_i8m2(...) __riscv_vmulhsu_vx_i8m2(__VA_ARGS__) -#define vmulhsu_vv_i8m4(...) __riscv_vmulhsu_vv_i8m4(__VA_ARGS__) -#define vmulhsu_vx_i8m4(...) __riscv_vmulhsu_vx_i8m4(__VA_ARGS__) -#define vmulhsu_vv_i8m8(...) __riscv_vmulhsu_vv_i8m8(__VA_ARGS__) -#define vmulhsu_vx_i8m8(...) __riscv_vmulhsu_vx_i8m8(__VA_ARGS__) -#define vmulhsu_vv_i16mf4(...) __riscv_vmulhsu_vv_i16mf4(__VA_ARGS__) -#define vmulhsu_vx_i16mf4(...) __riscv_vmulhsu_vx_i16mf4(__VA_ARGS__) -#define vmulhsu_vv_i16mf2(...) __riscv_vmulhsu_vv_i16mf2(__VA_ARGS__) -#define vmulhsu_vx_i16mf2(...) __riscv_vmulhsu_vx_i16mf2(__VA_ARGS__) -#define vmulhsu_vv_i16m1(...) __riscv_vmulhsu_vv_i16m1(__VA_ARGS__) -#define vmulhsu_vx_i16m1(...) __riscv_vmulhsu_vx_i16m1(__VA_ARGS__) -#define vmulhsu_vv_i16m2(...) __riscv_vmulhsu_vv_i16m2(__VA_ARGS__) -#define vmulhsu_vx_i16m2(...) __riscv_vmulhsu_vx_i16m2(__VA_ARGS__) -#define vmulhsu_vv_i16m4(...) __riscv_vmulhsu_vv_i16m4(__VA_ARGS__) -#define vmulhsu_vx_i16m4(...) __riscv_vmulhsu_vx_i16m4(__VA_ARGS__) -#define vmulhsu_vv_i16m8(...) __riscv_vmulhsu_vv_i16m8(__VA_ARGS__) -#define vmulhsu_vx_i16m8(...) __riscv_vmulhsu_vx_i16m8(__VA_ARGS__) -#define vmulhsu_vv_i32mf2(...) __riscv_vmulhsu_vv_i32mf2(__VA_ARGS__) -#define vmulhsu_vx_i32mf2(...) __riscv_vmulhsu_vx_i32mf2(__VA_ARGS__) -#define vmulhsu_vv_i32m1(...) __riscv_vmulhsu_vv_i32m1(__VA_ARGS__) -#define vmulhsu_vx_i32m1(...) __riscv_vmulhsu_vx_i32m1(__VA_ARGS__) -#define vmulhsu_vv_i32m2(...) __riscv_vmulhsu_vv_i32m2(__VA_ARGS__) -#define vmulhsu_vx_i32m2(...) __riscv_vmulhsu_vx_i32m2(__VA_ARGS__) -#define vmulhsu_vv_i32m4(...) __riscv_vmulhsu_vv_i32m4(__VA_ARGS__) -#define vmulhsu_vx_i32m4(...) __riscv_vmulhsu_vx_i32m4(__VA_ARGS__) -#define vmulhsu_vv_i32m8(...) __riscv_vmulhsu_vv_i32m8(__VA_ARGS__) -#define vmulhsu_vx_i32m8(...) __riscv_vmulhsu_vx_i32m8(__VA_ARGS__) -#define vmulhsu_vv_i64m1(...) __riscv_vmulhsu_vv_i64m1(__VA_ARGS__) -#define vmulhsu_vx_i64m1(...) __riscv_vmulhsu_vx_i64m1(__VA_ARGS__) -#define vmulhsu_vv_i64m2(...) __riscv_vmulhsu_vv_i64m2(__VA_ARGS__) -#define vmulhsu_vx_i64m2(...) __riscv_vmulhsu_vx_i64m2(__VA_ARGS__) -#define vmulhsu_vv_i64m4(...) __riscv_vmulhsu_vv_i64m4(__VA_ARGS__) -#define vmulhsu_vx_i64m4(...) __riscv_vmulhsu_vx_i64m4(__VA_ARGS__) -#define vmulhsu_vv_i64m8(...) __riscv_vmulhsu_vv_i64m8(__VA_ARGS__) -#define vmulhsu_vx_i64m8(...) __riscv_vmulhsu_vx_i64m8(__VA_ARGS__) -#define vmul_vv_u8mf8(...) __riscv_vmul_vv_u8mf8(__VA_ARGS__) -#define vmul_vx_u8mf8(...) __riscv_vmul_vx_u8mf8(__VA_ARGS__) -#define vmul_vv_u8mf4(...) __riscv_vmul_vv_u8mf4(__VA_ARGS__) -#define vmul_vx_u8mf4(...) __riscv_vmul_vx_u8mf4(__VA_ARGS__) -#define vmul_vv_u8mf2(...) __riscv_vmul_vv_u8mf2(__VA_ARGS__) -#define vmul_vx_u8mf2(...) __riscv_vmul_vx_u8mf2(__VA_ARGS__) -#define vmul_vv_u8m1(...) __riscv_vmul_vv_u8m1(__VA_ARGS__) -#define vmul_vx_u8m1(...) __riscv_vmul_vx_u8m1(__VA_ARGS__) -#define vmul_vv_u8m2(...) __riscv_vmul_vv_u8m2(__VA_ARGS__) -#define vmul_vx_u8m2(...) __riscv_vmul_vx_u8m2(__VA_ARGS__) -#define vmul_vv_u8m4(...) __riscv_vmul_vv_u8m4(__VA_ARGS__) -#define vmul_vx_u8m4(...) __riscv_vmul_vx_u8m4(__VA_ARGS__) -#define vmul_vv_u8m8(...) __riscv_vmul_vv_u8m8(__VA_ARGS__) -#define vmul_vx_u8m8(...) __riscv_vmul_vx_u8m8(__VA_ARGS__) -#define vmul_vv_u16mf4(...) __riscv_vmul_vv_u16mf4(__VA_ARGS__) -#define vmul_vx_u16mf4(...) __riscv_vmul_vx_u16mf4(__VA_ARGS__) -#define vmul_vv_u16mf2(...) __riscv_vmul_vv_u16mf2(__VA_ARGS__) -#define vmul_vx_u16mf2(...) __riscv_vmul_vx_u16mf2(__VA_ARGS__) -#define vmul_vv_u16m1(...) __riscv_vmul_vv_u16m1(__VA_ARGS__) -#define vmul_vx_u16m1(...) __riscv_vmul_vx_u16m1(__VA_ARGS__) -#define vmul_vv_u16m2(...) __riscv_vmul_vv_u16m2(__VA_ARGS__) -#define vmul_vx_u16m2(...) __riscv_vmul_vx_u16m2(__VA_ARGS__) -#define vmul_vv_u16m4(...) __riscv_vmul_vv_u16m4(__VA_ARGS__) -#define vmul_vx_u16m4(...) __riscv_vmul_vx_u16m4(__VA_ARGS__) -#define vmul_vv_u16m8(...) __riscv_vmul_vv_u16m8(__VA_ARGS__) -#define vmul_vx_u16m8(...) __riscv_vmul_vx_u16m8(__VA_ARGS__) -#define vmul_vv_u32mf2(...) __riscv_vmul_vv_u32mf2(__VA_ARGS__) -#define vmul_vx_u32mf2(...) __riscv_vmul_vx_u32mf2(__VA_ARGS__) -#define vmul_vv_u32m1(...) __riscv_vmul_vv_u32m1(__VA_ARGS__) -#define vmul_vx_u32m1(...) __riscv_vmul_vx_u32m1(__VA_ARGS__) -#define vmul_vv_u32m2(...) __riscv_vmul_vv_u32m2(__VA_ARGS__) -#define vmul_vx_u32m2(...) __riscv_vmul_vx_u32m2(__VA_ARGS__) -#define vmul_vv_u32m4(...) __riscv_vmul_vv_u32m4(__VA_ARGS__) -#define vmul_vx_u32m4(...) __riscv_vmul_vx_u32m4(__VA_ARGS__) -#define vmul_vv_u32m8(...) __riscv_vmul_vv_u32m8(__VA_ARGS__) -#define vmul_vx_u32m8(...) __riscv_vmul_vx_u32m8(__VA_ARGS__) -#define vmul_vv_u64m1(...) __riscv_vmul_vv_u64m1(__VA_ARGS__) -#define vmul_vx_u64m1(...) __riscv_vmul_vx_u64m1(__VA_ARGS__) -#define vmul_vv_u64m2(...) __riscv_vmul_vv_u64m2(__VA_ARGS__) -#define vmul_vx_u64m2(...) __riscv_vmul_vx_u64m2(__VA_ARGS__) -#define vmul_vv_u64m4(...) __riscv_vmul_vv_u64m4(__VA_ARGS__) -#define vmul_vx_u64m4(...) __riscv_vmul_vx_u64m4(__VA_ARGS__) -#define vmul_vv_u64m8(...) __riscv_vmul_vv_u64m8(__VA_ARGS__) -#define vmul_vx_u64m8(...) __riscv_vmul_vx_u64m8(__VA_ARGS__) -#define vmulhu_vv_u8mf8(...) __riscv_vmulhu_vv_u8mf8(__VA_ARGS__) -#define vmulhu_vx_u8mf8(...) __riscv_vmulhu_vx_u8mf8(__VA_ARGS__) -#define vmulhu_vv_u8mf4(...) __riscv_vmulhu_vv_u8mf4(__VA_ARGS__) -#define vmulhu_vx_u8mf4(...) __riscv_vmulhu_vx_u8mf4(__VA_ARGS__) -#define vmulhu_vv_u8mf2(...) __riscv_vmulhu_vv_u8mf2(__VA_ARGS__) -#define vmulhu_vx_u8mf2(...) __riscv_vmulhu_vx_u8mf2(__VA_ARGS__) -#define vmulhu_vv_u8m1(...) __riscv_vmulhu_vv_u8m1(__VA_ARGS__) -#define vmulhu_vx_u8m1(...) __riscv_vmulhu_vx_u8m1(__VA_ARGS__) -#define vmulhu_vv_u8m2(...) __riscv_vmulhu_vv_u8m2(__VA_ARGS__) -#define vmulhu_vx_u8m2(...) __riscv_vmulhu_vx_u8m2(__VA_ARGS__) -#define vmulhu_vv_u8m4(...) __riscv_vmulhu_vv_u8m4(__VA_ARGS__) -#define vmulhu_vx_u8m4(...) __riscv_vmulhu_vx_u8m4(__VA_ARGS__) -#define vmulhu_vv_u8m8(...) __riscv_vmulhu_vv_u8m8(__VA_ARGS__) -#define vmulhu_vx_u8m8(...) __riscv_vmulhu_vx_u8m8(__VA_ARGS__) -#define vmulhu_vv_u16mf4(...) __riscv_vmulhu_vv_u16mf4(__VA_ARGS__) -#define vmulhu_vx_u16mf4(...) __riscv_vmulhu_vx_u16mf4(__VA_ARGS__) -#define vmulhu_vv_u16mf2(...) __riscv_vmulhu_vv_u16mf2(__VA_ARGS__) -#define vmulhu_vx_u16mf2(...) __riscv_vmulhu_vx_u16mf2(__VA_ARGS__) -#define vmulhu_vv_u16m1(...) __riscv_vmulhu_vv_u16m1(__VA_ARGS__) -#define vmulhu_vx_u16m1(...) __riscv_vmulhu_vx_u16m1(__VA_ARGS__) -#define vmulhu_vv_u16m2(...) __riscv_vmulhu_vv_u16m2(__VA_ARGS__) -#define vmulhu_vx_u16m2(...) __riscv_vmulhu_vx_u16m2(__VA_ARGS__) -#define vmulhu_vv_u16m4(...) __riscv_vmulhu_vv_u16m4(__VA_ARGS__) -#define vmulhu_vx_u16m4(...) __riscv_vmulhu_vx_u16m4(__VA_ARGS__) -#define vmulhu_vv_u16m8(...) __riscv_vmulhu_vv_u16m8(__VA_ARGS__) -#define vmulhu_vx_u16m8(...) __riscv_vmulhu_vx_u16m8(__VA_ARGS__) -#define vmulhu_vv_u32mf2(...) __riscv_vmulhu_vv_u32mf2(__VA_ARGS__) -#define vmulhu_vx_u32mf2(...) __riscv_vmulhu_vx_u32mf2(__VA_ARGS__) -#define vmulhu_vv_u32m1(...) __riscv_vmulhu_vv_u32m1(__VA_ARGS__) -#define vmulhu_vx_u32m1(...) __riscv_vmulhu_vx_u32m1(__VA_ARGS__) -#define vmulhu_vv_u32m2(...) __riscv_vmulhu_vv_u32m2(__VA_ARGS__) -#define vmulhu_vx_u32m2(...) __riscv_vmulhu_vx_u32m2(__VA_ARGS__) -#define vmulhu_vv_u32m4(...) __riscv_vmulhu_vv_u32m4(__VA_ARGS__) -#define vmulhu_vx_u32m4(...) __riscv_vmulhu_vx_u32m4(__VA_ARGS__) -#define vmulhu_vv_u32m8(...) __riscv_vmulhu_vv_u32m8(__VA_ARGS__) -#define vmulhu_vx_u32m8(...) __riscv_vmulhu_vx_u32m8(__VA_ARGS__) -#define vmulhu_vv_u64m1(...) __riscv_vmulhu_vv_u64m1(__VA_ARGS__) -#define vmulhu_vx_u64m1(...) __riscv_vmulhu_vx_u64m1(__VA_ARGS__) -#define vmulhu_vv_u64m2(...) __riscv_vmulhu_vv_u64m2(__VA_ARGS__) -#define vmulhu_vx_u64m2(...) __riscv_vmulhu_vx_u64m2(__VA_ARGS__) -#define vmulhu_vv_u64m4(...) __riscv_vmulhu_vv_u64m4(__VA_ARGS__) -#define vmulhu_vx_u64m4(...) __riscv_vmulhu_vx_u64m4(__VA_ARGS__) -#define vmulhu_vv_u64m8(...) __riscv_vmulhu_vv_u64m8(__VA_ARGS__) -#define vmulhu_vx_u64m8(...) __riscv_vmulhu_vx_u64m8(__VA_ARGS__) -// masked functions -#define vmul_vv_i8mf8_m(...) __riscv_vmul_vv_i8mf8_tumu(__VA_ARGS__) -#define vmul_vx_i8mf8_m(...) __riscv_vmul_vx_i8mf8_tumu(__VA_ARGS__) -#define vmul_vv_i8mf4_m(...) __riscv_vmul_vv_i8mf4_tumu(__VA_ARGS__) -#define vmul_vx_i8mf4_m(...) __riscv_vmul_vx_i8mf4_tumu(__VA_ARGS__) -#define vmul_vv_i8mf2_m(...) __riscv_vmul_vv_i8mf2_tumu(__VA_ARGS__) -#define vmul_vx_i8mf2_m(...) __riscv_vmul_vx_i8mf2_tumu(__VA_ARGS__) -#define vmul_vv_i8m1_m(...) __riscv_vmul_vv_i8m1_tumu(__VA_ARGS__) -#define vmul_vx_i8m1_m(...) __riscv_vmul_vx_i8m1_tumu(__VA_ARGS__) -#define vmul_vv_i8m2_m(...) __riscv_vmul_vv_i8m2_tumu(__VA_ARGS__) -#define vmul_vx_i8m2_m(...) __riscv_vmul_vx_i8m2_tumu(__VA_ARGS__) -#define vmul_vv_i8m4_m(...) __riscv_vmul_vv_i8m4_tumu(__VA_ARGS__) -#define vmul_vx_i8m4_m(...) __riscv_vmul_vx_i8m4_tumu(__VA_ARGS__) -#define vmul_vv_i8m8_m(...) __riscv_vmul_vv_i8m8_tumu(__VA_ARGS__) -#define vmul_vx_i8m8_m(...) __riscv_vmul_vx_i8m8_tumu(__VA_ARGS__) -#define vmul_vv_i16mf4_m(...) __riscv_vmul_vv_i16mf4_tumu(__VA_ARGS__) -#define vmul_vx_i16mf4_m(...) __riscv_vmul_vx_i16mf4_tumu(__VA_ARGS__) -#define vmul_vv_i16mf2_m(...) __riscv_vmul_vv_i16mf2_tumu(__VA_ARGS__) -#define vmul_vx_i16mf2_m(...) __riscv_vmul_vx_i16mf2_tumu(__VA_ARGS__) -#define vmul_vv_i16m1_m(...) __riscv_vmul_vv_i16m1_tumu(__VA_ARGS__) -#define vmul_vx_i16m1_m(...) __riscv_vmul_vx_i16m1_tumu(__VA_ARGS__) -#define vmul_vv_i16m2_m(...) __riscv_vmul_vv_i16m2_tumu(__VA_ARGS__) -#define vmul_vx_i16m2_m(...) __riscv_vmul_vx_i16m2_tumu(__VA_ARGS__) -#define vmul_vv_i16m4_m(...) __riscv_vmul_vv_i16m4_tumu(__VA_ARGS__) -#define vmul_vx_i16m4_m(...) __riscv_vmul_vx_i16m4_tumu(__VA_ARGS__) -#define vmul_vv_i16m8_m(...) __riscv_vmul_vv_i16m8_tumu(__VA_ARGS__) -#define vmul_vx_i16m8_m(...) __riscv_vmul_vx_i16m8_tumu(__VA_ARGS__) -#define vmul_vv_i32mf2_m(...) __riscv_vmul_vv_i32mf2_tumu(__VA_ARGS__) -#define vmul_vx_i32mf2_m(...) __riscv_vmul_vx_i32mf2_tumu(__VA_ARGS__) -#define vmul_vv_i32m1_m(...) __riscv_vmul_vv_i32m1_tumu(__VA_ARGS__) -#define vmul_vx_i32m1_m(...) __riscv_vmul_vx_i32m1_tumu(__VA_ARGS__) -#define vmul_vv_i32m2_m(...) __riscv_vmul_vv_i32m2_tumu(__VA_ARGS__) -#define vmul_vx_i32m2_m(...) __riscv_vmul_vx_i32m2_tumu(__VA_ARGS__) -#define vmul_vv_i32m4_m(...) __riscv_vmul_vv_i32m4_tumu(__VA_ARGS__) -#define vmul_vx_i32m4_m(...) __riscv_vmul_vx_i32m4_tumu(__VA_ARGS__) -#define vmul_vv_i32m8_m(...) __riscv_vmul_vv_i32m8_tumu(__VA_ARGS__) -#define vmul_vx_i32m8_m(...) __riscv_vmul_vx_i32m8_tumu(__VA_ARGS__) -#define vmul_vv_i64m1_m(...) __riscv_vmul_vv_i64m1_tumu(__VA_ARGS__) -#define vmul_vx_i64m1_m(...) __riscv_vmul_vx_i64m1_tumu(__VA_ARGS__) -#define vmul_vv_i64m2_m(...) __riscv_vmul_vv_i64m2_tumu(__VA_ARGS__) -#define vmul_vx_i64m2_m(...) __riscv_vmul_vx_i64m2_tumu(__VA_ARGS__) -#define vmul_vv_i64m4_m(...) __riscv_vmul_vv_i64m4_tumu(__VA_ARGS__) -#define vmul_vx_i64m4_m(...) __riscv_vmul_vx_i64m4_tumu(__VA_ARGS__) -#define vmul_vv_i64m8_m(...) __riscv_vmul_vv_i64m8_tumu(__VA_ARGS__) -#define vmul_vx_i64m8_m(...) __riscv_vmul_vx_i64m8_tumu(__VA_ARGS__) -#define vmulh_vv_i8mf8_m(...) __riscv_vmulh_vv_i8mf8_tumu(__VA_ARGS__) -#define vmulh_vx_i8mf8_m(...) __riscv_vmulh_vx_i8mf8_tumu(__VA_ARGS__) -#define vmulh_vv_i8mf4_m(...) __riscv_vmulh_vv_i8mf4_tumu(__VA_ARGS__) -#define vmulh_vx_i8mf4_m(...) __riscv_vmulh_vx_i8mf4_tumu(__VA_ARGS__) -#define vmulh_vv_i8mf2_m(...) __riscv_vmulh_vv_i8mf2_tumu(__VA_ARGS__) -#define vmulh_vx_i8mf2_m(...) __riscv_vmulh_vx_i8mf2_tumu(__VA_ARGS__) -#define vmulh_vv_i8m1_m(...) __riscv_vmulh_vv_i8m1_tumu(__VA_ARGS__) -#define vmulh_vx_i8m1_m(...) __riscv_vmulh_vx_i8m1_tumu(__VA_ARGS__) -#define vmulh_vv_i8m2_m(...) __riscv_vmulh_vv_i8m2_tumu(__VA_ARGS__) -#define vmulh_vx_i8m2_m(...) __riscv_vmulh_vx_i8m2_tumu(__VA_ARGS__) -#define vmulh_vv_i8m4_m(...) __riscv_vmulh_vv_i8m4_tumu(__VA_ARGS__) -#define vmulh_vx_i8m4_m(...) __riscv_vmulh_vx_i8m4_tumu(__VA_ARGS__) -#define vmulh_vv_i8m8_m(...) __riscv_vmulh_vv_i8m8_tumu(__VA_ARGS__) -#define vmulh_vx_i8m8_m(...) __riscv_vmulh_vx_i8m8_tumu(__VA_ARGS__) -#define vmulh_vv_i16mf4_m(...) __riscv_vmulh_vv_i16mf4_tumu(__VA_ARGS__) -#define vmulh_vx_i16mf4_m(...) __riscv_vmulh_vx_i16mf4_tumu(__VA_ARGS__) -#define vmulh_vv_i16mf2_m(...) __riscv_vmulh_vv_i16mf2_tumu(__VA_ARGS__) -#define vmulh_vx_i16mf2_m(...) __riscv_vmulh_vx_i16mf2_tumu(__VA_ARGS__) -#define vmulh_vv_i16m1_m(...) __riscv_vmulh_vv_i16m1_tumu(__VA_ARGS__) -#define vmulh_vx_i16m1_m(...) __riscv_vmulh_vx_i16m1_tumu(__VA_ARGS__) -#define vmulh_vv_i16m2_m(...) __riscv_vmulh_vv_i16m2_tumu(__VA_ARGS__) -#define vmulh_vx_i16m2_m(...) __riscv_vmulh_vx_i16m2_tumu(__VA_ARGS__) -#define vmulh_vv_i16m4_m(...) __riscv_vmulh_vv_i16m4_tumu(__VA_ARGS__) -#define vmulh_vx_i16m4_m(...) __riscv_vmulh_vx_i16m4_tumu(__VA_ARGS__) -#define vmulh_vv_i16m8_m(...) __riscv_vmulh_vv_i16m8_tumu(__VA_ARGS__) -#define vmulh_vx_i16m8_m(...) __riscv_vmulh_vx_i16m8_tumu(__VA_ARGS__) -#define vmulh_vv_i32mf2_m(...) __riscv_vmulh_vv_i32mf2_tumu(__VA_ARGS__) -#define vmulh_vx_i32mf2_m(...) __riscv_vmulh_vx_i32mf2_tumu(__VA_ARGS__) -#define vmulh_vv_i32m1_m(...) __riscv_vmulh_vv_i32m1_tumu(__VA_ARGS__) -#define vmulh_vx_i32m1_m(...) __riscv_vmulh_vx_i32m1_tumu(__VA_ARGS__) -#define vmulh_vv_i32m2_m(...) __riscv_vmulh_vv_i32m2_tumu(__VA_ARGS__) -#define vmulh_vx_i32m2_m(...) __riscv_vmulh_vx_i32m2_tumu(__VA_ARGS__) -#define vmulh_vv_i32m4_m(...) __riscv_vmulh_vv_i32m4_tumu(__VA_ARGS__) -#define vmulh_vx_i32m4_m(...) __riscv_vmulh_vx_i32m4_tumu(__VA_ARGS__) -#define vmulh_vv_i32m8_m(...) __riscv_vmulh_vv_i32m8_tumu(__VA_ARGS__) -#define vmulh_vx_i32m8_m(...) __riscv_vmulh_vx_i32m8_tumu(__VA_ARGS__) -#define vmulh_vv_i64m1_m(...) __riscv_vmulh_vv_i64m1_tumu(__VA_ARGS__) -#define vmulh_vx_i64m1_m(...) __riscv_vmulh_vx_i64m1_tumu(__VA_ARGS__) -#define vmulh_vv_i64m2_m(...) __riscv_vmulh_vv_i64m2_tumu(__VA_ARGS__) -#define vmulh_vx_i64m2_m(...) __riscv_vmulh_vx_i64m2_tumu(__VA_ARGS__) -#define vmulh_vv_i64m4_m(...) __riscv_vmulh_vv_i64m4_tumu(__VA_ARGS__) -#define vmulh_vx_i64m4_m(...) __riscv_vmulh_vx_i64m4_tumu(__VA_ARGS__) -#define vmulh_vv_i64m8_m(...) __riscv_vmulh_vv_i64m8_tumu(__VA_ARGS__) -#define vmulh_vx_i64m8_m(...) __riscv_vmulh_vx_i64m8_tumu(__VA_ARGS__) -#define vmulhsu_vv_i8mf8_m(...) __riscv_vmulhsu_vv_i8mf8_tumu(__VA_ARGS__) -#define vmulhsu_vx_i8mf8_m(...) __riscv_vmulhsu_vx_i8mf8_tumu(__VA_ARGS__) -#define vmulhsu_vv_i8mf4_m(...) __riscv_vmulhsu_vv_i8mf4_tumu(__VA_ARGS__) -#define vmulhsu_vx_i8mf4_m(...) __riscv_vmulhsu_vx_i8mf4_tumu(__VA_ARGS__) -#define vmulhsu_vv_i8mf2_m(...) __riscv_vmulhsu_vv_i8mf2_tumu(__VA_ARGS__) -#define vmulhsu_vx_i8mf2_m(...) __riscv_vmulhsu_vx_i8mf2_tumu(__VA_ARGS__) -#define vmulhsu_vv_i8m1_m(...) __riscv_vmulhsu_vv_i8m1_tumu(__VA_ARGS__) -#define vmulhsu_vx_i8m1_m(...) __riscv_vmulhsu_vx_i8m1_tumu(__VA_ARGS__) -#define vmulhsu_vv_i8m2_m(...) __riscv_vmulhsu_vv_i8m2_tumu(__VA_ARGS__) -#define vmulhsu_vx_i8m2_m(...) __riscv_vmulhsu_vx_i8m2_tumu(__VA_ARGS__) -#define vmulhsu_vv_i8m4_m(...) __riscv_vmulhsu_vv_i8m4_tumu(__VA_ARGS__) -#define vmulhsu_vx_i8m4_m(...) __riscv_vmulhsu_vx_i8m4_tumu(__VA_ARGS__) -#define vmulhsu_vv_i8m8_m(...) __riscv_vmulhsu_vv_i8m8_tumu(__VA_ARGS__) -#define vmulhsu_vx_i8m8_m(...) __riscv_vmulhsu_vx_i8m8_tumu(__VA_ARGS__) -#define vmulhsu_vv_i16mf4_m(...) __riscv_vmulhsu_vv_i16mf4_tumu(__VA_ARGS__) -#define vmulhsu_vx_i16mf4_m(...) __riscv_vmulhsu_vx_i16mf4_tumu(__VA_ARGS__) -#define vmulhsu_vv_i16mf2_m(...) __riscv_vmulhsu_vv_i16mf2_tumu(__VA_ARGS__) -#define vmulhsu_vx_i16mf2_m(...) __riscv_vmulhsu_vx_i16mf2_tumu(__VA_ARGS__) -#define vmulhsu_vv_i16m1_m(...) __riscv_vmulhsu_vv_i16m1_tumu(__VA_ARGS__) -#define vmulhsu_vx_i16m1_m(...) __riscv_vmulhsu_vx_i16m1_tumu(__VA_ARGS__) -#define vmulhsu_vv_i16m2_m(...) __riscv_vmulhsu_vv_i16m2_tumu(__VA_ARGS__) -#define vmulhsu_vx_i16m2_m(...) __riscv_vmulhsu_vx_i16m2_tumu(__VA_ARGS__) -#define vmulhsu_vv_i16m4_m(...) __riscv_vmulhsu_vv_i16m4_tumu(__VA_ARGS__) -#define vmulhsu_vx_i16m4_m(...) __riscv_vmulhsu_vx_i16m4_tumu(__VA_ARGS__) -#define vmulhsu_vv_i16m8_m(...) __riscv_vmulhsu_vv_i16m8_tumu(__VA_ARGS__) -#define vmulhsu_vx_i16m8_m(...) __riscv_vmulhsu_vx_i16m8_tumu(__VA_ARGS__) -#define vmulhsu_vv_i32mf2_m(...) __riscv_vmulhsu_vv_i32mf2_tumu(__VA_ARGS__) -#define vmulhsu_vx_i32mf2_m(...) __riscv_vmulhsu_vx_i32mf2_tumu(__VA_ARGS__) -#define vmulhsu_vv_i32m1_m(...) __riscv_vmulhsu_vv_i32m1_tumu(__VA_ARGS__) -#define vmulhsu_vx_i32m1_m(...) __riscv_vmulhsu_vx_i32m1_tumu(__VA_ARGS__) -#define vmulhsu_vv_i32m2_m(...) __riscv_vmulhsu_vv_i32m2_tumu(__VA_ARGS__) -#define vmulhsu_vx_i32m2_m(...) __riscv_vmulhsu_vx_i32m2_tumu(__VA_ARGS__) -#define vmulhsu_vv_i32m4_m(...) __riscv_vmulhsu_vv_i32m4_tumu(__VA_ARGS__) -#define vmulhsu_vx_i32m4_m(...) __riscv_vmulhsu_vx_i32m4_tumu(__VA_ARGS__) -#define vmulhsu_vv_i32m8_m(...) __riscv_vmulhsu_vv_i32m8_tumu(__VA_ARGS__) -#define vmulhsu_vx_i32m8_m(...) __riscv_vmulhsu_vx_i32m8_tumu(__VA_ARGS__) -#define vmulhsu_vv_i64m1_m(...) __riscv_vmulhsu_vv_i64m1_tumu(__VA_ARGS__) -#define vmulhsu_vx_i64m1_m(...) __riscv_vmulhsu_vx_i64m1_tumu(__VA_ARGS__) -#define vmulhsu_vv_i64m2_m(...) __riscv_vmulhsu_vv_i64m2_tumu(__VA_ARGS__) -#define vmulhsu_vx_i64m2_m(...) __riscv_vmulhsu_vx_i64m2_tumu(__VA_ARGS__) -#define vmulhsu_vv_i64m4_m(...) __riscv_vmulhsu_vv_i64m4_tumu(__VA_ARGS__) -#define vmulhsu_vx_i64m4_m(...) __riscv_vmulhsu_vx_i64m4_tumu(__VA_ARGS__) -#define vmulhsu_vv_i64m8_m(...) __riscv_vmulhsu_vv_i64m8_tumu(__VA_ARGS__) -#define vmulhsu_vx_i64m8_m(...) __riscv_vmulhsu_vx_i64m8_tumu(__VA_ARGS__) -#define vmul_vv_u8mf8_m(...) __riscv_vmul_vv_u8mf8_tumu(__VA_ARGS__) -#define vmul_vx_u8mf8_m(...) __riscv_vmul_vx_u8mf8_tumu(__VA_ARGS__) -#define vmul_vv_u8mf4_m(...) __riscv_vmul_vv_u8mf4_tumu(__VA_ARGS__) -#define vmul_vx_u8mf4_m(...) __riscv_vmul_vx_u8mf4_tumu(__VA_ARGS__) -#define vmul_vv_u8mf2_m(...) __riscv_vmul_vv_u8mf2_tumu(__VA_ARGS__) -#define vmul_vx_u8mf2_m(...) __riscv_vmul_vx_u8mf2_tumu(__VA_ARGS__) -#define vmul_vv_u8m1_m(...) __riscv_vmul_vv_u8m1_tumu(__VA_ARGS__) -#define vmul_vx_u8m1_m(...) __riscv_vmul_vx_u8m1_tumu(__VA_ARGS__) -#define vmul_vv_u8m2_m(...) __riscv_vmul_vv_u8m2_tumu(__VA_ARGS__) -#define vmul_vx_u8m2_m(...) __riscv_vmul_vx_u8m2_tumu(__VA_ARGS__) -#define vmul_vv_u8m4_m(...) __riscv_vmul_vv_u8m4_tumu(__VA_ARGS__) -#define vmul_vx_u8m4_m(...) __riscv_vmul_vx_u8m4_tumu(__VA_ARGS__) -#define vmul_vv_u8m8_m(...) __riscv_vmul_vv_u8m8_tumu(__VA_ARGS__) -#define vmul_vx_u8m8_m(...) __riscv_vmul_vx_u8m8_tumu(__VA_ARGS__) -#define vmul_vv_u16mf4_m(...) __riscv_vmul_vv_u16mf4_tumu(__VA_ARGS__) -#define vmul_vx_u16mf4_m(...) __riscv_vmul_vx_u16mf4_tumu(__VA_ARGS__) -#define vmul_vv_u16mf2_m(...) __riscv_vmul_vv_u16mf2_tumu(__VA_ARGS__) -#define vmul_vx_u16mf2_m(...) __riscv_vmul_vx_u16mf2_tumu(__VA_ARGS__) -#define vmul_vv_u16m1_m(...) __riscv_vmul_vv_u16m1_tumu(__VA_ARGS__) -#define vmul_vx_u16m1_m(...) __riscv_vmul_vx_u16m1_tumu(__VA_ARGS__) -#define vmul_vv_u16m2_m(...) __riscv_vmul_vv_u16m2_tumu(__VA_ARGS__) -#define vmul_vx_u16m2_m(...) __riscv_vmul_vx_u16m2_tumu(__VA_ARGS__) -#define vmul_vv_u16m4_m(...) __riscv_vmul_vv_u16m4_tumu(__VA_ARGS__) -#define vmul_vx_u16m4_m(...) __riscv_vmul_vx_u16m4_tumu(__VA_ARGS__) -#define vmul_vv_u16m8_m(...) __riscv_vmul_vv_u16m8_tumu(__VA_ARGS__) -#define vmul_vx_u16m8_m(...) __riscv_vmul_vx_u16m8_tumu(__VA_ARGS__) -#define vmul_vv_u32mf2_m(...) __riscv_vmul_vv_u32mf2_tumu(__VA_ARGS__) -#define vmul_vx_u32mf2_m(...) __riscv_vmul_vx_u32mf2_tumu(__VA_ARGS__) -#define vmul_vv_u32m1_m(...) __riscv_vmul_vv_u32m1_tumu(__VA_ARGS__) -#define vmul_vx_u32m1_m(...) __riscv_vmul_vx_u32m1_tumu(__VA_ARGS__) -#define vmul_vv_u32m2_m(...) __riscv_vmul_vv_u32m2_tumu(__VA_ARGS__) -#define vmul_vx_u32m2_m(...) __riscv_vmul_vx_u32m2_tumu(__VA_ARGS__) -#define vmul_vv_u32m4_m(...) __riscv_vmul_vv_u32m4_tumu(__VA_ARGS__) -#define vmul_vx_u32m4_m(...) __riscv_vmul_vx_u32m4_tumu(__VA_ARGS__) -#define vmul_vv_u32m8_m(...) __riscv_vmul_vv_u32m8_tumu(__VA_ARGS__) -#define vmul_vx_u32m8_m(...) __riscv_vmul_vx_u32m8_tumu(__VA_ARGS__) -#define vmul_vv_u64m1_m(...) __riscv_vmul_vv_u64m1_tumu(__VA_ARGS__) -#define vmul_vx_u64m1_m(...) __riscv_vmul_vx_u64m1_tumu(__VA_ARGS__) -#define vmul_vv_u64m2_m(...) __riscv_vmul_vv_u64m2_tumu(__VA_ARGS__) -#define vmul_vx_u64m2_m(...) __riscv_vmul_vx_u64m2_tumu(__VA_ARGS__) -#define vmul_vv_u64m4_m(...) __riscv_vmul_vv_u64m4_tumu(__VA_ARGS__) -#define vmul_vx_u64m4_m(...) __riscv_vmul_vx_u64m4_tumu(__VA_ARGS__) -#define vmul_vv_u64m8_m(...) __riscv_vmul_vv_u64m8_tumu(__VA_ARGS__) -#define vmul_vx_u64m8_m(...) __riscv_vmul_vx_u64m8_tumu(__VA_ARGS__) -#define vmulhu_vv_u8mf8_m(...) __riscv_vmulhu_vv_u8mf8_tumu(__VA_ARGS__) -#define vmulhu_vx_u8mf8_m(...) __riscv_vmulhu_vx_u8mf8_tumu(__VA_ARGS__) -#define vmulhu_vv_u8mf4_m(...) __riscv_vmulhu_vv_u8mf4_tumu(__VA_ARGS__) -#define vmulhu_vx_u8mf4_m(...) __riscv_vmulhu_vx_u8mf4_tumu(__VA_ARGS__) -#define vmulhu_vv_u8mf2_m(...) __riscv_vmulhu_vv_u8mf2_tumu(__VA_ARGS__) -#define vmulhu_vx_u8mf2_m(...) __riscv_vmulhu_vx_u8mf2_tumu(__VA_ARGS__) -#define vmulhu_vv_u8m1_m(...) __riscv_vmulhu_vv_u8m1_tumu(__VA_ARGS__) -#define vmulhu_vx_u8m1_m(...) __riscv_vmulhu_vx_u8m1_tumu(__VA_ARGS__) -#define vmulhu_vv_u8m2_m(...) __riscv_vmulhu_vv_u8m2_tumu(__VA_ARGS__) -#define vmulhu_vx_u8m2_m(...) __riscv_vmulhu_vx_u8m2_tumu(__VA_ARGS__) -#define vmulhu_vv_u8m4_m(...) __riscv_vmulhu_vv_u8m4_tumu(__VA_ARGS__) -#define vmulhu_vx_u8m4_m(...) __riscv_vmulhu_vx_u8m4_tumu(__VA_ARGS__) -#define vmulhu_vv_u8m8_m(...) __riscv_vmulhu_vv_u8m8_tumu(__VA_ARGS__) -#define vmulhu_vx_u8m8_m(...) __riscv_vmulhu_vx_u8m8_tumu(__VA_ARGS__) -#define vmulhu_vv_u16mf4_m(...) __riscv_vmulhu_vv_u16mf4_tumu(__VA_ARGS__) -#define vmulhu_vx_u16mf4_m(...) __riscv_vmulhu_vx_u16mf4_tumu(__VA_ARGS__) -#define vmulhu_vv_u16mf2_m(...) __riscv_vmulhu_vv_u16mf2_tumu(__VA_ARGS__) -#define vmulhu_vx_u16mf2_m(...) __riscv_vmulhu_vx_u16mf2_tumu(__VA_ARGS__) -#define vmulhu_vv_u16m1_m(...) __riscv_vmulhu_vv_u16m1_tumu(__VA_ARGS__) -#define vmulhu_vx_u16m1_m(...) __riscv_vmulhu_vx_u16m1_tumu(__VA_ARGS__) -#define vmulhu_vv_u16m2_m(...) __riscv_vmulhu_vv_u16m2_tumu(__VA_ARGS__) -#define vmulhu_vx_u16m2_m(...) __riscv_vmulhu_vx_u16m2_tumu(__VA_ARGS__) -#define vmulhu_vv_u16m4_m(...) __riscv_vmulhu_vv_u16m4_tumu(__VA_ARGS__) -#define vmulhu_vx_u16m4_m(...) __riscv_vmulhu_vx_u16m4_tumu(__VA_ARGS__) -#define vmulhu_vv_u16m8_m(...) __riscv_vmulhu_vv_u16m8_tumu(__VA_ARGS__) -#define vmulhu_vx_u16m8_m(...) __riscv_vmulhu_vx_u16m8_tumu(__VA_ARGS__) -#define vmulhu_vv_u32mf2_m(...) __riscv_vmulhu_vv_u32mf2_tumu(__VA_ARGS__) -#define vmulhu_vx_u32mf2_m(...) __riscv_vmulhu_vx_u32mf2_tumu(__VA_ARGS__) -#define vmulhu_vv_u32m1_m(...) __riscv_vmulhu_vv_u32m1_tumu(__VA_ARGS__) -#define vmulhu_vx_u32m1_m(...) __riscv_vmulhu_vx_u32m1_tumu(__VA_ARGS__) -#define vmulhu_vv_u32m2_m(...) __riscv_vmulhu_vv_u32m2_tumu(__VA_ARGS__) -#define vmulhu_vx_u32m2_m(...) __riscv_vmulhu_vx_u32m2_tumu(__VA_ARGS__) -#define vmulhu_vv_u32m4_m(...) __riscv_vmulhu_vv_u32m4_tumu(__VA_ARGS__) -#define vmulhu_vx_u32m4_m(...) __riscv_vmulhu_vx_u32m4_tumu(__VA_ARGS__) -#define vmulhu_vv_u32m8_m(...) __riscv_vmulhu_vv_u32m8_tumu(__VA_ARGS__) -#define vmulhu_vx_u32m8_m(...) __riscv_vmulhu_vx_u32m8_tumu(__VA_ARGS__) -#define vmulhu_vv_u64m1_m(...) __riscv_vmulhu_vv_u64m1_tumu(__VA_ARGS__) -#define vmulhu_vx_u64m1_m(...) __riscv_vmulhu_vx_u64m1_tumu(__VA_ARGS__) -#define vmulhu_vv_u64m2_m(...) __riscv_vmulhu_vv_u64m2_tumu(__VA_ARGS__) -#define vmulhu_vx_u64m2_m(...) __riscv_vmulhu_vx_u64m2_tumu(__VA_ARGS__) -#define vmulhu_vv_u64m4_m(...) __riscv_vmulhu_vv_u64m4_tumu(__VA_ARGS__) -#define vmulhu_vx_u64m4_m(...) __riscv_vmulhu_vx_u64m4_tumu(__VA_ARGS__) -#define vmulhu_vv_u64m8_m(...) __riscv_vmulhu_vv_u64m8_tumu(__VA_ARGS__) -#define vmulhu_vx_u64m8_m(...) __riscv_vmulhu_vx_u64m8_tumu(__VA_ARGS__) -#define vdiv_vv_i8mf8(...) __riscv_vdiv_vv_i8mf8(__VA_ARGS__) -#define vdiv_vx_i8mf8(...) __riscv_vdiv_vx_i8mf8(__VA_ARGS__) -#define vdiv_vv_i8mf4(...) __riscv_vdiv_vv_i8mf4(__VA_ARGS__) -#define vdiv_vx_i8mf4(...) __riscv_vdiv_vx_i8mf4(__VA_ARGS__) -#define vdiv_vv_i8mf2(...) __riscv_vdiv_vv_i8mf2(__VA_ARGS__) -#define vdiv_vx_i8mf2(...) __riscv_vdiv_vx_i8mf2(__VA_ARGS__) -#define vdiv_vv_i8m1(...) __riscv_vdiv_vv_i8m1(__VA_ARGS__) -#define vdiv_vx_i8m1(...) __riscv_vdiv_vx_i8m1(__VA_ARGS__) -#define vdiv_vv_i8m2(...) __riscv_vdiv_vv_i8m2(__VA_ARGS__) -#define vdiv_vx_i8m2(...) __riscv_vdiv_vx_i8m2(__VA_ARGS__) -#define vdiv_vv_i8m4(...) __riscv_vdiv_vv_i8m4(__VA_ARGS__) -#define vdiv_vx_i8m4(...) __riscv_vdiv_vx_i8m4(__VA_ARGS__) -#define vdiv_vv_i8m8(...) __riscv_vdiv_vv_i8m8(__VA_ARGS__) -#define vdiv_vx_i8m8(...) __riscv_vdiv_vx_i8m8(__VA_ARGS__) -#define vdiv_vv_i16mf4(...) __riscv_vdiv_vv_i16mf4(__VA_ARGS__) -#define vdiv_vx_i16mf4(...) __riscv_vdiv_vx_i16mf4(__VA_ARGS__) -#define vdiv_vv_i16mf2(...) __riscv_vdiv_vv_i16mf2(__VA_ARGS__) -#define vdiv_vx_i16mf2(...) __riscv_vdiv_vx_i16mf2(__VA_ARGS__) -#define vdiv_vv_i16m1(...) __riscv_vdiv_vv_i16m1(__VA_ARGS__) -#define vdiv_vx_i16m1(...) __riscv_vdiv_vx_i16m1(__VA_ARGS__) -#define vdiv_vv_i16m2(...) __riscv_vdiv_vv_i16m2(__VA_ARGS__) -#define vdiv_vx_i16m2(...) __riscv_vdiv_vx_i16m2(__VA_ARGS__) -#define vdiv_vv_i16m4(...) __riscv_vdiv_vv_i16m4(__VA_ARGS__) -#define vdiv_vx_i16m4(...) __riscv_vdiv_vx_i16m4(__VA_ARGS__) -#define vdiv_vv_i16m8(...) __riscv_vdiv_vv_i16m8(__VA_ARGS__) -#define vdiv_vx_i16m8(...) __riscv_vdiv_vx_i16m8(__VA_ARGS__) -#define vdiv_vv_i32mf2(...) __riscv_vdiv_vv_i32mf2(__VA_ARGS__) -#define vdiv_vx_i32mf2(...) __riscv_vdiv_vx_i32mf2(__VA_ARGS__) -#define vdiv_vv_i32m1(...) __riscv_vdiv_vv_i32m1(__VA_ARGS__) -#define vdiv_vx_i32m1(...) __riscv_vdiv_vx_i32m1(__VA_ARGS__) -#define vdiv_vv_i32m2(...) __riscv_vdiv_vv_i32m2(__VA_ARGS__) -#define vdiv_vx_i32m2(...) __riscv_vdiv_vx_i32m2(__VA_ARGS__) -#define vdiv_vv_i32m4(...) __riscv_vdiv_vv_i32m4(__VA_ARGS__) -#define vdiv_vx_i32m4(...) __riscv_vdiv_vx_i32m4(__VA_ARGS__) -#define vdiv_vv_i32m8(...) __riscv_vdiv_vv_i32m8(__VA_ARGS__) -#define vdiv_vx_i32m8(...) __riscv_vdiv_vx_i32m8(__VA_ARGS__) -#define vdiv_vv_i64m1(...) __riscv_vdiv_vv_i64m1(__VA_ARGS__) -#define vdiv_vx_i64m1(...) __riscv_vdiv_vx_i64m1(__VA_ARGS__) -#define vdiv_vv_i64m2(...) __riscv_vdiv_vv_i64m2(__VA_ARGS__) -#define vdiv_vx_i64m2(...) __riscv_vdiv_vx_i64m2(__VA_ARGS__) -#define vdiv_vv_i64m4(...) __riscv_vdiv_vv_i64m4(__VA_ARGS__) -#define vdiv_vx_i64m4(...) __riscv_vdiv_vx_i64m4(__VA_ARGS__) -#define vdiv_vv_i64m8(...) __riscv_vdiv_vv_i64m8(__VA_ARGS__) -#define vdiv_vx_i64m8(...) __riscv_vdiv_vx_i64m8(__VA_ARGS__) -#define vrem_vv_i8mf8(...) __riscv_vrem_vv_i8mf8(__VA_ARGS__) -#define vrem_vx_i8mf8(...) __riscv_vrem_vx_i8mf8(__VA_ARGS__) -#define vrem_vv_i8mf4(...) __riscv_vrem_vv_i8mf4(__VA_ARGS__) -#define vrem_vx_i8mf4(...) __riscv_vrem_vx_i8mf4(__VA_ARGS__) -#define vrem_vv_i8mf2(...) __riscv_vrem_vv_i8mf2(__VA_ARGS__) -#define vrem_vx_i8mf2(...) __riscv_vrem_vx_i8mf2(__VA_ARGS__) -#define vrem_vv_i8m1(...) __riscv_vrem_vv_i8m1(__VA_ARGS__) -#define vrem_vx_i8m1(...) __riscv_vrem_vx_i8m1(__VA_ARGS__) -#define vrem_vv_i8m2(...) __riscv_vrem_vv_i8m2(__VA_ARGS__) -#define vrem_vx_i8m2(...) __riscv_vrem_vx_i8m2(__VA_ARGS__) -#define vrem_vv_i8m4(...) __riscv_vrem_vv_i8m4(__VA_ARGS__) -#define vrem_vx_i8m4(...) __riscv_vrem_vx_i8m4(__VA_ARGS__) -#define vrem_vv_i8m8(...) __riscv_vrem_vv_i8m8(__VA_ARGS__) -#define vrem_vx_i8m8(...) __riscv_vrem_vx_i8m8(__VA_ARGS__) -#define vrem_vv_i16mf4(...) __riscv_vrem_vv_i16mf4(__VA_ARGS__) -#define vrem_vx_i16mf4(...) __riscv_vrem_vx_i16mf4(__VA_ARGS__) -#define vrem_vv_i16mf2(...) __riscv_vrem_vv_i16mf2(__VA_ARGS__) -#define vrem_vx_i16mf2(...) __riscv_vrem_vx_i16mf2(__VA_ARGS__) -#define vrem_vv_i16m1(...) __riscv_vrem_vv_i16m1(__VA_ARGS__) -#define vrem_vx_i16m1(...) __riscv_vrem_vx_i16m1(__VA_ARGS__) -#define vrem_vv_i16m2(...) __riscv_vrem_vv_i16m2(__VA_ARGS__) -#define vrem_vx_i16m2(...) __riscv_vrem_vx_i16m2(__VA_ARGS__) -#define vrem_vv_i16m4(...) __riscv_vrem_vv_i16m4(__VA_ARGS__) -#define vrem_vx_i16m4(...) __riscv_vrem_vx_i16m4(__VA_ARGS__) -#define vrem_vv_i16m8(...) __riscv_vrem_vv_i16m8(__VA_ARGS__) -#define vrem_vx_i16m8(...) __riscv_vrem_vx_i16m8(__VA_ARGS__) -#define vrem_vv_i32mf2(...) __riscv_vrem_vv_i32mf2(__VA_ARGS__) -#define vrem_vx_i32mf2(...) __riscv_vrem_vx_i32mf2(__VA_ARGS__) -#define vrem_vv_i32m1(...) __riscv_vrem_vv_i32m1(__VA_ARGS__) -#define vrem_vx_i32m1(...) __riscv_vrem_vx_i32m1(__VA_ARGS__) -#define vrem_vv_i32m2(...) __riscv_vrem_vv_i32m2(__VA_ARGS__) -#define vrem_vx_i32m2(...) __riscv_vrem_vx_i32m2(__VA_ARGS__) -#define vrem_vv_i32m4(...) __riscv_vrem_vv_i32m4(__VA_ARGS__) -#define vrem_vx_i32m4(...) __riscv_vrem_vx_i32m4(__VA_ARGS__) -#define vrem_vv_i32m8(...) __riscv_vrem_vv_i32m8(__VA_ARGS__) -#define vrem_vx_i32m8(...) __riscv_vrem_vx_i32m8(__VA_ARGS__) -#define vrem_vv_i64m1(...) __riscv_vrem_vv_i64m1(__VA_ARGS__) -#define vrem_vx_i64m1(...) __riscv_vrem_vx_i64m1(__VA_ARGS__) -#define vrem_vv_i64m2(...) __riscv_vrem_vv_i64m2(__VA_ARGS__) -#define vrem_vx_i64m2(...) __riscv_vrem_vx_i64m2(__VA_ARGS__) -#define vrem_vv_i64m4(...) __riscv_vrem_vv_i64m4(__VA_ARGS__) -#define vrem_vx_i64m4(...) __riscv_vrem_vx_i64m4(__VA_ARGS__) -#define vrem_vv_i64m8(...) __riscv_vrem_vv_i64m8(__VA_ARGS__) -#define vrem_vx_i64m8(...) __riscv_vrem_vx_i64m8(__VA_ARGS__) -#define vdivu_vv_u8mf8(...) __riscv_vdivu_vv_u8mf8(__VA_ARGS__) -#define vdivu_vx_u8mf8(...) __riscv_vdivu_vx_u8mf8(__VA_ARGS__) -#define vdivu_vv_u8mf4(...) __riscv_vdivu_vv_u8mf4(__VA_ARGS__) -#define vdivu_vx_u8mf4(...) __riscv_vdivu_vx_u8mf4(__VA_ARGS__) -#define vdivu_vv_u8mf2(...) __riscv_vdivu_vv_u8mf2(__VA_ARGS__) -#define vdivu_vx_u8mf2(...) __riscv_vdivu_vx_u8mf2(__VA_ARGS__) -#define vdivu_vv_u8m1(...) __riscv_vdivu_vv_u8m1(__VA_ARGS__) -#define vdivu_vx_u8m1(...) __riscv_vdivu_vx_u8m1(__VA_ARGS__) -#define vdivu_vv_u8m2(...) __riscv_vdivu_vv_u8m2(__VA_ARGS__) -#define vdivu_vx_u8m2(...) __riscv_vdivu_vx_u8m2(__VA_ARGS__) -#define vdivu_vv_u8m4(...) __riscv_vdivu_vv_u8m4(__VA_ARGS__) -#define vdivu_vx_u8m4(...) __riscv_vdivu_vx_u8m4(__VA_ARGS__) -#define vdivu_vv_u8m8(...) __riscv_vdivu_vv_u8m8(__VA_ARGS__) -#define vdivu_vx_u8m8(...) __riscv_vdivu_vx_u8m8(__VA_ARGS__) -#define vdivu_vv_u16mf4(...) __riscv_vdivu_vv_u16mf4(__VA_ARGS__) -#define vdivu_vx_u16mf4(...) __riscv_vdivu_vx_u16mf4(__VA_ARGS__) -#define vdivu_vv_u16mf2(...) __riscv_vdivu_vv_u16mf2(__VA_ARGS__) -#define vdivu_vx_u16mf2(...) __riscv_vdivu_vx_u16mf2(__VA_ARGS__) -#define vdivu_vv_u16m1(...) __riscv_vdivu_vv_u16m1(__VA_ARGS__) -#define vdivu_vx_u16m1(...) __riscv_vdivu_vx_u16m1(__VA_ARGS__) -#define vdivu_vv_u16m2(...) __riscv_vdivu_vv_u16m2(__VA_ARGS__) -#define vdivu_vx_u16m2(...) __riscv_vdivu_vx_u16m2(__VA_ARGS__) -#define vdivu_vv_u16m4(...) __riscv_vdivu_vv_u16m4(__VA_ARGS__) -#define vdivu_vx_u16m4(...) __riscv_vdivu_vx_u16m4(__VA_ARGS__) -#define vdivu_vv_u16m8(...) __riscv_vdivu_vv_u16m8(__VA_ARGS__) -#define vdivu_vx_u16m8(...) __riscv_vdivu_vx_u16m8(__VA_ARGS__) -#define vdivu_vv_u32mf2(...) __riscv_vdivu_vv_u32mf2(__VA_ARGS__) -#define vdivu_vx_u32mf2(...) __riscv_vdivu_vx_u32mf2(__VA_ARGS__) -#define vdivu_vv_u32m1(...) __riscv_vdivu_vv_u32m1(__VA_ARGS__) -#define vdivu_vx_u32m1(...) __riscv_vdivu_vx_u32m1(__VA_ARGS__) -#define vdivu_vv_u32m2(...) __riscv_vdivu_vv_u32m2(__VA_ARGS__) -#define vdivu_vx_u32m2(...) __riscv_vdivu_vx_u32m2(__VA_ARGS__) -#define vdivu_vv_u32m4(...) __riscv_vdivu_vv_u32m4(__VA_ARGS__) -#define vdivu_vx_u32m4(...) __riscv_vdivu_vx_u32m4(__VA_ARGS__) -#define vdivu_vv_u32m8(...) __riscv_vdivu_vv_u32m8(__VA_ARGS__) -#define vdivu_vx_u32m8(...) __riscv_vdivu_vx_u32m8(__VA_ARGS__) -#define vdivu_vv_u64m1(...) __riscv_vdivu_vv_u64m1(__VA_ARGS__) -#define vdivu_vx_u64m1(...) __riscv_vdivu_vx_u64m1(__VA_ARGS__) -#define vdivu_vv_u64m2(...) __riscv_vdivu_vv_u64m2(__VA_ARGS__) -#define vdivu_vx_u64m2(...) __riscv_vdivu_vx_u64m2(__VA_ARGS__) -#define vdivu_vv_u64m4(...) __riscv_vdivu_vv_u64m4(__VA_ARGS__) -#define vdivu_vx_u64m4(...) __riscv_vdivu_vx_u64m4(__VA_ARGS__) -#define vdivu_vv_u64m8(...) __riscv_vdivu_vv_u64m8(__VA_ARGS__) -#define vdivu_vx_u64m8(...) __riscv_vdivu_vx_u64m8(__VA_ARGS__) -#define vremu_vv_u8mf8(...) __riscv_vremu_vv_u8mf8(__VA_ARGS__) -#define vremu_vx_u8mf8(...) __riscv_vremu_vx_u8mf8(__VA_ARGS__) -#define vremu_vv_u8mf4(...) __riscv_vremu_vv_u8mf4(__VA_ARGS__) -#define vremu_vx_u8mf4(...) __riscv_vremu_vx_u8mf4(__VA_ARGS__) -#define vremu_vv_u8mf2(...) __riscv_vremu_vv_u8mf2(__VA_ARGS__) -#define vremu_vx_u8mf2(...) __riscv_vremu_vx_u8mf2(__VA_ARGS__) -#define vremu_vv_u8m1(...) __riscv_vremu_vv_u8m1(__VA_ARGS__) -#define vremu_vx_u8m1(...) __riscv_vremu_vx_u8m1(__VA_ARGS__) -#define vremu_vv_u8m2(...) __riscv_vremu_vv_u8m2(__VA_ARGS__) -#define vremu_vx_u8m2(...) __riscv_vremu_vx_u8m2(__VA_ARGS__) -#define vremu_vv_u8m4(...) __riscv_vremu_vv_u8m4(__VA_ARGS__) -#define vremu_vx_u8m4(...) __riscv_vremu_vx_u8m4(__VA_ARGS__) -#define vremu_vv_u8m8(...) __riscv_vremu_vv_u8m8(__VA_ARGS__) -#define vremu_vx_u8m8(...) __riscv_vremu_vx_u8m8(__VA_ARGS__) -#define vremu_vv_u16mf4(...) __riscv_vremu_vv_u16mf4(__VA_ARGS__) -#define vremu_vx_u16mf4(...) __riscv_vremu_vx_u16mf4(__VA_ARGS__) -#define vremu_vv_u16mf2(...) __riscv_vremu_vv_u16mf2(__VA_ARGS__) -#define vremu_vx_u16mf2(...) __riscv_vremu_vx_u16mf2(__VA_ARGS__) -#define vremu_vv_u16m1(...) __riscv_vremu_vv_u16m1(__VA_ARGS__) -#define vremu_vx_u16m1(...) __riscv_vremu_vx_u16m1(__VA_ARGS__) -#define vremu_vv_u16m2(...) __riscv_vremu_vv_u16m2(__VA_ARGS__) -#define vremu_vx_u16m2(...) __riscv_vremu_vx_u16m2(__VA_ARGS__) -#define vremu_vv_u16m4(...) __riscv_vremu_vv_u16m4(__VA_ARGS__) -#define vremu_vx_u16m4(...) __riscv_vremu_vx_u16m4(__VA_ARGS__) -#define vremu_vv_u16m8(...) __riscv_vremu_vv_u16m8(__VA_ARGS__) -#define vremu_vx_u16m8(...) __riscv_vremu_vx_u16m8(__VA_ARGS__) -#define vremu_vv_u32mf2(...) __riscv_vremu_vv_u32mf2(__VA_ARGS__) -#define vremu_vx_u32mf2(...) __riscv_vremu_vx_u32mf2(__VA_ARGS__) -#define vremu_vv_u32m1(...) __riscv_vremu_vv_u32m1(__VA_ARGS__) -#define vremu_vx_u32m1(...) __riscv_vremu_vx_u32m1(__VA_ARGS__) -#define vremu_vv_u32m2(...) __riscv_vremu_vv_u32m2(__VA_ARGS__) -#define vremu_vx_u32m2(...) __riscv_vremu_vx_u32m2(__VA_ARGS__) -#define vremu_vv_u32m4(...) __riscv_vremu_vv_u32m4(__VA_ARGS__) -#define vremu_vx_u32m4(...) __riscv_vremu_vx_u32m4(__VA_ARGS__) -#define vremu_vv_u32m8(...) __riscv_vremu_vv_u32m8(__VA_ARGS__) -#define vremu_vx_u32m8(...) __riscv_vremu_vx_u32m8(__VA_ARGS__) -#define vremu_vv_u64m1(...) __riscv_vremu_vv_u64m1(__VA_ARGS__) -#define vremu_vx_u64m1(...) __riscv_vremu_vx_u64m1(__VA_ARGS__) -#define vremu_vv_u64m2(...) __riscv_vremu_vv_u64m2(__VA_ARGS__) -#define vremu_vx_u64m2(...) __riscv_vremu_vx_u64m2(__VA_ARGS__) -#define vremu_vv_u64m4(...) __riscv_vremu_vv_u64m4(__VA_ARGS__) -#define vremu_vx_u64m4(...) __riscv_vremu_vx_u64m4(__VA_ARGS__) -#define vremu_vv_u64m8(...) __riscv_vremu_vv_u64m8(__VA_ARGS__) -#define vremu_vx_u64m8(...) __riscv_vremu_vx_u64m8(__VA_ARGS__) -// masked functions -#define vdiv_vv_i8mf8_m(...) __riscv_vdiv_vv_i8mf8_tumu(__VA_ARGS__) -#define vdiv_vx_i8mf8_m(...) __riscv_vdiv_vx_i8mf8_tumu(__VA_ARGS__) -#define vdiv_vv_i8mf4_m(...) __riscv_vdiv_vv_i8mf4_tumu(__VA_ARGS__) -#define vdiv_vx_i8mf4_m(...) __riscv_vdiv_vx_i8mf4_tumu(__VA_ARGS__) -#define vdiv_vv_i8mf2_m(...) __riscv_vdiv_vv_i8mf2_tumu(__VA_ARGS__) -#define vdiv_vx_i8mf2_m(...) __riscv_vdiv_vx_i8mf2_tumu(__VA_ARGS__) -#define vdiv_vv_i8m1_m(...) __riscv_vdiv_vv_i8m1_tumu(__VA_ARGS__) -#define vdiv_vx_i8m1_m(...) __riscv_vdiv_vx_i8m1_tumu(__VA_ARGS__) -#define vdiv_vv_i8m2_m(...) __riscv_vdiv_vv_i8m2_tumu(__VA_ARGS__) -#define vdiv_vx_i8m2_m(...) __riscv_vdiv_vx_i8m2_tumu(__VA_ARGS__) -#define vdiv_vv_i8m4_m(...) __riscv_vdiv_vv_i8m4_tumu(__VA_ARGS__) -#define vdiv_vx_i8m4_m(...) __riscv_vdiv_vx_i8m4_tumu(__VA_ARGS__) -#define vdiv_vv_i8m8_m(...) __riscv_vdiv_vv_i8m8_tumu(__VA_ARGS__) -#define vdiv_vx_i8m8_m(...) __riscv_vdiv_vx_i8m8_tumu(__VA_ARGS__) -#define vdiv_vv_i16mf4_m(...) __riscv_vdiv_vv_i16mf4_tumu(__VA_ARGS__) -#define vdiv_vx_i16mf4_m(...) __riscv_vdiv_vx_i16mf4_tumu(__VA_ARGS__) -#define vdiv_vv_i16mf2_m(...) __riscv_vdiv_vv_i16mf2_tumu(__VA_ARGS__) -#define vdiv_vx_i16mf2_m(...) __riscv_vdiv_vx_i16mf2_tumu(__VA_ARGS__) -#define vdiv_vv_i16m1_m(...) __riscv_vdiv_vv_i16m1_tumu(__VA_ARGS__) -#define vdiv_vx_i16m1_m(...) __riscv_vdiv_vx_i16m1_tumu(__VA_ARGS__) -#define vdiv_vv_i16m2_m(...) __riscv_vdiv_vv_i16m2_tumu(__VA_ARGS__) -#define vdiv_vx_i16m2_m(...) __riscv_vdiv_vx_i16m2_tumu(__VA_ARGS__) -#define vdiv_vv_i16m4_m(...) __riscv_vdiv_vv_i16m4_tumu(__VA_ARGS__) -#define vdiv_vx_i16m4_m(...) __riscv_vdiv_vx_i16m4_tumu(__VA_ARGS__) -#define vdiv_vv_i16m8_m(...) __riscv_vdiv_vv_i16m8_tumu(__VA_ARGS__) -#define vdiv_vx_i16m8_m(...) __riscv_vdiv_vx_i16m8_tumu(__VA_ARGS__) -#define vdiv_vv_i32mf2_m(...) __riscv_vdiv_vv_i32mf2_tumu(__VA_ARGS__) -#define vdiv_vx_i32mf2_m(...) __riscv_vdiv_vx_i32mf2_tumu(__VA_ARGS__) -#define vdiv_vv_i32m1_m(...) __riscv_vdiv_vv_i32m1_tumu(__VA_ARGS__) -#define vdiv_vx_i32m1_m(...) __riscv_vdiv_vx_i32m1_tumu(__VA_ARGS__) -#define vdiv_vv_i32m2_m(...) __riscv_vdiv_vv_i32m2_tumu(__VA_ARGS__) -#define vdiv_vx_i32m2_m(...) __riscv_vdiv_vx_i32m2_tumu(__VA_ARGS__) -#define vdiv_vv_i32m4_m(...) __riscv_vdiv_vv_i32m4_tumu(__VA_ARGS__) -#define vdiv_vx_i32m4_m(...) __riscv_vdiv_vx_i32m4_tumu(__VA_ARGS__) -#define vdiv_vv_i32m8_m(...) __riscv_vdiv_vv_i32m8_tumu(__VA_ARGS__) -#define vdiv_vx_i32m8_m(...) __riscv_vdiv_vx_i32m8_tumu(__VA_ARGS__) -#define vdiv_vv_i64m1_m(...) __riscv_vdiv_vv_i64m1_tumu(__VA_ARGS__) -#define vdiv_vx_i64m1_m(...) __riscv_vdiv_vx_i64m1_tumu(__VA_ARGS__) -#define vdiv_vv_i64m2_m(...) __riscv_vdiv_vv_i64m2_tumu(__VA_ARGS__) -#define vdiv_vx_i64m2_m(...) __riscv_vdiv_vx_i64m2_tumu(__VA_ARGS__) -#define vdiv_vv_i64m4_m(...) __riscv_vdiv_vv_i64m4_tumu(__VA_ARGS__) -#define vdiv_vx_i64m4_m(...) __riscv_vdiv_vx_i64m4_tumu(__VA_ARGS__) -#define vdiv_vv_i64m8_m(...) __riscv_vdiv_vv_i64m8_tumu(__VA_ARGS__) -#define vdiv_vx_i64m8_m(...) __riscv_vdiv_vx_i64m8_tumu(__VA_ARGS__) -#define vrem_vv_i8mf8_m(...) __riscv_vrem_vv_i8mf8_tumu(__VA_ARGS__) -#define vrem_vx_i8mf8_m(...) __riscv_vrem_vx_i8mf8_tumu(__VA_ARGS__) -#define vrem_vv_i8mf4_m(...) __riscv_vrem_vv_i8mf4_tumu(__VA_ARGS__) -#define vrem_vx_i8mf4_m(...) __riscv_vrem_vx_i8mf4_tumu(__VA_ARGS__) -#define vrem_vv_i8mf2_m(...) __riscv_vrem_vv_i8mf2_tumu(__VA_ARGS__) -#define vrem_vx_i8mf2_m(...) __riscv_vrem_vx_i8mf2_tumu(__VA_ARGS__) -#define vrem_vv_i8m1_m(...) __riscv_vrem_vv_i8m1_tumu(__VA_ARGS__) -#define vrem_vx_i8m1_m(...) __riscv_vrem_vx_i8m1_tumu(__VA_ARGS__) -#define vrem_vv_i8m2_m(...) __riscv_vrem_vv_i8m2_tumu(__VA_ARGS__) -#define vrem_vx_i8m2_m(...) __riscv_vrem_vx_i8m2_tumu(__VA_ARGS__) -#define vrem_vv_i8m4_m(...) __riscv_vrem_vv_i8m4_tumu(__VA_ARGS__) -#define vrem_vx_i8m4_m(...) __riscv_vrem_vx_i8m4_tumu(__VA_ARGS__) -#define vrem_vv_i8m8_m(...) __riscv_vrem_vv_i8m8_tumu(__VA_ARGS__) -#define vrem_vx_i8m8_m(...) __riscv_vrem_vx_i8m8_tumu(__VA_ARGS__) -#define vrem_vv_i16mf4_m(...) __riscv_vrem_vv_i16mf4_tumu(__VA_ARGS__) -#define vrem_vx_i16mf4_m(...) __riscv_vrem_vx_i16mf4_tumu(__VA_ARGS__) -#define vrem_vv_i16mf2_m(...) __riscv_vrem_vv_i16mf2_tumu(__VA_ARGS__) -#define vrem_vx_i16mf2_m(...) __riscv_vrem_vx_i16mf2_tumu(__VA_ARGS__) -#define vrem_vv_i16m1_m(...) __riscv_vrem_vv_i16m1_tumu(__VA_ARGS__) -#define vrem_vx_i16m1_m(...) __riscv_vrem_vx_i16m1_tumu(__VA_ARGS__) -#define vrem_vv_i16m2_m(...) __riscv_vrem_vv_i16m2_tumu(__VA_ARGS__) -#define vrem_vx_i16m2_m(...) __riscv_vrem_vx_i16m2_tumu(__VA_ARGS__) -#define vrem_vv_i16m4_m(...) __riscv_vrem_vv_i16m4_tumu(__VA_ARGS__) -#define vrem_vx_i16m4_m(...) __riscv_vrem_vx_i16m4_tumu(__VA_ARGS__) -#define vrem_vv_i16m8_m(...) __riscv_vrem_vv_i16m8_tumu(__VA_ARGS__) -#define vrem_vx_i16m8_m(...) __riscv_vrem_vx_i16m8_tumu(__VA_ARGS__) -#define vrem_vv_i32mf2_m(...) __riscv_vrem_vv_i32mf2_tumu(__VA_ARGS__) -#define vrem_vx_i32mf2_m(...) __riscv_vrem_vx_i32mf2_tumu(__VA_ARGS__) -#define vrem_vv_i32m1_m(...) __riscv_vrem_vv_i32m1_tumu(__VA_ARGS__) -#define vrem_vx_i32m1_m(...) __riscv_vrem_vx_i32m1_tumu(__VA_ARGS__) -#define vrem_vv_i32m2_m(...) __riscv_vrem_vv_i32m2_tumu(__VA_ARGS__) -#define vrem_vx_i32m2_m(...) __riscv_vrem_vx_i32m2_tumu(__VA_ARGS__) -#define vrem_vv_i32m4_m(...) __riscv_vrem_vv_i32m4_tumu(__VA_ARGS__) -#define vrem_vx_i32m4_m(...) __riscv_vrem_vx_i32m4_tumu(__VA_ARGS__) -#define vrem_vv_i32m8_m(...) __riscv_vrem_vv_i32m8_tumu(__VA_ARGS__) -#define vrem_vx_i32m8_m(...) __riscv_vrem_vx_i32m8_tumu(__VA_ARGS__) -#define vrem_vv_i64m1_m(...) __riscv_vrem_vv_i64m1_tumu(__VA_ARGS__) -#define vrem_vx_i64m1_m(...) __riscv_vrem_vx_i64m1_tumu(__VA_ARGS__) -#define vrem_vv_i64m2_m(...) __riscv_vrem_vv_i64m2_tumu(__VA_ARGS__) -#define vrem_vx_i64m2_m(...) __riscv_vrem_vx_i64m2_tumu(__VA_ARGS__) -#define vrem_vv_i64m4_m(...) __riscv_vrem_vv_i64m4_tumu(__VA_ARGS__) -#define vrem_vx_i64m4_m(...) __riscv_vrem_vx_i64m4_tumu(__VA_ARGS__) -#define vrem_vv_i64m8_m(...) __riscv_vrem_vv_i64m8_tumu(__VA_ARGS__) -#define vrem_vx_i64m8_m(...) __riscv_vrem_vx_i64m8_tumu(__VA_ARGS__) -#define vdivu_vv_u8mf8_m(...) __riscv_vdivu_vv_u8mf8_tumu(__VA_ARGS__) -#define vdivu_vx_u8mf8_m(...) __riscv_vdivu_vx_u8mf8_tumu(__VA_ARGS__) -#define vdivu_vv_u8mf4_m(...) __riscv_vdivu_vv_u8mf4_tumu(__VA_ARGS__) -#define vdivu_vx_u8mf4_m(...) __riscv_vdivu_vx_u8mf4_tumu(__VA_ARGS__) -#define vdivu_vv_u8mf2_m(...) __riscv_vdivu_vv_u8mf2_tumu(__VA_ARGS__) -#define vdivu_vx_u8mf2_m(...) __riscv_vdivu_vx_u8mf2_tumu(__VA_ARGS__) -#define vdivu_vv_u8m1_m(...) __riscv_vdivu_vv_u8m1_tumu(__VA_ARGS__) -#define vdivu_vx_u8m1_m(...) __riscv_vdivu_vx_u8m1_tumu(__VA_ARGS__) -#define vdivu_vv_u8m2_m(...) __riscv_vdivu_vv_u8m2_tumu(__VA_ARGS__) -#define vdivu_vx_u8m2_m(...) __riscv_vdivu_vx_u8m2_tumu(__VA_ARGS__) -#define vdivu_vv_u8m4_m(...) __riscv_vdivu_vv_u8m4_tumu(__VA_ARGS__) -#define vdivu_vx_u8m4_m(...) __riscv_vdivu_vx_u8m4_tumu(__VA_ARGS__) -#define vdivu_vv_u8m8_m(...) __riscv_vdivu_vv_u8m8_tumu(__VA_ARGS__) -#define vdivu_vx_u8m8_m(...) __riscv_vdivu_vx_u8m8_tumu(__VA_ARGS__) -#define vdivu_vv_u16mf4_m(...) __riscv_vdivu_vv_u16mf4_tumu(__VA_ARGS__) -#define vdivu_vx_u16mf4_m(...) __riscv_vdivu_vx_u16mf4_tumu(__VA_ARGS__) -#define vdivu_vv_u16mf2_m(...) __riscv_vdivu_vv_u16mf2_tumu(__VA_ARGS__) -#define vdivu_vx_u16mf2_m(...) __riscv_vdivu_vx_u16mf2_tumu(__VA_ARGS__) -#define vdivu_vv_u16m1_m(...) __riscv_vdivu_vv_u16m1_tumu(__VA_ARGS__) -#define vdivu_vx_u16m1_m(...) __riscv_vdivu_vx_u16m1_tumu(__VA_ARGS__) -#define vdivu_vv_u16m2_m(...) __riscv_vdivu_vv_u16m2_tumu(__VA_ARGS__) -#define vdivu_vx_u16m2_m(...) __riscv_vdivu_vx_u16m2_tumu(__VA_ARGS__) -#define vdivu_vv_u16m4_m(...) __riscv_vdivu_vv_u16m4_tumu(__VA_ARGS__) -#define vdivu_vx_u16m4_m(...) __riscv_vdivu_vx_u16m4_tumu(__VA_ARGS__) -#define vdivu_vv_u16m8_m(...) __riscv_vdivu_vv_u16m8_tumu(__VA_ARGS__) -#define vdivu_vx_u16m8_m(...) __riscv_vdivu_vx_u16m8_tumu(__VA_ARGS__) -#define vdivu_vv_u32mf2_m(...) __riscv_vdivu_vv_u32mf2_tumu(__VA_ARGS__) -#define vdivu_vx_u32mf2_m(...) __riscv_vdivu_vx_u32mf2_tumu(__VA_ARGS__) -#define vdivu_vv_u32m1_m(...) __riscv_vdivu_vv_u32m1_tumu(__VA_ARGS__) -#define vdivu_vx_u32m1_m(...) __riscv_vdivu_vx_u32m1_tumu(__VA_ARGS__) -#define vdivu_vv_u32m2_m(...) __riscv_vdivu_vv_u32m2_tumu(__VA_ARGS__) -#define vdivu_vx_u32m2_m(...) __riscv_vdivu_vx_u32m2_tumu(__VA_ARGS__) -#define vdivu_vv_u32m4_m(...) __riscv_vdivu_vv_u32m4_tumu(__VA_ARGS__) -#define vdivu_vx_u32m4_m(...) __riscv_vdivu_vx_u32m4_tumu(__VA_ARGS__) -#define vdivu_vv_u32m8_m(...) __riscv_vdivu_vv_u32m8_tumu(__VA_ARGS__) -#define vdivu_vx_u32m8_m(...) __riscv_vdivu_vx_u32m8_tumu(__VA_ARGS__) -#define vdivu_vv_u64m1_m(...) __riscv_vdivu_vv_u64m1_tumu(__VA_ARGS__) -#define vdivu_vx_u64m1_m(...) __riscv_vdivu_vx_u64m1_tumu(__VA_ARGS__) -#define vdivu_vv_u64m2_m(...) __riscv_vdivu_vv_u64m2_tumu(__VA_ARGS__) -#define vdivu_vx_u64m2_m(...) __riscv_vdivu_vx_u64m2_tumu(__VA_ARGS__) -#define vdivu_vv_u64m4_m(...) __riscv_vdivu_vv_u64m4_tumu(__VA_ARGS__) -#define vdivu_vx_u64m4_m(...) __riscv_vdivu_vx_u64m4_tumu(__VA_ARGS__) -#define vdivu_vv_u64m8_m(...) __riscv_vdivu_vv_u64m8_tumu(__VA_ARGS__) -#define vdivu_vx_u64m8_m(...) __riscv_vdivu_vx_u64m8_tumu(__VA_ARGS__) -#define vremu_vv_u8mf8_m(...) __riscv_vremu_vv_u8mf8_tumu(__VA_ARGS__) -#define vremu_vx_u8mf8_m(...) __riscv_vremu_vx_u8mf8_tumu(__VA_ARGS__) -#define vremu_vv_u8mf4_m(...) __riscv_vremu_vv_u8mf4_tumu(__VA_ARGS__) -#define vremu_vx_u8mf4_m(...) __riscv_vremu_vx_u8mf4_tumu(__VA_ARGS__) -#define vremu_vv_u8mf2_m(...) __riscv_vremu_vv_u8mf2_tumu(__VA_ARGS__) -#define vremu_vx_u8mf2_m(...) __riscv_vremu_vx_u8mf2_tumu(__VA_ARGS__) -#define vremu_vv_u8m1_m(...) __riscv_vremu_vv_u8m1_tumu(__VA_ARGS__) -#define vremu_vx_u8m1_m(...) __riscv_vremu_vx_u8m1_tumu(__VA_ARGS__) -#define vremu_vv_u8m2_m(...) __riscv_vremu_vv_u8m2_tumu(__VA_ARGS__) -#define vremu_vx_u8m2_m(...) __riscv_vremu_vx_u8m2_tumu(__VA_ARGS__) -#define vremu_vv_u8m4_m(...) __riscv_vremu_vv_u8m4_tumu(__VA_ARGS__) -#define vremu_vx_u8m4_m(...) __riscv_vremu_vx_u8m4_tumu(__VA_ARGS__) -#define vremu_vv_u8m8_m(...) __riscv_vremu_vv_u8m8_tumu(__VA_ARGS__) -#define vremu_vx_u8m8_m(...) __riscv_vremu_vx_u8m8_tumu(__VA_ARGS__) -#define vremu_vv_u16mf4_m(...) __riscv_vremu_vv_u16mf4_tumu(__VA_ARGS__) -#define vremu_vx_u16mf4_m(...) __riscv_vremu_vx_u16mf4_tumu(__VA_ARGS__) -#define vremu_vv_u16mf2_m(...) __riscv_vremu_vv_u16mf2_tumu(__VA_ARGS__) -#define vremu_vx_u16mf2_m(...) __riscv_vremu_vx_u16mf2_tumu(__VA_ARGS__) -#define vremu_vv_u16m1_m(...) __riscv_vremu_vv_u16m1_tumu(__VA_ARGS__) -#define vremu_vx_u16m1_m(...) __riscv_vremu_vx_u16m1_tumu(__VA_ARGS__) -#define vremu_vv_u16m2_m(...) __riscv_vremu_vv_u16m2_tumu(__VA_ARGS__) -#define vremu_vx_u16m2_m(...) __riscv_vremu_vx_u16m2_tumu(__VA_ARGS__) -#define vremu_vv_u16m4_m(...) __riscv_vremu_vv_u16m4_tumu(__VA_ARGS__) -#define vremu_vx_u16m4_m(...) __riscv_vremu_vx_u16m4_tumu(__VA_ARGS__) -#define vremu_vv_u16m8_m(...) __riscv_vremu_vv_u16m8_tumu(__VA_ARGS__) -#define vremu_vx_u16m8_m(...) __riscv_vremu_vx_u16m8_tumu(__VA_ARGS__) -#define vremu_vv_u32mf2_m(...) __riscv_vremu_vv_u32mf2_tumu(__VA_ARGS__) -#define vremu_vx_u32mf2_m(...) __riscv_vremu_vx_u32mf2_tumu(__VA_ARGS__) -#define vremu_vv_u32m1_m(...) __riscv_vremu_vv_u32m1_tumu(__VA_ARGS__) -#define vremu_vx_u32m1_m(...) __riscv_vremu_vx_u32m1_tumu(__VA_ARGS__) -#define vremu_vv_u32m2_m(...) __riscv_vremu_vv_u32m2_tumu(__VA_ARGS__) -#define vremu_vx_u32m2_m(...) __riscv_vremu_vx_u32m2_tumu(__VA_ARGS__) -#define vremu_vv_u32m4_m(...) __riscv_vremu_vv_u32m4_tumu(__VA_ARGS__) -#define vremu_vx_u32m4_m(...) __riscv_vremu_vx_u32m4_tumu(__VA_ARGS__) -#define vremu_vv_u32m8_m(...) __riscv_vremu_vv_u32m8_tumu(__VA_ARGS__) -#define vremu_vx_u32m8_m(...) __riscv_vremu_vx_u32m8_tumu(__VA_ARGS__) -#define vremu_vv_u64m1_m(...) __riscv_vremu_vv_u64m1_tumu(__VA_ARGS__) -#define vremu_vx_u64m1_m(...) __riscv_vremu_vx_u64m1_tumu(__VA_ARGS__) -#define vremu_vv_u64m2_m(...) __riscv_vremu_vv_u64m2_tumu(__VA_ARGS__) -#define vremu_vx_u64m2_m(...) __riscv_vremu_vx_u64m2_tumu(__VA_ARGS__) -#define vremu_vv_u64m4_m(...) __riscv_vremu_vv_u64m4_tumu(__VA_ARGS__) -#define vremu_vx_u64m4_m(...) __riscv_vremu_vx_u64m4_tumu(__VA_ARGS__) -#define vremu_vv_u64m8_m(...) __riscv_vremu_vv_u64m8_tumu(__VA_ARGS__) -#define vremu_vx_u64m8_m(...) __riscv_vremu_vx_u64m8_tumu(__VA_ARGS__) -#define vwmul_vv_i16mf4(...) __riscv_vwmul_vv_i16mf4(__VA_ARGS__) -#define vwmul_vx_i16mf4(...) __riscv_vwmul_vx_i16mf4(__VA_ARGS__) -#define vwmul_vv_i16mf2(...) __riscv_vwmul_vv_i16mf2(__VA_ARGS__) -#define vwmul_vx_i16mf2(...) __riscv_vwmul_vx_i16mf2(__VA_ARGS__) -#define vwmul_vv_i16m1(...) __riscv_vwmul_vv_i16m1(__VA_ARGS__) -#define vwmul_vx_i16m1(...) __riscv_vwmul_vx_i16m1(__VA_ARGS__) -#define vwmul_vv_i16m2(...) __riscv_vwmul_vv_i16m2(__VA_ARGS__) -#define vwmul_vx_i16m2(...) __riscv_vwmul_vx_i16m2(__VA_ARGS__) -#define vwmul_vv_i16m4(...) __riscv_vwmul_vv_i16m4(__VA_ARGS__) -#define vwmul_vx_i16m4(...) __riscv_vwmul_vx_i16m4(__VA_ARGS__) -#define vwmul_vv_i16m8(...) __riscv_vwmul_vv_i16m8(__VA_ARGS__) -#define vwmul_vx_i16m8(...) __riscv_vwmul_vx_i16m8(__VA_ARGS__) -#define vwmul_vv_i32mf2(...) __riscv_vwmul_vv_i32mf2(__VA_ARGS__) -#define vwmul_vx_i32mf2(...) __riscv_vwmul_vx_i32mf2(__VA_ARGS__) -#define vwmul_vv_i32m1(...) __riscv_vwmul_vv_i32m1(__VA_ARGS__) -#define vwmul_vx_i32m1(...) __riscv_vwmul_vx_i32m1(__VA_ARGS__) -#define vwmul_vv_i32m2(...) __riscv_vwmul_vv_i32m2(__VA_ARGS__) -#define vwmul_vx_i32m2(...) __riscv_vwmul_vx_i32m2(__VA_ARGS__) -#define vwmul_vv_i32m4(...) __riscv_vwmul_vv_i32m4(__VA_ARGS__) -#define vwmul_vx_i32m4(...) __riscv_vwmul_vx_i32m4(__VA_ARGS__) -#define vwmul_vv_i32m8(...) __riscv_vwmul_vv_i32m8(__VA_ARGS__) -#define vwmul_vx_i32m8(...) __riscv_vwmul_vx_i32m8(__VA_ARGS__) -#define vwmul_vv_i64m1(...) __riscv_vwmul_vv_i64m1(__VA_ARGS__) -#define vwmul_vx_i64m1(...) __riscv_vwmul_vx_i64m1(__VA_ARGS__) -#define vwmul_vv_i64m2(...) __riscv_vwmul_vv_i64m2(__VA_ARGS__) -#define vwmul_vx_i64m2(...) __riscv_vwmul_vx_i64m2(__VA_ARGS__) -#define vwmul_vv_i64m4(...) __riscv_vwmul_vv_i64m4(__VA_ARGS__) -#define vwmul_vx_i64m4(...) __riscv_vwmul_vx_i64m4(__VA_ARGS__) -#define vwmul_vv_i64m8(...) __riscv_vwmul_vv_i64m8(__VA_ARGS__) -#define vwmul_vx_i64m8(...) __riscv_vwmul_vx_i64m8(__VA_ARGS__) -#define vwmulsu_vv_i16mf4(...) __riscv_vwmulsu_vv_i16mf4(__VA_ARGS__) -#define vwmulsu_vx_i16mf4(...) __riscv_vwmulsu_vx_i16mf4(__VA_ARGS__) -#define vwmulsu_vv_i16mf2(...) __riscv_vwmulsu_vv_i16mf2(__VA_ARGS__) -#define vwmulsu_vx_i16mf2(...) __riscv_vwmulsu_vx_i16mf2(__VA_ARGS__) -#define vwmulsu_vv_i16m1(...) __riscv_vwmulsu_vv_i16m1(__VA_ARGS__) -#define vwmulsu_vx_i16m1(...) __riscv_vwmulsu_vx_i16m1(__VA_ARGS__) -#define vwmulsu_vv_i16m2(...) __riscv_vwmulsu_vv_i16m2(__VA_ARGS__) -#define vwmulsu_vx_i16m2(...) __riscv_vwmulsu_vx_i16m2(__VA_ARGS__) -#define vwmulsu_vv_i16m4(...) __riscv_vwmulsu_vv_i16m4(__VA_ARGS__) -#define vwmulsu_vx_i16m4(...) __riscv_vwmulsu_vx_i16m4(__VA_ARGS__) -#define vwmulsu_vv_i16m8(...) __riscv_vwmulsu_vv_i16m8(__VA_ARGS__) -#define vwmulsu_vx_i16m8(...) __riscv_vwmulsu_vx_i16m8(__VA_ARGS__) -#define vwmulsu_vv_i32mf2(...) __riscv_vwmulsu_vv_i32mf2(__VA_ARGS__) -#define vwmulsu_vx_i32mf2(...) __riscv_vwmulsu_vx_i32mf2(__VA_ARGS__) -#define vwmulsu_vv_i32m1(...) __riscv_vwmulsu_vv_i32m1(__VA_ARGS__) -#define vwmulsu_vx_i32m1(...) __riscv_vwmulsu_vx_i32m1(__VA_ARGS__) -#define vwmulsu_vv_i32m2(...) __riscv_vwmulsu_vv_i32m2(__VA_ARGS__) -#define vwmulsu_vx_i32m2(...) __riscv_vwmulsu_vx_i32m2(__VA_ARGS__) -#define vwmulsu_vv_i32m4(...) __riscv_vwmulsu_vv_i32m4(__VA_ARGS__) -#define vwmulsu_vx_i32m4(...) __riscv_vwmulsu_vx_i32m4(__VA_ARGS__) -#define vwmulsu_vv_i32m8(...) __riscv_vwmulsu_vv_i32m8(__VA_ARGS__) -#define vwmulsu_vx_i32m8(...) __riscv_vwmulsu_vx_i32m8(__VA_ARGS__) -#define vwmulsu_vv_i64m1(...) __riscv_vwmulsu_vv_i64m1(__VA_ARGS__) -#define vwmulsu_vx_i64m1(...) __riscv_vwmulsu_vx_i64m1(__VA_ARGS__) -#define vwmulsu_vv_i64m2(...) __riscv_vwmulsu_vv_i64m2(__VA_ARGS__) -#define vwmulsu_vx_i64m2(...) __riscv_vwmulsu_vx_i64m2(__VA_ARGS__) -#define vwmulsu_vv_i64m4(...) __riscv_vwmulsu_vv_i64m4(__VA_ARGS__) -#define vwmulsu_vx_i64m4(...) __riscv_vwmulsu_vx_i64m4(__VA_ARGS__) -#define vwmulsu_vv_i64m8(...) __riscv_vwmulsu_vv_i64m8(__VA_ARGS__) -#define vwmulsu_vx_i64m8(...) __riscv_vwmulsu_vx_i64m8(__VA_ARGS__) -#define vwmulu_vv_u16mf4(...) __riscv_vwmulu_vv_u16mf4(__VA_ARGS__) -#define vwmulu_vx_u16mf4(...) __riscv_vwmulu_vx_u16mf4(__VA_ARGS__) -#define vwmulu_vv_u16mf2(...) __riscv_vwmulu_vv_u16mf2(__VA_ARGS__) -#define vwmulu_vx_u16mf2(...) __riscv_vwmulu_vx_u16mf2(__VA_ARGS__) -#define vwmulu_vv_u16m1(...) __riscv_vwmulu_vv_u16m1(__VA_ARGS__) -#define vwmulu_vx_u16m1(...) __riscv_vwmulu_vx_u16m1(__VA_ARGS__) -#define vwmulu_vv_u16m2(...) __riscv_vwmulu_vv_u16m2(__VA_ARGS__) -#define vwmulu_vx_u16m2(...) __riscv_vwmulu_vx_u16m2(__VA_ARGS__) -#define vwmulu_vv_u16m4(...) __riscv_vwmulu_vv_u16m4(__VA_ARGS__) -#define vwmulu_vx_u16m4(...) __riscv_vwmulu_vx_u16m4(__VA_ARGS__) -#define vwmulu_vv_u16m8(...) __riscv_vwmulu_vv_u16m8(__VA_ARGS__) -#define vwmulu_vx_u16m8(...) __riscv_vwmulu_vx_u16m8(__VA_ARGS__) -#define vwmulu_vv_u32mf2(...) __riscv_vwmulu_vv_u32mf2(__VA_ARGS__) -#define vwmulu_vx_u32mf2(...) __riscv_vwmulu_vx_u32mf2(__VA_ARGS__) -#define vwmulu_vv_u32m1(...) __riscv_vwmulu_vv_u32m1(__VA_ARGS__) -#define vwmulu_vx_u32m1(...) __riscv_vwmulu_vx_u32m1(__VA_ARGS__) -#define vwmulu_vv_u32m2(...) __riscv_vwmulu_vv_u32m2(__VA_ARGS__) -#define vwmulu_vx_u32m2(...) __riscv_vwmulu_vx_u32m2(__VA_ARGS__) -#define vwmulu_vv_u32m4(...) __riscv_vwmulu_vv_u32m4(__VA_ARGS__) -#define vwmulu_vx_u32m4(...) __riscv_vwmulu_vx_u32m4(__VA_ARGS__) -#define vwmulu_vv_u32m8(...) __riscv_vwmulu_vv_u32m8(__VA_ARGS__) -#define vwmulu_vx_u32m8(...) __riscv_vwmulu_vx_u32m8(__VA_ARGS__) -#define vwmulu_vv_u64m1(...) __riscv_vwmulu_vv_u64m1(__VA_ARGS__) -#define vwmulu_vx_u64m1(...) __riscv_vwmulu_vx_u64m1(__VA_ARGS__) -#define vwmulu_vv_u64m2(...) __riscv_vwmulu_vv_u64m2(__VA_ARGS__) -#define vwmulu_vx_u64m2(...) __riscv_vwmulu_vx_u64m2(__VA_ARGS__) -#define vwmulu_vv_u64m4(...) __riscv_vwmulu_vv_u64m4(__VA_ARGS__) -#define vwmulu_vx_u64m4(...) __riscv_vwmulu_vx_u64m4(__VA_ARGS__) -#define vwmulu_vv_u64m8(...) __riscv_vwmulu_vv_u64m8(__VA_ARGS__) -#define vwmulu_vx_u64m8(...) __riscv_vwmulu_vx_u64m8(__VA_ARGS__) -// masked functions -#define vwmul_vv_i16mf4_m(...) __riscv_vwmul_vv_i16mf4_tumu(__VA_ARGS__) -#define vwmul_vx_i16mf4_m(...) __riscv_vwmul_vx_i16mf4_tumu(__VA_ARGS__) -#define vwmul_vv_i16mf2_m(...) __riscv_vwmul_vv_i16mf2_tumu(__VA_ARGS__) -#define vwmul_vx_i16mf2_m(...) __riscv_vwmul_vx_i16mf2_tumu(__VA_ARGS__) -#define vwmul_vv_i16m1_m(...) __riscv_vwmul_vv_i16m1_tumu(__VA_ARGS__) -#define vwmul_vx_i16m1_m(...) __riscv_vwmul_vx_i16m1_tumu(__VA_ARGS__) -#define vwmul_vv_i16m2_m(...) __riscv_vwmul_vv_i16m2_tumu(__VA_ARGS__) -#define vwmul_vx_i16m2_m(...) __riscv_vwmul_vx_i16m2_tumu(__VA_ARGS__) -#define vwmul_vv_i16m4_m(...) __riscv_vwmul_vv_i16m4_tumu(__VA_ARGS__) -#define vwmul_vx_i16m4_m(...) __riscv_vwmul_vx_i16m4_tumu(__VA_ARGS__) -#define vwmul_vv_i16m8_m(...) __riscv_vwmul_vv_i16m8_tumu(__VA_ARGS__) -#define vwmul_vx_i16m8_m(...) __riscv_vwmul_vx_i16m8_tumu(__VA_ARGS__) -#define vwmul_vv_i32mf2_m(...) __riscv_vwmul_vv_i32mf2_tumu(__VA_ARGS__) -#define vwmul_vx_i32mf2_m(...) __riscv_vwmul_vx_i32mf2_tumu(__VA_ARGS__) -#define vwmul_vv_i32m1_m(...) __riscv_vwmul_vv_i32m1_tumu(__VA_ARGS__) -#define vwmul_vx_i32m1_m(...) __riscv_vwmul_vx_i32m1_tumu(__VA_ARGS__) -#define vwmul_vv_i32m2_m(...) __riscv_vwmul_vv_i32m2_tumu(__VA_ARGS__) -#define vwmul_vx_i32m2_m(...) __riscv_vwmul_vx_i32m2_tumu(__VA_ARGS__) -#define vwmul_vv_i32m4_m(...) __riscv_vwmul_vv_i32m4_tumu(__VA_ARGS__) -#define vwmul_vx_i32m4_m(...) __riscv_vwmul_vx_i32m4_tumu(__VA_ARGS__) -#define vwmul_vv_i32m8_m(...) __riscv_vwmul_vv_i32m8_tumu(__VA_ARGS__) -#define vwmul_vx_i32m8_m(...) __riscv_vwmul_vx_i32m8_tumu(__VA_ARGS__) -#define vwmul_vv_i64m1_m(...) __riscv_vwmul_vv_i64m1_tumu(__VA_ARGS__) -#define vwmul_vx_i64m1_m(...) __riscv_vwmul_vx_i64m1_tumu(__VA_ARGS__) -#define vwmul_vv_i64m2_m(...) __riscv_vwmul_vv_i64m2_tumu(__VA_ARGS__) -#define vwmul_vx_i64m2_m(...) __riscv_vwmul_vx_i64m2_tumu(__VA_ARGS__) -#define vwmul_vv_i64m4_m(...) __riscv_vwmul_vv_i64m4_tumu(__VA_ARGS__) -#define vwmul_vx_i64m4_m(...) __riscv_vwmul_vx_i64m4_tumu(__VA_ARGS__) -#define vwmul_vv_i64m8_m(...) __riscv_vwmul_vv_i64m8_tumu(__VA_ARGS__) -#define vwmul_vx_i64m8_m(...) __riscv_vwmul_vx_i64m8_tumu(__VA_ARGS__) -#define vwmulsu_vv_i16mf4_m(...) __riscv_vwmulsu_vv_i16mf4_tumu(__VA_ARGS__) -#define vwmulsu_vx_i16mf4_m(...) __riscv_vwmulsu_vx_i16mf4_tumu(__VA_ARGS__) -#define vwmulsu_vv_i16mf2_m(...) __riscv_vwmulsu_vv_i16mf2_tumu(__VA_ARGS__) -#define vwmulsu_vx_i16mf2_m(...) __riscv_vwmulsu_vx_i16mf2_tumu(__VA_ARGS__) -#define vwmulsu_vv_i16m1_m(...) __riscv_vwmulsu_vv_i16m1_tumu(__VA_ARGS__) -#define vwmulsu_vx_i16m1_m(...) __riscv_vwmulsu_vx_i16m1_tumu(__VA_ARGS__) -#define vwmulsu_vv_i16m2_m(...) __riscv_vwmulsu_vv_i16m2_tumu(__VA_ARGS__) -#define vwmulsu_vx_i16m2_m(...) __riscv_vwmulsu_vx_i16m2_tumu(__VA_ARGS__) -#define vwmulsu_vv_i16m4_m(...) __riscv_vwmulsu_vv_i16m4_tumu(__VA_ARGS__) -#define vwmulsu_vx_i16m4_m(...) __riscv_vwmulsu_vx_i16m4_tumu(__VA_ARGS__) -#define vwmulsu_vv_i16m8_m(...) __riscv_vwmulsu_vv_i16m8_tumu(__VA_ARGS__) -#define vwmulsu_vx_i16m8_m(...) __riscv_vwmulsu_vx_i16m8_tumu(__VA_ARGS__) -#define vwmulsu_vv_i32mf2_m(...) __riscv_vwmulsu_vv_i32mf2_tumu(__VA_ARGS__) -#define vwmulsu_vx_i32mf2_m(...) __riscv_vwmulsu_vx_i32mf2_tumu(__VA_ARGS__) -#define vwmulsu_vv_i32m1_m(...) __riscv_vwmulsu_vv_i32m1_tumu(__VA_ARGS__) -#define vwmulsu_vx_i32m1_m(...) __riscv_vwmulsu_vx_i32m1_tumu(__VA_ARGS__) -#define vwmulsu_vv_i32m2_m(...) __riscv_vwmulsu_vv_i32m2_tumu(__VA_ARGS__) -#define vwmulsu_vx_i32m2_m(...) __riscv_vwmulsu_vx_i32m2_tumu(__VA_ARGS__) -#define vwmulsu_vv_i32m4_m(...) __riscv_vwmulsu_vv_i32m4_tumu(__VA_ARGS__) -#define vwmulsu_vx_i32m4_m(...) __riscv_vwmulsu_vx_i32m4_tumu(__VA_ARGS__) -#define vwmulsu_vv_i32m8_m(...) __riscv_vwmulsu_vv_i32m8_tumu(__VA_ARGS__) -#define vwmulsu_vx_i32m8_m(...) __riscv_vwmulsu_vx_i32m8_tumu(__VA_ARGS__) -#define vwmulsu_vv_i64m1_m(...) __riscv_vwmulsu_vv_i64m1_tumu(__VA_ARGS__) -#define vwmulsu_vx_i64m1_m(...) __riscv_vwmulsu_vx_i64m1_tumu(__VA_ARGS__) -#define vwmulsu_vv_i64m2_m(...) __riscv_vwmulsu_vv_i64m2_tumu(__VA_ARGS__) -#define vwmulsu_vx_i64m2_m(...) __riscv_vwmulsu_vx_i64m2_tumu(__VA_ARGS__) -#define vwmulsu_vv_i64m4_m(...) __riscv_vwmulsu_vv_i64m4_tumu(__VA_ARGS__) -#define vwmulsu_vx_i64m4_m(...) __riscv_vwmulsu_vx_i64m4_tumu(__VA_ARGS__) -#define vwmulsu_vv_i64m8_m(...) __riscv_vwmulsu_vv_i64m8_tumu(__VA_ARGS__) -#define vwmulsu_vx_i64m8_m(...) __riscv_vwmulsu_vx_i64m8_tumu(__VA_ARGS__) -#define vwmulu_vv_u16mf4_m(...) __riscv_vwmulu_vv_u16mf4_tumu(__VA_ARGS__) -#define vwmulu_vx_u16mf4_m(...) __riscv_vwmulu_vx_u16mf4_tumu(__VA_ARGS__) -#define vwmulu_vv_u16mf2_m(...) __riscv_vwmulu_vv_u16mf2_tumu(__VA_ARGS__) -#define vwmulu_vx_u16mf2_m(...) __riscv_vwmulu_vx_u16mf2_tumu(__VA_ARGS__) -#define vwmulu_vv_u16m1_m(...) __riscv_vwmulu_vv_u16m1_tumu(__VA_ARGS__) -#define vwmulu_vx_u16m1_m(...) __riscv_vwmulu_vx_u16m1_tumu(__VA_ARGS__) -#define vwmulu_vv_u16m2_m(...) __riscv_vwmulu_vv_u16m2_tumu(__VA_ARGS__) -#define vwmulu_vx_u16m2_m(...) __riscv_vwmulu_vx_u16m2_tumu(__VA_ARGS__) -#define vwmulu_vv_u16m4_m(...) __riscv_vwmulu_vv_u16m4_tumu(__VA_ARGS__) -#define vwmulu_vx_u16m4_m(...) __riscv_vwmulu_vx_u16m4_tumu(__VA_ARGS__) -#define vwmulu_vv_u16m8_m(...) __riscv_vwmulu_vv_u16m8_tumu(__VA_ARGS__) -#define vwmulu_vx_u16m8_m(...) __riscv_vwmulu_vx_u16m8_tumu(__VA_ARGS__) -#define vwmulu_vv_u32mf2_m(...) __riscv_vwmulu_vv_u32mf2_tumu(__VA_ARGS__) -#define vwmulu_vx_u32mf2_m(...) __riscv_vwmulu_vx_u32mf2_tumu(__VA_ARGS__) -#define vwmulu_vv_u32m1_m(...) __riscv_vwmulu_vv_u32m1_tumu(__VA_ARGS__) -#define vwmulu_vx_u32m1_m(...) __riscv_vwmulu_vx_u32m1_tumu(__VA_ARGS__) -#define vwmulu_vv_u32m2_m(...) __riscv_vwmulu_vv_u32m2_tumu(__VA_ARGS__) -#define vwmulu_vx_u32m2_m(...) __riscv_vwmulu_vx_u32m2_tumu(__VA_ARGS__) -#define vwmulu_vv_u32m4_m(...) __riscv_vwmulu_vv_u32m4_tumu(__VA_ARGS__) -#define vwmulu_vx_u32m4_m(...) __riscv_vwmulu_vx_u32m4_tumu(__VA_ARGS__) -#define vwmulu_vv_u32m8_m(...) __riscv_vwmulu_vv_u32m8_tumu(__VA_ARGS__) -#define vwmulu_vx_u32m8_m(...) __riscv_vwmulu_vx_u32m8_tumu(__VA_ARGS__) -#define vwmulu_vv_u64m1_m(...) __riscv_vwmulu_vv_u64m1_tumu(__VA_ARGS__) -#define vwmulu_vx_u64m1_m(...) __riscv_vwmulu_vx_u64m1_tumu(__VA_ARGS__) -#define vwmulu_vv_u64m2_m(...) __riscv_vwmulu_vv_u64m2_tumu(__VA_ARGS__) -#define vwmulu_vx_u64m2_m(...) __riscv_vwmulu_vx_u64m2_tumu(__VA_ARGS__) -#define vwmulu_vv_u64m4_m(...) __riscv_vwmulu_vv_u64m4_tumu(__VA_ARGS__) -#define vwmulu_vx_u64m4_m(...) __riscv_vwmulu_vx_u64m4_tumu(__VA_ARGS__) -#define vwmulu_vv_u64m8_m(...) __riscv_vwmulu_vv_u64m8_tumu(__VA_ARGS__) -#define vwmulu_vx_u64m8_m(...) __riscv_vwmulu_vx_u64m8_tumu(__VA_ARGS__) -#define vmacc_vv_i8mf8(...) __riscv_vmacc_vv_i8mf8_tu(__VA_ARGS__) -#define vmacc_vx_i8mf8(...) __riscv_vmacc_vx_i8mf8_tu(__VA_ARGS__) -#define vmacc_vv_i8mf4(...) __riscv_vmacc_vv_i8mf4_tu(__VA_ARGS__) -#define vmacc_vx_i8mf4(...) __riscv_vmacc_vx_i8mf4_tu(__VA_ARGS__) -#define vmacc_vv_i8mf2(...) __riscv_vmacc_vv_i8mf2_tu(__VA_ARGS__) -#define vmacc_vx_i8mf2(...) __riscv_vmacc_vx_i8mf2_tu(__VA_ARGS__) -#define vmacc_vv_i8m1(...) __riscv_vmacc_vv_i8m1_tu(__VA_ARGS__) -#define vmacc_vx_i8m1(...) __riscv_vmacc_vx_i8m1_tu(__VA_ARGS__) -#define vmacc_vv_i8m2(...) __riscv_vmacc_vv_i8m2_tu(__VA_ARGS__) -#define vmacc_vx_i8m2(...) __riscv_vmacc_vx_i8m2_tu(__VA_ARGS__) -#define vmacc_vv_i8m4(...) __riscv_vmacc_vv_i8m4_tu(__VA_ARGS__) -#define vmacc_vx_i8m4(...) __riscv_vmacc_vx_i8m4_tu(__VA_ARGS__) -#define vmacc_vv_i8m8(...) __riscv_vmacc_vv_i8m8_tu(__VA_ARGS__) -#define vmacc_vx_i8m8(...) __riscv_vmacc_vx_i8m8_tu(__VA_ARGS__) -#define vmacc_vv_i16mf4(...) __riscv_vmacc_vv_i16mf4_tu(__VA_ARGS__) -#define vmacc_vx_i16mf4(...) __riscv_vmacc_vx_i16mf4_tu(__VA_ARGS__) -#define vmacc_vv_i16mf2(...) __riscv_vmacc_vv_i16mf2_tu(__VA_ARGS__) -#define vmacc_vx_i16mf2(...) __riscv_vmacc_vx_i16mf2_tu(__VA_ARGS__) -#define vmacc_vv_i16m1(...) __riscv_vmacc_vv_i16m1_tu(__VA_ARGS__) -#define vmacc_vx_i16m1(...) __riscv_vmacc_vx_i16m1_tu(__VA_ARGS__) -#define vmacc_vv_i16m2(...) __riscv_vmacc_vv_i16m2_tu(__VA_ARGS__) -#define vmacc_vx_i16m2(...) __riscv_vmacc_vx_i16m2_tu(__VA_ARGS__) -#define vmacc_vv_i16m4(...) __riscv_vmacc_vv_i16m4_tu(__VA_ARGS__) -#define vmacc_vx_i16m4(...) __riscv_vmacc_vx_i16m4_tu(__VA_ARGS__) -#define vmacc_vv_i16m8(...) __riscv_vmacc_vv_i16m8_tu(__VA_ARGS__) -#define vmacc_vx_i16m8(...) __riscv_vmacc_vx_i16m8_tu(__VA_ARGS__) -#define vmacc_vv_i32mf2(...) __riscv_vmacc_vv_i32mf2_tu(__VA_ARGS__) -#define vmacc_vx_i32mf2(...) __riscv_vmacc_vx_i32mf2_tu(__VA_ARGS__) -#define vmacc_vv_i32m1(...) __riscv_vmacc_vv_i32m1_tu(__VA_ARGS__) -#define vmacc_vx_i32m1(...) __riscv_vmacc_vx_i32m1_tu(__VA_ARGS__) -#define vmacc_vv_i32m2(...) __riscv_vmacc_vv_i32m2_tu(__VA_ARGS__) -#define vmacc_vx_i32m2(...) __riscv_vmacc_vx_i32m2_tu(__VA_ARGS__) -#define vmacc_vv_i32m4(...) __riscv_vmacc_vv_i32m4_tu(__VA_ARGS__) -#define vmacc_vx_i32m4(...) __riscv_vmacc_vx_i32m4_tu(__VA_ARGS__) -#define vmacc_vv_i32m8(...) __riscv_vmacc_vv_i32m8_tu(__VA_ARGS__) -#define vmacc_vx_i32m8(...) __riscv_vmacc_vx_i32m8_tu(__VA_ARGS__) -#define vmacc_vv_i64m1(...) __riscv_vmacc_vv_i64m1_tu(__VA_ARGS__) -#define vmacc_vx_i64m1(...) __riscv_vmacc_vx_i64m1_tu(__VA_ARGS__) -#define vmacc_vv_i64m2(...) __riscv_vmacc_vv_i64m2_tu(__VA_ARGS__) -#define vmacc_vx_i64m2(...) __riscv_vmacc_vx_i64m2_tu(__VA_ARGS__) -#define vmacc_vv_i64m4(...) __riscv_vmacc_vv_i64m4_tu(__VA_ARGS__) -#define vmacc_vx_i64m4(...) __riscv_vmacc_vx_i64m4_tu(__VA_ARGS__) -#define vmacc_vv_i64m8(...) __riscv_vmacc_vv_i64m8_tu(__VA_ARGS__) -#define vmacc_vx_i64m8(...) __riscv_vmacc_vx_i64m8_tu(__VA_ARGS__) -#define vnmsac_vv_i8mf8(...) __riscv_vnmsac_vv_i8mf8_tu(__VA_ARGS__) -#define vnmsac_vx_i8mf8(...) __riscv_vnmsac_vx_i8mf8_tu(__VA_ARGS__) -#define vnmsac_vv_i8mf4(...) __riscv_vnmsac_vv_i8mf4_tu(__VA_ARGS__) -#define vnmsac_vx_i8mf4(...) __riscv_vnmsac_vx_i8mf4_tu(__VA_ARGS__) -#define vnmsac_vv_i8mf2(...) __riscv_vnmsac_vv_i8mf2_tu(__VA_ARGS__) -#define vnmsac_vx_i8mf2(...) __riscv_vnmsac_vx_i8mf2_tu(__VA_ARGS__) -#define vnmsac_vv_i8m1(...) __riscv_vnmsac_vv_i8m1_tu(__VA_ARGS__) -#define vnmsac_vx_i8m1(...) __riscv_vnmsac_vx_i8m1_tu(__VA_ARGS__) -#define vnmsac_vv_i8m2(...) __riscv_vnmsac_vv_i8m2_tu(__VA_ARGS__) -#define vnmsac_vx_i8m2(...) __riscv_vnmsac_vx_i8m2_tu(__VA_ARGS__) -#define vnmsac_vv_i8m4(...) __riscv_vnmsac_vv_i8m4_tu(__VA_ARGS__) -#define vnmsac_vx_i8m4(...) __riscv_vnmsac_vx_i8m4_tu(__VA_ARGS__) -#define vnmsac_vv_i8m8(...) __riscv_vnmsac_vv_i8m8_tu(__VA_ARGS__) -#define vnmsac_vx_i8m8(...) __riscv_vnmsac_vx_i8m8_tu(__VA_ARGS__) -#define vnmsac_vv_i16mf4(...) __riscv_vnmsac_vv_i16mf4_tu(__VA_ARGS__) -#define vnmsac_vx_i16mf4(...) __riscv_vnmsac_vx_i16mf4_tu(__VA_ARGS__) -#define vnmsac_vv_i16mf2(...) __riscv_vnmsac_vv_i16mf2_tu(__VA_ARGS__) -#define vnmsac_vx_i16mf2(...) __riscv_vnmsac_vx_i16mf2_tu(__VA_ARGS__) -#define vnmsac_vv_i16m1(...) __riscv_vnmsac_vv_i16m1_tu(__VA_ARGS__) -#define vnmsac_vx_i16m1(...) __riscv_vnmsac_vx_i16m1_tu(__VA_ARGS__) -#define vnmsac_vv_i16m2(...) __riscv_vnmsac_vv_i16m2_tu(__VA_ARGS__) -#define vnmsac_vx_i16m2(...) __riscv_vnmsac_vx_i16m2_tu(__VA_ARGS__) -#define vnmsac_vv_i16m4(...) __riscv_vnmsac_vv_i16m4_tu(__VA_ARGS__) -#define vnmsac_vx_i16m4(...) __riscv_vnmsac_vx_i16m4_tu(__VA_ARGS__) -#define vnmsac_vv_i16m8(...) __riscv_vnmsac_vv_i16m8_tu(__VA_ARGS__) -#define vnmsac_vx_i16m8(...) __riscv_vnmsac_vx_i16m8_tu(__VA_ARGS__) -#define vnmsac_vv_i32mf2(...) __riscv_vnmsac_vv_i32mf2_tu(__VA_ARGS__) -#define vnmsac_vx_i32mf2(...) __riscv_vnmsac_vx_i32mf2_tu(__VA_ARGS__) -#define vnmsac_vv_i32m1(...) __riscv_vnmsac_vv_i32m1_tu(__VA_ARGS__) -#define vnmsac_vx_i32m1(...) __riscv_vnmsac_vx_i32m1_tu(__VA_ARGS__) -#define vnmsac_vv_i32m2(...) __riscv_vnmsac_vv_i32m2_tu(__VA_ARGS__) -#define vnmsac_vx_i32m2(...) __riscv_vnmsac_vx_i32m2_tu(__VA_ARGS__) -#define vnmsac_vv_i32m4(...) __riscv_vnmsac_vv_i32m4_tu(__VA_ARGS__) -#define vnmsac_vx_i32m4(...) __riscv_vnmsac_vx_i32m4_tu(__VA_ARGS__) -#define vnmsac_vv_i32m8(...) __riscv_vnmsac_vv_i32m8_tu(__VA_ARGS__) -#define vnmsac_vx_i32m8(...) __riscv_vnmsac_vx_i32m8_tu(__VA_ARGS__) -#define vnmsac_vv_i64m1(...) __riscv_vnmsac_vv_i64m1_tu(__VA_ARGS__) -#define vnmsac_vx_i64m1(...) __riscv_vnmsac_vx_i64m1_tu(__VA_ARGS__) -#define vnmsac_vv_i64m2(...) __riscv_vnmsac_vv_i64m2_tu(__VA_ARGS__) -#define vnmsac_vx_i64m2(...) __riscv_vnmsac_vx_i64m2_tu(__VA_ARGS__) -#define vnmsac_vv_i64m4(...) __riscv_vnmsac_vv_i64m4_tu(__VA_ARGS__) -#define vnmsac_vx_i64m4(...) __riscv_vnmsac_vx_i64m4_tu(__VA_ARGS__) -#define vnmsac_vv_i64m8(...) __riscv_vnmsac_vv_i64m8_tu(__VA_ARGS__) -#define vnmsac_vx_i64m8(...) __riscv_vnmsac_vx_i64m8_tu(__VA_ARGS__) -#define vmadd_vv_i8mf8(...) __riscv_vmadd_vv_i8mf8_tu(__VA_ARGS__) -#define vmadd_vx_i8mf8(...) __riscv_vmadd_vx_i8mf8_tu(__VA_ARGS__) -#define vmadd_vv_i8mf4(...) __riscv_vmadd_vv_i8mf4_tu(__VA_ARGS__) -#define vmadd_vx_i8mf4(...) __riscv_vmadd_vx_i8mf4_tu(__VA_ARGS__) -#define vmadd_vv_i8mf2(...) __riscv_vmadd_vv_i8mf2_tu(__VA_ARGS__) -#define vmadd_vx_i8mf2(...) __riscv_vmadd_vx_i8mf2_tu(__VA_ARGS__) -#define vmadd_vv_i8m1(...) __riscv_vmadd_vv_i8m1_tu(__VA_ARGS__) -#define vmadd_vx_i8m1(...) __riscv_vmadd_vx_i8m1_tu(__VA_ARGS__) -#define vmadd_vv_i8m2(...) __riscv_vmadd_vv_i8m2_tu(__VA_ARGS__) -#define vmadd_vx_i8m2(...) __riscv_vmadd_vx_i8m2_tu(__VA_ARGS__) -#define vmadd_vv_i8m4(...) __riscv_vmadd_vv_i8m4_tu(__VA_ARGS__) -#define vmadd_vx_i8m4(...) __riscv_vmadd_vx_i8m4_tu(__VA_ARGS__) -#define vmadd_vv_i8m8(...) __riscv_vmadd_vv_i8m8_tu(__VA_ARGS__) -#define vmadd_vx_i8m8(...) __riscv_vmadd_vx_i8m8_tu(__VA_ARGS__) -#define vmadd_vv_i16mf4(...) __riscv_vmadd_vv_i16mf4_tu(__VA_ARGS__) -#define vmadd_vx_i16mf4(...) __riscv_vmadd_vx_i16mf4_tu(__VA_ARGS__) -#define vmadd_vv_i16mf2(...) __riscv_vmadd_vv_i16mf2_tu(__VA_ARGS__) -#define vmadd_vx_i16mf2(...) __riscv_vmadd_vx_i16mf2_tu(__VA_ARGS__) -#define vmadd_vv_i16m1(...) __riscv_vmadd_vv_i16m1_tu(__VA_ARGS__) -#define vmadd_vx_i16m1(...) __riscv_vmadd_vx_i16m1_tu(__VA_ARGS__) -#define vmadd_vv_i16m2(...) __riscv_vmadd_vv_i16m2_tu(__VA_ARGS__) -#define vmadd_vx_i16m2(...) __riscv_vmadd_vx_i16m2_tu(__VA_ARGS__) -#define vmadd_vv_i16m4(...) __riscv_vmadd_vv_i16m4_tu(__VA_ARGS__) -#define vmadd_vx_i16m4(...) __riscv_vmadd_vx_i16m4_tu(__VA_ARGS__) -#define vmadd_vv_i16m8(...) __riscv_vmadd_vv_i16m8_tu(__VA_ARGS__) -#define vmadd_vx_i16m8(...) __riscv_vmadd_vx_i16m8_tu(__VA_ARGS__) -#define vmadd_vv_i32mf2(...) __riscv_vmadd_vv_i32mf2_tu(__VA_ARGS__) -#define vmadd_vx_i32mf2(...) __riscv_vmadd_vx_i32mf2_tu(__VA_ARGS__) -#define vmadd_vv_i32m1(...) __riscv_vmadd_vv_i32m1_tu(__VA_ARGS__) -#define vmadd_vx_i32m1(...) __riscv_vmadd_vx_i32m1_tu(__VA_ARGS__) -#define vmadd_vv_i32m2(...) __riscv_vmadd_vv_i32m2_tu(__VA_ARGS__) -#define vmadd_vx_i32m2(...) __riscv_vmadd_vx_i32m2_tu(__VA_ARGS__) -#define vmadd_vv_i32m4(...) __riscv_vmadd_vv_i32m4_tu(__VA_ARGS__) -#define vmadd_vx_i32m4(...) __riscv_vmadd_vx_i32m4_tu(__VA_ARGS__) -#define vmadd_vv_i32m8(...) __riscv_vmadd_vv_i32m8_tu(__VA_ARGS__) -#define vmadd_vx_i32m8(...) __riscv_vmadd_vx_i32m8_tu(__VA_ARGS__) -#define vmadd_vv_i64m1(...) __riscv_vmadd_vv_i64m1_tu(__VA_ARGS__) -#define vmadd_vx_i64m1(...) __riscv_vmadd_vx_i64m1_tu(__VA_ARGS__) -#define vmadd_vv_i64m2(...) __riscv_vmadd_vv_i64m2_tu(__VA_ARGS__) -#define vmadd_vx_i64m2(...) __riscv_vmadd_vx_i64m2_tu(__VA_ARGS__) -#define vmadd_vv_i64m4(...) __riscv_vmadd_vv_i64m4_tu(__VA_ARGS__) -#define vmadd_vx_i64m4(...) __riscv_vmadd_vx_i64m4_tu(__VA_ARGS__) -#define vmadd_vv_i64m8(...) __riscv_vmadd_vv_i64m8_tu(__VA_ARGS__) -#define vmadd_vx_i64m8(...) __riscv_vmadd_vx_i64m8_tu(__VA_ARGS__) -#define vnmsub_vv_i8mf8(...) __riscv_vnmsub_vv_i8mf8_tu(__VA_ARGS__) -#define vnmsub_vx_i8mf8(...) __riscv_vnmsub_vx_i8mf8_tu(__VA_ARGS__) -#define vnmsub_vv_i8mf4(...) __riscv_vnmsub_vv_i8mf4_tu(__VA_ARGS__) -#define vnmsub_vx_i8mf4(...) __riscv_vnmsub_vx_i8mf4_tu(__VA_ARGS__) -#define vnmsub_vv_i8mf2(...) __riscv_vnmsub_vv_i8mf2_tu(__VA_ARGS__) -#define vnmsub_vx_i8mf2(...) __riscv_vnmsub_vx_i8mf2_tu(__VA_ARGS__) -#define vnmsub_vv_i8m1(...) __riscv_vnmsub_vv_i8m1_tu(__VA_ARGS__) -#define vnmsub_vx_i8m1(...) __riscv_vnmsub_vx_i8m1_tu(__VA_ARGS__) -#define vnmsub_vv_i8m2(...) __riscv_vnmsub_vv_i8m2_tu(__VA_ARGS__) -#define vnmsub_vx_i8m2(...) __riscv_vnmsub_vx_i8m2_tu(__VA_ARGS__) -#define vnmsub_vv_i8m4(...) __riscv_vnmsub_vv_i8m4_tu(__VA_ARGS__) -#define vnmsub_vx_i8m4(...) __riscv_vnmsub_vx_i8m4_tu(__VA_ARGS__) -#define vnmsub_vv_i8m8(...) __riscv_vnmsub_vv_i8m8_tu(__VA_ARGS__) -#define vnmsub_vx_i8m8(...) __riscv_vnmsub_vx_i8m8_tu(__VA_ARGS__) -#define vnmsub_vv_i16mf4(...) __riscv_vnmsub_vv_i16mf4_tu(__VA_ARGS__) -#define vnmsub_vx_i16mf4(...) __riscv_vnmsub_vx_i16mf4_tu(__VA_ARGS__) -#define vnmsub_vv_i16mf2(...) __riscv_vnmsub_vv_i16mf2_tu(__VA_ARGS__) -#define vnmsub_vx_i16mf2(...) __riscv_vnmsub_vx_i16mf2_tu(__VA_ARGS__) -#define vnmsub_vv_i16m1(...) __riscv_vnmsub_vv_i16m1_tu(__VA_ARGS__) -#define vnmsub_vx_i16m1(...) __riscv_vnmsub_vx_i16m1_tu(__VA_ARGS__) -#define vnmsub_vv_i16m2(...) __riscv_vnmsub_vv_i16m2_tu(__VA_ARGS__) -#define vnmsub_vx_i16m2(...) __riscv_vnmsub_vx_i16m2_tu(__VA_ARGS__) -#define vnmsub_vv_i16m4(...) __riscv_vnmsub_vv_i16m4_tu(__VA_ARGS__) -#define vnmsub_vx_i16m4(...) __riscv_vnmsub_vx_i16m4_tu(__VA_ARGS__) -#define vnmsub_vv_i16m8(...) __riscv_vnmsub_vv_i16m8_tu(__VA_ARGS__) -#define vnmsub_vx_i16m8(...) __riscv_vnmsub_vx_i16m8_tu(__VA_ARGS__) -#define vnmsub_vv_i32mf2(...) __riscv_vnmsub_vv_i32mf2_tu(__VA_ARGS__) -#define vnmsub_vx_i32mf2(...) __riscv_vnmsub_vx_i32mf2_tu(__VA_ARGS__) -#define vnmsub_vv_i32m1(...) __riscv_vnmsub_vv_i32m1_tu(__VA_ARGS__) -#define vnmsub_vx_i32m1(...) __riscv_vnmsub_vx_i32m1_tu(__VA_ARGS__) -#define vnmsub_vv_i32m2(...) __riscv_vnmsub_vv_i32m2_tu(__VA_ARGS__) -#define vnmsub_vx_i32m2(...) __riscv_vnmsub_vx_i32m2_tu(__VA_ARGS__) -#define vnmsub_vv_i32m4(...) __riscv_vnmsub_vv_i32m4_tu(__VA_ARGS__) -#define vnmsub_vx_i32m4(...) __riscv_vnmsub_vx_i32m4_tu(__VA_ARGS__) -#define vnmsub_vv_i32m8(...) __riscv_vnmsub_vv_i32m8_tu(__VA_ARGS__) -#define vnmsub_vx_i32m8(...) __riscv_vnmsub_vx_i32m8_tu(__VA_ARGS__) -#define vnmsub_vv_i64m1(...) __riscv_vnmsub_vv_i64m1_tu(__VA_ARGS__) -#define vnmsub_vx_i64m1(...) __riscv_vnmsub_vx_i64m1_tu(__VA_ARGS__) -#define vnmsub_vv_i64m2(...) __riscv_vnmsub_vv_i64m2_tu(__VA_ARGS__) -#define vnmsub_vx_i64m2(...) __riscv_vnmsub_vx_i64m2_tu(__VA_ARGS__) -#define vnmsub_vv_i64m4(...) __riscv_vnmsub_vv_i64m4_tu(__VA_ARGS__) -#define vnmsub_vx_i64m4(...) __riscv_vnmsub_vx_i64m4_tu(__VA_ARGS__) -#define vnmsub_vv_i64m8(...) __riscv_vnmsub_vv_i64m8_tu(__VA_ARGS__) -#define vnmsub_vx_i64m8(...) __riscv_vnmsub_vx_i64m8_tu(__VA_ARGS__) -#define vmacc_vv_u8mf8(...) __riscv_vmacc_vv_u8mf8_tu(__VA_ARGS__) -#define vmacc_vx_u8mf8(...) __riscv_vmacc_vx_u8mf8_tu(__VA_ARGS__) -#define vmacc_vv_u8mf4(...) __riscv_vmacc_vv_u8mf4_tu(__VA_ARGS__) -#define vmacc_vx_u8mf4(...) __riscv_vmacc_vx_u8mf4_tu(__VA_ARGS__) -#define vmacc_vv_u8mf2(...) __riscv_vmacc_vv_u8mf2_tu(__VA_ARGS__) -#define vmacc_vx_u8mf2(...) __riscv_vmacc_vx_u8mf2_tu(__VA_ARGS__) -#define vmacc_vv_u8m1(...) __riscv_vmacc_vv_u8m1_tu(__VA_ARGS__) -#define vmacc_vx_u8m1(...) __riscv_vmacc_vx_u8m1_tu(__VA_ARGS__) -#define vmacc_vv_u8m2(...) __riscv_vmacc_vv_u8m2_tu(__VA_ARGS__) -#define vmacc_vx_u8m2(...) __riscv_vmacc_vx_u8m2_tu(__VA_ARGS__) -#define vmacc_vv_u8m4(...) __riscv_vmacc_vv_u8m4_tu(__VA_ARGS__) -#define vmacc_vx_u8m4(...) __riscv_vmacc_vx_u8m4_tu(__VA_ARGS__) -#define vmacc_vv_u8m8(...) __riscv_vmacc_vv_u8m8_tu(__VA_ARGS__) -#define vmacc_vx_u8m8(...) __riscv_vmacc_vx_u8m8_tu(__VA_ARGS__) -#define vmacc_vv_u16mf4(...) __riscv_vmacc_vv_u16mf4_tu(__VA_ARGS__) -#define vmacc_vx_u16mf4(...) __riscv_vmacc_vx_u16mf4_tu(__VA_ARGS__) -#define vmacc_vv_u16mf2(...) __riscv_vmacc_vv_u16mf2_tu(__VA_ARGS__) -#define vmacc_vx_u16mf2(...) __riscv_vmacc_vx_u16mf2_tu(__VA_ARGS__) -#define vmacc_vv_u16m1(...) __riscv_vmacc_vv_u16m1_tu(__VA_ARGS__) -#define vmacc_vx_u16m1(...) __riscv_vmacc_vx_u16m1_tu(__VA_ARGS__) -#define vmacc_vv_u16m2(...) __riscv_vmacc_vv_u16m2_tu(__VA_ARGS__) -#define vmacc_vx_u16m2(...) __riscv_vmacc_vx_u16m2_tu(__VA_ARGS__) -#define vmacc_vv_u16m4(...) __riscv_vmacc_vv_u16m4_tu(__VA_ARGS__) -#define vmacc_vx_u16m4(...) __riscv_vmacc_vx_u16m4_tu(__VA_ARGS__) -#define vmacc_vv_u16m8(...) __riscv_vmacc_vv_u16m8_tu(__VA_ARGS__) -#define vmacc_vx_u16m8(...) __riscv_vmacc_vx_u16m8_tu(__VA_ARGS__) -#define vmacc_vv_u32mf2(...) __riscv_vmacc_vv_u32mf2_tu(__VA_ARGS__) -#define vmacc_vx_u32mf2(...) __riscv_vmacc_vx_u32mf2_tu(__VA_ARGS__) -#define vmacc_vv_u32m1(...) __riscv_vmacc_vv_u32m1_tu(__VA_ARGS__) -#define vmacc_vx_u32m1(...) __riscv_vmacc_vx_u32m1_tu(__VA_ARGS__) -#define vmacc_vv_u32m2(...) __riscv_vmacc_vv_u32m2_tu(__VA_ARGS__) -#define vmacc_vx_u32m2(...) __riscv_vmacc_vx_u32m2_tu(__VA_ARGS__) -#define vmacc_vv_u32m4(...) __riscv_vmacc_vv_u32m4_tu(__VA_ARGS__) -#define vmacc_vx_u32m4(...) __riscv_vmacc_vx_u32m4_tu(__VA_ARGS__) -#define vmacc_vv_u32m8(...) __riscv_vmacc_vv_u32m8_tu(__VA_ARGS__) -#define vmacc_vx_u32m8(...) __riscv_vmacc_vx_u32m8_tu(__VA_ARGS__) -#define vmacc_vv_u64m1(...) __riscv_vmacc_vv_u64m1_tu(__VA_ARGS__) -#define vmacc_vx_u64m1(...) __riscv_vmacc_vx_u64m1_tu(__VA_ARGS__) -#define vmacc_vv_u64m2(...) __riscv_vmacc_vv_u64m2_tu(__VA_ARGS__) -#define vmacc_vx_u64m2(...) __riscv_vmacc_vx_u64m2_tu(__VA_ARGS__) -#define vmacc_vv_u64m4(...) __riscv_vmacc_vv_u64m4_tu(__VA_ARGS__) -#define vmacc_vx_u64m4(...) __riscv_vmacc_vx_u64m4_tu(__VA_ARGS__) -#define vmacc_vv_u64m8(...) __riscv_vmacc_vv_u64m8_tu(__VA_ARGS__) -#define vmacc_vx_u64m8(...) __riscv_vmacc_vx_u64m8_tu(__VA_ARGS__) -#define vnmsac_vv_u8mf8(...) __riscv_vnmsac_vv_u8mf8_tu(__VA_ARGS__) -#define vnmsac_vx_u8mf8(...) __riscv_vnmsac_vx_u8mf8_tu(__VA_ARGS__) -#define vnmsac_vv_u8mf4(...) __riscv_vnmsac_vv_u8mf4_tu(__VA_ARGS__) -#define vnmsac_vx_u8mf4(...) __riscv_vnmsac_vx_u8mf4_tu(__VA_ARGS__) -#define vnmsac_vv_u8mf2(...) __riscv_vnmsac_vv_u8mf2_tu(__VA_ARGS__) -#define vnmsac_vx_u8mf2(...) __riscv_vnmsac_vx_u8mf2_tu(__VA_ARGS__) -#define vnmsac_vv_u8m1(...) __riscv_vnmsac_vv_u8m1_tu(__VA_ARGS__) -#define vnmsac_vx_u8m1(...) __riscv_vnmsac_vx_u8m1_tu(__VA_ARGS__) -#define vnmsac_vv_u8m2(...) __riscv_vnmsac_vv_u8m2_tu(__VA_ARGS__) -#define vnmsac_vx_u8m2(...) __riscv_vnmsac_vx_u8m2_tu(__VA_ARGS__) -#define vnmsac_vv_u8m4(...) __riscv_vnmsac_vv_u8m4_tu(__VA_ARGS__) -#define vnmsac_vx_u8m4(...) __riscv_vnmsac_vx_u8m4_tu(__VA_ARGS__) -#define vnmsac_vv_u8m8(...) __riscv_vnmsac_vv_u8m8_tu(__VA_ARGS__) -#define vnmsac_vx_u8m8(...) __riscv_vnmsac_vx_u8m8_tu(__VA_ARGS__) -#define vnmsac_vv_u16mf4(...) __riscv_vnmsac_vv_u16mf4_tu(__VA_ARGS__) -#define vnmsac_vx_u16mf4(...) __riscv_vnmsac_vx_u16mf4_tu(__VA_ARGS__) -#define vnmsac_vv_u16mf2(...) __riscv_vnmsac_vv_u16mf2_tu(__VA_ARGS__) -#define vnmsac_vx_u16mf2(...) __riscv_vnmsac_vx_u16mf2_tu(__VA_ARGS__) -#define vnmsac_vv_u16m1(...) __riscv_vnmsac_vv_u16m1_tu(__VA_ARGS__) -#define vnmsac_vx_u16m1(...) __riscv_vnmsac_vx_u16m1_tu(__VA_ARGS__) -#define vnmsac_vv_u16m2(...) __riscv_vnmsac_vv_u16m2_tu(__VA_ARGS__) -#define vnmsac_vx_u16m2(...) __riscv_vnmsac_vx_u16m2_tu(__VA_ARGS__) -#define vnmsac_vv_u16m4(...) __riscv_vnmsac_vv_u16m4_tu(__VA_ARGS__) -#define vnmsac_vx_u16m4(...) __riscv_vnmsac_vx_u16m4_tu(__VA_ARGS__) -#define vnmsac_vv_u16m8(...) __riscv_vnmsac_vv_u16m8_tu(__VA_ARGS__) -#define vnmsac_vx_u16m8(...) __riscv_vnmsac_vx_u16m8_tu(__VA_ARGS__) -#define vnmsac_vv_u32mf2(...) __riscv_vnmsac_vv_u32mf2_tu(__VA_ARGS__) -#define vnmsac_vx_u32mf2(...) __riscv_vnmsac_vx_u32mf2_tu(__VA_ARGS__) -#define vnmsac_vv_u32m1(...) __riscv_vnmsac_vv_u32m1_tu(__VA_ARGS__) -#define vnmsac_vx_u32m1(...) __riscv_vnmsac_vx_u32m1_tu(__VA_ARGS__) -#define vnmsac_vv_u32m2(...) __riscv_vnmsac_vv_u32m2_tu(__VA_ARGS__) -#define vnmsac_vx_u32m2(...) __riscv_vnmsac_vx_u32m2_tu(__VA_ARGS__) -#define vnmsac_vv_u32m4(...) __riscv_vnmsac_vv_u32m4_tu(__VA_ARGS__) -#define vnmsac_vx_u32m4(...) __riscv_vnmsac_vx_u32m4_tu(__VA_ARGS__) -#define vnmsac_vv_u32m8(...) __riscv_vnmsac_vv_u32m8_tu(__VA_ARGS__) -#define vnmsac_vx_u32m8(...) __riscv_vnmsac_vx_u32m8_tu(__VA_ARGS__) -#define vnmsac_vv_u64m1(...) __riscv_vnmsac_vv_u64m1_tu(__VA_ARGS__) -#define vnmsac_vx_u64m1(...) __riscv_vnmsac_vx_u64m1_tu(__VA_ARGS__) -#define vnmsac_vv_u64m2(...) __riscv_vnmsac_vv_u64m2_tu(__VA_ARGS__) -#define vnmsac_vx_u64m2(...) __riscv_vnmsac_vx_u64m2_tu(__VA_ARGS__) -#define vnmsac_vv_u64m4(...) __riscv_vnmsac_vv_u64m4_tu(__VA_ARGS__) -#define vnmsac_vx_u64m4(...) __riscv_vnmsac_vx_u64m4_tu(__VA_ARGS__) -#define vnmsac_vv_u64m8(...) __riscv_vnmsac_vv_u64m8_tu(__VA_ARGS__) -#define vnmsac_vx_u64m8(...) __riscv_vnmsac_vx_u64m8_tu(__VA_ARGS__) -#define vmadd_vv_u8mf8(...) __riscv_vmadd_vv_u8mf8_tu(__VA_ARGS__) -#define vmadd_vx_u8mf8(...) __riscv_vmadd_vx_u8mf8_tu(__VA_ARGS__) -#define vmadd_vv_u8mf4(...) __riscv_vmadd_vv_u8mf4_tu(__VA_ARGS__) -#define vmadd_vx_u8mf4(...) __riscv_vmadd_vx_u8mf4_tu(__VA_ARGS__) -#define vmadd_vv_u8mf2(...) __riscv_vmadd_vv_u8mf2_tu(__VA_ARGS__) -#define vmadd_vx_u8mf2(...) __riscv_vmadd_vx_u8mf2_tu(__VA_ARGS__) -#define vmadd_vv_u8m1(...) __riscv_vmadd_vv_u8m1_tu(__VA_ARGS__) -#define vmadd_vx_u8m1(...) __riscv_vmadd_vx_u8m1_tu(__VA_ARGS__) -#define vmadd_vv_u8m2(...) __riscv_vmadd_vv_u8m2_tu(__VA_ARGS__) -#define vmadd_vx_u8m2(...) __riscv_vmadd_vx_u8m2_tu(__VA_ARGS__) -#define vmadd_vv_u8m4(...) __riscv_vmadd_vv_u8m4_tu(__VA_ARGS__) -#define vmadd_vx_u8m4(...) __riscv_vmadd_vx_u8m4_tu(__VA_ARGS__) -#define vmadd_vv_u8m8(...) __riscv_vmadd_vv_u8m8_tu(__VA_ARGS__) -#define vmadd_vx_u8m8(...) __riscv_vmadd_vx_u8m8_tu(__VA_ARGS__) -#define vmadd_vv_u16mf4(...) __riscv_vmadd_vv_u16mf4_tu(__VA_ARGS__) -#define vmadd_vx_u16mf4(...) __riscv_vmadd_vx_u16mf4_tu(__VA_ARGS__) -#define vmadd_vv_u16mf2(...) __riscv_vmadd_vv_u16mf2_tu(__VA_ARGS__) -#define vmadd_vx_u16mf2(...) __riscv_vmadd_vx_u16mf2_tu(__VA_ARGS__) -#define vmadd_vv_u16m1(...) __riscv_vmadd_vv_u16m1_tu(__VA_ARGS__) -#define vmadd_vx_u16m1(...) __riscv_vmadd_vx_u16m1_tu(__VA_ARGS__) -#define vmadd_vv_u16m2(...) __riscv_vmadd_vv_u16m2_tu(__VA_ARGS__) -#define vmadd_vx_u16m2(...) __riscv_vmadd_vx_u16m2_tu(__VA_ARGS__) -#define vmadd_vv_u16m4(...) __riscv_vmadd_vv_u16m4_tu(__VA_ARGS__) -#define vmadd_vx_u16m4(...) __riscv_vmadd_vx_u16m4_tu(__VA_ARGS__) -#define vmadd_vv_u16m8(...) __riscv_vmadd_vv_u16m8_tu(__VA_ARGS__) -#define vmadd_vx_u16m8(...) __riscv_vmadd_vx_u16m8_tu(__VA_ARGS__) -#define vmadd_vv_u32mf2(...) __riscv_vmadd_vv_u32mf2_tu(__VA_ARGS__) -#define vmadd_vx_u32mf2(...) __riscv_vmadd_vx_u32mf2_tu(__VA_ARGS__) -#define vmadd_vv_u32m1(...) __riscv_vmadd_vv_u32m1_tu(__VA_ARGS__) -#define vmadd_vx_u32m1(...) __riscv_vmadd_vx_u32m1_tu(__VA_ARGS__) -#define vmadd_vv_u32m2(...) __riscv_vmadd_vv_u32m2_tu(__VA_ARGS__) -#define vmadd_vx_u32m2(...) __riscv_vmadd_vx_u32m2_tu(__VA_ARGS__) -#define vmadd_vv_u32m4(...) __riscv_vmadd_vv_u32m4_tu(__VA_ARGS__) -#define vmadd_vx_u32m4(...) __riscv_vmadd_vx_u32m4_tu(__VA_ARGS__) -#define vmadd_vv_u32m8(...) __riscv_vmadd_vv_u32m8_tu(__VA_ARGS__) -#define vmadd_vx_u32m8(...) __riscv_vmadd_vx_u32m8_tu(__VA_ARGS__) -#define vmadd_vv_u64m1(...) __riscv_vmadd_vv_u64m1_tu(__VA_ARGS__) -#define vmadd_vx_u64m1(...) __riscv_vmadd_vx_u64m1_tu(__VA_ARGS__) -#define vmadd_vv_u64m2(...) __riscv_vmadd_vv_u64m2_tu(__VA_ARGS__) -#define vmadd_vx_u64m2(...) __riscv_vmadd_vx_u64m2_tu(__VA_ARGS__) -#define vmadd_vv_u64m4(...) __riscv_vmadd_vv_u64m4_tu(__VA_ARGS__) -#define vmadd_vx_u64m4(...) __riscv_vmadd_vx_u64m4_tu(__VA_ARGS__) -#define vmadd_vv_u64m8(...) __riscv_vmadd_vv_u64m8_tu(__VA_ARGS__) -#define vmadd_vx_u64m8(...) __riscv_vmadd_vx_u64m8_tu(__VA_ARGS__) -#define vnmsub_vv_u8mf8(...) __riscv_vnmsub_vv_u8mf8_tu(__VA_ARGS__) -#define vnmsub_vx_u8mf8(...) __riscv_vnmsub_vx_u8mf8_tu(__VA_ARGS__) -#define vnmsub_vv_u8mf4(...) __riscv_vnmsub_vv_u8mf4_tu(__VA_ARGS__) -#define vnmsub_vx_u8mf4(...) __riscv_vnmsub_vx_u8mf4_tu(__VA_ARGS__) -#define vnmsub_vv_u8mf2(...) __riscv_vnmsub_vv_u8mf2_tu(__VA_ARGS__) -#define vnmsub_vx_u8mf2(...) __riscv_vnmsub_vx_u8mf2_tu(__VA_ARGS__) -#define vnmsub_vv_u8m1(...) __riscv_vnmsub_vv_u8m1_tu(__VA_ARGS__) -#define vnmsub_vx_u8m1(...) __riscv_vnmsub_vx_u8m1_tu(__VA_ARGS__) -#define vnmsub_vv_u8m2(...) __riscv_vnmsub_vv_u8m2_tu(__VA_ARGS__) -#define vnmsub_vx_u8m2(...) __riscv_vnmsub_vx_u8m2_tu(__VA_ARGS__) -#define vnmsub_vv_u8m4(...) __riscv_vnmsub_vv_u8m4_tu(__VA_ARGS__) -#define vnmsub_vx_u8m4(...) __riscv_vnmsub_vx_u8m4_tu(__VA_ARGS__) -#define vnmsub_vv_u8m8(...) __riscv_vnmsub_vv_u8m8_tu(__VA_ARGS__) -#define vnmsub_vx_u8m8(...) __riscv_vnmsub_vx_u8m8_tu(__VA_ARGS__) -#define vnmsub_vv_u16mf4(...) __riscv_vnmsub_vv_u16mf4_tu(__VA_ARGS__) -#define vnmsub_vx_u16mf4(...) __riscv_vnmsub_vx_u16mf4_tu(__VA_ARGS__) -#define vnmsub_vv_u16mf2(...) __riscv_vnmsub_vv_u16mf2_tu(__VA_ARGS__) -#define vnmsub_vx_u16mf2(...) __riscv_vnmsub_vx_u16mf2_tu(__VA_ARGS__) -#define vnmsub_vv_u16m1(...) __riscv_vnmsub_vv_u16m1_tu(__VA_ARGS__) -#define vnmsub_vx_u16m1(...) __riscv_vnmsub_vx_u16m1_tu(__VA_ARGS__) -#define vnmsub_vv_u16m2(...) __riscv_vnmsub_vv_u16m2_tu(__VA_ARGS__) -#define vnmsub_vx_u16m2(...) __riscv_vnmsub_vx_u16m2_tu(__VA_ARGS__) -#define vnmsub_vv_u16m4(...) __riscv_vnmsub_vv_u16m4_tu(__VA_ARGS__) -#define vnmsub_vx_u16m4(...) __riscv_vnmsub_vx_u16m4_tu(__VA_ARGS__) -#define vnmsub_vv_u16m8(...) __riscv_vnmsub_vv_u16m8_tu(__VA_ARGS__) -#define vnmsub_vx_u16m8(...) __riscv_vnmsub_vx_u16m8_tu(__VA_ARGS__) -#define vnmsub_vv_u32mf2(...) __riscv_vnmsub_vv_u32mf2_tu(__VA_ARGS__) -#define vnmsub_vx_u32mf2(...) __riscv_vnmsub_vx_u32mf2_tu(__VA_ARGS__) -#define vnmsub_vv_u32m1(...) __riscv_vnmsub_vv_u32m1_tu(__VA_ARGS__) -#define vnmsub_vx_u32m1(...) __riscv_vnmsub_vx_u32m1_tu(__VA_ARGS__) -#define vnmsub_vv_u32m2(...) __riscv_vnmsub_vv_u32m2_tu(__VA_ARGS__) -#define vnmsub_vx_u32m2(...) __riscv_vnmsub_vx_u32m2_tu(__VA_ARGS__) -#define vnmsub_vv_u32m4(...) __riscv_vnmsub_vv_u32m4_tu(__VA_ARGS__) -#define vnmsub_vx_u32m4(...) __riscv_vnmsub_vx_u32m4_tu(__VA_ARGS__) -#define vnmsub_vv_u32m8(...) __riscv_vnmsub_vv_u32m8_tu(__VA_ARGS__) -#define vnmsub_vx_u32m8(...) __riscv_vnmsub_vx_u32m8_tu(__VA_ARGS__) -#define vnmsub_vv_u64m1(...) __riscv_vnmsub_vv_u64m1_tu(__VA_ARGS__) -#define vnmsub_vx_u64m1(...) __riscv_vnmsub_vx_u64m1_tu(__VA_ARGS__) -#define vnmsub_vv_u64m2(...) __riscv_vnmsub_vv_u64m2_tu(__VA_ARGS__) -#define vnmsub_vx_u64m2(...) __riscv_vnmsub_vx_u64m2_tu(__VA_ARGS__) -#define vnmsub_vv_u64m4(...) __riscv_vnmsub_vv_u64m4_tu(__VA_ARGS__) -#define vnmsub_vx_u64m4(...) __riscv_vnmsub_vx_u64m4_tu(__VA_ARGS__) -#define vnmsub_vv_u64m8(...) __riscv_vnmsub_vv_u64m8_tu(__VA_ARGS__) -#define vnmsub_vx_u64m8(...) __riscv_vnmsub_vx_u64m8_tu(__VA_ARGS__) -// masked functions -#define vmacc_vv_i8mf8_m(...) __riscv_vmacc_vv_i8mf8_tumu(__VA_ARGS__) -#define vmacc_vx_i8mf8_m(...) __riscv_vmacc_vx_i8mf8_tumu(__VA_ARGS__) -#define vmacc_vv_i8mf4_m(...) __riscv_vmacc_vv_i8mf4_tumu(__VA_ARGS__) -#define vmacc_vx_i8mf4_m(...) __riscv_vmacc_vx_i8mf4_tumu(__VA_ARGS__) -#define vmacc_vv_i8mf2_m(...) __riscv_vmacc_vv_i8mf2_tumu(__VA_ARGS__) -#define vmacc_vx_i8mf2_m(...) __riscv_vmacc_vx_i8mf2_tumu(__VA_ARGS__) -#define vmacc_vv_i8m1_m(...) __riscv_vmacc_vv_i8m1_tumu(__VA_ARGS__) -#define vmacc_vx_i8m1_m(...) __riscv_vmacc_vx_i8m1_tumu(__VA_ARGS__) -#define vmacc_vv_i8m2_m(...) __riscv_vmacc_vv_i8m2_tumu(__VA_ARGS__) -#define vmacc_vx_i8m2_m(...) __riscv_vmacc_vx_i8m2_tumu(__VA_ARGS__) -#define vmacc_vv_i8m4_m(...) __riscv_vmacc_vv_i8m4_tumu(__VA_ARGS__) -#define vmacc_vx_i8m4_m(...) __riscv_vmacc_vx_i8m4_tumu(__VA_ARGS__) -#define vmacc_vv_i8m8_m(...) __riscv_vmacc_vv_i8m8_tumu(__VA_ARGS__) -#define vmacc_vx_i8m8_m(...) __riscv_vmacc_vx_i8m8_tumu(__VA_ARGS__) -#define vmacc_vv_i16mf4_m(...) __riscv_vmacc_vv_i16mf4_tumu(__VA_ARGS__) -#define vmacc_vx_i16mf4_m(...) __riscv_vmacc_vx_i16mf4_tumu(__VA_ARGS__) -#define vmacc_vv_i16mf2_m(...) __riscv_vmacc_vv_i16mf2_tumu(__VA_ARGS__) -#define vmacc_vx_i16mf2_m(...) __riscv_vmacc_vx_i16mf2_tumu(__VA_ARGS__) -#define vmacc_vv_i16m1_m(...) __riscv_vmacc_vv_i16m1_tumu(__VA_ARGS__) -#define vmacc_vx_i16m1_m(...) __riscv_vmacc_vx_i16m1_tumu(__VA_ARGS__) -#define vmacc_vv_i16m2_m(...) __riscv_vmacc_vv_i16m2_tumu(__VA_ARGS__) -#define vmacc_vx_i16m2_m(...) __riscv_vmacc_vx_i16m2_tumu(__VA_ARGS__) -#define vmacc_vv_i16m4_m(...) __riscv_vmacc_vv_i16m4_tumu(__VA_ARGS__) -#define vmacc_vx_i16m4_m(...) __riscv_vmacc_vx_i16m4_tumu(__VA_ARGS__) -#define vmacc_vv_i16m8_m(...) __riscv_vmacc_vv_i16m8_tumu(__VA_ARGS__) -#define vmacc_vx_i16m8_m(...) __riscv_vmacc_vx_i16m8_tumu(__VA_ARGS__) -#define vmacc_vv_i32mf2_m(...) __riscv_vmacc_vv_i32mf2_tumu(__VA_ARGS__) -#define vmacc_vx_i32mf2_m(...) __riscv_vmacc_vx_i32mf2_tumu(__VA_ARGS__) -#define vmacc_vv_i32m1_m(...) __riscv_vmacc_vv_i32m1_tumu(__VA_ARGS__) -#define vmacc_vx_i32m1_m(...) __riscv_vmacc_vx_i32m1_tumu(__VA_ARGS__) -#define vmacc_vv_i32m2_m(...) __riscv_vmacc_vv_i32m2_tumu(__VA_ARGS__) -#define vmacc_vx_i32m2_m(...) __riscv_vmacc_vx_i32m2_tumu(__VA_ARGS__) -#define vmacc_vv_i32m4_m(...) __riscv_vmacc_vv_i32m4_tumu(__VA_ARGS__) -#define vmacc_vx_i32m4_m(...) __riscv_vmacc_vx_i32m4_tumu(__VA_ARGS__) -#define vmacc_vv_i32m8_m(...) __riscv_vmacc_vv_i32m8_tumu(__VA_ARGS__) -#define vmacc_vx_i32m8_m(...) __riscv_vmacc_vx_i32m8_tumu(__VA_ARGS__) -#define vmacc_vv_i64m1_m(...) __riscv_vmacc_vv_i64m1_tumu(__VA_ARGS__) -#define vmacc_vx_i64m1_m(...) __riscv_vmacc_vx_i64m1_tumu(__VA_ARGS__) -#define vmacc_vv_i64m2_m(...) __riscv_vmacc_vv_i64m2_tumu(__VA_ARGS__) -#define vmacc_vx_i64m2_m(...) __riscv_vmacc_vx_i64m2_tumu(__VA_ARGS__) -#define vmacc_vv_i64m4_m(...) __riscv_vmacc_vv_i64m4_tumu(__VA_ARGS__) -#define vmacc_vx_i64m4_m(...) __riscv_vmacc_vx_i64m4_tumu(__VA_ARGS__) -#define vmacc_vv_i64m8_m(...) __riscv_vmacc_vv_i64m8_tumu(__VA_ARGS__) -#define vmacc_vx_i64m8_m(...) __riscv_vmacc_vx_i64m8_tumu(__VA_ARGS__) -#define vnmsac_vv_i8mf8_m(...) __riscv_vnmsac_vv_i8mf8_tumu(__VA_ARGS__) -#define vnmsac_vx_i8mf8_m(...) __riscv_vnmsac_vx_i8mf8_tumu(__VA_ARGS__) -#define vnmsac_vv_i8mf4_m(...) __riscv_vnmsac_vv_i8mf4_tumu(__VA_ARGS__) -#define vnmsac_vx_i8mf4_m(...) __riscv_vnmsac_vx_i8mf4_tumu(__VA_ARGS__) -#define vnmsac_vv_i8mf2_m(...) __riscv_vnmsac_vv_i8mf2_tumu(__VA_ARGS__) -#define vnmsac_vx_i8mf2_m(...) __riscv_vnmsac_vx_i8mf2_tumu(__VA_ARGS__) -#define vnmsac_vv_i8m1_m(...) __riscv_vnmsac_vv_i8m1_tumu(__VA_ARGS__) -#define vnmsac_vx_i8m1_m(...) __riscv_vnmsac_vx_i8m1_tumu(__VA_ARGS__) -#define vnmsac_vv_i8m2_m(...) __riscv_vnmsac_vv_i8m2_tumu(__VA_ARGS__) -#define vnmsac_vx_i8m2_m(...) __riscv_vnmsac_vx_i8m2_tumu(__VA_ARGS__) -#define vnmsac_vv_i8m4_m(...) __riscv_vnmsac_vv_i8m4_tumu(__VA_ARGS__) -#define vnmsac_vx_i8m4_m(...) __riscv_vnmsac_vx_i8m4_tumu(__VA_ARGS__) -#define vnmsac_vv_i8m8_m(...) __riscv_vnmsac_vv_i8m8_tumu(__VA_ARGS__) -#define vnmsac_vx_i8m8_m(...) __riscv_vnmsac_vx_i8m8_tumu(__VA_ARGS__) -#define vnmsac_vv_i16mf4_m(...) __riscv_vnmsac_vv_i16mf4_tumu(__VA_ARGS__) -#define vnmsac_vx_i16mf4_m(...) __riscv_vnmsac_vx_i16mf4_tumu(__VA_ARGS__) -#define vnmsac_vv_i16mf2_m(...) __riscv_vnmsac_vv_i16mf2_tumu(__VA_ARGS__) -#define vnmsac_vx_i16mf2_m(...) __riscv_vnmsac_vx_i16mf2_tumu(__VA_ARGS__) -#define vnmsac_vv_i16m1_m(...) __riscv_vnmsac_vv_i16m1_tumu(__VA_ARGS__) -#define vnmsac_vx_i16m1_m(...) __riscv_vnmsac_vx_i16m1_tumu(__VA_ARGS__) -#define vnmsac_vv_i16m2_m(...) __riscv_vnmsac_vv_i16m2_tumu(__VA_ARGS__) -#define vnmsac_vx_i16m2_m(...) __riscv_vnmsac_vx_i16m2_tumu(__VA_ARGS__) -#define vnmsac_vv_i16m4_m(...) __riscv_vnmsac_vv_i16m4_tumu(__VA_ARGS__) -#define vnmsac_vx_i16m4_m(...) __riscv_vnmsac_vx_i16m4_tumu(__VA_ARGS__) -#define vnmsac_vv_i16m8_m(...) __riscv_vnmsac_vv_i16m8_tumu(__VA_ARGS__) -#define vnmsac_vx_i16m8_m(...) __riscv_vnmsac_vx_i16m8_tumu(__VA_ARGS__) -#define vnmsac_vv_i32mf2_m(...) __riscv_vnmsac_vv_i32mf2_tumu(__VA_ARGS__) -#define vnmsac_vx_i32mf2_m(...) __riscv_vnmsac_vx_i32mf2_tumu(__VA_ARGS__) -#define vnmsac_vv_i32m1_m(...) __riscv_vnmsac_vv_i32m1_tumu(__VA_ARGS__) -#define vnmsac_vx_i32m1_m(...) __riscv_vnmsac_vx_i32m1_tumu(__VA_ARGS__) -#define vnmsac_vv_i32m2_m(...) __riscv_vnmsac_vv_i32m2_tumu(__VA_ARGS__) -#define vnmsac_vx_i32m2_m(...) __riscv_vnmsac_vx_i32m2_tumu(__VA_ARGS__) -#define vnmsac_vv_i32m4_m(...) __riscv_vnmsac_vv_i32m4_tumu(__VA_ARGS__) -#define vnmsac_vx_i32m4_m(...) __riscv_vnmsac_vx_i32m4_tumu(__VA_ARGS__) -#define vnmsac_vv_i32m8_m(...) __riscv_vnmsac_vv_i32m8_tumu(__VA_ARGS__) -#define vnmsac_vx_i32m8_m(...) __riscv_vnmsac_vx_i32m8_tumu(__VA_ARGS__) -#define vnmsac_vv_i64m1_m(...) __riscv_vnmsac_vv_i64m1_tumu(__VA_ARGS__) -#define vnmsac_vx_i64m1_m(...) __riscv_vnmsac_vx_i64m1_tumu(__VA_ARGS__) -#define vnmsac_vv_i64m2_m(...) __riscv_vnmsac_vv_i64m2_tumu(__VA_ARGS__) -#define vnmsac_vx_i64m2_m(...) __riscv_vnmsac_vx_i64m2_tumu(__VA_ARGS__) -#define vnmsac_vv_i64m4_m(...) __riscv_vnmsac_vv_i64m4_tumu(__VA_ARGS__) -#define vnmsac_vx_i64m4_m(...) __riscv_vnmsac_vx_i64m4_tumu(__VA_ARGS__) -#define vnmsac_vv_i64m8_m(...) __riscv_vnmsac_vv_i64m8_tumu(__VA_ARGS__) -#define vnmsac_vx_i64m8_m(...) __riscv_vnmsac_vx_i64m8_tumu(__VA_ARGS__) -#define vmadd_vv_i8mf8_m(...) __riscv_vmadd_vv_i8mf8_tumu(__VA_ARGS__) -#define vmadd_vx_i8mf8_m(...) __riscv_vmadd_vx_i8mf8_tumu(__VA_ARGS__) -#define vmadd_vv_i8mf4_m(...) __riscv_vmadd_vv_i8mf4_tumu(__VA_ARGS__) -#define vmadd_vx_i8mf4_m(...) __riscv_vmadd_vx_i8mf4_tumu(__VA_ARGS__) -#define vmadd_vv_i8mf2_m(...) __riscv_vmadd_vv_i8mf2_tumu(__VA_ARGS__) -#define vmadd_vx_i8mf2_m(...) __riscv_vmadd_vx_i8mf2_tumu(__VA_ARGS__) -#define vmadd_vv_i8m1_m(...) __riscv_vmadd_vv_i8m1_tumu(__VA_ARGS__) -#define vmadd_vx_i8m1_m(...) __riscv_vmadd_vx_i8m1_tumu(__VA_ARGS__) -#define vmadd_vv_i8m2_m(...) __riscv_vmadd_vv_i8m2_tumu(__VA_ARGS__) -#define vmadd_vx_i8m2_m(...) __riscv_vmadd_vx_i8m2_tumu(__VA_ARGS__) -#define vmadd_vv_i8m4_m(...) __riscv_vmadd_vv_i8m4_tumu(__VA_ARGS__) -#define vmadd_vx_i8m4_m(...) __riscv_vmadd_vx_i8m4_tumu(__VA_ARGS__) -#define vmadd_vv_i8m8_m(...) __riscv_vmadd_vv_i8m8_tumu(__VA_ARGS__) -#define vmadd_vx_i8m8_m(...) __riscv_vmadd_vx_i8m8_tumu(__VA_ARGS__) -#define vmadd_vv_i16mf4_m(...) __riscv_vmadd_vv_i16mf4_tumu(__VA_ARGS__) -#define vmadd_vx_i16mf4_m(...) __riscv_vmadd_vx_i16mf4_tumu(__VA_ARGS__) -#define vmadd_vv_i16mf2_m(...) __riscv_vmadd_vv_i16mf2_tumu(__VA_ARGS__) -#define vmadd_vx_i16mf2_m(...) __riscv_vmadd_vx_i16mf2_tumu(__VA_ARGS__) -#define vmadd_vv_i16m1_m(...) __riscv_vmadd_vv_i16m1_tumu(__VA_ARGS__) -#define vmadd_vx_i16m1_m(...) __riscv_vmadd_vx_i16m1_tumu(__VA_ARGS__) -#define vmadd_vv_i16m2_m(...) __riscv_vmadd_vv_i16m2_tumu(__VA_ARGS__) -#define vmadd_vx_i16m2_m(...) __riscv_vmadd_vx_i16m2_tumu(__VA_ARGS__) -#define vmadd_vv_i16m4_m(...) __riscv_vmadd_vv_i16m4_tumu(__VA_ARGS__) -#define vmadd_vx_i16m4_m(...) __riscv_vmadd_vx_i16m4_tumu(__VA_ARGS__) -#define vmadd_vv_i16m8_m(...) __riscv_vmadd_vv_i16m8_tumu(__VA_ARGS__) -#define vmadd_vx_i16m8_m(...) __riscv_vmadd_vx_i16m8_tumu(__VA_ARGS__) -#define vmadd_vv_i32mf2_m(...) __riscv_vmadd_vv_i32mf2_tumu(__VA_ARGS__) -#define vmadd_vx_i32mf2_m(...) __riscv_vmadd_vx_i32mf2_tumu(__VA_ARGS__) -#define vmadd_vv_i32m1_m(...) __riscv_vmadd_vv_i32m1_tumu(__VA_ARGS__) -#define vmadd_vx_i32m1_m(...) __riscv_vmadd_vx_i32m1_tumu(__VA_ARGS__) -#define vmadd_vv_i32m2_m(...) __riscv_vmadd_vv_i32m2_tumu(__VA_ARGS__) -#define vmadd_vx_i32m2_m(...) __riscv_vmadd_vx_i32m2_tumu(__VA_ARGS__) -#define vmadd_vv_i32m4_m(...) __riscv_vmadd_vv_i32m4_tumu(__VA_ARGS__) -#define vmadd_vx_i32m4_m(...) __riscv_vmadd_vx_i32m4_tumu(__VA_ARGS__) -#define vmadd_vv_i32m8_m(...) __riscv_vmadd_vv_i32m8_tumu(__VA_ARGS__) -#define vmadd_vx_i32m8_m(...) __riscv_vmadd_vx_i32m8_tumu(__VA_ARGS__) -#define vmadd_vv_i64m1_m(...) __riscv_vmadd_vv_i64m1_tumu(__VA_ARGS__) -#define vmadd_vx_i64m1_m(...) __riscv_vmadd_vx_i64m1_tumu(__VA_ARGS__) -#define vmadd_vv_i64m2_m(...) __riscv_vmadd_vv_i64m2_tumu(__VA_ARGS__) -#define vmadd_vx_i64m2_m(...) __riscv_vmadd_vx_i64m2_tumu(__VA_ARGS__) -#define vmadd_vv_i64m4_m(...) __riscv_vmadd_vv_i64m4_tumu(__VA_ARGS__) -#define vmadd_vx_i64m4_m(...) __riscv_vmadd_vx_i64m4_tumu(__VA_ARGS__) -#define vmadd_vv_i64m8_m(...) __riscv_vmadd_vv_i64m8_tumu(__VA_ARGS__) -#define vmadd_vx_i64m8_m(...) __riscv_vmadd_vx_i64m8_tumu(__VA_ARGS__) -#define vnmsub_vv_i8mf8_m(...) __riscv_vnmsub_vv_i8mf8_tumu(__VA_ARGS__) -#define vnmsub_vx_i8mf8_m(...) __riscv_vnmsub_vx_i8mf8_tumu(__VA_ARGS__) -#define vnmsub_vv_i8mf4_m(...) __riscv_vnmsub_vv_i8mf4_tumu(__VA_ARGS__) -#define vnmsub_vx_i8mf4_m(...) __riscv_vnmsub_vx_i8mf4_tumu(__VA_ARGS__) -#define vnmsub_vv_i8mf2_m(...) __riscv_vnmsub_vv_i8mf2_tumu(__VA_ARGS__) -#define vnmsub_vx_i8mf2_m(...) __riscv_vnmsub_vx_i8mf2_tumu(__VA_ARGS__) -#define vnmsub_vv_i8m1_m(...) __riscv_vnmsub_vv_i8m1_tumu(__VA_ARGS__) -#define vnmsub_vx_i8m1_m(...) __riscv_vnmsub_vx_i8m1_tumu(__VA_ARGS__) -#define vnmsub_vv_i8m2_m(...) __riscv_vnmsub_vv_i8m2_tumu(__VA_ARGS__) -#define vnmsub_vx_i8m2_m(...) __riscv_vnmsub_vx_i8m2_tumu(__VA_ARGS__) -#define vnmsub_vv_i8m4_m(...) __riscv_vnmsub_vv_i8m4_tumu(__VA_ARGS__) -#define vnmsub_vx_i8m4_m(...) __riscv_vnmsub_vx_i8m4_tumu(__VA_ARGS__) -#define vnmsub_vv_i8m8_m(...) __riscv_vnmsub_vv_i8m8_tumu(__VA_ARGS__) -#define vnmsub_vx_i8m8_m(...) __riscv_vnmsub_vx_i8m8_tumu(__VA_ARGS__) -#define vnmsub_vv_i16mf4_m(...) __riscv_vnmsub_vv_i16mf4_tumu(__VA_ARGS__) -#define vnmsub_vx_i16mf4_m(...) __riscv_vnmsub_vx_i16mf4_tumu(__VA_ARGS__) -#define vnmsub_vv_i16mf2_m(...) __riscv_vnmsub_vv_i16mf2_tumu(__VA_ARGS__) -#define vnmsub_vx_i16mf2_m(...) __riscv_vnmsub_vx_i16mf2_tumu(__VA_ARGS__) -#define vnmsub_vv_i16m1_m(...) __riscv_vnmsub_vv_i16m1_tumu(__VA_ARGS__) -#define vnmsub_vx_i16m1_m(...) __riscv_vnmsub_vx_i16m1_tumu(__VA_ARGS__) -#define vnmsub_vv_i16m2_m(...) __riscv_vnmsub_vv_i16m2_tumu(__VA_ARGS__) -#define vnmsub_vx_i16m2_m(...) __riscv_vnmsub_vx_i16m2_tumu(__VA_ARGS__) -#define vnmsub_vv_i16m4_m(...) __riscv_vnmsub_vv_i16m4_tumu(__VA_ARGS__) -#define vnmsub_vx_i16m4_m(...) __riscv_vnmsub_vx_i16m4_tumu(__VA_ARGS__) -#define vnmsub_vv_i16m8_m(...) __riscv_vnmsub_vv_i16m8_tumu(__VA_ARGS__) -#define vnmsub_vx_i16m8_m(...) __riscv_vnmsub_vx_i16m8_tumu(__VA_ARGS__) -#define vnmsub_vv_i32mf2_m(...) __riscv_vnmsub_vv_i32mf2_tumu(__VA_ARGS__) -#define vnmsub_vx_i32mf2_m(...) __riscv_vnmsub_vx_i32mf2_tumu(__VA_ARGS__) -#define vnmsub_vv_i32m1_m(...) __riscv_vnmsub_vv_i32m1_tumu(__VA_ARGS__) -#define vnmsub_vx_i32m1_m(...) __riscv_vnmsub_vx_i32m1_tumu(__VA_ARGS__) -#define vnmsub_vv_i32m2_m(...) __riscv_vnmsub_vv_i32m2_tumu(__VA_ARGS__) -#define vnmsub_vx_i32m2_m(...) __riscv_vnmsub_vx_i32m2_tumu(__VA_ARGS__) -#define vnmsub_vv_i32m4_m(...) __riscv_vnmsub_vv_i32m4_tumu(__VA_ARGS__) -#define vnmsub_vx_i32m4_m(...) __riscv_vnmsub_vx_i32m4_tumu(__VA_ARGS__) -#define vnmsub_vv_i32m8_m(...) __riscv_vnmsub_vv_i32m8_tumu(__VA_ARGS__) -#define vnmsub_vx_i32m8_m(...) __riscv_vnmsub_vx_i32m8_tumu(__VA_ARGS__) -#define vnmsub_vv_i64m1_m(...) __riscv_vnmsub_vv_i64m1_tumu(__VA_ARGS__) -#define vnmsub_vx_i64m1_m(...) __riscv_vnmsub_vx_i64m1_tumu(__VA_ARGS__) -#define vnmsub_vv_i64m2_m(...) __riscv_vnmsub_vv_i64m2_tumu(__VA_ARGS__) -#define vnmsub_vx_i64m2_m(...) __riscv_vnmsub_vx_i64m2_tumu(__VA_ARGS__) -#define vnmsub_vv_i64m4_m(...) __riscv_vnmsub_vv_i64m4_tumu(__VA_ARGS__) -#define vnmsub_vx_i64m4_m(...) __riscv_vnmsub_vx_i64m4_tumu(__VA_ARGS__) -#define vnmsub_vv_i64m8_m(...) __riscv_vnmsub_vv_i64m8_tumu(__VA_ARGS__) -#define vnmsub_vx_i64m8_m(...) __riscv_vnmsub_vx_i64m8_tumu(__VA_ARGS__) -#define vmacc_vv_u8mf8_m(...) __riscv_vmacc_vv_u8mf8_tumu(__VA_ARGS__) -#define vmacc_vx_u8mf8_m(...) __riscv_vmacc_vx_u8mf8_tumu(__VA_ARGS__) -#define vmacc_vv_u8mf4_m(...) __riscv_vmacc_vv_u8mf4_tumu(__VA_ARGS__) -#define vmacc_vx_u8mf4_m(...) __riscv_vmacc_vx_u8mf4_tumu(__VA_ARGS__) -#define vmacc_vv_u8mf2_m(...) __riscv_vmacc_vv_u8mf2_tumu(__VA_ARGS__) -#define vmacc_vx_u8mf2_m(...) __riscv_vmacc_vx_u8mf2_tumu(__VA_ARGS__) -#define vmacc_vv_u8m1_m(...) __riscv_vmacc_vv_u8m1_tumu(__VA_ARGS__) -#define vmacc_vx_u8m1_m(...) __riscv_vmacc_vx_u8m1_tumu(__VA_ARGS__) -#define vmacc_vv_u8m2_m(...) __riscv_vmacc_vv_u8m2_tumu(__VA_ARGS__) -#define vmacc_vx_u8m2_m(...) __riscv_vmacc_vx_u8m2_tumu(__VA_ARGS__) -#define vmacc_vv_u8m4_m(...) __riscv_vmacc_vv_u8m4_tumu(__VA_ARGS__) -#define vmacc_vx_u8m4_m(...) __riscv_vmacc_vx_u8m4_tumu(__VA_ARGS__) -#define vmacc_vv_u8m8_m(...) __riscv_vmacc_vv_u8m8_tumu(__VA_ARGS__) -#define vmacc_vx_u8m8_m(...) __riscv_vmacc_vx_u8m8_tumu(__VA_ARGS__) -#define vmacc_vv_u16mf4_m(...) __riscv_vmacc_vv_u16mf4_tumu(__VA_ARGS__) -#define vmacc_vx_u16mf4_m(...) __riscv_vmacc_vx_u16mf4_tumu(__VA_ARGS__) -#define vmacc_vv_u16mf2_m(...) __riscv_vmacc_vv_u16mf2_tumu(__VA_ARGS__) -#define vmacc_vx_u16mf2_m(...) __riscv_vmacc_vx_u16mf2_tumu(__VA_ARGS__) -#define vmacc_vv_u16m1_m(...) __riscv_vmacc_vv_u16m1_tumu(__VA_ARGS__) -#define vmacc_vx_u16m1_m(...) __riscv_vmacc_vx_u16m1_tumu(__VA_ARGS__) -#define vmacc_vv_u16m2_m(...) __riscv_vmacc_vv_u16m2_tumu(__VA_ARGS__) -#define vmacc_vx_u16m2_m(...) __riscv_vmacc_vx_u16m2_tumu(__VA_ARGS__) -#define vmacc_vv_u16m4_m(...) __riscv_vmacc_vv_u16m4_tumu(__VA_ARGS__) -#define vmacc_vx_u16m4_m(...) __riscv_vmacc_vx_u16m4_tumu(__VA_ARGS__) -#define vmacc_vv_u16m8_m(...) __riscv_vmacc_vv_u16m8_tumu(__VA_ARGS__) -#define vmacc_vx_u16m8_m(...) __riscv_vmacc_vx_u16m8_tumu(__VA_ARGS__) -#define vmacc_vv_u32mf2_m(...) __riscv_vmacc_vv_u32mf2_tumu(__VA_ARGS__) -#define vmacc_vx_u32mf2_m(...) __riscv_vmacc_vx_u32mf2_tumu(__VA_ARGS__) -#define vmacc_vv_u32m1_m(...) __riscv_vmacc_vv_u32m1_tumu(__VA_ARGS__) -#define vmacc_vx_u32m1_m(...) __riscv_vmacc_vx_u32m1_tumu(__VA_ARGS__) -#define vmacc_vv_u32m2_m(...) __riscv_vmacc_vv_u32m2_tumu(__VA_ARGS__) -#define vmacc_vx_u32m2_m(...) __riscv_vmacc_vx_u32m2_tumu(__VA_ARGS__) -#define vmacc_vv_u32m4_m(...) __riscv_vmacc_vv_u32m4_tumu(__VA_ARGS__) -#define vmacc_vx_u32m4_m(...) __riscv_vmacc_vx_u32m4_tumu(__VA_ARGS__) -#define vmacc_vv_u32m8_m(...) __riscv_vmacc_vv_u32m8_tumu(__VA_ARGS__) -#define vmacc_vx_u32m8_m(...) __riscv_vmacc_vx_u32m8_tumu(__VA_ARGS__) -#define vmacc_vv_u64m1_m(...) __riscv_vmacc_vv_u64m1_tumu(__VA_ARGS__) -#define vmacc_vx_u64m1_m(...) __riscv_vmacc_vx_u64m1_tumu(__VA_ARGS__) -#define vmacc_vv_u64m2_m(...) __riscv_vmacc_vv_u64m2_tumu(__VA_ARGS__) -#define vmacc_vx_u64m2_m(...) __riscv_vmacc_vx_u64m2_tumu(__VA_ARGS__) -#define vmacc_vv_u64m4_m(...) __riscv_vmacc_vv_u64m4_tumu(__VA_ARGS__) -#define vmacc_vx_u64m4_m(...) __riscv_vmacc_vx_u64m4_tumu(__VA_ARGS__) -#define vmacc_vv_u64m8_m(...) __riscv_vmacc_vv_u64m8_tumu(__VA_ARGS__) -#define vmacc_vx_u64m8_m(...) __riscv_vmacc_vx_u64m8_tumu(__VA_ARGS__) -#define vnmsac_vv_u8mf8_m(...) __riscv_vnmsac_vv_u8mf8_tumu(__VA_ARGS__) -#define vnmsac_vx_u8mf8_m(...) __riscv_vnmsac_vx_u8mf8_tumu(__VA_ARGS__) -#define vnmsac_vv_u8mf4_m(...) __riscv_vnmsac_vv_u8mf4_tumu(__VA_ARGS__) -#define vnmsac_vx_u8mf4_m(...) __riscv_vnmsac_vx_u8mf4_tumu(__VA_ARGS__) -#define vnmsac_vv_u8mf2_m(...) __riscv_vnmsac_vv_u8mf2_tumu(__VA_ARGS__) -#define vnmsac_vx_u8mf2_m(...) __riscv_vnmsac_vx_u8mf2_tumu(__VA_ARGS__) -#define vnmsac_vv_u8m1_m(...) __riscv_vnmsac_vv_u8m1_tumu(__VA_ARGS__) -#define vnmsac_vx_u8m1_m(...) __riscv_vnmsac_vx_u8m1_tumu(__VA_ARGS__) -#define vnmsac_vv_u8m2_m(...) __riscv_vnmsac_vv_u8m2_tumu(__VA_ARGS__) -#define vnmsac_vx_u8m2_m(...) __riscv_vnmsac_vx_u8m2_tumu(__VA_ARGS__) -#define vnmsac_vv_u8m4_m(...) __riscv_vnmsac_vv_u8m4_tumu(__VA_ARGS__) -#define vnmsac_vx_u8m4_m(...) __riscv_vnmsac_vx_u8m4_tumu(__VA_ARGS__) -#define vnmsac_vv_u8m8_m(...) __riscv_vnmsac_vv_u8m8_tumu(__VA_ARGS__) -#define vnmsac_vx_u8m8_m(...) __riscv_vnmsac_vx_u8m8_tumu(__VA_ARGS__) -#define vnmsac_vv_u16mf4_m(...) __riscv_vnmsac_vv_u16mf4_tumu(__VA_ARGS__) -#define vnmsac_vx_u16mf4_m(...) __riscv_vnmsac_vx_u16mf4_tumu(__VA_ARGS__) -#define vnmsac_vv_u16mf2_m(...) __riscv_vnmsac_vv_u16mf2_tumu(__VA_ARGS__) -#define vnmsac_vx_u16mf2_m(...) __riscv_vnmsac_vx_u16mf2_tumu(__VA_ARGS__) -#define vnmsac_vv_u16m1_m(...) __riscv_vnmsac_vv_u16m1_tumu(__VA_ARGS__) -#define vnmsac_vx_u16m1_m(...) __riscv_vnmsac_vx_u16m1_tumu(__VA_ARGS__) -#define vnmsac_vv_u16m2_m(...) __riscv_vnmsac_vv_u16m2_tumu(__VA_ARGS__) -#define vnmsac_vx_u16m2_m(...) __riscv_vnmsac_vx_u16m2_tumu(__VA_ARGS__) -#define vnmsac_vv_u16m4_m(...) __riscv_vnmsac_vv_u16m4_tumu(__VA_ARGS__) -#define vnmsac_vx_u16m4_m(...) __riscv_vnmsac_vx_u16m4_tumu(__VA_ARGS__) -#define vnmsac_vv_u16m8_m(...) __riscv_vnmsac_vv_u16m8_tumu(__VA_ARGS__) -#define vnmsac_vx_u16m8_m(...) __riscv_vnmsac_vx_u16m8_tumu(__VA_ARGS__) -#define vnmsac_vv_u32mf2_m(...) __riscv_vnmsac_vv_u32mf2_tumu(__VA_ARGS__) -#define vnmsac_vx_u32mf2_m(...) __riscv_vnmsac_vx_u32mf2_tumu(__VA_ARGS__) -#define vnmsac_vv_u32m1_m(...) __riscv_vnmsac_vv_u32m1_tumu(__VA_ARGS__) -#define vnmsac_vx_u32m1_m(...) __riscv_vnmsac_vx_u32m1_tumu(__VA_ARGS__) -#define vnmsac_vv_u32m2_m(...) __riscv_vnmsac_vv_u32m2_tumu(__VA_ARGS__) -#define vnmsac_vx_u32m2_m(...) __riscv_vnmsac_vx_u32m2_tumu(__VA_ARGS__) -#define vnmsac_vv_u32m4_m(...) __riscv_vnmsac_vv_u32m4_tumu(__VA_ARGS__) -#define vnmsac_vx_u32m4_m(...) __riscv_vnmsac_vx_u32m4_tumu(__VA_ARGS__) -#define vnmsac_vv_u32m8_m(...) __riscv_vnmsac_vv_u32m8_tumu(__VA_ARGS__) -#define vnmsac_vx_u32m8_m(...) __riscv_vnmsac_vx_u32m8_tumu(__VA_ARGS__) -#define vnmsac_vv_u64m1_m(...) __riscv_vnmsac_vv_u64m1_tumu(__VA_ARGS__) -#define vnmsac_vx_u64m1_m(...) __riscv_vnmsac_vx_u64m1_tumu(__VA_ARGS__) -#define vnmsac_vv_u64m2_m(...) __riscv_vnmsac_vv_u64m2_tumu(__VA_ARGS__) -#define vnmsac_vx_u64m2_m(...) __riscv_vnmsac_vx_u64m2_tumu(__VA_ARGS__) -#define vnmsac_vv_u64m4_m(...) __riscv_vnmsac_vv_u64m4_tumu(__VA_ARGS__) -#define vnmsac_vx_u64m4_m(...) __riscv_vnmsac_vx_u64m4_tumu(__VA_ARGS__) -#define vnmsac_vv_u64m8_m(...) __riscv_vnmsac_vv_u64m8_tumu(__VA_ARGS__) -#define vnmsac_vx_u64m8_m(...) __riscv_vnmsac_vx_u64m8_tumu(__VA_ARGS__) -#define vmadd_vv_u8mf8_m(...) __riscv_vmadd_vv_u8mf8_tumu(__VA_ARGS__) -#define vmadd_vx_u8mf8_m(...) __riscv_vmadd_vx_u8mf8_tumu(__VA_ARGS__) -#define vmadd_vv_u8mf4_m(...) __riscv_vmadd_vv_u8mf4_tumu(__VA_ARGS__) -#define vmadd_vx_u8mf4_m(...) __riscv_vmadd_vx_u8mf4_tumu(__VA_ARGS__) -#define vmadd_vv_u8mf2_m(...) __riscv_vmadd_vv_u8mf2_tumu(__VA_ARGS__) -#define vmadd_vx_u8mf2_m(...) __riscv_vmadd_vx_u8mf2_tumu(__VA_ARGS__) -#define vmadd_vv_u8m1_m(...) __riscv_vmadd_vv_u8m1_tumu(__VA_ARGS__) -#define vmadd_vx_u8m1_m(...) __riscv_vmadd_vx_u8m1_tumu(__VA_ARGS__) -#define vmadd_vv_u8m2_m(...) __riscv_vmadd_vv_u8m2_tumu(__VA_ARGS__) -#define vmadd_vx_u8m2_m(...) __riscv_vmadd_vx_u8m2_tumu(__VA_ARGS__) -#define vmadd_vv_u8m4_m(...) __riscv_vmadd_vv_u8m4_tumu(__VA_ARGS__) -#define vmadd_vx_u8m4_m(...) __riscv_vmadd_vx_u8m4_tumu(__VA_ARGS__) -#define vmadd_vv_u8m8_m(...) __riscv_vmadd_vv_u8m8_tumu(__VA_ARGS__) -#define vmadd_vx_u8m8_m(...) __riscv_vmadd_vx_u8m8_tumu(__VA_ARGS__) -#define vmadd_vv_u16mf4_m(...) __riscv_vmadd_vv_u16mf4_tumu(__VA_ARGS__) -#define vmadd_vx_u16mf4_m(...) __riscv_vmadd_vx_u16mf4_tumu(__VA_ARGS__) -#define vmadd_vv_u16mf2_m(...) __riscv_vmadd_vv_u16mf2_tumu(__VA_ARGS__) -#define vmadd_vx_u16mf2_m(...) __riscv_vmadd_vx_u16mf2_tumu(__VA_ARGS__) -#define vmadd_vv_u16m1_m(...) __riscv_vmadd_vv_u16m1_tumu(__VA_ARGS__) -#define vmadd_vx_u16m1_m(...) __riscv_vmadd_vx_u16m1_tumu(__VA_ARGS__) -#define vmadd_vv_u16m2_m(...) __riscv_vmadd_vv_u16m2_tumu(__VA_ARGS__) -#define vmadd_vx_u16m2_m(...) __riscv_vmadd_vx_u16m2_tumu(__VA_ARGS__) -#define vmadd_vv_u16m4_m(...) __riscv_vmadd_vv_u16m4_tumu(__VA_ARGS__) -#define vmadd_vx_u16m4_m(...) __riscv_vmadd_vx_u16m4_tumu(__VA_ARGS__) -#define vmadd_vv_u16m8_m(...) __riscv_vmadd_vv_u16m8_tumu(__VA_ARGS__) -#define vmadd_vx_u16m8_m(...) __riscv_vmadd_vx_u16m8_tumu(__VA_ARGS__) -#define vmadd_vv_u32mf2_m(...) __riscv_vmadd_vv_u32mf2_tumu(__VA_ARGS__) -#define vmadd_vx_u32mf2_m(...) __riscv_vmadd_vx_u32mf2_tumu(__VA_ARGS__) -#define vmadd_vv_u32m1_m(...) __riscv_vmadd_vv_u32m1_tumu(__VA_ARGS__) -#define vmadd_vx_u32m1_m(...) __riscv_vmadd_vx_u32m1_tumu(__VA_ARGS__) -#define vmadd_vv_u32m2_m(...) __riscv_vmadd_vv_u32m2_tumu(__VA_ARGS__) -#define vmadd_vx_u32m2_m(...) __riscv_vmadd_vx_u32m2_tumu(__VA_ARGS__) -#define vmadd_vv_u32m4_m(...) __riscv_vmadd_vv_u32m4_tumu(__VA_ARGS__) -#define vmadd_vx_u32m4_m(...) __riscv_vmadd_vx_u32m4_tumu(__VA_ARGS__) -#define vmadd_vv_u32m8_m(...) __riscv_vmadd_vv_u32m8_tumu(__VA_ARGS__) -#define vmadd_vx_u32m8_m(...) __riscv_vmadd_vx_u32m8_tumu(__VA_ARGS__) -#define vmadd_vv_u64m1_m(...) __riscv_vmadd_vv_u64m1_tumu(__VA_ARGS__) -#define vmadd_vx_u64m1_m(...) __riscv_vmadd_vx_u64m1_tumu(__VA_ARGS__) -#define vmadd_vv_u64m2_m(...) __riscv_vmadd_vv_u64m2_tumu(__VA_ARGS__) -#define vmadd_vx_u64m2_m(...) __riscv_vmadd_vx_u64m2_tumu(__VA_ARGS__) -#define vmadd_vv_u64m4_m(...) __riscv_vmadd_vv_u64m4_tumu(__VA_ARGS__) -#define vmadd_vx_u64m4_m(...) __riscv_vmadd_vx_u64m4_tumu(__VA_ARGS__) -#define vmadd_vv_u64m8_m(...) __riscv_vmadd_vv_u64m8_tumu(__VA_ARGS__) -#define vmadd_vx_u64m8_m(...) __riscv_vmadd_vx_u64m8_tumu(__VA_ARGS__) -#define vnmsub_vv_u8mf8_m(...) __riscv_vnmsub_vv_u8mf8_tumu(__VA_ARGS__) -#define vnmsub_vx_u8mf8_m(...) __riscv_vnmsub_vx_u8mf8_tumu(__VA_ARGS__) -#define vnmsub_vv_u8mf4_m(...) __riscv_vnmsub_vv_u8mf4_tumu(__VA_ARGS__) -#define vnmsub_vx_u8mf4_m(...) __riscv_vnmsub_vx_u8mf4_tumu(__VA_ARGS__) -#define vnmsub_vv_u8mf2_m(...) __riscv_vnmsub_vv_u8mf2_tumu(__VA_ARGS__) -#define vnmsub_vx_u8mf2_m(...) __riscv_vnmsub_vx_u8mf2_tumu(__VA_ARGS__) -#define vnmsub_vv_u8m1_m(...) __riscv_vnmsub_vv_u8m1_tumu(__VA_ARGS__) -#define vnmsub_vx_u8m1_m(...) __riscv_vnmsub_vx_u8m1_tumu(__VA_ARGS__) -#define vnmsub_vv_u8m2_m(...) __riscv_vnmsub_vv_u8m2_tumu(__VA_ARGS__) -#define vnmsub_vx_u8m2_m(...) __riscv_vnmsub_vx_u8m2_tumu(__VA_ARGS__) -#define vnmsub_vv_u8m4_m(...) __riscv_vnmsub_vv_u8m4_tumu(__VA_ARGS__) -#define vnmsub_vx_u8m4_m(...) __riscv_vnmsub_vx_u8m4_tumu(__VA_ARGS__) -#define vnmsub_vv_u8m8_m(...) __riscv_vnmsub_vv_u8m8_tumu(__VA_ARGS__) -#define vnmsub_vx_u8m8_m(...) __riscv_vnmsub_vx_u8m8_tumu(__VA_ARGS__) -#define vnmsub_vv_u16mf4_m(...) __riscv_vnmsub_vv_u16mf4_tumu(__VA_ARGS__) -#define vnmsub_vx_u16mf4_m(...) __riscv_vnmsub_vx_u16mf4_tumu(__VA_ARGS__) -#define vnmsub_vv_u16mf2_m(...) __riscv_vnmsub_vv_u16mf2_tumu(__VA_ARGS__) -#define vnmsub_vx_u16mf2_m(...) __riscv_vnmsub_vx_u16mf2_tumu(__VA_ARGS__) -#define vnmsub_vv_u16m1_m(...) __riscv_vnmsub_vv_u16m1_tumu(__VA_ARGS__) -#define vnmsub_vx_u16m1_m(...) __riscv_vnmsub_vx_u16m1_tumu(__VA_ARGS__) -#define vnmsub_vv_u16m2_m(...) __riscv_vnmsub_vv_u16m2_tumu(__VA_ARGS__) -#define vnmsub_vx_u16m2_m(...) __riscv_vnmsub_vx_u16m2_tumu(__VA_ARGS__) -#define vnmsub_vv_u16m4_m(...) __riscv_vnmsub_vv_u16m4_tumu(__VA_ARGS__) -#define vnmsub_vx_u16m4_m(...) __riscv_vnmsub_vx_u16m4_tumu(__VA_ARGS__) -#define vnmsub_vv_u16m8_m(...) __riscv_vnmsub_vv_u16m8_tumu(__VA_ARGS__) -#define vnmsub_vx_u16m8_m(...) __riscv_vnmsub_vx_u16m8_tumu(__VA_ARGS__) -#define vnmsub_vv_u32mf2_m(...) __riscv_vnmsub_vv_u32mf2_tumu(__VA_ARGS__) -#define vnmsub_vx_u32mf2_m(...) __riscv_vnmsub_vx_u32mf2_tumu(__VA_ARGS__) -#define vnmsub_vv_u32m1_m(...) __riscv_vnmsub_vv_u32m1_tumu(__VA_ARGS__) -#define vnmsub_vx_u32m1_m(...) __riscv_vnmsub_vx_u32m1_tumu(__VA_ARGS__) -#define vnmsub_vv_u32m2_m(...) __riscv_vnmsub_vv_u32m2_tumu(__VA_ARGS__) -#define vnmsub_vx_u32m2_m(...) __riscv_vnmsub_vx_u32m2_tumu(__VA_ARGS__) -#define vnmsub_vv_u32m4_m(...) __riscv_vnmsub_vv_u32m4_tumu(__VA_ARGS__) -#define vnmsub_vx_u32m4_m(...) __riscv_vnmsub_vx_u32m4_tumu(__VA_ARGS__) -#define vnmsub_vv_u32m8_m(...) __riscv_vnmsub_vv_u32m8_tumu(__VA_ARGS__) -#define vnmsub_vx_u32m8_m(...) __riscv_vnmsub_vx_u32m8_tumu(__VA_ARGS__) -#define vnmsub_vv_u64m1_m(...) __riscv_vnmsub_vv_u64m1_tumu(__VA_ARGS__) -#define vnmsub_vx_u64m1_m(...) __riscv_vnmsub_vx_u64m1_tumu(__VA_ARGS__) -#define vnmsub_vv_u64m2_m(...) __riscv_vnmsub_vv_u64m2_tumu(__VA_ARGS__) -#define vnmsub_vx_u64m2_m(...) __riscv_vnmsub_vx_u64m2_tumu(__VA_ARGS__) -#define vnmsub_vv_u64m4_m(...) __riscv_vnmsub_vv_u64m4_tumu(__VA_ARGS__) -#define vnmsub_vx_u64m4_m(...) __riscv_vnmsub_vx_u64m4_tumu(__VA_ARGS__) -#define vnmsub_vv_u64m8_m(...) __riscv_vnmsub_vv_u64m8_tumu(__VA_ARGS__) -#define vnmsub_vx_u64m8_m(...) __riscv_vnmsub_vx_u64m8_tumu(__VA_ARGS__) -#define vwmacc_vv_i16mf4(...) __riscv_vwmacc_vv_i16mf4_tu(__VA_ARGS__) -#define vwmacc_vx_i16mf4(...) __riscv_vwmacc_vx_i16mf4_tu(__VA_ARGS__) -#define vwmacc_vv_i16mf2(...) __riscv_vwmacc_vv_i16mf2_tu(__VA_ARGS__) -#define vwmacc_vx_i16mf2(...) __riscv_vwmacc_vx_i16mf2_tu(__VA_ARGS__) -#define vwmacc_vv_i16m1(...) __riscv_vwmacc_vv_i16m1_tu(__VA_ARGS__) -#define vwmacc_vx_i16m1(...) __riscv_vwmacc_vx_i16m1_tu(__VA_ARGS__) -#define vwmacc_vv_i16m2(...) __riscv_vwmacc_vv_i16m2_tu(__VA_ARGS__) -#define vwmacc_vx_i16m2(...) __riscv_vwmacc_vx_i16m2_tu(__VA_ARGS__) -#define vwmacc_vv_i16m4(...) __riscv_vwmacc_vv_i16m4_tu(__VA_ARGS__) -#define vwmacc_vx_i16m4(...) __riscv_vwmacc_vx_i16m4_tu(__VA_ARGS__) -#define vwmacc_vv_i16m8(...) __riscv_vwmacc_vv_i16m8_tu(__VA_ARGS__) -#define vwmacc_vx_i16m8(...) __riscv_vwmacc_vx_i16m8_tu(__VA_ARGS__) -#define vwmacc_vv_i32mf2(...) __riscv_vwmacc_vv_i32mf2_tu(__VA_ARGS__) -#define vwmacc_vx_i32mf2(...) __riscv_vwmacc_vx_i32mf2_tu(__VA_ARGS__) -#define vwmacc_vv_i32m1(...) __riscv_vwmacc_vv_i32m1_tu(__VA_ARGS__) -#define vwmacc_vx_i32m1(...) __riscv_vwmacc_vx_i32m1_tu(__VA_ARGS__) -#define vwmacc_vv_i32m2(...) __riscv_vwmacc_vv_i32m2_tu(__VA_ARGS__) -#define vwmacc_vx_i32m2(...) __riscv_vwmacc_vx_i32m2_tu(__VA_ARGS__) -#define vwmacc_vv_i32m4(...) __riscv_vwmacc_vv_i32m4_tu(__VA_ARGS__) -#define vwmacc_vx_i32m4(...) __riscv_vwmacc_vx_i32m4_tu(__VA_ARGS__) -#define vwmacc_vv_i32m8(...) __riscv_vwmacc_vv_i32m8_tu(__VA_ARGS__) -#define vwmacc_vx_i32m8(...) __riscv_vwmacc_vx_i32m8_tu(__VA_ARGS__) -#define vwmacc_vv_i64m1(...) __riscv_vwmacc_vv_i64m1_tu(__VA_ARGS__) -#define vwmacc_vx_i64m1(...) __riscv_vwmacc_vx_i64m1_tu(__VA_ARGS__) -#define vwmacc_vv_i64m2(...) __riscv_vwmacc_vv_i64m2_tu(__VA_ARGS__) -#define vwmacc_vx_i64m2(...) __riscv_vwmacc_vx_i64m2_tu(__VA_ARGS__) -#define vwmacc_vv_i64m4(...) __riscv_vwmacc_vv_i64m4_tu(__VA_ARGS__) -#define vwmacc_vx_i64m4(...) __riscv_vwmacc_vx_i64m4_tu(__VA_ARGS__) -#define vwmacc_vv_i64m8(...) __riscv_vwmacc_vv_i64m8_tu(__VA_ARGS__) -#define vwmacc_vx_i64m8(...) __riscv_vwmacc_vx_i64m8_tu(__VA_ARGS__) -#define vwmaccsu_vv_i16mf4(...) __riscv_vwmaccsu_vv_i16mf4_tu(__VA_ARGS__) -#define vwmaccsu_vx_i16mf4(...) __riscv_vwmaccsu_vx_i16mf4_tu(__VA_ARGS__) -#define vwmaccsu_vv_i16mf2(...) __riscv_vwmaccsu_vv_i16mf2_tu(__VA_ARGS__) -#define vwmaccsu_vx_i16mf2(...) __riscv_vwmaccsu_vx_i16mf2_tu(__VA_ARGS__) -#define vwmaccsu_vv_i16m1(...) __riscv_vwmaccsu_vv_i16m1_tu(__VA_ARGS__) -#define vwmaccsu_vx_i16m1(...) __riscv_vwmaccsu_vx_i16m1_tu(__VA_ARGS__) -#define vwmaccsu_vv_i16m2(...) __riscv_vwmaccsu_vv_i16m2_tu(__VA_ARGS__) -#define vwmaccsu_vx_i16m2(...) __riscv_vwmaccsu_vx_i16m2_tu(__VA_ARGS__) -#define vwmaccsu_vv_i16m4(...) __riscv_vwmaccsu_vv_i16m4_tu(__VA_ARGS__) -#define vwmaccsu_vx_i16m4(...) __riscv_vwmaccsu_vx_i16m4_tu(__VA_ARGS__) -#define vwmaccsu_vv_i16m8(...) __riscv_vwmaccsu_vv_i16m8_tu(__VA_ARGS__) -#define vwmaccsu_vx_i16m8(...) __riscv_vwmaccsu_vx_i16m8_tu(__VA_ARGS__) -#define vwmaccsu_vv_i32mf2(...) __riscv_vwmaccsu_vv_i32mf2_tu(__VA_ARGS__) -#define vwmaccsu_vx_i32mf2(...) __riscv_vwmaccsu_vx_i32mf2_tu(__VA_ARGS__) -#define vwmaccsu_vv_i32m1(...) __riscv_vwmaccsu_vv_i32m1_tu(__VA_ARGS__) -#define vwmaccsu_vx_i32m1(...) __riscv_vwmaccsu_vx_i32m1_tu(__VA_ARGS__) -#define vwmaccsu_vv_i32m2(...) __riscv_vwmaccsu_vv_i32m2_tu(__VA_ARGS__) -#define vwmaccsu_vx_i32m2(...) __riscv_vwmaccsu_vx_i32m2_tu(__VA_ARGS__) -#define vwmaccsu_vv_i32m4(...) __riscv_vwmaccsu_vv_i32m4_tu(__VA_ARGS__) -#define vwmaccsu_vx_i32m4(...) __riscv_vwmaccsu_vx_i32m4_tu(__VA_ARGS__) -#define vwmaccsu_vv_i32m8(...) __riscv_vwmaccsu_vv_i32m8_tu(__VA_ARGS__) -#define vwmaccsu_vx_i32m8(...) __riscv_vwmaccsu_vx_i32m8_tu(__VA_ARGS__) -#define vwmaccsu_vv_i64m1(...) __riscv_vwmaccsu_vv_i64m1_tu(__VA_ARGS__) -#define vwmaccsu_vx_i64m1(...) __riscv_vwmaccsu_vx_i64m1_tu(__VA_ARGS__) -#define vwmaccsu_vv_i64m2(...) __riscv_vwmaccsu_vv_i64m2_tu(__VA_ARGS__) -#define vwmaccsu_vx_i64m2(...) __riscv_vwmaccsu_vx_i64m2_tu(__VA_ARGS__) -#define vwmaccsu_vv_i64m4(...) __riscv_vwmaccsu_vv_i64m4_tu(__VA_ARGS__) -#define vwmaccsu_vx_i64m4(...) __riscv_vwmaccsu_vx_i64m4_tu(__VA_ARGS__) -#define vwmaccsu_vv_i64m8(...) __riscv_vwmaccsu_vv_i64m8_tu(__VA_ARGS__) -#define vwmaccsu_vx_i64m8(...) __riscv_vwmaccsu_vx_i64m8_tu(__VA_ARGS__) -#define vwmaccus_vx_i16mf4(...) __riscv_vwmaccus_vx_i16mf4_tu(__VA_ARGS__) -#define vwmaccus_vx_i16mf2(...) __riscv_vwmaccus_vx_i16mf2_tu(__VA_ARGS__) -#define vwmaccus_vx_i16m1(...) __riscv_vwmaccus_vx_i16m1_tu(__VA_ARGS__) -#define vwmaccus_vx_i16m2(...) __riscv_vwmaccus_vx_i16m2_tu(__VA_ARGS__) -#define vwmaccus_vx_i16m4(...) __riscv_vwmaccus_vx_i16m4_tu(__VA_ARGS__) -#define vwmaccus_vx_i16m8(...) __riscv_vwmaccus_vx_i16m8_tu(__VA_ARGS__) -#define vwmaccus_vx_i32mf2(...) __riscv_vwmaccus_vx_i32mf2_tu(__VA_ARGS__) -#define vwmaccus_vx_i32m1(...) __riscv_vwmaccus_vx_i32m1_tu(__VA_ARGS__) -#define vwmaccus_vx_i32m2(...) __riscv_vwmaccus_vx_i32m2_tu(__VA_ARGS__) -#define vwmaccus_vx_i32m4(...) __riscv_vwmaccus_vx_i32m4_tu(__VA_ARGS__) -#define vwmaccus_vx_i32m8(...) __riscv_vwmaccus_vx_i32m8_tu(__VA_ARGS__) -#define vwmaccus_vx_i64m1(...) __riscv_vwmaccus_vx_i64m1_tu(__VA_ARGS__) -#define vwmaccus_vx_i64m2(...) __riscv_vwmaccus_vx_i64m2_tu(__VA_ARGS__) -#define vwmaccus_vx_i64m4(...) __riscv_vwmaccus_vx_i64m4_tu(__VA_ARGS__) -#define vwmaccus_vx_i64m8(...) __riscv_vwmaccus_vx_i64m8_tu(__VA_ARGS__) -#define vwmaccu_vv_u16mf4(...) __riscv_vwmaccu_vv_u16mf4_tu(__VA_ARGS__) -#define vwmaccu_vx_u16mf4(...) __riscv_vwmaccu_vx_u16mf4_tu(__VA_ARGS__) -#define vwmaccu_vv_u16mf2(...) __riscv_vwmaccu_vv_u16mf2_tu(__VA_ARGS__) -#define vwmaccu_vx_u16mf2(...) __riscv_vwmaccu_vx_u16mf2_tu(__VA_ARGS__) -#define vwmaccu_vv_u16m1(...) __riscv_vwmaccu_vv_u16m1_tu(__VA_ARGS__) -#define vwmaccu_vx_u16m1(...) __riscv_vwmaccu_vx_u16m1_tu(__VA_ARGS__) -#define vwmaccu_vv_u16m2(...) __riscv_vwmaccu_vv_u16m2_tu(__VA_ARGS__) -#define vwmaccu_vx_u16m2(...) __riscv_vwmaccu_vx_u16m2_tu(__VA_ARGS__) -#define vwmaccu_vv_u16m4(...) __riscv_vwmaccu_vv_u16m4_tu(__VA_ARGS__) -#define vwmaccu_vx_u16m4(...) __riscv_vwmaccu_vx_u16m4_tu(__VA_ARGS__) -#define vwmaccu_vv_u16m8(...) __riscv_vwmaccu_vv_u16m8_tu(__VA_ARGS__) -#define vwmaccu_vx_u16m8(...) __riscv_vwmaccu_vx_u16m8_tu(__VA_ARGS__) -#define vwmaccu_vv_u32mf2(...) __riscv_vwmaccu_vv_u32mf2_tu(__VA_ARGS__) -#define vwmaccu_vx_u32mf2(...) __riscv_vwmaccu_vx_u32mf2_tu(__VA_ARGS__) -#define vwmaccu_vv_u32m1(...) __riscv_vwmaccu_vv_u32m1_tu(__VA_ARGS__) -#define vwmaccu_vx_u32m1(...) __riscv_vwmaccu_vx_u32m1_tu(__VA_ARGS__) -#define vwmaccu_vv_u32m2(...) __riscv_vwmaccu_vv_u32m2_tu(__VA_ARGS__) -#define vwmaccu_vx_u32m2(...) __riscv_vwmaccu_vx_u32m2_tu(__VA_ARGS__) -#define vwmaccu_vv_u32m4(...) __riscv_vwmaccu_vv_u32m4_tu(__VA_ARGS__) -#define vwmaccu_vx_u32m4(...) __riscv_vwmaccu_vx_u32m4_tu(__VA_ARGS__) -#define vwmaccu_vv_u32m8(...) __riscv_vwmaccu_vv_u32m8_tu(__VA_ARGS__) -#define vwmaccu_vx_u32m8(...) __riscv_vwmaccu_vx_u32m8_tu(__VA_ARGS__) -#define vwmaccu_vv_u64m1(...) __riscv_vwmaccu_vv_u64m1_tu(__VA_ARGS__) -#define vwmaccu_vx_u64m1(...) __riscv_vwmaccu_vx_u64m1_tu(__VA_ARGS__) -#define vwmaccu_vv_u64m2(...) __riscv_vwmaccu_vv_u64m2_tu(__VA_ARGS__) -#define vwmaccu_vx_u64m2(...) __riscv_vwmaccu_vx_u64m2_tu(__VA_ARGS__) -#define vwmaccu_vv_u64m4(...) __riscv_vwmaccu_vv_u64m4_tu(__VA_ARGS__) -#define vwmaccu_vx_u64m4(...) __riscv_vwmaccu_vx_u64m4_tu(__VA_ARGS__) -#define vwmaccu_vv_u64m8(...) __riscv_vwmaccu_vv_u64m8_tu(__VA_ARGS__) -#define vwmaccu_vx_u64m8(...) __riscv_vwmaccu_vx_u64m8_tu(__VA_ARGS__) -// masked functions -#define vwmacc_vv_i16mf4_m(...) __riscv_vwmacc_vv_i16mf4_tumu(__VA_ARGS__) -#define vwmacc_vx_i16mf4_m(...) __riscv_vwmacc_vx_i16mf4_tumu(__VA_ARGS__) -#define vwmacc_vv_i16mf2_m(...) __riscv_vwmacc_vv_i16mf2_tumu(__VA_ARGS__) -#define vwmacc_vx_i16mf2_m(...) __riscv_vwmacc_vx_i16mf2_tumu(__VA_ARGS__) -#define vwmacc_vv_i16m1_m(...) __riscv_vwmacc_vv_i16m1_tumu(__VA_ARGS__) -#define vwmacc_vx_i16m1_m(...) __riscv_vwmacc_vx_i16m1_tumu(__VA_ARGS__) -#define vwmacc_vv_i16m2_m(...) __riscv_vwmacc_vv_i16m2_tumu(__VA_ARGS__) -#define vwmacc_vx_i16m2_m(...) __riscv_vwmacc_vx_i16m2_tumu(__VA_ARGS__) -#define vwmacc_vv_i16m4_m(...) __riscv_vwmacc_vv_i16m4_tumu(__VA_ARGS__) -#define vwmacc_vx_i16m4_m(...) __riscv_vwmacc_vx_i16m4_tumu(__VA_ARGS__) -#define vwmacc_vv_i16m8_m(...) __riscv_vwmacc_vv_i16m8_tumu(__VA_ARGS__) -#define vwmacc_vx_i16m8_m(...) __riscv_vwmacc_vx_i16m8_tumu(__VA_ARGS__) -#define vwmacc_vv_i32mf2_m(...) __riscv_vwmacc_vv_i32mf2_tumu(__VA_ARGS__) -#define vwmacc_vx_i32mf2_m(...) __riscv_vwmacc_vx_i32mf2_tumu(__VA_ARGS__) -#define vwmacc_vv_i32m1_m(...) __riscv_vwmacc_vv_i32m1_tumu(__VA_ARGS__) -#define vwmacc_vx_i32m1_m(...) __riscv_vwmacc_vx_i32m1_tumu(__VA_ARGS__) -#define vwmacc_vv_i32m2_m(...) __riscv_vwmacc_vv_i32m2_tumu(__VA_ARGS__) -#define vwmacc_vx_i32m2_m(...) __riscv_vwmacc_vx_i32m2_tumu(__VA_ARGS__) -#define vwmacc_vv_i32m4_m(...) __riscv_vwmacc_vv_i32m4_tumu(__VA_ARGS__) -#define vwmacc_vx_i32m4_m(...) __riscv_vwmacc_vx_i32m4_tumu(__VA_ARGS__) -#define vwmacc_vv_i32m8_m(...) __riscv_vwmacc_vv_i32m8_tumu(__VA_ARGS__) -#define vwmacc_vx_i32m8_m(...) __riscv_vwmacc_vx_i32m8_tumu(__VA_ARGS__) -#define vwmacc_vv_i64m1_m(...) __riscv_vwmacc_vv_i64m1_tumu(__VA_ARGS__) -#define vwmacc_vx_i64m1_m(...) __riscv_vwmacc_vx_i64m1_tumu(__VA_ARGS__) -#define vwmacc_vv_i64m2_m(...) __riscv_vwmacc_vv_i64m2_tumu(__VA_ARGS__) -#define vwmacc_vx_i64m2_m(...) __riscv_vwmacc_vx_i64m2_tumu(__VA_ARGS__) -#define vwmacc_vv_i64m4_m(...) __riscv_vwmacc_vv_i64m4_tumu(__VA_ARGS__) -#define vwmacc_vx_i64m4_m(...) __riscv_vwmacc_vx_i64m4_tumu(__VA_ARGS__) -#define vwmacc_vv_i64m8_m(...) __riscv_vwmacc_vv_i64m8_tumu(__VA_ARGS__) -#define vwmacc_vx_i64m8_m(...) __riscv_vwmacc_vx_i64m8_tumu(__VA_ARGS__) -#define vwmaccsu_vv_i16mf4_m(...) __riscv_vwmaccsu_vv_i16mf4_tumu(__VA_ARGS__) -#define vwmaccsu_vx_i16mf4_m(...) __riscv_vwmaccsu_vx_i16mf4_tumu(__VA_ARGS__) -#define vwmaccsu_vv_i16mf2_m(...) __riscv_vwmaccsu_vv_i16mf2_tumu(__VA_ARGS__) -#define vwmaccsu_vx_i16mf2_m(...) __riscv_vwmaccsu_vx_i16mf2_tumu(__VA_ARGS__) -#define vwmaccsu_vv_i16m1_m(...) __riscv_vwmaccsu_vv_i16m1_tumu(__VA_ARGS__) -#define vwmaccsu_vx_i16m1_m(...) __riscv_vwmaccsu_vx_i16m1_tumu(__VA_ARGS__) -#define vwmaccsu_vv_i16m2_m(...) __riscv_vwmaccsu_vv_i16m2_tumu(__VA_ARGS__) -#define vwmaccsu_vx_i16m2_m(...) __riscv_vwmaccsu_vx_i16m2_tumu(__VA_ARGS__) -#define vwmaccsu_vv_i16m4_m(...) __riscv_vwmaccsu_vv_i16m4_tumu(__VA_ARGS__) -#define vwmaccsu_vx_i16m4_m(...) __riscv_vwmaccsu_vx_i16m4_tumu(__VA_ARGS__) -#define vwmaccsu_vv_i16m8_m(...) __riscv_vwmaccsu_vv_i16m8_tumu(__VA_ARGS__) -#define vwmaccsu_vx_i16m8_m(...) __riscv_vwmaccsu_vx_i16m8_tumu(__VA_ARGS__) -#define vwmaccsu_vv_i32mf2_m(...) __riscv_vwmaccsu_vv_i32mf2_tumu(__VA_ARGS__) -#define vwmaccsu_vx_i32mf2_m(...) __riscv_vwmaccsu_vx_i32mf2_tumu(__VA_ARGS__) -#define vwmaccsu_vv_i32m1_m(...) __riscv_vwmaccsu_vv_i32m1_tumu(__VA_ARGS__) -#define vwmaccsu_vx_i32m1_m(...) __riscv_vwmaccsu_vx_i32m1_tumu(__VA_ARGS__) -#define vwmaccsu_vv_i32m2_m(...) __riscv_vwmaccsu_vv_i32m2_tumu(__VA_ARGS__) -#define vwmaccsu_vx_i32m2_m(...) __riscv_vwmaccsu_vx_i32m2_tumu(__VA_ARGS__) -#define vwmaccsu_vv_i32m4_m(...) __riscv_vwmaccsu_vv_i32m4_tumu(__VA_ARGS__) -#define vwmaccsu_vx_i32m4_m(...) __riscv_vwmaccsu_vx_i32m4_tumu(__VA_ARGS__) -#define vwmaccsu_vv_i32m8_m(...) __riscv_vwmaccsu_vv_i32m8_tumu(__VA_ARGS__) -#define vwmaccsu_vx_i32m8_m(...) __riscv_vwmaccsu_vx_i32m8_tumu(__VA_ARGS__) -#define vwmaccsu_vv_i64m1_m(...) __riscv_vwmaccsu_vv_i64m1_tumu(__VA_ARGS__) -#define vwmaccsu_vx_i64m1_m(...) __riscv_vwmaccsu_vx_i64m1_tumu(__VA_ARGS__) -#define vwmaccsu_vv_i64m2_m(...) __riscv_vwmaccsu_vv_i64m2_tumu(__VA_ARGS__) -#define vwmaccsu_vx_i64m2_m(...) __riscv_vwmaccsu_vx_i64m2_tumu(__VA_ARGS__) -#define vwmaccsu_vv_i64m4_m(...) __riscv_vwmaccsu_vv_i64m4_tumu(__VA_ARGS__) -#define vwmaccsu_vx_i64m4_m(...) __riscv_vwmaccsu_vx_i64m4_tumu(__VA_ARGS__) -#define vwmaccsu_vv_i64m8_m(...) __riscv_vwmaccsu_vv_i64m8_tumu(__VA_ARGS__) -#define vwmaccsu_vx_i64m8_m(...) __riscv_vwmaccsu_vx_i64m8_tumu(__VA_ARGS__) -#define vwmaccus_vx_i16mf4_m(...) __riscv_vwmaccus_vx_i16mf4_tumu(__VA_ARGS__) -#define vwmaccus_vx_i16mf2_m(...) __riscv_vwmaccus_vx_i16mf2_tumu(__VA_ARGS__) -#define vwmaccus_vx_i16m1_m(...) __riscv_vwmaccus_vx_i16m1_tumu(__VA_ARGS__) -#define vwmaccus_vx_i16m2_m(...) __riscv_vwmaccus_vx_i16m2_tumu(__VA_ARGS__) -#define vwmaccus_vx_i16m4_m(...) __riscv_vwmaccus_vx_i16m4_tumu(__VA_ARGS__) -#define vwmaccus_vx_i16m8_m(...) __riscv_vwmaccus_vx_i16m8_tumu(__VA_ARGS__) -#define vwmaccus_vx_i32mf2_m(...) __riscv_vwmaccus_vx_i32mf2_tumu(__VA_ARGS__) -#define vwmaccus_vx_i32m1_m(...) __riscv_vwmaccus_vx_i32m1_tumu(__VA_ARGS__) -#define vwmaccus_vx_i32m2_m(...) __riscv_vwmaccus_vx_i32m2_tumu(__VA_ARGS__) -#define vwmaccus_vx_i32m4_m(...) __riscv_vwmaccus_vx_i32m4_tumu(__VA_ARGS__) -#define vwmaccus_vx_i32m8_m(...) __riscv_vwmaccus_vx_i32m8_tumu(__VA_ARGS__) -#define vwmaccus_vx_i64m1_m(...) __riscv_vwmaccus_vx_i64m1_tumu(__VA_ARGS__) -#define vwmaccus_vx_i64m2_m(...) __riscv_vwmaccus_vx_i64m2_tumu(__VA_ARGS__) -#define vwmaccus_vx_i64m4_m(...) __riscv_vwmaccus_vx_i64m4_tumu(__VA_ARGS__) -#define vwmaccus_vx_i64m8_m(...) __riscv_vwmaccus_vx_i64m8_tumu(__VA_ARGS__) -#define vwmaccu_vv_u16mf4_m(...) __riscv_vwmaccu_vv_u16mf4_tumu(__VA_ARGS__) -#define vwmaccu_vx_u16mf4_m(...) __riscv_vwmaccu_vx_u16mf4_tumu(__VA_ARGS__) -#define vwmaccu_vv_u16mf2_m(...) __riscv_vwmaccu_vv_u16mf2_tumu(__VA_ARGS__) -#define vwmaccu_vx_u16mf2_m(...) __riscv_vwmaccu_vx_u16mf2_tumu(__VA_ARGS__) -#define vwmaccu_vv_u16m1_m(...) __riscv_vwmaccu_vv_u16m1_tumu(__VA_ARGS__) -#define vwmaccu_vx_u16m1_m(...) __riscv_vwmaccu_vx_u16m1_tumu(__VA_ARGS__) -#define vwmaccu_vv_u16m2_m(...) __riscv_vwmaccu_vv_u16m2_tumu(__VA_ARGS__) -#define vwmaccu_vx_u16m2_m(...) __riscv_vwmaccu_vx_u16m2_tumu(__VA_ARGS__) -#define vwmaccu_vv_u16m4_m(...) __riscv_vwmaccu_vv_u16m4_tumu(__VA_ARGS__) -#define vwmaccu_vx_u16m4_m(...) __riscv_vwmaccu_vx_u16m4_tumu(__VA_ARGS__) -#define vwmaccu_vv_u16m8_m(...) __riscv_vwmaccu_vv_u16m8_tumu(__VA_ARGS__) -#define vwmaccu_vx_u16m8_m(...) __riscv_vwmaccu_vx_u16m8_tumu(__VA_ARGS__) -#define vwmaccu_vv_u32mf2_m(...) __riscv_vwmaccu_vv_u32mf2_tumu(__VA_ARGS__) -#define vwmaccu_vx_u32mf2_m(...) __riscv_vwmaccu_vx_u32mf2_tumu(__VA_ARGS__) -#define vwmaccu_vv_u32m1_m(...) __riscv_vwmaccu_vv_u32m1_tumu(__VA_ARGS__) -#define vwmaccu_vx_u32m1_m(...) __riscv_vwmaccu_vx_u32m1_tumu(__VA_ARGS__) -#define vwmaccu_vv_u32m2_m(...) __riscv_vwmaccu_vv_u32m2_tumu(__VA_ARGS__) -#define vwmaccu_vx_u32m2_m(...) __riscv_vwmaccu_vx_u32m2_tumu(__VA_ARGS__) -#define vwmaccu_vv_u32m4_m(...) __riscv_vwmaccu_vv_u32m4_tumu(__VA_ARGS__) -#define vwmaccu_vx_u32m4_m(...) __riscv_vwmaccu_vx_u32m4_tumu(__VA_ARGS__) -#define vwmaccu_vv_u32m8_m(...) __riscv_vwmaccu_vv_u32m8_tumu(__VA_ARGS__) -#define vwmaccu_vx_u32m8_m(...) __riscv_vwmaccu_vx_u32m8_tumu(__VA_ARGS__) -#define vwmaccu_vv_u64m1_m(...) __riscv_vwmaccu_vv_u64m1_tumu(__VA_ARGS__) -#define vwmaccu_vx_u64m1_m(...) __riscv_vwmaccu_vx_u64m1_tumu(__VA_ARGS__) -#define vwmaccu_vv_u64m2_m(...) __riscv_vwmaccu_vv_u64m2_tumu(__VA_ARGS__) -#define vwmaccu_vx_u64m2_m(...) __riscv_vwmaccu_vx_u64m2_tumu(__VA_ARGS__) -#define vwmaccu_vv_u64m4_m(...) __riscv_vwmaccu_vv_u64m4_tumu(__VA_ARGS__) -#define vwmaccu_vx_u64m4_m(...) __riscv_vwmaccu_vx_u64m4_tumu(__VA_ARGS__) -#define vwmaccu_vv_u64m8_m(...) __riscv_vwmaccu_vv_u64m8_tumu(__VA_ARGS__) -#define vwmaccu_vx_u64m8_m(...) __riscv_vwmaccu_vx_u64m8_tumu(__VA_ARGS__) -#define vmerge_vvm_i8mf8(mask, op1, op2, vl) __riscv_vmerge_vvm_i8mf8((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i8mf8(mask, op1, op2, vl) __riscv_vmerge_vxm_i8mf8((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i8mf4(mask, op1, op2, vl) __riscv_vmerge_vvm_i8mf4((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i8mf4(mask, op1, op2, vl) __riscv_vmerge_vxm_i8mf4((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i8mf2(mask, op1, op2, vl) __riscv_vmerge_vvm_i8mf2((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i8mf2(mask, op1, op2, vl) __riscv_vmerge_vxm_i8mf2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i8m1(mask, op1, op2, vl) __riscv_vmerge_vvm_i8m1((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i8m1(mask, op1, op2, vl) __riscv_vmerge_vxm_i8m1((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i8m2(mask, op1, op2, vl) __riscv_vmerge_vvm_i8m2((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i8m2(mask, op1, op2, vl) __riscv_vmerge_vxm_i8m2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i8m4(mask, op1, op2, vl) __riscv_vmerge_vvm_i8m4((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i8m4(mask, op1, op2, vl) __riscv_vmerge_vxm_i8m4((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i8m8(mask, op1, op2, vl) __riscv_vmerge_vvm_i8m8((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i8m8(mask, op1, op2, vl) __riscv_vmerge_vxm_i8m8((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i16mf4(mask, op1, op2, vl) __riscv_vmerge_vvm_i16mf4((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i16mf4(mask, op1, op2, vl) __riscv_vmerge_vxm_i16mf4((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i16mf2(mask, op1, op2, vl) __riscv_vmerge_vvm_i16mf2((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i16mf2(mask, op1, op2, vl) __riscv_vmerge_vxm_i16mf2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i16m1(mask, op1, op2, vl) __riscv_vmerge_vvm_i16m1((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i16m1(mask, op1, op2, vl) __riscv_vmerge_vxm_i16m1((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i16m2(mask, op1, op2, vl) __riscv_vmerge_vvm_i16m2((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i16m2(mask, op1, op2, vl) __riscv_vmerge_vxm_i16m2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i16m4(mask, op1, op2, vl) __riscv_vmerge_vvm_i16m4((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i16m4(mask, op1, op2, vl) __riscv_vmerge_vxm_i16m4((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i16m8(mask, op1, op2, vl) __riscv_vmerge_vvm_i16m8((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i16m8(mask, op1, op2, vl) __riscv_vmerge_vxm_i16m8((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i32mf2(mask, op1, op2, vl) __riscv_vmerge_vvm_i32mf2((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i32mf2(mask, op1, op2, vl) __riscv_vmerge_vxm_i32mf2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i32m1(mask, op1, op2, vl) __riscv_vmerge_vvm_i32m1((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i32m1(mask, op1, op2, vl) __riscv_vmerge_vxm_i32m1((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i32m2(mask, op1, op2, vl) __riscv_vmerge_vvm_i32m2((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i32m2(mask, op1, op2, vl) __riscv_vmerge_vxm_i32m2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i32m4(mask, op1, op2, vl) __riscv_vmerge_vvm_i32m4((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i32m4(mask, op1, op2, vl) __riscv_vmerge_vxm_i32m4((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i32m8(mask, op1, op2, vl) __riscv_vmerge_vvm_i32m8((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i32m8(mask, op1, op2, vl) __riscv_vmerge_vxm_i32m8((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i64m1(mask, op1, op2, vl) __riscv_vmerge_vvm_i64m1((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i64m1(mask, op1, op2, vl) __riscv_vmerge_vxm_i64m1((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i64m2(mask, op1, op2, vl) __riscv_vmerge_vvm_i64m2((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i64m2(mask, op1, op2, vl) __riscv_vmerge_vxm_i64m2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i64m4(mask, op1, op2, vl) __riscv_vmerge_vvm_i64m4((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i64m4(mask, op1, op2, vl) __riscv_vmerge_vxm_i64m4((op1), (op2), (mask), (vl)) -#define vmerge_vvm_i64m8(mask, op1, op2, vl) __riscv_vmerge_vvm_i64m8((op1), (op2), (mask), (vl)) -#define vmerge_vxm_i64m8(mask, op1, op2, vl) __riscv_vmerge_vxm_i64m8((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u8mf8(mask, op1, op2, vl) __riscv_vmerge_vvm_u8mf8((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u8mf8(mask, op1, op2, vl) __riscv_vmerge_vxm_u8mf8((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u8mf4(mask, op1, op2, vl) __riscv_vmerge_vvm_u8mf4((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u8mf4(mask, op1, op2, vl) __riscv_vmerge_vxm_u8mf4((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u8mf2(mask, op1, op2, vl) __riscv_vmerge_vvm_u8mf2((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u8mf2(mask, op1, op2, vl) __riscv_vmerge_vxm_u8mf2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u8m1(mask, op1, op2, vl) __riscv_vmerge_vvm_u8m1((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u8m1(mask, op1, op2, vl) __riscv_vmerge_vxm_u8m1((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u8m2(mask, op1, op2, vl) __riscv_vmerge_vvm_u8m2((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u8m2(mask, op1, op2, vl) __riscv_vmerge_vxm_u8m2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u8m4(mask, op1, op2, vl) __riscv_vmerge_vvm_u8m4((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u8m4(mask, op1, op2, vl) __riscv_vmerge_vxm_u8m4((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u8m8(mask, op1, op2, vl) __riscv_vmerge_vvm_u8m8((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u8m8(mask, op1, op2, vl) __riscv_vmerge_vxm_u8m8((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u16mf4(mask, op1, op2, vl) __riscv_vmerge_vvm_u16mf4((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u16mf4(mask, op1, op2, vl) __riscv_vmerge_vxm_u16mf4((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u16mf2(mask, op1, op2, vl) __riscv_vmerge_vvm_u16mf2((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u16mf2(mask, op1, op2, vl) __riscv_vmerge_vxm_u16mf2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u16m1(mask, op1, op2, vl) __riscv_vmerge_vvm_u16m1((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u16m1(mask, op1, op2, vl) __riscv_vmerge_vxm_u16m1((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u16m2(mask, op1, op2, vl) __riscv_vmerge_vvm_u16m2((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u16m2(mask, op1, op2, vl) __riscv_vmerge_vxm_u16m2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u16m4(mask, op1, op2, vl) __riscv_vmerge_vvm_u16m4((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u16m4(mask, op1, op2, vl) __riscv_vmerge_vxm_u16m4((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u16m8(mask, op1, op2, vl) __riscv_vmerge_vvm_u16m8((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u16m8(mask, op1, op2, vl) __riscv_vmerge_vxm_u16m8((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u32mf2(mask, op1, op2, vl) __riscv_vmerge_vvm_u32mf2((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u32mf2(mask, op1, op2, vl) __riscv_vmerge_vxm_u32mf2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u32m1(mask, op1, op2, vl) __riscv_vmerge_vvm_u32m1((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u32m1(mask, op1, op2, vl) __riscv_vmerge_vxm_u32m1((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u32m2(mask, op1, op2, vl) __riscv_vmerge_vvm_u32m2((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u32m2(mask, op1, op2, vl) __riscv_vmerge_vxm_u32m2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u32m4(mask, op1, op2, vl) __riscv_vmerge_vvm_u32m4((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u32m4(mask, op1, op2, vl) __riscv_vmerge_vxm_u32m4((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u32m8(mask, op1, op2, vl) __riscv_vmerge_vvm_u32m8((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u32m8(mask, op1, op2, vl) __riscv_vmerge_vxm_u32m8((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u64m1(mask, op1, op2, vl) __riscv_vmerge_vvm_u64m1((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u64m1(mask, op1, op2, vl) __riscv_vmerge_vxm_u64m1((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u64m2(mask, op1, op2, vl) __riscv_vmerge_vvm_u64m2((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u64m2(mask, op1, op2, vl) __riscv_vmerge_vxm_u64m2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u64m4(mask, op1, op2, vl) __riscv_vmerge_vvm_u64m4((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u64m4(mask, op1, op2, vl) __riscv_vmerge_vxm_u64m4((op1), (op2), (mask), (vl)) -#define vmerge_vvm_u64m8(mask, op1, op2, vl) __riscv_vmerge_vvm_u64m8((op1), (op2), (mask), (vl)) -#define vmerge_vxm_u64m8(mask, op1, op2, vl) __riscv_vmerge_vxm_u64m8((op1), (op2), (mask), (vl)) -#define vmv_v_v_i8mf8(...) __riscv_vmv_v_v_i8mf8(__VA_ARGS__) -#define vmv_v_x_i8mf8(...) __riscv_vmv_v_x_i8mf8(__VA_ARGS__) -#define vmv_v_v_i8mf4(...) __riscv_vmv_v_v_i8mf4(__VA_ARGS__) -#define vmv_v_x_i8mf4(...) __riscv_vmv_v_x_i8mf4(__VA_ARGS__) -#define vmv_v_v_i8mf2(...) __riscv_vmv_v_v_i8mf2(__VA_ARGS__) -#define vmv_v_x_i8mf2(...) __riscv_vmv_v_x_i8mf2(__VA_ARGS__) -#define vmv_v_v_i8m1(...) __riscv_vmv_v_v_i8m1(__VA_ARGS__) -#define vmv_v_x_i8m1(...) __riscv_vmv_v_x_i8m1(__VA_ARGS__) -#define vmv_v_v_i8m2(...) __riscv_vmv_v_v_i8m2(__VA_ARGS__) -#define vmv_v_x_i8m2(...) __riscv_vmv_v_x_i8m2(__VA_ARGS__) -#define vmv_v_v_i8m4(...) __riscv_vmv_v_v_i8m4(__VA_ARGS__) -#define vmv_v_x_i8m4(...) __riscv_vmv_v_x_i8m4(__VA_ARGS__) -#define vmv_v_v_i8m8(...) __riscv_vmv_v_v_i8m8(__VA_ARGS__) -#define vmv_v_x_i8m8(...) __riscv_vmv_v_x_i8m8(__VA_ARGS__) -#define vmv_v_v_i16mf4(...) __riscv_vmv_v_v_i16mf4(__VA_ARGS__) -#define vmv_v_x_i16mf4(...) __riscv_vmv_v_x_i16mf4(__VA_ARGS__) -#define vmv_v_v_i16mf2(...) __riscv_vmv_v_v_i16mf2(__VA_ARGS__) -#define vmv_v_x_i16mf2(...) __riscv_vmv_v_x_i16mf2(__VA_ARGS__) -#define vmv_v_v_i16m1(...) __riscv_vmv_v_v_i16m1(__VA_ARGS__) -#define vmv_v_x_i16m1(...) __riscv_vmv_v_x_i16m1(__VA_ARGS__) -#define vmv_v_v_i16m2(...) __riscv_vmv_v_v_i16m2(__VA_ARGS__) -#define vmv_v_x_i16m2(...) __riscv_vmv_v_x_i16m2(__VA_ARGS__) -#define vmv_v_v_i16m4(...) __riscv_vmv_v_v_i16m4(__VA_ARGS__) -#define vmv_v_x_i16m4(...) __riscv_vmv_v_x_i16m4(__VA_ARGS__) -#define vmv_v_v_i16m8(...) __riscv_vmv_v_v_i16m8(__VA_ARGS__) -#define vmv_v_x_i16m8(...) __riscv_vmv_v_x_i16m8(__VA_ARGS__) -#define vmv_v_v_i32mf2(...) __riscv_vmv_v_v_i32mf2(__VA_ARGS__) -#define vmv_v_x_i32mf2(...) __riscv_vmv_v_x_i32mf2(__VA_ARGS__) -#define vmv_v_v_i32m1(...) __riscv_vmv_v_v_i32m1(__VA_ARGS__) -#define vmv_v_x_i32m1(...) __riscv_vmv_v_x_i32m1(__VA_ARGS__) -#define vmv_v_v_i32m2(...) __riscv_vmv_v_v_i32m2(__VA_ARGS__) -#define vmv_v_x_i32m2(...) __riscv_vmv_v_x_i32m2(__VA_ARGS__) -#define vmv_v_v_i32m4(...) __riscv_vmv_v_v_i32m4(__VA_ARGS__) -#define vmv_v_x_i32m4(...) __riscv_vmv_v_x_i32m4(__VA_ARGS__) -#define vmv_v_v_i32m8(...) __riscv_vmv_v_v_i32m8(__VA_ARGS__) -#define vmv_v_x_i32m8(...) __riscv_vmv_v_x_i32m8(__VA_ARGS__) -#define vmv_v_v_i64m1(...) __riscv_vmv_v_v_i64m1(__VA_ARGS__) -#define vmv_v_x_i64m1(...) __riscv_vmv_v_x_i64m1(__VA_ARGS__) -#define vmv_v_v_i64m2(...) __riscv_vmv_v_v_i64m2(__VA_ARGS__) -#define vmv_v_x_i64m2(...) __riscv_vmv_v_x_i64m2(__VA_ARGS__) -#define vmv_v_v_i64m4(...) __riscv_vmv_v_v_i64m4(__VA_ARGS__) -#define vmv_v_x_i64m4(...) __riscv_vmv_v_x_i64m4(__VA_ARGS__) -#define vmv_v_v_i64m8(...) __riscv_vmv_v_v_i64m8(__VA_ARGS__) -#define vmv_v_x_i64m8(...) __riscv_vmv_v_x_i64m8(__VA_ARGS__) -#define vmv_v_v_u8mf8(...) __riscv_vmv_v_v_u8mf8(__VA_ARGS__) -#define vmv_v_x_u8mf8(...) __riscv_vmv_v_x_u8mf8(__VA_ARGS__) -#define vmv_v_v_u8mf4(...) __riscv_vmv_v_v_u8mf4(__VA_ARGS__) -#define vmv_v_x_u8mf4(...) __riscv_vmv_v_x_u8mf4(__VA_ARGS__) -#define vmv_v_v_u8mf2(...) __riscv_vmv_v_v_u8mf2(__VA_ARGS__) -#define vmv_v_x_u8mf2(...) __riscv_vmv_v_x_u8mf2(__VA_ARGS__) -#define vmv_v_v_u8m1(...) __riscv_vmv_v_v_u8m1(__VA_ARGS__) -#define vmv_v_x_u8m1(...) __riscv_vmv_v_x_u8m1(__VA_ARGS__) -#define vmv_v_v_u8m2(...) __riscv_vmv_v_v_u8m2(__VA_ARGS__) -#define vmv_v_x_u8m2(...) __riscv_vmv_v_x_u8m2(__VA_ARGS__) -#define vmv_v_v_u8m4(...) __riscv_vmv_v_v_u8m4(__VA_ARGS__) -#define vmv_v_x_u8m4(...) __riscv_vmv_v_x_u8m4(__VA_ARGS__) -#define vmv_v_v_u8m8(...) __riscv_vmv_v_v_u8m8(__VA_ARGS__) -#define vmv_v_x_u8m8(...) __riscv_vmv_v_x_u8m8(__VA_ARGS__) -#define vmv_v_v_u16mf4(...) __riscv_vmv_v_v_u16mf4(__VA_ARGS__) -#define vmv_v_x_u16mf4(...) __riscv_vmv_v_x_u16mf4(__VA_ARGS__) -#define vmv_v_v_u16mf2(...) __riscv_vmv_v_v_u16mf2(__VA_ARGS__) -#define vmv_v_x_u16mf2(...) __riscv_vmv_v_x_u16mf2(__VA_ARGS__) -#define vmv_v_v_u16m1(...) __riscv_vmv_v_v_u16m1(__VA_ARGS__) -#define vmv_v_x_u16m1(...) __riscv_vmv_v_x_u16m1(__VA_ARGS__) -#define vmv_v_v_u16m2(...) __riscv_vmv_v_v_u16m2(__VA_ARGS__) -#define vmv_v_x_u16m2(...) __riscv_vmv_v_x_u16m2(__VA_ARGS__) -#define vmv_v_v_u16m4(...) __riscv_vmv_v_v_u16m4(__VA_ARGS__) -#define vmv_v_x_u16m4(...) __riscv_vmv_v_x_u16m4(__VA_ARGS__) -#define vmv_v_v_u16m8(...) __riscv_vmv_v_v_u16m8(__VA_ARGS__) -#define vmv_v_x_u16m8(...) __riscv_vmv_v_x_u16m8(__VA_ARGS__) -#define vmv_v_v_u32mf2(...) __riscv_vmv_v_v_u32mf2(__VA_ARGS__) -#define vmv_v_x_u32mf2(...) __riscv_vmv_v_x_u32mf2(__VA_ARGS__) -#define vmv_v_v_u32m1(...) __riscv_vmv_v_v_u32m1(__VA_ARGS__) -#define vmv_v_x_u32m1(...) __riscv_vmv_v_x_u32m1(__VA_ARGS__) -#define vmv_v_v_u32m2(...) __riscv_vmv_v_v_u32m2(__VA_ARGS__) -#define vmv_v_x_u32m2(...) __riscv_vmv_v_x_u32m2(__VA_ARGS__) -#define vmv_v_v_u32m4(...) __riscv_vmv_v_v_u32m4(__VA_ARGS__) -#define vmv_v_x_u32m4(...) __riscv_vmv_v_x_u32m4(__VA_ARGS__) -#define vmv_v_v_u32m8(...) __riscv_vmv_v_v_u32m8(__VA_ARGS__) -#define vmv_v_x_u32m8(...) __riscv_vmv_v_x_u32m8(__VA_ARGS__) -#define vmv_v_v_u64m1(...) __riscv_vmv_v_v_u64m1(__VA_ARGS__) -#define vmv_v_x_u64m1(...) __riscv_vmv_v_x_u64m1(__VA_ARGS__) -#define vmv_v_v_u64m2(...) __riscv_vmv_v_v_u64m2(__VA_ARGS__) -#define vmv_v_x_u64m2(...) __riscv_vmv_v_x_u64m2(__VA_ARGS__) -#define vmv_v_v_u64m4(...) __riscv_vmv_v_v_u64m4(__VA_ARGS__) -#define vmv_v_x_u64m4(...) __riscv_vmv_v_x_u64m4(__VA_ARGS__) -#define vmv_v_v_u64m8(...) __riscv_vmv_v_v_u64m8(__VA_ARGS__) -#define vmv_v_x_u64m8(...) __riscv_vmv_v_x_u64m8(__VA_ARGS__) -#define vsadd_vv_i8mf8(...) __riscv_vsadd_vv_i8mf8(__VA_ARGS__) -#define vsadd_vx_i8mf8(...) __riscv_vsadd_vx_i8mf8(__VA_ARGS__) -#define vsadd_vv_i8mf4(...) __riscv_vsadd_vv_i8mf4(__VA_ARGS__) -#define vsadd_vx_i8mf4(...) __riscv_vsadd_vx_i8mf4(__VA_ARGS__) -#define vsadd_vv_i8mf2(...) __riscv_vsadd_vv_i8mf2(__VA_ARGS__) -#define vsadd_vx_i8mf2(...) __riscv_vsadd_vx_i8mf2(__VA_ARGS__) -#define vsadd_vv_i8m1(...) __riscv_vsadd_vv_i8m1(__VA_ARGS__) -#define vsadd_vx_i8m1(...) __riscv_vsadd_vx_i8m1(__VA_ARGS__) -#define vsadd_vv_i8m2(...) __riscv_vsadd_vv_i8m2(__VA_ARGS__) -#define vsadd_vx_i8m2(...) __riscv_vsadd_vx_i8m2(__VA_ARGS__) -#define vsadd_vv_i8m4(...) __riscv_vsadd_vv_i8m4(__VA_ARGS__) -#define vsadd_vx_i8m4(...) __riscv_vsadd_vx_i8m4(__VA_ARGS__) -#define vsadd_vv_i8m8(...) __riscv_vsadd_vv_i8m8(__VA_ARGS__) -#define vsadd_vx_i8m8(...) __riscv_vsadd_vx_i8m8(__VA_ARGS__) -#define vsadd_vv_i16mf4(...) __riscv_vsadd_vv_i16mf4(__VA_ARGS__) -#define vsadd_vx_i16mf4(...) __riscv_vsadd_vx_i16mf4(__VA_ARGS__) -#define vsadd_vv_i16mf2(...) __riscv_vsadd_vv_i16mf2(__VA_ARGS__) -#define vsadd_vx_i16mf2(...) __riscv_vsadd_vx_i16mf2(__VA_ARGS__) -#define vsadd_vv_i16m1(...) __riscv_vsadd_vv_i16m1(__VA_ARGS__) -#define vsadd_vx_i16m1(...) __riscv_vsadd_vx_i16m1(__VA_ARGS__) -#define vsadd_vv_i16m2(...) __riscv_vsadd_vv_i16m2(__VA_ARGS__) -#define vsadd_vx_i16m2(...) __riscv_vsadd_vx_i16m2(__VA_ARGS__) -#define vsadd_vv_i16m4(...) __riscv_vsadd_vv_i16m4(__VA_ARGS__) -#define vsadd_vx_i16m4(...) __riscv_vsadd_vx_i16m4(__VA_ARGS__) -#define vsadd_vv_i16m8(...) __riscv_vsadd_vv_i16m8(__VA_ARGS__) -#define vsadd_vx_i16m8(...) __riscv_vsadd_vx_i16m8(__VA_ARGS__) -#define vsadd_vv_i32mf2(...) __riscv_vsadd_vv_i32mf2(__VA_ARGS__) -#define vsadd_vx_i32mf2(...) __riscv_vsadd_vx_i32mf2(__VA_ARGS__) -#define vsadd_vv_i32m1(...) __riscv_vsadd_vv_i32m1(__VA_ARGS__) -#define vsadd_vx_i32m1(...) __riscv_vsadd_vx_i32m1(__VA_ARGS__) -#define vsadd_vv_i32m2(...) __riscv_vsadd_vv_i32m2(__VA_ARGS__) -#define vsadd_vx_i32m2(...) __riscv_vsadd_vx_i32m2(__VA_ARGS__) -#define vsadd_vv_i32m4(...) __riscv_vsadd_vv_i32m4(__VA_ARGS__) -#define vsadd_vx_i32m4(...) __riscv_vsadd_vx_i32m4(__VA_ARGS__) -#define vsadd_vv_i32m8(...) __riscv_vsadd_vv_i32m8(__VA_ARGS__) -#define vsadd_vx_i32m8(...) __riscv_vsadd_vx_i32m8(__VA_ARGS__) -#define vsadd_vv_i64m1(...) __riscv_vsadd_vv_i64m1(__VA_ARGS__) -#define vsadd_vx_i64m1(...) __riscv_vsadd_vx_i64m1(__VA_ARGS__) -#define vsadd_vv_i64m2(...) __riscv_vsadd_vv_i64m2(__VA_ARGS__) -#define vsadd_vx_i64m2(...) __riscv_vsadd_vx_i64m2(__VA_ARGS__) -#define vsadd_vv_i64m4(...) __riscv_vsadd_vv_i64m4(__VA_ARGS__) -#define vsadd_vx_i64m4(...) __riscv_vsadd_vx_i64m4(__VA_ARGS__) -#define vsadd_vv_i64m8(...) __riscv_vsadd_vv_i64m8(__VA_ARGS__) -#define vsadd_vx_i64m8(...) __riscv_vsadd_vx_i64m8(__VA_ARGS__) -#define vssub_vv_i8mf8(...) __riscv_vssub_vv_i8mf8(__VA_ARGS__) -#define vssub_vx_i8mf8(...) __riscv_vssub_vx_i8mf8(__VA_ARGS__) -#define vssub_vv_i8mf4(...) __riscv_vssub_vv_i8mf4(__VA_ARGS__) -#define vssub_vx_i8mf4(...) __riscv_vssub_vx_i8mf4(__VA_ARGS__) -#define vssub_vv_i8mf2(...) __riscv_vssub_vv_i8mf2(__VA_ARGS__) -#define vssub_vx_i8mf2(...) __riscv_vssub_vx_i8mf2(__VA_ARGS__) -#define vssub_vv_i8m1(...) __riscv_vssub_vv_i8m1(__VA_ARGS__) -#define vssub_vx_i8m1(...) __riscv_vssub_vx_i8m1(__VA_ARGS__) -#define vssub_vv_i8m2(...) __riscv_vssub_vv_i8m2(__VA_ARGS__) -#define vssub_vx_i8m2(...) __riscv_vssub_vx_i8m2(__VA_ARGS__) -#define vssub_vv_i8m4(...) __riscv_vssub_vv_i8m4(__VA_ARGS__) -#define vssub_vx_i8m4(...) __riscv_vssub_vx_i8m4(__VA_ARGS__) -#define vssub_vv_i8m8(...) __riscv_vssub_vv_i8m8(__VA_ARGS__) -#define vssub_vx_i8m8(...) __riscv_vssub_vx_i8m8(__VA_ARGS__) -#define vssub_vv_i16mf4(...) __riscv_vssub_vv_i16mf4(__VA_ARGS__) -#define vssub_vx_i16mf4(...) __riscv_vssub_vx_i16mf4(__VA_ARGS__) -#define vssub_vv_i16mf2(...) __riscv_vssub_vv_i16mf2(__VA_ARGS__) -#define vssub_vx_i16mf2(...) __riscv_vssub_vx_i16mf2(__VA_ARGS__) -#define vssub_vv_i16m1(...) __riscv_vssub_vv_i16m1(__VA_ARGS__) -#define vssub_vx_i16m1(...) __riscv_vssub_vx_i16m1(__VA_ARGS__) -#define vssub_vv_i16m2(...) __riscv_vssub_vv_i16m2(__VA_ARGS__) -#define vssub_vx_i16m2(...) __riscv_vssub_vx_i16m2(__VA_ARGS__) -#define vssub_vv_i16m4(...) __riscv_vssub_vv_i16m4(__VA_ARGS__) -#define vssub_vx_i16m4(...) __riscv_vssub_vx_i16m4(__VA_ARGS__) -#define vssub_vv_i16m8(...) __riscv_vssub_vv_i16m8(__VA_ARGS__) -#define vssub_vx_i16m8(...) __riscv_vssub_vx_i16m8(__VA_ARGS__) -#define vssub_vv_i32mf2(...) __riscv_vssub_vv_i32mf2(__VA_ARGS__) -#define vssub_vx_i32mf2(...) __riscv_vssub_vx_i32mf2(__VA_ARGS__) -#define vssub_vv_i32m1(...) __riscv_vssub_vv_i32m1(__VA_ARGS__) -#define vssub_vx_i32m1(...) __riscv_vssub_vx_i32m1(__VA_ARGS__) -#define vssub_vv_i32m2(...) __riscv_vssub_vv_i32m2(__VA_ARGS__) -#define vssub_vx_i32m2(...) __riscv_vssub_vx_i32m2(__VA_ARGS__) -#define vssub_vv_i32m4(...) __riscv_vssub_vv_i32m4(__VA_ARGS__) -#define vssub_vx_i32m4(...) __riscv_vssub_vx_i32m4(__VA_ARGS__) -#define vssub_vv_i32m8(...) __riscv_vssub_vv_i32m8(__VA_ARGS__) -#define vssub_vx_i32m8(...) __riscv_vssub_vx_i32m8(__VA_ARGS__) -#define vssub_vv_i64m1(...) __riscv_vssub_vv_i64m1(__VA_ARGS__) -#define vssub_vx_i64m1(...) __riscv_vssub_vx_i64m1(__VA_ARGS__) -#define vssub_vv_i64m2(...) __riscv_vssub_vv_i64m2(__VA_ARGS__) -#define vssub_vx_i64m2(...) __riscv_vssub_vx_i64m2(__VA_ARGS__) -#define vssub_vv_i64m4(...) __riscv_vssub_vv_i64m4(__VA_ARGS__) -#define vssub_vx_i64m4(...) __riscv_vssub_vx_i64m4(__VA_ARGS__) -#define vssub_vv_i64m8(...) __riscv_vssub_vv_i64m8(__VA_ARGS__) -#define vssub_vx_i64m8(...) __riscv_vssub_vx_i64m8(__VA_ARGS__) -#define vsaddu_vv_u8mf8(...) __riscv_vsaddu_vv_u8mf8(__VA_ARGS__) -#define vsaddu_vx_u8mf8(...) __riscv_vsaddu_vx_u8mf8(__VA_ARGS__) -#define vsaddu_vv_u8mf4(...) __riscv_vsaddu_vv_u8mf4(__VA_ARGS__) -#define vsaddu_vx_u8mf4(...) __riscv_vsaddu_vx_u8mf4(__VA_ARGS__) -#define vsaddu_vv_u8mf2(...) __riscv_vsaddu_vv_u8mf2(__VA_ARGS__) -#define vsaddu_vx_u8mf2(...) __riscv_vsaddu_vx_u8mf2(__VA_ARGS__) -#define vsaddu_vv_u8m1(...) __riscv_vsaddu_vv_u8m1(__VA_ARGS__) -#define vsaddu_vx_u8m1(...) __riscv_vsaddu_vx_u8m1(__VA_ARGS__) -#define vsaddu_vv_u8m2(...) __riscv_vsaddu_vv_u8m2(__VA_ARGS__) -#define vsaddu_vx_u8m2(...) __riscv_vsaddu_vx_u8m2(__VA_ARGS__) -#define vsaddu_vv_u8m4(...) __riscv_vsaddu_vv_u8m4(__VA_ARGS__) -#define vsaddu_vx_u8m4(...) __riscv_vsaddu_vx_u8m4(__VA_ARGS__) -#define vsaddu_vv_u8m8(...) __riscv_vsaddu_vv_u8m8(__VA_ARGS__) -#define vsaddu_vx_u8m8(...) __riscv_vsaddu_vx_u8m8(__VA_ARGS__) -#define vsaddu_vv_u16mf4(...) __riscv_vsaddu_vv_u16mf4(__VA_ARGS__) -#define vsaddu_vx_u16mf4(...) __riscv_vsaddu_vx_u16mf4(__VA_ARGS__) -#define vsaddu_vv_u16mf2(...) __riscv_vsaddu_vv_u16mf2(__VA_ARGS__) -#define vsaddu_vx_u16mf2(...) __riscv_vsaddu_vx_u16mf2(__VA_ARGS__) -#define vsaddu_vv_u16m1(...) __riscv_vsaddu_vv_u16m1(__VA_ARGS__) -#define vsaddu_vx_u16m1(...) __riscv_vsaddu_vx_u16m1(__VA_ARGS__) -#define vsaddu_vv_u16m2(...) __riscv_vsaddu_vv_u16m2(__VA_ARGS__) -#define vsaddu_vx_u16m2(...) __riscv_vsaddu_vx_u16m2(__VA_ARGS__) -#define vsaddu_vv_u16m4(...) __riscv_vsaddu_vv_u16m4(__VA_ARGS__) -#define vsaddu_vx_u16m4(...) __riscv_vsaddu_vx_u16m4(__VA_ARGS__) -#define vsaddu_vv_u16m8(...) __riscv_vsaddu_vv_u16m8(__VA_ARGS__) -#define vsaddu_vx_u16m8(...) __riscv_vsaddu_vx_u16m8(__VA_ARGS__) -#define vsaddu_vv_u32mf2(...) __riscv_vsaddu_vv_u32mf2(__VA_ARGS__) -#define vsaddu_vx_u32mf2(...) __riscv_vsaddu_vx_u32mf2(__VA_ARGS__) -#define vsaddu_vv_u32m1(...) __riscv_vsaddu_vv_u32m1(__VA_ARGS__) -#define vsaddu_vx_u32m1(...) __riscv_vsaddu_vx_u32m1(__VA_ARGS__) -#define vsaddu_vv_u32m2(...) __riscv_vsaddu_vv_u32m2(__VA_ARGS__) -#define vsaddu_vx_u32m2(...) __riscv_vsaddu_vx_u32m2(__VA_ARGS__) -#define vsaddu_vv_u32m4(...) __riscv_vsaddu_vv_u32m4(__VA_ARGS__) -#define vsaddu_vx_u32m4(...) __riscv_vsaddu_vx_u32m4(__VA_ARGS__) -#define vsaddu_vv_u32m8(...) __riscv_vsaddu_vv_u32m8(__VA_ARGS__) -#define vsaddu_vx_u32m8(...) __riscv_vsaddu_vx_u32m8(__VA_ARGS__) -#define vsaddu_vv_u64m1(...) __riscv_vsaddu_vv_u64m1(__VA_ARGS__) -#define vsaddu_vx_u64m1(...) __riscv_vsaddu_vx_u64m1(__VA_ARGS__) -#define vsaddu_vv_u64m2(...) __riscv_vsaddu_vv_u64m2(__VA_ARGS__) -#define vsaddu_vx_u64m2(...) __riscv_vsaddu_vx_u64m2(__VA_ARGS__) -#define vsaddu_vv_u64m4(...) __riscv_vsaddu_vv_u64m4(__VA_ARGS__) -#define vsaddu_vx_u64m4(...) __riscv_vsaddu_vx_u64m4(__VA_ARGS__) -#define vsaddu_vv_u64m8(...) __riscv_vsaddu_vv_u64m8(__VA_ARGS__) -#define vsaddu_vx_u64m8(...) __riscv_vsaddu_vx_u64m8(__VA_ARGS__) -#define vssubu_vv_u8mf8(...) __riscv_vssubu_vv_u8mf8(__VA_ARGS__) -#define vssubu_vx_u8mf8(...) __riscv_vssubu_vx_u8mf8(__VA_ARGS__) -#define vssubu_vv_u8mf4(...) __riscv_vssubu_vv_u8mf4(__VA_ARGS__) -#define vssubu_vx_u8mf4(...) __riscv_vssubu_vx_u8mf4(__VA_ARGS__) -#define vssubu_vv_u8mf2(...) __riscv_vssubu_vv_u8mf2(__VA_ARGS__) -#define vssubu_vx_u8mf2(...) __riscv_vssubu_vx_u8mf2(__VA_ARGS__) -#define vssubu_vv_u8m1(...) __riscv_vssubu_vv_u8m1(__VA_ARGS__) -#define vssubu_vx_u8m1(...) __riscv_vssubu_vx_u8m1(__VA_ARGS__) -#define vssubu_vv_u8m2(...) __riscv_vssubu_vv_u8m2(__VA_ARGS__) -#define vssubu_vx_u8m2(...) __riscv_vssubu_vx_u8m2(__VA_ARGS__) -#define vssubu_vv_u8m4(...) __riscv_vssubu_vv_u8m4(__VA_ARGS__) -#define vssubu_vx_u8m4(...) __riscv_vssubu_vx_u8m4(__VA_ARGS__) -#define vssubu_vv_u8m8(...) __riscv_vssubu_vv_u8m8(__VA_ARGS__) -#define vssubu_vx_u8m8(...) __riscv_vssubu_vx_u8m8(__VA_ARGS__) -#define vssubu_vv_u16mf4(...) __riscv_vssubu_vv_u16mf4(__VA_ARGS__) -#define vssubu_vx_u16mf4(...) __riscv_vssubu_vx_u16mf4(__VA_ARGS__) -#define vssubu_vv_u16mf2(...) __riscv_vssubu_vv_u16mf2(__VA_ARGS__) -#define vssubu_vx_u16mf2(...) __riscv_vssubu_vx_u16mf2(__VA_ARGS__) -#define vssubu_vv_u16m1(...) __riscv_vssubu_vv_u16m1(__VA_ARGS__) -#define vssubu_vx_u16m1(...) __riscv_vssubu_vx_u16m1(__VA_ARGS__) -#define vssubu_vv_u16m2(...) __riscv_vssubu_vv_u16m2(__VA_ARGS__) -#define vssubu_vx_u16m2(...) __riscv_vssubu_vx_u16m2(__VA_ARGS__) -#define vssubu_vv_u16m4(...) __riscv_vssubu_vv_u16m4(__VA_ARGS__) -#define vssubu_vx_u16m4(...) __riscv_vssubu_vx_u16m4(__VA_ARGS__) -#define vssubu_vv_u16m8(...) __riscv_vssubu_vv_u16m8(__VA_ARGS__) -#define vssubu_vx_u16m8(...) __riscv_vssubu_vx_u16m8(__VA_ARGS__) -#define vssubu_vv_u32mf2(...) __riscv_vssubu_vv_u32mf2(__VA_ARGS__) -#define vssubu_vx_u32mf2(...) __riscv_vssubu_vx_u32mf2(__VA_ARGS__) -#define vssubu_vv_u32m1(...) __riscv_vssubu_vv_u32m1(__VA_ARGS__) -#define vssubu_vx_u32m1(...) __riscv_vssubu_vx_u32m1(__VA_ARGS__) -#define vssubu_vv_u32m2(...) __riscv_vssubu_vv_u32m2(__VA_ARGS__) -#define vssubu_vx_u32m2(...) __riscv_vssubu_vx_u32m2(__VA_ARGS__) -#define vssubu_vv_u32m4(...) __riscv_vssubu_vv_u32m4(__VA_ARGS__) -#define vssubu_vx_u32m4(...) __riscv_vssubu_vx_u32m4(__VA_ARGS__) -#define vssubu_vv_u32m8(...) __riscv_vssubu_vv_u32m8(__VA_ARGS__) -#define vssubu_vx_u32m8(...) __riscv_vssubu_vx_u32m8(__VA_ARGS__) -#define vssubu_vv_u64m1(...) __riscv_vssubu_vv_u64m1(__VA_ARGS__) -#define vssubu_vx_u64m1(...) __riscv_vssubu_vx_u64m1(__VA_ARGS__) -#define vssubu_vv_u64m2(...) __riscv_vssubu_vv_u64m2(__VA_ARGS__) -#define vssubu_vx_u64m2(...) __riscv_vssubu_vx_u64m2(__VA_ARGS__) -#define vssubu_vv_u64m4(...) __riscv_vssubu_vv_u64m4(__VA_ARGS__) -#define vssubu_vx_u64m4(...) __riscv_vssubu_vx_u64m4(__VA_ARGS__) -#define vssubu_vv_u64m8(...) __riscv_vssubu_vv_u64m8(__VA_ARGS__) -#define vssubu_vx_u64m8(...) __riscv_vssubu_vx_u64m8(__VA_ARGS__) -// masked functions -#define vsadd_vv_i8mf8_m(...) __riscv_vsadd_vv_i8mf8_tumu(__VA_ARGS__) -#define vsadd_vx_i8mf8_m(...) __riscv_vsadd_vx_i8mf8_tumu(__VA_ARGS__) -#define vsadd_vv_i8mf4_m(...) __riscv_vsadd_vv_i8mf4_tumu(__VA_ARGS__) -#define vsadd_vx_i8mf4_m(...) __riscv_vsadd_vx_i8mf4_tumu(__VA_ARGS__) -#define vsadd_vv_i8mf2_m(...) __riscv_vsadd_vv_i8mf2_tumu(__VA_ARGS__) -#define vsadd_vx_i8mf2_m(...) __riscv_vsadd_vx_i8mf2_tumu(__VA_ARGS__) -#define vsadd_vv_i8m1_m(...) __riscv_vsadd_vv_i8m1_tumu(__VA_ARGS__) -#define vsadd_vx_i8m1_m(...) __riscv_vsadd_vx_i8m1_tumu(__VA_ARGS__) -#define vsadd_vv_i8m2_m(...) __riscv_vsadd_vv_i8m2_tumu(__VA_ARGS__) -#define vsadd_vx_i8m2_m(...) __riscv_vsadd_vx_i8m2_tumu(__VA_ARGS__) -#define vsadd_vv_i8m4_m(...) __riscv_vsadd_vv_i8m4_tumu(__VA_ARGS__) -#define vsadd_vx_i8m4_m(...) __riscv_vsadd_vx_i8m4_tumu(__VA_ARGS__) -#define vsadd_vv_i8m8_m(...) __riscv_vsadd_vv_i8m8_tumu(__VA_ARGS__) -#define vsadd_vx_i8m8_m(...) __riscv_vsadd_vx_i8m8_tumu(__VA_ARGS__) -#define vsadd_vv_i16mf4_m(...) __riscv_vsadd_vv_i16mf4_tumu(__VA_ARGS__) -#define vsadd_vx_i16mf4_m(...) __riscv_vsadd_vx_i16mf4_tumu(__VA_ARGS__) -#define vsadd_vv_i16mf2_m(...) __riscv_vsadd_vv_i16mf2_tumu(__VA_ARGS__) -#define vsadd_vx_i16mf2_m(...) __riscv_vsadd_vx_i16mf2_tumu(__VA_ARGS__) -#define vsadd_vv_i16m1_m(...) __riscv_vsadd_vv_i16m1_tumu(__VA_ARGS__) -#define vsadd_vx_i16m1_m(...) __riscv_vsadd_vx_i16m1_tumu(__VA_ARGS__) -#define vsadd_vv_i16m2_m(...) __riscv_vsadd_vv_i16m2_tumu(__VA_ARGS__) -#define vsadd_vx_i16m2_m(...) __riscv_vsadd_vx_i16m2_tumu(__VA_ARGS__) -#define vsadd_vv_i16m4_m(...) __riscv_vsadd_vv_i16m4_tumu(__VA_ARGS__) -#define vsadd_vx_i16m4_m(...) __riscv_vsadd_vx_i16m4_tumu(__VA_ARGS__) -#define vsadd_vv_i16m8_m(...) __riscv_vsadd_vv_i16m8_tumu(__VA_ARGS__) -#define vsadd_vx_i16m8_m(...) __riscv_vsadd_vx_i16m8_tumu(__VA_ARGS__) -#define vsadd_vv_i32mf2_m(...) __riscv_vsadd_vv_i32mf2_tumu(__VA_ARGS__) -#define vsadd_vx_i32mf2_m(...) __riscv_vsadd_vx_i32mf2_tumu(__VA_ARGS__) -#define vsadd_vv_i32m1_m(...) __riscv_vsadd_vv_i32m1_tumu(__VA_ARGS__) -#define vsadd_vx_i32m1_m(...) __riscv_vsadd_vx_i32m1_tumu(__VA_ARGS__) -#define vsadd_vv_i32m2_m(...) __riscv_vsadd_vv_i32m2_tumu(__VA_ARGS__) -#define vsadd_vx_i32m2_m(...) __riscv_vsadd_vx_i32m2_tumu(__VA_ARGS__) -#define vsadd_vv_i32m4_m(...) __riscv_vsadd_vv_i32m4_tumu(__VA_ARGS__) -#define vsadd_vx_i32m4_m(...) __riscv_vsadd_vx_i32m4_tumu(__VA_ARGS__) -#define vsadd_vv_i32m8_m(...) __riscv_vsadd_vv_i32m8_tumu(__VA_ARGS__) -#define vsadd_vx_i32m8_m(...) __riscv_vsadd_vx_i32m8_tumu(__VA_ARGS__) -#define vsadd_vv_i64m1_m(...) __riscv_vsadd_vv_i64m1_tumu(__VA_ARGS__) -#define vsadd_vx_i64m1_m(...) __riscv_vsadd_vx_i64m1_tumu(__VA_ARGS__) -#define vsadd_vv_i64m2_m(...) __riscv_vsadd_vv_i64m2_tumu(__VA_ARGS__) -#define vsadd_vx_i64m2_m(...) __riscv_vsadd_vx_i64m2_tumu(__VA_ARGS__) -#define vsadd_vv_i64m4_m(...) __riscv_vsadd_vv_i64m4_tumu(__VA_ARGS__) -#define vsadd_vx_i64m4_m(...) __riscv_vsadd_vx_i64m4_tumu(__VA_ARGS__) -#define vsadd_vv_i64m8_m(...) __riscv_vsadd_vv_i64m8_tumu(__VA_ARGS__) -#define vsadd_vx_i64m8_m(...) __riscv_vsadd_vx_i64m8_tumu(__VA_ARGS__) -#define vssub_vv_i8mf8_m(...) __riscv_vssub_vv_i8mf8_tumu(__VA_ARGS__) -#define vssub_vx_i8mf8_m(...) __riscv_vssub_vx_i8mf8_tumu(__VA_ARGS__) -#define vssub_vv_i8mf4_m(...) __riscv_vssub_vv_i8mf4_tumu(__VA_ARGS__) -#define vssub_vx_i8mf4_m(...) __riscv_vssub_vx_i8mf4_tumu(__VA_ARGS__) -#define vssub_vv_i8mf2_m(...) __riscv_vssub_vv_i8mf2_tumu(__VA_ARGS__) -#define vssub_vx_i8mf2_m(...) __riscv_vssub_vx_i8mf2_tumu(__VA_ARGS__) -#define vssub_vv_i8m1_m(...) __riscv_vssub_vv_i8m1_tumu(__VA_ARGS__) -#define vssub_vx_i8m1_m(...) __riscv_vssub_vx_i8m1_tumu(__VA_ARGS__) -#define vssub_vv_i8m2_m(...) __riscv_vssub_vv_i8m2_tumu(__VA_ARGS__) -#define vssub_vx_i8m2_m(...) __riscv_vssub_vx_i8m2_tumu(__VA_ARGS__) -#define vssub_vv_i8m4_m(...) __riscv_vssub_vv_i8m4_tumu(__VA_ARGS__) -#define vssub_vx_i8m4_m(...) __riscv_vssub_vx_i8m4_tumu(__VA_ARGS__) -#define vssub_vv_i8m8_m(...) __riscv_vssub_vv_i8m8_tumu(__VA_ARGS__) -#define vssub_vx_i8m8_m(...) __riscv_vssub_vx_i8m8_tumu(__VA_ARGS__) -#define vssub_vv_i16mf4_m(...) __riscv_vssub_vv_i16mf4_tumu(__VA_ARGS__) -#define vssub_vx_i16mf4_m(...) __riscv_vssub_vx_i16mf4_tumu(__VA_ARGS__) -#define vssub_vv_i16mf2_m(...) __riscv_vssub_vv_i16mf2_tumu(__VA_ARGS__) -#define vssub_vx_i16mf2_m(...) __riscv_vssub_vx_i16mf2_tumu(__VA_ARGS__) -#define vssub_vv_i16m1_m(...) __riscv_vssub_vv_i16m1_tumu(__VA_ARGS__) -#define vssub_vx_i16m1_m(...) __riscv_vssub_vx_i16m1_tumu(__VA_ARGS__) -#define vssub_vv_i16m2_m(...) __riscv_vssub_vv_i16m2_tumu(__VA_ARGS__) -#define vssub_vx_i16m2_m(...) __riscv_vssub_vx_i16m2_tumu(__VA_ARGS__) -#define vssub_vv_i16m4_m(...) __riscv_vssub_vv_i16m4_tumu(__VA_ARGS__) -#define vssub_vx_i16m4_m(...) __riscv_vssub_vx_i16m4_tumu(__VA_ARGS__) -#define vssub_vv_i16m8_m(...) __riscv_vssub_vv_i16m8_tumu(__VA_ARGS__) -#define vssub_vx_i16m8_m(...) __riscv_vssub_vx_i16m8_tumu(__VA_ARGS__) -#define vssub_vv_i32mf2_m(...) __riscv_vssub_vv_i32mf2_tumu(__VA_ARGS__) -#define vssub_vx_i32mf2_m(...) __riscv_vssub_vx_i32mf2_tumu(__VA_ARGS__) -#define vssub_vv_i32m1_m(...) __riscv_vssub_vv_i32m1_tumu(__VA_ARGS__) -#define vssub_vx_i32m1_m(...) __riscv_vssub_vx_i32m1_tumu(__VA_ARGS__) -#define vssub_vv_i32m2_m(...) __riscv_vssub_vv_i32m2_tumu(__VA_ARGS__) -#define vssub_vx_i32m2_m(...) __riscv_vssub_vx_i32m2_tumu(__VA_ARGS__) -#define vssub_vv_i32m4_m(...) __riscv_vssub_vv_i32m4_tumu(__VA_ARGS__) -#define vssub_vx_i32m4_m(...) __riscv_vssub_vx_i32m4_tumu(__VA_ARGS__) -#define vssub_vv_i32m8_m(...) __riscv_vssub_vv_i32m8_tumu(__VA_ARGS__) -#define vssub_vx_i32m8_m(...) __riscv_vssub_vx_i32m8_tumu(__VA_ARGS__) -#define vssub_vv_i64m1_m(...) __riscv_vssub_vv_i64m1_tumu(__VA_ARGS__) -#define vssub_vx_i64m1_m(...) __riscv_vssub_vx_i64m1_tumu(__VA_ARGS__) -#define vssub_vv_i64m2_m(...) __riscv_vssub_vv_i64m2_tumu(__VA_ARGS__) -#define vssub_vx_i64m2_m(...) __riscv_vssub_vx_i64m2_tumu(__VA_ARGS__) -#define vssub_vv_i64m4_m(...) __riscv_vssub_vv_i64m4_tumu(__VA_ARGS__) -#define vssub_vx_i64m4_m(...) __riscv_vssub_vx_i64m4_tumu(__VA_ARGS__) -#define vssub_vv_i64m8_m(...) __riscv_vssub_vv_i64m8_tumu(__VA_ARGS__) -#define vssub_vx_i64m8_m(...) __riscv_vssub_vx_i64m8_tumu(__VA_ARGS__) -#define vsaddu_vv_u8mf8_m(...) __riscv_vsaddu_vv_u8mf8_tumu(__VA_ARGS__) -#define vsaddu_vx_u8mf8_m(...) __riscv_vsaddu_vx_u8mf8_tumu(__VA_ARGS__) -#define vsaddu_vv_u8mf4_m(...) __riscv_vsaddu_vv_u8mf4_tumu(__VA_ARGS__) -#define vsaddu_vx_u8mf4_m(...) __riscv_vsaddu_vx_u8mf4_tumu(__VA_ARGS__) -#define vsaddu_vv_u8mf2_m(...) __riscv_vsaddu_vv_u8mf2_tumu(__VA_ARGS__) -#define vsaddu_vx_u8mf2_m(...) __riscv_vsaddu_vx_u8mf2_tumu(__VA_ARGS__) -#define vsaddu_vv_u8m1_m(...) __riscv_vsaddu_vv_u8m1_tumu(__VA_ARGS__) -#define vsaddu_vx_u8m1_m(...) __riscv_vsaddu_vx_u8m1_tumu(__VA_ARGS__) -#define vsaddu_vv_u8m2_m(...) __riscv_vsaddu_vv_u8m2_tumu(__VA_ARGS__) -#define vsaddu_vx_u8m2_m(...) __riscv_vsaddu_vx_u8m2_tumu(__VA_ARGS__) -#define vsaddu_vv_u8m4_m(...) __riscv_vsaddu_vv_u8m4_tumu(__VA_ARGS__) -#define vsaddu_vx_u8m4_m(...) __riscv_vsaddu_vx_u8m4_tumu(__VA_ARGS__) -#define vsaddu_vv_u8m8_m(...) __riscv_vsaddu_vv_u8m8_tumu(__VA_ARGS__) -#define vsaddu_vx_u8m8_m(...) __riscv_vsaddu_vx_u8m8_tumu(__VA_ARGS__) -#define vsaddu_vv_u16mf4_m(...) __riscv_vsaddu_vv_u16mf4_tumu(__VA_ARGS__) -#define vsaddu_vx_u16mf4_m(...) __riscv_vsaddu_vx_u16mf4_tumu(__VA_ARGS__) -#define vsaddu_vv_u16mf2_m(...) __riscv_vsaddu_vv_u16mf2_tumu(__VA_ARGS__) -#define vsaddu_vx_u16mf2_m(...) __riscv_vsaddu_vx_u16mf2_tumu(__VA_ARGS__) -#define vsaddu_vv_u16m1_m(...) __riscv_vsaddu_vv_u16m1_tumu(__VA_ARGS__) -#define vsaddu_vx_u16m1_m(...) __riscv_vsaddu_vx_u16m1_tumu(__VA_ARGS__) -#define vsaddu_vv_u16m2_m(...) __riscv_vsaddu_vv_u16m2_tumu(__VA_ARGS__) -#define vsaddu_vx_u16m2_m(...) __riscv_vsaddu_vx_u16m2_tumu(__VA_ARGS__) -#define vsaddu_vv_u16m4_m(...) __riscv_vsaddu_vv_u16m4_tumu(__VA_ARGS__) -#define vsaddu_vx_u16m4_m(...) __riscv_vsaddu_vx_u16m4_tumu(__VA_ARGS__) -#define vsaddu_vv_u16m8_m(...) __riscv_vsaddu_vv_u16m8_tumu(__VA_ARGS__) -#define vsaddu_vx_u16m8_m(...) __riscv_vsaddu_vx_u16m8_tumu(__VA_ARGS__) -#define vsaddu_vv_u32mf2_m(...) __riscv_vsaddu_vv_u32mf2_tumu(__VA_ARGS__) -#define vsaddu_vx_u32mf2_m(...) __riscv_vsaddu_vx_u32mf2_tumu(__VA_ARGS__) -#define vsaddu_vv_u32m1_m(...) __riscv_vsaddu_vv_u32m1_tumu(__VA_ARGS__) -#define vsaddu_vx_u32m1_m(...) __riscv_vsaddu_vx_u32m1_tumu(__VA_ARGS__) -#define vsaddu_vv_u32m2_m(...) __riscv_vsaddu_vv_u32m2_tumu(__VA_ARGS__) -#define vsaddu_vx_u32m2_m(...) __riscv_vsaddu_vx_u32m2_tumu(__VA_ARGS__) -#define vsaddu_vv_u32m4_m(...) __riscv_vsaddu_vv_u32m4_tumu(__VA_ARGS__) -#define vsaddu_vx_u32m4_m(...) __riscv_vsaddu_vx_u32m4_tumu(__VA_ARGS__) -#define vsaddu_vv_u32m8_m(...) __riscv_vsaddu_vv_u32m8_tumu(__VA_ARGS__) -#define vsaddu_vx_u32m8_m(...) __riscv_vsaddu_vx_u32m8_tumu(__VA_ARGS__) -#define vsaddu_vv_u64m1_m(...) __riscv_vsaddu_vv_u64m1_tumu(__VA_ARGS__) -#define vsaddu_vx_u64m1_m(...) __riscv_vsaddu_vx_u64m1_tumu(__VA_ARGS__) -#define vsaddu_vv_u64m2_m(...) __riscv_vsaddu_vv_u64m2_tumu(__VA_ARGS__) -#define vsaddu_vx_u64m2_m(...) __riscv_vsaddu_vx_u64m2_tumu(__VA_ARGS__) -#define vsaddu_vv_u64m4_m(...) __riscv_vsaddu_vv_u64m4_tumu(__VA_ARGS__) -#define vsaddu_vx_u64m4_m(...) __riscv_vsaddu_vx_u64m4_tumu(__VA_ARGS__) -#define vsaddu_vv_u64m8_m(...) __riscv_vsaddu_vv_u64m8_tumu(__VA_ARGS__) -#define vsaddu_vx_u64m8_m(...) __riscv_vsaddu_vx_u64m8_tumu(__VA_ARGS__) -#define vssubu_vv_u8mf8_m(...) __riscv_vssubu_vv_u8mf8_tumu(__VA_ARGS__) -#define vssubu_vx_u8mf8_m(...) __riscv_vssubu_vx_u8mf8_tumu(__VA_ARGS__) -#define vssubu_vv_u8mf4_m(...) __riscv_vssubu_vv_u8mf4_tumu(__VA_ARGS__) -#define vssubu_vx_u8mf4_m(...) __riscv_vssubu_vx_u8mf4_tumu(__VA_ARGS__) -#define vssubu_vv_u8mf2_m(...) __riscv_vssubu_vv_u8mf2_tumu(__VA_ARGS__) -#define vssubu_vx_u8mf2_m(...) __riscv_vssubu_vx_u8mf2_tumu(__VA_ARGS__) -#define vssubu_vv_u8m1_m(...) __riscv_vssubu_vv_u8m1_tumu(__VA_ARGS__) -#define vssubu_vx_u8m1_m(...) __riscv_vssubu_vx_u8m1_tumu(__VA_ARGS__) -#define vssubu_vv_u8m2_m(...) __riscv_vssubu_vv_u8m2_tumu(__VA_ARGS__) -#define vssubu_vx_u8m2_m(...) __riscv_vssubu_vx_u8m2_tumu(__VA_ARGS__) -#define vssubu_vv_u8m4_m(...) __riscv_vssubu_vv_u8m4_tumu(__VA_ARGS__) -#define vssubu_vx_u8m4_m(...) __riscv_vssubu_vx_u8m4_tumu(__VA_ARGS__) -#define vssubu_vv_u8m8_m(...) __riscv_vssubu_vv_u8m8_tumu(__VA_ARGS__) -#define vssubu_vx_u8m8_m(...) __riscv_vssubu_vx_u8m8_tumu(__VA_ARGS__) -#define vssubu_vv_u16mf4_m(...) __riscv_vssubu_vv_u16mf4_tumu(__VA_ARGS__) -#define vssubu_vx_u16mf4_m(...) __riscv_vssubu_vx_u16mf4_tumu(__VA_ARGS__) -#define vssubu_vv_u16mf2_m(...) __riscv_vssubu_vv_u16mf2_tumu(__VA_ARGS__) -#define vssubu_vx_u16mf2_m(...) __riscv_vssubu_vx_u16mf2_tumu(__VA_ARGS__) -#define vssubu_vv_u16m1_m(...) __riscv_vssubu_vv_u16m1_tumu(__VA_ARGS__) -#define vssubu_vx_u16m1_m(...) __riscv_vssubu_vx_u16m1_tumu(__VA_ARGS__) -#define vssubu_vv_u16m2_m(...) __riscv_vssubu_vv_u16m2_tumu(__VA_ARGS__) -#define vssubu_vx_u16m2_m(...) __riscv_vssubu_vx_u16m2_tumu(__VA_ARGS__) -#define vssubu_vv_u16m4_m(...) __riscv_vssubu_vv_u16m4_tumu(__VA_ARGS__) -#define vssubu_vx_u16m4_m(...) __riscv_vssubu_vx_u16m4_tumu(__VA_ARGS__) -#define vssubu_vv_u16m8_m(...) __riscv_vssubu_vv_u16m8_tumu(__VA_ARGS__) -#define vssubu_vx_u16m8_m(...) __riscv_vssubu_vx_u16m8_tumu(__VA_ARGS__) -#define vssubu_vv_u32mf2_m(...) __riscv_vssubu_vv_u32mf2_tumu(__VA_ARGS__) -#define vssubu_vx_u32mf2_m(...) __riscv_vssubu_vx_u32mf2_tumu(__VA_ARGS__) -#define vssubu_vv_u32m1_m(...) __riscv_vssubu_vv_u32m1_tumu(__VA_ARGS__) -#define vssubu_vx_u32m1_m(...) __riscv_vssubu_vx_u32m1_tumu(__VA_ARGS__) -#define vssubu_vv_u32m2_m(...) __riscv_vssubu_vv_u32m2_tumu(__VA_ARGS__) -#define vssubu_vx_u32m2_m(...) __riscv_vssubu_vx_u32m2_tumu(__VA_ARGS__) -#define vssubu_vv_u32m4_m(...) __riscv_vssubu_vv_u32m4_tumu(__VA_ARGS__) -#define vssubu_vx_u32m4_m(...) __riscv_vssubu_vx_u32m4_tumu(__VA_ARGS__) -#define vssubu_vv_u32m8_m(...) __riscv_vssubu_vv_u32m8_tumu(__VA_ARGS__) -#define vssubu_vx_u32m8_m(...) __riscv_vssubu_vx_u32m8_tumu(__VA_ARGS__) -#define vssubu_vv_u64m1_m(...) __riscv_vssubu_vv_u64m1_tumu(__VA_ARGS__) -#define vssubu_vx_u64m1_m(...) __riscv_vssubu_vx_u64m1_tumu(__VA_ARGS__) -#define vssubu_vv_u64m2_m(...) __riscv_vssubu_vv_u64m2_tumu(__VA_ARGS__) -#define vssubu_vx_u64m2_m(...) __riscv_vssubu_vx_u64m2_tumu(__VA_ARGS__) -#define vssubu_vv_u64m4_m(...) __riscv_vssubu_vv_u64m4_tumu(__VA_ARGS__) -#define vssubu_vx_u64m4_m(...) __riscv_vssubu_vx_u64m4_tumu(__VA_ARGS__) -#define vssubu_vv_u64m8_m(...) __riscv_vssubu_vv_u64m8_tumu(__VA_ARGS__) -#define vssubu_vx_u64m8_m(...) __riscv_vssubu_vx_u64m8_tumu(__VA_ARGS__) -#define vaadd_vv_i8mf8(...) __riscv_vaadd_vv_i8mf8(__VA_ARGS__) -#define vaadd_vx_i8mf8(...) __riscv_vaadd_vx_i8mf8(__VA_ARGS__) -#define vaadd_vv_i8mf4(...) __riscv_vaadd_vv_i8mf4(__VA_ARGS__) -#define vaadd_vx_i8mf4(...) __riscv_vaadd_vx_i8mf4(__VA_ARGS__) -#define vaadd_vv_i8mf2(...) __riscv_vaadd_vv_i8mf2(__VA_ARGS__) -#define vaadd_vx_i8mf2(...) __riscv_vaadd_vx_i8mf2(__VA_ARGS__) -#define vaadd_vv_i8m1(...) __riscv_vaadd_vv_i8m1(__VA_ARGS__) -#define vaadd_vx_i8m1(...) __riscv_vaadd_vx_i8m1(__VA_ARGS__) -#define vaadd_vv_i8m2(...) __riscv_vaadd_vv_i8m2(__VA_ARGS__) -#define vaadd_vx_i8m2(...) __riscv_vaadd_vx_i8m2(__VA_ARGS__) -#define vaadd_vv_i8m4(...) __riscv_vaadd_vv_i8m4(__VA_ARGS__) -#define vaadd_vx_i8m4(...) __riscv_vaadd_vx_i8m4(__VA_ARGS__) -#define vaadd_vv_i8m8(...) __riscv_vaadd_vv_i8m8(__VA_ARGS__) -#define vaadd_vx_i8m8(...) __riscv_vaadd_vx_i8m8(__VA_ARGS__) -#define vaadd_vv_i16mf4(...) __riscv_vaadd_vv_i16mf4(__VA_ARGS__) -#define vaadd_vx_i16mf4(...) __riscv_vaadd_vx_i16mf4(__VA_ARGS__) -#define vaadd_vv_i16mf2(...) __riscv_vaadd_vv_i16mf2(__VA_ARGS__) -#define vaadd_vx_i16mf2(...) __riscv_vaadd_vx_i16mf2(__VA_ARGS__) -#define vaadd_vv_i16m1(...) __riscv_vaadd_vv_i16m1(__VA_ARGS__) -#define vaadd_vx_i16m1(...) __riscv_vaadd_vx_i16m1(__VA_ARGS__) -#define vaadd_vv_i16m2(...) __riscv_vaadd_vv_i16m2(__VA_ARGS__) -#define vaadd_vx_i16m2(...) __riscv_vaadd_vx_i16m2(__VA_ARGS__) -#define vaadd_vv_i16m4(...) __riscv_vaadd_vv_i16m4(__VA_ARGS__) -#define vaadd_vx_i16m4(...) __riscv_vaadd_vx_i16m4(__VA_ARGS__) -#define vaadd_vv_i16m8(...) __riscv_vaadd_vv_i16m8(__VA_ARGS__) -#define vaadd_vx_i16m8(...) __riscv_vaadd_vx_i16m8(__VA_ARGS__) -#define vaadd_vv_i32mf2(...) __riscv_vaadd_vv_i32mf2(__VA_ARGS__) -#define vaadd_vx_i32mf2(...) __riscv_vaadd_vx_i32mf2(__VA_ARGS__) -#define vaadd_vv_i32m1(...) __riscv_vaadd_vv_i32m1(__VA_ARGS__) -#define vaadd_vx_i32m1(...) __riscv_vaadd_vx_i32m1(__VA_ARGS__) -#define vaadd_vv_i32m2(...) __riscv_vaadd_vv_i32m2(__VA_ARGS__) -#define vaadd_vx_i32m2(...) __riscv_vaadd_vx_i32m2(__VA_ARGS__) -#define vaadd_vv_i32m4(...) __riscv_vaadd_vv_i32m4(__VA_ARGS__) -#define vaadd_vx_i32m4(...) __riscv_vaadd_vx_i32m4(__VA_ARGS__) -#define vaadd_vv_i32m8(...) __riscv_vaadd_vv_i32m8(__VA_ARGS__) -#define vaadd_vx_i32m8(...) __riscv_vaadd_vx_i32m8(__VA_ARGS__) -#define vaadd_vv_i64m1(...) __riscv_vaadd_vv_i64m1(__VA_ARGS__) -#define vaadd_vx_i64m1(...) __riscv_vaadd_vx_i64m1(__VA_ARGS__) -#define vaadd_vv_i64m2(...) __riscv_vaadd_vv_i64m2(__VA_ARGS__) -#define vaadd_vx_i64m2(...) __riscv_vaadd_vx_i64m2(__VA_ARGS__) -#define vaadd_vv_i64m4(...) __riscv_vaadd_vv_i64m4(__VA_ARGS__) -#define vaadd_vx_i64m4(...) __riscv_vaadd_vx_i64m4(__VA_ARGS__) -#define vaadd_vv_i64m8(...) __riscv_vaadd_vv_i64m8(__VA_ARGS__) -#define vaadd_vx_i64m8(...) __riscv_vaadd_vx_i64m8(__VA_ARGS__) -#define vasub_vv_i8mf8(...) __riscv_vasub_vv_i8mf8(__VA_ARGS__) -#define vasub_vx_i8mf8(...) __riscv_vasub_vx_i8mf8(__VA_ARGS__) -#define vasub_vv_i8mf4(...) __riscv_vasub_vv_i8mf4(__VA_ARGS__) -#define vasub_vx_i8mf4(...) __riscv_vasub_vx_i8mf4(__VA_ARGS__) -#define vasub_vv_i8mf2(...) __riscv_vasub_vv_i8mf2(__VA_ARGS__) -#define vasub_vx_i8mf2(...) __riscv_vasub_vx_i8mf2(__VA_ARGS__) -#define vasub_vv_i8m1(...) __riscv_vasub_vv_i8m1(__VA_ARGS__) -#define vasub_vx_i8m1(...) __riscv_vasub_vx_i8m1(__VA_ARGS__) -#define vasub_vv_i8m2(...) __riscv_vasub_vv_i8m2(__VA_ARGS__) -#define vasub_vx_i8m2(...) __riscv_vasub_vx_i8m2(__VA_ARGS__) -#define vasub_vv_i8m4(...) __riscv_vasub_vv_i8m4(__VA_ARGS__) -#define vasub_vx_i8m4(...) __riscv_vasub_vx_i8m4(__VA_ARGS__) -#define vasub_vv_i8m8(...) __riscv_vasub_vv_i8m8(__VA_ARGS__) -#define vasub_vx_i8m8(...) __riscv_vasub_vx_i8m8(__VA_ARGS__) -#define vasub_vv_i16mf4(...) __riscv_vasub_vv_i16mf4(__VA_ARGS__) -#define vasub_vx_i16mf4(...) __riscv_vasub_vx_i16mf4(__VA_ARGS__) -#define vasub_vv_i16mf2(...) __riscv_vasub_vv_i16mf2(__VA_ARGS__) -#define vasub_vx_i16mf2(...) __riscv_vasub_vx_i16mf2(__VA_ARGS__) -#define vasub_vv_i16m1(...) __riscv_vasub_vv_i16m1(__VA_ARGS__) -#define vasub_vx_i16m1(...) __riscv_vasub_vx_i16m1(__VA_ARGS__) -#define vasub_vv_i16m2(...) __riscv_vasub_vv_i16m2(__VA_ARGS__) -#define vasub_vx_i16m2(...) __riscv_vasub_vx_i16m2(__VA_ARGS__) -#define vasub_vv_i16m4(...) __riscv_vasub_vv_i16m4(__VA_ARGS__) -#define vasub_vx_i16m4(...) __riscv_vasub_vx_i16m4(__VA_ARGS__) -#define vasub_vv_i16m8(...) __riscv_vasub_vv_i16m8(__VA_ARGS__) -#define vasub_vx_i16m8(...) __riscv_vasub_vx_i16m8(__VA_ARGS__) -#define vasub_vv_i32mf2(...) __riscv_vasub_vv_i32mf2(__VA_ARGS__) -#define vasub_vx_i32mf2(...) __riscv_vasub_vx_i32mf2(__VA_ARGS__) -#define vasub_vv_i32m1(...) __riscv_vasub_vv_i32m1(__VA_ARGS__) -#define vasub_vx_i32m1(...) __riscv_vasub_vx_i32m1(__VA_ARGS__) -#define vasub_vv_i32m2(...) __riscv_vasub_vv_i32m2(__VA_ARGS__) -#define vasub_vx_i32m2(...) __riscv_vasub_vx_i32m2(__VA_ARGS__) -#define vasub_vv_i32m4(...) __riscv_vasub_vv_i32m4(__VA_ARGS__) -#define vasub_vx_i32m4(...) __riscv_vasub_vx_i32m4(__VA_ARGS__) -#define vasub_vv_i32m8(...) __riscv_vasub_vv_i32m8(__VA_ARGS__) -#define vasub_vx_i32m8(...) __riscv_vasub_vx_i32m8(__VA_ARGS__) -#define vasub_vv_i64m1(...) __riscv_vasub_vv_i64m1(__VA_ARGS__) -#define vasub_vx_i64m1(...) __riscv_vasub_vx_i64m1(__VA_ARGS__) -#define vasub_vv_i64m2(...) __riscv_vasub_vv_i64m2(__VA_ARGS__) -#define vasub_vx_i64m2(...) __riscv_vasub_vx_i64m2(__VA_ARGS__) -#define vasub_vv_i64m4(...) __riscv_vasub_vv_i64m4(__VA_ARGS__) -#define vasub_vx_i64m4(...) __riscv_vasub_vx_i64m4(__VA_ARGS__) -#define vasub_vv_i64m8(...) __riscv_vasub_vv_i64m8(__VA_ARGS__) -#define vasub_vx_i64m8(...) __riscv_vasub_vx_i64m8(__VA_ARGS__) -#define vaaddu_vv_u8mf8(...) __riscv_vaaddu_vv_u8mf8(__VA_ARGS__) -#define vaaddu_vx_u8mf8(...) __riscv_vaaddu_vx_u8mf8(__VA_ARGS__) -#define vaaddu_vv_u8mf4(...) __riscv_vaaddu_vv_u8mf4(__VA_ARGS__) -#define vaaddu_vx_u8mf4(...) __riscv_vaaddu_vx_u8mf4(__VA_ARGS__) -#define vaaddu_vv_u8mf2(...) __riscv_vaaddu_vv_u8mf2(__VA_ARGS__) -#define vaaddu_vx_u8mf2(...) __riscv_vaaddu_vx_u8mf2(__VA_ARGS__) -#define vaaddu_vv_u8m1(...) __riscv_vaaddu_vv_u8m1(__VA_ARGS__) -#define vaaddu_vx_u8m1(...) __riscv_vaaddu_vx_u8m1(__VA_ARGS__) -#define vaaddu_vv_u8m2(...) __riscv_vaaddu_vv_u8m2(__VA_ARGS__) -#define vaaddu_vx_u8m2(...) __riscv_vaaddu_vx_u8m2(__VA_ARGS__) -#define vaaddu_vv_u8m4(...) __riscv_vaaddu_vv_u8m4(__VA_ARGS__) -#define vaaddu_vx_u8m4(...) __riscv_vaaddu_vx_u8m4(__VA_ARGS__) -#define vaaddu_vv_u8m8(...) __riscv_vaaddu_vv_u8m8(__VA_ARGS__) -#define vaaddu_vx_u8m8(...) __riscv_vaaddu_vx_u8m8(__VA_ARGS__) -#define vaaddu_vv_u16mf4(...) __riscv_vaaddu_vv_u16mf4(__VA_ARGS__) -#define vaaddu_vx_u16mf4(...) __riscv_vaaddu_vx_u16mf4(__VA_ARGS__) -#define vaaddu_vv_u16mf2(...) __riscv_vaaddu_vv_u16mf2(__VA_ARGS__) -#define vaaddu_vx_u16mf2(...) __riscv_vaaddu_vx_u16mf2(__VA_ARGS__) -#define vaaddu_vv_u16m1(...) __riscv_vaaddu_vv_u16m1(__VA_ARGS__) -#define vaaddu_vx_u16m1(...) __riscv_vaaddu_vx_u16m1(__VA_ARGS__) -#define vaaddu_vv_u16m2(...) __riscv_vaaddu_vv_u16m2(__VA_ARGS__) -#define vaaddu_vx_u16m2(...) __riscv_vaaddu_vx_u16m2(__VA_ARGS__) -#define vaaddu_vv_u16m4(...) __riscv_vaaddu_vv_u16m4(__VA_ARGS__) -#define vaaddu_vx_u16m4(...) __riscv_vaaddu_vx_u16m4(__VA_ARGS__) -#define vaaddu_vv_u16m8(...) __riscv_vaaddu_vv_u16m8(__VA_ARGS__) -#define vaaddu_vx_u16m8(...) __riscv_vaaddu_vx_u16m8(__VA_ARGS__) -#define vaaddu_vv_u32mf2(...) __riscv_vaaddu_vv_u32mf2(__VA_ARGS__) -#define vaaddu_vx_u32mf2(...) __riscv_vaaddu_vx_u32mf2(__VA_ARGS__) -#define vaaddu_vv_u32m1(...) __riscv_vaaddu_vv_u32m1(__VA_ARGS__) -#define vaaddu_vx_u32m1(...) __riscv_vaaddu_vx_u32m1(__VA_ARGS__) -#define vaaddu_vv_u32m2(...) __riscv_vaaddu_vv_u32m2(__VA_ARGS__) -#define vaaddu_vx_u32m2(...) __riscv_vaaddu_vx_u32m2(__VA_ARGS__) -#define vaaddu_vv_u32m4(...) __riscv_vaaddu_vv_u32m4(__VA_ARGS__) -#define vaaddu_vx_u32m4(...) __riscv_vaaddu_vx_u32m4(__VA_ARGS__) -#define vaaddu_vv_u32m8(...) __riscv_vaaddu_vv_u32m8(__VA_ARGS__) -#define vaaddu_vx_u32m8(...) __riscv_vaaddu_vx_u32m8(__VA_ARGS__) -#define vaaddu_vv_u64m1(...) __riscv_vaaddu_vv_u64m1(__VA_ARGS__) -#define vaaddu_vx_u64m1(...) __riscv_vaaddu_vx_u64m1(__VA_ARGS__) -#define vaaddu_vv_u64m2(...) __riscv_vaaddu_vv_u64m2(__VA_ARGS__) -#define vaaddu_vx_u64m2(...) __riscv_vaaddu_vx_u64m2(__VA_ARGS__) -#define vaaddu_vv_u64m4(...) __riscv_vaaddu_vv_u64m4(__VA_ARGS__) -#define vaaddu_vx_u64m4(...) __riscv_vaaddu_vx_u64m4(__VA_ARGS__) -#define vaaddu_vv_u64m8(...) __riscv_vaaddu_vv_u64m8(__VA_ARGS__) -#define vaaddu_vx_u64m8(...) __riscv_vaaddu_vx_u64m8(__VA_ARGS__) -#define vasubu_vv_u8mf8(...) __riscv_vasubu_vv_u8mf8(__VA_ARGS__) -#define vasubu_vx_u8mf8(...) __riscv_vasubu_vx_u8mf8(__VA_ARGS__) -#define vasubu_vv_u8mf4(...) __riscv_vasubu_vv_u8mf4(__VA_ARGS__) -#define vasubu_vx_u8mf4(...) __riscv_vasubu_vx_u8mf4(__VA_ARGS__) -#define vasubu_vv_u8mf2(...) __riscv_vasubu_vv_u8mf2(__VA_ARGS__) -#define vasubu_vx_u8mf2(...) __riscv_vasubu_vx_u8mf2(__VA_ARGS__) -#define vasubu_vv_u8m1(...) __riscv_vasubu_vv_u8m1(__VA_ARGS__) -#define vasubu_vx_u8m1(...) __riscv_vasubu_vx_u8m1(__VA_ARGS__) -#define vasubu_vv_u8m2(...) __riscv_vasubu_vv_u8m2(__VA_ARGS__) -#define vasubu_vx_u8m2(...) __riscv_vasubu_vx_u8m2(__VA_ARGS__) -#define vasubu_vv_u8m4(...) __riscv_vasubu_vv_u8m4(__VA_ARGS__) -#define vasubu_vx_u8m4(...) __riscv_vasubu_vx_u8m4(__VA_ARGS__) -#define vasubu_vv_u8m8(...) __riscv_vasubu_vv_u8m8(__VA_ARGS__) -#define vasubu_vx_u8m8(...) __riscv_vasubu_vx_u8m8(__VA_ARGS__) -#define vasubu_vv_u16mf4(...) __riscv_vasubu_vv_u16mf4(__VA_ARGS__) -#define vasubu_vx_u16mf4(...) __riscv_vasubu_vx_u16mf4(__VA_ARGS__) -#define vasubu_vv_u16mf2(...) __riscv_vasubu_vv_u16mf2(__VA_ARGS__) -#define vasubu_vx_u16mf2(...) __riscv_vasubu_vx_u16mf2(__VA_ARGS__) -#define vasubu_vv_u16m1(...) __riscv_vasubu_vv_u16m1(__VA_ARGS__) -#define vasubu_vx_u16m1(...) __riscv_vasubu_vx_u16m1(__VA_ARGS__) -#define vasubu_vv_u16m2(...) __riscv_vasubu_vv_u16m2(__VA_ARGS__) -#define vasubu_vx_u16m2(...) __riscv_vasubu_vx_u16m2(__VA_ARGS__) -#define vasubu_vv_u16m4(...) __riscv_vasubu_vv_u16m4(__VA_ARGS__) -#define vasubu_vx_u16m4(...) __riscv_vasubu_vx_u16m4(__VA_ARGS__) -#define vasubu_vv_u16m8(...) __riscv_vasubu_vv_u16m8(__VA_ARGS__) -#define vasubu_vx_u16m8(...) __riscv_vasubu_vx_u16m8(__VA_ARGS__) -#define vasubu_vv_u32mf2(...) __riscv_vasubu_vv_u32mf2(__VA_ARGS__) -#define vasubu_vx_u32mf2(...) __riscv_vasubu_vx_u32mf2(__VA_ARGS__) -#define vasubu_vv_u32m1(...) __riscv_vasubu_vv_u32m1(__VA_ARGS__) -#define vasubu_vx_u32m1(...) __riscv_vasubu_vx_u32m1(__VA_ARGS__) -#define vasubu_vv_u32m2(...) __riscv_vasubu_vv_u32m2(__VA_ARGS__) -#define vasubu_vx_u32m2(...) __riscv_vasubu_vx_u32m2(__VA_ARGS__) -#define vasubu_vv_u32m4(...) __riscv_vasubu_vv_u32m4(__VA_ARGS__) -#define vasubu_vx_u32m4(...) __riscv_vasubu_vx_u32m4(__VA_ARGS__) -#define vasubu_vv_u32m8(...) __riscv_vasubu_vv_u32m8(__VA_ARGS__) -#define vasubu_vx_u32m8(...) __riscv_vasubu_vx_u32m8(__VA_ARGS__) -#define vasubu_vv_u64m1(...) __riscv_vasubu_vv_u64m1(__VA_ARGS__) -#define vasubu_vx_u64m1(...) __riscv_vasubu_vx_u64m1(__VA_ARGS__) -#define vasubu_vv_u64m2(...) __riscv_vasubu_vv_u64m2(__VA_ARGS__) -#define vasubu_vx_u64m2(...) __riscv_vasubu_vx_u64m2(__VA_ARGS__) -#define vasubu_vv_u64m4(...) __riscv_vasubu_vv_u64m4(__VA_ARGS__) -#define vasubu_vx_u64m4(...) __riscv_vasubu_vx_u64m4(__VA_ARGS__) -#define vasubu_vv_u64m8(...) __riscv_vasubu_vv_u64m8(__VA_ARGS__) -#define vasubu_vx_u64m8(...) __riscv_vasubu_vx_u64m8(__VA_ARGS__) -// masked functions -#define vaadd_vv_i8mf8_m(...) __riscv_vaadd_vv_i8mf8_tumu(__VA_ARGS__) -#define vaadd_vx_i8mf8_m(...) __riscv_vaadd_vx_i8mf8_tumu(__VA_ARGS__) -#define vaadd_vv_i8mf4_m(...) __riscv_vaadd_vv_i8mf4_tumu(__VA_ARGS__) -#define vaadd_vx_i8mf4_m(...) __riscv_vaadd_vx_i8mf4_tumu(__VA_ARGS__) -#define vaadd_vv_i8mf2_m(...) __riscv_vaadd_vv_i8mf2_tumu(__VA_ARGS__) -#define vaadd_vx_i8mf2_m(...) __riscv_vaadd_vx_i8mf2_tumu(__VA_ARGS__) -#define vaadd_vv_i8m1_m(...) __riscv_vaadd_vv_i8m1_tumu(__VA_ARGS__) -#define vaadd_vx_i8m1_m(...) __riscv_vaadd_vx_i8m1_tumu(__VA_ARGS__) -#define vaadd_vv_i8m2_m(...) __riscv_vaadd_vv_i8m2_tumu(__VA_ARGS__) -#define vaadd_vx_i8m2_m(...) __riscv_vaadd_vx_i8m2_tumu(__VA_ARGS__) -#define vaadd_vv_i8m4_m(...) __riscv_vaadd_vv_i8m4_tumu(__VA_ARGS__) -#define vaadd_vx_i8m4_m(...) __riscv_vaadd_vx_i8m4_tumu(__VA_ARGS__) -#define vaadd_vv_i8m8_m(...) __riscv_vaadd_vv_i8m8_tumu(__VA_ARGS__) -#define vaadd_vx_i8m8_m(...) __riscv_vaadd_vx_i8m8_tumu(__VA_ARGS__) -#define vaadd_vv_i16mf4_m(...) __riscv_vaadd_vv_i16mf4_tumu(__VA_ARGS__) -#define vaadd_vx_i16mf4_m(...) __riscv_vaadd_vx_i16mf4_tumu(__VA_ARGS__) -#define vaadd_vv_i16mf2_m(...) __riscv_vaadd_vv_i16mf2_tumu(__VA_ARGS__) -#define vaadd_vx_i16mf2_m(...) __riscv_vaadd_vx_i16mf2_tumu(__VA_ARGS__) -#define vaadd_vv_i16m1_m(...) __riscv_vaadd_vv_i16m1_tumu(__VA_ARGS__) -#define vaadd_vx_i16m1_m(...) __riscv_vaadd_vx_i16m1_tumu(__VA_ARGS__) -#define vaadd_vv_i16m2_m(...) __riscv_vaadd_vv_i16m2_tumu(__VA_ARGS__) -#define vaadd_vx_i16m2_m(...) __riscv_vaadd_vx_i16m2_tumu(__VA_ARGS__) -#define vaadd_vv_i16m4_m(...) __riscv_vaadd_vv_i16m4_tumu(__VA_ARGS__) -#define vaadd_vx_i16m4_m(...) __riscv_vaadd_vx_i16m4_tumu(__VA_ARGS__) -#define vaadd_vv_i16m8_m(...) __riscv_vaadd_vv_i16m8_tumu(__VA_ARGS__) -#define vaadd_vx_i16m8_m(...) __riscv_vaadd_vx_i16m8_tumu(__VA_ARGS__) -#define vaadd_vv_i32mf2_m(...) __riscv_vaadd_vv_i32mf2_tumu(__VA_ARGS__) -#define vaadd_vx_i32mf2_m(...) __riscv_vaadd_vx_i32mf2_tumu(__VA_ARGS__) -#define vaadd_vv_i32m1_m(...) __riscv_vaadd_vv_i32m1_tumu(__VA_ARGS__) -#define vaadd_vx_i32m1_m(...) __riscv_vaadd_vx_i32m1_tumu(__VA_ARGS__) -#define vaadd_vv_i32m2_m(...) __riscv_vaadd_vv_i32m2_tumu(__VA_ARGS__) -#define vaadd_vx_i32m2_m(...) __riscv_vaadd_vx_i32m2_tumu(__VA_ARGS__) -#define vaadd_vv_i32m4_m(...) __riscv_vaadd_vv_i32m4_tumu(__VA_ARGS__) -#define vaadd_vx_i32m4_m(...) __riscv_vaadd_vx_i32m4_tumu(__VA_ARGS__) -#define vaadd_vv_i32m8_m(...) __riscv_vaadd_vv_i32m8_tumu(__VA_ARGS__) -#define vaadd_vx_i32m8_m(...) __riscv_vaadd_vx_i32m8_tumu(__VA_ARGS__) -#define vaadd_vv_i64m1_m(...) __riscv_vaadd_vv_i64m1_tumu(__VA_ARGS__) -#define vaadd_vx_i64m1_m(...) __riscv_vaadd_vx_i64m1_tumu(__VA_ARGS__) -#define vaadd_vv_i64m2_m(...) __riscv_vaadd_vv_i64m2_tumu(__VA_ARGS__) -#define vaadd_vx_i64m2_m(...) __riscv_vaadd_vx_i64m2_tumu(__VA_ARGS__) -#define vaadd_vv_i64m4_m(...) __riscv_vaadd_vv_i64m4_tumu(__VA_ARGS__) -#define vaadd_vx_i64m4_m(...) __riscv_vaadd_vx_i64m4_tumu(__VA_ARGS__) -#define vaadd_vv_i64m8_m(...) __riscv_vaadd_vv_i64m8_tumu(__VA_ARGS__) -#define vaadd_vx_i64m8_m(...) __riscv_vaadd_vx_i64m8_tumu(__VA_ARGS__) -#define vasub_vv_i8mf8_m(...) __riscv_vasub_vv_i8mf8_tumu(__VA_ARGS__) -#define vasub_vx_i8mf8_m(...) __riscv_vasub_vx_i8mf8_tumu(__VA_ARGS__) -#define vasub_vv_i8mf4_m(...) __riscv_vasub_vv_i8mf4_tumu(__VA_ARGS__) -#define vasub_vx_i8mf4_m(...) __riscv_vasub_vx_i8mf4_tumu(__VA_ARGS__) -#define vasub_vv_i8mf2_m(...) __riscv_vasub_vv_i8mf2_tumu(__VA_ARGS__) -#define vasub_vx_i8mf2_m(...) __riscv_vasub_vx_i8mf2_tumu(__VA_ARGS__) -#define vasub_vv_i8m1_m(...) __riscv_vasub_vv_i8m1_tumu(__VA_ARGS__) -#define vasub_vx_i8m1_m(...) __riscv_vasub_vx_i8m1_tumu(__VA_ARGS__) -#define vasub_vv_i8m2_m(...) __riscv_vasub_vv_i8m2_tumu(__VA_ARGS__) -#define vasub_vx_i8m2_m(...) __riscv_vasub_vx_i8m2_tumu(__VA_ARGS__) -#define vasub_vv_i8m4_m(...) __riscv_vasub_vv_i8m4_tumu(__VA_ARGS__) -#define vasub_vx_i8m4_m(...) __riscv_vasub_vx_i8m4_tumu(__VA_ARGS__) -#define vasub_vv_i8m8_m(...) __riscv_vasub_vv_i8m8_tumu(__VA_ARGS__) -#define vasub_vx_i8m8_m(...) __riscv_vasub_vx_i8m8_tumu(__VA_ARGS__) -#define vasub_vv_i16mf4_m(...) __riscv_vasub_vv_i16mf4_tumu(__VA_ARGS__) -#define vasub_vx_i16mf4_m(...) __riscv_vasub_vx_i16mf4_tumu(__VA_ARGS__) -#define vasub_vv_i16mf2_m(...) __riscv_vasub_vv_i16mf2_tumu(__VA_ARGS__) -#define vasub_vx_i16mf2_m(...) __riscv_vasub_vx_i16mf2_tumu(__VA_ARGS__) -#define vasub_vv_i16m1_m(...) __riscv_vasub_vv_i16m1_tumu(__VA_ARGS__) -#define vasub_vx_i16m1_m(...) __riscv_vasub_vx_i16m1_tumu(__VA_ARGS__) -#define vasub_vv_i16m2_m(...) __riscv_vasub_vv_i16m2_tumu(__VA_ARGS__) -#define vasub_vx_i16m2_m(...) __riscv_vasub_vx_i16m2_tumu(__VA_ARGS__) -#define vasub_vv_i16m4_m(...) __riscv_vasub_vv_i16m4_tumu(__VA_ARGS__) -#define vasub_vx_i16m4_m(...) __riscv_vasub_vx_i16m4_tumu(__VA_ARGS__) -#define vasub_vv_i16m8_m(...) __riscv_vasub_vv_i16m8_tumu(__VA_ARGS__) -#define vasub_vx_i16m8_m(...) __riscv_vasub_vx_i16m8_tumu(__VA_ARGS__) -#define vasub_vv_i32mf2_m(...) __riscv_vasub_vv_i32mf2_tumu(__VA_ARGS__) -#define vasub_vx_i32mf2_m(...) __riscv_vasub_vx_i32mf2_tumu(__VA_ARGS__) -#define vasub_vv_i32m1_m(...) __riscv_vasub_vv_i32m1_tumu(__VA_ARGS__) -#define vasub_vx_i32m1_m(...) __riscv_vasub_vx_i32m1_tumu(__VA_ARGS__) -#define vasub_vv_i32m2_m(...) __riscv_vasub_vv_i32m2_tumu(__VA_ARGS__) -#define vasub_vx_i32m2_m(...) __riscv_vasub_vx_i32m2_tumu(__VA_ARGS__) -#define vasub_vv_i32m4_m(...) __riscv_vasub_vv_i32m4_tumu(__VA_ARGS__) -#define vasub_vx_i32m4_m(...) __riscv_vasub_vx_i32m4_tumu(__VA_ARGS__) -#define vasub_vv_i32m8_m(...) __riscv_vasub_vv_i32m8_tumu(__VA_ARGS__) -#define vasub_vx_i32m8_m(...) __riscv_vasub_vx_i32m8_tumu(__VA_ARGS__) -#define vasub_vv_i64m1_m(...) __riscv_vasub_vv_i64m1_tumu(__VA_ARGS__) -#define vasub_vx_i64m1_m(...) __riscv_vasub_vx_i64m1_tumu(__VA_ARGS__) -#define vasub_vv_i64m2_m(...) __riscv_vasub_vv_i64m2_tumu(__VA_ARGS__) -#define vasub_vx_i64m2_m(...) __riscv_vasub_vx_i64m2_tumu(__VA_ARGS__) -#define vasub_vv_i64m4_m(...) __riscv_vasub_vv_i64m4_tumu(__VA_ARGS__) -#define vasub_vx_i64m4_m(...) __riscv_vasub_vx_i64m4_tumu(__VA_ARGS__) -#define vasub_vv_i64m8_m(...) __riscv_vasub_vv_i64m8_tumu(__VA_ARGS__) -#define vasub_vx_i64m8_m(...) __riscv_vasub_vx_i64m8_tumu(__VA_ARGS__) -#define vaaddu_vv_u8mf8_m(...) __riscv_vaaddu_vv_u8mf8_tumu(__VA_ARGS__) -#define vaaddu_vx_u8mf8_m(...) __riscv_vaaddu_vx_u8mf8_tumu(__VA_ARGS__) -#define vaaddu_vv_u8mf4_m(...) __riscv_vaaddu_vv_u8mf4_tumu(__VA_ARGS__) -#define vaaddu_vx_u8mf4_m(...) __riscv_vaaddu_vx_u8mf4_tumu(__VA_ARGS__) -#define vaaddu_vv_u8mf2_m(...) __riscv_vaaddu_vv_u8mf2_tumu(__VA_ARGS__) -#define vaaddu_vx_u8mf2_m(...) __riscv_vaaddu_vx_u8mf2_tumu(__VA_ARGS__) -#define vaaddu_vv_u8m1_m(...) __riscv_vaaddu_vv_u8m1_tumu(__VA_ARGS__) -#define vaaddu_vx_u8m1_m(...) __riscv_vaaddu_vx_u8m1_tumu(__VA_ARGS__) -#define vaaddu_vv_u8m2_m(...) __riscv_vaaddu_vv_u8m2_tumu(__VA_ARGS__) -#define vaaddu_vx_u8m2_m(...) __riscv_vaaddu_vx_u8m2_tumu(__VA_ARGS__) -#define vaaddu_vv_u8m4_m(...) __riscv_vaaddu_vv_u8m4_tumu(__VA_ARGS__) -#define vaaddu_vx_u8m4_m(...) __riscv_vaaddu_vx_u8m4_tumu(__VA_ARGS__) -#define vaaddu_vv_u8m8_m(...) __riscv_vaaddu_vv_u8m8_tumu(__VA_ARGS__) -#define vaaddu_vx_u8m8_m(...) __riscv_vaaddu_vx_u8m8_tumu(__VA_ARGS__) -#define vaaddu_vv_u16mf4_m(...) __riscv_vaaddu_vv_u16mf4_tumu(__VA_ARGS__) -#define vaaddu_vx_u16mf4_m(...) __riscv_vaaddu_vx_u16mf4_tumu(__VA_ARGS__) -#define vaaddu_vv_u16mf2_m(...) __riscv_vaaddu_vv_u16mf2_tumu(__VA_ARGS__) -#define vaaddu_vx_u16mf2_m(...) __riscv_vaaddu_vx_u16mf2_tumu(__VA_ARGS__) -#define vaaddu_vv_u16m1_m(...) __riscv_vaaddu_vv_u16m1_tumu(__VA_ARGS__) -#define vaaddu_vx_u16m1_m(...) __riscv_vaaddu_vx_u16m1_tumu(__VA_ARGS__) -#define vaaddu_vv_u16m2_m(...) __riscv_vaaddu_vv_u16m2_tumu(__VA_ARGS__) -#define vaaddu_vx_u16m2_m(...) __riscv_vaaddu_vx_u16m2_tumu(__VA_ARGS__) -#define vaaddu_vv_u16m4_m(...) __riscv_vaaddu_vv_u16m4_tumu(__VA_ARGS__) -#define vaaddu_vx_u16m4_m(...) __riscv_vaaddu_vx_u16m4_tumu(__VA_ARGS__) -#define vaaddu_vv_u16m8_m(...) __riscv_vaaddu_vv_u16m8_tumu(__VA_ARGS__) -#define vaaddu_vx_u16m8_m(...) __riscv_vaaddu_vx_u16m8_tumu(__VA_ARGS__) -#define vaaddu_vv_u32mf2_m(...) __riscv_vaaddu_vv_u32mf2_tumu(__VA_ARGS__) -#define vaaddu_vx_u32mf2_m(...) __riscv_vaaddu_vx_u32mf2_tumu(__VA_ARGS__) -#define vaaddu_vv_u32m1_m(...) __riscv_vaaddu_vv_u32m1_tumu(__VA_ARGS__) -#define vaaddu_vx_u32m1_m(...) __riscv_vaaddu_vx_u32m1_tumu(__VA_ARGS__) -#define vaaddu_vv_u32m2_m(...) __riscv_vaaddu_vv_u32m2_tumu(__VA_ARGS__) -#define vaaddu_vx_u32m2_m(...) __riscv_vaaddu_vx_u32m2_tumu(__VA_ARGS__) -#define vaaddu_vv_u32m4_m(...) __riscv_vaaddu_vv_u32m4_tumu(__VA_ARGS__) -#define vaaddu_vx_u32m4_m(...) __riscv_vaaddu_vx_u32m4_tumu(__VA_ARGS__) -#define vaaddu_vv_u32m8_m(...) __riscv_vaaddu_vv_u32m8_tumu(__VA_ARGS__) -#define vaaddu_vx_u32m8_m(...) __riscv_vaaddu_vx_u32m8_tumu(__VA_ARGS__) -#define vaaddu_vv_u64m1_m(...) __riscv_vaaddu_vv_u64m1_tumu(__VA_ARGS__) -#define vaaddu_vx_u64m1_m(...) __riscv_vaaddu_vx_u64m1_tumu(__VA_ARGS__) -#define vaaddu_vv_u64m2_m(...) __riscv_vaaddu_vv_u64m2_tumu(__VA_ARGS__) -#define vaaddu_vx_u64m2_m(...) __riscv_vaaddu_vx_u64m2_tumu(__VA_ARGS__) -#define vaaddu_vv_u64m4_m(...) __riscv_vaaddu_vv_u64m4_tumu(__VA_ARGS__) -#define vaaddu_vx_u64m4_m(...) __riscv_vaaddu_vx_u64m4_tumu(__VA_ARGS__) -#define vaaddu_vv_u64m8_m(...) __riscv_vaaddu_vv_u64m8_tumu(__VA_ARGS__) -#define vaaddu_vx_u64m8_m(...) __riscv_vaaddu_vx_u64m8_tumu(__VA_ARGS__) -#define vasubu_vv_u8mf8_m(...) __riscv_vasubu_vv_u8mf8_tumu(__VA_ARGS__) -#define vasubu_vx_u8mf8_m(...) __riscv_vasubu_vx_u8mf8_tumu(__VA_ARGS__) -#define vasubu_vv_u8mf4_m(...) __riscv_vasubu_vv_u8mf4_tumu(__VA_ARGS__) -#define vasubu_vx_u8mf4_m(...) __riscv_vasubu_vx_u8mf4_tumu(__VA_ARGS__) -#define vasubu_vv_u8mf2_m(...) __riscv_vasubu_vv_u8mf2_tumu(__VA_ARGS__) -#define vasubu_vx_u8mf2_m(...) __riscv_vasubu_vx_u8mf2_tumu(__VA_ARGS__) -#define vasubu_vv_u8m1_m(...) __riscv_vasubu_vv_u8m1_tumu(__VA_ARGS__) -#define vasubu_vx_u8m1_m(...) __riscv_vasubu_vx_u8m1_tumu(__VA_ARGS__) -#define vasubu_vv_u8m2_m(...) __riscv_vasubu_vv_u8m2_tumu(__VA_ARGS__) -#define vasubu_vx_u8m2_m(...) __riscv_vasubu_vx_u8m2_tumu(__VA_ARGS__) -#define vasubu_vv_u8m4_m(...) __riscv_vasubu_vv_u8m4_tumu(__VA_ARGS__) -#define vasubu_vx_u8m4_m(...) __riscv_vasubu_vx_u8m4_tumu(__VA_ARGS__) -#define vasubu_vv_u8m8_m(...) __riscv_vasubu_vv_u8m8_tumu(__VA_ARGS__) -#define vasubu_vx_u8m8_m(...) __riscv_vasubu_vx_u8m8_tumu(__VA_ARGS__) -#define vasubu_vv_u16mf4_m(...) __riscv_vasubu_vv_u16mf4_tumu(__VA_ARGS__) -#define vasubu_vx_u16mf4_m(...) __riscv_vasubu_vx_u16mf4_tumu(__VA_ARGS__) -#define vasubu_vv_u16mf2_m(...) __riscv_vasubu_vv_u16mf2_tumu(__VA_ARGS__) -#define vasubu_vx_u16mf2_m(...) __riscv_vasubu_vx_u16mf2_tumu(__VA_ARGS__) -#define vasubu_vv_u16m1_m(...) __riscv_vasubu_vv_u16m1_tumu(__VA_ARGS__) -#define vasubu_vx_u16m1_m(...) __riscv_vasubu_vx_u16m1_tumu(__VA_ARGS__) -#define vasubu_vv_u16m2_m(...) __riscv_vasubu_vv_u16m2_tumu(__VA_ARGS__) -#define vasubu_vx_u16m2_m(...) __riscv_vasubu_vx_u16m2_tumu(__VA_ARGS__) -#define vasubu_vv_u16m4_m(...) __riscv_vasubu_vv_u16m4_tumu(__VA_ARGS__) -#define vasubu_vx_u16m4_m(...) __riscv_vasubu_vx_u16m4_tumu(__VA_ARGS__) -#define vasubu_vv_u16m8_m(...) __riscv_vasubu_vv_u16m8_tumu(__VA_ARGS__) -#define vasubu_vx_u16m8_m(...) __riscv_vasubu_vx_u16m8_tumu(__VA_ARGS__) -#define vasubu_vv_u32mf2_m(...) __riscv_vasubu_vv_u32mf2_tumu(__VA_ARGS__) -#define vasubu_vx_u32mf2_m(...) __riscv_vasubu_vx_u32mf2_tumu(__VA_ARGS__) -#define vasubu_vv_u32m1_m(...) __riscv_vasubu_vv_u32m1_tumu(__VA_ARGS__) -#define vasubu_vx_u32m1_m(...) __riscv_vasubu_vx_u32m1_tumu(__VA_ARGS__) -#define vasubu_vv_u32m2_m(...) __riscv_vasubu_vv_u32m2_tumu(__VA_ARGS__) -#define vasubu_vx_u32m2_m(...) __riscv_vasubu_vx_u32m2_tumu(__VA_ARGS__) -#define vasubu_vv_u32m4_m(...) __riscv_vasubu_vv_u32m4_tumu(__VA_ARGS__) -#define vasubu_vx_u32m4_m(...) __riscv_vasubu_vx_u32m4_tumu(__VA_ARGS__) -#define vasubu_vv_u32m8_m(...) __riscv_vasubu_vv_u32m8_tumu(__VA_ARGS__) -#define vasubu_vx_u32m8_m(...) __riscv_vasubu_vx_u32m8_tumu(__VA_ARGS__) -#define vasubu_vv_u64m1_m(...) __riscv_vasubu_vv_u64m1_tumu(__VA_ARGS__) -#define vasubu_vx_u64m1_m(...) __riscv_vasubu_vx_u64m1_tumu(__VA_ARGS__) -#define vasubu_vv_u64m2_m(...) __riscv_vasubu_vv_u64m2_tumu(__VA_ARGS__) -#define vasubu_vx_u64m2_m(...) __riscv_vasubu_vx_u64m2_tumu(__VA_ARGS__) -#define vasubu_vv_u64m4_m(...) __riscv_vasubu_vv_u64m4_tumu(__VA_ARGS__) -#define vasubu_vx_u64m4_m(...) __riscv_vasubu_vx_u64m4_tumu(__VA_ARGS__) -#define vasubu_vv_u64m8_m(...) __riscv_vasubu_vv_u64m8_tumu(__VA_ARGS__) -#define vasubu_vx_u64m8_m(...) __riscv_vasubu_vx_u64m8_tumu(__VA_ARGS__) -#define vsmul_vv_i8mf8(...) __riscv_vsmul_vv_i8mf8(__VA_ARGS__) -#define vsmul_vx_i8mf8(...) __riscv_vsmul_vx_i8mf8(__VA_ARGS__) -#define vsmul_vv_i8mf4(...) __riscv_vsmul_vv_i8mf4(__VA_ARGS__) -#define vsmul_vx_i8mf4(...) __riscv_vsmul_vx_i8mf4(__VA_ARGS__) -#define vsmul_vv_i8mf2(...) __riscv_vsmul_vv_i8mf2(__VA_ARGS__) -#define vsmul_vx_i8mf2(...) __riscv_vsmul_vx_i8mf2(__VA_ARGS__) -#define vsmul_vv_i8m1(...) __riscv_vsmul_vv_i8m1(__VA_ARGS__) -#define vsmul_vx_i8m1(...) __riscv_vsmul_vx_i8m1(__VA_ARGS__) -#define vsmul_vv_i8m2(...) __riscv_vsmul_vv_i8m2(__VA_ARGS__) -#define vsmul_vx_i8m2(...) __riscv_vsmul_vx_i8m2(__VA_ARGS__) -#define vsmul_vv_i8m4(...) __riscv_vsmul_vv_i8m4(__VA_ARGS__) -#define vsmul_vx_i8m4(...) __riscv_vsmul_vx_i8m4(__VA_ARGS__) -#define vsmul_vv_i8m8(...) __riscv_vsmul_vv_i8m8(__VA_ARGS__) -#define vsmul_vx_i8m8(...) __riscv_vsmul_vx_i8m8(__VA_ARGS__) -#define vsmul_vv_i16mf4(...) __riscv_vsmul_vv_i16mf4(__VA_ARGS__) -#define vsmul_vx_i16mf4(...) __riscv_vsmul_vx_i16mf4(__VA_ARGS__) -#define vsmul_vv_i16mf2(...) __riscv_vsmul_vv_i16mf2(__VA_ARGS__) -#define vsmul_vx_i16mf2(...) __riscv_vsmul_vx_i16mf2(__VA_ARGS__) -#define vsmul_vv_i16m1(...) __riscv_vsmul_vv_i16m1(__VA_ARGS__) -#define vsmul_vx_i16m1(...) __riscv_vsmul_vx_i16m1(__VA_ARGS__) -#define vsmul_vv_i16m2(...) __riscv_vsmul_vv_i16m2(__VA_ARGS__) -#define vsmul_vx_i16m2(...) __riscv_vsmul_vx_i16m2(__VA_ARGS__) -#define vsmul_vv_i16m4(...) __riscv_vsmul_vv_i16m4(__VA_ARGS__) -#define vsmul_vx_i16m4(...) __riscv_vsmul_vx_i16m4(__VA_ARGS__) -#define vsmul_vv_i16m8(...) __riscv_vsmul_vv_i16m8(__VA_ARGS__) -#define vsmul_vx_i16m8(...) __riscv_vsmul_vx_i16m8(__VA_ARGS__) -#define vsmul_vv_i32mf2(...) __riscv_vsmul_vv_i32mf2(__VA_ARGS__) -#define vsmul_vx_i32mf2(...) __riscv_vsmul_vx_i32mf2(__VA_ARGS__) -#define vsmul_vv_i32m1(...) __riscv_vsmul_vv_i32m1(__VA_ARGS__) -#define vsmul_vx_i32m1(...) __riscv_vsmul_vx_i32m1(__VA_ARGS__) -#define vsmul_vv_i32m2(...) __riscv_vsmul_vv_i32m2(__VA_ARGS__) -#define vsmul_vx_i32m2(...) __riscv_vsmul_vx_i32m2(__VA_ARGS__) -#define vsmul_vv_i32m4(...) __riscv_vsmul_vv_i32m4(__VA_ARGS__) -#define vsmul_vx_i32m4(...) __riscv_vsmul_vx_i32m4(__VA_ARGS__) -#define vsmul_vv_i32m8(...) __riscv_vsmul_vv_i32m8(__VA_ARGS__) -#define vsmul_vx_i32m8(...) __riscv_vsmul_vx_i32m8(__VA_ARGS__) -#define vsmul_vv_i64m1(...) __riscv_vsmul_vv_i64m1(__VA_ARGS__) -#define vsmul_vx_i64m1(...) __riscv_vsmul_vx_i64m1(__VA_ARGS__) -#define vsmul_vv_i64m2(...) __riscv_vsmul_vv_i64m2(__VA_ARGS__) -#define vsmul_vx_i64m2(...) __riscv_vsmul_vx_i64m2(__VA_ARGS__) -#define vsmul_vv_i64m4(...) __riscv_vsmul_vv_i64m4(__VA_ARGS__) -#define vsmul_vx_i64m4(...) __riscv_vsmul_vx_i64m4(__VA_ARGS__) -#define vsmul_vv_i64m8(...) __riscv_vsmul_vv_i64m8(__VA_ARGS__) -#define vsmul_vx_i64m8(...) __riscv_vsmul_vx_i64m8(__VA_ARGS__) -// masked functions -#define vsmul_vv_i8mf8_m(...) __riscv_vsmul_vv_i8mf8_mu(__VA_ARGS__) -#define vsmul_vx_i8mf8_m(...) __riscv_vsmul_vx_i8mf8_mu(__VA_ARGS__) -#define vsmul_vv_i8mf4_m(...) __riscv_vsmul_vv_i8mf4_mu(__VA_ARGS__) -#define vsmul_vx_i8mf4_m(...) __riscv_vsmul_vx_i8mf4_mu(__VA_ARGS__) -#define vsmul_vv_i8mf2_m(...) __riscv_vsmul_vv_i8mf2_mu(__VA_ARGS__) -#define vsmul_vx_i8mf2_m(...) __riscv_vsmul_vx_i8mf2_mu(__VA_ARGS__) -#define vsmul_vv_i8m1_m(...) __riscv_vsmul_vv_i8m1_mu(__VA_ARGS__) -#define vsmul_vx_i8m1_m(...) __riscv_vsmul_vx_i8m1_mu(__VA_ARGS__) -#define vsmul_vv_i8m2_m(...) __riscv_vsmul_vv_i8m2_mu(__VA_ARGS__) -#define vsmul_vx_i8m2_m(...) __riscv_vsmul_vx_i8m2_mu(__VA_ARGS__) -#define vsmul_vv_i8m4_m(...) __riscv_vsmul_vv_i8m4_mu(__VA_ARGS__) -#define vsmul_vx_i8m4_m(...) __riscv_vsmul_vx_i8m4_mu(__VA_ARGS__) -#define vsmul_vv_i8m8_m(...) __riscv_vsmul_vv_i8m8_mu(__VA_ARGS__) -#define vsmul_vx_i8m8_m(...) __riscv_vsmul_vx_i8m8_mu(__VA_ARGS__) -#define vsmul_vv_i16mf4_m(...) __riscv_vsmul_vv_i16mf4_mu(__VA_ARGS__) -#define vsmul_vx_i16mf4_m(...) __riscv_vsmul_vx_i16mf4_mu(__VA_ARGS__) -#define vsmul_vv_i16mf2_m(...) __riscv_vsmul_vv_i16mf2_mu(__VA_ARGS__) -#define vsmul_vx_i16mf2_m(...) __riscv_vsmul_vx_i16mf2_mu(__VA_ARGS__) -#define vsmul_vv_i16m1_m(...) __riscv_vsmul_vv_i16m1_mu(__VA_ARGS__) -#define vsmul_vx_i16m1_m(...) __riscv_vsmul_vx_i16m1_mu(__VA_ARGS__) -#define vsmul_vv_i16m2_m(...) __riscv_vsmul_vv_i16m2_mu(__VA_ARGS__) -#define vsmul_vx_i16m2_m(...) __riscv_vsmul_vx_i16m2_mu(__VA_ARGS__) -#define vsmul_vv_i16m4_m(...) __riscv_vsmul_vv_i16m4_mu(__VA_ARGS__) -#define vsmul_vx_i16m4_m(...) __riscv_vsmul_vx_i16m4_mu(__VA_ARGS__) -#define vsmul_vv_i16m8_m(...) __riscv_vsmul_vv_i16m8_mu(__VA_ARGS__) -#define vsmul_vx_i16m8_m(...) __riscv_vsmul_vx_i16m8_mu(__VA_ARGS__) -#define vsmul_vv_i32mf2_m(...) __riscv_vsmul_vv_i32mf2_mu(__VA_ARGS__) -#define vsmul_vx_i32mf2_m(...) __riscv_vsmul_vx_i32mf2_mu(__VA_ARGS__) -#define vsmul_vv_i32m1_m(...) __riscv_vsmul_vv_i32m1_mu(__VA_ARGS__) -#define vsmul_vx_i32m1_m(...) __riscv_vsmul_vx_i32m1_mu(__VA_ARGS__) -#define vsmul_vv_i32m2_m(...) __riscv_vsmul_vv_i32m2_mu(__VA_ARGS__) -#define vsmul_vx_i32m2_m(...) __riscv_vsmul_vx_i32m2_mu(__VA_ARGS__) -#define vsmul_vv_i32m4_m(...) __riscv_vsmul_vv_i32m4_mu(__VA_ARGS__) -#define vsmul_vx_i32m4_m(...) __riscv_vsmul_vx_i32m4_mu(__VA_ARGS__) -#define vsmul_vv_i32m8_m(...) __riscv_vsmul_vv_i32m8_mu(__VA_ARGS__) -#define vsmul_vx_i32m8_m(...) __riscv_vsmul_vx_i32m8_mu(__VA_ARGS__) -#define vsmul_vv_i64m1_m(...) __riscv_vsmul_vv_i64m1_mu(__VA_ARGS__) -#define vsmul_vx_i64m1_m(...) __riscv_vsmul_vx_i64m1_mu(__VA_ARGS__) -#define vsmul_vv_i64m2_m(...) __riscv_vsmul_vv_i64m2_mu(__VA_ARGS__) -#define vsmul_vx_i64m2_m(...) __riscv_vsmul_vx_i64m2_mu(__VA_ARGS__) -#define vsmul_vv_i64m4_m(...) __riscv_vsmul_vv_i64m4_mu(__VA_ARGS__) -#define vsmul_vx_i64m4_m(...) __riscv_vsmul_vx_i64m4_mu(__VA_ARGS__) -#define vsmul_vv_i64m8_m(...) __riscv_vsmul_vv_i64m8_mu(__VA_ARGS__) -#define vsmul_vx_i64m8_m(...) __riscv_vsmul_vx_i64m8_mu(__VA_ARGS__) -#define vssra_vv_i8mf8(...) __riscv_vssra_vv_i8mf8(__VA_ARGS__) -#define vssra_vx_i8mf8(...) __riscv_vssra_vx_i8mf8(__VA_ARGS__) -#define vssra_vv_i8mf4(...) __riscv_vssra_vv_i8mf4(__VA_ARGS__) -#define vssra_vx_i8mf4(...) __riscv_vssra_vx_i8mf4(__VA_ARGS__) -#define vssra_vv_i8mf2(...) __riscv_vssra_vv_i8mf2(__VA_ARGS__) -#define vssra_vx_i8mf2(...) __riscv_vssra_vx_i8mf2(__VA_ARGS__) -#define vssra_vv_i8m1(...) __riscv_vssra_vv_i8m1(__VA_ARGS__) -#define vssra_vx_i8m1(...) __riscv_vssra_vx_i8m1(__VA_ARGS__) -#define vssra_vv_i8m2(...) __riscv_vssra_vv_i8m2(__VA_ARGS__) -#define vssra_vx_i8m2(...) __riscv_vssra_vx_i8m2(__VA_ARGS__) -#define vssra_vv_i8m4(...) __riscv_vssra_vv_i8m4(__VA_ARGS__) -#define vssra_vx_i8m4(...) __riscv_vssra_vx_i8m4(__VA_ARGS__) -#define vssra_vv_i8m8(...) __riscv_vssra_vv_i8m8(__VA_ARGS__) -#define vssra_vx_i8m8(...) __riscv_vssra_vx_i8m8(__VA_ARGS__) -#define vssra_vv_i16mf4(...) __riscv_vssra_vv_i16mf4(__VA_ARGS__) -#define vssra_vx_i16mf4(...) __riscv_vssra_vx_i16mf4(__VA_ARGS__) -#define vssra_vv_i16mf2(...) __riscv_vssra_vv_i16mf2(__VA_ARGS__) -#define vssra_vx_i16mf2(...) __riscv_vssra_vx_i16mf2(__VA_ARGS__) -#define vssra_vv_i16m1(...) __riscv_vssra_vv_i16m1(__VA_ARGS__) -#define vssra_vx_i16m1(...) __riscv_vssra_vx_i16m1(__VA_ARGS__) -#define vssra_vv_i16m2(...) __riscv_vssra_vv_i16m2(__VA_ARGS__) -#define vssra_vx_i16m2(...) __riscv_vssra_vx_i16m2(__VA_ARGS__) -#define vssra_vv_i16m4(...) __riscv_vssra_vv_i16m4(__VA_ARGS__) -#define vssra_vx_i16m4(...) __riscv_vssra_vx_i16m4(__VA_ARGS__) -#define vssra_vv_i16m8(...) __riscv_vssra_vv_i16m8(__VA_ARGS__) -#define vssra_vx_i16m8(...) __riscv_vssra_vx_i16m8(__VA_ARGS__) -#define vssra_vv_i32mf2(...) __riscv_vssra_vv_i32mf2(__VA_ARGS__) -#define vssra_vx_i32mf2(...) __riscv_vssra_vx_i32mf2(__VA_ARGS__) -#define vssra_vv_i32m1(...) __riscv_vssra_vv_i32m1(__VA_ARGS__) -#define vssra_vx_i32m1(...) __riscv_vssra_vx_i32m1(__VA_ARGS__) -#define vssra_vv_i32m2(...) __riscv_vssra_vv_i32m2(__VA_ARGS__) -#define vssra_vx_i32m2(...) __riscv_vssra_vx_i32m2(__VA_ARGS__) -#define vssra_vv_i32m4(...) __riscv_vssra_vv_i32m4(__VA_ARGS__) -#define vssra_vx_i32m4(...) __riscv_vssra_vx_i32m4(__VA_ARGS__) -#define vssra_vv_i32m8(...) __riscv_vssra_vv_i32m8(__VA_ARGS__) -#define vssra_vx_i32m8(...) __riscv_vssra_vx_i32m8(__VA_ARGS__) -#define vssra_vv_i64m1(...) __riscv_vssra_vv_i64m1(__VA_ARGS__) -#define vssra_vx_i64m1(...) __riscv_vssra_vx_i64m1(__VA_ARGS__) -#define vssra_vv_i64m2(...) __riscv_vssra_vv_i64m2(__VA_ARGS__) -#define vssra_vx_i64m2(...) __riscv_vssra_vx_i64m2(__VA_ARGS__) -#define vssra_vv_i64m4(...) __riscv_vssra_vv_i64m4(__VA_ARGS__) -#define vssra_vx_i64m4(...) __riscv_vssra_vx_i64m4(__VA_ARGS__) -#define vssra_vv_i64m8(...) __riscv_vssra_vv_i64m8(__VA_ARGS__) -#define vssra_vx_i64m8(...) __riscv_vssra_vx_i64m8(__VA_ARGS__) -#define vssrl_vv_u8mf8(...) __riscv_vssrl_vv_u8mf8(__VA_ARGS__) -#define vssrl_vx_u8mf8(...) __riscv_vssrl_vx_u8mf8(__VA_ARGS__) -#define vssrl_vv_u8mf4(...) __riscv_vssrl_vv_u8mf4(__VA_ARGS__) -#define vssrl_vx_u8mf4(...) __riscv_vssrl_vx_u8mf4(__VA_ARGS__) -#define vssrl_vv_u8mf2(...) __riscv_vssrl_vv_u8mf2(__VA_ARGS__) -#define vssrl_vx_u8mf2(...) __riscv_vssrl_vx_u8mf2(__VA_ARGS__) -#define vssrl_vv_u8m1(...) __riscv_vssrl_vv_u8m1(__VA_ARGS__) -#define vssrl_vx_u8m1(...) __riscv_vssrl_vx_u8m1(__VA_ARGS__) -#define vssrl_vv_u8m2(...) __riscv_vssrl_vv_u8m2(__VA_ARGS__) -#define vssrl_vx_u8m2(...) __riscv_vssrl_vx_u8m2(__VA_ARGS__) -#define vssrl_vv_u8m4(...) __riscv_vssrl_vv_u8m4(__VA_ARGS__) -#define vssrl_vx_u8m4(...) __riscv_vssrl_vx_u8m4(__VA_ARGS__) -#define vssrl_vv_u8m8(...) __riscv_vssrl_vv_u8m8(__VA_ARGS__) -#define vssrl_vx_u8m8(...) __riscv_vssrl_vx_u8m8(__VA_ARGS__) -#define vssrl_vv_u16mf4(...) __riscv_vssrl_vv_u16mf4(__VA_ARGS__) -#define vssrl_vx_u16mf4(...) __riscv_vssrl_vx_u16mf4(__VA_ARGS__) -#define vssrl_vv_u16mf2(...) __riscv_vssrl_vv_u16mf2(__VA_ARGS__) -#define vssrl_vx_u16mf2(...) __riscv_vssrl_vx_u16mf2(__VA_ARGS__) -#define vssrl_vv_u16m1(...) __riscv_vssrl_vv_u16m1(__VA_ARGS__) -#define vssrl_vx_u16m1(...) __riscv_vssrl_vx_u16m1(__VA_ARGS__) -#define vssrl_vv_u16m2(...) __riscv_vssrl_vv_u16m2(__VA_ARGS__) -#define vssrl_vx_u16m2(...) __riscv_vssrl_vx_u16m2(__VA_ARGS__) -#define vssrl_vv_u16m4(...) __riscv_vssrl_vv_u16m4(__VA_ARGS__) -#define vssrl_vx_u16m4(...) __riscv_vssrl_vx_u16m4(__VA_ARGS__) -#define vssrl_vv_u16m8(...) __riscv_vssrl_vv_u16m8(__VA_ARGS__) -#define vssrl_vx_u16m8(...) __riscv_vssrl_vx_u16m8(__VA_ARGS__) -#define vssrl_vv_u32mf2(...) __riscv_vssrl_vv_u32mf2(__VA_ARGS__) -#define vssrl_vx_u32mf2(...) __riscv_vssrl_vx_u32mf2(__VA_ARGS__) -#define vssrl_vv_u32m1(...) __riscv_vssrl_vv_u32m1(__VA_ARGS__) -#define vssrl_vx_u32m1(...) __riscv_vssrl_vx_u32m1(__VA_ARGS__) -#define vssrl_vv_u32m2(...) __riscv_vssrl_vv_u32m2(__VA_ARGS__) -#define vssrl_vx_u32m2(...) __riscv_vssrl_vx_u32m2(__VA_ARGS__) -#define vssrl_vv_u32m4(...) __riscv_vssrl_vv_u32m4(__VA_ARGS__) -#define vssrl_vx_u32m4(...) __riscv_vssrl_vx_u32m4(__VA_ARGS__) -#define vssrl_vv_u32m8(...) __riscv_vssrl_vv_u32m8(__VA_ARGS__) -#define vssrl_vx_u32m8(...) __riscv_vssrl_vx_u32m8(__VA_ARGS__) -#define vssrl_vv_u64m1(...) __riscv_vssrl_vv_u64m1(__VA_ARGS__) -#define vssrl_vx_u64m1(...) __riscv_vssrl_vx_u64m1(__VA_ARGS__) -#define vssrl_vv_u64m2(...) __riscv_vssrl_vv_u64m2(__VA_ARGS__) -#define vssrl_vx_u64m2(...) __riscv_vssrl_vx_u64m2(__VA_ARGS__) -#define vssrl_vv_u64m4(...) __riscv_vssrl_vv_u64m4(__VA_ARGS__) -#define vssrl_vx_u64m4(...) __riscv_vssrl_vx_u64m4(__VA_ARGS__) -#define vssrl_vv_u64m8(...) __riscv_vssrl_vv_u64m8(__VA_ARGS__) -#define vssrl_vx_u64m8(...) __riscv_vssrl_vx_u64m8(__VA_ARGS__) -// masked functions -#define vssra_vv_i8mf8_m(...) __riscv_vssra_vv_i8mf8_tumu(__VA_ARGS__) -#define vssra_vx_i8mf8_m(...) __riscv_vssra_vx_i8mf8_tumu(__VA_ARGS__) -#define vssra_vv_i8mf4_m(...) __riscv_vssra_vv_i8mf4_tumu(__VA_ARGS__) -#define vssra_vx_i8mf4_m(...) __riscv_vssra_vx_i8mf4_tumu(__VA_ARGS__) -#define vssra_vv_i8mf2_m(...) __riscv_vssra_vv_i8mf2_tumu(__VA_ARGS__) -#define vssra_vx_i8mf2_m(...) __riscv_vssra_vx_i8mf2_tumu(__VA_ARGS__) -#define vssra_vv_i8m1_m(...) __riscv_vssra_vv_i8m1_tumu(__VA_ARGS__) -#define vssra_vx_i8m1_m(...) __riscv_vssra_vx_i8m1_tumu(__VA_ARGS__) -#define vssra_vv_i8m2_m(...) __riscv_vssra_vv_i8m2_tumu(__VA_ARGS__) -#define vssra_vx_i8m2_m(...) __riscv_vssra_vx_i8m2_tumu(__VA_ARGS__) -#define vssra_vv_i8m4_m(...) __riscv_vssra_vv_i8m4_tumu(__VA_ARGS__) -#define vssra_vx_i8m4_m(...) __riscv_vssra_vx_i8m4_tumu(__VA_ARGS__) -#define vssra_vv_i8m8_m(...) __riscv_vssra_vv_i8m8_tumu(__VA_ARGS__) -#define vssra_vx_i8m8_m(...) __riscv_vssra_vx_i8m8_tumu(__VA_ARGS__) -#define vssra_vv_i16mf4_m(...) __riscv_vssra_vv_i16mf4_tumu(__VA_ARGS__) -#define vssra_vx_i16mf4_m(...) __riscv_vssra_vx_i16mf4_tumu(__VA_ARGS__) -#define vssra_vv_i16mf2_m(...) __riscv_vssra_vv_i16mf2_tumu(__VA_ARGS__) -#define vssra_vx_i16mf2_m(...) __riscv_vssra_vx_i16mf2_tumu(__VA_ARGS__) -#define vssra_vv_i16m1_m(...) __riscv_vssra_vv_i16m1_tumu(__VA_ARGS__) -#define vssra_vx_i16m1_m(...) __riscv_vssra_vx_i16m1_tumu(__VA_ARGS__) -#define vssra_vv_i16m2_m(...) __riscv_vssra_vv_i16m2_tumu(__VA_ARGS__) -#define vssra_vx_i16m2_m(...) __riscv_vssra_vx_i16m2_tumu(__VA_ARGS__) -#define vssra_vv_i16m4_m(...) __riscv_vssra_vv_i16m4_tumu(__VA_ARGS__) -#define vssra_vx_i16m4_m(...) __riscv_vssra_vx_i16m4_tumu(__VA_ARGS__) -#define vssra_vv_i16m8_m(...) __riscv_vssra_vv_i16m8_tumu(__VA_ARGS__) -#define vssra_vx_i16m8_m(...) __riscv_vssra_vx_i16m8_tumu(__VA_ARGS__) -#define vssra_vv_i32mf2_m(...) __riscv_vssra_vv_i32mf2_tumu(__VA_ARGS__) -#define vssra_vx_i32mf2_m(...) __riscv_vssra_vx_i32mf2_tumu(__VA_ARGS__) -#define vssra_vv_i32m1_m(...) __riscv_vssra_vv_i32m1_tumu(__VA_ARGS__) -#define vssra_vx_i32m1_m(...) __riscv_vssra_vx_i32m1_tumu(__VA_ARGS__) -#define vssra_vv_i32m2_m(...) __riscv_vssra_vv_i32m2_tumu(__VA_ARGS__) -#define vssra_vx_i32m2_m(...) __riscv_vssra_vx_i32m2_tumu(__VA_ARGS__) -#define vssra_vv_i32m4_m(...) __riscv_vssra_vv_i32m4_tumu(__VA_ARGS__) -#define vssra_vx_i32m4_m(...) __riscv_vssra_vx_i32m4_tumu(__VA_ARGS__) -#define vssra_vv_i32m8_m(...) __riscv_vssra_vv_i32m8_tumu(__VA_ARGS__) -#define vssra_vx_i32m8_m(...) __riscv_vssra_vx_i32m8_tumu(__VA_ARGS__) -#define vssra_vv_i64m1_m(...) __riscv_vssra_vv_i64m1_tumu(__VA_ARGS__) -#define vssra_vx_i64m1_m(...) __riscv_vssra_vx_i64m1_tumu(__VA_ARGS__) -#define vssra_vv_i64m2_m(...) __riscv_vssra_vv_i64m2_tumu(__VA_ARGS__) -#define vssra_vx_i64m2_m(...) __riscv_vssra_vx_i64m2_tumu(__VA_ARGS__) -#define vssra_vv_i64m4_m(...) __riscv_vssra_vv_i64m4_tumu(__VA_ARGS__) -#define vssra_vx_i64m4_m(...) __riscv_vssra_vx_i64m4_tumu(__VA_ARGS__) -#define vssra_vv_i64m8_m(...) __riscv_vssra_vv_i64m8_tumu(__VA_ARGS__) -#define vssra_vx_i64m8_m(...) __riscv_vssra_vx_i64m8_tumu(__VA_ARGS__) -#define vssrl_vv_u8mf8_m(...) __riscv_vssrl_vv_u8mf8_tumu(__VA_ARGS__) -#define vssrl_vx_u8mf8_m(...) __riscv_vssrl_vx_u8mf8_tumu(__VA_ARGS__) -#define vssrl_vv_u8mf4_m(...) __riscv_vssrl_vv_u8mf4_tumu(__VA_ARGS__) -#define vssrl_vx_u8mf4_m(...) __riscv_vssrl_vx_u8mf4_tumu(__VA_ARGS__) -#define vssrl_vv_u8mf2_m(...) __riscv_vssrl_vv_u8mf2_tumu(__VA_ARGS__) -#define vssrl_vx_u8mf2_m(...) __riscv_vssrl_vx_u8mf2_tumu(__VA_ARGS__) -#define vssrl_vv_u8m1_m(...) __riscv_vssrl_vv_u8m1_tumu(__VA_ARGS__) -#define vssrl_vx_u8m1_m(...) __riscv_vssrl_vx_u8m1_tumu(__VA_ARGS__) -#define vssrl_vv_u8m2_m(...) __riscv_vssrl_vv_u8m2_tumu(__VA_ARGS__) -#define vssrl_vx_u8m2_m(...) __riscv_vssrl_vx_u8m2_tumu(__VA_ARGS__) -#define vssrl_vv_u8m4_m(...) __riscv_vssrl_vv_u8m4_tumu(__VA_ARGS__) -#define vssrl_vx_u8m4_m(...) __riscv_vssrl_vx_u8m4_tumu(__VA_ARGS__) -#define vssrl_vv_u8m8_m(...) __riscv_vssrl_vv_u8m8_tumu(__VA_ARGS__) -#define vssrl_vx_u8m8_m(...) __riscv_vssrl_vx_u8m8_tumu(__VA_ARGS__) -#define vssrl_vv_u16mf4_m(...) __riscv_vssrl_vv_u16mf4_tumu(__VA_ARGS__) -#define vssrl_vx_u16mf4_m(...) __riscv_vssrl_vx_u16mf4_tumu(__VA_ARGS__) -#define vssrl_vv_u16mf2_m(...) __riscv_vssrl_vv_u16mf2_tumu(__VA_ARGS__) -#define vssrl_vx_u16mf2_m(...) __riscv_vssrl_vx_u16mf2_tumu(__VA_ARGS__) -#define vssrl_vv_u16m1_m(...) __riscv_vssrl_vv_u16m1_tumu(__VA_ARGS__) -#define vssrl_vx_u16m1_m(...) __riscv_vssrl_vx_u16m1_tumu(__VA_ARGS__) -#define vssrl_vv_u16m2_m(...) __riscv_vssrl_vv_u16m2_tumu(__VA_ARGS__) -#define vssrl_vx_u16m2_m(...) __riscv_vssrl_vx_u16m2_tumu(__VA_ARGS__) -#define vssrl_vv_u16m4_m(...) __riscv_vssrl_vv_u16m4_tumu(__VA_ARGS__) -#define vssrl_vx_u16m4_m(...) __riscv_vssrl_vx_u16m4_tumu(__VA_ARGS__) -#define vssrl_vv_u16m8_m(...) __riscv_vssrl_vv_u16m8_tumu(__VA_ARGS__) -#define vssrl_vx_u16m8_m(...) __riscv_vssrl_vx_u16m8_tumu(__VA_ARGS__) -#define vssrl_vv_u32mf2_m(...) __riscv_vssrl_vv_u32mf2_tumu(__VA_ARGS__) -#define vssrl_vx_u32mf2_m(...) __riscv_vssrl_vx_u32mf2_tumu(__VA_ARGS__) -#define vssrl_vv_u32m1_m(...) __riscv_vssrl_vv_u32m1_tumu(__VA_ARGS__) -#define vssrl_vx_u32m1_m(...) __riscv_vssrl_vx_u32m1_tumu(__VA_ARGS__) -#define vssrl_vv_u32m2_m(...) __riscv_vssrl_vv_u32m2_tumu(__VA_ARGS__) -#define vssrl_vx_u32m2_m(...) __riscv_vssrl_vx_u32m2_tumu(__VA_ARGS__) -#define vssrl_vv_u32m4_m(...) __riscv_vssrl_vv_u32m4_tumu(__VA_ARGS__) -#define vssrl_vx_u32m4_m(...) __riscv_vssrl_vx_u32m4_tumu(__VA_ARGS__) -#define vssrl_vv_u32m8_m(...) __riscv_vssrl_vv_u32m8_tumu(__VA_ARGS__) -#define vssrl_vx_u32m8_m(...) __riscv_vssrl_vx_u32m8_tumu(__VA_ARGS__) -#define vssrl_vv_u64m1_m(...) __riscv_vssrl_vv_u64m1_tumu(__VA_ARGS__) -#define vssrl_vx_u64m1_m(...) __riscv_vssrl_vx_u64m1_tumu(__VA_ARGS__) -#define vssrl_vv_u64m2_m(...) __riscv_vssrl_vv_u64m2_tumu(__VA_ARGS__) -#define vssrl_vx_u64m2_m(...) __riscv_vssrl_vx_u64m2_tumu(__VA_ARGS__) -#define vssrl_vv_u64m4_m(...) __riscv_vssrl_vv_u64m4_tumu(__VA_ARGS__) -#define vssrl_vx_u64m4_m(...) __riscv_vssrl_vx_u64m4_tumu(__VA_ARGS__) -#define vssrl_vv_u64m8_m(...) __riscv_vssrl_vv_u64m8_tumu(__VA_ARGS__) -#define vssrl_vx_u64m8_m(...) __riscv_vssrl_vx_u64m8_tumu(__VA_ARGS__) -#define vnclip_wv_i8mf8(...) __riscv_vnclip_wv_i8mf8(__VA_ARGS__) -#define vnclip_wx_i8mf8(...) __riscv_vnclip_wx_i8mf8(__VA_ARGS__) -#define vnclip_wv_i8mf4(...) __riscv_vnclip_wv_i8mf4(__VA_ARGS__) -#define vnclip_wx_i8mf4(...) __riscv_vnclip_wx_i8mf4(__VA_ARGS__) -#define vnclip_wv_i8mf2(...) __riscv_vnclip_wv_i8mf2(__VA_ARGS__) -#define vnclip_wx_i8mf2(...) __riscv_vnclip_wx_i8mf2(__VA_ARGS__) -#define vnclip_wv_i8m1(...) __riscv_vnclip_wv_i8m1(__VA_ARGS__) -#define vnclip_wx_i8m1(...) __riscv_vnclip_wx_i8m1(__VA_ARGS__) -#define vnclip_wv_i8m2(...) __riscv_vnclip_wv_i8m2(__VA_ARGS__) -#define vnclip_wx_i8m2(...) __riscv_vnclip_wx_i8m2(__VA_ARGS__) -#define vnclip_wv_i8m4(...) __riscv_vnclip_wv_i8m4(__VA_ARGS__) -#define vnclip_wx_i8m4(...) __riscv_vnclip_wx_i8m4(__VA_ARGS__) -#define vnclip_wv_i16mf4(...) __riscv_vnclip_wv_i16mf4(__VA_ARGS__) -#define vnclip_wx_i16mf4(...) __riscv_vnclip_wx_i16mf4(__VA_ARGS__) -#define vnclip_wv_i16mf2(...) __riscv_vnclip_wv_i16mf2(__VA_ARGS__) -#define vnclip_wx_i16mf2(...) __riscv_vnclip_wx_i16mf2(__VA_ARGS__) -#define vnclip_wv_i16m1(...) __riscv_vnclip_wv_i16m1(__VA_ARGS__) -#define vnclip_wx_i16m1(...) __riscv_vnclip_wx_i16m1(__VA_ARGS__) -#define vnclip_wv_i16m2(...) __riscv_vnclip_wv_i16m2(__VA_ARGS__) -#define vnclip_wx_i16m2(...) __riscv_vnclip_wx_i16m2(__VA_ARGS__) -#define vnclip_wv_i16m4(...) __riscv_vnclip_wv_i16m4(__VA_ARGS__) -#define vnclip_wx_i16m4(...) __riscv_vnclip_wx_i16m4(__VA_ARGS__) -#define vnclip_wv_i32mf2(...) __riscv_vnclip_wv_i32mf2(__VA_ARGS__) -#define vnclip_wx_i32mf2(...) __riscv_vnclip_wx_i32mf2(__VA_ARGS__) -#define vnclip_wv_i32m1(...) __riscv_vnclip_wv_i32m1(__VA_ARGS__) -#define vnclip_wx_i32m1(...) __riscv_vnclip_wx_i32m1(__VA_ARGS__) -#define vnclip_wv_i32m2(...) __riscv_vnclip_wv_i32m2(__VA_ARGS__) -#define vnclip_wx_i32m2(...) __riscv_vnclip_wx_i32m2(__VA_ARGS__) -#define vnclip_wv_i32m4(...) __riscv_vnclip_wv_i32m4(__VA_ARGS__) -#define vnclip_wx_i32m4(...) __riscv_vnclip_wx_i32m4(__VA_ARGS__) -#define vnclipu_wv_u8mf8(...) __riscv_vnclipu_wv_u8mf8(__VA_ARGS__) -#define vnclipu_wx_u8mf8(...) __riscv_vnclipu_wx_u8mf8(__VA_ARGS__) -#define vnclipu_wv_u8mf4(...) __riscv_vnclipu_wv_u8mf4(__VA_ARGS__) -#define vnclipu_wx_u8mf4(...) __riscv_vnclipu_wx_u8mf4(__VA_ARGS__) -#define vnclipu_wv_u8mf2(...) __riscv_vnclipu_wv_u8mf2(__VA_ARGS__) -#define vnclipu_wx_u8mf2(...) __riscv_vnclipu_wx_u8mf2(__VA_ARGS__) -#define vnclipu_wv_u8m1(...) __riscv_vnclipu_wv_u8m1(__VA_ARGS__) -#define vnclipu_wx_u8m1(...) __riscv_vnclipu_wx_u8m1(__VA_ARGS__) -#define vnclipu_wv_u8m2(...) __riscv_vnclipu_wv_u8m2(__VA_ARGS__) -#define vnclipu_wx_u8m2(...) __riscv_vnclipu_wx_u8m2(__VA_ARGS__) -#define vnclipu_wv_u8m4(...) __riscv_vnclipu_wv_u8m4(__VA_ARGS__) -#define vnclipu_wx_u8m4(...) __riscv_vnclipu_wx_u8m4(__VA_ARGS__) -#define vnclipu_wv_u16mf4(...) __riscv_vnclipu_wv_u16mf4(__VA_ARGS__) -#define vnclipu_wx_u16mf4(...) __riscv_vnclipu_wx_u16mf4(__VA_ARGS__) -#define vnclipu_wv_u16mf2(...) __riscv_vnclipu_wv_u16mf2(__VA_ARGS__) -#define vnclipu_wx_u16mf2(...) __riscv_vnclipu_wx_u16mf2(__VA_ARGS__) -#define vnclipu_wv_u16m1(...) __riscv_vnclipu_wv_u16m1(__VA_ARGS__) -#define vnclipu_wx_u16m1(...) __riscv_vnclipu_wx_u16m1(__VA_ARGS__) -#define vnclipu_wv_u16m2(...) __riscv_vnclipu_wv_u16m2(__VA_ARGS__) -#define vnclipu_wx_u16m2(...) __riscv_vnclipu_wx_u16m2(__VA_ARGS__) -#define vnclipu_wv_u16m4(...) __riscv_vnclipu_wv_u16m4(__VA_ARGS__) -#define vnclipu_wx_u16m4(...) __riscv_vnclipu_wx_u16m4(__VA_ARGS__) -#define vnclipu_wv_u32mf2(...) __riscv_vnclipu_wv_u32mf2(__VA_ARGS__) -#define vnclipu_wx_u32mf2(...) __riscv_vnclipu_wx_u32mf2(__VA_ARGS__) -#define vnclipu_wv_u32m1(...) __riscv_vnclipu_wv_u32m1(__VA_ARGS__) -#define vnclipu_wx_u32m1(...) __riscv_vnclipu_wx_u32m1(__VA_ARGS__) -#define vnclipu_wv_u32m2(...) __riscv_vnclipu_wv_u32m2(__VA_ARGS__) -#define vnclipu_wx_u32m2(...) __riscv_vnclipu_wx_u32m2(__VA_ARGS__) -#define vnclipu_wv_u32m4(...) __riscv_vnclipu_wv_u32m4(__VA_ARGS__) -#define vnclipu_wx_u32m4(...) __riscv_vnclipu_wx_u32m4(__VA_ARGS__) -// masked functions -#define vnclip_wv_i8mf8_m(...) __riscv_vnclip_wv_i8mf8_tumu(__VA_ARGS__) -#define vnclip_wx_i8mf8_m(...) __riscv_vnclip_wx_i8mf8_tumu(__VA_ARGS__) -#define vnclip_wv_i8mf4_m(...) __riscv_vnclip_wv_i8mf4_tumu(__VA_ARGS__) -#define vnclip_wx_i8mf4_m(...) __riscv_vnclip_wx_i8mf4_tumu(__VA_ARGS__) -#define vnclip_wv_i8mf2_m(...) __riscv_vnclip_wv_i8mf2_tumu(__VA_ARGS__) -#define vnclip_wx_i8mf2_m(...) __riscv_vnclip_wx_i8mf2_tumu(__VA_ARGS__) -#define vnclip_wv_i8m1_m(...) __riscv_vnclip_wv_i8m1_tumu(__VA_ARGS__) -#define vnclip_wx_i8m1_m(...) __riscv_vnclip_wx_i8m1_tumu(__VA_ARGS__) -#define vnclip_wv_i8m2_m(...) __riscv_vnclip_wv_i8m2_tumu(__VA_ARGS__) -#define vnclip_wx_i8m2_m(...) __riscv_vnclip_wx_i8m2_tumu(__VA_ARGS__) -#define vnclip_wv_i8m4_m(...) __riscv_vnclip_wv_i8m4_tumu(__VA_ARGS__) -#define vnclip_wx_i8m4_m(...) __riscv_vnclip_wx_i8m4_tumu(__VA_ARGS__) -#define vnclip_wv_i16mf4_m(...) __riscv_vnclip_wv_i16mf4_tumu(__VA_ARGS__) -#define vnclip_wx_i16mf4_m(...) __riscv_vnclip_wx_i16mf4_tumu(__VA_ARGS__) -#define vnclip_wv_i16mf2_m(...) __riscv_vnclip_wv_i16mf2_tumu(__VA_ARGS__) -#define vnclip_wx_i16mf2_m(...) __riscv_vnclip_wx_i16mf2_tumu(__VA_ARGS__) -#define vnclip_wv_i16m1_m(...) __riscv_vnclip_wv_i16m1_tumu(__VA_ARGS__) -#define vnclip_wx_i16m1_m(...) __riscv_vnclip_wx_i16m1_tumu(__VA_ARGS__) -#define vnclip_wv_i16m2_m(...) __riscv_vnclip_wv_i16m2_tumu(__VA_ARGS__) -#define vnclip_wx_i16m2_m(...) __riscv_vnclip_wx_i16m2_tumu(__VA_ARGS__) -#define vnclip_wv_i16m4_m(...) __riscv_vnclip_wv_i16m4_tumu(__VA_ARGS__) -#define vnclip_wx_i16m4_m(...) __riscv_vnclip_wx_i16m4_tumu(__VA_ARGS__) -#define vnclip_wv_i32mf2_m(...) __riscv_vnclip_wv_i32mf2_tumu(__VA_ARGS__) -#define vnclip_wx_i32mf2_m(...) __riscv_vnclip_wx_i32mf2_tumu(__VA_ARGS__) -#define vnclip_wv_i32m1_m(...) __riscv_vnclip_wv_i32m1_tumu(__VA_ARGS__) -#define vnclip_wx_i32m1_m(...) __riscv_vnclip_wx_i32m1_tumu(__VA_ARGS__) -#define vnclip_wv_i32m2_m(...) __riscv_vnclip_wv_i32m2_tumu(__VA_ARGS__) -#define vnclip_wx_i32m2_m(...) __riscv_vnclip_wx_i32m2_tumu(__VA_ARGS__) -#define vnclip_wv_i32m4_m(...) __riscv_vnclip_wv_i32m4_tumu(__VA_ARGS__) -#define vnclip_wx_i32m4_m(...) __riscv_vnclip_wx_i32m4_tumu(__VA_ARGS__) -#define vnclipu_wv_u8mf8_m(...) __riscv_vnclipu_wv_u8mf8_tumu(__VA_ARGS__) -#define vnclipu_wx_u8mf8_m(...) __riscv_vnclipu_wx_u8mf8_tumu(__VA_ARGS__) -#define vnclipu_wv_u8mf4_m(...) __riscv_vnclipu_wv_u8mf4_tumu(__VA_ARGS__) -#define vnclipu_wx_u8mf4_m(...) __riscv_vnclipu_wx_u8mf4_tumu(__VA_ARGS__) -#define vnclipu_wv_u8mf2_m(...) __riscv_vnclipu_wv_u8mf2_tumu(__VA_ARGS__) -#define vnclipu_wx_u8mf2_m(...) __riscv_vnclipu_wx_u8mf2_tumu(__VA_ARGS__) -#define vnclipu_wv_u8m1_m(...) __riscv_vnclipu_wv_u8m1_tumu(__VA_ARGS__) -#define vnclipu_wx_u8m1_m(...) __riscv_vnclipu_wx_u8m1_tumu(__VA_ARGS__) -#define vnclipu_wv_u8m2_m(...) __riscv_vnclipu_wv_u8m2_tumu(__VA_ARGS__) -#define vnclipu_wx_u8m2_m(...) __riscv_vnclipu_wx_u8m2_tumu(__VA_ARGS__) -#define vnclipu_wv_u8m4_m(...) __riscv_vnclipu_wv_u8m4_tumu(__VA_ARGS__) -#define vnclipu_wx_u8m4_m(...) __riscv_vnclipu_wx_u8m4_tumu(__VA_ARGS__) -#define vnclipu_wv_u16mf4_m(...) __riscv_vnclipu_wv_u16mf4_tumu(__VA_ARGS__) -#define vnclipu_wx_u16mf4_m(...) __riscv_vnclipu_wx_u16mf4_tumu(__VA_ARGS__) -#define vnclipu_wv_u16mf2_m(...) __riscv_vnclipu_wv_u16mf2_tumu(__VA_ARGS__) -#define vnclipu_wx_u16mf2_m(...) __riscv_vnclipu_wx_u16mf2_tumu(__VA_ARGS__) -#define vnclipu_wv_u16m1_m(...) __riscv_vnclipu_wv_u16m1_tumu(__VA_ARGS__) -#define vnclipu_wx_u16m1_m(...) __riscv_vnclipu_wx_u16m1_tumu(__VA_ARGS__) -#define vnclipu_wv_u16m2_m(...) __riscv_vnclipu_wv_u16m2_tumu(__VA_ARGS__) -#define vnclipu_wx_u16m2_m(...) __riscv_vnclipu_wx_u16m2_tumu(__VA_ARGS__) -#define vnclipu_wv_u16m4_m(...) __riscv_vnclipu_wv_u16m4_tumu(__VA_ARGS__) -#define vnclipu_wx_u16m4_m(...) __riscv_vnclipu_wx_u16m4_tumu(__VA_ARGS__) -#define vnclipu_wv_u32mf2_m(...) __riscv_vnclipu_wv_u32mf2_tumu(__VA_ARGS__) -#define vnclipu_wx_u32mf2_m(...) __riscv_vnclipu_wx_u32mf2_tumu(__VA_ARGS__) -#define vnclipu_wv_u32m1_m(...) __riscv_vnclipu_wv_u32m1_tumu(__VA_ARGS__) -#define vnclipu_wx_u32m1_m(...) __riscv_vnclipu_wx_u32m1_tumu(__VA_ARGS__) -#define vnclipu_wv_u32m2_m(...) __riscv_vnclipu_wv_u32m2_tumu(__VA_ARGS__) -#define vnclipu_wx_u32m2_m(...) __riscv_vnclipu_wx_u32m2_tumu(__VA_ARGS__) -#define vnclipu_wv_u32m4_m(...) __riscv_vnclipu_wv_u32m4_tumu(__VA_ARGS__) -#define vnclipu_wx_u32m4_m(...) __riscv_vnclipu_wx_u32m4_tumu(__VA_ARGS__) -#define vfadd_vv_f16mf4(...) __riscv_vfadd_vv_f16mf4(__VA_ARGS__) -#define vfadd_vf_f16mf4(...) __riscv_vfadd_vf_f16mf4(__VA_ARGS__) -#define vfadd_vv_f16mf2(...) __riscv_vfadd_vv_f16mf2(__VA_ARGS__) -#define vfadd_vf_f16mf2(...) __riscv_vfadd_vf_f16mf2(__VA_ARGS__) -#define vfadd_vv_f16m1(...) __riscv_vfadd_vv_f16m1(__VA_ARGS__) -#define vfadd_vf_f16m1(...) __riscv_vfadd_vf_f16m1(__VA_ARGS__) -#define vfadd_vv_f16m2(...) __riscv_vfadd_vv_f16m2(__VA_ARGS__) -#define vfadd_vf_f16m2(...) __riscv_vfadd_vf_f16m2(__VA_ARGS__) -#define vfadd_vv_f16m4(...) __riscv_vfadd_vv_f16m4(__VA_ARGS__) -#define vfadd_vf_f16m4(...) __riscv_vfadd_vf_f16m4(__VA_ARGS__) -#define vfadd_vv_f16m8(...) __riscv_vfadd_vv_f16m8(__VA_ARGS__) -#define vfadd_vf_f16m8(...) __riscv_vfadd_vf_f16m8(__VA_ARGS__) -#define vfadd_vv_f32mf2(...) __riscv_vfadd_vv_f32mf2(__VA_ARGS__) -#define vfadd_vf_f32mf2(...) __riscv_vfadd_vf_f32mf2(__VA_ARGS__) -#define vfadd_vv_f32m1(...) __riscv_vfadd_vv_f32m1(__VA_ARGS__) -#define vfadd_vf_f32m1(...) __riscv_vfadd_vf_f32m1(__VA_ARGS__) -#define vfadd_vv_f32m2(...) __riscv_vfadd_vv_f32m2(__VA_ARGS__) -#define vfadd_vf_f32m2(...) __riscv_vfadd_vf_f32m2(__VA_ARGS__) -#define vfadd_vv_f32m4(...) __riscv_vfadd_vv_f32m4(__VA_ARGS__) -#define vfadd_vf_f32m4(...) __riscv_vfadd_vf_f32m4(__VA_ARGS__) -#define vfadd_vv_f32m8(...) __riscv_vfadd_vv_f32m8(__VA_ARGS__) -#define vfadd_vf_f32m8(...) __riscv_vfadd_vf_f32m8(__VA_ARGS__) -#define vfadd_vv_f64m1(...) __riscv_vfadd_vv_f64m1(__VA_ARGS__) -#define vfadd_vf_f64m1(...) __riscv_vfadd_vf_f64m1(__VA_ARGS__) -#define vfadd_vv_f64m2(...) __riscv_vfadd_vv_f64m2(__VA_ARGS__) -#define vfadd_vf_f64m2(...) __riscv_vfadd_vf_f64m2(__VA_ARGS__) -#define vfadd_vv_f64m4(...) __riscv_vfadd_vv_f64m4(__VA_ARGS__) -#define vfadd_vf_f64m4(...) __riscv_vfadd_vf_f64m4(__VA_ARGS__) -#define vfadd_vv_f64m8(...) __riscv_vfadd_vv_f64m8(__VA_ARGS__) -#define vfadd_vf_f64m8(...) __riscv_vfadd_vf_f64m8(__VA_ARGS__) -#define vfsub_vv_f16mf4(...) __riscv_vfsub_vv_f16mf4(__VA_ARGS__) -#define vfsub_vf_f16mf4(...) __riscv_vfsub_vf_f16mf4(__VA_ARGS__) -#define vfsub_vv_f16mf2(...) __riscv_vfsub_vv_f16mf2(__VA_ARGS__) -#define vfsub_vf_f16mf2(...) __riscv_vfsub_vf_f16mf2(__VA_ARGS__) -#define vfsub_vv_f16m1(...) __riscv_vfsub_vv_f16m1(__VA_ARGS__) -#define vfsub_vf_f16m1(...) __riscv_vfsub_vf_f16m1(__VA_ARGS__) -#define vfsub_vv_f16m2(...) __riscv_vfsub_vv_f16m2(__VA_ARGS__) -#define vfsub_vf_f16m2(...) __riscv_vfsub_vf_f16m2(__VA_ARGS__) -#define vfsub_vv_f16m4(...) __riscv_vfsub_vv_f16m4(__VA_ARGS__) -#define vfsub_vf_f16m4(...) __riscv_vfsub_vf_f16m4(__VA_ARGS__) -#define vfsub_vv_f16m8(...) __riscv_vfsub_vv_f16m8(__VA_ARGS__) -#define vfsub_vf_f16m8(...) __riscv_vfsub_vf_f16m8(__VA_ARGS__) -#define vfsub_vv_f32mf2(...) __riscv_vfsub_vv_f32mf2(__VA_ARGS__) -#define vfsub_vf_f32mf2(...) __riscv_vfsub_vf_f32mf2(__VA_ARGS__) -#define vfsub_vv_f32m1(...) __riscv_vfsub_vv_f32m1(__VA_ARGS__) -#define vfsub_vf_f32m1(...) __riscv_vfsub_vf_f32m1(__VA_ARGS__) -#define vfsub_vv_f32m2(...) __riscv_vfsub_vv_f32m2(__VA_ARGS__) -#define vfsub_vf_f32m2(...) __riscv_vfsub_vf_f32m2(__VA_ARGS__) -#define vfsub_vv_f32m4(...) __riscv_vfsub_vv_f32m4(__VA_ARGS__) -#define vfsub_vf_f32m4(...) __riscv_vfsub_vf_f32m4(__VA_ARGS__) -#define vfsub_vv_f32m8(...) __riscv_vfsub_vv_f32m8(__VA_ARGS__) -#define vfsub_vf_f32m8(...) __riscv_vfsub_vf_f32m8(__VA_ARGS__) -#define vfsub_vv_f64m1(...) __riscv_vfsub_vv_f64m1(__VA_ARGS__) -#define vfsub_vf_f64m1(...) __riscv_vfsub_vf_f64m1(__VA_ARGS__) -#define vfsub_vv_f64m2(...) __riscv_vfsub_vv_f64m2(__VA_ARGS__) -#define vfsub_vf_f64m2(...) __riscv_vfsub_vf_f64m2(__VA_ARGS__) -#define vfsub_vv_f64m4(...) __riscv_vfsub_vv_f64m4(__VA_ARGS__) -#define vfsub_vf_f64m4(...) __riscv_vfsub_vf_f64m4(__VA_ARGS__) -#define vfsub_vv_f64m8(...) __riscv_vfsub_vv_f64m8(__VA_ARGS__) -#define vfsub_vf_f64m8(...) __riscv_vfsub_vf_f64m8(__VA_ARGS__) -#define vfrsub_vf_f16mf4(...) __riscv_vfrsub_vf_f16mf4(__VA_ARGS__) -#define vfrsub_vf_f16mf2(...) __riscv_vfrsub_vf_f16mf2(__VA_ARGS__) -#define vfrsub_vf_f16m1(...) __riscv_vfrsub_vf_f16m1(__VA_ARGS__) -#define vfrsub_vf_f16m2(...) __riscv_vfrsub_vf_f16m2(__VA_ARGS__) -#define vfrsub_vf_f16m4(...) __riscv_vfrsub_vf_f16m4(__VA_ARGS__) -#define vfrsub_vf_f16m8(...) __riscv_vfrsub_vf_f16m8(__VA_ARGS__) -#define vfrsub_vf_f32mf2(...) __riscv_vfrsub_vf_f32mf2(__VA_ARGS__) -#define vfrsub_vf_f32m1(...) __riscv_vfrsub_vf_f32m1(__VA_ARGS__) -#define vfrsub_vf_f32m2(...) __riscv_vfrsub_vf_f32m2(__VA_ARGS__) -#define vfrsub_vf_f32m4(...) __riscv_vfrsub_vf_f32m4(__VA_ARGS__) -#define vfrsub_vf_f32m8(...) __riscv_vfrsub_vf_f32m8(__VA_ARGS__) -#define vfrsub_vf_f64m1(...) __riscv_vfrsub_vf_f64m1(__VA_ARGS__) -#define vfrsub_vf_f64m2(...) __riscv_vfrsub_vf_f64m2(__VA_ARGS__) -#define vfrsub_vf_f64m4(...) __riscv_vfrsub_vf_f64m4(__VA_ARGS__) -#define vfrsub_vf_f64m8(...) __riscv_vfrsub_vf_f64m8(__VA_ARGS__) -#define vfneg_v_f16mf4(...) __riscv_vfneg_v_f16mf4(__VA_ARGS__) -#define vfneg_v_f16mf2(...) __riscv_vfneg_v_f16mf2(__VA_ARGS__) -#define vfneg_v_f16m1(...) __riscv_vfneg_v_f16m1(__VA_ARGS__) -#define vfneg_v_f16m2(...) __riscv_vfneg_v_f16m2(__VA_ARGS__) -#define vfneg_v_f16m4(...) __riscv_vfneg_v_f16m4(__VA_ARGS__) -#define vfneg_v_f16m8(...) __riscv_vfneg_v_f16m8(__VA_ARGS__) -#define vfneg_v_f32mf2(...) __riscv_vfneg_v_f32mf2(__VA_ARGS__) -#define vfneg_v_f32m1(...) __riscv_vfneg_v_f32m1(__VA_ARGS__) -#define vfneg_v_f32m2(...) __riscv_vfneg_v_f32m2(__VA_ARGS__) -#define vfneg_v_f32m4(...) __riscv_vfneg_v_f32m4(__VA_ARGS__) -#define vfneg_v_f32m8(...) __riscv_vfneg_v_f32m8(__VA_ARGS__) -#define vfneg_v_f64m1(...) __riscv_vfneg_v_f64m1(__VA_ARGS__) -#define vfneg_v_f64m2(...) __riscv_vfneg_v_f64m2(__VA_ARGS__) -#define vfneg_v_f64m4(...) __riscv_vfneg_v_f64m4(__VA_ARGS__) -#define vfneg_v_f64m8(...) __riscv_vfneg_v_f64m8(__VA_ARGS__) -// masked functions -#define vfadd_vv_f16mf4_m(...) __riscv_vfadd_vv_f16mf4_tumu(__VA_ARGS__) -#define vfadd_vf_f16mf4_m(...) __riscv_vfadd_vf_f16mf4_tumu(__VA_ARGS__) -#define vfadd_vv_f16mf2_m(...) __riscv_vfadd_vv_f16mf2_tumu(__VA_ARGS__) -#define vfadd_vf_f16mf2_m(...) __riscv_vfadd_vf_f16mf2_tumu(__VA_ARGS__) -#define vfadd_vv_f16m1_m(...) __riscv_vfadd_vv_f16m1_tumu(__VA_ARGS__) -#define vfadd_vf_f16m1_m(...) __riscv_vfadd_vf_f16m1_tumu(__VA_ARGS__) -#define vfadd_vv_f16m2_m(...) __riscv_vfadd_vv_f16m2_tumu(__VA_ARGS__) -#define vfadd_vf_f16m2_m(...) __riscv_vfadd_vf_f16m2_tumu(__VA_ARGS__) -#define vfadd_vv_f16m4_m(...) __riscv_vfadd_vv_f16m4_tumu(__VA_ARGS__) -#define vfadd_vf_f16m4_m(...) __riscv_vfadd_vf_f16m4_tumu(__VA_ARGS__) -#define vfadd_vv_f16m8_m(...) __riscv_vfadd_vv_f16m8_tumu(__VA_ARGS__) -#define vfadd_vf_f16m8_m(...) __riscv_vfadd_vf_f16m8_tumu(__VA_ARGS__) -#define vfadd_vv_f32mf2_m(...) __riscv_vfadd_vv_f32mf2_tumu(__VA_ARGS__) -#define vfadd_vf_f32mf2_m(...) __riscv_vfadd_vf_f32mf2_tumu(__VA_ARGS__) -#define vfadd_vv_f32m1_m(...) __riscv_vfadd_vv_f32m1_tumu(__VA_ARGS__) -#define vfadd_vf_f32m1_m(...) __riscv_vfadd_vf_f32m1_tumu(__VA_ARGS__) -#define vfadd_vv_f32m2_m(...) __riscv_vfadd_vv_f32m2_tumu(__VA_ARGS__) -#define vfadd_vf_f32m2_m(...) __riscv_vfadd_vf_f32m2_tumu(__VA_ARGS__) -#define vfadd_vv_f32m4_m(...) __riscv_vfadd_vv_f32m4_tumu(__VA_ARGS__) -#define vfadd_vf_f32m4_m(...) __riscv_vfadd_vf_f32m4_tumu(__VA_ARGS__) -#define vfadd_vv_f32m8_m(...) __riscv_vfadd_vv_f32m8_tumu(__VA_ARGS__) -#define vfadd_vf_f32m8_m(...) __riscv_vfadd_vf_f32m8_tumu(__VA_ARGS__) -#define vfadd_vv_f64m1_m(...) __riscv_vfadd_vv_f64m1_tumu(__VA_ARGS__) -#define vfadd_vf_f64m1_m(...) __riscv_vfadd_vf_f64m1_tumu(__VA_ARGS__) -#define vfadd_vv_f64m2_m(...) __riscv_vfadd_vv_f64m2_tumu(__VA_ARGS__) -#define vfadd_vf_f64m2_m(...) __riscv_vfadd_vf_f64m2_tumu(__VA_ARGS__) -#define vfadd_vv_f64m4_m(...) __riscv_vfadd_vv_f64m4_tumu(__VA_ARGS__) -#define vfadd_vf_f64m4_m(...) __riscv_vfadd_vf_f64m4_tumu(__VA_ARGS__) -#define vfadd_vv_f64m8_m(...) __riscv_vfadd_vv_f64m8_tumu(__VA_ARGS__) -#define vfadd_vf_f64m8_m(...) __riscv_vfadd_vf_f64m8_tumu(__VA_ARGS__) -#define vfsub_vv_f16mf4_m(...) __riscv_vfsub_vv_f16mf4_tumu(__VA_ARGS__) -#define vfsub_vf_f16mf4_m(...) __riscv_vfsub_vf_f16mf4_tumu(__VA_ARGS__) -#define vfsub_vv_f16mf2_m(...) __riscv_vfsub_vv_f16mf2_tumu(__VA_ARGS__) -#define vfsub_vf_f16mf2_m(...) __riscv_vfsub_vf_f16mf2_tumu(__VA_ARGS__) -#define vfsub_vv_f16m1_m(...) __riscv_vfsub_vv_f16m1_tumu(__VA_ARGS__) -#define vfsub_vf_f16m1_m(...) __riscv_vfsub_vf_f16m1_tumu(__VA_ARGS__) -#define vfsub_vv_f16m2_m(...) __riscv_vfsub_vv_f16m2_tumu(__VA_ARGS__) -#define vfsub_vf_f16m2_m(...) __riscv_vfsub_vf_f16m2_tumu(__VA_ARGS__) -#define vfsub_vv_f16m4_m(...) __riscv_vfsub_vv_f16m4_tumu(__VA_ARGS__) -#define vfsub_vf_f16m4_m(...) __riscv_vfsub_vf_f16m4_tumu(__VA_ARGS__) -#define vfsub_vv_f16m8_m(...) __riscv_vfsub_vv_f16m8_tumu(__VA_ARGS__) -#define vfsub_vf_f16m8_m(...) __riscv_vfsub_vf_f16m8_tumu(__VA_ARGS__) -#define vfsub_vv_f32mf2_m(...) __riscv_vfsub_vv_f32mf2_tumu(__VA_ARGS__) -#define vfsub_vf_f32mf2_m(...) __riscv_vfsub_vf_f32mf2_tumu(__VA_ARGS__) -#define vfsub_vv_f32m1_m(...) __riscv_vfsub_vv_f32m1_tumu(__VA_ARGS__) -#define vfsub_vf_f32m1_m(...) __riscv_vfsub_vf_f32m1_tumu(__VA_ARGS__) -#define vfsub_vv_f32m2_m(...) __riscv_vfsub_vv_f32m2_tumu(__VA_ARGS__) -#define vfsub_vf_f32m2_m(...) __riscv_vfsub_vf_f32m2_tumu(__VA_ARGS__) -#define vfsub_vv_f32m4_m(...) __riscv_vfsub_vv_f32m4_tumu(__VA_ARGS__) -#define vfsub_vf_f32m4_m(...) __riscv_vfsub_vf_f32m4_tumu(__VA_ARGS__) -#define vfsub_vv_f32m8_m(...) __riscv_vfsub_vv_f32m8_tumu(__VA_ARGS__) -#define vfsub_vf_f32m8_m(...) __riscv_vfsub_vf_f32m8_tumu(__VA_ARGS__) -#define vfsub_vv_f64m1_m(...) __riscv_vfsub_vv_f64m1_tumu(__VA_ARGS__) -#define vfsub_vf_f64m1_m(...) __riscv_vfsub_vf_f64m1_tumu(__VA_ARGS__) -#define vfsub_vv_f64m2_m(...) __riscv_vfsub_vv_f64m2_tumu(__VA_ARGS__) -#define vfsub_vf_f64m2_m(...) __riscv_vfsub_vf_f64m2_tumu(__VA_ARGS__) -#define vfsub_vv_f64m4_m(...) __riscv_vfsub_vv_f64m4_tumu(__VA_ARGS__) -#define vfsub_vf_f64m4_m(...) __riscv_vfsub_vf_f64m4_tumu(__VA_ARGS__) -#define vfsub_vv_f64m8_m(...) __riscv_vfsub_vv_f64m8_tumu(__VA_ARGS__) -#define vfsub_vf_f64m8_m(...) __riscv_vfsub_vf_f64m8_tumu(__VA_ARGS__) -#define vfrsub_vf_f16mf4_m(...) __riscv_vfrsub_vf_f16mf4_tumu(__VA_ARGS__) -#define vfrsub_vf_f16mf2_m(...) __riscv_vfrsub_vf_f16mf2_tumu(__VA_ARGS__) -#define vfrsub_vf_f16m1_m(...) __riscv_vfrsub_vf_f16m1_tumu(__VA_ARGS__) -#define vfrsub_vf_f16m2_m(...) __riscv_vfrsub_vf_f16m2_tumu(__VA_ARGS__) -#define vfrsub_vf_f16m4_m(...) __riscv_vfrsub_vf_f16m4_tumu(__VA_ARGS__) -#define vfrsub_vf_f16m8_m(...) __riscv_vfrsub_vf_f16m8_tumu(__VA_ARGS__) -#define vfrsub_vf_f32mf2_m(...) __riscv_vfrsub_vf_f32mf2_tumu(__VA_ARGS__) -#define vfrsub_vf_f32m1_m(...) __riscv_vfrsub_vf_f32m1_tumu(__VA_ARGS__) -#define vfrsub_vf_f32m2_m(...) __riscv_vfrsub_vf_f32m2_tumu(__VA_ARGS__) -#define vfrsub_vf_f32m4_m(...) __riscv_vfrsub_vf_f32m4_tumu(__VA_ARGS__) -#define vfrsub_vf_f32m8_m(...) __riscv_vfrsub_vf_f32m8_tumu(__VA_ARGS__) -#define vfrsub_vf_f64m1_m(...) __riscv_vfrsub_vf_f64m1_tumu(__VA_ARGS__) -#define vfrsub_vf_f64m2_m(...) __riscv_vfrsub_vf_f64m2_tumu(__VA_ARGS__) -#define vfrsub_vf_f64m4_m(...) __riscv_vfrsub_vf_f64m4_tumu(__VA_ARGS__) -#define vfrsub_vf_f64m8_m(...) __riscv_vfrsub_vf_f64m8_tumu(__VA_ARGS__) -#define vfneg_v_f16mf4_m(...) __riscv_vfneg_v_f16mf4_tumu(__VA_ARGS__) -#define vfneg_v_f16mf2_m(...) __riscv_vfneg_v_f16mf2_tumu(__VA_ARGS__) -#define vfneg_v_f16m1_m(...) __riscv_vfneg_v_f16m1_tumu(__VA_ARGS__) -#define vfneg_v_f16m2_m(...) __riscv_vfneg_v_f16m2_tumu(__VA_ARGS__) -#define vfneg_v_f16m4_m(...) __riscv_vfneg_v_f16m4_tumu(__VA_ARGS__) -#define vfneg_v_f16m8_m(...) __riscv_vfneg_v_f16m8_tumu(__VA_ARGS__) -#define vfneg_v_f32mf2_m(...) __riscv_vfneg_v_f32mf2_tumu(__VA_ARGS__) -#define vfneg_v_f32m1_m(...) __riscv_vfneg_v_f32m1_tumu(__VA_ARGS__) -#define vfneg_v_f32m2_m(...) __riscv_vfneg_v_f32m2_tumu(__VA_ARGS__) -#define vfneg_v_f32m4_m(...) __riscv_vfneg_v_f32m4_tumu(__VA_ARGS__) -#define vfneg_v_f32m8_m(...) __riscv_vfneg_v_f32m8_tumu(__VA_ARGS__) -#define vfneg_v_f64m1_m(...) __riscv_vfneg_v_f64m1_tumu(__VA_ARGS__) -#define vfneg_v_f64m2_m(...) __riscv_vfneg_v_f64m2_tumu(__VA_ARGS__) -#define vfneg_v_f64m4_m(...) __riscv_vfneg_v_f64m4_tumu(__VA_ARGS__) -#define vfneg_v_f64m8_m(...) __riscv_vfneg_v_f64m8_tumu(__VA_ARGS__) -#define vfwadd_vv_f32mf2(...) __riscv_vfwadd_vv_f32mf2(__VA_ARGS__) -#define vfwadd_vf_f32mf2(...) __riscv_vfwadd_vf_f32mf2(__VA_ARGS__) -#define vfwadd_wv_f32mf2(...) __riscv_vfwadd_wv_f32mf2(__VA_ARGS__) -#define vfwadd_wf_f32mf2(...) __riscv_vfwadd_wf_f32mf2(__VA_ARGS__) -#define vfwadd_vv_f32m1(...) __riscv_vfwadd_vv_f32m1(__VA_ARGS__) -#define vfwadd_vf_f32m1(...) __riscv_vfwadd_vf_f32m1(__VA_ARGS__) -#define vfwadd_wv_f32m1(...) __riscv_vfwadd_wv_f32m1(__VA_ARGS__) -#define vfwadd_wf_f32m1(...) __riscv_vfwadd_wf_f32m1(__VA_ARGS__) -#define vfwadd_vv_f32m2(...) __riscv_vfwadd_vv_f32m2(__VA_ARGS__) -#define vfwadd_vf_f32m2(...) __riscv_vfwadd_vf_f32m2(__VA_ARGS__) -#define vfwadd_wv_f32m2(...) __riscv_vfwadd_wv_f32m2(__VA_ARGS__) -#define vfwadd_wf_f32m2(...) __riscv_vfwadd_wf_f32m2(__VA_ARGS__) -#define vfwadd_vv_f32m4(...) __riscv_vfwadd_vv_f32m4(__VA_ARGS__) -#define vfwadd_vf_f32m4(...) __riscv_vfwadd_vf_f32m4(__VA_ARGS__) -#define vfwadd_wv_f32m4(...) __riscv_vfwadd_wv_f32m4(__VA_ARGS__) -#define vfwadd_wf_f32m4(...) __riscv_vfwadd_wf_f32m4(__VA_ARGS__) -#define vfwadd_vv_f32m8(...) __riscv_vfwadd_vv_f32m8(__VA_ARGS__) -#define vfwadd_vf_f32m8(...) __riscv_vfwadd_vf_f32m8(__VA_ARGS__) -#define vfwadd_wv_f32m8(...) __riscv_vfwadd_wv_f32m8(__VA_ARGS__) -#define vfwadd_wf_f32m8(...) __riscv_vfwadd_wf_f32m8(__VA_ARGS__) -#define vfwadd_vv_f64m1(...) __riscv_vfwadd_vv_f64m1(__VA_ARGS__) -#define vfwadd_vf_f64m1(...) __riscv_vfwadd_vf_f64m1(__VA_ARGS__) -#define vfwadd_wv_f64m1(...) __riscv_vfwadd_wv_f64m1(__VA_ARGS__) -#define vfwadd_wf_f64m1(...) __riscv_vfwadd_wf_f64m1(__VA_ARGS__) -#define vfwadd_vv_f64m2(...) __riscv_vfwadd_vv_f64m2(__VA_ARGS__) -#define vfwadd_vf_f64m2(...) __riscv_vfwadd_vf_f64m2(__VA_ARGS__) -#define vfwadd_wv_f64m2(...) __riscv_vfwadd_wv_f64m2(__VA_ARGS__) -#define vfwadd_wf_f64m2(...) __riscv_vfwadd_wf_f64m2(__VA_ARGS__) -#define vfwadd_vv_f64m4(...) __riscv_vfwadd_vv_f64m4(__VA_ARGS__) -#define vfwadd_vf_f64m4(...) __riscv_vfwadd_vf_f64m4(__VA_ARGS__) -#define vfwadd_wv_f64m4(...) __riscv_vfwadd_wv_f64m4(__VA_ARGS__) -#define vfwadd_wf_f64m4(...) __riscv_vfwadd_wf_f64m4(__VA_ARGS__) -#define vfwadd_vv_f64m8(...) __riscv_vfwadd_vv_f64m8(__VA_ARGS__) -#define vfwadd_vf_f64m8(...) __riscv_vfwadd_vf_f64m8(__VA_ARGS__) -#define vfwadd_wv_f64m8(...) __riscv_vfwadd_wv_f64m8(__VA_ARGS__) -#define vfwadd_wf_f64m8(...) __riscv_vfwadd_wf_f64m8(__VA_ARGS__) -#define vfwsub_vv_f32mf2(...) __riscv_vfwsub_vv_f32mf2(__VA_ARGS__) -#define vfwsub_vf_f32mf2(...) __riscv_vfwsub_vf_f32mf2(__VA_ARGS__) -#define vfwsub_wv_f32mf2(...) __riscv_vfwsub_wv_f32mf2(__VA_ARGS__) -#define vfwsub_wf_f32mf2(...) __riscv_vfwsub_wf_f32mf2(__VA_ARGS__) -#define vfwsub_vv_f32m1(...) __riscv_vfwsub_vv_f32m1(__VA_ARGS__) -#define vfwsub_vf_f32m1(...) __riscv_vfwsub_vf_f32m1(__VA_ARGS__) -#define vfwsub_wv_f32m1(...) __riscv_vfwsub_wv_f32m1(__VA_ARGS__) -#define vfwsub_wf_f32m1(...) __riscv_vfwsub_wf_f32m1(__VA_ARGS__) -#define vfwsub_vv_f32m2(...) __riscv_vfwsub_vv_f32m2(__VA_ARGS__) -#define vfwsub_vf_f32m2(...) __riscv_vfwsub_vf_f32m2(__VA_ARGS__) -#define vfwsub_wv_f32m2(...) __riscv_vfwsub_wv_f32m2(__VA_ARGS__) -#define vfwsub_wf_f32m2(...) __riscv_vfwsub_wf_f32m2(__VA_ARGS__) -#define vfwsub_vv_f32m4(...) __riscv_vfwsub_vv_f32m4(__VA_ARGS__) -#define vfwsub_vf_f32m4(...) __riscv_vfwsub_vf_f32m4(__VA_ARGS__) -#define vfwsub_wv_f32m4(...) __riscv_vfwsub_wv_f32m4(__VA_ARGS__) -#define vfwsub_wf_f32m4(...) __riscv_vfwsub_wf_f32m4(__VA_ARGS__) -#define vfwsub_vv_f32m8(...) __riscv_vfwsub_vv_f32m8(__VA_ARGS__) -#define vfwsub_vf_f32m8(...) __riscv_vfwsub_vf_f32m8(__VA_ARGS__) -#define vfwsub_wv_f32m8(...) __riscv_vfwsub_wv_f32m8(__VA_ARGS__) -#define vfwsub_wf_f32m8(...) __riscv_vfwsub_wf_f32m8(__VA_ARGS__) -#define vfwsub_vv_f64m1(...) __riscv_vfwsub_vv_f64m1(__VA_ARGS__) -#define vfwsub_vf_f64m1(...) __riscv_vfwsub_vf_f64m1(__VA_ARGS__) -#define vfwsub_wv_f64m1(...) __riscv_vfwsub_wv_f64m1(__VA_ARGS__) -#define vfwsub_wf_f64m1(...) __riscv_vfwsub_wf_f64m1(__VA_ARGS__) -#define vfwsub_vv_f64m2(...) __riscv_vfwsub_vv_f64m2(__VA_ARGS__) -#define vfwsub_vf_f64m2(...) __riscv_vfwsub_vf_f64m2(__VA_ARGS__) -#define vfwsub_wv_f64m2(...) __riscv_vfwsub_wv_f64m2(__VA_ARGS__) -#define vfwsub_wf_f64m2(...) __riscv_vfwsub_wf_f64m2(__VA_ARGS__) -#define vfwsub_vv_f64m4(...) __riscv_vfwsub_vv_f64m4(__VA_ARGS__) -#define vfwsub_vf_f64m4(...) __riscv_vfwsub_vf_f64m4(__VA_ARGS__) -#define vfwsub_wv_f64m4(...) __riscv_vfwsub_wv_f64m4(__VA_ARGS__) -#define vfwsub_wf_f64m4(...) __riscv_vfwsub_wf_f64m4(__VA_ARGS__) -#define vfwsub_vv_f64m8(...) __riscv_vfwsub_vv_f64m8(__VA_ARGS__) -#define vfwsub_vf_f64m8(...) __riscv_vfwsub_vf_f64m8(__VA_ARGS__) -#define vfwsub_wv_f64m8(...) __riscv_vfwsub_wv_f64m8(__VA_ARGS__) -#define vfwsub_wf_f64m8(...) __riscv_vfwsub_wf_f64m8(__VA_ARGS__) -// masked functions -#define vfwadd_vv_f32mf2_m(...) __riscv_vfwadd_vv_f32mf2_tumu(__VA_ARGS__) -#define vfwadd_vf_f32mf2_m(...) __riscv_vfwadd_vf_f32mf2_tumu(__VA_ARGS__) -#define vfwadd_wv_f32mf2_m(...) __riscv_vfwadd_wv_f32mf2_tumu(__VA_ARGS__) -#define vfwadd_wf_f32mf2_m(...) __riscv_vfwadd_wf_f32mf2_tumu(__VA_ARGS__) -#define vfwadd_vv_f32m1_m(...) __riscv_vfwadd_vv_f32m1_tumu(__VA_ARGS__) -#define vfwadd_vf_f32m1_m(...) __riscv_vfwadd_vf_f32m1_tumu(__VA_ARGS__) -#define vfwadd_wv_f32m1_m(...) __riscv_vfwadd_wv_f32m1_tumu(__VA_ARGS__) -#define vfwadd_wf_f32m1_m(...) __riscv_vfwadd_wf_f32m1_tumu(__VA_ARGS__) -#define vfwadd_vv_f32m2_m(...) __riscv_vfwadd_vv_f32m2_tumu(__VA_ARGS__) -#define vfwadd_vf_f32m2_m(...) __riscv_vfwadd_vf_f32m2_tumu(__VA_ARGS__) -#define vfwadd_wv_f32m2_m(...) __riscv_vfwadd_wv_f32m2_tumu(__VA_ARGS__) -#define vfwadd_wf_f32m2_m(...) __riscv_vfwadd_wf_f32m2_tumu(__VA_ARGS__) -#define vfwadd_vv_f32m4_m(...) __riscv_vfwadd_vv_f32m4_tumu(__VA_ARGS__) -#define vfwadd_vf_f32m4_m(...) __riscv_vfwadd_vf_f32m4_tumu(__VA_ARGS__) -#define vfwadd_wv_f32m4_m(...) __riscv_vfwadd_wv_f32m4_tumu(__VA_ARGS__) -#define vfwadd_wf_f32m4_m(...) __riscv_vfwadd_wf_f32m4_tumu(__VA_ARGS__) -#define vfwadd_vv_f32m8_m(...) __riscv_vfwadd_vv_f32m8_tumu(__VA_ARGS__) -#define vfwadd_vf_f32m8_m(...) __riscv_vfwadd_vf_f32m8_tumu(__VA_ARGS__) -#define vfwadd_wv_f32m8_m(...) __riscv_vfwadd_wv_f32m8_tumu(__VA_ARGS__) -#define vfwadd_wf_f32m8_m(...) __riscv_vfwadd_wf_f32m8_tumu(__VA_ARGS__) -#define vfwadd_vv_f64m1_m(...) __riscv_vfwadd_vv_f64m1_tumu(__VA_ARGS__) -#define vfwadd_vf_f64m1_m(...) __riscv_vfwadd_vf_f64m1_tumu(__VA_ARGS__) -#define vfwadd_wv_f64m1_m(...) __riscv_vfwadd_wv_f64m1_tumu(__VA_ARGS__) -#define vfwadd_wf_f64m1_m(...) __riscv_vfwadd_wf_f64m1_tumu(__VA_ARGS__) -#define vfwadd_vv_f64m2_m(...) __riscv_vfwadd_vv_f64m2_tumu(__VA_ARGS__) -#define vfwadd_vf_f64m2_m(...) __riscv_vfwadd_vf_f64m2_tumu(__VA_ARGS__) -#define vfwadd_wv_f64m2_m(...) __riscv_vfwadd_wv_f64m2_tumu(__VA_ARGS__) -#define vfwadd_wf_f64m2_m(...) __riscv_vfwadd_wf_f64m2_tumu(__VA_ARGS__) -#define vfwadd_vv_f64m4_m(...) __riscv_vfwadd_vv_f64m4_tumu(__VA_ARGS__) -#define vfwadd_vf_f64m4_m(...) __riscv_vfwadd_vf_f64m4_tumu(__VA_ARGS__) -#define vfwadd_wv_f64m4_m(...) __riscv_vfwadd_wv_f64m4_tumu(__VA_ARGS__) -#define vfwadd_wf_f64m4_m(...) __riscv_vfwadd_wf_f64m4_tumu(__VA_ARGS__) -#define vfwadd_vv_f64m8_m(...) __riscv_vfwadd_vv_f64m8_tumu(__VA_ARGS__) -#define vfwadd_vf_f64m8_m(...) __riscv_vfwadd_vf_f64m8_tumu(__VA_ARGS__) -#define vfwadd_wv_f64m8_m(...) __riscv_vfwadd_wv_f64m8_tumu(__VA_ARGS__) -#define vfwadd_wf_f64m8_m(...) __riscv_vfwadd_wf_f64m8_tumu(__VA_ARGS__) -#define vfwsub_vv_f32mf2_m(...) __riscv_vfwsub_vv_f32mf2_tumu(__VA_ARGS__) -#define vfwsub_vf_f32mf2_m(...) __riscv_vfwsub_vf_f32mf2_tumu(__VA_ARGS__) -#define vfwsub_wv_f32mf2_m(...) __riscv_vfwsub_wv_f32mf2_tumu(__VA_ARGS__) -#define vfwsub_wf_f32mf2_m(...) __riscv_vfwsub_wf_f32mf2_tumu(__VA_ARGS__) -#define vfwsub_vv_f32m1_m(...) __riscv_vfwsub_vv_f32m1_tumu(__VA_ARGS__) -#define vfwsub_vf_f32m1_m(...) __riscv_vfwsub_vf_f32m1_tumu(__VA_ARGS__) -#define vfwsub_wv_f32m1_m(...) __riscv_vfwsub_wv_f32m1_tumu(__VA_ARGS__) -#define vfwsub_wf_f32m1_m(...) __riscv_vfwsub_wf_f32m1_tumu(__VA_ARGS__) -#define vfwsub_vv_f32m2_m(...) __riscv_vfwsub_vv_f32m2_tumu(__VA_ARGS__) -#define vfwsub_vf_f32m2_m(...) __riscv_vfwsub_vf_f32m2_tumu(__VA_ARGS__) -#define vfwsub_wv_f32m2_m(...) __riscv_vfwsub_wv_f32m2_tumu(__VA_ARGS__) -#define vfwsub_wf_f32m2_m(...) __riscv_vfwsub_wf_f32m2_tumu(__VA_ARGS__) -#define vfwsub_vv_f32m4_m(...) __riscv_vfwsub_vv_f32m4_tumu(__VA_ARGS__) -#define vfwsub_vf_f32m4_m(...) __riscv_vfwsub_vf_f32m4_tumu(__VA_ARGS__) -#define vfwsub_wv_f32m4_m(...) __riscv_vfwsub_wv_f32m4_tumu(__VA_ARGS__) -#define vfwsub_wf_f32m4_m(...) __riscv_vfwsub_wf_f32m4_tumu(__VA_ARGS__) -#define vfwsub_vv_f32m8_m(...) __riscv_vfwsub_vv_f32m8_tumu(__VA_ARGS__) -#define vfwsub_vf_f32m8_m(...) __riscv_vfwsub_vf_f32m8_tumu(__VA_ARGS__) -#define vfwsub_wv_f32m8_m(...) __riscv_vfwsub_wv_f32m8_tumu(__VA_ARGS__) -#define vfwsub_wf_f32m8_m(...) __riscv_vfwsub_wf_f32m8_tumu(__VA_ARGS__) -#define vfwsub_vv_f64m1_m(...) __riscv_vfwsub_vv_f64m1_tumu(__VA_ARGS__) -#define vfwsub_vf_f64m1_m(...) __riscv_vfwsub_vf_f64m1_tumu(__VA_ARGS__) -#define vfwsub_wv_f64m1_m(...) __riscv_vfwsub_wv_f64m1_tumu(__VA_ARGS__) -#define vfwsub_wf_f64m1_m(...) __riscv_vfwsub_wf_f64m1_tumu(__VA_ARGS__) -#define vfwsub_vv_f64m2_m(...) __riscv_vfwsub_vv_f64m2_tumu(__VA_ARGS__) -#define vfwsub_vf_f64m2_m(...) __riscv_vfwsub_vf_f64m2_tumu(__VA_ARGS__) -#define vfwsub_wv_f64m2_m(...) __riscv_vfwsub_wv_f64m2_tumu(__VA_ARGS__) -#define vfwsub_wf_f64m2_m(...) __riscv_vfwsub_wf_f64m2_tumu(__VA_ARGS__) -#define vfwsub_vv_f64m4_m(...) __riscv_vfwsub_vv_f64m4_tumu(__VA_ARGS__) -#define vfwsub_vf_f64m4_m(...) __riscv_vfwsub_vf_f64m4_tumu(__VA_ARGS__) -#define vfwsub_wv_f64m4_m(...) __riscv_vfwsub_wv_f64m4_tumu(__VA_ARGS__) -#define vfwsub_wf_f64m4_m(...) __riscv_vfwsub_wf_f64m4_tumu(__VA_ARGS__) -#define vfwsub_vv_f64m8_m(...) __riscv_vfwsub_vv_f64m8_tumu(__VA_ARGS__) -#define vfwsub_vf_f64m8_m(...) __riscv_vfwsub_vf_f64m8_tumu(__VA_ARGS__) -#define vfwsub_wv_f64m8_m(...) __riscv_vfwsub_wv_f64m8_tumu(__VA_ARGS__) -#define vfwsub_wf_f64m8_m(...) __riscv_vfwsub_wf_f64m8_tumu(__VA_ARGS__) -#define vfmul_vv_f16mf4(...) __riscv_vfmul_vv_f16mf4(__VA_ARGS__) -#define vfmul_vf_f16mf4(...) __riscv_vfmul_vf_f16mf4(__VA_ARGS__) -#define vfmul_vv_f16mf2(...) __riscv_vfmul_vv_f16mf2(__VA_ARGS__) -#define vfmul_vf_f16mf2(...) __riscv_vfmul_vf_f16mf2(__VA_ARGS__) -#define vfmul_vv_f16m1(...) __riscv_vfmul_vv_f16m1(__VA_ARGS__) -#define vfmul_vf_f16m1(...) __riscv_vfmul_vf_f16m1(__VA_ARGS__) -#define vfmul_vv_f16m2(...) __riscv_vfmul_vv_f16m2(__VA_ARGS__) -#define vfmul_vf_f16m2(...) __riscv_vfmul_vf_f16m2(__VA_ARGS__) -#define vfmul_vv_f16m4(...) __riscv_vfmul_vv_f16m4(__VA_ARGS__) -#define vfmul_vf_f16m4(...) __riscv_vfmul_vf_f16m4(__VA_ARGS__) -#define vfmul_vv_f16m8(...) __riscv_vfmul_vv_f16m8(__VA_ARGS__) -#define vfmul_vf_f16m8(...) __riscv_vfmul_vf_f16m8(__VA_ARGS__) -#define vfmul_vv_f32mf2(...) __riscv_vfmul_vv_f32mf2(__VA_ARGS__) -#define vfmul_vf_f32mf2(...) __riscv_vfmul_vf_f32mf2(__VA_ARGS__) -#define vfmul_vv_f32m1(...) __riscv_vfmul_vv_f32m1(__VA_ARGS__) -#define vfmul_vf_f32m1(...) __riscv_vfmul_vf_f32m1(__VA_ARGS__) -#define vfmul_vv_f32m2(...) __riscv_vfmul_vv_f32m2(__VA_ARGS__) -#define vfmul_vf_f32m2(...) __riscv_vfmul_vf_f32m2(__VA_ARGS__) -#define vfmul_vv_f32m4(...) __riscv_vfmul_vv_f32m4(__VA_ARGS__) -#define vfmul_vf_f32m4(...) __riscv_vfmul_vf_f32m4(__VA_ARGS__) -#define vfmul_vv_f32m8(...) __riscv_vfmul_vv_f32m8(__VA_ARGS__) -#define vfmul_vf_f32m8(...) __riscv_vfmul_vf_f32m8(__VA_ARGS__) -#define vfmul_vv_f64m1(...) __riscv_vfmul_vv_f64m1(__VA_ARGS__) -#define vfmul_vf_f64m1(...) __riscv_vfmul_vf_f64m1(__VA_ARGS__) -#define vfmul_vv_f64m2(...) __riscv_vfmul_vv_f64m2(__VA_ARGS__) -#define vfmul_vf_f64m2(...) __riscv_vfmul_vf_f64m2(__VA_ARGS__) -#define vfmul_vv_f64m4(...) __riscv_vfmul_vv_f64m4(__VA_ARGS__) -#define vfmul_vf_f64m4(...) __riscv_vfmul_vf_f64m4(__VA_ARGS__) -#define vfmul_vv_f64m8(...) __riscv_vfmul_vv_f64m8(__VA_ARGS__) -#define vfmul_vf_f64m8(...) __riscv_vfmul_vf_f64m8(__VA_ARGS__) -#define vfdiv_vv_f16mf4(...) __riscv_vfdiv_vv_f16mf4(__VA_ARGS__) -#define vfdiv_vf_f16mf4(...) __riscv_vfdiv_vf_f16mf4(__VA_ARGS__) -#define vfdiv_vv_f16mf2(...) __riscv_vfdiv_vv_f16mf2(__VA_ARGS__) -#define vfdiv_vf_f16mf2(...) __riscv_vfdiv_vf_f16mf2(__VA_ARGS__) -#define vfdiv_vv_f16m1(...) __riscv_vfdiv_vv_f16m1(__VA_ARGS__) -#define vfdiv_vf_f16m1(...) __riscv_vfdiv_vf_f16m1(__VA_ARGS__) -#define vfdiv_vv_f16m2(...) __riscv_vfdiv_vv_f16m2(__VA_ARGS__) -#define vfdiv_vf_f16m2(...) __riscv_vfdiv_vf_f16m2(__VA_ARGS__) -#define vfdiv_vv_f16m4(...) __riscv_vfdiv_vv_f16m4(__VA_ARGS__) -#define vfdiv_vf_f16m4(...) __riscv_vfdiv_vf_f16m4(__VA_ARGS__) -#define vfdiv_vv_f16m8(...) __riscv_vfdiv_vv_f16m8(__VA_ARGS__) -#define vfdiv_vf_f16m8(...) __riscv_vfdiv_vf_f16m8(__VA_ARGS__) -#define vfdiv_vv_f32mf2(...) __riscv_vfdiv_vv_f32mf2(__VA_ARGS__) -#define vfdiv_vf_f32mf2(...) __riscv_vfdiv_vf_f32mf2(__VA_ARGS__) -#define vfdiv_vv_f32m1(...) __riscv_vfdiv_vv_f32m1(__VA_ARGS__) -#define vfdiv_vf_f32m1(...) __riscv_vfdiv_vf_f32m1(__VA_ARGS__) -#define vfdiv_vv_f32m2(...) __riscv_vfdiv_vv_f32m2(__VA_ARGS__) -#define vfdiv_vf_f32m2(...) __riscv_vfdiv_vf_f32m2(__VA_ARGS__) -#define vfdiv_vv_f32m4(...) __riscv_vfdiv_vv_f32m4(__VA_ARGS__) -#define vfdiv_vf_f32m4(...) __riscv_vfdiv_vf_f32m4(__VA_ARGS__) -#define vfdiv_vv_f32m8(...) __riscv_vfdiv_vv_f32m8(__VA_ARGS__) -#define vfdiv_vf_f32m8(...) __riscv_vfdiv_vf_f32m8(__VA_ARGS__) -#define vfdiv_vv_f64m1(...) __riscv_vfdiv_vv_f64m1(__VA_ARGS__) -#define vfdiv_vf_f64m1(...) __riscv_vfdiv_vf_f64m1(__VA_ARGS__) -#define vfdiv_vv_f64m2(...) __riscv_vfdiv_vv_f64m2(__VA_ARGS__) -#define vfdiv_vf_f64m2(...) __riscv_vfdiv_vf_f64m2(__VA_ARGS__) -#define vfdiv_vv_f64m4(...) __riscv_vfdiv_vv_f64m4(__VA_ARGS__) -#define vfdiv_vf_f64m4(...) __riscv_vfdiv_vf_f64m4(__VA_ARGS__) -#define vfdiv_vv_f64m8(...) __riscv_vfdiv_vv_f64m8(__VA_ARGS__) -#define vfdiv_vf_f64m8(...) __riscv_vfdiv_vf_f64m8(__VA_ARGS__) -#define vfrdiv_vf_f16mf4(...) __riscv_vfrdiv_vf_f16mf4(__VA_ARGS__) -#define vfrdiv_vf_f16mf2(...) __riscv_vfrdiv_vf_f16mf2(__VA_ARGS__) -#define vfrdiv_vf_f16m1(...) __riscv_vfrdiv_vf_f16m1(__VA_ARGS__) -#define vfrdiv_vf_f16m2(...) __riscv_vfrdiv_vf_f16m2(__VA_ARGS__) -#define vfrdiv_vf_f16m4(...) __riscv_vfrdiv_vf_f16m4(__VA_ARGS__) -#define vfrdiv_vf_f16m8(...) __riscv_vfrdiv_vf_f16m8(__VA_ARGS__) -#define vfrdiv_vf_f32mf2(...) __riscv_vfrdiv_vf_f32mf2(__VA_ARGS__) -#define vfrdiv_vf_f32m1(...) __riscv_vfrdiv_vf_f32m1(__VA_ARGS__) -#define vfrdiv_vf_f32m2(...) __riscv_vfrdiv_vf_f32m2(__VA_ARGS__) -#define vfrdiv_vf_f32m4(...) __riscv_vfrdiv_vf_f32m4(__VA_ARGS__) -#define vfrdiv_vf_f32m8(...) __riscv_vfrdiv_vf_f32m8(__VA_ARGS__) -#define vfrdiv_vf_f64m1(...) __riscv_vfrdiv_vf_f64m1(__VA_ARGS__) -#define vfrdiv_vf_f64m2(...) __riscv_vfrdiv_vf_f64m2(__VA_ARGS__) -#define vfrdiv_vf_f64m4(...) __riscv_vfrdiv_vf_f64m4(__VA_ARGS__) -#define vfrdiv_vf_f64m8(...) __riscv_vfrdiv_vf_f64m8(__VA_ARGS__) -// masked functions -#define vfmul_vv_f16mf4_m(...) __riscv_vfmul_vv_f16mf4_tumu(__VA_ARGS__) -#define vfmul_vf_f16mf4_m(...) __riscv_vfmul_vf_f16mf4_tumu(__VA_ARGS__) -#define vfmul_vv_f16mf2_m(...) __riscv_vfmul_vv_f16mf2_tumu(__VA_ARGS__) -#define vfmul_vf_f16mf2_m(...) __riscv_vfmul_vf_f16mf2_tumu(__VA_ARGS__) -#define vfmul_vv_f16m1_m(...) __riscv_vfmul_vv_f16m1_tumu(__VA_ARGS__) -#define vfmul_vf_f16m1_m(...) __riscv_vfmul_vf_f16m1_tumu(__VA_ARGS__) -#define vfmul_vv_f16m2_m(...) __riscv_vfmul_vv_f16m2_tumu(__VA_ARGS__) -#define vfmul_vf_f16m2_m(...) __riscv_vfmul_vf_f16m2_tumu(__VA_ARGS__) -#define vfmul_vv_f16m4_m(...) __riscv_vfmul_vv_f16m4_tumu(__VA_ARGS__) -#define vfmul_vf_f16m4_m(...) __riscv_vfmul_vf_f16m4_tumu(__VA_ARGS__) -#define vfmul_vv_f16m8_m(...) __riscv_vfmul_vv_f16m8_tumu(__VA_ARGS__) -#define vfmul_vf_f16m8_m(...) __riscv_vfmul_vf_f16m8_tumu(__VA_ARGS__) -#define vfmul_vv_f32mf2_m(...) __riscv_vfmul_vv_f32mf2_tumu(__VA_ARGS__) -#define vfmul_vf_f32mf2_m(...) __riscv_vfmul_vf_f32mf2_tumu(__VA_ARGS__) -#define vfmul_vv_f32m1_m(...) __riscv_vfmul_vv_f32m1_tumu(__VA_ARGS__) -#define vfmul_vf_f32m1_m(...) __riscv_vfmul_vf_f32m1_tumu(__VA_ARGS__) -#define vfmul_vv_f32m2_m(...) __riscv_vfmul_vv_f32m2_tumu(__VA_ARGS__) -#define vfmul_vf_f32m2_m(...) __riscv_vfmul_vf_f32m2_tumu(__VA_ARGS__) -#define vfmul_vv_f32m4_m(...) __riscv_vfmul_vv_f32m4_tumu(__VA_ARGS__) -#define vfmul_vf_f32m4_m(...) __riscv_vfmul_vf_f32m4_tumu(__VA_ARGS__) -#define vfmul_vv_f32m8_m(...) __riscv_vfmul_vv_f32m8_tumu(__VA_ARGS__) -#define vfmul_vf_f32m8_m(...) __riscv_vfmul_vf_f32m8_tumu(__VA_ARGS__) -#define vfmul_vv_f64m1_m(...) __riscv_vfmul_vv_f64m1_tumu(__VA_ARGS__) -#define vfmul_vf_f64m1_m(...) __riscv_vfmul_vf_f64m1_tumu(__VA_ARGS__) -#define vfmul_vv_f64m2_m(...) __riscv_vfmul_vv_f64m2_tumu(__VA_ARGS__) -#define vfmul_vf_f64m2_m(...) __riscv_vfmul_vf_f64m2_tumu(__VA_ARGS__) -#define vfmul_vv_f64m4_m(...) __riscv_vfmul_vv_f64m4_tumu(__VA_ARGS__) -#define vfmul_vf_f64m4_m(...) __riscv_vfmul_vf_f64m4_tumu(__VA_ARGS__) -#define vfmul_vv_f64m8_m(...) __riscv_vfmul_vv_f64m8_tumu(__VA_ARGS__) -#define vfmul_vf_f64m8_m(...) __riscv_vfmul_vf_f64m8_tumu(__VA_ARGS__) -#define vfdiv_vv_f16mf4_m(...) __riscv_vfdiv_vv_f16mf4_tumu(__VA_ARGS__) -#define vfdiv_vf_f16mf4_m(...) __riscv_vfdiv_vf_f16mf4_tumu(__VA_ARGS__) -#define vfdiv_vv_f16mf2_m(...) __riscv_vfdiv_vv_f16mf2_tumu(__VA_ARGS__) -#define vfdiv_vf_f16mf2_m(...) __riscv_vfdiv_vf_f16mf2_tumu(__VA_ARGS__) -#define vfdiv_vv_f16m1_m(...) __riscv_vfdiv_vv_f16m1_tumu(__VA_ARGS__) -#define vfdiv_vf_f16m1_m(...) __riscv_vfdiv_vf_f16m1_tumu(__VA_ARGS__) -#define vfdiv_vv_f16m2_m(...) __riscv_vfdiv_vv_f16m2_tumu(__VA_ARGS__) -#define vfdiv_vf_f16m2_m(...) __riscv_vfdiv_vf_f16m2_tumu(__VA_ARGS__) -#define vfdiv_vv_f16m4_m(...) __riscv_vfdiv_vv_f16m4_tumu(__VA_ARGS__) -#define vfdiv_vf_f16m4_m(...) __riscv_vfdiv_vf_f16m4_tumu(__VA_ARGS__) -#define vfdiv_vv_f16m8_m(...) __riscv_vfdiv_vv_f16m8_tumu(__VA_ARGS__) -#define vfdiv_vf_f16m8_m(...) __riscv_vfdiv_vf_f16m8_tumu(__VA_ARGS__) -#define vfdiv_vv_f32mf2_m(...) __riscv_vfdiv_vv_f32mf2_tumu(__VA_ARGS__) -#define vfdiv_vf_f32mf2_m(...) __riscv_vfdiv_vf_f32mf2_tumu(__VA_ARGS__) -#define vfdiv_vv_f32m1_m(...) __riscv_vfdiv_vv_f32m1_tumu(__VA_ARGS__) -#define vfdiv_vf_f32m1_m(...) __riscv_vfdiv_vf_f32m1_tumu(__VA_ARGS__) -#define vfdiv_vv_f32m2_m(...) __riscv_vfdiv_vv_f32m2_tumu(__VA_ARGS__) -#define vfdiv_vf_f32m2_m(...) __riscv_vfdiv_vf_f32m2_tumu(__VA_ARGS__) -#define vfdiv_vv_f32m4_m(...) __riscv_vfdiv_vv_f32m4_tumu(__VA_ARGS__) -#define vfdiv_vf_f32m4_m(...) __riscv_vfdiv_vf_f32m4_tumu(__VA_ARGS__) -#define vfdiv_vv_f32m8_m(...) __riscv_vfdiv_vv_f32m8_tumu(__VA_ARGS__) -#define vfdiv_vf_f32m8_m(...) __riscv_vfdiv_vf_f32m8_tumu(__VA_ARGS__) -#define vfdiv_vv_f64m1_m(...) __riscv_vfdiv_vv_f64m1_tumu(__VA_ARGS__) -#define vfdiv_vf_f64m1_m(...) __riscv_vfdiv_vf_f64m1_tumu(__VA_ARGS__) -#define vfdiv_vv_f64m2_m(...) __riscv_vfdiv_vv_f64m2_tumu(__VA_ARGS__) -#define vfdiv_vf_f64m2_m(...) __riscv_vfdiv_vf_f64m2_tumu(__VA_ARGS__) -#define vfdiv_vv_f64m4_m(...) __riscv_vfdiv_vv_f64m4_tumu(__VA_ARGS__) -#define vfdiv_vf_f64m4_m(...) __riscv_vfdiv_vf_f64m4_tumu(__VA_ARGS__) -#define vfdiv_vv_f64m8_m(...) __riscv_vfdiv_vv_f64m8_tumu(__VA_ARGS__) -#define vfdiv_vf_f64m8_m(...) __riscv_vfdiv_vf_f64m8_tumu(__VA_ARGS__) -#define vfrdiv_vf_f16mf4_m(...) __riscv_vfrdiv_vf_f16mf4_tumu(__VA_ARGS__) -#define vfrdiv_vf_f16mf2_m(...) __riscv_vfrdiv_vf_f16mf2_tumu(__VA_ARGS__) -#define vfrdiv_vf_f16m1_m(...) __riscv_vfrdiv_vf_f16m1_tumu(__VA_ARGS__) -#define vfrdiv_vf_f16m2_m(...) __riscv_vfrdiv_vf_f16m2_tumu(__VA_ARGS__) -#define vfrdiv_vf_f16m4_m(...) __riscv_vfrdiv_vf_f16m4_tumu(__VA_ARGS__) -#define vfrdiv_vf_f16m8_m(...) __riscv_vfrdiv_vf_f16m8_tumu(__VA_ARGS__) -#define vfrdiv_vf_f32mf2_m(...) __riscv_vfrdiv_vf_f32mf2_tumu(__VA_ARGS__) -#define vfrdiv_vf_f32m1_m(...) __riscv_vfrdiv_vf_f32m1_tumu(__VA_ARGS__) -#define vfrdiv_vf_f32m2_m(...) __riscv_vfrdiv_vf_f32m2_tumu(__VA_ARGS__) -#define vfrdiv_vf_f32m4_m(...) __riscv_vfrdiv_vf_f32m4_tumu(__VA_ARGS__) -#define vfrdiv_vf_f32m8_m(...) __riscv_vfrdiv_vf_f32m8_tumu(__VA_ARGS__) -#define vfrdiv_vf_f64m1_m(...) __riscv_vfrdiv_vf_f64m1_tumu(__VA_ARGS__) -#define vfrdiv_vf_f64m2_m(...) __riscv_vfrdiv_vf_f64m2_tumu(__VA_ARGS__) -#define vfrdiv_vf_f64m4_m(...) __riscv_vfrdiv_vf_f64m4_tumu(__VA_ARGS__) -#define vfrdiv_vf_f64m8_m(...) __riscv_vfrdiv_vf_f64m8_tumu(__VA_ARGS__) -#define vfwmul_vv_f32mf2(...) __riscv_vfwmul_vv_f32mf2(__VA_ARGS__) -#define vfwmul_vf_f32mf2(...) __riscv_vfwmul_vf_f32mf2(__VA_ARGS__) -#define vfwmul_vv_f32m1(...) __riscv_vfwmul_vv_f32m1(__VA_ARGS__) -#define vfwmul_vf_f32m1(...) __riscv_vfwmul_vf_f32m1(__VA_ARGS__) -#define vfwmul_vv_f32m2(...) __riscv_vfwmul_vv_f32m2(__VA_ARGS__) -#define vfwmul_vf_f32m2(...) __riscv_vfwmul_vf_f32m2(__VA_ARGS__) -#define vfwmul_vv_f32m4(...) __riscv_vfwmul_vv_f32m4(__VA_ARGS__) -#define vfwmul_vf_f32m4(...) __riscv_vfwmul_vf_f32m4(__VA_ARGS__) -#define vfwmul_vv_f32m8(...) __riscv_vfwmul_vv_f32m8(__VA_ARGS__) -#define vfwmul_vf_f32m8(...) __riscv_vfwmul_vf_f32m8(__VA_ARGS__) -#define vfwmul_vv_f64m1(...) __riscv_vfwmul_vv_f64m1(__VA_ARGS__) -#define vfwmul_vf_f64m1(...) __riscv_vfwmul_vf_f64m1(__VA_ARGS__) -#define vfwmul_vv_f64m2(...) __riscv_vfwmul_vv_f64m2(__VA_ARGS__) -#define vfwmul_vf_f64m2(...) __riscv_vfwmul_vf_f64m2(__VA_ARGS__) -#define vfwmul_vv_f64m4(...) __riscv_vfwmul_vv_f64m4(__VA_ARGS__) -#define vfwmul_vf_f64m4(...) __riscv_vfwmul_vf_f64m4(__VA_ARGS__) -#define vfwmul_vv_f64m8(...) __riscv_vfwmul_vv_f64m8(__VA_ARGS__) -#define vfwmul_vf_f64m8(...) __riscv_vfwmul_vf_f64m8(__VA_ARGS__) -// masked functions -#define vfwmul_vv_f32mf2_m(...) __riscv_vfwmul_vv_f32mf2_tumu(__VA_ARGS__) -#define vfwmul_vf_f32mf2_m(...) __riscv_vfwmul_vf_f32mf2_tumu(__VA_ARGS__) -#define vfwmul_vv_f32m1_m(...) __riscv_vfwmul_vv_f32m1_tumu(__VA_ARGS__) -#define vfwmul_vf_f32m1_m(...) __riscv_vfwmul_vf_f32m1_tumu(__VA_ARGS__) -#define vfwmul_vv_f32m2_m(...) __riscv_vfwmul_vv_f32m2_tumu(__VA_ARGS__) -#define vfwmul_vf_f32m2_m(...) __riscv_vfwmul_vf_f32m2_tumu(__VA_ARGS__) -#define vfwmul_vv_f32m4_m(...) __riscv_vfwmul_vv_f32m4_tumu(__VA_ARGS__) -#define vfwmul_vf_f32m4_m(...) __riscv_vfwmul_vf_f32m4_tumu(__VA_ARGS__) -#define vfwmul_vv_f32m8_m(...) __riscv_vfwmul_vv_f32m8_tumu(__VA_ARGS__) -#define vfwmul_vf_f32m8_m(...) __riscv_vfwmul_vf_f32m8_tumu(__VA_ARGS__) -#define vfwmul_vv_f64m1_m(...) __riscv_vfwmul_vv_f64m1_tumu(__VA_ARGS__) -#define vfwmul_vf_f64m1_m(...) __riscv_vfwmul_vf_f64m1_tumu(__VA_ARGS__) -#define vfwmul_vv_f64m2_m(...) __riscv_vfwmul_vv_f64m2_tumu(__VA_ARGS__) -#define vfwmul_vf_f64m2_m(...) __riscv_vfwmul_vf_f64m2_tumu(__VA_ARGS__) -#define vfwmul_vv_f64m4_m(...) __riscv_vfwmul_vv_f64m4_tumu(__VA_ARGS__) -#define vfwmul_vf_f64m4_m(...) __riscv_vfwmul_vf_f64m4_tumu(__VA_ARGS__) -#define vfwmul_vv_f64m8_m(...) __riscv_vfwmul_vv_f64m8_tumu(__VA_ARGS__) -#define vfwmul_vf_f64m8_m(...) __riscv_vfwmul_vf_f64m8_tumu(__VA_ARGS__) -#define vfmacc_vv_f16mf4(...) __riscv_vfmacc_vv_f16mf4_tu(__VA_ARGS__) -#define vfmacc_vf_f16mf4(...) __riscv_vfmacc_vf_f16mf4_tu(__VA_ARGS__) -#define vfmacc_vv_f16mf2(...) __riscv_vfmacc_vv_f16mf2_tu(__VA_ARGS__) -#define vfmacc_vf_f16mf2(...) __riscv_vfmacc_vf_f16mf2_tu(__VA_ARGS__) -#define vfmacc_vv_f16m1(...) __riscv_vfmacc_vv_f16m1_tu(__VA_ARGS__) -#define vfmacc_vf_f16m1(...) __riscv_vfmacc_vf_f16m1_tu(__VA_ARGS__) -#define vfmacc_vv_f16m2(...) __riscv_vfmacc_vv_f16m2_tu(__VA_ARGS__) -#define vfmacc_vf_f16m2(...) __riscv_vfmacc_vf_f16m2_tu(__VA_ARGS__) -#define vfmacc_vv_f16m4(...) __riscv_vfmacc_vv_f16m4_tu(__VA_ARGS__) -#define vfmacc_vf_f16m4(...) __riscv_vfmacc_vf_f16m4_tu(__VA_ARGS__) -#define vfmacc_vv_f16m8(...) __riscv_vfmacc_vv_f16m8_tu(__VA_ARGS__) -#define vfmacc_vf_f16m8(...) __riscv_vfmacc_vf_f16m8_tu(__VA_ARGS__) -#define vfmacc_vv_f32mf2(...) __riscv_vfmacc_vv_f32mf2_tu(__VA_ARGS__) -#define vfmacc_vf_f32mf2(...) __riscv_vfmacc_vf_f32mf2_tu(__VA_ARGS__) -#define vfmacc_vv_f32m1(...) __riscv_vfmacc_vv_f32m1_tu(__VA_ARGS__) -#define vfmacc_vf_f32m1(...) __riscv_vfmacc_vf_f32m1_tu(__VA_ARGS__) -#define vfmacc_vv_f32m2(...) __riscv_vfmacc_vv_f32m2_tu(__VA_ARGS__) -#define vfmacc_vf_f32m2(...) __riscv_vfmacc_vf_f32m2_tu(__VA_ARGS__) -#define vfmacc_vv_f32m4(...) __riscv_vfmacc_vv_f32m4_tu(__VA_ARGS__) -#define vfmacc_vf_f32m4(...) __riscv_vfmacc_vf_f32m4_tu(__VA_ARGS__) -#define vfmacc_vv_f32m8(...) __riscv_vfmacc_vv_f32m8_tu(__VA_ARGS__) -#define vfmacc_vf_f32m8(...) __riscv_vfmacc_vf_f32m8_tu(__VA_ARGS__) -#define vfmacc_vv_f64m1(...) __riscv_vfmacc_vv_f64m1_tu(__VA_ARGS__) -#define vfmacc_vf_f64m1(...) __riscv_vfmacc_vf_f64m1_tu(__VA_ARGS__) -#define vfmacc_vv_f64m2(...) __riscv_vfmacc_vv_f64m2_tu(__VA_ARGS__) -#define vfmacc_vf_f64m2(...) __riscv_vfmacc_vf_f64m2_tu(__VA_ARGS__) -#define vfmacc_vv_f64m4(...) __riscv_vfmacc_vv_f64m4_tu(__VA_ARGS__) -#define vfmacc_vf_f64m4(...) __riscv_vfmacc_vf_f64m4_tu(__VA_ARGS__) -#define vfmacc_vv_f64m8(...) __riscv_vfmacc_vv_f64m8_tu(__VA_ARGS__) -#define vfmacc_vf_f64m8(...) __riscv_vfmacc_vf_f64m8_tu(__VA_ARGS__) -#define vfnmacc_vv_f16mf4(...) __riscv_vfnmacc_vv_f16mf4_tu(__VA_ARGS__) -#define vfnmacc_vf_f16mf4(...) __riscv_vfnmacc_vf_f16mf4_tu(__VA_ARGS__) -#define vfnmacc_vv_f16mf2(...) __riscv_vfnmacc_vv_f16mf2_tu(__VA_ARGS__) -#define vfnmacc_vf_f16mf2(...) __riscv_vfnmacc_vf_f16mf2_tu(__VA_ARGS__) -#define vfnmacc_vv_f16m1(...) __riscv_vfnmacc_vv_f16m1_tu(__VA_ARGS__) -#define vfnmacc_vf_f16m1(...) __riscv_vfnmacc_vf_f16m1_tu(__VA_ARGS__) -#define vfnmacc_vv_f16m2(...) __riscv_vfnmacc_vv_f16m2_tu(__VA_ARGS__) -#define vfnmacc_vf_f16m2(...) __riscv_vfnmacc_vf_f16m2_tu(__VA_ARGS__) -#define vfnmacc_vv_f16m4(...) __riscv_vfnmacc_vv_f16m4_tu(__VA_ARGS__) -#define vfnmacc_vf_f16m4(...) __riscv_vfnmacc_vf_f16m4_tu(__VA_ARGS__) -#define vfnmacc_vv_f16m8(...) __riscv_vfnmacc_vv_f16m8_tu(__VA_ARGS__) -#define vfnmacc_vf_f16m8(...) __riscv_vfnmacc_vf_f16m8_tu(__VA_ARGS__) -#define vfnmacc_vv_f32mf2(...) __riscv_vfnmacc_vv_f32mf2_tu(__VA_ARGS__) -#define vfnmacc_vf_f32mf2(...) __riscv_vfnmacc_vf_f32mf2_tu(__VA_ARGS__) -#define vfnmacc_vv_f32m1(...) __riscv_vfnmacc_vv_f32m1_tu(__VA_ARGS__) -#define vfnmacc_vf_f32m1(...) __riscv_vfnmacc_vf_f32m1_tu(__VA_ARGS__) -#define vfnmacc_vv_f32m2(...) __riscv_vfnmacc_vv_f32m2_tu(__VA_ARGS__) -#define vfnmacc_vf_f32m2(...) __riscv_vfnmacc_vf_f32m2_tu(__VA_ARGS__) -#define vfnmacc_vv_f32m4(...) __riscv_vfnmacc_vv_f32m4_tu(__VA_ARGS__) -#define vfnmacc_vf_f32m4(...) __riscv_vfnmacc_vf_f32m4_tu(__VA_ARGS__) -#define vfnmacc_vv_f32m8(...) __riscv_vfnmacc_vv_f32m8_tu(__VA_ARGS__) -#define vfnmacc_vf_f32m8(...) __riscv_vfnmacc_vf_f32m8_tu(__VA_ARGS__) -#define vfnmacc_vv_f64m1(...) __riscv_vfnmacc_vv_f64m1_tu(__VA_ARGS__) -#define vfnmacc_vf_f64m1(...) __riscv_vfnmacc_vf_f64m1_tu(__VA_ARGS__) -#define vfnmacc_vv_f64m2(...) __riscv_vfnmacc_vv_f64m2_tu(__VA_ARGS__) -#define vfnmacc_vf_f64m2(...) __riscv_vfnmacc_vf_f64m2_tu(__VA_ARGS__) -#define vfnmacc_vv_f64m4(...) __riscv_vfnmacc_vv_f64m4_tu(__VA_ARGS__) -#define vfnmacc_vf_f64m4(...) __riscv_vfnmacc_vf_f64m4_tu(__VA_ARGS__) -#define vfnmacc_vv_f64m8(...) __riscv_vfnmacc_vv_f64m8_tu(__VA_ARGS__) -#define vfnmacc_vf_f64m8(...) __riscv_vfnmacc_vf_f64m8_tu(__VA_ARGS__) -#define vfmsac_vv_f16mf4(...) __riscv_vfmsac_vv_f16mf4_tu(__VA_ARGS__) -#define vfmsac_vf_f16mf4(...) __riscv_vfmsac_vf_f16mf4_tu(__VA_ARGS__) -#define vfmsac_vv_f16mf2(...) __riscv_vfmsac_vv_f16mf2_tu(__VA_ARGS__) -#define vfmsac_vf_f16mf2(...) __riscv_vfmsac_vf_f16mf2_tu(__VA_ARGS__) -#define vfmsac_vv_f16m1(...) __riscv_vfmsac_vv_f16m1_tu(__VA_ARGS__) -#define vfmsac_vf_f16m1(...) __riscv_vfmsac_vf_f16m1_tu(__VA_ARGS__) -#define vfmsac_vv_f16m2(...) __riscv_vfmsac_vv_f16m2_tu(__VA_ARGS__) -#define vfmsac_vf_f16m2(...) __riscv_vfmsac_vf_f16m2_tu(__VA_ARGS__) -#define vfmsac_vv_f16m4(...) __riscv_vfmsac_vv_f16m4_tu(__VA_ARGS__) -#define vfmsac_vf_f16m4(...) __riscv_vfmsac_vf_f16m4_tu(__VA_ARGS__) -#define vfmsac_vv_f16m8(...) __riscv_vfmsac_vv_f16m8_tu(__VA_ARGS__) -#define vfmsac_vf_f16m8(...) __riscv_vfmsac_vf_f16m8_tu(__VA_ARGS__) -#define vfmsac_vv_f32mf2(...) __riscv_vfmsac_vv_f32mf2_tu(__VA_ARGS__) -#define vfmsac_vf_f32mf2(...) __riscv_vfmsac_vf_f32mf2_tu(__VA_ARGS__) -#define vfmsac_vv_f32m1(...) __riscv_vfmsac_vv_f32m1_tu(__VA_ARGS__) -#define vfmsac_vf_f32m1(...) __riscv_vfmsac_vf_f32m1_tu(__VA_ARGS__) -#define vfmsac_vv_f32m2(...) __riscv_vfmsac_vv_f32m2_tu(__VA_ARGS__) -#define vfmsac_vf_f32m2(...) __riscv_vfmsac_vf_f32m2_tu(__VA_ARGS__) -#define vfmsac_vv_f32m4(...) __riscv_vfmsac_vv_f32m4_tu(__VA_ARGS__) -#define vfmsac_vf_f32m4(...) __riscv_vfmsac_vf_f32m4_tu(__VA_ARGS__) -#define vfmsac_vv_f32m8(...) __riscv_vfmsac_vv_f32m8_tu(__VA_ARGS__) -#define vfmsac_vf_f32m8(...) __riscv_vfmsac_vf_f32m8_tu(__VA_ARGS__) -#define vfmsac_vv_f64m1(...) __riscv_vfmsac_vv_f64m1_tu(__VA_ARGS__) -#define vfmsac_vf_f64m1(...) __riscv_vfmsac_vf_f64m1_tu(__VA_ARGS__) -#define vfmsac_vv_f64m2(...) __riscv_vfmsac_vv_f64m2_tu(__VA_ARGS__) -#define vfmsac_vf_f64m2(...) __riscv_vfmsac_vf_f64m2_tu(__VA_ARGS__) -#define vfmsac_vv_f64m4(...) __riscv_vfmsac_vv_f64m4_tu(__VA_ARGS__) -#define vfmsac_vf_f64m4(...) __riscv_vfmsac_vf_f64m4_tu(__VA_ARGS__) -#define vfmsac_vv_f64m8(...) __riscv_vfmsac_vv_f64m8_tu(__VA_ARGS__) -#define vfmsac_vf_f64m8(...) __riscv_vfmsac_vf_f64m8_tu(__VA_ARGS__) -#define vfnmsac_vv_f16mf4(...) __riscv_vfnmsac_vv_f16mf4_tu(__VA_ARGS__) -#define vfnmsac_vf_f16mf4(...) __riscv_vfnmsac_vf_f16mf4_tu(__VA_ARGS__) -#define vfnmsac_vv_f16mf2(...) __riscv_vfnmsac_vv_f16mf2_tu(__VA_ARGS__) -#define vfnmsac_vf_f16mf2(...) __riscv_vfnmsac_vf_f16mf2_tu(__VA_ARGS__) -#define vfnmsac_vv_f16m1(...) __riscv_vfnmsac_vv_f16m1_tu(__VA_ARGS__) -#define vfnmsac_vf_f16m1(...) __riscv_vfnmsac_vf_f16m1_tu(__VA_ARGS__) -#define vfnmsac_vv_f16m2(...) __riscv_vfnmsac_vv_f16m2_tu(__VA_ARGS__) -#define vfnmsac_vf_f16m2(...) __riscv_vfnmsac_vf_f16m2_tu(__VA_ARGS__) -#define vfnmsac_vv_f16m4(...) __riscv_vfnmsac_vv_f16m4_tu(__VA_ARGS__) -#define vfnmsac_vf_f16m4(...) __riscv_vfnmsac_vf_f16m4_tu(__VA_ARGS__) -#define vfnmsac_vv_f16m8(...) __riscv_vfnmsac_vv_f16m8_tu(__VA_ARGS__) -#define vfnmsac_vf_f16m8(...) __riscv_vfnmsac_vf_f16m8_tu(__VA_ARGS__) -#define vfnmsac_vv_f32mf2(...) __riscv_vfnmsac_vv_f32mf2_tu(__VA_ARGS__) -#define vfnmsac_vf_f32mf2(...) __riscv_vfnmsac_vf_f32mf2_tu(__VA_ARGS__) -#define vfnmsac_vv_f32m1(...) __riscv_vfnmsac_vv_f32m1_tu(__VA_ARGS__) -#define vfnmsac_vf_f32m1(...) __riscv_vfnmsac_vf_f32m1_tu(__VA_ARGS__) -#define vfnmsac_vv_f32m2(...) __riscv_vfnmsac_vv_f32m2_tu(__VA_ARGS__) -#define vfnmsac_vf_f32m2(...) __riscv_vfnmsac_vf_f32m2_tu(__VA_ARGS__) -#define vfnmsac_vv_f32m4(...) __riscv_vfnmsac_vv_f32m4_tu(__VA_ARGS__) -#define vfnmsac_vf_f32m4(...) __riscv_vfnmsac_vf_f32m4_tu(__VA_ARGS__) -#define vfnmsac_vv_f32m8(...) __riscv_vfnmsac_vv_f32m8_tu(__VA_ARGS__) -#define vfnmsac_vf_f32m8(...) __riscv_vfnmsac_vf_f32m8_tu(__VA_ARGS__) -#define vfnmsac_vv_f64m1(...) __riscv_vfnmsac_vv_f64m1_tu(__VA_ARGS__) -#define vfnmsac_vf_f64m1(...) __riscv_vfnmsac_vf_f64m1_tu(__VA_ARGS__) -#define vfnmsac_vv_f64m2(...) __riscv_vfnmsac_vv_f64m2_tu(__VA_ARGS__) -#define vfnmsac_vf_f64m2(...) __riscv_vfnmsac_vf_f64m2_tu(__VA_ARGS__) -#define vfnmsac_vv_f64m4(...) __riscv_vfnmsac_vv_f64m4_tu(__VA_ARGS__) -#define vfnmsac_vf_f64m4(...) __riscv_vfnmsac_vf_f64m4_tu(__VA_ARGS__) -#define vfnmsac_vv_f64m8(...) __riscv_vfnmsac_vv_f64m8_tu(__VA_ARGS__) -#define vfnmsac_vf_f64m8(...) __riscv_vfnmsac_vf_f64m8_tu(__VA_ARGS__) -#define vfmadd_vv_f16mf4(...) __riscv_vfmadd_vv_f16mf4_tu(__VA_ARGS__) -#define vfmadd_vf_f16mf4(...) __riscv_vfmadd_vf_f16mf4_tu(__VA_ARGS__) -#define vfmadd_vv_f16mf2(...) __riscv_vfmadd_vv_f16mf2_tu(__VA_ARGS__) -#define vfmadd_vf_f16mf2(...) __riscv_vfmadd_vf_f16mf2_tu(__VA_ARGS__) -#define vfmadd_vv_f16m1(...) __riscv_vfmadd_vv_f16m1_tu(__VA_ARGS__) -#define vfmadd_vf_f16m1(...) __riscv_vfmadd_vf_f16m1_tu(__VA_ARGS__) -#define vfmadd_vv_f16m2(...) __riscv_vfmadd_vv_f16m2_tu(__VA_ARGS__) -#define vfmadd_vf_f16m2(...) __riscv_vfmadd_vf_f16m2_tu(__VA_ARGS__) -#define vfmadd_vv_f16m4(...) __riscv_vfmadd_vv_f16m4_tu(__VA_ARGS__) -#define vfmadd_vf_f16m4(...) __riscv_vfmadd_vf_f16m4_tu(__VA_ARGS__) -#define vfmadd_vv_f16m8(...) __riscv_vfmadd_vv_f16m8_tu(__VA_ARGS__) -#define vfmadd_vf_f16m8(...) __riscv_vfmadd_vf_f16m8_tu(__VA_ARGS__) -#define vfmadd_vv_f32mf2(...) __riscv_vfmadd_vv_f32mf2_tu(__VA_ARGS__) -#define vfmadd_vf_f32mf2(...) __riscv_vfmadd_vf_f32mf2_tu(__VA_ARGS__) -#define vfmadd_vv_f32m1(...) __riscv_vfmadd_vv_f32m1_tu(__VA_ARGS__) -#define vfmadd_vf_f32m1(...) __riscv_vfmadd_vf_f32m1_tu(__VA_ARGS__) -#define vfmadd_vv_f32m2(...) __riscv_vfmadd_vv_f32m2_tu(__VA_ARGS__) -#define vfmadd_vf_f32m2(...) __riscv_vfmadd_vf_f32m2_tu(__VA_ARGS__) -#define vfmadd_vv_f32m4(...) __riscv_vfmadd_vv_f32m4_tu(__VA_ARGS__) -#define vfmadd_vf_f32m4(...) __riscv_vfmadd_vf_f32m4_tu(__VA_ARGS__) -#define vfmadd_vv_f32m8(...) __riscv_vfmadd_vv_f32m8_tu(__VA_ARGS__) -#define vfmadd_vf_f32m8(...) __riscv_vfmadd_vf_f32m8_tu(__VA_ARGS__) -#define vfmadd_vv_f64m1(...) __riscv_vfmadd_vv_f64m1_tu(__VA_ARGS__) -#define vfmadd_vf_f64m1(...) __riscv_vfmadd_vf_f64m1_tu(__VA_ARGS__) -#define vfmadd_vv_f64m2(...) __riscv_vfmadd_vv_f64m2_tu(__VA_ARGS__) -#define vfmadd_vf_f64m2(...) __riscv_vfmadd_vf_f64m2_tu(__VA_ARGS__) -#define vfmadd_vv_f64m4(...) __riscv_vfmadd_vv_f64m4_tu(__VA_ARGS__) -#define vfmadd_vf_f64m4(...) __riscv_vfmadd_vf_f64m4_tu(__VA_ARGS__) -#define vfmadd_vv_f64m8(...) __riscv_vfmadd_vv_f64m8_tu(__VA_ARGS__) -#define vfmadd_vf_f64m8(...) __riscv_vfmadd_vf_f64m8_tu(__VA_ARGS__) -#define vfnmadd_vv_f16mf4(...) __riscv_vfnmadd_vv_f16mf4_tu(__VA_ARGS__) -#define vfnmadd_vf_f16mf4(...) __riscv_vfnmadd_vf_f16mf4_tu(__VA_ARGS__) -#define vfnmadd_vv_f16mf2(...) __riscv_vfnmadd_vv_f16mf2_tu(__VA_ARGS__) -#define vfnmadd_vf_f16mf2(...) __riscv_vfnmadd_vf_f16mf2_tu(__VA_ARGS__) -#define vfnmadd_vv_f16m1(...) __riscv_vfnmadd_vv_f16m1_tu(__VA_ARGS__) -#define vfnmadd_vf_f16m1(...) __riscv_vfnmadd_vf_f16m1_tu(__VA_ARGS__) -#define vfnmadd_vv_f16m2(...) __riscv_vfnmadd_vv_f16m2_tu(__VA_ARGS__) -#define vfnmadd_vf_f16m2(...) __riscv_vfnmadd_vf_f16m2_tu(__VA_ARGS__) -#define vfnmadd_vv_f16m4(...) __riscv_vfnmadd_vv_f16m4_tu(__VA_ARGS__) -#define vfnmadd_vf_f16m4(...) __riscv_vfnmadd_vf_f16m4_tu(__VA_ARGS__) -#define vfnmadd_vv_f16m8(...) __riscv_vfnmadd_vv_f16m8_tu(__VA_ARGS__) -#define vfnmadd_vf_f16m8(...) __riscv_vfnmadd_vf_f16m8_tu(__VA_ARGS__) -#define vfnmadd_vv_f32mf2(...) __riscv_vfnmadd_vv_f32mf2_tu(__VA_ARGS__) -#define vfnmadd_vf_f32mf2(...) __riscv_vfnmadd_vf_f32mf2_tu(__VA_ARGS__) -#define vfnmadd_vv_f32m1(...) __riscv_vfnmadd_vv_f32m1_tu(__VA_ARGS__) -#define vfnmadd_vf_f32m1(...) __riscv_vfnmadd_vf_f32m1_tu(__VA_ARGS__) -#define vfnmadd_vv_f32m2(...) __riscv_vfnmadd_vv_f32m2_tu(__VA_ARGS__) -#define vfnmadd_vf_f32m2(...) __riscv_vfnmadd_vf_f32m2_tu(__VA_ARGS__) -#define vfnmadd_vv_f32m4(...) __riscv_vfnmadd_vv_f32m4_tu(__VA_ARGS__) -#define vfnmadd_vf_f32m4(...) __riscv_vfnmadd_vf_f32m4_tu(__VA_ARGS__) -#define vfnmadd_vv_f32m8(...) __riscv_vfnmadd_vv_f32m8_tu(__VA_ARGS__) -#define vfnmadd_vf_f32m8(...) __riscv_vfnmadd_vf_f32m8_tu(__VA_ARGS__) -#define vfnmadd_vv_f64m1(...) __riscv_vfnmadd_vv_f64m1_tu(__VA_ARGS__) -#define vfnmadd_vf_f64m1(...) __riscv_vfnmadd_vf_f64m1_tu(__VA_ARGS__) -#define vfnmadd_vv_f64m2(...) __riscv_vfnmadd_vv_f64m2_tu(__VA_ARGS__) -#define vfnmadd_vf_f64m2(...) __riscv_vfnmadd_vf_f64m2_tu(__VA_ARGS__) -#define vfnmadd_vv_f64m4(...) __riscv_vfnmadd_vv_f64m4_tu(__VA_ARGS__) -#define vfnmadd_vf_f64m4(...) __riscv_vfnmadd_vf_f64m4_tu(__VA_ARGS__) -#define vfnmadd_vv_f64m8(...) __riscv_vfnmadd_vv_f64m8_tu(__VA_ARGS__) -#define vfnmadd_vf_f64m8(...) __riscv_vfnmadd_vf_f64m8_tu(__VA_ARGS__) -#define vfmsub_vv_f16mf4(...) __riscv_vfmsub_vv_f16mf4_tu(__VA_ARGS__) -#define vfmsub_vf_f16mf4(...) __riscv_vfmsub_vf_f16mf4_tu(__VA_ARGS__) -#define vfmsub_vv_f16mf2(...) __riscv_vfmsub_vv_f16mf2_tu(__VA_ARGS__) -#define vfmsub_vf_f16mf2(...) __riscv_vfmsub_vf_f16mf2_tu(__VA_ARGS__) -#define vfmsub_vv_f16m1(...) __riscv_vfmsub_vv_f16m1_tu(__VA_ARGS__) -#define vfmsub_vf_f16m1(...) __riscv_vfmsub_vf_f16m1_tu(__VA_ARGS__) -#define vfmsub_vv_f16m2(...) __riscv_vfmsub_vv_f16m2_tu(__VA_ARGS__) -#define vfmsub_vf_f16m2(...) __riscv_vfmsub_vf_f16m2_tu(__VA_ARGS__) -#define vfmsub_vv_f16m4(...) __riscv_vfmsub_vv_f16m4_tu(__VA_ARGS__) -#define vfmsub_vf_f16m4(...) __riscv_vfmsub_vf_f16m4_tu(__VA_ARGS__) -#define vfmsub_vv_f16m8(...) __riscv_vfmsub_vv_f16m8_tu(__VA_ARGS__) -#define vfmsub_vf_f16m8(...) __riscv_vfmsub_vf_f16m8_tu(__VA_ARGS__) -#define vfmsub_vv_f32mf2(...) __riscv_vfmsub_vv_f32mf2_tu(__VA_ARGS__) -#define vfmsub_vf_f32mf2(...) __riscv_vfmsub_vf_f32mf2_tu(__VA_ARGS__) -#define vfmsub_vv_f32m1(...) __riscv_vfmsub_vv_f32m1_tu(__VA_ARGS__) -#define vfmsub_vf_f32m1(...) __riscv_vfmsub_vf_f32m1_tu(__VA_ARGS__) -#define vfmsub_vv_f32m2(...) __riscv_vfmsub_vv_f32m2_tu(__VA_ARGS__) -#define vfmsub_vf_f32m2(...) __riscv_vfmsub_vf_f32m2_tu(__VA_ARGS__) -#define vfmsub_vv_f32m4(...) __riscv_vfmsub_vv_f32m4_tu(__VA_ARGS__) -#define vfmsub_vf_f32m4(...) __riscv_vfmsub_vf_f32m4_tu(__VA_ARGS__) -#define vfmsub_vv_f32m8(...) __riscv_vfmsub_vv_f32m8_tu(__VA_ARGS__) -#define vfmsub_vf_f32m8(...) __riscv_vfmsub_vf_f32m8_tu(__VA_ARGS__) -#define vfmsub_vv_f64m1(...) __riscv_vfmsub_vv_f64m1_tu(__VA_ARGS__) -#define vfmsub_vf_f64m1(...) __riscv_vfmsub_vf_f64m1_tu(__VA_ARGS__) -#define vfmsub_vv_f64m2(...) __riscv_vfmsub_vv_f64m2_tu(__VA_ARGS__) -#define vfmsub_vf_f64m2(...) __riscv_vfmsub_vf_f64m2_tu(__VA_ARGS__) -#define vfmsub_vv_f64m4(...) __riscv_vfmsub_vv_f64m4_tu(__VA_ARGS__) -#define vfmsub_vf_f64m4(...) __riscv_vfmsub_vf_f64m4_tu(__VA_ARGS__) -#define vfmsub_vv_f64m8(...) __riscv_vfmsub_vv_f64m8_tu(__VA_ARGS__) -#define vfmsub_vf_f64m8(...) __riscv_vfmsub_vf_f64m8_tu(__VA_ARGS__) -#define vfnmsub_vv_f16mf4(...) __riscv_vfnmsub_vv_f16mf4_tu(__VA_ARGS__) -#define vfnmsub_vf_f16mf4(...) __riscv_vfnmsub_vf_f16mf4_tu(__VA_ARGS__) -#define vfnmsub_vv_f16mf2(...) __riscv_vfnmsub_vv_f16mf2_tu(__VA_ARGS__) -#define vfnmsub_vf_f16mf2(...) __riscv_vfnmsub_vf_f16mf2_tu(__VA_ARGS__) -#define vfnmsub_vv_f16m1(...) __riscv_vfnmsub_vv_f16m1_tu(__VA_ARGS__) -#define vfnmsub_vf_f16m1(...) __riscv_vfnmsub_vf_f16m1_tu(__VA_ARGS__) -#define vfnmsub_vv_f16m2(...) __riscv_vfnmsub_vv_f16m2_tu(__VA_ARGS__) -#define vfnmsub_vf_f16m2(...) __riscv_vfnmsub_vf_f16m2_tu(__VA_ARGS__) -#define vfnmsub_vv_f16m4(...) __riscv_vfnmsub_vv_f16m4_tu(__VA_ARGS__) -#define vfnmsub_vf_f16m4(...) __riscv_vfnmsub_vf_f16m4_tu(__VA_ARGS__) -#define vfnmsub_vv_f16m8(...) __riscv_vfnmsub_vv_f16m8_tu(__VA_ARGS__) -#define vfnmsub_vf_f16m8(...) __riscv_vfnmsub_vf_f16m8_tu(__VA_ARGS__) -#define vfnmsub_vv_f32mf2(...) __riscv_vfnmsub_vv_f32mf2_tu(__VA_ARGS__) -#define vfnmsub_vf_f32mf2(...) __riscv_vfnmsub_vf_f32mf2_tu(__VA_ARGS__) -#define vfnmsub_vv_f32m1(...) __riscv_vfnmsub_vv_f32m1_tu(__VA_ARGS__) -#define vfnmsub_vf_f32m1(...) __riscv_vfnmsub_vf_f32m1_tu(__VA_ARGS__) -#define vfnmsub_vv_f32m2(...) __riscv_vfnmsub_vv_f32m2_tu(__VA_ARGS__) -#define vfnmsub_vf_f32m2(...) __riscv_vfnmsub_vf_f32m2_tu(__VA_ARGS__) -#define vfnmsub_vv_f32m4(...) __riscv_vfnmsub_vv_f32m4_tu(__VA_ARGS__) -#define vfnmsub_vf_f32m4(...) __riscv_vfnmsub_vf_f32m4_tu(__VA_ARGS__) -#define vfnmsub_vv_f32m8(...) __riscv_vfnmsub_vv_f32m8_tu(__VA_ARGS__) -#define vfnmsub_vf_f32m8(...) __riscv_vfnmsub_vf_f32m8_tu(__VA_ARGS__) -#define vfnmsub_vv_f64m1(...) __riscv_vfnmsub_vv_f64m1_tu(__VA_ARGS__) -#define vfnmsub_vf_f64m1(...) __riscv_vfnmsub_vf_f64m1_tu(__VA_ARGS__) -#define vfnmsub_vv_f64m2(...) __riscv_vfnmsub_vv_f64m2_tu(__VA_ARGS__) -#define vfnmsub_vf_f64m2(...) __riscv_vfnmsub_vf_f64m2_tu(__VA_ARGS__) -#define vfnmsub_vv_f64m4(...) __riscv_vfnmsub_vv_f64m4_tu(__VA_ARGS__) -#define vfnmsub_vf_f64m4(...) __riscv_vfnmsub_vf_f64m4_tu(__VA_ARGS__) -#define vfnmsub_vv_f64m8(...) __riscv_vfnmsub_vv_f64m8_tu(__VA_ARGS__) -#define vfnmsub_vf_f64m8(...) __riscv_vfnmsub_vf_f64m8_tu(__VA_ARGS__) -// masked functions -#define vfmacc_vv_f16mf4_m(...) __riscv_vfmacc_vv_f16mf4_tumu(__VA_ARGS__) -#define vfmacc_vf_f16mf4_m(...) __riscv_vfmacc_vf_f16mf4_tumu(__VA_ARGS__) -#define vfmacc_vv_f16mf2_m(...) __riscv_vfmacc_vv_f16mf2_tumu(__VA_ARGS__) -#define vfmacc_vf_f16mf2_m(...) __riscv_vfmacc_vf_f16mf2_tumu(__VA_ARGS__) -#define vfmacc_vv_f16m1_m(...) __riscv_vfmacc_vv_f16m1_tumu(__VA_ARGS__) -#define vfmacc_vf_f16m1_m(...) __riscv_vfmacc_vf_f16m1_tumu(__VA_ARGS__) -#define vfmacc_vv_f16m2_m(...) __riscv_vfmacc_vv_f16m2_tumu(__VA_ARGS__) -#define vfmacc_vf_f16m2_m(...) __riscv_vfmacc_vf_f16m2_tumu(__VA_ARGS__) -#define vfmacc_vv_f16m4_m(...) __riscv_vfmacc_vv_f16m4_tumu(__VA_ARGS__) -#define vfmacc_vf_f16m4_m(...) __riscv_vfmacc_vf_f16m4_tumu(__VA_ARGS__) -#define vfmacc_vv_f16m8_m(...) __riscv_vfmacc_vv_f16m8_tumu(__VA_ARGS__) -#define vfmacc_vf_f16m8_m(...) __riscv_vfmacc_vf_f16m8_tumu(__VA_ARGS__) -#define vfmacc_vv_f32mf2_m(...) __riscv_vfmacc_vv_f32mf2_tumu(__VA_ARGS__) -#define vfmacc_vf_f32mf2_m(...) __riscv_vfmacc_vf_f32mf2_tumu(__VA_ARGS__) -#define vfmacc_vv_f32m1_m(...) __riscv_vfmacc_vv_f32m1_tumu(__VA_ARGS__) -#define vfmacc_vf_f32m1_m(...) __riscv_vfmacc_vf_f32m1_tumu(__VA_ARGS__) -#define vfmacc_vv_f32m2_m(...) __riscv_vfmacc_vv_f32m2_tumu(__VA_ARGS__) -#define vfmacc_vf_f32m2_m(...) __riscv_vfmacc_vf_f32m2_tumu(__VA_ARGS__) -#define vfmacc_vv_f32m4_m(...) __riscv_vfmacc_vv_f32m4_tumu(__VA_ARGS__) -#define vfmacc_vf_f32m4_m(...) __riscv_vfmacc_vf_f32m4_tumu(__VA_ARGS__) -#define vfmacc_vv_f32m8_m(...) __riscv_vfmacc_vv_f32m8_tumu(__VA_ARGS__) -#define vfmacc_vf_f32m8_m(...) __riscv_vfmacc_vf_f32m8_tumu(__VA_ARGS__) -#define vfmacc_vv_f64m1_m(...) __riscv_vfmacc_vv_f64m1_tumu(__VA_ARGS__) -#define vfmacc_vf_f64m1_m(...) __riscv_vfmacc_vf_f64m1_tumu(__VA_ARGS__) -#define vfmacc_vv_f64m2_m(...) __riscv_vfmacc_vv_f64m2_tumu(__VA_ARGS__) -#define vfmacc_vf_f64m2_m(...) __riscv_vfmacc_vf_f64m2_tumu(__VA_ARGS__) -#define vfmacc_vv_f64m4_m(...) __riscv_vfmacc_vv_f64m4_tumu(__VA_ARGS__) -#define vfmacc_vf_f64m4_m(...) __riscv_vfmacc_vf_f64m4_tumu(__VA_ARGS__) -#define vfmacc_vv_f64m8_m(...) __riscv_vfmacc_vv_f64m8_tumu(__VA_ARGS__) -#define vfmacc_vf_f64m8_m(...) __riscv_vfmacc_vf_f64m8_tumu(__VA_ARGS__) -#define vfnmacc_vv_f16mf4_m(...) __riscv_vfnmacc_vv_f16mf4_tumu(__VA_ARGS__) -#define vfnmacc_vf_f16mf4_m(...) __riscv_vfnmacc_vf_f16mf4_tumu(__VA_ARGS__) -#define vfnmacc_vv_f16mf2_m(...) __riscv_vfnmacc_vv_f16mf2_tumu(__VA_ARGS__) -#define vfnmacc_vf_f16mf2_m(...) __riscv_vfnmacc_vf_f16mf2_tumu(__VA_ARGS__) -#define vfnmacc_vv_f16m1_m(...) __riscv_vfnmacc_vv_f16m1_tumu(__VA_ARGS__) -#define vfnmacc_vf_f16m1_m(...) __riscv_vfnmacc_vf_f16m1_tumu(__VA_ARGS__) -#define vfnmacc_vv_f16m2_m(...) __riscv_vfnmacc_vv_f16m2_tumu(__VA_ARGS__) -#define vfnmacc_vf_f16m2_m(...) __riscv_vfnmacc_vf_f16m2_tumu(__VA_ARGS__) -#define vfnmacc_vv_f16m4_m(...) __riscv_vfnmacc_vv_f16m4_tumu(__VA_ARGS__) -#define vfnmacc_vf_f16m4_m(...) __riscv_vfnmacc_vf_f16m4_tumu(__VA_ARGS__) -#define vfnmacc_vv_f16m8_m(...) __riscv_vfnmacc_vv_f16m8_tumu(__VA_ARGS__) -#define vfnmacc_vf_f16m8_m(...) __riscv_vfnmacc_vf_f16m8_tumu(__VA_ARGS__) -#define vfnmacc_vv_f32mf2_m(...) __riscv_vfnmacc_vv_f32mf2_tumu(__VA_ARGS__) -#define vfnmacc_vf_f32mf2_m(...) __riscv_vfnmacc_vf_f32mf2_tumu(__VA_ARGS__) -#define vfnmacc_vv_f32m1_m(...) __riscv_vfnmacc_vv_f32m1_tumu(__VA_ARGS__) -#define vfnmacc_vf_f32m1_m(...) __riscv_vfnmacc_vf_f32m1_tumu(__VA_ARGS__) -#define vfnmacc_vv_f32m2_m(...) __riscv_vfnmacc_vv_f32m2_tumu(__VA_ARGS__) -#define vfnmacc_vf_f32m2_m(...) __riscv_vfnmacc_vf_f32m2_tumu(__VA_ARGS__) -#define vfnmacc_vv_f32m4_m(...) __riscv_vfnmacc_vv_f32m4_tumu(__VA_ARGS__) -#define vfnmacc_vf_f32m4_m(...) __riscv_vfnmacc_vf_f32m4_tumu(__VA_ARGS__) -#define vfnmacc_vv_f32m8_m(...) __riscv_vfnmacc_vv_f32m8_tumu(__VA_ARGS__) -#define vfnmacc_vf_f32m8_m(...) __riscv_vfnmacc_vf_f32m8_tumu(__VA_ARGS__) -#define vfnmacc_vv_f64m1_m(...) __riscv_vfnmacc_vv_f64m1_tumu(__VA_ARGS__) -#define vfnmacc_vf_f64m1_m(...) __riscv_vfnmacc_vf_f64m1_tumu(__VA_ARGS__) -#define vfnmacc_vv_f64m2_m(...) __riscv_vfnmacc_vv_f64m2_tumu(__VA_ARGS__) -#define vfnmacc_vf_f64m2_m(...) __riscv_vfnmacc_vf_f64m2_tumu(__VA_ARGS__) -#define vfnmacc_vv_f64m4_m(...) __riscv_vfnmacc_vv_f64m4_tumu(__VA_ARGS__) -#define vfnmacc_vf_f64m4_m(...) __riscv_vfnmacc_vf_f64m4_tumu(__VA_ARGS__) -#define vfnmacc_vv_f64m8_m(...) __riscv_vfnmacc_vv_f64m8_tumu(__VA_ARGS__) -#define vfnmacc_vf_f64m8_m(...) __riscv_vfnmacc_vf_f64m8_tumu(__VA_ARGS__) -#define vfmsac_vv_f16mf4_m(...) __riscv_vfmsac_vv_f16mf4_tumu(__VA_ARGS__) -#define vfmsac_vf_f16mf4_m(...) __riscv_vfmsac_vf_f16mf4_tumu(__VA_ARGS__) -#define vfmsac_vv_f16mf2_m(...) __riscv_vfmsac_vv_f16mf2_tumu(__VA_ARGS__) -#define vfmsac_vf_f16mf2_m(...) __riscv_vfmsac_vf_f16mf2_tumu(__VA_ARGS__) -#define vfmsac_vv_f16m1_m(...) __riscv_vfmsac_vv_f16m1_tumu(__VA_ARGS__) -#define vfmsac_vf_f16m1_m(...) __riscv_vfmsac_vf_f16m1_tumu(__VA_ARGS__) -#define vfmsac_vv_f16m2_m(...) __riscv_vfmsac_vv_f16m2_tumu(__VA_ARGS__) -#define vfmsac_vf_f16m2_m(...) __riscv_vfmsac_vf_f16m2_tumu(__VA_ARGS__) -#define vfmsac_vv_f16m4_m(...) __riscv_vfmsac_vv_f16m4_tumu(__VA_ARGS__) -#define vfmsac_vf_f16m4_m(...) __riscv_vfmsac_vf_f16m4_tumu(__VA_ARGS__) -#define vfmsac_vv_f16m8_m(...) __riscv_vfmsac_vv_f16m8_tumu(__VA_ARGS__) -#define vfmsac_vf_f16m8_m(...) __riscv_vfmsac_vf_f16m8_tumu(__VA_ARGS__) -#define vfmsac_vv_f32mf2_m(...) __riscv_vfmsac_vv_f32mf2_tumu(__VA_ARGS__) -#define vfmsac_vf_f32mf2_m(...) __riscv_vfmsac_vf_f32mf2_tumu(__VA_ARGS__) -#define vfmsac_vv_f32m1_m(...) __riscv_vfmsac_vv_f32m1_tumu(__VA_ARGS__) -#define vfmsac_vf_f32m1_m(...) __riscv_vfmsac_vf_f32m1_tumu(__VA_ARGS__) -#define vfmsac_vv_f32m2_m(...) __riscv_vfmsac_vv_f32m2_tumu(__VA_ARGS__) -#define vfmsac_vf_f32m2_m(...) __riscv_vfmsac_vf_f32m2_tumu(__VA_ARGS__) -#define vfmsac_vv_f32m4_m(...) __riscv_vfmsac_vv_f32m4_tumu(__VA_ARGS__) -#define vfmsac_vf_f32m4_m(...) __riscv_vfmsac_vf_f32m4_tumu(__VA_ARGS__) -#define vfmsac_vv_f32m8_m(...) __riscv_vfmsac_vv_f32m8_tumu(__VA_ARGS__) -#define vfmsac_vf_f32m8_m(...) __riscv_vfmsac_vf_f32m8_tumu(__VA_ARGS__) -#define vfmsac_vv_f64m1_m(...) __riscv_vfmsac_vv_f64m1_tumu(__VA_ARGS__) -#define vfmsac_vf_f64m1_m(...) __riscv_vfmsac_vf_f64m1_tumu(__VA_ARGS__) -#define vfmsac_vv_f64m2_m(...) __riscv_vfmsac_vv_f64m2_tumu(__VA_ARGS__) -#define vfmsac_vf_f64m2_m(...) __riscv_vfmsac_vf_f64m2_tumu(__VA_ARGS__) -#define vfmsac_vv_f64m4_m(...) __riscv_vfmsac_vv_f64m4_tumu(__VA_ARGS__) -#define vfmsac_vf_f64m4_m(...) __riscv_vfmsac_vf_f64m4_tumu(__VA_ARGS__) -#define vfmsac_vv_f64m8_m(...) __riscv_vfmsac_vv_f64m8_tumu(__VA_ARGS__) -#define vfmsac_vf_f64m8_m(...) __riscv_vfmsac_vf_f64m8_tumu(__VA_ARGS__) -#define vfnmsac_vv_f16mf4_m(...) __riscv_vfnmsac_vv_f16mf4_tumu(__VA_ARGS__) -#define vfnmsac_vf_f16mf4_m(...) __riscv_vfnmsac_vf_f16mf4_tumu(__VA_ARGS__) -#define vfnmsac_vv_f16mf2_m(...) __riscv_vfnmsac_vv_f16mf2_tumu(__VA_ARGS__) -#define vfnmsac_vf_f16mf2_m(...) __riscv_vfnmsac_vf_f16mf2_tumu(__VA_ARGS__) -#define vfnmsac_vv_f16m1_m(...) __riscv_vfnmsac_vv_f16m1_tumu(__VA_ARGS__) -#define vfnmsac_vf_f16m1_m(...) __riscv_vfnmsac_vf_f16m1_tumu(__VA_ARGS__) -#define vfnmsac_vv_f16m2_m(...) __riscv_vfnmsac_vv_f16m2_tumu(__VA_ARGS__) -#define vfnmsac_vf_f16m2_m(...) __riscv_vfnmsac_vf_f16m2_tumu(__VA_ARGS__) -#define vfnmsac_vv_f16m4_m(...) __riscv_vfnmsac_vv_f16m4_tumu(__VA_ARGS__) -#define vfnmsac_vf_f16m4_m(...) __riscv_vfnmsac_vf_f16m4_tumu(__VA_ARGS__) -#define vfnmsac_vv_f16m8_m(...) __riscv_vfnmsac_vv_f16m8_tumu(__VA_ARGS__) -#define vfnmsac_vf_f16m8_m(...) __riscv_vfnmsac_vf_f16m8_tumu(__VA_ARGS__) -#define vfnmsac_vv_f32mf2_m(...) __riscv_vfnmsac_vv_f32mf2_tumu(__VA_ARGS__) -#define vfnmsac_vf_f32mf2_m(...) __riscv_vfnmsac_vf_f32mf2_tumu(__VA_ARGS__) -#define vfnmsac_vv_f32m1_m(...) __riscv_vfnmsac_vv_f32m1_tumu(__VA_ARGS__) -#define vfnmsac_vf_f32m1_m(...) __riscv_vfnmsac_vf_f32m1_tumu(__VA_ARGS__) -#define vfnmsac_vv_f32m2_m(...) __riscv_vfnmsac_vv_f32m2_tumu(__VA_ARGS__) -#define vfnmsac_vf_f32m2_m(...) __riscv_vfnmsac_vf_f32m2_tumu(__VA_ARGS__) -#define vfnmsac_vv_f32m4_m(...) __riscv_vfnmsac_vv_f32m4_tumu(__VA_ARGS__) -#define vfnmsac_vf_f32m4_m(...) __riscv_vfnmsac_vf_f32m4_tumu(__VA_ARGS__) -#define vfnmsac_vv_f32m8_m(...) __riscv_vfnmsac_vv_f32m8_tumu(__VA_ARGS__) -#define vfnmsac_vf_f32m8_m(...) __riscv_vfnmsac_vf_f32m8_tumu(__VA_ARGS__) -#define vfnmsac_vv_f64m1_m(...) __riscv_vfnmsac_vv_f64m1_tumu(__VA_ARGS__) -#define vfnmsac_vf_f64m1_m(...) __riscv_vfnmsac_vf_f64m1_tumu(__VA_ARGS__) -#define vfnmsac_vv_f64m2_m(...) __riscv_vfnmsac_vv_f64m2_tumu(__VA_ARGS__) -#define vfnmsac_vf_f64m2_m(...) __riscv_vfnmsac_vf_f64m2_tumu(__VA_ARGS__) -#define vfnmsac_vv_f64m4_m(...) __riscv_vfnmsac_vv_f64m4_tumu(__VA_ARGS__) -#define vfnmsac_vf_f64m4_m(...) __riscv_vfnmsac_vf_f64m4_tumu(__VA_ARGS__) -#define vfnmsac_vv_f64m8_m(...) __riscv_vfnmsac_vv_f64m8_tumu(__VA_ARGS__) -#define vfnmsac_vf_f64m8_m(...) __riscv_vfnmsac_vf_f64m8_tumu(__VA_ARGS__) -#define vfmadd_vv_f16mf4_m(...) __riscv_vfmadd_vv_f16mf4_tumu(__VA_ARGS__) -#define vfmadd_vf_f16mf4_m(...) __riscv_vfmadd_vf_f16mf4_tumu(__VA_ARGS__) -#define vfmadd_vv_f16mf2_m(...) __riscv_vfmadd_vv_f16mf2_tumu(__VA_ARGS__) -#define vfmadd_vf_f16mf2_m(...) __riscv_vfmadd_vf_f16mf2_tumu(__VA_ARGS__) -#define vfmadd_vv_f16m1_m(...) __riscv_vfmadd_vv_f16m1_tumu(__VA_ARGS__) -#define vfmadd_vf_f16m1_m(...) __riscv_vfmadd_vf_f16m1_tumu(__VA_ARGS__) -#define vfmadd_vv_f16m2_m(...) __riscv_vfmadd_vv_f16m2_tumu(__VA_ARGS__) -#define vfmadd_vf_f16m2_m(...) __riscv_vfmadd_vf_f16m2_tumu(__VA_ARGS__) -#define vfmadd_vv_f16m4_m(...) __riscv_vfmadd_vv_f16m4_tumu(__VA_ARGS__) -#define vfmadd_vf_f16m4_m(...) __riscv_vfmadd_vf_f16m4_tumu(__VA_ARGS__) -#define vfmadd_vv_f16m8_m(...) __riscv_vfmadd_vv_f16m8_tumu(__VA_ARGS__) -#define vfmadd_vf_f16m8_m(...) __riscv_vfmadd_vf_f16m8_tumu(__VA_ARGS__) -#define vfmadd_vv_f32mf2_m(...) __riscv_vfmadd_vv_f32mf2_tumu(__VA_ARGS__) -#define vfmadd_vf_f32mf2_m(...) __riscv_vfmadd_vf_f32mf2_tumu(__VA_ARGS__) -#define vfmadd_vv_f32m1_m(...) __riscv_vfmadd_vv_f32m1_tumu(__VA_ARGS__) -#define vfmadd_vf_f32m1_m(...) __riscv_vfmadd_vf_f32m1_tumu(__VA_ARGS__) -#define vfmadd_vv_f32m2_m(...) __riscv_vfmadd_vv_f32m2_tumu(__VA_ARGS__) -#define vfmadd_vf_f32m2_m(...) __riscv_vfmadd_vf_f32m2_tumu(__VA_ARGS__) -#define vfmadd_vv_f32m4_m(...) __riscv_vfmadd_vv_f32m4_tumu(__VA_ARGS__) -#define vfmadd_vf_f32m4_m(...) __riscv_vfmadd_vf_f32m4_tumu(__VA_ARGS__) -#define vfmadd_vv_f32m8_m(...) __riscv_vfmadd_vv_f32m8_tumu(__VA_ARGS__) -#define vfmadd_vf_f32m8_m(...) __riscv_vfmadd_vf_f32m8_tumu(__VA_ARGS__) -#define vfmadd_vv_f64m1_m(...) __riscv_vfmadd_vv_f64m1_tumu(__VA_ARGS__) -#define vfmadd_vf_f64m1_m(...) __riscv_vfmadd_vf_f64m1_tumu(__VA_ARGS__) -#define vfmadd_vv_f64m2_m(...) __riscv_vfmadd_vv_f64m2_tumu(__VA_ARGS__) -#define vfmadd_vf_f64m2_m(...) __riscv_vfmadd_vf_f64m2_tumu(__VA_ARGS__) -#define vfmadd_vv_f64m4_m(...) __riscv_vfmadd_vv_f64m4_tumu(__VA_ARGS__) -#define vfmadd_vf_f64m4_m(...) __riscv_vfmadd_vf_f64m4_tumu(__VA_ARGS__) -#define vfmadd_vv_f64m8_m(...) __riscv_vfmadd_vv_f64m8_tumu(__VA_ARGS__) -#define vfmadd_vf_f64m8_m(...) __riscv_vfmadd_vf_f64m8_tumu(__VA_ARGS__) -#define vfnmadd_vv_f16mf4_m(...) __riscv_vfnmadd_vv_f16mf4_tumu(__VA_ARGS__) -#define vfnmadd_vf_f16mf4_m(...) __riscv_vfnmadd_vf_f16mf4_tumu(__VA_ARGS__) -#define vfnmadd_vv_f16mf2_m(...) __riscv_vfnmadd_vv_f16mf2_tumu(__VA_ARGS__) -#define vfnmadd_vf_f16mf2_m(...) __riscv_vfnmadd_vf_f16mf2_tumu(__VA_ARGS__) -#define vfnmadd_vv_f16m1_m(...) __riscv_vfnmadd_vv_f16m1_tumu(__VA_ARGS__) -#define vfnmadd_vf_f16m1_m(...) __riscv_vfnmadd_vf_f16m1_tumu(__VA_ARGS__) -#define vfnmadd_vv_f16m2_m(...) __riscv_vfnmadd_vv_f16m2_tumu(__VA_ARGS__) -#define vfnmadd_vf_f16m2_m(...) __riscv_vfnmadd_vf_f16m2_tumu(__VA_ARGS__) -#define vfnmadd_vv_f16m4_m(...) __riscv_vfnmadd_vv_f16m4_tumu(__VA_ARGS__) -#define vfnmadd_vf_f16m4_m(...) __riscv_vfnmadd_vf_f16m4_tumu(__VA_ARGS__) -#define vfnmadd_vv_f16m8_m(...) __riscv_vfnmadd_vv_f16m8_tumu(__VA_ARGS__) -#define vfnmadd_vf_f16m8_m(...) __riscv_vfnmadd_vf_f16m8_tumu(__VA_ARGS__) -#define vfnmadd_vv_f32mf2_m(...) __riscv_vfnmadd_vv_f32mf2_tumu(__VA_ARGS__) -#define vfnmadd_vf_f32mf2_m(...) __riscv_vfnmadd_vf_f32mf2_tumu(__VA_ARGS__) -#define vfnmadd_vv_f32m1_m(...) __riscv_vfnmadd_vv_f32m1_tumu(__VA_ARGS__) -#define vfnmadd_vf_f32m1_m(...) __riscv_vfnmadd_vf_f32m1_tumu(__VA_ARGS__) -#define vfnmadd_vv_f32m2_m(...) __riscv_vfnmadd_vv_f32m2_tumu(__VA_ARGS__) -#define vfnmadd_vf_f32m2_m(...) __riscv_vfnmadd_vf_f32m2_tumu(__VA_ARGS__) -#define vfnmadd_vv_f32m4_m(...) __riscv_vfnmadd_vv_f32m4_tumu(__VA_ARGS__) -#define vfnmadd_vf_f32m4_m(...) __riscv_vfnmadd_vf_f32m4_tumu(__VA_ARGS__) -#define vfnmadd_vv_f32m8_m(...) __riscv_vfnmadd_vv_f32m8_tumu(__VA_ARGS__) -#define vfnmadd_vf_f32m8_m(...) __riscv_vfnmadd_vf_f32m8_tumu(__VA_ARGS__) -#define vfnmadd_vv_f64m1_m(...) __riscv_vfnmadd_vv_f64m1_tumu(__VA_ARGS__) -#define vfnmadd_vf_f64m1_m(...) __riscv_vfnmadd_vf_f64m1_tumu(__VA_ARGS__) -#define vfnmadd_vv_f64m2_m(...) __riscv_vfnmadd_vv_f64m2_tumu(__VA_ARGS__) -#define vfnmadd_vf_f64m2_m(...) __riscv_vfnmadd_vf_f64m2_tumu(__VA_ARGS__) -#define vfnmadd_vv_f64m4_m(...) __riscv_vfnmadd_vv_f64m4_tumu(__VA_ARGS__) -#define vfnmadd_vf_f64m4_m(...) __riscv_vfnmadd_vf_f64m4_tumu(__VA_ARGS__) -#define vfnmadd_vv_f64m8_m(...) __riscv_vfnmadd_vv_f64m8_tumu(__VA_ARGS__) -#define vfnmadd_vf_f64m8_m(...) __riscv_vfnmadd_vf_f64m8_tumu(__VA_ARGS__) -#define vfmsub_vv_f16mf4_m(...) __riscv_vfmsub_vv_f16mf4_tumu(__VA_ARGS__) -#define vfmsub_vf_f16mf4_m(...) __riscv_vfmsub_vf_f16mf4_tumu(__VA_ARGS__) -#define vfmsub_vv_f16mf2_m(...) __riscv_vfmsub_vv_f16mf2_tumu(__VA_ARGS__) -#define vfmsub_vf_f16mf2_m(...) __riscv_vfmsub_vf_f16mf2_tumu(__VA_ARGS__) -#define vfmsub_vv_f16m1_m(...) __riscv_vfmsub_vv_f16m1_tumu(__VA_ARGS__) -#define vfmsub_vf_f16m1_m(...) __riscv_vfmsub_vf_f16m1_tumu(__VA_ARGS__) -#define vfmsub_vv_f16m2_m(...) __riscv_vfmsub_vv_f16m2_tumu(__VA_ARGS__) -#define vfmsub_vf_f16m2_m(...) __riscv_vfmsub_vf_f16m2_tumu(__VA_ARGS__) -#define vfmsub_vv_f16m4_m(...) __riscv_vfmsub_vv_f16m4_tumu(__VA_ARGS__) -#define vfmsub_vf_f16m4_m(...) __riscv_vfmsub_vf_f16m4_tumu(__VA_ARGS__) -#define vfmsub_vv_f16m8_m(...) __riscv_vfmsub_vv_f16m8_tumu(__VA_ARGS__) -#define vfmsub_vf_f16m8_m(...) __riscv_vfmsub_vf_f16m8_tumu(__VA_ARGS__) -#define vfmsub_vv_f32mf2_m(...) __riscv_vfmsub_vv_f32mf2_tumu(__VA_ARGS__) -#define vfmsub_vf_f32mf2_m(...) __riscv_vfmsub_vf_f32mf2_tumu(__VA_ARGS__) -#define vfmsub_vv_f32m1_m(...) __riscv_vfmsub_vv_f32m1_tumu(__VA_ARGS__) -#define vfmsub_vf_f32m1_m(...) __riscv_vfmsub_vf_f32m1_tumu(__VA_ARGS__) -#define vfmsub_vv_f32m2_m(...) __riscv_vfmsub_vv_f32m2_tumu(__VA_ARGS__) -#define vfmsub_vf_f32m2_m(...) __riscv_vfmsub_vf_f32m2_tumu(__VA_ARGS__) -#define vfmsub_vv_f32m4_m(...) __riscv_vfmsub_vv_f32m4_tumu(__VA_ARGS__) -#define vfmsub_vf_f32m4_m(...) __riscv_vfmsub_vf_f32m4_tumu(__VA_ARGS__) -#define vfmsub_vv_f32m8_m(...) __riscv_vfmsub_vv_f32m8_tumu(__VA_ARGS__) -#define vfmsub_vf_f32m8_m(...) __riscv_vfmsub_vf_f32m8_tumu(__VA_ARGS__) -#define vfmsub_vv_f64m1_m(...) __riscv_vfmsub_vv_f64m1_tumu(__VA_ARGS__) -#define vfmsub_vf_f64m1_m(...) __riscv_vfmsub_vf_f64m1_tumu(__VA_ARGS__) -#define vfmsub_vv_f64m2_m(...) __riscv_vfmsub_vv_f64m2_tumu(__VA_ARGS__) -#define vfmsub_vf_f64m2_m(...) __riscv_vfmsub_vf_f64m2_tumu(__VA_ARGS__) -#define vfmsub_vv_f64m4_m(...) __riscv_vfmsub_vv_f64m4_tumu(__VA_ARGS__) -#define vfmsub_vf_f64m4_m(...) __riscv_vfmsub_vf_f64m4_tumu(__VA_ARGS__) -#define vfmsub_vv_f64m8_m(...) __riscv_vfmsub_vv_f64m8_tumu(__VA_ARGS__) -#define vfmsub_vf_f64m8_m(...) __riscv_vfmsub_vf_f64m8_tumu(__VA_ARGS__) -#define vfnmsub_vv_f16mf4_m(...) __riscv_vfnmsub_vv_f16mf4_tumu(__VA_ARGS__) -#define vfnmsub_vf_f16mf4_m(...) __riscv_vfnmsub_vf_f16mf4_tumu(__VA_ARGS__) -#define vfnmsub_vv_f16mf2_m(...) __riscv_vfnmsub_vv_f16mf2_tumu(__VA_ARGS__) -#define vfnmsub_vf_f16mf2_m(...) __riscv_vfnmsub_vf_f16mf2_tumu(__VA_ARGS__) -#define vfnmsub_vv_f16m1_m(...) __riscv_vfnmsub_vv_f16m1_tumu(__VA_ARGS__) -#define vfnmsub_vf_f16m1_m(...) __riscv_vfnmsub_vf_f16m1_tumu(__VA_ARGS__) -#define vfnmsub_vv_f16m2_m(...) __riscv_vfnmsub_vv_f16m2_tumu(__VA_ARGS__) -#define vfnmsub_vf_f16m2_m(...) __riscv_vfnmsub_vf_f16m2_tumu(__VA_ARGS__) -#define vfnmsub_vv_f16m4_m(...) __riscv_vfnmsub_vv_f16m4_tumu(__VA_ARGS__) -#define vfnmsub_vf_f16m4_m(...) __riscv_vfnmsub_vf_f16m4_tumu(__VA_ARGS__) -#define vfnmsub_vv_f16m8_m(...) __riscv_vfnmsub_vv_f16m8_tumu(__VA_ARGS__) -#define vfnmsub_vf_f16m8_m(...) __riscv_vfnmsub_vf_f16m8_tumu(__VA_ARGS__) -#define vfnmsub_vv_f32mf2_m(...) __riscv_vfnmsub_vv_f32mf2_tumu(__VA_ARGS__) -#define vfnmsub_vf_f32mf2_m(...) __riscv_vfnmsub_vf_f32mf2_tumu(__VA_ARGS__) -#define vfnmsub_vv_f32m1_m(...) __riscv_vfnmsub_vv_f32m1_tumu(__VA_ARGS__) -#define vfnmsub_vf_f32m1_m(...) __riscv_vfnmsub_vf_f32m1_tumu(__VA_ARGS__) -#define vfnmsub_vv_f32m2_m(...) __riscv_vfnmsub_vv_f32m2_tumu(__VA_ARGS__) -#define vfnmsub_vf_f32m2_m(...) __riscv_vfnmsub_vf_f32m2_tumu(__VA_ARGS__) -#define vfnmsub_vv_f32m4_m(...) __riscv_vfnmsub_vv_f32m4_tumu(__VA_ARGS__) -#define vfnmsub_vf_f32m4_m(...) __riscv_vfnmsub_vf_f32m4_tumu(__VA_ARGS__) -#define vfnmsub_vv_f32m8_m(...) __riscv_vfnmsub_vv_f32m8_tumu(__VA_ARGS__) -#define vfnmsub_vf_f32m8_m(...) __riscv_vfnmsub_vf_f32m8_tumu(__VA_ARGS__) -#define vfnmsub_vv_f64m1_m(...) __riscv_vfnmsub_vv_f64m1_tumu(__VA_ARGS__) -#define vfnmsub_vf_f64m1_m(...) __riscv_vfnmsub_vf_f64m1_tumu(__VA_ARGS__) -#define vfnmsub_vv_f64m2_m(...) __riscv_vfnmsub_vv_f64m2_tumu(__VA_ARGS__) -#define vfnmsub_vf_f64m2_m(...) __riscv_vfnmsub_vf_f64m2_tumu(__VA_ARGS__) -#define vfnmsub_vv_f64m4_m(...) __riscv_vfnmsub_vv_f64m4_tumu(__VA_ARGS__) -#define vfnmsub_vf_f64m4_m(...) __riscv_vfnmsub_vf_f64m4_tumu(__VA_ARGS__) -#define vfnmsub_vv_f64m8_m(...) __riscv_vfnmsub_vv_f64m8_tumu(__VA_ARGS__) -#define vfnmsub_vf_f64m8_m(...) __riscv_vfnmsub_vf_f64m8_tumu(__VA_ARGS__) -#define vfwmacc_vv_f32mf2(...) __riscv_vfwmacc_vv_f32mf2_tu(__VA_ARGS__) -#define vfwmacc_vf_f32mf2(...) __riscv_vfwmacc_vf_f32mf2_tu(__VA_ARGS__) -#define vfwmacc_vv_f32m1(...) __riscv_vfwmacc_vv_f32m1_tu(__VA_ARGS__) -#define vfwmacc_vf_f32m1(...) __riscv_vfwmacc_vf_f32m1_tu(__VA_ARGS__) -#define vfwmacc_vv_f32m2(...) __riscv_vfwmacc_vv_f32m2_tu(__VA_ARGS__) -#define vfwmacc_vf_f32m2(...) __riscv_vfwmacc_vf_f32m2_tu(__VA_ARGS__) -#define vfwmacc_vv_f32m4(...) __riscv_vfwmacc_vv_f32m4_tu(__VA_ARGS__) -#define vfwmacc_vf_f32m4(...) __riscv_vfwmacc_vf_f32m4_tu(__VA_ARGS__) -#define vfwmacc_vv_f32m8(...) __riscv_vfwmacc_vv_f32m8_tu(__VA_ARGS__) -#define vfwmacc_vf_f32m8(...) __riscv_vfwmacc_vf_f32m8_tu(__VA_ARGS__) -#define vfwmacc_vv_f64m1(...) __riscv_vfwmacc_vv_f64m1_tu(__VA_ARGS__) -#define vfwmacc_vf_f64m1(...) __riscv_vfwmacc_vf_f64m1_tu(__VA_ARGS__) -#define vfwmacc_vv_f64m2(...) __riscv_vfwmacc_vv_f64m2_tu(__VA_ARGS__) -#define vfwmacc_vf_f64m2(...) __riscv_vfwmacc_vf_f64m2_tu(__VA_ARGS__) -#define vfwmacc_vv_f64m4(...) __riscv_vfwmacc_vv_f64m4_tu(__VA_ARGS__) -#define vfwmacc_vf_f64m4(...) __riscv_vfwmacc_vf_f64m4_tu(__VA_ARGS__) -#define vfwmacc_vv_f64m8(...) __riscv_vfwmacc_vv_f64m8_tu(__VA_ARGS__) -#define vfwmacc_vf_f64m8(...) __riscv_vfwmacc_vf_f64m8_tu(__VA_ARGS__) -#define vfwnmacc_vv_f32mf2(...) __riscv_vfwnmacc_vv_f32mf2_tu(__VA_ARGS__) -#define vfwnmacc_vf_f32mf2(...) __riscv_vfwnmacc_vf_f32mf2_tu(__VA_ARGS__) -#define vfwnmacc_vv_f32m1(...) __riscv_vfwnmacc_vv_f32m1_tu(__VA_ARGS__) -#define vfwnmacc_vf_f32m1(...) __riscv_vfwnmacc_vf_f32m1_tu(__VA_ARGS__) -#define vfwnmacc_vv_f32m2(...) __riscv_vfwnmacc_vv_f32m2_tu(__VA_ARGS__) -#define vfwnmacc_vf_f32m2(...) __riscv_vfwnmacc_vf_f32m2_tu(__VA_ARGS__) -#define vfwnmacc_vv_f32m4(...) __riscv_vfwnmacc_vv_f32m4_tu(__VA_ARGS__) -#define vfwnmacc_vf_f32m4(...) __riscv_vfwnmacc_vf_f32m4_tu(__VA_ARGS__) -#define vfwnmacc_vv_f32m8(...) __riscv_vfwnmacc_vv_f32m8_tu(__VA_ARGS__) -#define vfwnmacc_vf_f32m8(...) __riscv_vfwnmacc_vf_f32m8_tu(__VA_ARGS__) -#define vfwnmacc_vv_f64m1(...) __riscv_vfwnmacc_vv_f64m1_tu(__VA_ARGS__) -#define vfwnmacc_vf_f64m1(...) __riscv_vfwnmacc_vf_f64m1_tu(__VA_ARGS__) -#define vfwnmacc_vv_f64m2(...) __riscv_vfwnmacc_vv_f64m2_tu(__VA_ARGS__) -#define vfwnmacc_vf_f64m2(...) __riscv_vfwnmacc_vf_f64m2_tu(__VA_ARGS__) -#define vfwnmacc_vv_f64m4(...) __riscv_vfwnmacc_vv_f64m4_tu(__VA_ARGS__) -#define vfwnmacc_vf_f64m4(...) __riscv_vfwnmacc_vf_f64m4_tu(__VA_ARGS__) -#define vfwnmacc_vv_f64m8(...) __riscv_vfwnmacc_vv_f64m8_tu(__VA_ARGS__) -#define vfwnmacc_vf_f64m8(...) __riscv_vfwnmacc_vf_f64m8_tu(__VA_ARGS__) -#define vfwmsac_vv_f32mf2(...) __riscv_vfwmsac_vv_f32mf2_tu(__VA_ARGS__) -#define vfwmsac_vf_f32mf2(...) __riscv_vfwmsac_vf_f32mf2_tu(__VA_ARGS__) -#define vfwmsac_vv_f32m1(...) __riscv_vfwmsac_vv_f32m1_tu(__VA_ARGS__) -#define vfwmsac_vf_f32m1(...) __riscv_vfwmsac_vf_f32m1_tu(__VA_ARGS__) -#define vfwmsac_vv_f32m2(...) __riscv_vfwmsac_vv_f32m2_tu(__VA_ARGS__) -#define vfwmsac_vf_f32m2(...) __riscv_vfwmsac_vf_f32m2_tu(__VA_ARGS__) -#define vfwmsac_vv_f32m4(...) __riscv_vfwmsac_vv_f32m4_tu(__VA_ARGS__) -#define vfwmsac_vf_f32m4(...) __riscv_vfwmsac_vf_f32m4_tu(__VA_ARGS__) -#define vfwmsac_vv_f32m8(...) __riscv_vfwmsac_vv_f32m8_tu(__VA_ARGS__) -#define vfwmsac_vf_f32m8(...) __riscv_vfwmsac_vf_f32m8_tu(__VA_ARGS__) -#define vfwmsac_vv_f64m1(...) __riscv_vfwmsac_vv_f64m1_tu(__VA_ARGS__) -#define vfwmsac_vf_f64m1(...) __riscv_vfwmsac_vf_f64m1_tu(__VA_ARGS__) -#define vfwmsac_vv_f64m2(...) __riscv_vfwmsac_vv_f64m2_tu(__VA_ARGS__) -#define vfwmsac_vf_f64m2(...) __riscv_vfwmsac_vf_f64m2_tu(__VA_ARGS__) -#define vfwmsac_vv_f64m4(...) __riscv_vfwmsac_vv_f64m4_tu(__VA_ARGS__) -#define vfwmsac_vf_f64m4(...) __riscv_vfwmsac_vf_f64m4_tu(__VA_ARGS__) -#define vfwmsac_vv_f64m8(...) __riscv_vfwmsac_vv_f64m8_tu(__VA_ARGS__) -#define vfwmsac_vf_f64m8(...) __riscv_vfwmsac_vf_f64m8_tu(__VA_ARGS__) -#define vfwnmsac_vv_f32mf2(...) __riscv_vfwnmsac_vv_f32mf2_tu(__VA_ARGS__) -#define vfwnmsac_vf_f32mf2(...) __riscv_vfwnmsac_vf_f32mf2_tu(__VA_ARGS__) -#define vfwnmsac_vv_f32m1(...) __riscv_vfwnmsac_vv_f32m1_tu(__VA_ARGS__) -#define vfwnmsac_vf_f32m1(...) __riscv_vfwnmsac_vf_f32m1_tu(__VA_ARGS__) -#define vfwnmsac_vv_f32m2(...) __riscv_vfwnmsac_vv_f32m2_tu(__VA_ARGS__) -#define vfwnmsac_vf_f32m2(...) __riscv_vfwnmsac_vf_f32m2_tu(__VA_ARGS__) -#define vfwnmsac_vv_f32m4(...) __riscv_vfwnmsac_vv_f32m4_tu(__VA_ARGS__) -#define vfwnmsac_vf_f32m4(...) __riscv_vfwnmsac_vf_f32m4_tu(__VA_ARGS__) -#define vfwnmsac_vv_f32m8(...) __riscv_vfwnmsac_vv_f32m8_tu(__VA_ARGS__) -#define vfwnmsac_vf_f32m8(...) __riscv_vfwnmsac_vf_f32m8_tu(__VA_ARGS__) -#define vfwnmsac_vv_f64m1(...) __riscv_vfwnmsac_vv_f64m1_tu(__VA_ARGS__) -#define vfwnmsac_vf_f64m1(...) __riscv_vfwnmsac_vf_f64m1_tu(__VA_ARGS__) -#define vfwnmsac_vv_f64m2(...) __riscv_vfwnmsac_vv_f64m2_tu(__VA_ARGS__) -#define vfwnmsac_vf_f64m2(...) __riscv_vfwnmsac_vf_f64m2_tu(__VA_ARGS__) -#define vfwnmsac_vv_f64m4(...) __riscv_vfwnmsac_vv_f64m4_tu(__VA_ARGS__) -#define vfwnmsac_vf_f64m4(...) __riscv_vfwnmsac_vf_f64m4_tu(__VA_ARGS__) -#define vfwnmsac_vv_f64m8(...) __riscv_vfwnmsac_vv_f64m8_tu(__VA_ARGS__) -#define vfwnmsac_vf_f64m8(...) __riscv_vfwnmsac_vf_f64m8_tu(__VA_ARGS__) -// masked functions -#define vfwmacc_vv_f32mf2_m(...) __riscv_vfwmacc_vv_f32mf2_tumu(__VA_ARGS__) -#define vfwmacc_vf_f32mf2_m(...) __riscv_vfwmacc_vf_f32mf2_tumu(__VA_ARGS__) -#define vfwmacc_vv_f32m1_m(...) __riscv_vfwmacc_vv_f32m1_tumu(__VA_ARGS__) -#define vfwmacc_vf_f32m1_m(...) __riscv_vfwmacc_vf_f32m1_tumu(__VA_ARGS__) -#define vfwmacc_vv_f32m2_m(...) __riscv_vfwmacc_vv_f32m2_tumu(__VA_ARGS__) -#define vfwmacc_vf_f32m2_m(...) __riscv_vfwmacc_vf_f32m2_tumu(__VA_ARGS__) -#define vfwmacc_vv_f32m4_m(...) __riscv_vfwmacc_vv_f32m4_tumu(__VA_ARGS__) -#define vfwmacc_vf_f32m4_m(...) __riscv_vfwmacc_vf_f32m4_tumu(__VA_ARGS__) -#define vfwmacc_vv_f32m8_m(...) __riscv_vfwmacc_vv_f32m8_tumu(__VA_ARGS__) -#define vfwmacc_vf_f32m8_m(...) __riscv_vfwmacc_vf_f32m8_tumu(__VA_ARGS__) -#define vfwmacc_vv_f64m1_m(...) __riscv_vfwmacc_vv_f64m1_tumu(__VA_ARGS__) -#define vfwmacc_vf_f64m1_m(...) __riscv_vfwmacc_vf_f64m1_tumu(__VA_ARGS__) -#define vfwmacc_vv_f64m2_m(...) __riscv_vfwmacc_vv_f64m2_tumu(__VA_ARGS__) -#define vfwmacc_vf_f64m2_m(...) __riscv_vfwmacc_vf_f64m2_tumu(__VA_ARGS__) -#define vfwmacc_vv_f64m4_m(...) __riscv_vfwmacc_vv_f64m4_tumu(__VA_ARGS__) -#define vfwmacc_vf_f64m4_m(...) __riscv_vfwmacc_vf_f64m4_tumu(__VA_ARGS__) -#define vfwmacc_vv_f64m8_m(...) __riscv_vfwmacc_vv_f64m8_tumu(__VA_ARGS__) -#define vfwmacc_vf_f64m8_m(...) __riscv_vfwmacc_vf_f64m8_tumu(__VA_ARGS__) -#define vfwnmacc_vv_f32mf2_m(...) __riscv_vfwnmacc_vv_f32mf2_tumu(__VA_ARGS__) -#define vfwnmacc_vf_f32mf2_m(...) __riscv_vfwnmacc_vf_f32mf2_tumu(__VA_ARGS__) -#define vfwnmacc_vv_f32m1_m(...) __riscv_vfwnmacc_vv_f32m1_tumu(__VA_ARGS__) -#define vfwnmacc_vf_f32m1_m(...) __riscv_vfwnmacc_vf_f32m1_tumu(__VA_ARGS__) -#define vfwnmacc_vv_f32m2_m(...) __riscv_vfwnmacc_vv_f32m2_tumu(__VA_ARGS__) -#define vfwnmacc_vf_f32m2_m(...) __riscv_vfwnmacc_vf_f32m2_tumu(__VA_ARGS__) -#define vfwnmacc_vv_f32m4_m(...) __riscv_vfwnmacc_vv_f32m4_tumu(__VA_ARGS__) -#define vfwnmacc_vf_f32m4_m(...) __riscv_vfwnmacc_vf_f32m4_tumu(__VA_ARGS__) -#define vfwnmacc_vv_f32m8_m(...) __riscv_vfwnmacc_vv_f32m8_tumu(__VA_ARGS__) -#define vfwnmacc_vf_f32m8_m(...) __riscv_vfwnmacc_vf_f32m8_tumu(__VA_ARGS__) -#define vfwnmacc_vv_f64m1_m(...) __riscv_vfwnmacc_vv_f64m1_tumu(__VA_ARGS__) -#define vfwnmacc_vf_f64m1_m(...) __riscv_vfwnmacc_vf_f64m1_tumu(__VA_ARGS__) -#define vfwnmacc_vv_f64m2_m(...) __riscv_vfwnmacc_vv_f64m2_tumu(__VA_ARGS__) -#define vfwnmacc_vf_f64m2_m(...) __riscv_vfwnmacc_vf_f64m2_tumu(__VA_ARGS__) -#define vfwnmacc_vv_f64m4_m(...) __riscv_vfwnmacc_vv_f64m4_tumu(__VA_ARGS__) -#define vfwnmacc_vf_f64m4_m(...) __riscv_vfwnmacc_vf_f64m4_tumu(__VA_ARGS__) -#define vfwnmacc_vv_f64m8_m(...) __riscv_vfwnmacc_vv_f64m8_tumu(__VA_ARGS__) -#define vfwnmacc_vf_f64m8_m(...) __riscv_vfwnmacc_vf_f64m8_tumu(__VA_ARGS__) -#define vfwmsac_vv_f32mf2_m(...) __riscv_vfwmsac_vv_f32mf2_tumu(__VA_ARGS__) -#define vfwmsac_vf_f32mf2_m(...) __riscv_vfwmsac_vf_f32mf2_tumu(__VA_ARGS__) -#define vfwmsac_vv_f32m1_m(...) __riscv_vfwmsac_vv_f32m1_tumu(__VA_ARGS__) -#define vfwmsac_vf_f32m1_m(...) __riscv_vfwmsac_vf_f32m1_tumu(__VA_ARGS__) -#define vfwmsac_vv_f32m2_m(...) __riscv_vfwmsac_vv_f32m2_tumu(__VA_ARGS__) -#define vfwmsac_vf_f32m2_m(...) __riscv_vfwmsac_vf_f32m2_tumu(__VA_ARGS__) -#define vfwmsac_vv_f32m4_m(...) __riscv_vfwmsac_vv_f32m4_tumu(__VA_ARGS__) -#define vfwmsac_vf_f32m4_m(...) __riscv_vfwmsac_vf_f32m4_tumu(__VA_ARGS__) -#define vfwmsac_vv_f32m8_m(...) __riscv_vfwmsac_vv_f32m8_tumu(__VA_ARGS__) -#define vfwmsac_vf_f32m8_m(...) __riscv_vfwmsac_vf_f32m8_tumu(__VA_ARGS__) -#define vfwmsac_vv_f64m1_m(...) __riscv_vfwmsac_vv_f64m1_tumu(__VA_ARGS__) -#define vfwmsac_vf_f64m1_m(...) __riscv_vfwmsac_vf_f64m1_tumu(__VA_ARGS__) -#define vfwmsac_vv_f64m2_m(...) __riscv_vfwmsac_vv_f64m2_tumu(__VA_ARGS__) -#define vfwmsac_vf_f64m2_m(...) __riscv_vfwmsac_vf_f64m2_tumu(__VA_ARGS__) -#define vfwmsac_vv_f64m4_m(...) __riscv_vfwmsac_vv_f64m4_tumu(__VA_ARGS__) -#define vfwmsac_vf_f64m4_m(...) __riscv_vfwmsac_vf_f64m4_tumu(__VA_ARGS__) -#define vfwmsac_vv_f64m8_m(...) __riscv_vfwmsac_vv_f64m8_tumu(__VA_ARGS__) -#define vfwmsac_vf_f64m8_m(...) __riscv_vfwmsac_vf_f64m8_tumu(__VA_ARGS__) -#define vfwnmsac_vv_f32mf2_m(...) __riscv_vfwnmsac_vv_f32mf2_tumu(__VA_ARGS__) -#define vfwnmsac_vf_f32mf2_m(...) __riscv_vfwnmsac_vf_f32mf2_tumu(__VA_ARGS__) -#define vfwnmsac_vv_f32m1_m(...) __riscv_vfwnmsac_vv_f32m1_tumu(__VA_ARGS__) -#define vfwnmsac_vf_f32m1_m(...) __riscv_vfwnmsac_vf_f32m1_tumu(__VA_ARGS__) -#define vfwnmsac_vv_f32m2_m(...) __riscv_vfwnmsac_vv_f32m2_tumu(__VA_ARGS__) -#define vfwnmsac_vf_f32m2_m(...) __riscv_vfwnmsac_vf_f32m2_tumu(__VA_ARGS__) -#define vfwnmsac_vv_f32m4_m(...) __riscv_vfwnmsac_vv_f32m4_tumu(__VA_ARGS__) -#define vfwnmsac_vf_f32m4_m(...) __riscv_vfwnmsac_vf_f32m4_tumu(__VA_ARGS__) -#define vfwnmsac_vv_f32m8_m(...) __riscv_vfwnmsac_vv_f32m8_tumu(__VA_ARGS__) -#define vfwnmsac_vf_f32m8_m(...) __riscv_vfwnmsac_vf_f32m8_tumu(__VA_ARGS__) -#define vfwnmsac_vv_f64m1_m(...) __riscv_vfwnmsac_vv_f64m1_tumu(__VA_ARGS__) -#define vfwnmsac_vf_f64m1_m(...) __riscv_vfwnmsac_vf_f64m1_tumu(__VA_ARGS__) -#define vfwnmsac_vv_f64m2_m(...) __riscv_vfwnmsac_vv_f64m2_tumu(__VA_ARGS__) -#define vfwnmsac_vf_f64m2_m(...) __riscv_vfwnmsac_vf_f64m2_tumu(__VA_ARGS__) -#define vfwnmsac_vv_f64m4_m(...) __riscv_vfwnmsac_vv_f64m4_tumu(__VA_ARGS__) -#define vfwnmsac_vf_f64m4_m(...) __riscv_vfwnmsac_vf_f64m4_tumu(__VA_ARGS__) -#define vfwnmsac_vv_f64m8_m(...) __riscv_vfwnmsac_vv_f64m8_tumu(__VA_ARGS__) -#define vfwnmsac_vf_f64m8_m(...) __riscv_vfwnmsac_vf_f64m8_tumu(__VA_ARGS__) -#define vfsqrt_v_f16mf4(...) __riscv_vfsqrt_v_f16mf4(__VA_ARGS__) -#define vfsqrt_v_f16mf2(...) __riscv_vfsqrt_v_f16mf2(__VA_ARGS__) -#define vfsqrt_v_f16m1(...) __riscv_vfsqrt_v_f16m1(__VA_ARGS__) -#define vfsqrt_v_f16m2(...) __riscv_vfsqrt_v_f16m2(__VA_ARGS__) -#define vfsqrt_v_f16m4(...) __riscv_vfsqrt_v_f16m4(__VA_ARGS__) -#define vfsqrt_v_f16m8(...) __riscv_vfsqrt_v_f16m8(__VA_ARGS__) -#define vfsqrt_v_f32mf2(...) __riscv_vfsqrt_v_f32mf2(__VA_ARGS__) -#define vfsqrt_v_f32m1(...) __riscv_vfsqrt_v_f32m1(__VA_ARGS__) -#define vfsqrt_v_f32m2(...) __riscv_vfsqrt_v_f32m2(__VA_ARGS__) -#define vfsqrt_v_f32m4(...) __riscv_vfsqrt_v_f32m4(__VA_ARGS__) -#define vfsqrt_v_f32m8(...) __riscv_vfsqrt_v_f32m8(__VA_ARGS__) -#define vfsqrt_v_f64m1(...) __riscv_vfsqrt_v_f64m1(__VA_ARGS__) -#define vfsqrt_v_f64m2(...) __riscv_vfsqrt_v_f64m2(__VA_ARGS__) -#define vfsqrt_v_f64m4(...) __riscv_vfsqrt_v_f64m4(__VA_ARGS__) -#define vfsqrt_v_f64m8(...) __riscv_vfsqrt_v_f64m8(__VA_ARGS__) -// masked functions -#define vfsqrt_v_f16mf4_m(...) __riscv_vfsqrt_v_f16mf4_tumu(__VA_ARGS__) -#define vfsqrt_v_f16mf2_m(...) __riscv_vfsqrt_v_f16mf2_tumu(__VA_ARGS__) -#define vfsqrt_v_f16m1_m(...) __riscv_vfsqrt_v_f16m1_tumu(__VA_ARGS__) -#define vfsqrt_v_f16m2_m(...) __riscv_vfsqrt_v_f16m2_tumu(__VA_ARGS__) -#define vfsqrt_v_f16m4_m(...) __riscv_vfsqrt_v_f16m4_tumu(__VA_ARGS__) -#define vfsqrt_v_f16m8_m(...) __riscv_vfsqrt_v_f16m8_tumu(__VA_ARGS__) -#define vfsqrt_v_f32mf2_m(...) __riscv_vfsqrt_v_f32mf2_tumu(__VA_ARGS__) -#define vfsqrt_v_f32m1_m(...) __riscv_vfsqrt_v_f32m1_tumu(__VA_ARGS__) -#define vfsqrt_v_f32m2_m(...) __riscv_vfsqrt_v_f32m2_tumu(__VA_ARGS__) -#define vfsqrt_v_f32m4_m(...) __riscv_vfsqrt_v_f32m4_tumu(__VA_ARGS__) -#define vfsqrt_v_f32m8_m(...) __riscv_vfsqrt_v_f32m8_tumu(__VA_ARGS__) -#define vfsqrt_v_f64m1_m(...) __riscv_vfsqrt_v_f64m1_tumu(__VA_ARGS__) -#define vfsqrt_v_f64m2_m(...) __riscv_vfsqrt_v_f64m2_tumu(__VA_ARGS__) -#define vfsqrt_v_f64m4_m(...) __riscv_vfsqrt_v_f64m4_tumu(__VA_ARGS__) -#define vfsqrt_v_f64m8_m(...) __riscv_vfsqrt_v_f64m8_tumu(__VA_ARGS__) -#define vfrsqrt7_v_f16mf4(...) __riscv_vfrsqrt7_v_f16mf4(__VA_ARGS__) -#define vfrsqrt7_v_f16mf2(...) __riscv_vfrsqrt7_v_f16mf2(__VA_ARGS__) -#define vfrsqrt7_v_f16m1(...) __riscv_vfrsqrt7_v_f16m1(__VA_ARGS__) -#define vfrsqrt7_v_f16m2(...) __riscv_vfrsqrt7_v_f16m2(__VA_ARGS__) -#define vfrsqrt7_v_f16m4(...) __riscv_vfrsqrt7_v_f16m4(__VA_ARGS__) -#define vfrsqrt7_v_f16m8(...) __riscv_vfrsqrt7_v_f16m8(__VA_ARGS__) -#define vfrsqrt7_v_f32mf2(...) __riscv_vfrsqrt7_v_f32mf2(__VA_ARGS__) -#define vfrsqrt7_v_f32m1(...) __riscv_vfrsqrt7_v_f32m1(__VA_ARGS__) -#define vfrsqrt7_v_f32m2(...) __riscv_vfrsqrt7_v_f32m2(__VA_ARGS__) -#define vfrsqrt7_v_f32m4(...) __riscv_vfrsqrt7_v_f32m4(__VA_ARGS__) -#define vfrsqrt7_v_f32m8(...) __riscv_vfrsqrt7_v_f32m8(__VA_ARGS__) -#define vfrsqrt7_v_f64m1(...) __riscv_vfrsqrt7_v_f64m1(__VA_ARGS__) -#define vfrsqrt7_v_f64m2(...) __riscv_vfrsqrt7_v_f64m2(__VA_ARGS__) -#define vfrsqrt7_v_f64m4(...) __riscv_vfrsqrt7_v_f64m4(__VA_ARGS__) -#define vfrsqrt7_v_f64m8(...) __riscv_vfrsqrt7_v_f64m8(__VA_ARGS__) -// masked functions -#define vfrsqrt7_v_f16mf4_m(...) __riscv_vfrsqrt7_v_f16mf4_tumu(__VA_ARGS__) -#define vfrsqrt7_v_f16mf2_m(...) __riscv_vfrsqrt7_v_f16mf2_tumu(__VA_ARGS__) -#define vfrsqrt7_v_f16m1_m(...) __riscv_vfrsqrt7_v_f16m1_tumu(__VA_ARGS__) -#define vfrsqrt7_v_f16m2_m(...) __riscv_vfrsqrt7_v_f16m2_tumu(__VA_ARGS__) -#define vfrsqrt7_v_f16m4_m(...) __riscv_vfrsqrt7_v_f16m4_tumu(__VA_ARGS__) -#define vfrsqrt7_v_f16m8_m(...) __riscv_vfrsqrt7_v_f16m8_tumu(__VA_ARGS__) -#define vfrsqrt7_v_f32mf2_m(...) __riscv_vfrsqrt7_v_f32mf2_tumu(__VA_ARGS__) -#define vfrsqrt7_v_f32m1_m(...) __riscv_vfrsqrt7_v_f32m1_tumu(__VA_ARGS__) -#define vfrsqrt7_v_f32m2_m(...) __riscv_vfrsqrt7_v_f32m2_tumu(__VA_ARGS__) -#define vfrsqrt7_v_f32m4_m(...) __riscv_vfrsqrt7_v_f32m4_tumu(__VA_ARGS__) -#define vfrsqrt7_v_f32m8_m(...) __riscv_vfrsqrt7_v_f32m8_tumu(__VA_ARGS__) -#define vfrsqrt7_v_f64m1_m(...) __riscv_vfrsqrt7_v_f64m1_tumu(__VA_ARGS__) -#define vfrsqrt7_v_f64m2_m(...) __riscv_vfrsqrt7_v_f64m2_tumu(__VA_ARGS__) -#define vfrsqrt7_v_f64m4_m(...) __riscv_vfrsqrt7_v_f64m4_tumu(__VA_ARGS__) -#define vfrsqrt7_v_f64m8_m(...) __riscv_vfrsqrt7_v_f64m8_tumu(__VA_ARGS__) -#define vfrec7_v_f16mf4(...) __riscv_vfrec7_v_f16mf4(__VA_ARGS__) -#define vfrec7_v_f16mf2(...) __riscv_vfrec7_v_f16mf2(__VA_ARGS__) -#define vfrec7_v_f16m1(...) __riscv_vfrec7_v_f16m1(__VA_ARGS__) -#define vfrec7_v_f16m2(...) __riscv_vfrec7_v_f16m2(__VA_ARGS__) -#define vfrec7_v_f16m4(...) __riscv_vfrec7_v_f16m4(__VA_ARGS__) -#define vfrec7_v_f16m8(...) __riscv_vfrec7_v_f16m8(__VA_ARGS__) -#define vfrec7_v_f32mf2(...) __riscv_vfrec7_v_f32mf2(__VA_ARGS__) -#define vfrec7_v_f32m1(...) __riscv_vfrec7_v_f32m1(__VA_ARGS__) -#define vfrec7_v_f32m2(...) __riscv_vfrec7_v_f32m2(__VA_ARGS__) -#define vfrec7_v_f32m4(...) __riscv_vfrec7_v_f32m4(__VA_ARGS__) -#define vfrec7_v_f32m8(...) __riscv_vfrec7_v_f32m8(__VA_ARGS__) -#define vfrec7_v_f64m1(...) __riscv_vfrec7_v_f64m1(__VA_ARGS__) -#define vfrec7_v_f64m2(...) __riscv_vfrec7_v_f64m2(__VA_ARGS__) -#define vfrec7_v_f64m4(...) __riscv_vfrec7_v_f64m4(__VA_ARGS__) -#define vfrec7_v_f64m8(...) __riscv_vfrec7_v_f64m8(__VA_ARGS__) -// masked functions -#define vfrec7_v_f16mf4_m(...) __riscv_vfrec7_v_f16mf4_tumu(__VA_ARGS__) -#define vfrec7_v_f16mf2_m(...) __riscv_vfrec7_v_f16mf2_tumu(__VA_ARGS__) -#define vfrec7_v_f16m1_m(...) __riscv_vfrec7_v_f16m1_tumu(__VA_ARGS__) -#define vfrec7_v_f16m2_m(...) __riscv_vfrec7_v_f16m2_tumu(__VA_ARGS__) -#define vfrec7_v_f16m4_m(...) __riscv_vfrec7_v_f16m4_tumu(__VA_ARGS__) -#define vfrec7_v_f16m8_m(...) __riscv_vfrec7_v_f16m8_tumu(__VA_ARGS__) -#define vfrec7_v_f32mf2_m(...) __riscv_vfrec7_v_f32mf2_tumu(__VA_ARGS__) -#define vfrec7_v_f32m1_m(...) __riscv_vfrec7_v_f32m1_tumu(__VA_ARGS__) -#define vfrec7_v_f32m2_m(...) __riscv_vfrec7_v_f32m2_tumu(__VA_ARGS__) -#define vfrec7_v_f32m4_m(...) __riscv_vfrec7_v_f32m4_tumu(__VA_ARGS__) -#define vfrec7_v_f32m8_m(...) __riscv_vfrec7_v_f32m8_tumu(__VA_ARGS__) -#define vfrec7_v_f64m1_m(...) __riscv_vfrec7_v_f64m1_tumu(__VA_ARGS__) -#define vfrec7_v_f64m2_m(...) __riscv_vfrec7_v_f64m2_tumu(__VA_ARGS__) -#define vfrec7_v_f64m4_m(...) __riscv_vfrec7_v_f64m4_tumu(__VA_ARGS__) -#define vfrec7_v_f64m8_m(...) __riscv_vfrec7_v_f64m8_tumu(__VA_ARGS__) -#define vfmin_vv_f16mf4(...) __riscv_vfmin_vv_f16mf4(__VA_ARGS__) -#define vfmin_vf_f16mf4(...) __riscv_vfmin_vf_f16mf4(__VA_ARGS__) -#define vfmin_vv_f16mf2(...) __riscv_vfmin_vv_f16mf2(__VA_ARGS__) -#define vfmin_vf_f16mf2(...) __riscv_vfmin_vf_f16mf2(__VA_ARGS__) -#define vfmin_vv_f16m1(...) __riscv_vfmin_vv_f16m1(__VA_ARGS__) -#define vfmin_vf_f16m1(...) __riscv_vfmin_vf_f16m1(__VA_ARGS__) -#define vfmin_vv_f16m2(...) __riscv_vfmin_vv_f16m2(__VA_ARGS__) -#define vfmin_vf_f16m2(...) __riscv_vfmin_vf_f16m2(__VA_ARGS__) -#define vfmin_vv_f16m4(...) __riscv_vfmin_vv_f16m4(__VA_ARGS__) -#define vfmin_vf_f16m4(...) __riscv_vfmin_vf_f16m4(__VA_ARGS__) -#define vfmin_vv_f16m8(...) __riscv_vfmin_vv_f16m8(__VA_ARGS__) -#define vfmin_vf_f16m8(...) __riscv_vfmin_vf_f16m8(__VA_ARGS__) -#define vfmin_vv_f32mf2(...) __riscv_vfmin_vv_f32mf2(__VA_ARGS__) -#define vfmin_vf_f32mf2(...) __riscv_vfmin_vf_f32mf2(__VA_ARGS__) -#define vfmin_vv_f32m1(...) __riscv_vfmin_vv_f32m1(__VA_ARGS__) -#define vfmin_vf_f32m1(...) __riscv_vfmin_vf_f32m1(__VA_ARGS__) -#define vfmin_vv_f32m2(...) __riscv_vfmin_vv_f32m2(__VA_ARGS__) -#define vfmin_vf_f32m2(...) __riscv_vfmin_vf_f32m2(__VA_ARGS__) -#define vfmin_vv_f32m4(...) __riscv_vfmin_vv_f32m4(__VA_ARGS__) -#define vfmin_vf_f32m4(...) __riscv_vfmin_vf_f32m4(__VA_ARGS__) -#define vfmin_vv_f32m8(...) __riscv_vfmin_vv_f32m8(__VA_ARGS__) -#define vfmin_vf_f32m8(...) __riscv_vfmin_vf_f32m8(__VA_ARGS__) -#define vfmin_vv_f64m1(...) __riscv_vfmin_vv_f64m1(__VA_ARGS__) -#define vfmin_vf_f64m1(...) __riscv_vfmin_vf_f64m1(__VA_ARGS__) -#define vfmin_vv_f64m2(...) __riscv_vfmin_vv_f64m2(__VA_ARGS__) -#define vfmin_vf_f64m2(...) __riscv_vfmin_vf_f64m2(__VA_ARGS__) -#define vfmin_vv_f64m4(...) __riscv_vfmin_vv_f64m4(__VA_ARGS__) -#define vfmin_vf_f64m4(...) __riscv_vfmin_vf_f64m4(__VA_ARGS__) -#define vfmin_vv_f64m8(...) __riscv_vfmin_vv_f64m8(__VA_ARGS__) -#define vfmin_vf_f64m8(...) __riscv_vfmin_vf_f64m8(__VA_ARGS__) -#define vfmax_vv_f16mf4(...) __riscv_vfmax_vv_f16mf4(__VA_ARGS__) -#define vfmax_vf_f16mf4(...) __riscv_vfmax_vf_f16mf4(__VA_ARGS__) -#define vfmax_vv_f16mf2(...) __riscv_vfmax_vv_f16mf2(__VA_ARGS__) -#define vfmax_vf_f16mf2(...) __riscv_vfmax_vf_f16mf2(__VA_ARGS__) -#define vfmax_vv_f16m1(...) __riscv_vfmax_vv_f16m1(__VA_ARGS__) -#define vfmax_vf_f16m1(...) __riscv_vfmax_vf_f16m1(__VA_ARGS__) -#define vfmax_vv_f16m2(...) __riscv_vfmax_vv_f16m2(__VA_ARGS__) -#define vfmax_vf_f16m2(...) __riscv_vfmax_vf_f16m2(__VA_ARGS__) -#define vfmax_vv_f16m4(...) __riscv_vfmax_vv_f16m4(__VA_ARGS__) -#define vfmax_vf_f16m4(...) __riscv_vfmax_vf_f16m4(__VA_ARGS__) -#define vfmax_vv_f16m8(...) __riscv_vfmax_vv_f16m8(__VA_ARGS__) -#define vfmax_vf_f16m8(...) __riscv_vfmax_vf_f16m8(__VA_ARGS__) -#define vfmax_vv_f32mf2(...) __riscv_vfmax_vv_f32mf2(__VA_ARGS__) -#define vfmax_vf_f32mf2(...) __riscv_vfmax_vf_f32mf2(__VA_ARGS__) -#define vfmax_vv_f32m1(...) __riscv_vfmax_vv_f32m1(__VA_ARGS__) -#define vfmax_vf_f32m1(...) __riscv_vfmax_vf_f32m1(__VA_ARGS__) -#define vfmax_vv_f32m2(...) __riscv_vfmax_vv_f32m2(__VA_ARGS__) -#define vfmax_vf_f32m2(...) __riscv_vfmax_vf_f32m2(__VA_ARGS__) -#define vfmax_vv_f32m4(...) __riscv_vfmax_vv_f32m4(__VA_ARGS__) -#define vfmax_vf_f32m4(...) __riscv_vfmax_vf_f32m4(__VA_ARGS__) -#define vfmax_vv_f32m8(...) __riscv_vfmax_vv_f32m8(__VA_ARGS__) -#define vfmax_vf_f32m8(...) __riscv_vfmax_vf_f32m8(__VA_ARGS__) -#define vfmax_vv_f64m1(...) __riscv_vfmax_vv_f64m1(__VA_ARGS__) -#define vfmax_vf_f64m1(...) __riscv_vfmax_vf_f64m1(__VA_ARGS__) -#define vfmax_vv_f64m2(...) __riscv_vfmax_vv_f64m2(__VA_ARGS__) -#define vfmax_vf_f64m2(...) __riscv_vfmax_vf_f64m2(__VA_ARGS__) -#define vfmax_vv_f64m4(...) __riscv_vfmax_vv_f64m4(__VA_ARGS__) -#define vfmax_vf_f64m4(...) __riscv_vfmax_vf_f64m4(__VA_ARGS__) -#define vfmax_vv_f64m8(...) __riscv_vfmax_vv_f64m8(__VA_ARGS__) -#define vfmax_vf_f64m8(...) __riscv_vfmax_vf_f64m8(__VA_ARGS__) -// masked functions -#define vfmin_vv_f16mf4_m(...) __riscv_vfmin_vv_f16mf4_tumu(__VA_ARGS__) -#define vfmin_vf_f16mf4_m(...) __riscv_vfmin_vf_f16mf4_tumu(__VA_ARGS__) -#define vfmin_vv_f16mf2_m(...) __riscv_vfmin_vv_f16mf2_tumu(__VA_ARGS__) -#define vfmin_vf_f16mf2_m(...) __riscv_vfmin_vf_f16mf2_tumu(__VA_ARGS__) -#define vfmin_vv_f16m1_m(...) __riscv_vfmin_vv_f16m1_tumu(__VA_ARGS__) -#define vfmin_vf_f16m1_m(...) __riscv_vfmin_vf_f16m1_tumu(__VA_ARGS__) -#define vfmin_vv_f16m2_m(...) __riscv_vfmin_vv_f16m2_tumu(__VA_ARGS__) -#define vfmin_vf_f16m2_m(...) __riscv_vfmin_vf_f16m2_tumu(__VA_ARGS__) -#define vfmin_vv_f16m4_m(...) __riscv_vfmin_vv_f16m4_tumu(__VA_ARGS__) -#define vfmin_vf_f16m4_m(...) __riscv_vfmin_vf_f16m4_tumu(__VA_ARGS__) -#define vfmin_vv_f16m8_m(...) __riscv_vfmin_vv_f16m8_tumu(__VA_ARGS__) -#define vfmin_vf_f16m8_m(...) __riscv_vfmin_vf_f16m8_tumu(__VA_ARGS__) -#define vfmin_vv_f32mf2_m(...) __riscv_vfmin_vv_f32mf2_tumu(__VA_ARGS__) -#define vfmin_vf_f32mf2_m(...) __riscv_vfmin_vf_f32mf2_tumu(__VA_ARGS__) -#define vfmin_vv_f32m1_m(...) __riscv_vfmin_vv_f32m1_tumu(__VA_ARGS__) -#define vfmin_vf_f32m1_m(...) __riscv_vfmin_vf_f32m1_tumu(__VA_ARGS__) -#define vfmin_vv_f32m2_m(...) __riscv_vfmin_vv_f32m2_tumu(__VA_ARGS__) -#define vfmin_vf_f32m2_m(...) __riscv_vfmin_vf_f32m2_tumu(__VA_ARGS__) -#define vfmin_vv_f32m4_m(...) __riscv_vfmin_vv_f32m4_tumu(__VA_ARGS__) -#define vfmin_vf_f32m4_m(...) __riscv_vfmin_vf_f32m4_tumu(__VA_ARGS__) -#define vfmin_vv_f32m8_m(...) __riscv_vfmin_vv_f32m8_tumu(__VA_ARGS__) -#define vfmin_vf_f32m8_m(...) __riscv_vfmin_vf_f32m8_tumu(__VA_ARGS__) -#define vfmin_vv_f64m1_m(...) __riscv_vfmin_vv_f64m1_tumu(__VA_ARGS__) -#define vfmin_vf_f64m1_m(...) __riscv_vfmin_vf_f64m1_tumu(__VA_ARGS__) -#define vfmin_vv_f64m2_m(...) __riscv_vfmin_vv_f64m2_tumu(__VA_ARGS__) -#define vfmin_vf_f64m2_m(...) __riscv_vfmin_vf_f64m2_tumu(__VA_ARGS__) -#define vfmin_vv_f64m4_m(...) __riscv_vfmin_vv_f64m4_tumu(__VA_ARGS__) -#define vfmin_vf_f64m4_m(...) __riscv_vfmin_vf_f64m4_tumu(__VA_ARGS__) -#define vfmin_vv_f64m8_m(...) __riscv_vfmin_vv_f64m8_tumu(__VA_ARGS__) -#define vfmin_vf_f64m8_m(...) __riscv_vfmin_vf_f64m8_tumu(__VA_ARGS__) -#define vfmax_vv_f16mf4_m(...) __riscv_vfmax_vv_f16mf4_tumu(__VA_ARGS__) -#define vfmax_vf_f16mf4_m(...) __riscv_vfmax_vf_f16mf4_tumu(__VA_ARGS__) -#define vfmax_vv_f16mf2_m(...) __riscv_vfmax_vv_f16mf2_tumu(__VA_ARGS__) -#define vfmax_vf_f16mf2_m(...) __riscv_vfmax_vf_f16mf2_tumu(__VA_ARGS__) -#define vfmax_vv_f16m1_m(...) __riscv_vfmax_vv_f16m1_tumu(__VA_ARGS__) -#define vfmax_vf_f16m1_m(...) __riscv_vfmax_vf_f16m1_tumu(__VA_ARGS__) -#define vfmax_vv_f16m2_m(...) __riscv_vfmax_vv_f16m2_tumu(__VA_ARGS__) -#define vfmax_vf_f16m2_m(...) __riscv_vfmax_vf_f16m2_tumu(__VA_ARGS__) -#define vfmax_vv_f16m4_m(...) __riscv_vfmax_vv_f16m4_tumu(__VA_ARGS__) -#define vfmax_vf_f16m4_m(...) __riscv_vfmax_vf_f16m4_tumu(__VA_ARGS__) -#define vfmax_vv_f16m8_m(...) __riscv_vfmax_vv_f16m8_tumu(__VA_ARGS__) -#define vfmax_vf_f16m8_m(...) __riscv_vfmax_vf_f16m8_tumu(__VA_ARGS__) -#define vfmax_vv_f32mf2_m(...) __riscv_vfmax_vv_f32mf2_tumu(__VA_ARGS__) -#define vfmax_vf_f32mf2_m(...) __riscv_vfmax_vf_f32mf2_tumu(__VA_ARGS__) -#define vfmax_vv_f32m1_m(...) __riscv_vfmax_vv_f32m1_tumu(__VA_ARGS__) -#define vfmax_vf_f32m1_m(...) __riscv_vfmax_vf_f32m1_tumu(__VA_ARGS__) -#define vfmax_vv_f32m2_m(...) __riscv_vfmax_vv_f32m2_tumu(__VA_ARGS__) -#define vfmax_vf_f32m2_m(...) __riscv_vfmax_vf_f32m2_tumu(__VA_ARGS__) -#define vfmax_vv_f32m4_m(...) __riscv_vfmax_vv_f32m4_tumu(__VA_ARGS__) -#define vfmax_vf_f32m4_m(...) __riscv_vfmax_vf_f32m4_tumu(__VA_ARGS__) -#define vfmax_vv_f32m8_m(...) __riscv_vfmax_vv_f32m8_tumu(__VA_ARGS__) -#define vfmax_vf_f32m8_m(...) __riscv_vfmax_vf_f32m8_tumu(__VA_ARGS__) -#define vfmax_vv_f64m1_m(...) __riscv_vfmax_vv_f64m1_tumu(__VA_ARGS__) -#define vfmax_vf_f64m1_m(...) __riscv_vfmax_vf_f64m1_tumu(__VA_ARGS__) -#define vfmax_vv_f64m2_m(...) __riscv_vfmax_vv_f64m2_tumu(__VA_ARGS__) -#define vfmax_vf_f64m2_m(...) __riscv_vfmax_vf_f64m2_tumu(__VA_ARGS__) -#define vfmax_vv_f64m4_m(...) __riscv_vfmax_vv_f64m4_tumu(__VA_ARGS__) -#define vfmax_vf_f64m4_m(...) __riscv_vfmax_vf_f64m4_tumu(__VA_ARGS__) -#define vfmax_vv_f64m8_m(...) __riscv_vfmax_vv_f64m8_tumu(__VA_ARGS__) -#define vfmax_vf_f64m8_m(...) __riscv_vfmax_vf_f64m8_tumu(__VA_ARGS__) -#define vfsgnj_vv_f16mf4(...) __riscv_vfsgnj_vv_f16mf4(__VA_ARGS__) -#define vfsgnj_vf_f16mf4(...) __riscv_vfsgnj_vf_f16mf4(__VA_ARGS__) -#define vfsgnj_vv_f16mf2(...) __riscv_vfsgnj_vv_f16mf2(__VA_ARGS__) -#define vfsgnj_vf_f16mf2(...) __riscv_vfsgnj_vf_f16mf2(__VA_ARGS__) -#define vfsgnj_vv_f16m1(...) __riscv_vfsgnj_vv_f16m1(__VA_ARGS__) -#define vfsgnj_vf_f16m1(...) __riscv_vfsgnj_vf_f16m1(__VA_ARGS__) -#define vfsgnj_vv_f16m2(...) __riscv_vfsgnj_vv_f16m2(__VA_ARGS__) -#define vfsgnj_vf_f16m2(...) __riscv_vfsgnj_vf_f16m2(__VA_ARGS__) -#define vfsgnj_vv_f16m4(...) __riscv_vfsgnj_vv_f16m4(__VA_ARGS__) -#define vfsgnj_vf_f16m4(...) __riscv_vfsgnj_vf_f16m4(__VA_ARGS__) -#define vfsgnj_vv_f16m8(...) __riscv_vfsgnj_vv_f16m8(__VA_ARGS__) -#define vfsgnj_vf_f16m8(...) __riscv_vfsgnj_vf_f16m8(__VA_ARGS__) -#define vfsgnj_vv_f32mf2(...) __riscv_vfsgnj_vv_f32mf2(__VA_ARGS__) -#define vfsgnj_vf_f32mf2(...) __riscv_vfsgnj_vf_f32mf2(__VA_ARGS__) -#define vfsgnj_vv_f32m1(...) __riscv_vfsgnj_vv_f32m1(__VA_ARGS__) -#define vfsgnj_vf_f32m1(...) __riscv_vfsgnj_vf_f32m1(__VA_ARGS__) -#define vfsgnj_vv_f32m2(...) __riscv_vfsgnj_vv_f32m2(__VA_ARGS__) -#define vfsgnj_vf_f32m2(...) __riscv_vfsgnj_vf_f32m2(__VA_ARGS__) -#define vfsgnj_vv_f32m4(...) __riscv_vfsgnj_vv_f32m4(__VA_ARGS__) -#define vfsgnj_vf_f32m4(...) __riscv_vfsgnj_vf_f32m4(__VA_ARGS__) -#define vfsgnj_vv_f32m8(...) __riscv_vfsgnj_vv_f32m8(__VA_ARGS__) -#define vfsgnj_vf_f32m8(...) __riscv_vfsgnj_vf_f32m8(__VA_ARGS__) -#define vfsgnj_vv_f64m1(...) __riscv_vfsgnj_vv_f64m1(__VA_ARGS__) -#define vfsgnj_vf_f64m1(...) __riscv_vfsgnj_vf_f64m1(__VA_ARGS__) -#define vfsgnj_vv_f64m2(...) __riscv_vfsgnj_vv_f64m2(__VA_ARGS__) -#define vfsgnj_vf_f64m2(...) __riscv_vfsgnj_vf_f64m2(__VA_ARGS__) -#define vfsgnj_vv_f64m4(...) __riscv_vfsgnj_vv_f64m4(__VA_ARGS__) -#define vfsgnj_vf_f64m4(...) __riscv_vfsgnj_vf_f64m4(__VA_ARGS__) -#define vfsgnj_vv_f64m8(...) __riscv_vfsgnj_vv_f64m8(__VA_ARGS__) -#define vfsgnj_vf_f64m8(...) __riscv_vfsgnj_vf_f64m8(__VA_ARGS__) -#define vfsgnjn_vv_f16mf4(...) __riscv_vfsgnjn_vv_f16mf4(__VA_ARGS__) -#define vfsgnjn_vf_f16mf4(...) __riscv_vfsgnjn_vf_f16mf4(__VA_ARGS__) -#define vfsgnjn_vv_f16mf2(...) __riscv_vfsgnjn_vv_f16mf2(__VA_ARGS__) -#define vfsgnjn_vf_f16mf2(...) __riscv_vfsgnjn_vf_f16mf2(__VA_ARGS__) -#define vfsgnjn_vv_f16m1(...) __riscv_vfsgnjn_vv_f16m1(__VA_ARGS__) -#define vfsgnjn_vf_f16m1(...) __riscv_vfsgnjn_vf_f16m1(__VA_ARGS__) -#define vfsgnjn_vv_f16m2(...) __riscv_vfsgnjn_vv_f16m2(__VA_ARGS__) -#define vfsgnjn_vf_f16m2(...) __riscv_vfsgnjn_vf_f16m2(__VA_ARGS__) -#define vfsgnjn_vv_f16m4(...) __riscv_vfsgnjn_vv_f16m4(__VA_ARGS__) -#define vfsgnjn_vf_f16m4(...) __riscv_vfsgnjn_vf_f16m4(__VA_ARGS__) -#define vfsgnjn_vv_f16m8(...) __riscv_vfsgnjn_vv_f16m8(__VA_ARGS__) -#define vfsgnjn_vf_f16m8(...) __riscv_vfsgnjn_vf_f16m8(__VA_ARGS__) -#define vfsgnjn_vv_f32mf2(...) __riscv_vfsgnjn_vv_f32mf2(__VA_ARGS__) -#define vfsgnjn_vf_f32mf2(...) __riscv_vfsgnjn_vf_f32mf2(__VA_ARGS__) -#define vfsgnjn_vv_f32m1(...) __riscv_vfsgnjn_vv_f32m1(__VA_ARGS__) -#define vfsgnjn_vf_f32m1(...) __riscv_vfsgnjn_vf_f32m1(__VA_ARGS__) -#define vfsgnjn_vv_f32m2(...) __riscv_vfsgnjn_vv_f32m2(__VA_ARGS__) -#define vfsgnjn_vf_f32m2(...) __riscv_vfsgnjn_vf_f32m2(__VA_ARGS__) -#define vfsgnjn_vv_f32m4(...) __riscv_vfsgnjn_vv_f32m4(__VA_ARGS__) -#define vfsgnjn_vf_f32m4(...) __riscv_vfsgnjn_vf_f32m4(__VA_ARGS__) -#define vfsgnjn_vv_f32m8(...) __riscv_vfsgnjn_vv_f32m8(__VA_ARGS__) -#define vfsgnjn_vf_f32m8(...) __riscv_vfsgnjn_vf_f32m8(__VA_ARGS__) -#define vfsgnjn_vv_f64m1(...) __riscv_vfsgnjn_vv_f64m1(__VA_ARGS__) -#define vfsgnjn_vf_f64m1(...) __riscv_vfsgnjn_vf_f64m1(__VA_ARGS__) -#define vfsgnjn_vv_f64m2(...) __riscv_vfsgnjn_vv_f64m2(__VA_ARGS__) -#define vfsgnjn_vf_f64m2(...) __riscv_vfsgnjn_vf_f64m2(__VA_ARGS__) -#define vfsgnjn_vv_f64m4(...) __riscv_vfsgnjn_vv_f64m4(__VA_ARGS__) -#define vfsgnjn_vf_f64m4(...) __riscv_vfsgnjn_vf_f64m4(__VA_ARGS__) -#define vfsgnjn_vv_f64m8(...) __riscv_vfsgnjn_vv_f64m8(__VA_ARGS__) -#define vfsgnjn_vf_f64m8(...) __riscv_vfsgnjn_vf_f64m8(__VA_ARGS__) -#define vfsgnjx_vv_f16mf4(...) __riscv_vfsgnjx_vv_f16mf4(__VA_ARGS__) -#define vfsgnjx_vf_f16mf4(...) __riscv_vfsgnjx_vf_f16mf4(__VA_ARGS__) -#define vfsgnjx_vv_f16mf2(...) __riscv_vfsgnjx_vv_f16mf2(__VA_ARGS__) -#define vfsgnjx_vf_f16mf2(...) __riscv_vfsgnjx_vf_f16mf2(__VA_ARGS__) -#define vfsgnjx_vv_f16m1(...) __riscv_vfsgnjx_vv_f16m1(__VA_ARGS__) -#define vfsgnjx_vf_f16m1(...) __riscv_vfsgnjx_vf_f16m1(__VA_ARGS__) -#define vfsgnjx_vv_f16m2(...) __riscv_vfsgnjx_vv_f16m2(__VA_ARGS__) -#define vfsgnjx_vf_f16m2(...) __riscv_vfsgnjx_vf_f16m2(__VA_ARGS__) -#define vfsgnjx_vv_f16m4(...) __riscv_vfsgnjx_vv_f16m4(__VA_ARGS__) -#define vfsgnjx_vf_f16m4(...) __riscv_vfsgnjx_vf_f16m4(__VA_ARGS__) -#define vfsgnjx_vv_f16m8(...) __riscv_vfsgnjx_vv_f16m8(__VA_ARGS__) -#define vfsgnjx_vf_f16m8(...) __riscv_vfsgnjx_vf_f16m8(__VA_ARGS__) -#define vfsgnjx_vv_f32mf2(...) __riscv_vfsgnjx_vv_f32mf2(__VA_ARGS__) -#define vfsgnjx_vf_f32mf2(...) __riscv_vfsgnjx_vf_f32mf2(__VA_ARGS__) -#define vfsgnjx_vv_f32m1(...) __riscv_vfsgnjx_vv_f32m1(__VA_ARGS__) -#define vfsgnjx_vf_f32m1(...) __riscv_vfsgnjx_vf_f32m1(__VA_ARGS__) -#define vfsgnjx_vv_f32m2(...) __riscv_vfsgnjx_vv_f32m2(__VA_ARGS__) -#define vfsgnjx_vf_f32m2(...) __riscv_vfsgnjx_vf_f32m2(__VA_ARGS__) -#define vfsgnjx_vv_f32m4(...) __riscv_vfsgnjx_vv_f32m4(__VA_ARGS__) -#define vfsgnjx_vf_f32m4(...) __riscv_vfsgnjx_vf_f32m4(__VA_ARGS__) -#define vfsgnjx_vv_f32m8(...) __riscv_vfsgnjx_vv_f32m8(__VA_ARGS__) -#define vfsgnjx_vf_f32m8(...) __riscv_vfsgnjx_vf_f32m8(__VA_ARGS__) -#define vfsgnjx_vv_f64m1(...) __riscv_vfsgnjx_vv_f64m1(__VA_ARGS__) -#define vfsgnjx_vf_f64m1(...) __riscv_vfsgnjx_vf_f64m1(__VA_ARGS__) -#define vfsgnjx_vv_f64m2(...) __riscv_vfsgnjx_vv_f64m2(__VA_ARGS__) -#define vfsgnjx_vf_f64m2(...) __riscv_vfsgnjx_vf_f64m2(__VA_ARGS__) -#define vfsgnjx_vv_f64m4(...) __riscv_vfsgnjx_vv_f64m4(__VA_ARGS__) -#define vfsgnjx_vf_f64m4(...) __riscv_vfsgnjx_vf_f64m4(__VA_ARGS__) -#define vfsgnjx_vv_f64m8(...) __riscv_vfsgnjx_vv_f64m8(__VA_ARGS__) -#define vfsgnjx_vf_f64m8(...) __riscv_vfsgnjx_vf_f64m8(__VA_ARGS__) -// masked functions -#define vfsgnj_vv_f16mf4_m(...) __riscv_vfsgnj_vv_f16mf4_tumu(__VA_ARGS__) -#define vfsgnj_vf_f16mf4_m(...) __riscv_vfsgnj_vf_f16mf4_tumu(__VA_ARGS__) -#define vfsgnj_vv_f16mf2_m(...) __riscv_vfsgnj_vv_f16mf2_tumu(__VA_ARGS__) -#define vfsgnj_vf_f16mf2_m(...) __riscv_vfsgnj_vf_f16mf2_tumu(__VA_ARGS__) -#define vfsgnj_vv_f16m1_m(...) __riscv_vfsgnj_vv_f16m1_tumu(__VA_ARGS__) -#define vfsgnj_vf_f16m1_m(...) __riscv_vfsgnj_vf_f16m1_tumu(__VA_ARGS__) -#define vfsgnj_vv_f16m2_m(...) __riscv_vfsgnj_vv_f16m2_tumu(__VA_ARGS__) -#define vfsgnj_vf_f16m2_m(...) __riscv_vfsgnj_vf_f16m2_tumu(__VA_ARGS__) -#define vfsgnj_vv_f16m4_m(...) __riscv_vfsgnj_vv_f16m4_tumu(__VA_ARGS__) -#define vfsgnj_vf_f16m4_m(...) __riscv_vfsgnj_vf_f16m4_tumu(__VA_ARGS__) -#define vfsgnj_vv_f16m8_m(...) __riscv_vfsgnj_vv_f16m8_tumu(__VA_ARGS__) -#define vfsgnj_vf_f16m8_m(...) __riscv_vfsgnj_vf_f16m8_tumu(__VA_ARGS__) -#define vfsgnj_vv_f32mf2_m(...) __riscv_vfsgnj_vv_f32mf2_tumu(__VA_ARGS__) -#define vfsgnj_vf_f32mf2_m(...) __riscv_vfsgnj_vf_f32mf2_tumu(__VA_ARGS__) -#define vfsgnj_vv_f32m1_m(...) __riscv_vfsgnj_vv_f32m1_tumu(__VA_ARGS__) -#define vfsgnj_vf_f32m1_m(...) __riscv_vfsgnj_vf_f32m1_tumu(__VA_ARGS__) -#define vfsgnj_vv_f32m2_m(...) __riscv_vfsgnj_vv_f32m2_tumu(__VA_ARGS__) -#define vfsgnj_vf_f32m2_m(...) __riscv_vfsgnj_vf_f32m2_tumu(__VA_ARGS__) -#define vfsgnj_vv_f32m4_m(...) __riscv_vfsgnj_vv_f32m4_tumu(__VA_ARGS__) -#define vfsgnj_vf_f32m4_m(...) __riscv_vfsgnj_vf_f32m4_tumu(__VA_ARGS__) -#define vfsgnj_vv_f32m8_m(...) __riscv_vfsgnj_vv_f32m8_tumu(__VA_ARGS__) -#define vfsgnj_vf_f32m8_m(...) __riscv_vfsgnj_vf_f32m8_tumu(__VA_ARGS__) -#define vfsgnj_vv_f64m1_m(...) __riscv_vfsgnj_vv_f64m1_tumu(__VA_ARGS__) -#define vfsgnj_vf_f64m1_m(...) __riscv_vfsgnj_vf_f64m1_tumu(__VA_ARGS__) -#define vfsgnj_vv_f64m2_m(...) __riscv_vfsgnj_vv_f64m2_tumu(__VA_ARGS__) -#define vfsgnj_vf_f64m2_m(...) __riscv_vfsgnj_vf_f64m2_tumu(__VA_ARGS__) -#define vfsgnj_vv_f64m4_m(...) __riscv_vfsgnj_vv_f64m4_tumu(__VA_ARGS__) -#define vfsgnj_vf_f64m4_m(...) __riscv_vfsgnj_vf_f64m4_tumu(__VA_ARGS__) -#define vfsgnj_vv_f64m8_m(...) __riscv_vfsgnj_vv_f64m8_tumu(__VA_ARGS__) -#define vfsgnj_vf_f64m8_m(...) __riscv_vfsgnj_vf_f64m8_tumu(__VA_ARGS__) -#define vfsgnjn_vv_f16mf4_m(...) __riscv_vfsgnjn_vv_f16mf4_tumu(__VA_ARGS__) -#define vfsgnjn_vf_f16mf4_m(...) __riscv_vfsgnjn_vf_f16mf4_tumu(__VA_ARGS__) -#define vfsgnjn_vv_f16mf2_m(...) __riscv_vfsgnjn_vv_f16mf2_tumu(__VA_ARGS__) -#define vfsgnjn_vf_f16mf2_m(...) __riscv_vfsgnjn_vf_f16mf2_tumu(__VA_ARGS__) -#define vfsgnjn_vv_f16m1_m(...) __riscv_vfsgnjn_vv_f16m1_tumu(__VA_ARGS__) -#define vfsgnjn_vf_f16m1_m(...) __riscv_vfsgnjn_vf_f16m1_tumu(__VA_ARGS__) -#define vfsgnjn_vv_f16m2_m(...) __riscv_vfsgnjn_vv_f16m2_tumu(__VA_ARGS__) -#define vfsgnjn_vf_f16m2_m(...) __riscv_vfsgnjn_vf_f16m2_tumu(__VA_ARGS__) -#define vfsgnjn_vv_f16m4_m(...) __riscv_vfsgnjn_vv_f16m4_tumu(__VA_ARGS__) -#define vfsgnjn_vf_f16m4_m(...) __riscv_vfsgnjn_vf_f16m4_tumu(__VA_ARGS__) -#define vfsgnjn_vv_f16m8_m(...) __riscv_vfsgnjn_vv_f16m8_tumu(__VA_ARGS__) -#define vfsgnjn_vf_f16m8_m(...) __riscv_vfsgnjn_vf_f16m8_tumu(__VA_ARGS__) -#define vfsgnjn_vv_f32mf2_m(...) __riscv_vfsgnjn_vv_f32mf2_tumu(__VA_ARGS__) -#define vfsgnjn_vf_f32mf2_m(...) __riscv_vfsgnjn_vf_f32mf2_tumu(__VA_ARGS__) -#define vfsgnjn_vv_f32m1_m(...) __riscv_vfsgnjn_vv_f32m1_tumu(__VA_ARGS__) -#define vfsgnjn_vf_f32m1_m(...) __riscv_vfsgnjn_vf_f32m1_tumu(__VA_ARGS__) -#define vfsgnjn_vv_f32m2_m(...) __riscv_vfsgnjn_vv_f32m2_tumu(__VA_ARGS__) -#define vfsgnjn_vf_f32m2_m(...) __riscv_vfsgnjn_vf_f32m2_tumu(__VA_ARGS__) -#define vfsgnjn_vv_f32m4_m(...) __riscv_vfsgnjn_vv_f32m4_tumu(__VA_ARGS__) -#define vfsgnjn_vf_f32m4_m(...) __riscv_vfsgnjn_vf_f32m4_tumu(__VA_ARGS__) -#define vfsgnjn_vv_f32m8_m(...) __riscv_vfsgnjn_vv_f32m8_tumu(__VA_ARGS__) -#define vfsgnjn_vf_f32m8_m(...) __riscv_vfsgnjn_vf_f32m8_tumu(__VA_ARGS__) -#define vfsgnjn_vv_f64m1_m(...) __riscv_vfsgnjn_vv_f64m1_tumu(__VA_ARGS__) -#define vfsgnjn_vf_f64m1_m(...) __riscv_vfsgnjn_vf_f64m1_tumu(__VA_ARGS__) -#define vfsgnjn_vv_f64m2_m(...) __riscv_vfsgnjn_vv_f64m2_tumu(__VA_ARGS__) -#define vfsgnjn_vf_f64m2_m(...) __riscv_vfsgnjn_vf_f64m2_tumu(__VA_ARGS__) -#define vfsgnjn_vv_f64m4_m(...) __riscv_vfsgnjn_vv_f64m4_tumu(__VA_ARGS__) -#define vfsgnjn_vf_f64m4_m(...) __riscv_vfsgnjn_vf_f64m4_tumu(__VA_ARGS__) -#define vfsgnjn_vv_f64m8_m(...) __riscv_vfsgnjn_vv_f64m8_tumu(__VA_ARGS__) -#define vfsgnjn_vf_f64m8_m(...) __riscv_vfsgnjn_vf_f64m8_tumu(__VA_ARGS__) -#define vfsgnjx_vv_f16mf4_m(...) __riscv_vfsgnjx_vv_f16mf4_tumu(__VA_ARGS__) -#define vfsgnjx_vf_f16mf4_m(...) __riscv_vfsgnjx_vf_f16mf4_tumu(__VA_ARGS__) -#define vfsgnjx_vv_f16mf2_m(...) __riscv_vfsgnjx_vv_f16mf2_tumu(__VA_ARGS__) -#define vfsgnjx_vf_f16mf2_m(...) __riscv_vfsgnjx_vf_f16mf2_tumu(__VA_ARGS__) -#define vfsgnjx_vv_f16m1_m(...) __riscv_vfsgnjx_vv_f16m1_tumu(__VA_ARGS__) -#define vfsgnjx_vf_f16m1_m(...) __riscv_vfsgnjx_vf_f16m1_tumu(__VA_ARGS__) -#define vfsgnjx_vv_f16m2_m(...) __riscv_vfsgnjx_vv_f16m2_tumu(__VA_ARGS__) -#define vfsgnjx_vf_f16m2_m(...) __riscv_vfsgnjx_vf_f16m2_tumu(__VA_ARGS__) -#define vfsgnjx_vv_f16m4_m(...) __riscv_vfsgnjx_vv_f16m4_tumu(__VA_ARGS__) -#define vfsgnjx_vf_f16m4_m(...) __riscv_vfsgnjx_vf_f16m4_tumu(__VA_ARGS__) -#define vfsgnjx_vv_f16m8_m(...) __riscv_vfsgnjx_vv_f16m8_tumu(__VA_ARGS__) -#define vfsgnjx_vf_f16m8_m(...) __riscv_vfsgnjx_vf_f16m8_tumu(__VA_ARGS__) -#define vfsgnjx_vv_f32mf2_m(...) __riscv_vfsgnjx_vv_f32mf2_tumu(__VA_ARGS__) -#define vfsgnjx_vf_f32mf2_m(...) __riscv_vfsgnjx_vf_f32mf2_tumu(__VA_ARGS__) -#define vfsgnjx_vv_f32m1_m(...) __riscv_vfsgnjx_vv_f32m1_tumu(__VA_ARGS__) -#define vfsgnjx_vf_f32m1_m(...) __riscv_vfsgnjx_vf_f32m1_tumu(__VA_ARGS__) -#define vfsgnjx_vv_f32m2_m(...) __riscv_vfsgnjx_vv_f32m2_tumu(__VA_ARGS__) -#define vfsgnjx_vf_f32m2_m(...) __riscv_vfsgnjx_vf_f32m2_tumu(__VA_ARGS__) -#define vfsgnjx_vv_f32m4_m(...) __riscv_vfsgnjx_vv_f32m4_tumu(__VA_ARGS__) -#define vfsgnjx_vf_f32m4_m(...) __riscv_vfsgnjx_vf_f32m4_tumu(__VA_ARGS__) -#define vfsgnjx_vv_f32m8_m(...) __riscv_vfsgnjx_vv_f32m8_tumu(__VA_ARGS__) -#define vfsgnjx_vf_f32m8_m(...) __riscv_vfsgnjx_vf_f32m8_tumu(__VA_ARGS__) -#define vfsgnjx_vv_f64m1_m(...) __riscv_vfsgnjx_vv_f64m1_tumu(__VA_ARGS__) -#define vfsgnjx_vf_f64m1_m(...) __riscv_vfsgnjx_vf_f64m1_tumu(__VA_ARGS__) -#define vfsgnjx_vv_f64m2_m(...) __riscv_vfsgnjx_vv_f64m2_tumu(__VA_ARGS__) -#define vfsgnjx_vf_f64m2_m(...) __riscv_vfsgnjx_vf_f64m2_tumu(__VA_ARGS__) -#define vfsgnjx_vv_f64m4_m(...) __riscv_vfsgnjx_vv_f64m4_tumu(__VA_ARGS__) -#define vfsgnjx_vf_f64m4_m(...) __riscv_vfsgnjx_vf_f64m4_tumu(__VA_ARGS__) -#define vfsgnjx_vv_f64m8_m(...) __riscv_vfsgnjx_vv_f64m8_tumu(__VA_ARGS__) -#define vfsgnjx_vf_f64m8_m(...) __riscv_vfsgnjx_vf_f64m8_tumu(__VA_ARGS__) -#define vfabs_v_f16mf4(...) __riscv_vfabs_v_f16mf4(__VA_ARGS__) -#define vfabs_v_f16mf2(...) __riscv_vfabs_v_f16mf2(__VA_ARGS__) -#define vfabs_v_f16m1(...) __riscv_vfabs_v_f16m1(__VA_ARGS__) -#define vfabs_v_f16m2(...) __riscv_vfabs_v_f16m2(__VA_ARGS__) -#define vfabs_v_f16m4(...) __riscv_vfabs_v_f16m4(__VA_ARGS__) -#define vfabs_v_f16m8(...) __riscv_vfabs_v_f16m8(__VA_ARGS__) -#define vfabs_v_f32mf2(...) __riscv_vfabs_v_f32mf2(__VA_ARGS__) -#define vfabs_v_f32m1(...) __riscv_vfabs_v_f32m1(__VA_ARGS__) -#define vfabs_v_f32m2(...) __riscv_vfabs_v_f32m2(__VA_ARGS__) -#define vfabs_v_f32m4(...) __riscv_vfabs_v_f32m4(__VA_ARGS__) -#define vfabs_v_f32m8(...) __riscv_vfabs_v_f32m8(__VA_ARGS__) -#define vfabs_v_f64m1(...) __riscv_vfabs_v_f64m1(__VA_ARGS__) -#define vfabs_v_f64m2(...) __riscv_vfabs_v_f64m2(__VA_ARGS__) -#define vfabs_v_f64m4(...) __riscv_vfabs_v_f64m4(__VA_ARGS__) -#define vfabs_v_f64m8(...) __riscv_vfabs_v_f64m8(__VA_ARGS__) -// masked functions -#define vfabs_v_f16mf4_m(...) __riscv_vfabs_v_f16mf4_tumu(__VA_ARGS__) -#define vfabs_v_f16mf2_m(...) __riscv_vfabs_v_f16mf2_tumu(__VA_ARGS__) -#define vfabs_v_f16m1_m(...) __riscv_vfabs_v_f16m1_tumu(__VA_ARGS__) -#define vfabs_v_f16m2_m(...) __riscv_vfabs_v_f16m2_tumu(__VA_ARGS__) -#define vfabs_v_f16m4_m(...) __riscv_vfabs_v_f16m4_tumu(__VA_ARGS__) -#define vfabs_v_f16m8_m(...) __riscv_vfabs_v_f16m8_tumu(__VA_ARGS__) -#define vfabs_v_f32mf2_m(...) __riscv_vfabs_v_f32mf2_tumu(__VA_ARGS__) -#define vfabs_v_f32m1_m(...) __riscv_vfabs_v_f32m1_tumu(__VA_ARGS__) -#define vfabs_v_f32m2_m(...) __riscv_vfabs_v_f32m2_tumu(__VA_ARGS__) -#define vfabs_v_f32m4_m(...) __riscv_vfabs_v_f32m4_tumu(__VA_ARGS__) -#define vfabs_v_f32m8_m(...) __riscv_vfabs_v_f32m8_tumu(__VA_ARGS__) -#define vfabs_v_f64m1_m(...) __riscv_vfabs_v_f64m1_tumu(__VA_ARGS__) -#define vfabs_v_f64m2_m(...) __riscv_vfabs_v_f64m2_tumu(__VA_ARGS__) -#define vfabs_v_f64m4_m(...) __riscv_vfabs_v_f64m4_tumu(__VA_ARGS__) -#define vfabs_v_f64m8_m(...) __riscv_vfabs_v_f64m8_tumu(__VA_ARGS__) -#define vmfeq_vv_f16mf4_b64(...) __riscv_vmfeq_vv_f16mf4_b64(__VA_ARGS__) -#define vmfeq_vf_f16mf4_b64(...) __riscv_vmfeq_vf_f16mf4_b64(__VA_ARGS__) -#define vmfeq_vv_f16mf2_b32(...) __riscv_vmfeq_vv_f16mf2_b32(__VA_ARGS__) -#define vmfeq_vf_f16mf2_b32(...) __riscv_vmfeq_vf_f16mf2_b32(__VA_ARGS__) -#define vmfeq_vv_f16m1_b16(...) __riscv_vmfeq_vv_f16m1_b16(__VA_ARGS__) -#define vmfeq_vf_f16m1_b16(...) __riscv_vmfeq_vf_f16m1_b16(__VA_ARGS__) -#define vmfeq_vv_f16m2_b8(...) __riscv_vmfeq_vv_f16m2_b8(__VA_ARGS__) -#define vmfeq_vf_f16m2_b8(...) __riscv_vmfeq_vf_f16m2_b8(__VA_ARGS__) -#define vmfeq_vv_f16m4_b4(...) __riscv_vmfeq_vv_f16m4_b4(__VA_ARGS__) -#define vmfeq_vf_f16m4_b4(...) __riscv_vmfeq_vf_f16m4_b4(__VA_ARGS__) -#define vmfeq_vv_f16m8_b2(...) __riscv_vmfeq_vv_f16m8_b2(__VA_ARGS__) -#define vmfeq_vf_f16m8_b2(...) __riscv_vmfeq_vf_f16m8_b2(__VA_ARGS__) -#define vmfeq_vv_f32mf2_b64(...) __riscv_vmfeq_vv_f32mf2_b64(__VA_ARGS__) -#define vmfeq_vf_f32mf2_b64(...) __riscv_vmfeq_vf_f32mf2_b64(__VA_ARGS__) -#define vmfeq_vv_f32m1_b32(...) __riscv_vmfeq_vv_f32m1_b32(__VA_ARGS__) -#define vmfeq_vf_f32m1_b32(...) __riscv_vmfeq_vf_f32m1_b32(__VA_ARGS__) -#define vmfeq_vv_f32m2_b16(...) __riscv_vmfeq_vv_f32m2_b16(__VA_ARGS__) -#define vmfeq_vf_f32m2_b16(...) __riscv_vmfeq_vf_f32m2_b16(__VA_ARGS__) -#define vmfeq_vv_f32m4_b8(...) __riscv_vmfeq_vv_f32m4_b8(__VA_ARGS__) -#define vmfeq_vf_f32m4_b8(...) __riscv_vmfeq_vf_f32m4_b8(__VA_ARGS__) -#define vmfeq_vv_f32m8_b4(...) __riscv_vmfeq_vv_f32m8_b4(__VA_ARGS__) -#define vmfeq_vf_f32m8_b4(...) __riscv_vmfeq_vf_f32m8_b4(__VA_ARGS__) -#define vmfeq_vv_f64m1_b64(...) __riscv_vmfeq_vv_f64m1_b64(__VA_ARGS__) -#define vmfeq_vf_f64m1_b64(...) __riscv_vmfeq_vf_f64m1_b64(__VA_ARGS__) -#define vmfeq_vv_f64m2_b32(...) __riscv_vmfeq_vv_f64m2_b32(__VA_ARGS__) -#define vmfeq_vf_f64m2_b32(...) __riscv_vmfeq_vf_f64m2_b32(__VA_ARGS__) -#define vmfeq_vv_f64m4_b16(...) __riscv_vmfeq_vv_f64m4_b16(__VA_ARGS__) -#define vmfeq_vf_f64m4_b16(...) __riscv_vmfeq_vf_f64m4_b16(__VA_ARGS__) -#define vmfeq_vv_f64m8_b8(...) __riscv_vmfeq_vv_f64m8_b8(__VA_ARGS__) -#define vmfeq_vf_f64m8_b8(...) __riscv_vmfeq_vf_f64m8_b8(__VA_ARGS__) -#define vmfne_vv_f16mf4_b64(...) __riscv_vmfne_vv_f16mf4_b64(__VA_ARGS__) -#define vmfne_vf_f16mf4_b64(...) __riscv_vmfne_vf_f16mf4_b64(__VA_ARGS__) -#define vmfne_vv_f16mf2_b32(...) __riscv_vmfne_vv_f16mf2_b32(__VA_ARGS__) -#define vmfne_vf_f16mf2_b32(...) __riscv_vmfne_vf_f16mf2_b32(__VA_ARGS__) -#define vmfne_vv_f16m1_b16(...) __riscv_vmfne_vv_f16m1_b16(__VA_ARGS__) -#define vmfne_vf_f16m1_b16(...) __riscv_vmfne_vf_f16m1_b16(__VA_ARGS__) -#define vmfne_vv_f16m2_b8(...) __riscv_vmfne_vv_f16m2_b8(__VA_ARGS__) -#define vmfne_vf_f16m2_b8(...) __riscv_vmfne_vf_f16m2_b8(__VA_ARGS__) -#define vmfne_vv_f16m4_b4(...) __riscv_vmfne_vv_f16m4_b4(__VA_ARGS__) -#define vmfne_vf_f16m4_b4(...) __riscv_vmfne_vf_f16m4_b4(__VA_ARGS__) -#define vmfne_vv_f16m8_b2(...) __riscv_vmfne_vv_f16m8_b2(__VA_ARGS__) -#define vmfne_vf_f16m8_b2(...) __riscv_vmfne_vf_f16m8_b2(__VA_ARGS__) -#define vmfne_vv_f32mf2_b64(...) __riscv_vmfne_vv_f32mf2_b64(__VA_ARGS__) -#define vmfne_vf_f32mf2_b64(...) __riscv_vmfne_vf_f32mf2_b64(__VA_ARGS__) -#define vmfne_vv_f32m1_b32(...) __riscv_vmfne_vv_f32m1_b32(__VA_ARGS__) -#define vmfne_vf_f32m1_b32(...) __riscv_vmfne_vf_f32m1_b32(__VA_ARGS__) -#define vmfne_vv_f32m2_b16(...) __riscv_vmfne_vv_f32m2_b16(__VA_ARGS__) -#define vmfne_vf_f32m2_b16(...) __riscv_vmfne_vf_f32m2_b16(__VA_ARGS__) -#define vmfne_vv_f32m4_b8(...) __riscv_vmfne_vv_f32m4_b8(__VA_ARGS__) -#define vmfne_vf_f32m4_b8(...) __riscv_vmfne_vf_f32m4_b8(__VA_ARGS__) -#define vmfne_vv_f32m8_b4(...) __riscv_vmfne_vv_f32m8_b4(__VA_ARGS__) -#define vmfne_vf_f32m8_b4(...) __riscv_vmfne_vf_f32m8_b4(__VA_ARGS__) -#define vmfne_vv_f64m1_b64(...) __riscv_vmfne_vv_f64m1_b64(__VA_ARGS__) -#define vmfne_vf_f64m1_b64(...) __riscv_vmfne_vf_f64m1_b64(__VA_ARGS__) -#define vmfne_vv_f64m2_b32(...) __riscv_vmfne_vv_f64m2_b32(__VA_ARGS__) -#define vmfne_vf_f64m2_b32(...) __riscv_vmfne_vf_f64m2_b32(__VA_ARGS__) -#define vmfne_vv_f64m4_b16(...) __riscv_vmfne_vv_f64m4_b16(__VA_ARGS__) -#define vmfne_vf_f64m4_b16(...) __riscv_vmfne_vf_f64m4_b16(__VA_ARGS__) -#define vmfne_vv_f64m8_b8(...) __riscv_vmfne_vv_f64m8_b8(__VA_ARGS__) -#define vmfne_vf_f64m8_b8(...) __riscv_vmfne_vf_f64m8_b8(__VA_ARGS__) -#define vmflt_vv_f16mf4_b64(...) __riscv_vmflt_vv_f16mf4_b64(__VA_ARGS__) -#define vmflt_vf_f16mf4_b64(...) __riscv_vmflt_vf_f16mf4_b64(__VA_ARGS__) -#define vmflt_vv_f16mf2_b32(...) __riscv_vmflt_vv_f16mf2_b32(__VA_ARGS__) -#define vmflt_vf_f16mf2_b32(...) __riscv_vmflt_vf_f16mf2_b32(__VA_ARGS__) -#define vmflt_vv_f16m1_b16(...) __riscv_vmflt_vv_f16m1_b16(__VA_ARGS__) -#define vmflt_vf_f16m1_b16(...) __riscv_vmflt_vf_f16m1_b16(__VA_ARGS__) -#define vmflt_vv_f16m2_b8(...) __riscv_vmflt_vv_f16m2_b8(__VA_ARGS__) -#define vmflt_vf_f16m2_b8(...) __riscv_vmflt_vf_f16m2_b8(__VA_ARGS__) -#define vmflt_vv_f16m4_b4(...) __riscv_vmflt_vv_f16m4_b4(__VA_ARGS__) -#define vmflt_vf_f16m4_b4(...) __riscv_vmflt_vf_f16m4_b4(__VA_ARGS__) -#define vmflt_vv_f16m8_b2(...) __riscv_vmflt_vv_f16m8_b2(__VA_ARGS__) -#define vmflt_vf_f16m8_b2(...) __riscv_vmflt_vf_f16m8_b2(__VA_ARGS__) -#define vmflt_vv_f32mf2_b64(...) __riscv_vmflt_vv_f32mf2_b64(__VA_ARGS__) -#define vmflt_vf_f32mf2_b64(...) __riscv_vmflt_vf_f32mf2_b64(__VA_ARGS__) -#define vmflt_vv_f32m1_b32(...) __riscv_vmflt_vv_f32m1_b32(__VA_ARGS__) -#define vmflt_vf_f32m1_b32(...) __riscv_vmflt_vf_f32m1_b32(__VA_ARGS__) -#define vmflt_vv_f32m2_b16(...) __riscv_vmflt_vv_f32m2_b16(__VA_ARGS__) -#define vmflt_vf_f32m2_b16(...) __riscv_vmflt_vf_f32m2_b16(__VA_ARGS__) -#define vmflt_vv_f32m4_b8(...) __riscv_vmflt_vv_f32m4_b8(__VA_ARGS__) -#define vmflt_vf_f32m4_b8(...) __riscv_vmflt_vf_f32m4_b8(__VA_ARGS__) -#define vmflt_vv_f32m8_b4(...) __riscv_vmflt_vv_f32m8_b4(__VA_ARGS__) -#define vmflt_vf_f32m8_b4(...) __riscv_vmflt_vf_f32m8_b4(__VA_ARGS__) -#define vmflt_vv_f64m1_b64(...) __riscv_vmflt_vv_f64m1_b64(__VA_ARGS__) -#define vmflt_vf_f64m1_b64(...) __riscv_vmflt_vf_f64m1_b64(__VA_ARGS__) -#define vmflt_vv_f64m2_b32(...) __riscv_vmflt_vv_f64m2_b32(__VA_ARGS__) -#define vmflt_vf_f64m2_b32(...) __riscv_vmflt_vf_f64m2_b32(__VA_ARGS__) -#define vmflt_vv_f64m4_b16(...) __riscv_vmflt_vv_f64m4_b16(__VA_ARGS__) -#define vmflt_vf_f64m4_b16(...) __riscv_vmflt_vf_f64m4_b16(__VA_ARGS__) -#define vmflt_vv_f64m8_b8(...) __riscv_vmflt_vv_f64m8_b8(__VA_ARGS__) -#define vmflt_vf_f64m8_b8(...) __riscv_vmflt_vf_f64m8_b8(__VA_ARGS__) -#define vmfle_vv_f16mf4_b64(...) __riscv_vmfle_vv_f16mf4_b64(__VA_ARGS__) -#define vmfle_vf_f16mf4_b64(...) __riscv_vmfle_vf_f16mf4_b64(__VA_ARGS__) -#define vmfle_vv_f16mf2_b32(...) __riscv_vmfle_vv_f16mf2_b32(__VA_ARGS__) -#define vmfle_vf_f16mf2_b32(...) __riscv_vmfle_vf_f16mf2_b32(__VA_ARGS__) -#define vmfle_vv_f16m1_b16(...) __riscv_vmfle_vv_f16m1_b16(__VA_ARGS__) -#define vmfle_vf_f16m1_b16(...) __riscv_vmfle_vf_f16m1_b16(__VA_ARGS__) -#define vmfle_vv_f16m2_b8(...) __riscv_vmfle_vv_f16m2_b8(__VA_ARGS__) -#define vmfle_vf_f16m2_b8(...) __riscv_vmfle_vf_f16m2_b8(__VA_ARGS__) -#define vmfle_vv_f16m4_b4(...) __riscv_vmfle_vv_f16m4_b4(__VA_ARGS__) -#define vmfle_vf_f16m4_b4(...) __riscv_vmfle_vf_f16m4_b4(__VA_ARGS__) -#define vmfle_vv_f16m8_b2(...) __riscv_vmfle_vv_f16m8_b2(__VA_ARGS__) -#define vmfle_vf_f16m8_b2(...) __riscv_vmfle_vf_f16m8_b2(__VA_ARGS__) -#define vmfle_vv_f32mf2_b64(...) __riscv_vmfle_vv_f32mf2_b64(__VA_ARGS__) -#define vmfle_vf_f32mf2_b64(...) __riscv_vmfle_vf_f32mf2_b64(__VA_ARGS__) -#define vmfle_vv_f32m1_b32(...) __riscv_vmfle_vv_f32m1_b32(__VA_ARGS__) -#define vmfle_vf_f32m1_b32(...) __riscv_vmfle_vf_f32m1_b32(__VA_ARGS__) -#define vmfle_vv_f32m2_b16(...) __riscv_vmfle_vv_f32m2_b16(__VA_ARGS__) -#define vmfle_vf_f32m2_b16(...) __riscv_vmfle_vf_f32m2_b16(__VA_ARGS__) -#define vmfle_vv_f32m4_b8(...) __riscv_vmfle_vv_f32m4_b8(__VA_ARGS__) -#define vmfle_vf_f32m4_b8(...) __riscv_vmfle_vf_f32m4_b8(__VA_ARGS__) -#define vmfle_vv_f32m8_b4(...) __riscv_vmfle_vv_f32m8_b4(__VA_ARGS__) -#define vmfle_vf_f32m8_b4(...) __riscv_vmfle_vf_f32m8_b4(__VA_ARGS__) -#define vmfle_vv_f64m1_b64(...) __riscv_vmfle_vv_f64m1_b64(__VA_ARGS__) -#define vmfle_vf_f64m1_b64(...) __riscv_vmfle_vf_f64m1_b64(__VA_ARGS__) -#define vmfle_vv_f64m2_b32(...) __riscv_vmfle_vv_f64m2_b32(__VA_ARGS__) -#define vmfle_vf_f64m2_b32(...) __riscv_vmfle_vf_f64m2_b32(__VA_ARGS__) -#define vmfle_vv_f64m4_b16(...) __riscv_vmfle_vv_f64m4_b16(__VA_ARGS__) -#define vmfle_vf_f64m4_b16(...) __riscv_vmfle_vf_f64m4_b16(__VA_ARGS__) -#define vmfle_vv_f64m8_b8(...) __riscv_vmfle_vv_f64m8_b8(__VA_ARGS__) -#define vmfle_vf_f64m8_b8(...) __riscv_vmfle_vf_f64m8_b8(__VA_ARGS__) -#define vmfgt_vv_f16mf4_b64(...) __riscv_vmfgt_vv_f16mf4_b64(__VA_ARGS__) -#define vmfgt_vf_f16mf4_b64(...) __riscv_vmfgt_vf_f16mf4_b64(__VA_ARGS__) -#define vmfgt_vv_f16mf2_b32(...) __riscv_vmfgt_vv_f16mf2_b32(__VA_ARGS__) -#define vmfgt_vf_f16mf2_b32(...) __riscv_vmfgt_vf_f16mf2_b32(__VA_ARGS__) -#define vmfgt_vv_f16m1_b16(...) __riscv_vmfgt_vv_f16m1_b16(__VA_ARGS__) -#define vmfgt_vf_f16m1_b16(...) __riscv_vmfgt_vf_f16m1_b16(__VA_ARGS__) -#define vmfgt_vv_f16m2_b8(...) __riscv_vmfgt_vv_f16m2_b8(__VA_ARGS__) -#define vmfgt_vf_f16m2_b8(...) __riscv_vmfgt_vf_f16m2_b8(__VA_ARGS__) -#define vmfgt_vv_f16m4_b4(...) __riscv_vmfgt_vv_f16m4_b4(__VA_ARGS__) -#define vmfgt_vf_f16m4_b4(...) __riscv_vmfgt_vf_f16m4_b4(__VA_ARGS__) -#define vmfgt_vv_f16m8_b2(...) __riscv_vmfgt_vv_f16m8_b2(__VA_ARGS__) -#define vmfgt_vf_f16m8_b2(...) __riscv_vmfgt_vf_f16m8_b2(__VA_ARGS__) -#define vmfgt_vv_f32mf2_b64(...) __riscv_vmfgt_vv_f32mf2_b64(__VA_ARGS__) -#define vmfgt_vf_f32mf2_b64(...) __riscv_vmfgt_vf_f32mf2_b64(__VA_ARGS__) -#define vmfgt_vv_f32m1_b32(...) __riscv_vmfgt_vv_f32m1_b32(__VA_ARGS__) -#define vmfgt_vf_f32m1_b32(...) __riscv_vmfgt_vf_f32m1_b32(__VA_ARGS__) -#define vmfgt_vv_f32m2_b16(...) __riscv_vmfgt_vv_f32m2_b16(__VA_ARGS__) -#define vmfgt_vf_f32m2_b16(...) __riscv_vmfgt_vf_f32m2_b16(__VA_ARGS__) -#define vmfgt_vv_f32m4_b8(...) __riscv_vmfgt_vv_f32m4_b8(__VA_ARGS__) -#define vmfgt_vf_f32m4_b8(...) __riscv_vmfgt_vf_f32m4_b8(__VA_ARGS__) -#define vmfgt_vv_f32m8_b4(...) __riscv_vmfgt_vv_f32m8_b4(__VA_ARGS__) -#define vmfgt_vf_f32m8_b4(...) __riscv_vmfgt_vf_f32m8_b4(__VA_ARGS__) -#define vmfgt_vv_f64m1_b64(...) __riscv_vmfgt_vv_f64m1_b64(__VA_ARGS__) -#define vmfgt_vf_f64m1_b64(...) __riscv_vmfgt_vf_f64m1_b64(__VA_ARGS__) -#define vmfgt_vv_f64m2_b32(...) __riscv_vmfgt_vv_f64m2_b32(__VA_ARGS__) -#define vmfgt_vf_f64m2_b32(...) __riscv_vmfgt_vf_f64m2_b32(__VA_ARGS__) -#define vmfgt_vv_f64m4_b16(...) __riscv_vmfgt_vv_f64m4_b16(__VA_ARGS__) -#define vmfgt_vf_f64m4_b16(...) __riscv_vmfgt_vf_f64m4_b16(__VA_ARGS__) -#define vmfgt_vv_f64m8_b8(...) __riscv_vmfgt_vv_f64m8_b8(__VA_ARGS__) -#define vmfgt_vf_f64m8_b8(...) __riscv_vmfgt_vf_f64m8_b8(__VA_ARGS__) -#define vmfge_vv_f16mf4_b64(...) __riscv_vmfge_vv_f16mf4_b64(__VA_ARGS__) -#define vmfge_vf_f16mf4_b64(...) __riscv_vmfge_vf_f16mf4_b64(__VA_ARGS__) -#define vmfge_vv_f16mf2_b32(...) __riscv_vmfge_vv_f16mf2_b32(__VA_ARGS__) -#define vmfge_vf_f16mf2_b32(...) __riscv_vmfge_vf_f16mf2_b32(__VA_ARGS__) -#define vmfge_vv_f16m1_b16(...) __riscv_vmfge_vv_f16m1_b16(__VA_ARGS__) -#define vmfge_vf_f16m1_b16(...) __riscv_vmfge_vf_f16m1_b16(__VA_ARGS__) -#define vmfge_vv_f16m2_b8(...) __riscv_vmfge_vv_f16m2_b8(__VA_ARGS__) -#define vmfge_vf_f16m2_b8(...) __riscv_vmfge_vf_f16m2_b8(__VA_ARGS__) -#define vmfge_vv_f16m4_b4(...) __riscv_vmfge_vv_f16m4_b4(__VA_ARGS__) -#define vmfge_vf_f16m4_b4(...) __riscv_vmfge_vf_f16m4_b4(__VA_ARGS__) -#define vmfge_vv_f16m8_b2(...) __riscv_vmfge_vv_f16m8_b2(__VA_ARGS__) -#define vmfge_vf_f16m8_b2(...) __riscv_vmfge_vf_f16m8_b2(__VA_ARGS__) -#define vmfge_vv_f32mf2_b64(...) __riscv_vmfge_vv_f32mf2_b64(__VA_ARGS__) -#define vmfge_vf_f32mf2_b64(...) __riscv_vmfge_vf_f32mf2_b64(__VA_ARGS__) -#define vmfge_vv_f32m1_b32(...) __riscv_vmfge_vv_f32m1_b32(__VA_ARGS__) -#define vmfge_vf_f32m1_b32(...) __riscv_vmfge_vf_f32m1_b32(__VA_ARGS__) -#define vmfge_vv_f32m2_b16(...) __riscv_vmfge_vv_f32m2_b16(__VA_ARGS__) -#define vmfge_vf_f32m2_b16(...) __riscv_vmfge_vf_f32m2_b16(__VA_ARGS__) -#define vmfge_vv_f32m4_b8(...) __riscv_vmfge_vv_f32m4_b8(__VA_ARGS__) -#define vmfge_vf_f32m4_b8(...) __riscv_vmfge_vf_f32m4_b8(__VA_ARGS__) -#define vmfge_vv_f32m8_b4(...) __riscv_vmfge_vv_f32m8_b4(__VA_ARGS__) -#define vmfge_vf_f32m8_b4(...) __riscv_vmfge_vf_f32m8_b4(__VA_ARGS__) -#define vmfge_vv_f64m1_b64(...) __riscv_vmfge_vv_f64m1_b64(__VA_ARGS__) -#define vmfge_vf_f64m1_b64(...) __riscv_vmfge_vf_f64m1_b64(__VA_ARGS__) -#define vmfge_vv_f64m2_b32(...) __riscv_vmfge_vv_f64m2_b32(__VA_ARGS__) -#define vmfge_vf_f64m2_b32(...) __riscv_vmfge_vf_f64m2_b32(__VA_ARGS__) -#define vmfge_vv_f64m4_b16(...) __riscv_vmfge_vv_f64m4_b16(__VA_ARGS__) -#define vmfge_vf_f64m4_b16(...) __riscv_vmfge_vf_f64m4_b16(__VA_ARGS__) -#define vmfge_vv_f64m8_b8(...) __riscv_vmfge_vv_f64m8_b8(__VA_ARGS__) -#define vmfge_vf_f64m8_b8(...) __riscv_vmfge_vf_f64m8_b8(__VA_ARGS__) -// masked functions -#define vmfeq_vv_f16mf4_b64_m(...) __riscv_vmfeq_vv_f16mf4_b64_mu(__VA_ARGS__) -#define vmfeq_vf_f16mf4_b64_m(...) __riscv_vmfeq_vf_f16mf4_b64_mu(__VA_ARGS__) -#define vmfeq_vv_f16mf2_b32_m(...) __riscv_vmfeq_vv_f16mf2_b32_mu(__VA_ARGS__) -#define vmfeq_vf_f16mf2_b32_m(...) __riscv_vmfeq_vf_f16mf2_b32_mu(__VA_ARGS__) -#define vmfeq_vv_f16m1_b16_m(...) __riscv_vmfeq_vv_f16m1_b16_mu(__VA_ARGS__) -#define vmfeq_vf_f16m1_b16_m(...) __riscv_vmfeq_vf_f16m1_b16_mu(__VA_ARGS__) -#define vmfeq_vv_f16m2_b8_m(...) __riscv_vmfeq_vv_f16m2_b8_mu(__VA_ARGS__) -#define vmfeq_vf_f16m2_b8_m(...) __riscv_vmfeq_vf_f16m2_b8_mu(__VA_ARGS__) -#define vmfeq_vv_f16m4_b4_m(...) __riscv_vmfeq_vv_f16m4_b4_mu(__VA_ARGS__) -#define vmfeq_vf_f16m4_b4_m(...) __riscv_vmfeq_vf_f16m4_b4_mu(__VA_ARGS__) -#define vmfeq_vv_f16m8_b2_m(...) __riscv_vmfeq_vv_f16m8_b2_mu(__VA_ARGS__) -#define vmfeq_vf_f16m8_b2_m(...) __riscv_vmfeq_vf_f16m8_b2_mu(__VA_ARGS__) -#define vmfeq_vv_f32mf2_b64_m(...) __riscv_vmfeq_vv_f32mf2_b64_mu(__VA_ARGS__) -#define vmfeq_vf_f32mf2_b64_m(...) __riscv_vmfeq_vf_f32mf2_b64_mu(__VA_ARGS__) -#define vmfeq_vv_f32m1_b32_m(...) __riscv_vmfeq_vv_f32m1_b32_mu(__VA_ARGS__) -#define vmfeq_vf_f32m1_b32_m(...) __riscv_vmfeq_vf_f32m1_b32_mu(__VA_ARGS__) -#define vmfeq_vv_f32m2_b16_m(...) __riscv_vmfeq_vv_f32m2_b16_mu(__VA_ARGS__) -#define vmfeq_vf_f32m2_b16_m(...) __riscv_vmfeq_vf_f32m2_b16_mu(__VA_ARGS__) -#define vmfeq_vv_f32m4_b8_m(...) __riscv_vmfeq_vv_f32m4_b8_mu(__VA_ARGS__) -#define vmfeq_vf_f32m4_b8_m(...) __riscv_vmfeq_vf_f32m4_b8_mu(__VA_ARGS__) -#define vmfeq_vv_f32m8_b4_m(...) __riscv_vmfeq_vv_f32m8_b4_mu(__VA_ARGS__) -#define vmfeq_vf_f32m8_b4_m(...) __riscv_vmfeq_vf_f32m8_b4_mu(__VA_ARGS__) -#define vmfeq_vv_f64m1_b64_m(...) __riscv_vmfeq_vv_f64m1_b64_mu(__VA_ARGS__) -#define vmfeq_vf_f64m1_b64_m(...) __riscv_vmfeq_vf_f64m1_b64_mu(__VA_ARGS__) -#define vmfeq_vv_f64m2_b32_m(...) __riscv_vmfeq_vv_f64m2_b32_mu(__VA_ARGS__) -#define vmfeq_vf_f64m2_b32_m(...) __riscv_vmfeq_vf_f64m2_b32_mu(__VA_ARGS__) -#define vmfeq_vv_f64m4_b16_m(...) __riscv_vmfeq_vv_f64m4_b16_mu(__VA_ARGS__) -#define vmfeq_vf_f64m4_b16_m(...) __riscv_vmfeq_vf_f64m4_b16_mu(__VA_ARGS__) -#define vmfeq_vv_f64m8_b8_m(...) __riscv_vmfeq_vv_f64m8_b8_mu(__VA_ARGS__) -#define vmfeq_vf_f64m8_b8_m(...) __riscv_vmfeq_vf_f64m8_b8_mu(__VA_ARGS__) -#define vmfne_vv_f16mf4_b64_m(...) __riscv_vmfne_vv_f16mf4_b64_mu(__VA_ARGS__) -#define vmfne_vf_f16mf4_b64_m(...) __riscv_vmfne_vf_f16mf4_b64_mu(__VA_ARGS__) -#define vmfne_vv_f16mf2_b32_m(...) __riscv_vmfne_vv_f16mf2_b32_mu(__VA_ARGS__) -#define vmfne_vf_f16mf2_b32_m(...) __riscv_vmfne_vf_f16mf2_b32_mu(__VA_ARGS__) -#define vmfne_vv_f16m1_b16_m(...) __riscv_vmfne_vv_f16m1_b16_mu(__VA_ARGS__) -#define vmfne_vf_f16m1_b16_m(...) __riscv_vmfne_vf_f16m1_b16_mu(__VA_ARGS__) -#define vmfne_vv_f16m2_b8_m(...) __riscv_vmfne_vv_f16m2_b8_mu(__VA_ARGS__) -#define vmfne_vf_f16m2_b8_m(...) __riscv_vmfne_vf_f16m2_b8_mu(__VA_ARGS__) -#define vmfne_vv_f16m4_b4_m(...) __riscv_vmfne_vv_f16m4_b4_mu(__VA_ARGS__) -#define vmfne_vf_f16m4_b4_m(...) __riscv_vmfne_vf_f16m4_b4_mu(__VA_ARGS__) -#define vmfne_vv_f16m8_b2_m(...) __riscv_vmfne_vv_f16m8_b2_mu(__VA_ARGS__) -#define vmfne_vf_f16m8_b2_m(...) __riscv_vmfne_vf_f16m8_b2_mu(__VA_ARGS__) -#define vmfne_vv_f32mf2_b64_m(...) __riscv_vmfne_vv_f32mf2_b64_mu(__VA_ARGS__) -#define vmfne_vf_f32mf2_b64_m(...) __riscv_vmfne_vf_f32mf2_b64_mu(__VA_ARGS__) -#define vmfne_vv_f32m1_b32_m(...) __riscv_vmfne_vv_f32m1_b32_mu(__VA_ARGS__) -#define vmfne_vf_f32m1_b32_m(...) __riscv_vmfne_vf_f32m1_b32_mu(__VA_ARGS__) -#define vmfne_vv_f32m2_b16_m(...) __riscv_vmfne_vv_f32m2_b16_mu(__VA_ARGS__) -#define vmfne_vf_f32m2_b16_m(...) __riscv_vmfne_vf_f32m2_b16_mu(__VA_ARGS__) -#define vmfne_vv_f32m4_b8_m(...) __riscv_vmfne_vv_f32m4_b8_mu(__VA_ARGS__) -#define vmfne_vf_f32m4_b8_m(...) __riscv_vmfne_vf_f32m4_b8_mu(__VA_ARGS__) -#define vmfne_vv_f32m8_b4_m(...) __riscv_vmfne_vv_f32m8_b4_mu(__VA_ARGS__) -#define vmfne_vf_f32m8_b4_m(...) __riscv_vmfne_vf_f32m8_b4_mu(__VA_ARGS__) -#define vmfne_vv_f64m1_b64_m(...) __riscv_vmfne_vv_f64m1_b64_mu(__VA_ARGS__) -#define vmfne_vf_f64m1_b64_m(...) __riscv_vmfne_vf_f64m1_b64_mu(__VA_ARGS__) -#define vmfne_vv_f64m2_b32_m(...) __riscv_vmfne_vv_f64m2_b32_mu(__VA_ARGS__) -#define vmfne_vf_f64m2_b32_m(...) __riscv_vmfne_vf_f64m2_b32_mu(__VA_ARGS__) -#define vmfne_vv_f64m4_b16_m(...) __riscv_vmfne_vv_f64m4_b16_mu(__VA_ARGS__) -#define vmfne_vf_f64m4_b16_m(...) __riscv_vmfne_vf_f64m4_b16_mu(__VA_ARGS__) -#define vmfne_vv_f64m8_b8_m(...) __riscv_vmfne_vv_f64m8_b8_mu(__VA_ARGS__) -#define vmfne_vf_f64m8_b8_m(...) __riscv_vmfne_vf_f64m8_b8_mu(__VA_ARGS__) -#define vmflt_vv_f16mf4_b64_m(...) __riscv_vmflt_vv_f16mf4_b64_mu(__VA_ARGS__) -#define vmflt_vf_f16mf4_b64_m(...) __riscv_vmflt_vf_f16mf4_b64_mu(__VA_ARGS__) -#define vmflt_vv_f16mf2_b32_m(...) __riscv_vmflt_vv_f16mf2_b32_mu(__VA_ARGS__) -#define vmflt_vf_f16mf2_b32_m(...) __riscv_vmflt_vf_f16mf2_b32_mu(__VA_ARGS__) -#define vmflt_vv_f16m1_b16_m(...) __riscv_vmflt_vv_f16m1_b16_mu(__VA_ARGS__) -#define vmflt_vf_f16m1_b16_m(...) __riscv_vmflt_vf_f16m1_b16_mu(__VA_ARGS__) -#define vmflt_vv_f16m2_b8_m(...) __riscv_vmflt_vv_f16m2_b8_mu(__VA_ARGS__) -#define vmflt_vf_f16m2_b8_m(...) __riscv_vmflt_vf_f16m2_b8_mu(__VA_ARGS__) -#define vmflt_vv_f16m4_b4_m(...) __riscv_vmflt_vv_f16m4_b4_mu(__VA_ARGS__) -#define vmflt_vf_f16m4_b4_m(...) __riscv_vmflt_vf_f16m4_b4_mu(__VA_ARGS__) -#define vmflt_vv_f16m8_b2_m(...) __riscv_vmflt_vv_f16m8_b2_mu(__VA_ARGS__) -#define vmflt_vf_f16m8_b2_m(...) __riscv_vmflt_vf_f16m8_b2_mu(__VA_ARGS__) -#define vmflt_vv_f32mf2_b64_m(...) __riscv_vmflt_vv_f32mf2_b64_mu(__VA_ARGS__) -#define vmflt_vf_f32mf2_b64_m(...) __riscv_vmflt_vf_f32mf2_b64_mu(__VA_ARGS__) -#define vmflt_vv_f32m1_b32_m(...) __riscv_vmflt_vv_f32m1_b32_mu(__VA_ARGS__) -#define vmflt_vf_f32m1_b32_m(...) __riscv_vmflt_vf_f32m1_b32_mu(__VA_ARGS__) -#define vmflt_vv_f32m2_b16_m(...) __riscv_vmflt_vv_f32m2_b16_mu(__VA_ARGS__) -#define vmflt_vf_f32m2_b16_m(...) __riscv_vmflt_vf_f32m2_b16_mu(__VA_ARGS__) -#define vmflt_vv_f32m4_b8_m(...) __riscv_vmflt_vv_f32m4_b8_mu(__VA_ARGS__) -#define vmflt_vf_f32m4_b8_m(...) __riscv_vmflt_vf_f32m4_b8_mu(__VA_ARGS__) -#define vmflt_vv_f32m8_b4_m(...) __riscv_vmflt_vv_f32m8_b4_mu(__VA_ARGS__) -#define vmflt_vf_f32m8_b4_m(...) __riscv_vmflt_vf_f32m8_b4_mu(__VA_ARGS__) -#define vmflt_vv_f64m1_b64_m(...) __riscv_vmflt_vv_f64m1_b64_mu(__VA_ARGS__) -#define vmflt_vf_f64m1_b64_m(...) __riscv_vmflt_vf_f64m1_b64_mu(__VA_ARGS__) -#define vmflt_vv_f64m2_b32_m(...) __riscv_vmflt_vv_f64m2_b32_mu(__VA_ARGS__) -#define vmflt_vf_f64m2_b32_m(...) __riscv_vmflt_vf_f64m2_b32_mu(__VA_ARGS__) -#define vmflt_vv_f64m4_b16_m(...) __riscv_vmflt_vv_f64m4_b16_mu(__VA_ARGS__) -#define vmflt_vf_f64m4_b16_m(...) __riscv_vmflt_vf_f64m4_b16_mu(__VA_ARGS__) -#define vmflt_vv_f64m8_b8_m(...) __riscv_vmflt_vv_f64m8_b8_mu(__VA_ARGS__) -#define vmflt_vf_f64m8_b8_m(...) __riscv_vmflt_vf_f64m8_b8_mu(__VA_ARGS__) -#define vmfle_vv_f16mf4_b64_m(...) __riscv_vmfle_vv_f16mf4_b64_mu(__VA_ARGS__) -#define vmfle_vf_f16mf4_b64_m(...) __riscv_vmfle_vf_f16mf4_b64_mu(__VA_ARGS__) -#define vmfle_vv_f16mf2_b32_m(...) __riscv_vmfle_vv_f16mf2_b32_mu(__VA_ARGS__) -#define vmfle_vf_f16mf2_b32_m(...) __riscv_vmfle_vf_f16mf2_b32_mu(__VA_ARGS__) -#define vmfle_vv_f16m1_b16_m(...) __riscv_vmfle_vv_f16m1_b16_mu(__VA_ARGS__) -#define vmfle_vf_f16m1_b16_m(...) __riscv_vmfle_vf_f16m1_b16_mu(__VA_ARGS__) -#define vmfle_vv_f16m2_b8_m(...) __riscv_vmfle_vv_f16m2_b8_mu(__VA_ARGS__) -#define vmfle_vf_f16m2_b8_m(...) __riscv_vmfle_vf_f16m2_b8_mu(__VA_ARGS__) -#define vmfle_vv_f16m4_b4_m(...) __riscv_vmfle_vv_f16m4_b4_mu(__VA_ARGS__) -#define vmfle_vf_f16m4_b4_m(...) __riscv_vmfle_vf_f16m4_b4_mu(__VA_ARGS__) -#define vmfle_vv_f16m8_b2_m(...) __riscv_vmfle_vv_f16m8_b2_mu(__VA_ARGS__) -#define vmfle_vf_f16m8_b2_m(...) __riscv_vmfle_vf_f16m8_b2_mu(__VA_ARGS__) -#define vmfle_vv_f32mf2_b64_m(...) __riscv_vmfle_vv_f32mf2_b64_mu(__VA_ARGS__) -#define vmfle_vf_f32mf2_b64_m(...) __riscv_vmfle_vf_f32mf2_b64_mu(__VA_ARGS__) -#define vmfle_vv_f32m1_b32_m(...) __riscv_vmfle_vv_f32m1_b32_mu(__VA_ARGS__) -#define vmfle_vf_f32m1_b32_m(...) __riscv_vmfle_vf_f32m1_b32_mu(__VA_ARGS__) -#define vmfle_vv_f32m2_b16_m(...) __riscv_vmfle_vv_f32m2_b16_mu(__VA_ARGS__) -#define vmfle_vf_f32m2_b16_m(...) __riscv_vmfle_vf_f32m2_b16_mu(__VA_ARGS__) -#define vmfle_vv_f32m4_b8_m(...) __riscv_vmfle_vv_f32m4_b8_mu(__VA_ARGS__) -#define vmfle_vf_f32m4_b8_m(...) __riscv_vmfle_vf_f32m4_b8_mu(__VA_ARGS__) -#define vmfle_vv_f32m8_b4_m(...) __riscv_vmfle_vv_f32m8_b4_mu(__VA_ARGS__) -#define vmfle_vf_f32m8_b4_m(...) __riscv_vmfle_vf_f32m8_b4_mu(__VA_ARGS__) -#define vmfle_vv_f64m1_b64_m(...) __riscv_vmfle_vv_f64m1_b64_mu(__VA_ARGS__) -#define vmfle_vf_f64m1_b64_m(...) __riscv_vmfle_vf_f64m1_b64_mu(__VA_ARGS__) -#define vmfle_vv_f64m2_b32_m(...) __riscv_vmfle_vv_f64m2_b32_mu(__VA_ARGS__) -#define vmfle_vf_f64m2_b32_m(...) __riscv_vmfle_vf_f64m2_b32_mu(__VA_ARGS__) -#define vmfle_vv_f64m4_b16_m(...) __riscv_vmfle_vv_f64m4_b16_mu(__VA_ARGS__) -#define vmfle_vf_f64m4_b16_m(...) __riscv_vmfle_vf_f64m4_b16_mu(__VA_ARGS__) -#define vmfle_vv_f64m8_b8_m(...) __riscv_vmfle_vv_f64m8_b8_mu(__VA_ARGS__) -#define vmfle_vf_f64m8_b8_m(...) __riscv_vmfle_vf_f64m8_b8_mu(__VA_ARGS__) -#define vmfgt_vv_f16mf4_b64_m(...) __riscv_vmfgt_vv_f16mf4_b64_mu(__VA_ARGS__) -#define vmfgt_vf_f16mf4_b64_m(...) __riscv_vmfgt_vf_f16mf4_b64_mu(__VA_ARGS__) -#define vmfgt_vv_f16mf2_b32_m(...) __riscv_vmfgt_vv_f16mf2_b32_mu(__VA_ARGS__) -#define vmfgt_vf_f16mf2_b32_m(...) __riscv_vmfgt_vf_f16mf2_b32_mu(__VA_ARGS__) -#define vmfgt_vv_f16m1_b16_m(...) __riscv_vmfgt_vv_f16m1_b16_mu(__VA_ARGS__) -#define vmfgt_vf_f16m1_b16_m(...) __riscv_vmfgt_vf_f16m1_b16_mu(__VA_ARGS__) -#define vmfgt_vv_f16m2_b8_m(...) __riscv_vmfgt_vv_f16m2_b8_mu(__VA_ARGS__) -#define vmfgt_vf_f16m2_b8_m(...) __riscv_vmfgt_vf_f16m2_b8_mu(__VA_ARGS__) -#define vmfgt_vv_f16m4_b4_m(...) __riscv_vmfgt_vv_f16m4_b4_mu(__VA_ARGS__) -#define vmfgt_vf_f16m4_b4_m(...) __riscv_vmfgt_vf_f16m4_b4_mu(__VA_ARGS__) -#define vmfgt_vv_f16m8_b2_m(...) __riscv_vmfgt_vv_f16m8_b2_mu(__VA_ARGS__) -#define vmfgt_vf_f16m8_b2_m(...) __riscv_vmfgt_vf_f16m8_b2_mu(__VA_ARGS__) -#define vmfgt_vv_f32mf2_b64_m(...) __riscv_vmfgt_vv_f32mf2_b64_mu(__VA_ARGS__) -#define vmfgt_vf_f32mf2_b64_m(...) __riscv_vmfgt_vf_f32mf2_b64_mu(__VA_ARGS__) -#define vmfgt_vv_f32m1_b32_m(...) __riscv_vmfgt_vv_f32m1_b32_mu(__VA_ARGS__) -#define vmfgt_vf_f32m1_b32_m(...) __riscv_vmfgt_vf_f32m1_b32_mu(__VA_ARGS__) -#define vmfgt_vv_f32m2_b16_m(...) __riscv_vmfgt_vv_f32m2_b16_mu(__VA_ARGS__) -#define vmfgt_vf_f32m2_b16_m(...) __riscv_vmfgt_vf_f32m2_b16_mu(__VA_ARGS__) -#define vmfgt_vv_f32m4_b8_m(...) __riscv_vmfgt_vv_f32m4_b8_mu(__VA_ARGS__) -#define vmfgt_vf_f32m4_b8_m(...) __riscv_vmfgt_vf_f32m4_b8_mu(__VA_ARGS__) -#define vmfgt_vv_f32m8_b4_m(...) __riscv_vmfgt_vv_f32m8_b4_mu(__VA_ARGS__) -#define vmfgt_vf_f32m8_b4_m(...) __riscv_vmfgt_vf_f32m8_b4_mu(__VA_ARGS__) -#define vmfgt_vv_f64m1_b64_m(...) __riscv_vmfgt_vv_f64m1_b64_mu(__VA_ARGS__) -#define vmfgt_vf_f64m1_b64_m(...) __riscv_vmfgt_vf_f64m1_b64_mu(__VA_ARGS__) -#define vmfgt_vv_f64m2_b32_m(...) __riscv_vmfgt_vv_f64m2_b32_mu(__VA_ARGS__) -#define vmfgt_vf_f64m2_b32_m(...) __riscv_vmfgt_vf_f64m2_b32_mu(__VA_ARGS__) -#define vmfgt_vv_f64m4_b16_m(...) __riscv_vmfgt_vv_f64m4_b16_mu(__VA_ARGS__) -#define vmfgt_vf_f64m4_b16_m(...) __riscv_vmfgt_vf_f64m4_b16_mu(__VA_ARGS__) -#define vmfgt_vv_f64m8_b8_m(...) __riscv_vmfgt_vv_f64m8_b8_mu(__VA_ARGS__) -#define vmfgt_vf_f64m8_b8_m(...) __riscv_vmfgt_vf_f64m8_b8_mu(__VA_ARGS__) -#define vmfge_vv_f16mf4_b64_m(...) __riscv_vmfge_vv_f16mf4_b64_mu(__VA_ARGS__) -#define vmfge_vf_f16mf4_b64_m(...) __riscv_vmfge_vf_f16mf4_b64_mu(__VA_ARGS__) -#define vmfge_vv_f16mf2_b32_m(...) __riscv_vmfge_vv_f16mf2_b32_mu(__VA_ARGS__) -#define vmfge_vf_f16mf2_b32_m(...) __riscv_vmfge_vf_f16mf2_b32_mu(__VA_ARGS__) -#define vmfge_vv_f16m1_b16_m(...) __riscv_vmfge_vv_f16m1_b16_mu(__VA_ARGS__) -#define vmfge_vf_f16m1_b16_m(...) __riscv_vmfge_vf_f16m1_b16_mu(__VA_ARGS__) -#define vmfge_vv_f16m2_b8_m(...) __riscv_vmfge_vv_f16m2_b8_mu(__VA_ARGS__) -#define vmfge_vf_f16m2_b8_m(...) __riscv_vmfge_vf_f16m2_b8_mu(__VA_ARGS__) -#define vmfge_vv_f16m4_b4_m(...) __riscv_vmfge_vv_f16m4_b4_mu(__VA_ARGS__) -#define vmfge_vf_f16m4_b4_m(...) __riscv_vmfge_vf_f16m4_b4_mu(__VA_ARGS__) -#define vmfge_vv_f16m8_b2_m(...) __riscv_vmfge_vv_f16m8_b2_mu(__VA_ARGS__) -#define vmfge_vf_f16m8_b2_m(...) __riscv_vmfge_vf_f16m8_b2_mu(__VA_ARGS__) -#define vmfge_vv_f32mf2_b64_m(...) __riscv_vmfge_vv_f32mf2_b64_mu(__VA_ARGS__) -#define vmfge_vf_f32mf2_b64_m(...) __riscv_vmfge_vf_f32mf2_b64_mu(__VA_ARGS__) -#define vmfge_vv_f32m1_b32_m(...) __riscv_vmfge_vv_f32m1_b32_mu(__VA_ARGS__) -#define vmfge_vf_f32m1_b32_m(...) __riscv_vmfge_vf_f32m1_b32_mu(__VA_ARGS__) -#define vmfge_vv_f32m2_b16_m(...) __riscv_vmfge_vv_f32m2_b16_mu(__VA_ARGS__) -#define vmfge_vf_f32m2_b16_m(...) __riscv_vmfge_vf_f32m2_b16_mu(__VA_ARGS__) -#define vmfge_vv_f32m4_b8_m(...) __riscv_vmfge_vv_f32m4_b8_mu(__VA_ARGS__) -#define vmfge_vf_f32m4_b8_m(...) __riscv_vmfge_vf_f32m4_b8_mu(__VA_ARGS__) -#define vmfge_vv_f32m8_b4_m(...) __riscv_vmfge_vv_f32m8_b4_mu(__VA_ARGS__) -#define vmfge_vf_f32m8_b4_m(...) __riscv_vmfge_vf_f32m8_b4_mu(__VA_ARGS__) -#define vmfge_vv_f64m1_b64_m(...) __riscv_vmfge_vv_f64m1_b64_mu(__VA_ARGS__) -#define vmfge_vf_f64m1_b64_m(...) __riscv_vmfge_vf_f64m1_b64_mu(__VA_ARGS__) -#define vmfge_vv_f64m2_b32_m(...) __riscv_vmfge_vv_f64m2_b32_mu(__VA_ARGS__) -#define vmfge_vf_f64m2_b32_m(...) __riscv_vmfge_vf_f64m2_b32_mu(__VA_ARGS__) -#define vmfge_vv_f64m4_b16_m(...) __riscv_vmfge_vv_f64m4_b16_mu(__VA_ARGS__) -#define vmfge_vf_f64m4_b16_m(...) __riscv_vmfge_vf_f64m4_b16_mu(__VA_ARGS__) -#define vmfge_vv_f64m8_b8_m(...) __riscv_vmfge_vv_f64m8_b8_mu(__VA_ARGS__) -#define vmfge_vf_f64m8_b8_m(...) __riscv_vmfge_vf_f64m8_b8_mu(__VA_ARGS__) -#define vfclass_v_u16mf4(...) __riscv_vfclass_v_u16mf4(__VA_ARGS__) -#define vfclass_v_u16mf2(...) __riscv_vfclass_v_u16mf2(__VA_ARGS__) -#define vfclass_v_u16m1(...) __riscv_vfclass_v_u16m1(__VA_ARGS__) -#define vfclass_v_u16m2(...) __riscv_vfclass_v_u16m2(__VA_ARGS__) -#define vfclass_v_u16m4(...) __riscv_vfclass_v_u16m4(__VA_ARGS__) -#define vfclass_v_u16m8(...) __riscv_vfclass_v_u16m8(__VA_ARGS__) -#define vfclass_v_u32mf2(...) __riscv_vfclass_v_u32mf2(__VA_ARGS__) -#define vfclass_v_u32m1(...) __riscv_vfclass_v_u32m1(__VA_ARGS__) -#define vfclass_v_u32m2(...) __riscv_vfclass_v_u32m2(__VA_ARGS__) -#define vfclass_v_u32m4(...) __riscv_vfclass_v_u32m4(__VA_ARGS__) -#define vfclass_v_u32m8(...) __riscv_vfclass_v_u32m8(__VA_ARGS__) -#define vfclass_v_u64m1(...) __riscv_vfclass_v_u64m1(__VA_ARGS__) -#define vfclass_v_u64m2(...) __riscv_vfclass_v_u64m2(__VA_ARGS__) -#define vfclass_v_u64m4(...) __riscv_vfclass_v_u64m4(__VA_ARGS__) -#define vfclass_v_u64m8(...) __riscv_vfclass_v_u64m8(__VA_ARGS__) -// masked functions -#define vfclass_v_u16mf4_m(...) __riscv_vfclass_v_u16mf4_tumu(__VA_ARGS__) -#define vfclass_v_u16mf2_m(...) __riscv_vfclass_v_u16mf2_tumu(__VA_ARGS__) -#define vfclass_v_u16m1_m(...) __riscv_vfclass_v_u16m1_tumu(__VA_ARGS__) -#define vfclass_v_u16m2_m(...) __riscv_vfclass_v_u16m2_tumu(__VA_ARGS__) -#define vfclass_v_u16m4_m(...) __riscv_vfclass_v_u16m4_tumu(__VA_ARGS__) -#define vfclass_v_u16m8_m(...) __riscv_vfclass_v_u16m8_tumu(__VA_ARGS__) -#define vfclass_v_u32mf2_m(...) __riscv_vfclass_v_u32mf2_tumu(__VA_ARGS__) -#define vfclass_v_u32m1_m(...) __riscv_vfclass_v_u32m1_tumu(__VA_ARGS__) -#define vfclass_v_u32m2_m(...) __riscv_vfclass_v_u32m2_tumu(__VA_ARGS__) -#define vfclass_v_u32m4_m(...) __riscv_vfclass_v_u32m4_tumu(__VA_ARGS__) -#define vfclass_v_u32m8_m(...) __riscv_vfclass_v_u32m8_tumu(__VA_ARGS__) -#define vfclass_v_u64m1_m(...) __riscv_vfclass_v_u64m1_tumu(__VA_ARGS__) -#define vfclass_v_u64m2_m(...) __riscv_vfclass_v_u64m2_tumu(__VA_ARGS__) -#define vfclass_v_u64m4_m(...) __riscv_vfclass_v_u64m4_tumu(__VA_ARGS__) -#define vfclass_v_u64m8_m(...) __riscv_vfclass_v_u64m8_tumu(__VA_ARGS__) -#define vmerge_vvm_f16mf4(mask, op1, op2, vl) __riscv_vmerge_vvm_f16mf4((op1), (op2), (mask), (vl)) -#define vfmerge_vfm_f16mf4(mask, op1, op2, vl) __riscv_vfmerge_vfm_f16mf4((op1), (op2), (mask), (vl)) -#define vmerge_vvm_f16mf2(mask, op1, op2, vl) __riscv_vmerge_vvm_f16mf2((op1), (op2), (mask), (vl)) -#define vfmerge_vfm_f16mf2(mask, op1, op2, vl) __riscv_vfmerge_vfm_f16mf2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_f16m1(mask, op1, op2, vl) __riscv_vmerge_vvm_f16m1((op1), (op2), (mask), (vl)) -#define vfmerge_vfm_f16m1(mask, op1, op2, vl) __riscv_vfmerge_vfm_f16m1((op1), (op2), (mask), (vl)) -#define vmerge_vvm_f16m2(mask, op1, op2, vl) __riscv_vmerge_vvm_f16m2((op1), (op2), (mask), (vl)) -#define vfmerge_vfm_f16m2(mask, op1, op2, vl) __riscv_vfmerge_vfm_f16m2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_f16m4(mask, op1, op2, vl) __riscv_vmerge_vvm_f16m4((op1), (op2), (mask), (vl)) -#define vfmerge_vfm_f16m4(mask, op1, op2, vl) __riscv_vfmerge_vfm_f16m4((op1), (op2), (mask), (vl)) -#define vmerge_vvm_f16m8(mask, op1, op2, vl) __riscv_vmerge_vvm_f16m8((op1), (op2), (mask), (vl)) -#define vfmerge_vfm_f16m8(mask, op1, op2, vl) __riscv_vfmerge_vfm_f16m8((op1), (op2), (mask), (vl)) -#define vmerge_vvm_f32mf2(mask, op1, op2, vl) __riscv_vmerge_vvm_f32mf2((op1), (op2), (mask), (vl)) -#define vfmerge_vfm_f32mf2(mask, op1, op2, vl) __riscv_vfmerge_vfm_f32mf2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_f32m1(mask, op1, op2, vl) __riscv_vmerge_vvm_f32m1((op1), (op2), (mask), (vl)) -#define vfmerge_vfm_f32m1(mask, op1, op2, vl) __riscv_vfmerge_vfm_f32m1((op1), (op2), (mask), (vl)) -#define vmerge_vvm_f32m2(mask, op1, op2, vl) __riscv_vmerge_vvm_f32m2((op1), (op2), (mask), (vl)) -#define vfmerge_vfm_f32m2(mask, op1, op2, vl) __riscv_vfmerge_vfm_f32m2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_f32m4(mask, op1, op2, vl) __riscv_vmerge_vvm_f32m4((op1), (op2), (mask), (vl)) -#define vfmerge_vfm_f32m4(mask, op1, op2, vl) __riscv_vfmerge_vfm_f32m4((op1), (op2), (mask), (vl)) -#define vmerge_vvm_f32m8(mask, op1, op2, vl) __riscv_vmerge_vvm_f32m8((op1), (op2), (mask), (vl)) -#define vfmerge_vfm_f32m8(mask, op1, op2, vl) __riscv_vfmerge_vfm_f32m8((op1), (op2), (mask), (vl)) -#define vmerge_vvm_f64m1(mask, op1, op2, vl) __riscv_vmerge_vvm_f64m1((op1), (op2), (mask), (vl)) -#define vfmerge_vfm_f64m1(mask, op1, op2, vl) __riscv_vfmerge_vfm_f64m1((op1), (op2), (mask), (vl)) -#define vmerge_vvm_f64m2(mask, op1, op2, vl) __riscv_vmerge_vvm_f64m2((op1), (op2), (mask), (vl)) -#define vfmerge_vfm_f64m2(mask, op1, op2, vl) __riscv_vfmerge_vfm_f64m2((op1), (op2), (mask), (vl)) -#define vmerge_vvm_f64m4(mask, op1, op2, vl) __riscv_vmerge_vvm_f64m4((op1), (op2), (mask), (vl)) -#define vfmerge_vfm_f64m4(mask, op1, op2, vl) __riscv_vfmerge_vfm_f64m4((op1), (op2), (mask), (vl)) -#define vmerge_vvm_f64m8(mask, op1, op2, vl) __riscv_vmerge_vvm_f64m8((op1), (op2), (mask), (vl)) -#define vfmerge_vfm_f64m8(mask, op1, op2, vl) __riscv_vfmerge_vfm_f64m8((op1), (op2), (mask), (vl)) -#define vmv_v_v_f16mf4(...) __riscv_vmv_v_v_f16mf4(__VA_ARGS__) -#define vfmv_v_f_f16mf4(...) __riscv_vfmv_v_f_f16mf4(__VA_ARGS__) -#define vmv_v_v_f16mf2(...) __riscv_vmv_v_v_f16mf2(__VA_ARGS__) -#define vfmv_v_f_f16mf2(...) __riscv_vfmv_v_f_f16mf2(__VA_ARGS__) -#define vmv_v_v_f16m1(...) __riscv_vmv_v_v_f16m1(__VA_ARGS__) -#define vfmv_v_f_f16m1(...) __riscv_vfmv_v_f_f16m1(__VA_ARGS__) -#define vmv_v_v_f16m2(...) __riscv_vmv_v_v_f16m2(__VA_ARGS__) -#define vfmv_v_f_f16m2(...) __riscv_vfmv_v_f_f16m2(__VA_ARGS__) -#define vmv_v_v_f16m4(...) __riscv_vmv_v_v_f16m4(__VA_ARGS__) -#define vfmv_v_f_f16m4(...) __riscv_vfmv_v_f_f16m4(__VA_ARGS__) -#define vmv_v_v_f16m8(...) __riscv_vmv_v_v_f16m8(__VA_ARGS__) -#define vfmv_v_f_f16m8(...) __riscv_vfmv_v_f_f16m8(__VA_ARGS__) -#define vmv_v_v_f32mf2(...) __riscv_vmv_v_v_f32mf2(__VA_ARGS__) -#define vfmv_v_f_f32mf2(...) __riscv_vfmv_v_f_f32mf2(__VA_ARGS__) -#define vmv_v_v_f32m1(...) __riscv_vmv_v_v_f32m1(__VA_ARGS__) -#define vfmv_v_f_f32m1(...) __riscv_vfmv_v_f_f32m1(__VA_ARGS__) -#define vmv_v_v_f32m2(...) __riscv_vmv_v_v_f32m2(__VA_ARGS__) -#define vfmv_v_f_f32m2(...) __riscv_vfmv_v_f_f32m2(__VA_ARGS__) -#define vmv_v_v_f32m4(...) __riscv_vmv_v_v_f32m4(__VA_ARGS__) -#define vfmv_v_f_f32m4(...) __riscv_vfmv_v_f_f32m4(__VA_ARGS__) -#define vmv_v_v_f32m8(...) __riscv_vmv_v_v_f32m8(__VA_ARGS__) -#define vfmv_v_f_f32m8(...) __riscv_vfmv_v_f_f32m8(__VA_ARGS__) -#define vmv_v_v_f64m1(...) __riscv_vmv_v_v_f64m1(__VA_ARGS__) -#define vfmv_v_f_f64m1(...) __riscv_vfmv_v_f_f64m1(__VA_ARGS__) -#define vmv_v_v_f64m2(...) __riscv_vmv_v_v_f64m2(__VA_ARGS__) -#define vfmv_v_f_f64m2(...) __riscv_vfmv_v_f_f64m2(__VA_ARGS__) -#define vmv_v_v_f64m4(...) __riscv_vmv_v_v_f64m4(__VA_ARGS__) -#define vfmv_v_f_f64m4(...) __riscv_vfmv_v_f_f64m4(__VA_ARGS__) -#define vmv_v_v_f64m8(...) __riscv_vmv_v_v_f64m8(__VA_ARGS__) -#define vfmv_v_f_f64m8(...) __riscv_vfmv_v_f_f64m8(__VA_ARGS__) -#define vfcvt_x_f_v_i16mf4(...) __riscv_vfcvt_x_f_v_i16mf4(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i16mf4(...) __riscv_vfcvt_rtz_x_f_v_i16mf4(__VA_ARGS__) -#define vfcvt_x_f_v_i16mf2(...) __riscv_vfcvt_x_f_v_i16mf2(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i16mf2(...) __riscv_vfcvt_rtz_x_f_v_i16mf2(__VA_ARGS__) -#define vfcvt_x_f_v_i16m1(...) __riscv_vfcvt_x_f_v_i16m1(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i16m1(...) __riscv_vfcvt_rtz_x_f_v_i16m1(__VA_ARGS__) -#define vfcvt_x_f_v_i16m2(...) __riscv_vfcvt_x_f_v_i16m2(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i16m2(...) __riscv_vfcvt_rtz_x_f_v_i16m2(__VA_ARGS__) -#define vfcvt_x_f_v_i16m4(...) __riscv_vfcvt_x_f_v_i16m4(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i16m4(...) __riscv_vfcvt_rtz_x_f_v_i16m4(__VA_ARGS__) -#define vfcvt_x_f_v_i16m8(...) __riscv_vfcvt_x_f_v_i16m8(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i16m8(...) __riscv_vfcvt_rtz_x_f_v_i16m8(__VA_ARGS__) -#define vfcvt_xu_f_v_u16mf4(...) __riscv_vfcvt_xu_f_v_u16mf4(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u16mf4(...) __riscv_vfcvt_rtz_xu_f_v_u16mf4(__VA_ARGS__) -#define vfcvt_xu_f_v_u16mf2(...) __riscv_vfcvt_xu_f_v_u16mf2(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u16mf2(...) __riscv_vfcvt_rtz_xu_f_v_u16mf2(__VA_ARGS__) -#define vfcvt_xu_f_v_u16m1(...) __riscv_vfcvt_xu_f_v_u16m1(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u16m1(...) __riscv_vfcvt_rtz_xu_f_v_u16m1(__VA_ARGS__) -#define vfcvt_xu_f_v_u16m2(...) __riscv_vfcvt_xu_f_v_u16m2(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u16m2(...) __riscv_vfcvt_rtz_xu_f_v_u16m2(__VA_ARGS__) -#define vfcvt_xu_f_v_u16m4(...) __riscv_vfcvt_xu_f_v_u16m4(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u16m4(...) __riscv_vfcvt_rtz_xu_f_v_u16m4(__VA_ARGS__) -#define vfcvt_xu_f_v_u16m8(...) __riscv_vfcvt_xu_f_v_u16m8(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u16m8(...) __riscv_vfcvt_rtz_xu_f_v_u16m8(__VA_ARGS__) -#define vfcvt_f_x_v_f16mf4(...) __riscv_vfcvt_f_x_v_f16mf4(__VA_ARGS__) -#define vfcvt_f_x_v_f16mf2(...) __riscv_vfcvt_f_x_v_f16mf2(__VA_ARGS__) -#define vfcvt_f_x_v_f16m1(...) __riscv_vfcvt_f_x_v_f16m1(__VA_ARGS__) -#define vfcvt_f_x_v_f16m2(...) __riscv_vfcvt_f_x_v_f16m2(__VA_ARGS__) -#define vfcvt_f_x_v_f16m4(...) __riscv_vfcvt_f_x_v_f16m4(__VA_ARGS__) -#define vfcvt_f_x_v_f16m8(...) __riscv_vfcvt_f_x_v_f16m8(__VA_ARGS__) -#define vfcvt_f_xu_v_f16mf4(...) __riscv_vfcvt_f_xu_v_f16mf4(__VA_ARGS__) -#define vfcvt_f_xu_v_f16mf2(...) __riscv_vfcvt_f_xu_v_f16mf2(__VA_ARGS__) -#define vfcvt_f_xu_v_f16m1(...) __riscv_vfcvt_f_xu_v_f16m1(__VA_ARGS__) -#define vfcvt_f_xu_v_f16m2(...) __riscv_vfcvt_f_xu_v_f16m2(__VA_ARGS__) -#define vfcvt_f_xu_v_f16m4(...) __riscv_vfcvt_f_xu_v_f16m4(__VA_ARGS__) -#define vfcvt_f_xu_v_f16m8(...) __riscv_vfcvt_f_xu_v_f16m8(__VA_ARGS__) -#define vfcvt_x_f_v_i32mf2(...) __riscv_vfcvt_x_f_v_i32mf2(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i32mf2(...) __riscv_vfcvt_rtz_x_f_v_i32mf2(__VA_ARGS__) -#define vfcvt_x_f_v_i32m1(...) __riscv_vfcvt_x_f_v_i32m1(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i32m1(...) __riscv_vfcvt_rtz_x_f_v_i32m1(__VA_ARGS__) -#define vfcvt_x_f_v_i32m2(...) __riscv_vfcvt_x_f_v_i32m2(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i32m2(...) __riscv_vfcvt_rtz_x_f_v_i32m2(__VA_ARGS__) -#define vfcvt_x_f_v_i32m4(...) __riscv_vfcvt_x_f_v_i32m4(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i32m4(...) __riscv_vfcvt_rtz_x_f_v_i32m4(__VA_ARGS__) -#define vfcvt_x_f_v_i32m8(...) __riscv_vfcvt_x_f_v_i32m8(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i32m8(...) __riscv_vfcvt_rtz_x_f_v_i32m8(__VA_ARGS__) -#define vfcvt_xu_f_v_u32mf2(...) __riscv_vfcvt_xu_f_v_u32mf2(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u32mf2(...) __riscv_vfcvt_rtz_xu_f_v_u32mf2(__VA_ARGS__) -#define vfcvt_xu_f_v_u32m1(...) __riscv_vfcvt_xu_f_v_u32m1(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u32m1(...) __riscv_vfcvt_rtz_xu_f_v_u32m1(__VA_ARGS__) -#define vfcvt_xu_f_v_u32m2(...) __riscv_vfcvt_xu_f_v_u32m2(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u32m2(...) __riscv_vfcvt_rtz_xu_f_v_u32m2(__VA_ARGS__) -#define vfcvt_xu_f_v_u32m4(...) __riscv_vfcvt_xu_f_v_u32m4(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u32m4(...) __riscv_vfcvt_rtz_xu_f_v_u32m4(__VA_ARGS__) -#define vfcvt_xu_f_v_u32m8(...) __riscv_vfcvt_xu_f_v_u32m8(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u32m8(...) __riscv_vfcvt_rtz_xu_f_v_u32m8(__VA_ARGS__) -#define vfcvt_f_x_v_f32mf2(...) __riscv_vfcvt_f_x_v_f32mf2(__VA_ARGS__) -#define vfcvt_f_x_v_f32m1(...) __riscv_vfcvt_f_x_v_f32m1(__VA_ARGS__) -#define vfcvt_f_x_v_f32m2(...) __riscv_vfcvt_f_x_v_f32m2(__VA_ARGS__) -#define vfcvt_f_x_v_f32m4(...) __riscv_vfcvt_f_x_v_f32m4(__VA_ARGS__) -#define vfcvt_f_x_v_f32m8(...) __riscv_vfcvt_f_x_v_f32m8(__VA_ARGS__) -#define vfcvt_f_xu_v_f32mf2(...) __riscv_vfcvt_f_xu_v_f32mf2(__VA_ARGS__) -#define vfcvt_f_xu_v_f32m1(...) __riscv_vfcvt_f_xu_v_f32m1(__VA_ARGS__) -#define vfcvt_f_xu_v_f32m2(...) __riscv_vfcvt_f_xu_v_f32m2(__VA_ARGS__) -#define vfcvt_f_xu_v_f32m4(...) __riscv_vfcvt_f_xu_v_f32m4(__VA_ARGS__) -#define vfcvt_f_xu_v_f32m8(...) __riscv_vfcvt_f_xu_v_f32m8(__VA_ARGS__) -#define vfcvt_x_f_v_i64m1(...) __riscv_vfcvt_x_f_v_i64m1(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i64m1(...) __riscv_vfcvt_rtz_x_f_v_i64m1(__VA_ARGS__) -#define vfcvt_x_f_v_i64m2(...) __riscv_vfcvt_x_f_v_i64m2(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i64m2(...) __riscv_vfcvt_rtz_x_f_v_i64m2(__VA_ARGS__) -#define vfcvt_x_f_v_i64m4(...) __riscv_vfcvt_x_f_v_i64m4(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i64m4(...) __riscv_vfcvt_rtz_x_f_v_i64m4(__VA_ARGS__) -#define vfcvt_x_f_v_i64m8(...) __riscv_vfcvt_x_f_v_i64m8(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i64m8(...) __riscv_vfcvt_rtz_x_f_v_i64m8(__VA_ARGS__) -#define vfcvt_xu_f_v_u64m1(...) __riscv_vfcvt_xu_f_v_u64m1(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u64m1(...) __riscv_vfcvt_rtz_xu_f_v_u64m1(__VA_ARGS__) -#define vfcvt_xu_f_v_u64m2(...) __riscv_vfcvt_xu_f_v_u64m2(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u64m2(...) __riscv_vfcvt_rtz_xu_f_v_u64m2(__VA_ARGS__) -#define vfcvt_xu_f_v_u64m4(...) __riscv_vfcvt_xu_f_v_u64m4(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u64m4(...) __riscv_vfcvt_rtz_xu_f_v_u64m4(__VA_ARGS__) -#define vfcvt_xu_f_v_u64m8(...) __riscv_vfcvt_xu_f_v_u64m8(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u64m8(...) __riscv_vfcvt_rtz_xu_f_v_u64m8(__VA_ARGS__) -#define vfcvt_f_x_v_f64m1(...) __riscv_vfcvt_f_x_v_f64m1(__VA_ARGS__) -#define vfcvt_f_x_v_f64m2(...) __riscv_vfcvt_f_x_v_f64m2(__VA_ARGS__) -#define vfcvt_f_x_v_f64m4(...) __riscv_vfcvt_f_x_v_f64m4(__VA_ARGS__) -#define vfcvt_f_x_v_f64m8(...) __riscv_vfcvt_f_x_v_f64m8(__VA_ARGS__) -#define vfcvt_f_xu_v_f64m1(...) __riscv_vfcvt_f_xu_v_f64m1(__VA_ARGS__) -#define vfcvt_f_xu_v_f64m2(...) __riscv_vfcvt_f_xu_v_f64m2(__VA_ARGS__) -#define vfcvt_f_xu_v_f64m4(...) __riscv_vfcvt_f_xu_v_f64m4(__VA_ARGS__) -#define vfcvt_f_xu_v_f64m8(...) __riscv_vfcvt_f_xu_v_f64m8(__VA_ARGS__) -// masked functions -#define vfcvt_x_f_v_i16mf4_m(...) __riscv_vfcvt_x_f_v_i16mf4_tumu(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i16mf4_m(...) __riscv_vfcvt_rtz_x_f_v_i16mf4_tumu(__VA_ARGS__) -#define vfcvt_x_f_v_i16mf2_m(...) __riscv_vfcvt_x_f_v_i16mf2_tumu(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i16mf2_m(...) __riscv_vfcvt_rtz_x_f_v_i16mf2_tumu(__VA_ARGS__) -#define vfcvt_x_f_v_i16m1_m(...) __riscv_vfcvt_x_f_v_i16m1_tumu(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i16m1_m(...) __riscv_vfcvt_rtz_x_f_v_i16m1_tumu(__VA_ARGS__) -#define vfcvt_x_f_v_i16m2_m(...) __riscv_vfcvt_x_f_v_i16m2_tumu(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i16m2_m(...) __riscv_vfcvt_rtz_x_f_v_i16m2_tumu(__VA_ARGS__) -#define vfcvt_x_f_v_i16m4_m(...) __riscv_vfcvt_x_f_v_i16m4_tumu(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i16m4_m(...) __riscv_vfcvt_rtz_x_f_v_i16m4_tumu(__VA_ARGS__) -#define vfcvt_x_f_v_i16m8_m(...) __riscv_vfcvt_x_f_v_i16m8_tumu(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i16m8_m(...) __riscv_vfcvt_rtz_x_f_v_i16m8_tumu(__VA_ARGS__) -#define vfcvt_xu_f_v_u16mf4_m(...) __riscv_vfcvt_xu_f_v_u16mf4_tumu(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u16mf4_m(...) __riscv_vfcvt_rtz_xu_f_v_u16mf4_tumu(__VA_ARGS__) -#define vfcvt_xu_f_v_u16mf2_m(...) __riscv_vfcvt_xu_f_v_u16mf2_tumu(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u16mf2_m(...) __riscv_vfcvt_rtz_xu_f_v_u16mf2_tumu(__VA_ARGS__) -#define vfcvt_xu_f_v_u16m1_m(...) __riscv_vfcvt_xu_f_v_u16m1_tumu(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u16m1_m(...) __riscv_vfcvt_rtz_xu_f_v_u16m1_tumu(__VA_ARGS__) -#define vfcvt_xu_f_v_u16m2_m(...) __riscv_vfcvt_xu_f_v_u16m2_tumu(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u16m2_m(...) __riscv_vfcvt_rtz_xu_f_v_u16m2_tumu(__VA_ARGS__) -#define vfcvt_xu_f_v_u16m4_m(...) __riscv_vfcvt_xu_f_v_u16m4_tumu(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u16m4_m(...) __riscv_vfcvt_rtz_xu_f_v_u16m4_tumu(__VA_ARGS__) -#define vfcvt_xu_f_v_u16m8_m(...) __riscv_vfcvt_xu_f_v_u16m8_tumu(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u16m8_m(...) __riscv_vfcvt_rtz_xu_f_v_u16m8_tumu(__VA_ARGS__) -#define vfcvt_f_x_v_f16mf4_m(...) __riscv_vfcvt_f_x_v_f16mf4_tumu(__VA_ARGS__) -#define vfcvt_f_x_v_f16mf2_m(...) __riscv_vfcvt_f_x_v_f16mf2_tumu(__VA_ARGS__) -#define vfcvt_f_x_v_f16m1_m(...) __riscv_vfcvt_f_x_v_f16m1_tumu(__VA_ARGS__) -#define vfcvt_f_x_v_f16m2_m(...) __riscv_vfcvt_f_x_v_f16m2_tumu(__VA_ARGS__) -#define vfcvt_f_x_v_f16m4_m(...) __riscv_vfcvt_f_x_v_f16m4_tumu(__VA_ARGS__) -#define vfcvt_f_x_v_f16m8_m(...) __riscv_vfcvt_f_x_v_f16m8_tumu(__VA_ARGS__) -#define vfcvt_f_xu_v_f16mf4_m(...) __riscv_vfcvt_f_xu_v_f16mf4_tumu(__VA_ARGS__) -#define vfcvt_f_xu_v_f16mf2_m(...) __riscv_vfcvt_f_xu_v_f16mf2_tumu(__VA_ARGS__) -#define vfcvt_f_xu_v_f16m1_m(...) __riscv_vfcvt_f_xu_v_f16m1_tumu(__VA_ARGS__) -#define vfcvt_f_xu_v_f16m2_m(...) __riscv_vfcvt_f_xu_v_f16m2_tumu(__VA_ARGS__) -#define vfcvt_f_xu_v_f16m4_m(...) __riscv_vfcvt_f_xu_v_f16m4_tumu(__VA_ARGS__) -#define vfcvt_f_xu_v_f16m8_m(...) __riscv_vfcvt_f_xu_v_f16m8_tumu(__VA_ARGS__) -#define vfcvt_x_f_v_i32mf2_m(...) __riscv_vfcvt_x_f_v_i32mf2_tumu(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i32mf2_m(...) __riscv_vfcvt_rtz_x_f_v_i32mf2_tumu(__VA_ARGS__) -#define vfcvt_x_f_v_i32m1_m(...) __riscv_vfcvt_x_f_v_i32m1_tumu(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i32m1_m(...) __riscv_vfcvt_rtz_x_f_v_i32m1_tumu(__VA_ARGS__) -#define vfcvt_x_f_v_i32m2_m(...) __riscv_vfcvt_x_f_v_i32m2_tumu(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i32m2_m(...) __riscv_vfcvt_rtz_x_f_v_i32m2_tumu(__VA_ARGS__) -#define vfcvt_x_f_v_i32m4_m(...) __riscv_vfcvt_x_f_v_i32m4_tumu(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i32m4_m(...) __riscv_vfcvt_rtz_x_f_v_i32m4_tumu(__VA_ARGS__) -#define vfcvt_x_f_v_i32m8_m(...) __riscv_vfcvt_x_f_v_i32m8_tumu(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i32m8_m(...) __riscv_vfcvt_rtz_x_f_v_i32m8_tumu(__VA_ARGS__) -#define vfcvt_xu_f_v_u32mf2_m(...) __riscv_vfcvt_xu_f_v_u32mf2_tumu(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u32mf2_m(...) __riscv_vfcvt_rtz_xu_f_v_u32mf2_tumu(__VA_ARGS__) -#define vfcvt_xu_f_v_u32m1_m(...) __riscv_vfcvt_xu_f_v_u32m1_tumu(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u32m1_m(...) __riscv_vfcvt_rtz_xu_f_v_u32m1_tumu(__VA_ARGS__) -#define vfcvt_xu_f_v_u32m2_m(...) __riscv_vfcvt_xu_f_v_u32m2_tumu(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u32m2_m(...) __riscv_vfcvt_rtz_xu_f_v_u32m2_tumu(__VA_ARGS__) -#define vfcvt_xu_f_v_u32m4_m(...) __riscv_vfcvt_xu_f_v_u32m4_tumu(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u32m4_m(...) __riscv_vfcvt_rtz_xu_f_v_u32m4_tumu(__VA_ARGS__) -#define vfcvt_xu_f_v_u32m8_m(...) __riscv_vfcvt_xu_f_v_u32m8_tumu(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u32m8_m(...) __riscv_vfcvt_rtz_xu_f_v_u32m8_tumu(__VA_ARGS__) -#define vfcvt_f_x_v_f32mf2_m(...) __riscv_vfcvt_f_x_v_f32mf2_tumu(__VA_ARGS__) -#define vfcvt_f_x_v_f32m1_m(...) __riscv_vfcvt_f_x_v_f32m1_tumu(__VA_ARGS__) -#define vfcvt_f_x_v_f32m2_m(...) __riscv_vfcvt_f_x_v_f32m2_tumu(__VA_ARGS__) -#define vfcvt_f_x_v_f32m4_m(...) __riscv_vfcvt_f_x_v_f32m4_tumu(__VA_ARGS__) -#define vfcvt_f_x_v_f32m8_m(...) __riscv_vfcvt_f_x_v_f32m8_tumu(__VA_ARGS__) -#define vfcvt_f_xu_v_f32mf2_m(...) __riscv_vfcvt_f_xu_v_f32mf2_tumu(__VA_ARGS__) -#define vfcvt_f_xu_v_f32m1_m(...) __riscv_vfcvt_f_xu_v_f32m1_tumu(__VA_ARGS__) -#define vfcvt_f_xu_v_f32m2_m(...) __riscv_vfcvt_f_xu_v_f32m2_tumu(__VA_ARGS__) -#define vfcvt_f_xu_v_f32m4_m(...) __riscv_vfcvt_f_xu_v_f32m4_tumu(__VA_ARGS__) -#define vfcvt_f_xu_v_f32m8_m(...) __riscv_vfcvt_f_xu_v_f32m8_tumu(__VA_ARGS__) -#define vfcvt_x_f_v_i64m1_m(...) __riscv_vfcvt_x_f_v_i64m1_tumu(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i64m1_m(...) __riscv_vfcvt_rtz_x_f_v_i64m1_tumu(__VA_ARGS__) -#define vfcvt_x_f_v_i64m2_m(...) __riscv_vfcvt_x_f_v_i64m2_tumu(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i64m2_m(...) __riscv_vfcvt_rtz_x_f_v_i64m2_tumu(__VA_ARGS__) -#define vfcvt_x_f_v_i64m4_m(...) __riscv_vfcvt_x_f_v_i64m4_tumu(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i64m4_m(...) __riscv_vfcvt_rtz_x_f_v_i64m4_tumu(__VA_ARGS__) -#define vfcvt_x_f_v_i64m8_m(...) __riscv_vfcvt_x_f_v_i64m8_tumu(__VA_ARGS__) -#define vfcvt_rtz_x_f_v_i64m8_m(...) __riscv_vfcvt_rtz_x_f_v_i64m8_tumu(__VA_ARGS__) -#define vfcvt_xu_f_v_u64m1_m(...) __riscv_vfcvt_xu_f_v_u64m1_tumu(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u64m1_m(...) __riscv_vfcvt_rtz_xu_f_v_u64m1_tumu(__VA_ARGS__) -#define vfcvt_xu_f_v_u64m2_m(...) __riscv_vfcvt_xu_f_v_u64m2_tumu(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u64m2_m(...) __riscv_vfcvt_rtz_xu_f_v_u64m2_tumu(__VA_ARGS__) -#define vfcvt_xu_f_v_u64m4_m(...) __riscv_vfcvt_xu_f_v_u64m4_tumu(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u64m4_m(...) __riscv_vfcvt_rtz_xu_f_v_u64m4_tumu(__VA_ARGS__) -#define vfcvt_xu_f_v_u64m8_m(...) __riscv_vfcvt_xu_f_v_u64m8_tumu(__VA_ARGS__) -#define vfcvt_rtz_xu_f_v_u64m8_m(...) __riscv_vfcvt_rtz_xu_f_v_u64m8_tumu(__VA_ARGS__) -#define vfcvt_f_x_v_f64m1_m(...) __riscv_vfcvt_f_x_v_f64m1_tumu(__VA_ARGS__) -#define vfcvt_f_x_v_f64m2_m(...) __riscv_vfcvt_f_x_v_f64m2_tumu(__VA_ARGS__) -#define vfcvt_f_x_v_f64m4_m(...) __riscv_vfcvt_f_x_v_f64m4_tumu(__VA_ARGS__) -#define vfcvt_f_x_v_f64m8_m(...) __riscv_vfcvt_f_x_v_f64m8_tumu(__VA_ARGS__) -#define vfcvt_f_xu_v_f64m1_m(...) __riscv_vfcvt_f_xu_v_f64m1_tumu(__VA_ARGS__) -#define vfcvt_f_xu_v_f64m2_m(...) __riscv_vfcvt_f_xu_v_f64m2_tumu(__VA_ARGS__) -#define vfcvt_f_xu_v_f64m4_m(...) __riscv_vfcvt_f_xu_v_f64m4_tumu(__VA_ARGS__) -#define vfcvt_f_xu_v_f64m8_m(...) __riscv_vfcvt_f_xu_v_f64m8_tumu(__VA_ARGS__) -#define vwcvt_x_x_v_i16mf4(...) __riscv_vwcvt_x_x_v_i16mf4(__VA_ARGS__) -#define vwcvt_x_x_v_i16mf2(...) __riscv_vwcvt_x_x_v_i16mf2(__VA_ARGS__) -#define vwcvt_x_x_v_i16m1(...) __riscv_vwcvt_x_x_v_i16m1(__VA_ARGS__) -#define vwcvt_x_x_v_i16m2(...) __riscv_vwcvt_x_x_v_i16m2(__VA_ARGS__) -#define vwcvt_x_x_v_i16m4(...) __riscv_vwcvt_x_x_v_i16m4(__VA_ARGS__) -#define vwcvt_x_x_v_i16m8(...) __riscv_vwcvt_x_x_v_i16m8(__VA_ARGS__) -#define vwcvtu_x_x_v_u16mf4(...) __riscv_vwcvtu_x_x_v_u16mf4(__VA_ARGS__) -#define vwcvtu_x_x_v_u16mf2(...) __riscv_vwcvtu_x_x_v_u16mf2(__VA_ARGS__) -#define vwcvtu_x_x_v_u16m1(...) __riscv_vwcvtu_x_x_v_u16m1(__VA_ARGS__) -#define vwcvtu_x_x_v_u16m2(...) __riscv_vwcvtu_x_x_v_u16m2(__VA_ARGS__) -#define vwcvtu_x_x_v_u16m4(...) __riscv_vwcvtu_x_x_v_u16m4(__VA_ARGS__) -#define vwcvtu_x_x_v_u16m8(...) __riscv_vwcvtu_x_x_v_u16m8(__VA_ARGS__) -#define vfwcvt_f_x_v_f16mf4(...) __riscv_vfwcvt_f_x_v_f16mf4(__VA_ARGS__) -#define vfwcvt_f_x_v_f16mf2(...) __riscv_vfwcvt_f_x_v_f16mf2(__VA_ARGS__) -#define vfwcvt_f_x_v_f16m1(...) __riscv_vfwcvt_f_x_v_f16m1(__VA_ARGS__) -#define vfwcvt_f_x_v_f16m2(...) __riscv_vfwcvt_f_x_v_f16m2(__VA_ARGS__) -#define vfwcvt_f_x_v_f16m4(...) __riscv_vfwcvt_f_x_v_f16m4(__VA_ARGS__) -#define vfwcvt_f_x_v_f16m8(...) __riscv_vfwcvt_f_x_v_f16m8(__VA_ARGS__) -#define vfwcvt_f_xu_v_f16mf4(...) __riscv_vfwcvt_f_xu_v_f16mf4(__VA_ARGS__) -#define vfwcvt_f_xu_v_f16mf2(...) __riscv_vfwcvt_f_xu_v_f16mf2(__VA_ARGS__) -#define vfwcvt_f_xu_v_f16m1(...) __riscv_vfwcvt_f_xu_v_f16m1(__VA_ARGS__) -#define vfwcvt_f_xu_v_f16m2(...) __riscv_vfwcvt_f_xu_v_f16m2(__VA_ARGS__) -#define vfwcvt_f_xu_v_f16m4(...) __riscv_vfwcvt_f_xu_v_f16m4(__VA_ARGS__) -#define vfwcvt_f_xu_v_f16m8(...) __riscv_vfwcvt_f_xu_v_f16m8(__VA_ARGS__) -#define vfwcvt_x_f_v_i32mf2(...) __riscv_vfwcvt_x_f_v_i32mf2(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i32mf2(...) __riscv_vfwcvt_rtz_x_f_v_i32mf2(__VA_ARGS__) -#define vfwcvt_x_f_v_i32m1(...) __riscv_vfwcvt_x_f_v_i32m1(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i32m1(...) __riscv_vfwcvt_rtz_x_f_v_i32m1(__VA_ARGS__) -#define vfwcvt_x_f_v_i32m2(...) __riscv_vfwcvt_x_f_v_i32m2(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i32m2(...) __riscv_vfwcvt_rtz_x_f_v_i32m2(__VA_ARGS__) -#define vfwcvt_x_f_v_i32m4(...) __riscv_vfwcvt_x_f_v_i32m4(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i32m4(...) __riscv_vfwcvt_rtz_x_f_v_i32m4(__VA_ARGS__) -#define vfwcvt_x_f_v_i32m8(...) __riscv_vfwcvt_x_f_v_i32m8(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i32m8(...) __riscv_vfwcvt_rtz_x_f_v_i32m8(__VA_ARGS__) -#define vwcvt_x_x_v_i32mf2(...) __riscv_vwcvt_x_x_v_i32mf2(__VA_ARGS__) -#define vwcvt_x_x_v_i32m1(...) __riscv_vwcvt_x_x_v_i32m1(__VA_ARGS__) -#define vwcvt_x_x_v_i32m2(...) __riscv_vwcvt_x_x_v_i32m2(__VA_ARGS__) -#define vwcvt_x_x_v_i32m4(...) __riscv_vwcvt_x_x_v_i32m4(__VA_ARGS__) -#define vwcvt_x_x_v_i32m8(...) __riscv_vwcvt_x_x_v_i32m8(__VA_ARGS__) -#define vwcvtu_x_x_v_u32mf2(...) __riscv_vwcvtu_x_x_v_u32mf2(__VA_ARGS__) -#define vwcvtu_x_x_v_u32m1(...) __riscv_vwcvtu_x_x_v_u32m1(__VA_ARGS__) -#define vwcvtu_x_x_v_u32m2(...) __riscv_vwcvtu_x_x_v_u32m2(__VA_ARGS__) -#define vwcvtu_x_x_v_u32m4(...) __riscv_vwcvtu_x_x_v_u32m4(__VA_ARGS__) -#define vwcvtu_x_x_v_u32m8(...) __riscv_vwcvtu_x_x_v_u32m8(__VA_ARGS__) -#define vfwcvt_xu_f_v_u32mf2(...) __riscv_vfwcvt_xu_f_v_u32mf2(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u32mf2(...) __riscv_vfwcvt_rtz_xu_f_v_u32mf2(__VA_ARGS__) -#define vfwcvt_xu_f_v_u32m1(...) __riscv_vfwcvt_xu_f_v_u32m1(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u32m1(...) __riscv_vfwcvt_rtz_xu_f_v_u32m1(__VA_ARGS__) -#define vfwcvt_xu_f_v_u32m2(...) __riscv_vfwcvt_xu_f_v_u32m2(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u32m2(...) __riscv_vfwcvt_rtz_xu_f_v_u32m2(__VA_ARGS__) -#define vfwcvt_xu_f_v_u32m4(...) __riscv_vfwcvt_xu_f_v_u32m4(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u32m4(...) __riscv_vfwcvt_rtz_xu_f_v_u32m4(__VA_ARGS__) -#define vfwcvt_xu_f_v_u32m8(...) __riscv_vfwcvt_xu_f_v_u32m8(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u32m8(...) __riscv_vfwcvt_rtz_xu_f_v_u32m8(__VA_ARGS__) -#define vfwcvt_f_x_v_f32mf2(...) __riscv_vfwcvt_f_x_v_f32mf2(__VA_ARGS__) -#define vfwcvt_f_x_v_f32m1(...) __riscv_vfwcvt_f_x_v_f32m1(__VA_ARGS__) -#define vfwcvt_f_x_v_f32m2(...) __riscv_vfwcvt_f_x_v_f32m2(__VA_ARGS__) -#define vfwcvt_f_x_v_f32m4(...) __riscv_vfwcvt_f_x_v_f32m4(__VA_ARGS__) -#define vfwcvt_f_x_v_f32m8(...) __riscv_vfwcvt_f_x_v_f32m8(__VA_ARGS__) -#define vfwcvt_f_xu_v_f32mf2(...) __riscv_vfwcvt_f_xu_v_f32mf2(__VA_ARGS__) -#define vfwcvt_f_xu_v_f32m1(...) __riscv_vfwcvt_f_xu_v_f32m1(__VA_ARGS__) -#define vfwcvt_f_xu_v_f32m2(...) __riscv_vfwcvt_f_xu_v_f32m2(__VA_ARGS__) -#define vfwcvt_f_xu_v_f32m4(...) __riscv_vfwcvt_f_xu_v_f32m4(__VA_ARGS__) -#define vfwcvt_f_xu_v_f32m8(...) __riscv_vfwcvt_f_xu_v_f32m8(__VA_ARGS__) -#define vfwcvt_f_f_v_f32mf2(...) __riscv_vfwcvt_f_f_v_f32mf2(__VA_ARGS__) -#define vfwcvt_f_f_v_f32m1(...) __riscv_vfwcvt_f_f_v_f32m1(__VA_ARGS__) -#define vfwcvt_f_f_v_f32m2(...) __riscv_vfwcvt_f_f_v_f32m2(__VA_ARGS__) -#define vfwcvt_f_f_v_f32m4(...) __riscv_vfwcvt_f_f_v_f32m4(__VA_ARGS__) -#define vfwcvt_f_f_v_f32m8(...) __riscv_vfwcvt_f_f_v_f32m8(__VA_ARGS__) -#define vfwcvt_x_f_v_i64m1(...) __riscv_vfwcvt_x_f_v_i64m1(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i64m1(...) __riscv_vfwcvt_rtz_x_f_v_i64m1(__VA_ARGS__) -#define vfwcvt_x_f_v_i64m2(...) __riscv_vfwcvt_x_f_v_i64m2(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i64m2(...) __riscv_vfwcvt_rtz_x_f_v_i64m2(__VA_ARGS__) -#define vfwcvt_x_f_v_i64m4(...) __riscv_vfwcvt_x_f_v_i64m4(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i64m4(...) __riscv_vfwcvt_rtz_x_f_v_i64m4(__VA_ARGS__) -#define vfwcvt_x_f_v_i64m8(...) __riscv_vfwcvt_x_f_v_i64m8(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i64m8(...) __riscv_vfwcvt_rtz_x_f_v_i64m8(__VA_ARGS__) -#define vwcvt_x_x_v_i64m1(...) __riscv_vwcvt_x_x_v_i64m1(__VA_ARGS__) -#define vwcvt_x_x_v_i64m2(...) __riscv_vwcvt_x_x_v_i64m2(__VA_ARGS__) -#define vwcvt_x_x_v_i64m4(...) __riscv_vwcvt_x_x_v_i64m4(__VA_ARGS__) -#define vwcvt_x_x_v_i64m8(...) __riscv_vwcvt_x_x_v_i64m8(__VA_ARGS__) -#define vwcvtu_x_x_v_u64m1(...) __riscv_vwcvtu_x_x_v_u64m1(__VA_ARGS__) -#define vwcvtu_x_x_v_u64m2(...) __riscv_vwcvtu_x_x_v_u64m2(__VA_ARGS__) -#define vwcvtu_x_x_v_u64m4(...) __riscv_vwcvtu_x_x_v_u64m4(__VA_ARGS__) -#define vwcvtu_x_x_v_u64m8(...) __riscv_vwcvtu_x_x_v_u64m8(__VA_ARGS__) -#define vfwcvt_xu_f_v_u64m1(...) __riscv_vfwcvt_xu_f_v_u64m1(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u64m1(...) __riscv_vfwcvt_rtz_xu_f_v_u64m1(__VA_ARGS__) -#define vfwcvt_xu_f_v_u64m2(...) __riscv_vfwcvt_xu_f_v_u64m2(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u64m2(...) __riscv_vfwcvt_rtz_xu_f_v_u64m2(__VA_ARGS__) -#define vfwcvt_xu_f_v_u64m4(...) __riscv_vfwcvt_xu_f_v_u64m4(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u64m4(...) __riscv_vfwcvt_rtz_xu_f_v_u64m4(__VA_ARGS__) -#define vfwcvt_xu_f_v_u64m8(...) __riscv_vfwcvt_xu_f_v_u64m8(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u64m8(...) __riscv_vfwcvt_rtz_xu_f_v_u64m8(__VA_ARGS__) -#define vfwcvt_f_x_v_f64m1(...) __riscv_vfwcvt_f_x_v_f64m1(__VA_ARGS__) -#define vfwcvt_f_x_v_f64m2(...) __riscv_vfwcvt_f_x_v_f64m2(__VA_ARGS__) -#define vfwcvt_f_x_v_f64m4(...) __riscv_vfwcvt_f_x_v_f64m4(__VA_ARGS__) -#define vfwcvt_f_x_v_f64m8(...) __riscv_vfwcvt_f_x_v_f64m8(__VA_ARGS__) -#define vfwcvt_f_xu_v_f64m1(...) __riscv_vfwcvt_f_xu_v_f64m1(__VA_ARGS__) -#define vfwcvt_f_xu_v_f64m2(...) __riscv_vfwcvt_f_xu_v_f64m2(__VA_ARGS__) -#define vfwcvt_f_xu_v_f64m4(...) __riscv_vfwcvt_f_xu_v_f64m4(__VA_ARGS__) -#define vfwcvt_f_xu_v_f64m8(...) __riscv_vfwcvt_f_xu_v_f64m8(__VA_ARGS__) -#define vfwcvt_f_f_v_f64m1(...) __riscv_vfwcvt_f_f_v_f64m1(__VA_ARGS__) -#define vfwcvt_f_f_v_f64m2(...) __riscv_vfwcvt_f_f_v_f64m2(__VA_ARGS__) -#define vfwcvt_f_f_v_f64m4(...) __riscv_vfwcvt_f_f_v_f64m4(__VA_ARGS__) -#define vfwcvt_f_f_v_f64m8(...) __riscv_vfwcvt_f_f_v_f64m8(__VA_ARGS__) -// masked functions -#define vwcvt_x_x_v_i16mf4_m(...) __riscv_vwcvt_x_x_v_i16mf4_tumu(__VA_ARGS__) -#define vwcvt_x_x_v_i16mf2_m(...) __riscv_vwcvt_x_x_v_i16mf2_tumu(__VA_ARGS__) -#define vwcvt_x_x_v_i16m1_m(...) __riscv_vwcvt_x_x_v_i16m1_tumu(__VA_ARGS__) -#define vwcvt_x_x_v_i16m2_m(...) __riscv_vwcvt_x_x_v_i16m2_tumu(__VA_ARGS__) -#define vwcvt_x_x_v_i16m4_m(...) __riscv_vwcvt_x_x_v_i16m4_tumu(__VA_ARGS__) -#define vwcvt_x_x_v_i16m8_m(...) __riscv_vwcvt_x_x_v_i16m8_tumu(__VA_ARGS__) -#define vwcvtu_x_x_v_u16mf4_m(...) __riscv_vwcvtu_x_x_v_u16mf4_tumu(__VA_ARGS__) -#define vwcvtu_x_x_v_u16mf2_m(...) __riscv_vwcvtu_x_x_v_u16mf2_tumu(__VA_ARGS__) -#define vwcvtu_x_x_v_u16m1_m(...) __riscv_vwcvtu_x_x_v_u16m1_tumu(__VA_ARGS__) -#define vwcvtu_x_x_v_u16m2_m(...) __riscv_vwcvtu_x_x_v_u16m2_tumu(__VA_ARGS__) -#define vwcvtu_x_x_v_u16m4_m(...) __riscv_vwcvtu_x_x_v_u16m4_tumu(__VA_ARGS__) -#define vwcvtu_x_x_v_u16m8_m(...) __riscv_vwcvtu_x_x_v_u16m8_tumu(__VA_ARGS__) -#define vfwcvt_f_x_v_f16mf4_m(...) __riscv_vfwcvt_f_x_v_f16mf4_tumu(__VA_ARGS__) -#define vfwcvt_f_x_v_f16mf2_m(...) __riscv_vfwcvt_f_x_v_f16mf2_tumu(__VA_ARGS__) -#define vfwcvt_f_x_v_f16m1_m(...) __riscv_vfwcvt_f_x_v_f16m1_tumu(__VA_ARGS__) -#define vfwcvt_f_x_v_f16m2_m(...) __riscv_vfwcvt_f_x_v_f16m2_tumu(__VA_ARGS__) -#define vfwcvt_f_x_v_f16m4_m(...) __riscv_vfwcvt_f_x_v_f16m4_tumu(__VA_ARGS__) -#define vfwcvt_f_x_v_f16m8_m(...) __riscv_vfwcvt_f_x_v_f16m8_tumu(__VA_ARGS__) -#define vfwcvt_f_xu_v_f16mf4_m(...) __riscv_vfwcvt_f_xu_v_f16mf4_tumu(__VA_ARGS__) -#define vfwcvt_f_xu_v_f16mf2_m(...) __riscv_vfwcvt_f_xu_v_f16mf2_tumu(__VA_ARGS__) -#define vfwcvt_f_xu_v_f16m1_m(...) __riscv_vfwcvt_f_xu_v_f16m1_tumu(__VA_ARGS__) -#define vfwcvt_f_xu_v_f16m2_m(...) __riscv_vfwcvt_f_xu_v_f16m2_tumu(__VA_ARGS__) -#define vfwcvt_f_xu_v_f16m4_m(...) __riscv_vfwcvt_f_xu_v_f16m4_tumu(__VA_ARGS__) -#define vfwcvt_f_xu_v_f16m8_m(...) __riscv_vfwcvt_f_xu_v_f16m8_tumu(__VA_ARGS__) -#define vfwcvt_x_f_v_i32mf2_m(...) __riscv_vfwcvt_x_f_v_i32mf2_tumu(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i32mf2_m(...) __riscv_vfwcvt_rtz_x_f_v_i32mf2_tumu(__VA_ARGS__) -#define vfwcvt_x_f_v_i32m1_m(...) __riscv_vfwcvt_x_f_v_i32m1_tumu(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i32m1_m(...) __riscv_vfwcvt_rtz_x_f_v_i32m1_tumu(__VA_ARGS__) -#define vfwcvt_x_f_v_i32m2_m(...) __riscv_vfwcvt_x_f_v_i32m2_tumu(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i32m2_m(...) __riscv_vfwcvt_rtz_x_f_v_i32m2_tumu(__VA_ARGS__) -#define vfwcvt_x_f_v_i32m4_m(...) __riscv_vfwcvt_x_f_v_i32m4_tumu(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i32m4_m(...) __riscv_vfwcvt_rtz_x_f_v_i32m4_tumu(__VA_ARGS__) -#define vfwcvt_x_f_v_i32m8_m(...) __riscv_vfwcvt_x_f_v_i32m8_tumu(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i32m8_m(...) __riscv_vfwcvt_rtz_x_f_v_i32m8_tumu(__VA_ARGS__) -#define vwcvt_x_x_v_i32mf2_m(...) __riscv_vwcvt_x_x_v_i32mf2_tumu(__VA_ARGS__) -#define vwcvt_x_x_v_i32m1_m(...) __riscv_vwcvt_x_x_v_i32m1_tumu(__VA_ARGS__) -#define vwcvt_x_x_v_i32m2_m(...) __riscv_vwcvt_x_x_v_i32m2_tumu(__VA_ARGS__) -#define vwcvt_x_x_v_i32m4_m(...) __riscv_vwcvt_x_x_v_i32m4_tumu(__VA_ARGS__) -#define vwcvt_x_x_v_i32m8_m(...) __riscv_vwcvt_x_x_v_i32m8_tumu(__VA_ARGS__) -#define vwcvtu_x_x_v_u32mf2_m(...) __riscv_vwcvtu_x_x_v_u32mf2_tumu(__VA_ARGS__) -#define vwcvtu_x_x_v_u32m1_m(...) __riscv_vwcvtu_x_x_v_u32m1_tumu(__VA_ARGS__) -#define vwcvtu_x_x_v_u32m2_m(...) __riscv_vwcvtu_x_x_v_u32m2_tumu(__VA_ARGS__) -#define vwcvtu_x_x_v_u32m4_m(...) __riscv_vwcvtu_x_x_v_u32m4_tumu(__VA_ARGS__) -#define vwcvtu_x_x_v_u32m8_m(...) __riscv_vwcvtu_x_x_v_u32m8_tumu(__VA_ARGS__) -#define vfwcvt_xu_f_v_u32mf2_m(...) __riscv_vfwcvt_xu_f_v_u32mf2_tumu(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u32mf2_m(...) __riscv_vfwcvt_rtz_xu_f_v_u32mf2_tumu(__VA_ARGS__) -#define vfwcvt_xu_f_v_u32m1_m(...) __riscv_vfwcvt_xu_f_v_u32m1_tumu(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u32m1_m(...) __riscv_vfwcvt_rtz_xu_f_v_u32m1_tumu(__VA_ARGS__) -#define vfwcvt_xu_f_v_u32m2_m(...) __riscv_vfwcvt_xu_f_v_u32m2_tumu(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u32m2_m(...) __riscv_vfwcvt_rtz_xu_f_v_u32m2_tumu(__VA_ARGS__) -#define vfwcvt_xu_f_v_u32m4_m(...) __riscv_vfwcvt_xu_f_v_u32m4_tumu(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u32m4_m(...) __riscv_vfwcvt_rtz_xu_f_v_u32m4_tumu(__VA_ARGS__) -#define vfwcvt_xu_f_v_u32m8_m(...) __riscv_vfwcvt_xu_f_v_u32m8_tumu(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u32m8_m(...) __riscv_vfwcvt_rtz_xu_f_v_u32m8_tumu(__VA_ARGS__) -#define vfwcvt_f_x_v_f32mf2_m(...) __riscv_vfwcvt_f_x_v_f32mf2_tumu(__VA_ARGS__) -#define vfwcvt_f_x_v_f32m1_m(...) __riscv_vfwcvt_f_x_v_f32m1_tumu(__VA_ARGS__) -#define vfwcvt_f_x_v_f32m2_m(...) __riscv_vfwcvt_f_x_v_f32m2_tumu(__VA_ARGS__) -#define vfwcvt_f_x_v_f32m4_m(...) __riscv_vfwcvt_f_x_v_f32m4_tumu(__VA_ARGS__) -#define vfwcvt_f_x_v_f32m8_m(...) __riscv_vfwcvt_f_x_v_f32m8_tumu(__VA_ARGS__) -#define vfwcvt_f_xu_v_f32mf2_m(...) __riscv_vfwcvt_f_xu_v_f32mf2_tumu(__VA_ARGS__) -#define vfwcvt_f_xu_v_f32m1_m(...) __riscv_vfwcvt_f_xu_v_f32m1_tumu(__VA_ARGS__) -#define vfwcvt_f_xu_v_f32m2_m(...) __riscv_vfwcvt_f_xu_v_f32m2_tumu(__VA_ARGS__) -#define vfwcvt_f_xu_v_f32m4_m(...) __riscv_vfwcvt_f_xu_v_f32m4_tumu(__VA_ARGS__) -#define vfwcvt_f_xu_v_f32m8_m(...) __riscv_vfwcvt_f_xu_v_f32m8_tumu(__VA_ARGS__) -#define vfwcvt_f_f_v_f32mf2_m(...) __riscv_vfwcvt_f_f_v_f32mf2_tumu(__VA_ARGS__) -#define vfwcvt_f_f_v_f32m1_m(...) __riscv_vfwcvt_f_f_v_f32m1_tumu(__VA_ARGS__) -#define vfwcvt_f_f_v_f32m2_m(...) __riscv_vfwcvt_f_f_v_f32m2_tumu(__VA_ARGS__) -#define vfwcvt_f_f_v_f32m4_m(...) __riscv_vfwcvt_f_f_v_f32m4_tumu(__VA_ARGS__) -#define vfwcvt_f_f_v_f32m8_m(...) __riscv_vfwcvt_f_f_v_f32m8_tumu(__VA_ARGS__) -#define vfwcvt_x_f_v_i64m1_m(...) __riscv_vfwcvt_x_f_v_i64m1_tumu(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i64m1_m(...) __riscv_vfwcvt_rtz_x_f_v_i64m1_tumu(__VA_ARGS__) -#define vfwcvt_x_f_v_i64m2_m(...) __riscv_vfwcvt_x_f_v_i64m2_tumu(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i64m2_m(...) __riscv_vfwcvt_rtz_x_f_v_i64m2_tumu(__VA_ARGS__) -#define vfwcvt_x_f_v_i64m4_m(...) __riscv_vfwcvt_x_f_v_i64m4_tumu(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i64m4_m(...) __riscv_vfwcvt_rtz_x_f_v_i64m4_tumu(__VA_ARGS__) -#define vfwcvt_x_f_v_i64m8_m(...) __riscv_vfwcvt_x_f_v_i64m8_tumu(__VA_ARGS__) -#define vfwcvt_rtz_x_f_v_i64m8_m(...) __riscv_vfwcvt_rtz_x_f_v_i64m8_tumu(__VA_ARGS__) -#define vwcvt_x_x_v_i64m1_m(...) __riscv_vwcvt_x_x_v_i64m1_tumu(__VA_ARGS__) -#define vwcvt_x_x_v_i64m2_m(...) __riscv_vwcvt_x_x_v_i64m2_tumu(__VA_ARGS__) -#define vwcvt_x_x_v_i64m4_m(...) __riscv_vwcvt_x_x_v_i64m4_tumu(__VA_ARGS__) -#define vwcvt_x_x_v_i64m8_m(...) __riscv_vwcvt_x_x_v_i64m8_tumu(__VA_ARGS__) -#define vwcvtu_x_x_v_u64m1_m(...) __riscv_vwcvtu_x_x_v_u64m1_tumu(__VA_ARGS__) -#define vwcvtu_x_x_v_u64m2_m(...) __riscv_vwcvtu_x_x_v_u64m2_tumu(__VA_ARGS__) -#define vwcvtu_x_x_v_u64m4_m(...) __riscv_vwcvtu_x_x_v_u64m4_tumu(__VA_ARGS__) -#define vwcvtu_x_x_v_u64m8_m(...) __riscv_vwcvtu_x_x_v_u64m8_tumu(__VA_ARGS__) -#define vfwcvt_xu_f_v_u64m1_m(...) __riscv_vfwcvt_xu_f_v_u64m1_tumu(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u64m1_m(...) __riscv_vfwcvt_rtz_xu_f_v_u64m1_tumu(__VA_ARGS__) -#define vfwcvt_xu_f_v_u64m2_m(...) __riscv_vfwcvt_xu_f_v_u64m2_tumu(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u64m2_m(...) __riscv_vfwcvt_rtz_xu_f_v_u64m2_tumu(__VA_ARGS__) -#define vfwcvt_xu_f_v_u64m4_m(...) __riscv_vfwcvt_xu_f_v_u64m4_tumu(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u64m4_m(...) __riscv_vfwcvt_rtz_xu_f_v_u64m4_tumu(__VA_ARGS__) -#define vfwcvt_xu_f_v_u64m8_m(...) __riscv_vfwcvt_xu_f_v_u64m8_tumu(__VA_ARGS__) -#define vfwcvt_rtz_xu_f_v_u64m8_m(...) __riscv_vfwcvt_rtz_xu_f_v_u64m8_tumu(__VA_ARGS__) -#define vfwcvt_f_x_v_f64m1_m(...) __riscv_vfwcvt_f_x_v_f64m1_tumu(__VA_ARGS__) -#define vfwcvt_f_x_v_f64m2_m(...) __riscv_vfwcvt_f_x_v_f64m2_tumu(__VA_ARGS__) -#define vfwcvt_f_x_v_f64m4_m(...) __riscv_vfwcvt_f_x_v_f64m4_tumu(__VA_ARGS__) -#define vfwcvt_f_x_v_f64m8_m(...) __riscv_vfwcvt_f_x_v_f64m8_tumu(__VA_ARGS__) -#define vfwcvt_f_xu_v_f64m1_m(...) __riscv_vfwcvt_f_xu_v_f64m1_tumu(__VA_ARGS__) -#define vfwcvt_f_xu_v_f64m2_m(...) __riscv_vfwcvt_f_xu_v_f64m2_tumu(__VA_ARGS__) -#define vfwcvt_f_xu_v_f64m4_m(...) __riscv_vfwcvt_f_xu_v_f64m4_tumu(__VA_ARGS__) -#define vfwcvt_f_xu_v_f64m8_m(...) __riscv_vfwcvt_f_xu_v_f64m8_tumu(__VA_ARGS__) -#define vfwcvt_f_f_v_f64m1_m(...) __riscv_vfwcvt_f_f_v_f64m1_tumu(__VA_ARGS__) -#define vfwcvt_f_f_v_f64m2_m(...) __riscv_vfwcvt_f_f_v_f64m2_tumu(__VA_ARGS__) -#define vfwcvt_f_f_v_f64m4_m(...) __riscv_vfwcvt_f_f_v_f64m4_tumu(__VA_ARGS__) -#define vfwcvt_f_f_v_f64m8_m(...) __riscv_vfwcvt_f_f_v_f64m8_tumu(__VA_ARGS__) -#define vfncvt_x_f_w_i8mf8(...) __riscv_vfncvt_x_f_w_i8mf8(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i8mf8(...) __riscv_vfncvt_rtz_x_f_w_i8mf8(__VA_ARGS__) -#define vfncvt_x_f_w_i8mf4(...) __riscv_vfncvt_x_f_w_i8mf4(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i8mf4(...) __riscv_vfncvt_rtz_x_f_w_i8mf4(__VA_ARGS__) -#define vfncvt_x_f_w_i8mf2(...) __riscv_vfncvt_x_f_w_i8mf2(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i8mf2(...) __riscv_vfncvt_rtz_x_f_w_i8mf2(__VA_ARGS__) -#define vfncvt_x_f_w_i8m1(...) __riscv_vfncvt_x_f_w_i8m1(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i8m1(...) __riscv_vfncvt_rtz_x_f_w_i8m1(__VA_ARGS__) -#define vfncvt_x_f_w_i8m2(...) __riscv_vfncvt_x_f_w_i8m2(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i8m2(...) __riscv_vfncvt_rtz_x_f_w_i8m2(__VA_ARGS__) -#define vfncvt_x_f_w_i8m4(...) __riscv_vfncvt_x_f_w_i8m4(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i8m4(...) __riscv_vfncvt_rtz_x_f_w_i8m4(__VA_ARGS__) -#define vncvt_x_x_w_i8mf8(...) __riscv_vncvt_x_x_w_i8mf8(__VA_ARGS__) -#define vncvt_x_x_w_i8mf4(...) __riscv_vncvt_x_x_w_i8mf4(__VA_ARGS__) -#define vncvt_x_x_w_i8mf2(...) __riscv_vncvt_x_x_w_i8mf2(__VA_ARGS__) -#define vncvt_x_x_w_i8m1(...) __riscv_vncvt_x_x_w_i8m1(__VA_ARGS__) -#define vncvt_x_x_w_i8m2(...) __riscv_vncvt_x_x_w_i8m2(__VA_ARGS__) -#define vncvt_x_x_w_i8m4(...) __riscv_vncvt_x_x_w_i8m4(__VA_ARGS__) -#define vncvt_x_x_w_u8mf8(...) __riscv_vncvt_x_x_w_u8mf8(__VA_ARGS__) -#define vncvt_x_x_w_u8mf4(...) __riscv_vncvt_x_x_w_u8mf4(__VA_ARGS__) -#define vncvt_x_x_w_u8mf2(...) __riscv_vncvt_x_x_w_u8mf2(__VA_ARGS__) -#define vncvt_x_x_w_u8m1(...) __riscv_vncvt_x_x_w_u8m1(__VA_ARGS__) -#define vncvt_x_x_w_u8m2(...) __riscv_vncvt_x_x_w_u8m2(__VA_ARGS__) -#define vncvt_x_x_w_u8m4(...) __riscv_vncvt_x_x_w_u8m4(__VA_ARGS__) -#define vfncvt_xu_f_w_u8mf8(...) __riscv_vfncvt_xu_f_w_u8mf8(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u8mf8(...) __riscv_vfncvt_rtz_xu_f_w_u8mf8(__VA_ARGS__) -#define vfncvt_xu_f_w_u8mf4(...) __riscv_vfncvt_xu_f_w_u8mf4(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u8mf4(...) __riscv_vfncvt_rtz_xu_f_w_u8mf4(__VA_ARGS__) -#define vfncvt_xu_f_w_u8mf2(...) __riscv_vfncvt_xu_f_w_u8mf2(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u8mf2(...) __riscv_vfncvt_rtz_xu_f_w_u8mf2(__VA_ARGS__) -#define vfncvt_xu_f_w_u8m1(...) __riscv_vfncvt_xu_f_w_u8m1(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u8m1(...) __riscv_vfncvt_rtz_xu_f_w_u8m1(__VA_ARGS__) -#define vfncvt_xu_f_w_u8m2(...) __riscv_vfncvt_xu_f_w_u8m2(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u8m2(...) __riscv_vfncvt_rtz_xu_f_w_u8m2(__VA_ARGS__) -#define vfncvt_xu_f_w_u8m4(...) __riscv_vfncvt_xu_f_w_u8m4(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u8m4(...) __riscv_vfncvt_rtz_xu_f_w_u8m4(__VA_ARGS__) -#define vfncvt_x_f_w_i16mf4(...) __riscv_vfncvt_x_f_w_i16mf4(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i16mf4(...) __riscv_vfncvt_rtz_x_f_w_i16mf4(__VA_ARGS__) -#define vfncvt_x_f_w_i16mf2(...) __riscv_vfncvt_x_f_w_i16mf2(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i16mf2(...) __riscv_vfncvt_rtz_x_f_w_i16mf2(__VA_ARGS__) -#define vfncvt_x_f_w_i16m1(...) __riscv_vfncvt_x_f_w_i16m1(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i16m1(...) __riscv_vfncvt_rtz_x_f_w_i16m1(__VA_ARGS__) -#define vfncvt_x_f_w_i16m2(...) __riscv_vfncvt_x_f_w_i16m2(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i16m2(...) __riscv_vfncvt_rtz_x_f_w_i16m2(__VA_ARGS__) -#define vfncvt_x_f_w_i16m4(...) __riscv_vfncvt_x_f_w_i16m4(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i16m4(...) __riscv_vfncvt_rtz_x_f_w_i16m4(__VA_ARGS__) -#define vncvt_x_x_w_i16mf4(...) __riscv_vncvt_x_x_w_i16mf4(__VA_ARGS__) -#define vncvt_x_x_w_i16mf2(...) __riscv_vncvt_x_x_w_i16mf2(__VA_ARGS__) -#define vncvt_x_x_w_i16m1(...) __riscv_vncvt_x_x_w_i16m1(__VA_ARGS__) -#define vncvt_x_x_w_i16m2(...) __riscv_vncvt_x_x_w_i16m2(__VA_ARGS__) -#define vncvt_x_x_w_i16m4(...) __riscv_vncvt_x_x_w_i16m4(__VA_ARGS__) -#define vncvt_x_x_w_u16mf4(...) __riscv_vncvt_x_x_w_u16mf4(__VA_ARGS__) -#define vncvt_x_x_w_u16mf2(...) __riscv_vncvt_x_x_w_u16mf2(__VA_ARGS__) -#define vncvt_x_x_w_u16m1(...) __riscv_vncvt_x_x_w_u16m1(__VA_ARGS__) -#define vncvt_x_x_w_u16m2(...) __riscv_vncvt_x_x_w_u16m2(__VA_ARGS__) -#define vncvt_x_x_w_u16m4(...) __riscv_vncvt_x_x_w_u16m4(__VA_ARGS__) -#define vfncvt_xu_f_w_u16mf4(...) __riscv_vfncvt_xu_f_w_u16mf4(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u16mf4(...) __riscv_vfncvt_rtz_xu_f_w_u16mf4(__VA_ARGS__) -#define vfncvt_xu_f_w_u16mf2(...) __riscv_vfncvt_xu_f_w_u16mf2(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u16mf2(...) __riscv_vfncvt_rtz_xu_f_w_u16mf2(__VA_ARGS__) -#define vfncvt_xu_f_w_u16m1(...) __riscv_vfncvt_xu_f_w_u16m1(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u16m1(...) __riscv_vfncvt_rtz_xu_f_w_u16m1(__VA_ARGS__) -#define vfncvt_xu_f_w_u16m2(...) __riscv_vfncvt_xu_f_w_u16m2(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u16m2(...) __riscv_vfncvt_rtz_xu_f_w_u16m2(__VA_ARGS__) -#define vfncvt_xu_f_w_u16m4(...) __riscv_vfncvt_xu_f_w_u16m4(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u16m4(...) __riscv_vfncvt_rtz_xu_f_w_u16m4(__VA_ARGS__) -#define vfncvt_f_x_w_f16mf4(...) __riscv_vfncvt_f_x_w_f16mf4(__VA_ARGS__) -#define vfncvt_f_x_w_f16mf2(...) __riscv_vfncvt_f_x_w_f16mf2(__VA_ARGS__) -#define vfncvt_f_x_w_f16m1(...) __riscv_vfncvt_f_x_w_f16m1(__VA_ARGS__) -#define vfncvt_f_x_w_f16m2(...) __riscv_vfncvt_f_x_w_f16m2(__VA_ARGS__) -#define vfncvt_f_x_w_f16m4(...) __riscv_vfncvt_f_x_w_f16m4(__VA_ARGS__) -#define vfncvt_f_xu_w_f16mf4(...) __riscv_vfncvt_f_xu_w_f16mf4(__VA_ARGS__) -#define vfncvt_f_xu_w_f16mf2(...) __riscv_vfncvt_f_xu_w_f16mf2(__VA_ARGS__) -#define vfncvt_f_xu_w_f16m1(...) __riscv_vfncvt_f_xu_w_f16m1(__VA_ARGS__) -#define vfncvt_f_xu_w_f16m2(...) __riscv_vfncvt_f_xu_w_f16m2(__VA_ARGS__) -#define vfncvt_f_xu_w_f16m4(...) __riscv_vfncvt_f_xu_w_f16m4(__VA_ARGS__) -#define vfncvt_f_f_w_f16mf4(...) __riscv_vfncvt_f_f_w_f16mf4(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f16mf4(...) __riscv_vfncvt_rod_f_f_w_f16mf4(__VA_ARGS__) -#define vfncvt_f_f_w_f16mf2(...) __riscv_vfncvt_f_f_w_f16mf2(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f16mf2(...) __riscv_vfncvt_rod_f_f_w_f16mf2(__VA_ARGS__) -#define vfncvt_f_f_w_f16m1(...) __riscv_vfncvt_f_f_w_f16m1(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f16m1(...) __riscv_vfncvt_rod_f_f_w_f16m1(__VA_ARGS__) -#define vfncvt_f_f_w_f16m2(...) __riscv_vfncvt_f_f_w_f16m2(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f16m2(...) __riscv_vfncvt_rod_f_f_w_f16m2(__VA_ARGS__) -#define vfncvt_f_f_w_f16m4(...) __riscv_vfncvt_f_f_w_f16m4(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f16m4(...) __riscv_vfncvt_rod_f_f_w_f16m4(__VA_ARGS__) -#define vfncvt_x_f_w_i32mf2(...) __riscv_vfncvt_x_f_w_i32mf2(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i32mf2(...) __riscv_vfncvt_rtz_x_f_w_i32mf2(__VA_ARGS__) -#define vfncvt_x_f_w_i32m1(...) __riscv_vfncvt_x_f_w_i32m1(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i32m1(...) __riscv_vfncvt_rtz_x_f_w_i32m1(__VA_ARGS__) -#define vfncvt_x_f_w_i32m2(...) __riscv_vfncvt_x_f_w_i32m2(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i32m2(...) __riscv_vfncvt_rtz_x_f_w_i32m2(__VA_ARGS__) -#define vfncvt_x_f_w_i32m4(...) __riscv_vfncvt_x_f_w_i32m4(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i32m4(...) __riscv_vfncvt_rtz_x_f_w_i32m4(__VA_ARGS__) -#define vncvt_x_x_w_i32mf2(...) __riscv_vncvt_x_x_w_i32mf2(__VA_ARGS__) -#define vncvt_x_x_w_i32m1(...) __riscv_vncvt_x_x_w_i32m1(__VA_ARGS__) -#define vncvt_x_x_w_i32m2(...) __riscv_vncvt_x_x_w_i32m2(__VA_ARGS__) -#define vncvt_x_x_w_i32m4(...) __riscv_vncvt_x_x_w_i32m4(__VA_ARGS__) -#define vncvt_x_x_w_u32mf2(...) __riscv_vncvt_x_x_w_u32mf2(__VA_ARGS__) -#define vncvt_x_x_w_u32m1(...) __riscv_vncvt_x_x_w_u32m1(__VA_ARGS__) -#define vncvt_x_x_w_u32m2(...) __riscv_vncvt_x_x_w_u32m2(__VA_ARGS__) -#define vncvt_x_x_w_u32m4(...) __riscv_vncvt_x_x_w_u32m4(__VA_ARGS__) -#define vfncvt_xu_f_w_u32mf2(...) __riscv_vfncvt_xu_f_w_u32mf2(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u32mf2(...) __riscv_vfncvt_rtz_xu_f_w_u32mf2(__VA_ARGS__) -#define vfncvt_xu_f_w_u32m1(...) __riscv_vfncvt_xu_f_w_u32m1(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u32m1(...) __riscv_vfncvt_rtz_xu_f_w_u32m1(__VA_ARGS__) -#define vfncvt_xu_f_w_u32m2(...) __riscv_vfncvt_xu_f_w_u32m2(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u32m2(...) __riscv_vfncvt_rtz_xu_f_w_u32m2(__VA_ARGS__) -#define vfncvt_xu_f_w_u32m4(...) __riscv_vfncvt_xu_f_w_u32m4(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u32m4(...) __riscv_vfncvt_rtz_xu_f_w_u32m4(__VA_ARGS__) -#define vfncvt_f_x_w_f32mf2(...) __riscv_vfncvt_f_x_w_f32mf2(__VA_ARGS__) -#define vfncvt_f_x_w_f32m1(...) __riscv_vfncvt_f_x_w_f32m1(__VA_ARGS__) -#define vfncvt_f_x_w_f32m2(...) __riscv_vfncvt_f_x_w_f32m2(__VA_ARGS__) -#define vfncvt_f_x_w_f32m4(...) __riscv_vfncvt_f_x_w_f32m4(__VA_ARGS__) -#define vfncvt_f_xu_w_f32mf2(...) __riscv_vfncvt_f_xu_w_f32mf2(__VA_ARGS__) -#define vfncvt_f_xu_w_f32m1(...) __riscv_vfncvt_f_xu_w_f32m1(__VA_ARGS__) -#define vfncvt_f_xu_w_f32m2(...) __riscv_vfncvt_f_xu_w_f32m2(__VA_ARGS__) -#define vfncvt_f_xu_w_f32m4(...) __riscv_vfncvt_f_xu_w_f32m4(__VA_ARGS__) -#define vfncvt_f_f_w_f32mf2(...) __riscv_vfncvt_f_f_w_f32mf2(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f32mf2(...) __riscv_vfncvt_rod_f_f_w_f32mf2(__VA_ARGS__) -#define vfncvt_f_f_w_f32m1(...) __riscv_vfncvt_f_f_w_f32m1(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f32m1(...) __riscv_vfncvt_rod_f_f_w_f32m1(__VA_ARGS__) -#define vfncvt_f_f_w_f32m2(...) __riscv_vfncvt_f_f_w_f32m2(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f32m2(...) __riscv_vfncvt_rod_f_f_w_f32m2(__VA_ARGS__) -#define vfncvt_f_f_w_f32m4(...) __riscv_vfncvt_f_f_w_f32m4(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f32m4(...) __riscv_vfncvt_rod_f_f_w_f32m4(__VA_ARGS__) -// masked functions -#define vfncvt_x_f_w_i8mf8_m(...) __riscv_vfncvt_x_f_w_i8mf8_tumu(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i8mf8_m(...) __riscv_vfncvt_rtz_x_f_w_i8mf8_tumu(__VA_ARGS__) -#define vfncvt_x_f_w_i8mf4_m(...) __riscv_vfncvt_x_f_w_i8mf4_tumu(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i8mf4_m(...) __riscv_vfncvt_rtz_x_f_w_i8mf4_tumu(__VA_ARGS__) -#define vfncvt_x_f_w_i8mf2_m(...) __riscv_vfncvt_x_f_w_i8mf2_tumu(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i8mf2_m(...) __riscv_vfncvt_rtz_x_f_w_i8mf2_tumu(__VA_ARGS__) -#define vfncvt_x_f_w_i8m1_m(...) __riscv_vfncvt_x_f_w_i8m1_tumu(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i8m1_m(...) __riscv_vfncvt_rtz_x_f_w_i8m1_tumu(__VA_ARGS__) -#define vfncvt_x_f_w_i8m2_m(...) __riscv_vfncvt_x_f_w_i8m2_tumu(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i8m2_m(...) __riscv_vfncvt_rtz_x_f_w_i8m2_tumu(__VA_ARGS__) -#define vfncvt_x_f_w_i8m4_m(...) __riscv_vfncvt_x_f_w_i8m4_tumu(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i8m4_m(...) __riscv_vfncvt_rtz_x_f_w_i8m4_tumu(__VA_ARGS__) -#define vncvt_x_x_w_i8mf8_m(...) __riscv_vncvt_x_x_w_i8mf8_tumu(__VA_ARGS__) -#define vncvt_x_x_w_i8mf4_m(...) __riscv_vncvt_x_x_w_i8mf4_tumu(__VA_ARGS__) -#define vncvt_x_x_w_i8mf2_m(...) __riscv_vncvt_x_x_w_i8mf2_tumu(__VA_ARGS__) -#define vncvt_x_x_w_i8m1_m(...) __riscv_vncvt_x_x_w_i8m1_tumu(__VA_ARGS__) -#define vncvt_x_x_w_i8m2_m(...) __riscv_vncvt_x_x_w_i8m2_tumu(__VA_ARGS__) -#define vncvt_x_x_w_i8m4_m(...) __riscv_vncvt_x_x_w_i8m4_tumu(__VA_ARGS__) -#define vncvt_x_x_w_u8mf8_m(...) __riscv_vncvt_x_x_w_u8mf8_tumu(__VA_ARGS__) -#define vncvt_x_x_w_u8mf4_m(...) __riscv_vncvt_x_x_w_u8mf4_tumu(__VA_ARGS__) -#define vncvt_x_x_w_u8mf2_m(...) __riscv_vncvt_x_x_w_u8mf2_tumu(__VA_ARGS__) -#define vncvt_x_x_w_u8m1_m(...) __riscv_vncvt_x_x_w_u8m1_tumu(__VA_ARGS__) -#define vncvt_x_x_w_u8m2_m(...) __riscv_vncvt_x_x_w_u8m2_tumu(__VA_ARGS__) -#define vncvt_x_x_w_u8m4_m(...) __riscv_vncvt_x_x_w_u8m4_tumu(__VA_ARGS__) -#define vfncvt_xu_f_w_u8mf8_m(...) __riscv_vfncvt_xu_f_w_u8mf8_tumu(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u8mf8_m(...) __riscv_vfncvt_rtz_xu_f_w_u8mf8_tumu(__VA_ARGS__) -#define vfncvt_xu_f_w_u8mf4_m(...) __riscv_vfncvt_xu_f_w_u8mf4_tumu(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u8mf4_m(...) __riscv_vfncvt_rtz_xu_f_w_u8mf4_tumu(__VA_ARGS__) -#define vfncvt_xu_f_w_u8mf2_m(...) __riscv_vfncvt_xu_f_w_u8mf2_tumu(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u8mf2_m(...) __riscv_vfncvt_rtz_xu_f_w_u8mf2_tumu(__VA_ARGS__) -#define vfncvt_xu_f_w_u8m1_m(...) __riscv_vfncvt_xu_f_w_u8m1_tumu(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u8m1_m(...) __riscv_vfncvt_rtz_xu_f_w_u8m1_tumu(__VA_ARGS__) -#define vfncvt_xu_f_w_u8m2_m(...) __riscv_vfncvt_xu_f_w_u8m2_tumu(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u8m2_m(...) __riscv_vfncvt_rtz_xu_f_w_u8m2_tumu(__VA_ARGS__) -#define vfncvt_xu_f_w_u8m4_m(...) __riscv_vfncvt_xu_f_w_u8m4_tumu(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u8m4_m(...) __riscv_vfncvt_rtz_xu_f_w_u8m4_tumu(__VA_ARGS__) -#define vfncvt_x_f_w_i16mf4_m(...) __riscv_vfncvt_x_f_w_i16mf4_tumu(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i16mf4_m(...) __riscv_vfncvt_rtz_x_f_w_i16mf4_tumu(__VA_ARGS__) -#define vfncvt_x_f_w_i16mf2_m(...) __riscv_vfncvt_x_f_w_i16mf2_tumu(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i16mf2_m(...) __riscv_vfncvt_rtz_x_f_w_i16mf2_tumu(__VA_ARGS__) -#define vfncvt_x_f_w_i16m1_m(...) __riscv_vfncvt_x_f_w_i16m1_tumu(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i16m1_m(...) __riscv_vfncvt_rtz_x_f_w_i16m1_tumu(__VA_ARGS__) -#define vfncvt_x_f_w_i16m2_m(...) __riscv_vfncvt_x_f_w_i16m2_tumu(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i16m2_m(...) __riscv_vfncvt_rtz_x_f_w_i16m2_tumu(__VA_ARGS__) -#define vfncvt_x_f_w_i16m4_m(...) __riscv_vfncvt_x_f_w_i16m4_tumu(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i16m4_m(...) __riscv_vfncvt_rtz_x_f_w_i16m4_tumu(__VA_ARGS__) -#define vncvt_x_x_w_i16mf4_m(...) __riscv_vncvt_x_x_w_i16mf4_tumu(__VA_ARGS__) -#define vncvt_x_x_w_i16mf2_m(...) __riscv_vncvt_x_x_w_i16mf2_tumu(__VA_ARGS__) -#define vncvt_x_x_w_i16m1_m(...) __riscv_vncvt_x_x_w_i16m1_tumu(__VA_ARGS__) -#define vncvt_x_x_w_i16m2_m(...) __riscv_vncvt_x_x_w_i16m2_tumu(__VA_ARGS__) -#define vncvt_x_x_w_i16m4_m(...) __riscv_vncvt_x_x_w_i16m4_tumu(__VA_ARGS__) -#define vncvt_x_x_w_u16mf4_m(...) __riscv_vncvt_x_x_w_u16mf4_tumu(__VA_ARGS__) -#define vncvt_x_x_w_u16mf2_m(...) __riscv_vncvt_x_x_w_u16mf2_tumu(__VA_ARGS__) -#define vncvt_x_x_w_u16m1_m(...) __riscv_vncvt_x_x_w_u16m1_tumu(__VA_ARGS__) -#define vncvt_x_x_w_u16m2_m(...) __riscv_vncvt_x_x_w_u16m2_tumu(__VA_ARGS__) -#define vncvt_x_x_w_u16m4_m(...) __riscv_vncvt_x_x_w_u16m4_tumu(__VA_ARGS__) -#define vfncvt_xu_f_w_u16mf4_m(...) __riscv_vfncvt_xu_f_w_u16mf4_tumu(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u16mf4_m(...) __riscv_vfncvt_rtz_xu_f_w_u16mf4_tumu(__VA_ARGS__) -#define vfncvt_xu_f_w_u16mf2_m(...) __riscv_vfncvt_xu_f_w_u16mf2_tumu(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u16mf2_m(...) __riscv_vfncvt_rtz_xu_f_w_u16mf2_tumu(__VA_ARGS__) -#define vfncvt_xu_f_w_u16m1_m(...) __riscv_vfncvt_xu_f_w_u16m1_tumu(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u16m1_m(...) __riscv_vfncvt_rtz_xu_f_w_u16m1_tumu(__VA_ARGS__) -#define vfncvt_xu_f_w_u16m2_m(...) __riscv_vfncvt_xu_f_w_u16m2_tumu(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u16m2_m(...) __riscv_vfncvt_rtz_xu_f_w_u16m2_tumu(__VA_ARGS__) -#define vfncvt_xu_f_w_u16m4_m(...) __riscv_vfncvt_xu_f_w_u16m4_tumu(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u16m4_m(...) __riscv_vfncvt_rtz_xu_f_w_u16m4_tumu(__VA_ARGS__) -#define vfncvt_f_x_w_f16mf4_m(...) __riscv_vfncvt_f_x_w_f16mf4_tumu(__VA_ARGS__) -#define vfncvt_f_x_w_f16mf2_m(...) __riscv_vfncvt_f_x_w_f16mf2_tumu(__VA_ARGS__) -#define vfncvt_f_x_w_f16m1_m(...) __riscv_vfncvt_f_x_w_f16m1_tumu(__VA_ARGS__) -#define vfncvt_f_x_w_f16m2_m(...) __riscv_vfncvt_f_x_w_f16m2_tumu(__VA_ARGS__) -#define vfncvt_f_x_w_f16m4_m(...) __riscv_vfncvt_f_x_w_f16m4_tumu(__VA_ARGS__) -#define vfncvt_f_xu_w_f16mf4_m(...) __riscv_vfncvt_f_xu_w_f16mf4_tumu(__VA_ARGS__) -#define vfncvt_f_xu_w_f16mf2_m(...) __riscv_vfncvt_f_xu_w_f16mf2_tumu(__VA_ARGS__) -#define vfncvt_f_xu_w_f16m1_m(...) __riscv_vfncvt_f_xu_w_f16m1_tumu(__VA_ARGS__) -#define vfncvt_f_xu_w_f16m2_m(...) __riscv_vfncvt_f_xu_w_f16m2_tumu(__VA_ARGS__) -#define vfncvt_f_xu_w_f16m4_m(...) __riscv_vfncvt_f_xu_w_f16m4_tumu(__VA_ARGS__) -#define vfncvt_f_f_w_f16mf4_m(...) __riscv_vfncvt_f_f_w_f16mf4_tumu(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f16mf4_m(...) __riscv_vfncvt_rod_f_f_w_f16mf4_tumu(__VA_ARGS__) -#define vfncvt_f_f_w_f16mf2_m(...) __riscv_vfncvt_f_f_w_f16mf2_tumu(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f16mf2_m(...) __riscv_vfncvt_rod_f_f_w_f16mf2_tumu(__VA_ARGS__) -#define vfncvt_f_f_w_f16m1_m(...) __riscv_vfncvt_f_f_w_f16m1_tumu(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f16m1_m(...) __riscv_vfncvt_rod_f_f_w_f16m1_tumu(__VA_ARGS__) -#define vfncvt_f_f_w_f16m2_m(...) __riscv_vfncvt_f_f_w_f16m2_tumu(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f16m2_m(...) __riscv_vfncvt_rod_f_f_w_f16m2_tumu(__VA_ARGS__) -#define vfncvt_f_f_w_f16m4_m(...) __riscv_vfncvt_f_f_w_f16m4_tumu(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f16m4_m(...) __riscv_vfncvt_rod_f_f_w_f16m4_tumu(__VA_ARGS__) -#define vfncvt_x_f_w_i32mf2_m(...) __riscv_vfncvt_x_f_w_i32mf2_tumu(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i32mf2_m(...) __riscv_vfncvt_rtz_x_f_w_i32mf2_tumu(__VA_ARGS__) -#define vfncvt_x_f_w_i32m1_m(...) __riscv_vfncvt_x_f_w_i32m1_tumu(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i32m1_m(...) __riscv_vfncvt_rtz_x_f_w_i32m1_tumu(__VA_ARGS__) -#define vfncvt_x_f_w_i32m2_m(...) __riscv_vfncvt_x_f_w_i32m2_tumu(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i32m2_m(...) __riscv_vfncvt_rtz_x_f_w_i32m2_tumu(__VA_ARGS__) -#define vfncvt_x_f_w_i32m4_m(...) __riscv_vfncvt_x_f_w_i32m4_tumu(__VA_ARGS__) -#define vfncvt_rtz_x_f_w_i32m4_m(...) __riscv_vfncvt_rtz_x_f_w_i32m4_tumu(__VA_ARGS__) -#define vncvt_x_x_w_i32mf2_m(...) __riscv_vncvt_x_x_w_i32mf2_tumu(__VA_ARGS__) -#define vncvt_x_x_w_i32m1_m(...) __riscv_vncvt_x_x_w_i32m1_tumu(__VA_ARGS__) -#define vncvt_x_x_w_i32m2_m(...) __riscv_vncvt_x_x_w_i32m2_tumu(__VA_ARGS__) -#define vncvt_x_x_w_i32m4_m(...) __riscv_vncvt_x_x_w_i32m4_tumu(__VA_ARGS__) -#define vncvt_x_x_w_u32mf2_m(...) __riscv_vncvt_x_x_w_u32mf2_tumu(__VA_ARGS__) -#define vncvt_x_x_w_u32m1_m(...) __riscv_vncvt_x_x_w_u32m1_tumu(__VA_ARGS__) -#define vncvt_x_x_w_u32m2_m(...) __riscv_vncvt_x_x_w_u32m2_tumu(__VA_ARGS__) -#define vncvt_x_x_w_u32m4_m(...) __riscv_vncvt_x_x_w_u32m4_tumu(__VA_ARGS__) -#define vfncvt_xu_f_w_u32mf2_m(...) __riscv_vfncvt_xu_f_w_u32mf2_tumu(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u32mf2_m(...) __riscv_vfncvt_rtz_xu_f_w_u32mf2_tumu(__VA_ARGS__) -#define vfncvt_xu_f_w_u32m1_m(...) __riscv_vfncvt_xu_f_w_u32m1_tumu(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u32m1_m(...) __riscv_vfncvt_rtz_xu_f_w_u32m1_tumu(__VA_ARGS__) -#define vfncvt_xu_f_w_u32m2_m(...) __riscv_vfncvt_xu_f_w_u32m2_tumu(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u32m2_m(...) __riscv_vfncvt_rtz_xu_f_w_u32m2_tumu(__VA_ARGS__) -#define vfncvt_xu_f_w_u32m4_m(...) __riscv_vfncvt_xu_f_w_u32m4_tumu(__VA_ARGS__) -#define vfncvt_rtz_xu_f_w_u32m4_m(...) __riscv_vfncvt_rtz_xu_f_w_u32m4_tumu(__VA_ARGS__) -#define vfncvt_f_x_w_f32mf2_m(...) __riscv_vfncvt_f_x_w_f32mf2_tumu(__VA_ARGS__) -#define vfncvt_f_x_w_f32m1_m(...) __riscv_vfncvt_f_x_w_f32m1_tumu(__VA_ARGS__) -#define vfncvt_f_x_w_f32m2_m(...) __riscv_vfncvt_f_x_w_f32m2_tumu(__VA_ARGS__) -#define vfncvt_f_x_w_f32m4_m(...) __riscv_vfncvt_f_x_w_f32m4_tumu(__VA_ARGS__) -#define vfncvt_f_xu_w_f32mf2_m(...) __riscv_vfncvt_f_xu_w_f32mf2_tumu(__VA_ARGS__) -#define vfncvt_f_xu_w_f32m1_m(...) __riscv_vfncvt_f_xu_w_f32m1_tumu(__VA_ARGS__) -#define vfncvt_f_xu_w_f32m2_m(...) __riscv_vfncvt_f_xu_w_f32m2_tumu(__VA_ARGS__) -#define vfncvt_f_xu_w_f32m4_m(...) __riscv_vfncvt_f_xu_w_f32m4_tumu(__VA_ARGS__) -#define vfncvt_f_f_w_f32mf2_m(...) __riscv_vfncvt_f_f_w_f32mf2_tumu(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f32mf2_m(...) __riscv_vfncvt_rod_f_f_w_f32mf2_tumu(__VA_ARGS__) -#define vfncvt_f_f_w_f32m1_m(...) __riscv_vfncvt_f_f_w_f32m1_tumu(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f32m1_m(...) __riscv_vfncvt_rod_f_f_w_f32m1_tumu(__VA_ARGS__) -#define vfncvt_f_f_w_f32m2_m(...) __riscv_vfncvt_f_f_w_f32m2_tumu(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f32m2_m(...) __riscv_vfncvt_rod_f_f_w_f32m2_tumu(__VA_ARGS__) -#define vfncvt_f_f_w_f32m4_m(...) __riscv_vfncvt_f_f_w_f32m4_tumu(__VA_ARGS__) -#define vfncvt_rod_f_f_w_f32m4_m(...) __riscv_vfncvt_rod_f_f_w_f32m4_tumu(__VA_ARGS__) -#define vredsum_vs_i8mf8_i8m1(...) __riscv_vredsum_vs_i8mf8_i8m1_tu(__VA_ARGS__) -#define vredsum_vs_i8mf4_i8m1(...) __riscv_vredsum_vs_i8mf4_i8m1_tu(__VA_ARGS__) -#define vredsum_vs_i8mf2_i8m1(...) __riscv_vredsum_vs_i8mf2_i8m1_tu(__VA_ARGS__) -#define vredsum_vs_i8m1_i8m1(...) __riscv_vredsum_vs_i8m1_i8m1_tu(__VA_ARGS__) -#define vredsum_vs_i8m2_i8m1(...) __riscv_vredsum_vs_i8m2_i8m1_tu(__VA_ARGS__) -#define vredsum_vs_i8m4_i8m1(...) __riscv_vredsum_vs_i8m4_i8m1_tu(__VA_ARGS__) -#define vredsum_vs_i8m8_i8m1(...) __riscv_vredsum_vs_i8m8_i8m1_tu(__VA_ARGS__) -#define vredsum_vs_i16mf4_i16m1(...) __riscv_vredsum_vs_i16mf4_i16m1_tu(__VA_ARGS__) -#define vredsum_vs_i16mf2_i16m1(...) __riscv_vredsum_vs_i16mf2_i16m1_tu(__VA_ARGS__) -#define vredsum_vs_i16m1_i16m1(...) __riscv_vredsum_vs_i16m1_i16m1_tu(__VA_ARGS__) -#define vredsum_vs_i16m2_i16m1(...) __riscv_vredsum_vs_i16m2_i16m1_tu(__VA_ARGS__) -#define vredsum_vs_i16m4_i16m1(...) __riscv_vredsum_vs_i16m4_i16m1_tu(__VA_ARGS__) -#define vredsum_vs_i16m8_i16m1(...) __riscv_vredsum_vs_i16m8_i16m1_tu(__VA_ARGS__) -#define vredsum_vs_i32mf2_i32m1(...) __riscv_vredsum_vs_i32mf2_i32m1_tu(__VA_ARGS__) -#define vredsum_vs_i32m1_i32m1(...) __riscv_vredsum_vs_i32m1_i32m1_tu(__VA_ARGS__) -#define vredsum_vs_i32m2_i32m1(...) __riscv_vredsum_vs_i32m2_i32m1_tu(__VA_ARGS__) -#define vredsum_vs_i32m4_i32m1(...) __riscv_vredsum_vs_i32m4_i32m1_tu(__VA_ARGS__) -#define vredsum_vs_i32m8_i32m1(...) __riscv_vredsum_vs_i32m8_i32m1_tu(__VA_ARGS__) -#define vredsum_vs_i64m1_i64m1(...) __riscv_vredsum_vs_i64m1_i64m1_tu(__VA_ARGS__) -#define vredsum_vs_i64m2_i64m1(...) __riscv_vredsum_vs_i64m2_i64m1_tu(__VA_ARGS__) -#define vredsum_vs_i64m4_i64m1(...) __riscv_vredsum_vs_i64m4_i64m1_tu(__VA_ARGS__) -#define vredsum_vs_i64m8_i64m1(...) __riscv_vredsum_vs_i64m8_i64m1_tu(__VA_ARGS__) -#define vredmax_vs_i8mf8_i8m1(...) __riscv_vredmax_vs_i8mf8_i8m1_tu(__VA_ARGS__) -#define vredmax_vs_i8mf4_i8m1(...) __riscv_vredmax_vs_i8mf4_i8m1_tu(__VA_ARGS__) -#define vredmax_vs_i8mf2_i8m1(...) __riscv_vredmax_vs_i8mf2_i8m1_tu(__VA_ARGS__) -#define vredmax_vs_i8m1_i8m1(...) __riscv_vredmax_vs_i8m1_i8m1_tu(__VA_ARGS__) -#define vredmax_vs_i8m2_i8m1(...) __riscv_vredmax_vs_i8m2_i8m1_tu(__VA_ARGS__) -#define vredmax_vs_i8m4_i8m1(...) __riscv_vredmax_vs_i8m4_i8m1_tu(__VA_ARGS__) -#define vredmax_vs_i8m8_i8m1(...) __riscv_vredmax_vs_i8m8_i8m1_tu(__VA_ARGS__) -#define vredmax_vs_i16mf4_i16m1(...) __riscv_vredmax_vs_i16mf4_i16m1_tu(__VA_ARGS__) -#define vredmax_vs_i16mf2_i16m1(...) __riscv_vredmax_vs_i16mf2_i16m1_tu(__VA_ARGS__) -#define vredmax_vs_i16m1_i16m1(...) __riscv_vredmax_vs_i16m1_i16m1_tu(__VA_ARGS__) -#define vredmax_vs_i16m2_i16m1(...) __riscv_vredmax_vs_i16m2_i16m1_tu(__VA_ARGS__) -#define vredmax_vs_i16m4_i16m1(...) __riscv_vredmax_vs_i16m4_i16m1_tu(__VA_ARGS__) -#define vredmax_vs_i16m8_i16m1(...) __riscv_vredmax_vs_i16m8_i16m1_tu(__VA_ARGS__) -#define vredmax_vs_i32mf2_i32m1(...) __riscv_vredmax_vs_i32mf2_i32m1_tu(__VA_ARGS__) -#define vredmax_vs_i32m1_i32m1(...) __riscv_vredmax_vs_i32m1_i32m1_tu(__VA_ARGS__) -#define vredmax_vs_i32m2_i32m1(...) __riscv_vredmax_vs_i32m2_i32m1_tu(__VA_ARGS__) -#define vredmax_vs_i32m4_i32m1(...) __riscv_vredmax_vs_i32m4_i32m1_tu(__VA_ARGS__) -#define vredmax_vs_i32m8_i32m1(...) __riscv_vredmax_vs_i32m8_i32m1_tu(__VA_ARGS__) -#define vredmax_vs_i64m1_i64m1(...) __riscv_vredmax_vs_i64m1_i64m1_tu(__VA_ARGS__) -#define vredmax_vs_i64m2_i64m1(...) __riscv_vredmax_vs_i64m2_i64m1_tu(__VA_ARGS__) -#define vredmax_vs_i64m4_i64m1(...) __riscv_vredmax_vs_i64m4_i64m1_tu(__VA_ARGS__) -#define vredmax_vs_i64m8_i64m1(...) __riscv_vredmax_vs_i64m8_i64m1_tu(__VA_ARGS__) -#define vredmin_vs_i8mf8_i8m1(...) __riscv_vredmin_vs_i8mf8_i8m1_tu(__VA_ARGS__) -#define vredmin_vs_i8mf4_i8m1(...) __riscv_vredmin_vs_i8mf4_i8m1_tu(__VA_ARGS__) -#define vredmin_vs_i8mf2_i8m1(...) __riscv_vredmin_vs_i8mf2_i8m1_tu(__VA_ARGS__) -#define vredmin_vs_i8m1_i8m1(...) __riscv_vredmin_vs_i8m1_i8m1_tu(__VA_ARGS__) -#define vredmin_vs_i8m2_i8m1(...) __riscv_vredmin_vs_i8m2_i8m1_tu(__VA_ARGS__) -#define vredmin_vs_i8m4_i8m1(...) __riscv_vredmin_vs_i8m4_i8m1_tu(__VA_ARGS__) -#define vredmin_vs_i8m8_i8m1(...) __riscv_vredmin_vs_i8m8_i8m1_tu(__VA_ARGS__) -#define vredmin_vs_i16mf4_i16m1(...) __riscv_vredmin_vs_i16mf4_i16m1_tu(__VA_ARGS__) -#define vredmin_vs_i16mf2_i16m1(...) __riscv_vredmin_vs_i16mf2_i16m1_tu(__VA_ARGS__) -#define vredmin_vs_i16m1_i16m1(...) __riscv_vredmin_vs_i16m1_i16m1_tu(__VA_ARGS__) -#define vredmin_vs_i16m2_i16m1(...) __riscv_vredmin_vs_i16m2_i16m1_tu(__VA_ARGS__) -#define vredmin_vs_i16m4_i16m1(...) __riscv_vredmin_vs_i16m4_i16m1_tu(__VA_ARGS__) -#define vredmin_vs_i16m8_i16m1(...) __riscv_vredmin_vs_i16m8_i16m1_tu(__VA_ARGS__) -#define vredmin_vs_i32mf2_i32m1(...) __riscv_vredmin_vs_i32mf2_i32m1_tu(__VA_ARGS__) -#define vredmin_vs_i32m1_i32m1(...) __riscv_vredmin_vs_i32m1_i32m1_tu(__VA_ARGS__) -#define vredmin_vs_i32m2_i32m1(...) __riscv_vredmin_vs_i32m2_i32m1_tu(__VA_ARGS__) -#define vredmin_vs_i32m4_i32m1(...) __riscv_vredmin_vs_i32m4_i32m1_tu(__VA_ARGS__) -#define vredmin_vs_i32m8_i32m1(...) __riscv_vredmin_vs_i32m8_i32m1_tu(__VA_ARGS__) -#define vredmin_vs_i64m1_i64m1(...) __riscv_vredmin_vs_i64m1_i64m1_tu(__VA_ARGS__) -#define vredmin_vs_i64m2_i64m1(...) __riscv_vredmin_vs_i64m2_i64m1_tu(__VA_ARGS__) -#define vredmin_vs_i64m4_i64m1(...) __riscv_vredmin_vs_i64m4_i64m1_tu(__VA_ARGS__) -#define vredmin_vs_i64m8_i64m1(...) __riscv_vredmin_vs_i64m8_i64m1_tu(__VA_ARGS__) -#define vredand_vs_i8mf8_i8m1(...) __riscv_vredand_vs_i8mf8_i8m1_tu(__VA_ARGS__) -#define vredand_vs_i8mf4_i8m1(...) __riscv_vredand_vs_i8mf4_i8m1_tu(__VA_ARGS__) -#define vredand_vs_i8mf2_i8m1(...) __riscv_vredand_vs_i8mf2_i8m1_tu(__VA_ARGS__) -#define vredand_vs_i8m1_i8m1(...) __riscv_vredand_vs_i8m1_i8m1_tu(__VA_ARGS__) -#define vredand_vs_i8m2_i8m1(...) __riscv_vredand_vs_i8m2_i8m1_tu(__VA_ARGS__) -#define vredand_vs_i8m4_i8m1(...) __riscv_vredand_vs_i8m4_i8m1_tu(__VA_ARGS__) -#define vredand_vs_i8m8_i8m1(...) __riscv_vredand_vs_i8m8_i8m1_tu(__VA_ARGS__) -#define vredand_vs_i16mf4_i16m1(...) __riscv_vredand_vs_i16mf4_i16m1_tu(__VA_ARGS__) -#define vredand_vs_i16mf2_i16m1(...) __riscv_vredand_vs_i16mf2_i16m1_tu(__VA_ARGS__) -#define vredand_vs_i16m1_i16m1(...) __riscv_vredand_vs_i16m1_i16m1_tu(__VA_ARGS__) -#define vredand_vs_i16m2_i16m1(...) __riscv_vredand_vs_i16m2_i16m1_tu(__VA_ARGS__) -#define vredand_vs_i16m4_i16m1(...) __riscv_vredand_vs_i16m4_i16m1_tu(__VA_ARGS__) -#define vredand_vs_i16m8_i16m1(...) __riscv_vredand_vs_i16m8_i16m1_tu(__VA_ARGS__) -#define vredand_vs_i32mf2_i32m1(...) __riscv_vredand_vs_i32mf2_i32m1_tu(__VA_ARGS__) -#define vredand_vs_i32m1_i32m1(...) __riscv_vredand_vs_i32m1_i32m1_tu(__VA_ARGS__) -#define vredand_vs_i32m2_i32m1(...) __riscv_vredand_vs_i32m2_i32m1_tu(__VA_ARGS__) -#define vredand_vs_i32m4_i32m1(...) __riscv_vredand_vs_i32m4_i32m1_tu(__VA_ARGS__) -#define vredand_vs_i32m8_i32m1(...) __riscv_vredand_vs_i32m8_i32m1_tu(__VA_ARGS__) -#define vredand_vs_i64m1_i64m1(...) __riscv_vredand_vs_i64m1_i64m1_tu(__VA_ARGS__) -#define vredand_vs_i64m2_i64m1(...) __riscv_vredand_vs_i64m2_i64m1_tu(__VA_ARGS__) -#define vredand_vs_i64m4_i64m1(...) __riscv_vredand_vs_i64m4_i64m1_tu(__VA_ARGS__) -#define vredand_vs_i64m8_i64m1(...) __riscv_vredand_vs_i64m8_i64m1_tu(__VA_ARGS__) -#define vredor_vs_i8mf8_i8m1(...) __riscv_vredor_vs_i8mf8_i8m1_tu(__VA_ARGS__) -#define vredor_vs_i8mf4_i8m1(...) __riscv_vredor_vs_i8mf4_i8m1_tu(__VA_ARGS__) -#define vredor_vs_i8mf2_i8m1(...) __riscv_vredor_vs_i8mf2_i8m1_tu(__VA_ARGS__) -#define vredor_vs_i8m1_i8m1(...) __riscv_vredor_vs_i8m1_i8m1_tu(__VA_ARGS__) -#define vredor_vs_i8m2_i8m1(...) __riscv_vredor_vs_i8m2_i8m1_tu(__VA_ARGS__) -#define vredor_vs_i8m4_i8m1(...) __riscv_vredor_vs_i8m4_i8m1_tu(__VA_ARGS__) -#define vredor_vs_i8m8_i8m1(...) __riscv_vredor_vs_i8m8_i8m1_tu(__VA_ARGS__) -#define vredor_vs_i16mf4_i16m1(...) __riscv_vredor_vs_i16mf4_i16m1_tu(__VA_ARGS__) -#define vredor_vs_i16mf2_i16m1(...) __riscv_vredor_vs_i16mf2_i16m1_tu(__VA_ARGS__) -#define vredor_vs_i16m1_i16m1(...) __riscv_vredor_vs_i16m1_i16m1_tu(__VA_ARGS__) -#define vredor_vs_i16m2_i16m1(...) __riscv_vredor_vs_i16m2_i16m1_tu(__VA_ARGS__) -#define vredor_vs_i16m4_i16m1(...) __riscv_vredor_vs_i16m4_i16m1_tu(__VA_ARGS__) -#define vredor_vs_i16m8_i16m1(...) __riscv_vredor_vs_i16m8_i16m1_tu(__VA_ARGS__) -#define vredor_vs_i32mf2_i32m1(...) __riscv_vredor_vs_i32mf2_i32m1_tu(__VA_ARGS__) -#define vredor_vs_i32m1_i32m1(...) __riscv_vredor_vs_i32m1_i32m1_tu(__VA_ARGS__) -#define vredor_vs_i32m2_i32m1(...) __riscv_vredor_vs_i32m2_i32m1_tu(__VA_ARGS__) -#define vredor_vs_i32m4_i32m1(...) __riscv_vredor_vs_i32m4_i32m1_tu(__VA_ARGS__) -#define vredor_vs_i32m8_i32m1(...) __riscv_vredor_vs_i32m8_i32m1_tu(__VA_ARGS__) -#define vredor_vs_i64m1_i64m1(...) __riscv_vredor_vs_i64m1_i64m1_tu(__VA_ARGS__) -#define vredor_vs_i64m2_i64m1(...) __riscv_vredor_vs_i64m2_i64m1_tu(__VA_ARGS__) -#define vredor_vs_i64m4_i64m1(...) __riscv_vredor_vs_i64m4_i64m1_tu(__VA_ARGS__) -#define vredor_vs_i64m8_i64m1(...) __riscv_vredor_vs_i64m8_i64m1_tu(__VA_ARGS__) -#define vredxor_vs_i8mf8_i8m1(...) __riscv_vredxor_vs_i8mf8_i8m1_tu(__VA_ARGS__) -#define vredxor_vs_i8mf4_i8m1(...) __riscv_vredxor_vs_i8mf4_i8m1_tu(__VA_ARGS__) -#define vredxor_vs_i8mf2_i8m1(...) __riscv_vredxor_vs_i8mf2_i8m1_tu(__VA_ARGS__) -#define vredxor_vs_i8m1_i8m1(...) __riscv_vredxor_vs_i8m1_i8m1_tu(__VA_ARGS__) -#define vredxor_vs_i8m2_i8m1(...) __riscv_vredxor_vs_i8m2_i8m1_tu(__VA_ARGS__) -#define vredxor_vs_i8m4_i8m1(...) __riscv_vredxor_vs_i8m4_i8m1_tu(__VA_ARGS__) -#define vredxor_vs_i8m8_i8m1(...) __riscv_vredxor_vs_i8m8_i8m1_tu(__VA_ARGS__) -#define vredxor_vs_i16mf4_i16m1(...) __riscv_vredxor_vs_i16mf4_i16m1_tu(__VA_ARGS__) -#define vredxor_vs_i16mf2_i16m1(...) __riscv_vredxor_vs_i16mf2_i16m1_tu(__VA_ARGS__) -#define vredxor_vs_i16m1_i16m1(...) __riscv_vredxor_vs_i16m1_i16m1_tu(__VA_ARGS__) -#define vredxor_vs_i16m2_i16m1(...) __riscv_vredxor_vs_i16m2_i16m1_tu(__VA_ARGS__) -#define vredxor_vs_i16m4_i16m1(...) __riscv_vredxor_vs_i16m4_i16m1_tu(__VA_ARGS__) -#define vredxor_vs_i16m8_i16m1(...) __riscv_vredxor_vs_i16m8_i16m1_tu(__VA_ARGS__) -#define vredxor_vs_i32mf2_i32m1(...) __riscv_vredxor_vs_i32mf2_i32m1_tu(__VA_ARGS__) -#define vredxor_vs_i32m1_i32m1(...) __riscv_vredxor_vs_i32m1_i32m1_tu(__VA_ARGS__) -#define vredxor_vs_i32m2_i32m1(...) __riscv_vredxor_vs_i32m2_i32m1_tu(__VA_ARGS__) -#define vredxor_vs_i32m4_i32m1(...) __riscv_vredxor_vs_i32m4_i32m1_tu(__VA_ARGS__) -#define vredxor_vs_i32m8_i32m1(...) __riscv_vredxor_vs_i32m8_i32m1_tu(__VA_ARGS__) -#define vredxor_vs_i64m1_i64m1(...) __riscv_vredxor_vs_i64m1_i64m1_tu(__VA_ARGS__) -#define vredxor_vs_i64m2_i64m1(...) __riscv_vredxor_vs_i64m2_i64m1_tu(__VA_ARGS__) -#define vredxor_vs_i64m4_i64m1(...) __riscv_vredxor_vs_i64m4_i64m1_tu(__VA_ARGS__) -#define vredxor_vs_i64m8_i64m1(...) __riscv_vredxor_vs_i64m8_i64m1_tu(__VA_ARGS__) -#define vredsum_vs_u8mf8_u8m1(...) __riscv_vredsum_vs_u8mf8_u8m1_tu(__VA_ARGS__) -#define vredsum_vs_u8mf4_u8m1(...) __riscv_vredsum_vs_u8mf4_u8m1_tu(__VA_ARGS__) -#define vredsum_vs_u8mf2_u8m1(...) __riscv_vredsum_vs_u8mf2_u8m1_tu(__VA_ARGS__) -#define vredsum_vs_u8m1_u8m1(...) __riscv_vredsum_vs_u8m1_u8m1_tu(__VA_ARGS__) -#define vredsum_vs_u8m2_u8m1(...) __riscv_vredsum_vs_u8m2_u8m1_tu(__VA_ARGS__) -#define vredsum_vs_u8m4_u8m1(...) __riscv_vredsum_vs_u8m4_u8m1_tu(__VA_ARGS__) -#define vredsum_vs_u8m8_u8m1(...) __riscv_vredsum_vs_u8m8_u8m1_tu(__VA_ARGS__) -#define vredsum_vs_u16mf4_u16m1(...) __riscv_vredsum_vs_u16mf4_u16m1_tu(__VA_ARGS__) -#define vredsum_vs_u16mf2_u16m1(...) __riscv_vredsum_vs_u16mf2_u16m1_tu(__VA_ARGS__) -#define vredsum_vs_u16m1_u16m1(...) __riscv_vredsum_vs_u16m1_u16m1_tu(__VA_ARGS__) -#define vredsum_vs_u16m2_u16m1(...) __riscv_vredsum_vs_u16m2_u16m1_tu(__VA_ARGS__) -#define vredsum_vs_u16m4_u16m1(...) __riscv_vredsum_vs_u16m4_u16m1_tu(__VA_ARGS__) -#define vredsum_vs_u16m8_u16m1(...) __riscv_vredsum_vs_u16m8_u16m1_tu(__VA_ARGS__) -#define vredsum_vs_u32mf2_u32m1(...) __riscv_vredsum_vs_u32mf2_u32m1_tu(__VA_ARGS__) -#define vredsum_vs_u32m1_u32m1(...) __riscv_vredsum_vs_u32m1_u32m1_tu(__VA_ARGS__) -#define vredsum_vs_u32m2_u32m1(...) __riscv_vredsum_vs_u32m2_u32m1_tu(__VA_ARGS__) -#define vredsum_vs_u32m4_u32m1(...) __riscv_vredsum_vs_u32m4_u32m1_tu(__VA_ARGS__) -#define vredsum_vs_u32m8_u32m1(...) __riscv_vredsum_vs_u32m8_u32m1_tu(__VA_ARGS__) -#define vredsum_vs_u64m1_u64m1(...) __riscv_vredsum_vs_u64m1_u64m1_tu(__VA_ARGS__) -#define vredsum_vs_u64m2_u64m1(...) __riscv_vredsum_vs_u64m2_u64m1_tu(__VA_ARGS__) -#define vredsum_vs_u64m4_u64m1(...) __riscv_vredsum_vs_u64m4_u64m1_tu(__VA_ARGS__) -#define vredsum_vs_u64m8_u64m1(...) __riscv_vredsum_vs_u64m8_u64m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u8mf8_u8m1(...) __riscv_vredmaxu_vs_u8mf8_u8m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u8mf4_u8m1(...) __riscv_vredmaxu_vs_u8mf4_u8m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u8mf2_u8m1(...) __riscv_vredmaxu_vs_u8mf2_u8m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u8m1_u8m1(...) __riscv_vredmaxu_vs_u8m1_u8m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u8m2_u8m1(...) __riscv_vredmaxu_vs_u8m2_u8m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u8m4_u8m1(...) __riscv_vredmaxu_vs_u8m4_u8m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u8m8_u8m1(...) __riscv_vredmaxu_vs_u8m8_u8m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u16mf4_u16m1(...) __riscv_vredmaxu_vs_u16mf4_u16m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u16mf2_u16m1(...) __riscv_vredmaxu_vs_u16mf2_u16m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u16m1_u16m1(...) __riscv_vredmaxu_vs_u16m1_u16m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u16m2_u16m1(...) __riscv_vredmaxu_vs_u16m2_u16m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u16m4_u16m1(...) __riscv_vredmaxu_vs_u16m4_u16m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u16m8_u16m1(...) __riscv_vredmaxu_vs_u16m8_u16m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u32mf2_u32m1(...) __riscv_vredmaxu_vs_u32mf2_u32m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u32m1_u32m1(...) __riscv_vredmaxu_vs_u32m1_u32m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u32m2_u32m1(...) __riscv_vredmaxu_vs_u32m2_u32m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u32m4_u32m1(...) __riscv_vredmaxu_vs_u32m4_u32m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u32m8_u32m1(...) __riscv_vredmaxu_vs_u32m8_u32m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u64m1_u64m1(...) __riscv_vredmaxu_vs_u64m1_u64m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u64m2_u64m1(...) __riscv_vredmaxu_vs_u64m2_u64m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u64m4_u64m1(...) __riscv_vredmaxu_vs_u64m4_u64m1_tu(__VA_ARGS__) -#define vredmaxu_vs_u64m8_u64m1(...) __riscv_vredmaxu_vs_u64m8_u64m1_tu(__VA_ARGS__) -#define vredminu_vs_u8mf8_u8m1(...) __riscv_vredminu_vs_u8mf8_u8m1_tu(__VA_ARGS__) -#define vredminu_vs_u8mf4_u8m1(...) __riscv_vredminu_vs_u8mf4_u8m1_tu(__VA_ARGS__) -#define vredminu_vs_u8mf2_u8m1(...) __riscv_vredminu_vs_u8mf2_u8m1_tu(__VA_ARGS__) -#define vredminu_vs_u8m1_u8m1(...) __riscv_vredminu_vs_u8m1_u8m1_tu(__VA_ARGS__) -#define vredminu_vs_u8m2_u8m1(...) __riscv_vredminu_vs_u8m2_u8m1_tu(__VA_ARGS__) -#define vredminu_vs_u8m4_u8m1(...) __riscv_vredminu_vs_u8m4_u8m1_tu(__VA_ARGS__) -#define vredminu_vs_u8m8_u8m1(...) __riscv_vredminu_vs_u8m8_u8m1_tu(__VA_ARGS__) -#define vredminu_vs_u16mf4_u16m1(...) __riscv_vredminu_vs_u16mf4_u16m1_tu(__VA_ARGS__) -#define vredminu_vs_u16mf2_u16m1(...) __riscv_vredminu_vs_u16mf2_u16m1_tu(__VA_ARGS__) -#define vredminu_vs_u16m1_u16m1(...) __riscv_vredminu_vs_u16m1_u16m1_tu(__VA_ARGS__) -#define vredminu_vs_u16m2_u16m1(...) __riscv_vredminu_vs_u16m2_u16m1_tu(__VA_ARGS__) -#define vredminu_vs_u16m4_u16m1(...) __riscv_vredminu_vs_u16m4_u16m1_tu(__VA_ARGS__) -#define vredminu_vs_u16m8_u16m1(...) __riscv_vredminu_vs_u16m8_u16m1_tu(__VA_ARGS__) -#define vredminu_vs_u32mf2_u32m1(...) __riscv_vredminu_vs_u32mf2_u32m1_tu(__VA_ARGS__) -#define vredminu_vs_u32m1_u32m1(...) __riscv_vredminu_vs_u32m1_u32m1_tu(__VA_ARGS__) -#define vredminu_vs_u32m2_u32m1(...) __riscv_vredminu_vs_u32m2_u32m1_tu(__VA_ARGS__) -#define vredminu_vs_u32m4_u32m1(...) __riscv_vredminu_vs_u32m4_u32m1_tu(__VA_ARGS__) -#define vredminu_vs_u32m8_u32m1(...) __riscv_vredminu_vs_u32m8_u32m1_tu(__VA_ARGS__) -#define vredminu_vs_u64m1_u64m1(...) __riscv_vredminu_vs_u64m1_u64m1_tu(__VA_ARGS__) -#define vredminu_vs_u64m2_u64m1(...) __riscv_vredminu_vs_u64m2_u64m1_tu(__VA_ARGS__) -#define vredminu_vs_u64m4_u64m1(...) __riscv_vredminu_vs_u64m4_u64m1_tu(__VA_ARGS__) -#define vredminu_vs_u64m8_u64m1(...) __riscv_vredminu_vs_u64m8_u64m1_tu(__VA_ARGS__) -#define vredand_vs_u8mf8_u8m1(...) __riscv_vredand_vs_u8mf8_u8m1_tu(__VA_ARGS__) -#define vredand_vs_u8mf4_u8m1(...) __riscv_vredand_vs_u8mf4_u8m1_tu(__VA_ARGS__) -#define vredand_vs_u8mf2_u8m1(...) __riscv_vredand_vs_u8mf2_u8m1_tu(__VA_ARGS__) -#define vredand_vs_u8m1_u8m1(...) __riscv_vredand_vs_u8m1_u8m1_tu(__VA_ARGS__) -#define vredand_vs_u8m2_u8m1(...) __riscv_vredand_vs_u8m2_u8m1_tu(__VA_ARGS__) -#define vredand_vs_u8m4_u8m1(...) __riscv_vredand_vs_u8m4_u8m1_tu(__VA_ARGS__) -#define vredand_vs_u8m8_u8m1(...) __riscv_vredand_vs_u8m8_u8m1_tu(__VA_ARGS__) -#define vredand_vs_u16mf4_u16m1(...) __riscv_vredand_vs_u16mf4_u16m1_tu(__VA_ARGS__) -#define vredand_vs_u16mf2_u16m1(...) __riscv_vredand_vs_u16mf2_u16m1_tu(__VA_ARGS__) -#define vredand_vs_u16m1_u16m1(...) __riscv_vredand_vs_u16m1_u16m1_tu(__VA_ARGS__) -#define vredand_vs_u16m2_u16m1(...) __riscv_vredand_vs_u16m2_u16m1_tu(__VA_ARGS__) -#define vredand_vs_u16m4_u16m1(...) __riscv_vredand_vs_u16m4_u16m1_tu(__VA_ARGS__) -#define vredand_vs_u16m8_u16m1(...) __riscv_vredand_vs_u16m8_u16m1_tu(__VA_ARGS__) -#define vredand_vs_u32mf2_u32m1(...) __riscv_vredand_vs_u32mf2_u32m1_tu(__VA_ARGS__) -#define vredand_vs_u32m1_u32m1(...) __riscv_vredand_vs_u32m1_u32m1_tu(__VA_ARGS__) -#define vredand_vs_u32m2_u32m1(...) __riscv_vredand_vs_u32m2_u32m1_tu(__VA_ARGS__) -#define vredand_vs_u32m4_u32m1(...) __riscv_vredand_vs_u32m4_u32m1_tu(__VA_ARGS__) -#define vredand_vs_u32m8_u32m1(...) __riscv_vredand_vs_u32m8_u32m1_tu(__VA_ARGS__) -#define vredand_vs_u64m1_u64m1(...) __riscv_vredand_vs_u64m1_u64m1_tu(__VA_ARGS__) -#define vredand_vs_u64m2_u64m1(...) __riscv_vredand_vs_u64m2_u64m1_tu(__VA_ARGS__) -#define vredand_vs_u64m4_u64m1(...) __riscv_vredand_vs_u64m4_u64m1_tu(__VA_ARGS__) -#define vredand_vs_u64m8_u64m1(...) __riscv_vredand_vs_u64m8_u64m1_tu(__VA_ARGS__) -#define vredor_vs_u8mf8_u8m1(...) __riscv_vredor_vs_u8mf8_u8m1_tu(__VA_ARGS__) -#define vredor_vs_u8mf4_u8m1(...) __riscv_vredor_vs_u8mf4_u8m1_tu(__VA_ARGS__) -#define vredor_vs_u8mf2_u8m1(...) __riscv_vredor_vs_u8mf2_u8m1_tu(__VA_ARGS__) -#define vredor_vs_u8m1_u8m1(...) __riscv_vredor_vs_u8m1_u8m1_tu(__VA_ARGS__) -#define vredor_vs_u8m2_u8m1(...) __riscv_vredor_vs_u8m2_u8m1_tu(__VA_ARGS__) -#define vredor_vs_u8m4_u8m1(...) __riscv_vredor_vs_u8m4_u8m1_tu(__VA_ARGS__) -#define vredor_vs_u8m8_u8m1(...) __riscv_vredor_vs_u8m8_u8m1_tu(__VA_ARGS__) -#define vredor_vs_u16mf4_u16m1(...) __riscv_vredor_vs_u16mf4_u16m1_tu(__VA_ARGS__) -#define vredor_vs_u16mf2_u16m1(...) __riscv_vredor_vs_u16mf2_u16m1_tu(__VA_ARGS__) -#define vredor_vs_u16m1_u16m1(...) __riscv_vredor_vs_u16m1_u16m1_tu(__VA_ARGS__) -#define vredor_vs_u16m2_u16m1(...) __riscv_vredor_vs_u16m2_u16m1_tu(__VA_ARGS__) -#define vredor_vs_u16m4_u16m1(...) __riscv_vredor_vs_u16m4_u16m1_tu(__VA_ARGS__) -#define vredor_vs_u16m8_u16m1(...) __riscv_vredor_vs_u16m8_u16m1_tu(__VA_ARGS__) -#define vredor_vs_u32mf2_u32m1(...) __riscv_vredor_vs_u32mf2_u32m1_tu(__VA_ARGS__) -#define vredor_vs_u32m1_u32m1(...) __riscv_vredor_vs_u32m1_u32m1_tu(__VA_ARGS__) -#define vredor_vs_u32m2_u32m1(...) __riscv_vredor_vs_u32m2_u32m1_tu(__VA_ARGS__) -#define vredor_vs_u32m4_u32m1(...) __riscv_vredor_vs_u32m4_u32m1_tu(__VA_ARGS__) -#define vredor_vs_u32m8_u32m1(...) __riscv_vredor_vs_u32m8_u32m1_tu(__VA_ARGS__) -#define vredor_vs_u64m1_u64m1(...) __riscv_vredor_vs_u64m1_u64m1_tu(__VA_ARGS__) -#define vredor_vs_u64m2_u64m1(...) __riscv_vredor_vs_u64m2_u64m1_tu(__VA_ARGS__) -#define vredor_vs_u64m4_u64m1(...) __riscv_vredor_vs_u64m4_u64m1_tu(__VA_ARGS__) -#define vredor_vs_u64m8_u64m1(...) __riscv_vredor_vs_u64m8_u64m1_tu(__VA_ARGS__) -#define vredxor_vs_u8mf8_u8m1(...) __riscv_vredxor_vs_u8mf8_u8m1_tu(__VA_ARGS__) -#define vredxor_vs_u8mf4_u8m1(...) __riscv_vredxor_vs_u8mf4_u8m1_tu(__VA_ARGS__) -#define vredxor_vs_u8mf2_u8m1(...) __riscv_vredxor_vs_u8mf2_u8m1_tu(__VA_ARGS__) -#define vredxor_vs_u8m1_u8m1(...) __riscv_vredxor_vs_u8m1_u8m1_tu(__VA_ARGS__) -#define vredxor_vs_u8m2_u8m1(...) __riscv_vredxor_vs_u8m2_u8m1_tu(__VA_ARGS__) -#define vredxor_vs_u8m4_u8m1(...) __riscv_vredxor_vs_u8m4_u8m1_tu(__VA_ARGS__) -#define vredxor_vs_u8m8_u8m1(...) __riscv_vredxor_vs_u8m8_u8m1_tu(__VA_ARGS__) -#define vredxor_vs_u16mf4_u16m1(...) __riscv_vredxor_vs_u16mf4_u16m1_tu(__VA_ARGS__) -#define vredxor_vs_u16mf2_u16m1(...) __riscv_vredxor_vs_u16mf2_u16m1_tu(__VA_ARGS__) -#define vredxor_vs_u16m1_u16m1(...) __riscv_vredxor_vs_u16m1_u16m1_tu(__VA_ARGS__) -#define vredxor_vs_u16m2_u16m1(...) __riscv_vredxor_vs_u16m2_u16m1_tu(__VA_ARGS__) -#define vredxor_vs_u16m4_u16m1(...) __riscv_vredxor_vs_u16m4_u16m1_tu(__VA_ARGS__) -#define vredxor_vs_u16m8_u16m1(...) __riscv_vredxor_vs_u16m8_u16m1_tu(__VA_ARGS__) -#define vredxor_vs_u32mf2_u32m1(...) __riscv_vredxor_vs_u32mf2_u32m1_tu(__VA_ARGS__) -#define vredxor_vs_u32m1_u32m1(...) __riscv_vredxor_vs_u32m1_u32m1_tu(__VA_ARGS__) -#define vredxor_vs_u32m2_u32m1(...) __riscv_vredxor_vs_u32m2_u32m1_tu(__VA_ARGS__) -#define vredxor_vs_u32m4_u32m1(...) __riscv_vredxor_vs_u32m4_u32m1_tu(__VA_ARGS__) -#define vredxor_vs_u32m8_u32m1(...) __riscv_vredxor_vs_u32m8_u32m1_tu(__VA_ARGS__) -#define vredxor_vs_u64m1_u64m1(...) __riscv_vredxor_vs_u64m1_u64m1_tu(__VA_ARGS__) -#define vredxor_vs_u64m2_u64m1(...) __riscv_vredxor_vs_u64m2_u64m1_tu(__VA_ARGS__) -#define vredxor_vs_u64m4_u64m1(...) __riscv_vredxor_vs_u64m4_u64m1_tu(__VA_ARGS__) -#define vredxor_vs_u64m8_u64m1(...) __riscv_vredxor_vs_u64m8_u64m1_tu(__VA_ARGS__) -// masked functions -#define vredsum_vs_i8mf8_i8m1_m(...) __riscv_vredsum_vs_i8mf8_i8m1_tum(__VA_ARGS__) -#define vredsum_vs_i8mf4_i8m1_m(...) __riscv_vredsum_vs_i8mf4_i8m1_tum(__VA_ARGS__) -#define vredsum_vs_i8mf2_i8m1_m(...) __riscv_vredsum_vs_i8mf2_i8m1_tum(__VA_ARGS__) -#define vredsum_vs_i8m1_i8m1_m(...) __riscv_vredsum_vs_i8m1_i8m1_tum(__VA_ARGS__) -#define vredsum_vs_i8m2_i8m1_m(...) __riscv_vredsum_vs_i8m2_i8m1_tum(__VA_ARGS__) -#define vredsum_vs_i8m4_i8m1_m(...) __riscv_vredsum_vs_i8m4_i8m1_tum(__VA_ARGS__) -#define vredsum_vs_i8m8_i8m1_m(...) __riscv_vredsum_vs_i8m8_i8m1_tum(__VA_ARGS__) -#define vredsum_vs_i16mf4_i16m1_m(...) __riscv_vredsum_vs_i16mf4_i16m1_tum(__VA_ARGS__) -#define vredsum_vs_i16mf2_i16m1_m(...) __riscv_vredsum_vs_i16mf2_i16m1_tum(__VA_ARGS__) -#define vredsum_vs_i16m1_i16m1_m(...) __riscv_vredsum_vs_i16m1_i16m1_tum(__VA_ARGS__) -#define vredsum_vs_i16m2_i16m1_m(...) __riscv_vredsum_vs_i16m2_i16m1_tum(__VA_ARGS__) -#define vredsum_vs_i16m4_i16m1_m(...) __riscv_vredsum_vs_i16m4_i16m1_tum(__VA_ARGS__) -#define vredsum_vs_i16m8_i16m1_m(...) __riscv_vredsum_vs_i16m8_i16m1_tum(__VA_ARGS__) -#define vredsum_vs_i32mf2_i32m1_m(...) __riscv_vredsum_vs_i32mf2_i32m1_tum(__VA_ARGS__) -#define vredsum_vs_i32m1_i32m1_m(...) __riscv_vredsum_vs_i32m1_i32m1_tum(__VA_ARGS__) -#define vredsum_vs_i32m2_i32m1_m(...) __riscv_vredsum_vs_i32m2_i32m1_tum(__VA_ARGS__) -#define vredsum_vs_i32m4_i32m1_m(...) __riscv_vredsum_vs_i32m4_i32m1_tum(__VA_ARGS__) -#define vredsum_vs_i32m8_i32m1_m(...) __riscv_vredsum_vs_i32m8_i32m1_tum(__VA_ARGS__) -#define vredsum_vs_i64m1_i64m1_m(...) __riscv_vredsum_vs_i64m1_i64m1_tum(__VA_ARGS__) -#define vredsum_vs_i64m2_i64m1_m(...) __riscv_vredsum_vs_i64m2_i64m1_tum(__VA_ARGS__) -#define vredsum_vs_i64m4_i64m1_m(...) __riscv_vredsum_vs_i64m4_i64m1_tum(__VA_ARGS__) -#define vredsum_vs_i64m8_i64m1_m(...) __riscv_vredsum_vs_i64m8_i64m1_tum(__VA_ARGS__) -#define vredmax_vs_i8mf8_i8m1_m(...) __riscv_vredmax_vs_i8mf8_i8m1_tum(__VA_ARGS__) -#define vredmax_vs_i8mf4_i8m1_m(...) __riscv_vredmax_vs_i8mf4_i8m1_tum(__VA_ARGS__) -#define vredmax_vs_i8mf2_i8m1_m(...) __riscv_vredmax_vs_i8mf2_i8m1_tum(__VA_ARGS__) -#define vredmax_vs_i8m1_i8m1_m(...) __riscv_vredmax_vs_i8m1_i8m1_tum(__VA_ARGS__) -#define vredmax_vs_i8m2_i8m1_m(...) __riscv_vredmax_vs_i8m2_i8m1_tum(__VA_ARGS__) -#define vredmax_vs_i8m4_i8m1_m(...) __riscv_vredmax_vs_i8m4_i8m1_tum(__VA_ARGS__) -#define vredmax_vs_i8m8_i8m1_m(...) __riscv_vredmax_vs_i8m8_i8m1_tum(__VA_ARGS__) -#define vredmax_vs_i16mf4_i16m1_m(...) __riscv_vredmax_vs_i16mf4_i16m1_tum(__VA_ARGS__) -#define vredmax_vs_i16mf2_i16m1_m(...) __riscv_vredmax_vs_i16mf2_i16m1_tum(__VA_ARGS__) -#define vredmax_vs_i16m1_i16m1_m(...) __riscv_vredmax_vs_i16m1_i16m1_tum(__VA_ARGS__) -#define vredmax_vs_i16m2_i16m1_m(...) __riscv_vredmax_vs_i16m2_i16m1_tum(__VA_ARGS__) -#define vredmax_vs_i16m4_i16m1_m(...) __riscv_vredmax_vs_i16m4_i16m1_tum(__VA_ARGS__) -#define vredmax_vs_i16m8_i16m1_m(...) __riscv_vredmax_vs_i16m8_i16m1_tum(__VA_ARGS__) -#define vredmax_vs_i32mf2_i32m1_m(...) __riscv_vredmax_vs_i32mf2_i32m1_tum(__VA_ARGS__) -#define vredmax_vs_i32m1_i32m1_m(...) __riscv_vredmax_vs_i32m1_i32m1_tum(__VA_ARGS__) -#define vredmax_vs_i32m2_i32m1_m(...) __riscv_vredmax_vs_i32m2_i32m1_tum(__VA_ARGS__) -#define vredmax_vs_i32m4_i32m1_m(...) __riscv_vredmax_vs_i32m4_i32m1_tum(__VA_ARGS__) -#define vredmax_vs_i32m8_i32m1_m(...) __riscv_vredmax_vs_i32m8_i32m1_tum(__VA_ARGS__) -#define vredmax_vs_i64m1_i64m1_m(...) __riscv_vredmax_vs_i64m1_i64m1_tum(__VA_ARGS__) -#define vredmax_vs_i64m2_i64m1_m(...) __riscv_vredmax_vs_i64m2_i64m1_tum(__VA_ARGS__) -#define vredmax_vs_i64m4_i64m1_m(...) __riscv_vredmax_vs_i64m4_i64m1_tum(__VA_ARGS__) -#define vredmax_vs_i64m8_i64m1_m(...) __riscv_vredmax_vs_i64m8_i64m1_tum(__VA_ARGS__) -#define vredmin_vs_i8mf8_i8m1_m(...) __riscv_vredmin_vs_i8mf8_i8m1_tum(__VA_ARGS__) -#define vredmin_vs_i8mf4_i8m1_m(...) __riscv_vredmin_vs_i8mf4_i8m1_tum(__VA_ARGS__) -#define vredmin_vs_i8mf2_i8m1_m(...) __riscv_vredmin_vs_i8mf2_i8m1_tum(__VA_ARGS__) -#define vredmin_vs_i8m1_i8m1_m(...) __riscv_vredmin_vs_i8m1_i8m1_tum(__VA_ARGS__) -#define vredmin_vs_i8m2_i8m1_m(...) __riscv_vredmin_vs_i8m2_i8m1_tum(__VA_ARGS__) -#define vredmin_vs_i8m4_i8m1_m(...) __riscv_vredmin_vs_i8m4_i8m1_tum(__VA_ARGS__) -#define vredmin_vs_i8m8_i8m1_m(...) __riscv_vredmin_vs_i8m8_i8m1_tum(__VA_ARGS__) -#define vredmin_vs_i16mf4_i16m1_m(...) __riscv_vredmin_vs_i16mf4_i16m1_tum(__VA_ARGS__) -#define vredmin_vs_i16mf2_i16m1_m(...) __riscv_vredmin_vs_i16mf2_i16m1_tum(__VA_ARGS__) -#define vredmin_vs_i16m1_i16m1_m(...) __riscv_vredmin_vs_i16m1_i16m1_tum(__VA_ARGS__) -#define vredmin_vs_i16m2_i16m1_m(...) __riscv_vredmin_vs_i16m2_i16m1_tum(__VA_ARGS__) -#define vredmin_vs_i16m4_i16m1_m(...) __riscv_vredmin_vs_i16m4_i16m1_tum(__VA_ARGS__) -#define vredmin_vs_i16m8_i16m1_m(...) __riscv_vredmin_vs_i16m8_i16m1_tum(__VA_ARGS__) -#define vredmin_vs_i32mf2_i32m1_m(...) __riscv_vredmin_vs_i32mf2_i32m1_tum(__VA_ARGS__) -#define vredmin_vs_i32m1_i32m1_m(...) __riscv_vredmin_vs_i32m1_i32m1_tum(__VA_ARGS__) -#define vredmin_vs_i32m2_i32m1_m(...) __riscv_vredmin_vs_i32m2_i32m1_tum(__VA_ARGS__) -#define vredmin_vs_i32m4_i32m1_m(...) __riscv_vredmin_vs_i32m4_i32m1_tum(__VA_ARGS__) -#define vredmin_vs_i32m8_i32m1_m(...) __riscv_vredmin_vs_i32m8_i32m1_tum(__VA_ARGS__) -#define vredmin_vs_i64m1_i64m1_m(...) __riscv_vredmin_vs_i64m1_i64m1_tum(__VA_ARGS__) -#define vredmin_vs_i64m2_i64m1_m(...) __riscv_vredmin_vs_i64m2_i64m1_tum(__VA_ARGS__) -#define vredmin_vs_i64m4_i64m1_m(...) __riscv_vredmin_vs_i64m4_i64m1_tum(__VA_ARGS__) -#define vredmin_vs_i64m8_i64m1_m(...) __riscv_vredmin_vs_i64m8_i64m1_tum(__VA_ARGS__) -#define vredand_vs_i8mf8_i8m1_m(...) __riscv_vredand_vs_i8mf8_i8m1_tum(__VA_ARGS__) -#define vredand_vs_i8mf4_i8m1_m(...) __riscv_vredand_vs_i8mf4_i8m1_tum(__VA_ARGS__) -#define vredand_vs_i8mf2_i8m1_m(...) __riscv_vredand_vs_i8mf2_i8m1_tum(__VA_ARGS__) -#define vredand_vs_i8m1_i8m1_m(...) __riscv_vredand_vs_i8m1_i8m1_tum(__VA_ARGS__) -#define vredand_vs_i8m2_i8m1_m(...) __riscv_vredand_vs_i8m2_i8m1_tum(__VA_ARGS__) -#define vredand_vs_i8m4_i8m1_m(...) __riscv_vredand_vs_i8m4_i8m1_tum(__VA_ARGS__) -#define vredand_vs_i8m8_i8m1_m(...) __riscv_vredand_vs_i8m8_i8m1_tum(__VA_ARGS__) -#define vredand_vs_i16mf4_i16m1_m(...) __riscv_vredand_vs_i16mf4_i16m1_tum(__VA_ARGS__) -#define vredand_vs_i16mf2_i16m1_m(...) __riscv_vredand_vs_i16mf2_i16m1_tum(__VA_ARGS__) -#define vredand_vs_i16m1_i16m1_m(...) __riscv_vredand_vs_i16m1_i16m1_tum(__VA_ARGS__) -#define vredand_vs_i16m2_i16m1_m(...) __riscv_vredand_vs_i16m2_i16m1_tum(__VA_ARGS__) -#define vredand_vs_i16m4_i16m1_m(...) __riscv_vredand_vs_i16m4_i16m1_tum(__VA_ARGS__) -#define vredand_vs_i16m8_i16m1_m(...) __riscv_vredand_vs_i16m8_i16m1_tum(__VA_ARGS__) -#define vredand_vs_i32mf2_i32m1_m(...) __riscv_vredand_vs_i32mf2_i32m1_tum(__VA_ARGS__) -#define vredand_vs_i32m1_i32m1_m(...) __riscv_vredand_vs_i32m1_i32m1_tum(__VA_ARGS__) -#define vredand_vs_i32m2_i32m1_m(...) __riscv_vredand_vs_i32m2_i32m1_tum(__VA_ARGS__) -#define vredand_vs_i32m4_i32m1_m(...) __riscv_vredand_vs_i32m4_i32m1_tum(__VA_ARGS__) -#define vredand_vs_i32m8_i32m1_m(...) __riscv_vredand_vs_i32m8_i32m1_tum(__VA_ARGS__) -#define vredand_vs_i64m1_i64m1_m(...) __riscv_vredand_vs_i64m1_i64m1_tum(__VA_ARGS__) -#define vredand_vs_i64m2_i64m1_m(...) __riscv_vredand_vs_i64m2_i64m1_tum(__VA_ARGS__) -#define vredand_vs_i64m4_i64m1_m(...) __riscv_vredand_vs_i64m4_i64m1_tum(__VA_ARGS__) -#define vredand_vs_i64m8_i64m1_m(...) __riscv_vredand_vs_i64m8_i64m1_tum(__VA_ARGS__) -#define vredor_vs_i8mf8_i8m1_m(...) __riscv_vredor_vs_i8mf8_i8m1_tum(__VA_ARGS__) -#define vredor_vs_i8mf4_i8m1_m(...) __riscv_vredor_vs_i8mf4_i8m1_tum(__VA_ARGS__) -#define vredor_vs_i8mf2_i8m1_m(...) __riscv_vredor_vs_i8mf2_i8m1_tum(__VA_ARGS__) -#define vredor_vs_i8m1_i8m1_m(...) __riscv_vredor_vs_i8m1_i8m1_tum(__VA_ARGS__) -#define vredor_vs_i8m2_i8m1_m(...) __riscv_vredor_vs_i8m2_i8m1_tum(__VA_ARGS__) -#define vredor_vs_i8m4_i8m1_m(...) __riscv_vredor_vs_i8m4_i8m1_tum(__VA_ARGS__) -#define vredor_vs_i8m8_i8m1_m(...) __riscv_vredor_vs_i8m8_i8m1_tum(__VA_ARGS__) -#define vredor_vs_i16mf4_i16m1_m(...) __riscv_vredor_vs_i16mf4_i16m1_tum(__VA_ARGS__) -#define vredor_vs_i16mf2_i16m1_m(...) __riscv_vredor_vs_i16mf2_i16m1_tum(__VA_ARGS__) -#define vredor_vs_i16m1_i16m1_m(...) __riscv_vredor_vs_i16m1_i16m1_tum(__VA_ARGS__) -#define vredor_vs_i16m2_i16m1_m(...) __riscv_vredor_vs_i16m2_i16m1_tum(__VA_ARGS__) -#define vredor_vs_i16m4_i16m1_m(...) __riscv_vredor_vs_i16m4_i16m1_tum(__VA_ARGS__) -#define vredor_vs_i16m8_i16m1_m(...) __riscv_vredor_vs_i16m8_i16m1_tum(__VA_ARGS__) -#define vredor_vs_i32mf2_i32m1_m(...) __riscv_vredor_vs_i32mf2_i32m1_tum(__VA_ARGS__) -#define vredor_vs_i32m1_i32m1_m(...) __riscv_vredor_vs_i32m1_i32m1_tum(__VA_ARGS__) -#define vredor_vs_i32m2_i32m1_m(...) __riscv_vredor_vs_i32m2_i32m1_tum(__VA_ARGS__) -#define vredor_vs_i32m4_i32m1_m(...) __riscv_vredor_vs_i32m4_i32m1_tum(__VA_ARGS__) -#define vredor_vs_i32m8_i32m1_m(...) __riscv_vredor_vs_i32m8_i32m1_tum(__VA_ARGS__) -#define vredor_vs_i64m1_i64m1_m(...) __riscv_vredor_vs_i64m1_i64m1_tum(__VA_ARGS__) -#define vredor_vs_i64m2_i64m1_m(...) __riscv_vredor_vs_i64m2_i64m1_tum(__VA_ARGS__) -#define vredor_vs_i64m4_i64m1_m(...) __riscv_vredor_vs_i64m4_i64m1_tum(__VA_ARGS__) -#define vredor_vs_i64m8_i64m1_m(...) __riscv_vredor_vs_i64m8_i64m1_tum(__VA_ARGS__) -#define vredxor_vs_i8mf8_i8m1_m(...) __riscv_vredxor_vs_i8mf8_i8m1_tum(__VA_ARGS__) -#define vredxor_vs_i8mf4_i8m1_m(...) __riscv_vredxor_vs_i8mf4_i8m1_tum(__VA_ARGS__) -#define vredxor_vs_i8mf2_i8m1_m(...) __riscv_vredxor_vs_i8mf2_i8m1_tum(__VA_ARGS__) -#define vredxor_vs_i8m1_i8m1_m(...) __riscv_vredxor_vs_i8m1_i8m1_tum(__VA_ARGS__) -#define vredxor_vs_i8m2_i8m1_m(...) __riscv_vredxor_vs_i8m2_i8m1_tum(__VA_ARGS__) -#define vredxor_vs_i8m4_i8m1_m(...) __riscv_vredxor_vs_i8m4_i8m1_tum(__VA_ARGS__) -#define vredxor_vs_i8m8_i8m1_m(...) __riscv_vredxor_vs_i8m8_i8m1_tum(__VA_ARGS__) -#define vredxor_vs_i16mf4_i16m1_m(...) __riscv_vredxor_vs_i16mf4_i16m1_tum(__VA_ARGS__) -#define vredxor_vs_i16mf2_i16m1_m(...) __riscv_vredxor_vs_i16mf2_i16m1_tum(__VA_ARGS__) -#define vredxor_vs_i16m1_i16m1_m(...) __riscv_vredxor_vs_i16m1_i16m1_tum(__VA_ARGS__) -#define vredxor_vs_i16m2_i16m1_m(...) __riscv_vredxor_vs_i16m2_i16m1_tum(__VA_ARGS__) -#define vredxor_vs_i16m4_i16m1_m(...) __riscv_vredxor_vs_i16m4_i16m1_tum(__VA_ARGS__) -#define vredxor_vs_i16m8_i16m1_m(...) __riscv_vredxor_vs_i16m8_i16m1_tum(__VA_ARGS__) -#define vredxor_vs_i32mf2_i32m1_m(...) __riscv_vredxor_vs_i32mf2_i32m1_tum(__VA_ARGS__) -#define vredxor_vs_i32m1_i32m1_m(...) __riscv_vredxor_vs_i32m1_i32m1_tum(__VA_ARGS__) -#define vredxor_vs_i32m2_i32m1_m(...) __riscv_vredxor_vs_i32m2_i32m1_tum(__VA_ARGS__) -#define vredxor_vs_i32m4_i32m1_m(...) __riscv_vredxor_vs_i32m4_i32m1_tum(__VA_ARGS__) -#define vredxor_vs_i32m8_i32m1_m(...) __riscv_vredxor_vs_i32m8_i32m1_tum(__VA_ARGS__) -#define vredxor_vs_i64m1_i64m1_m(...) __riscv_vredxor_vs_i64m1_i64m1_tum(__VA_ARGS__) -#define vredxor_vs_i64m2_i64m1_m(...) __riscv_vredxor_vs_i64m2_i64m1_tum(__VA_ARGS__) -#define vredxor_vs_i64m4_i64m1_m(...) __riscv_vredxor_vs_i64m4_i64m1_tum(__VA_ARGS__) -#define vredxor_vs_i64m8_i64m1_m(...) __riscv_vredxor_vs_i64m8_i64m1_tum(__VA_ARGS__) -#define vredsum_vs_u8mf8_u8m1_m(...) __riscv_vredsum_vs_u8mf8_u8m1_tum(__VA_ARGS__) -#define vredsum_vs_u8mf4_u8m1_m(...) __riscv_vredsum_vs_u8mf4_u8m1_tum(__VA_ARGS__) -#define vredsum_vs_u8mf2_u8m1_m(...) __riscv_vredsum_vs_u8mf2_u8m1_tum(__VA_ARGS__) -#define vredsum_vs_u8m1_u8m1_m(...) __riscv_vredsum_vs_u8m1_u8m1_tum(__VA_ARGS__) -#define vredsum_vs_u8m2_u8m1_m(...) __riscv_vredsum_vs_u8m2_u8m1_tum(__VA_ARGS__) -#define vredsum_vs_u8m4_u8m1_m(...) __riscv_vredsum_vs_u8m4_u8m1_tum(__VA_ARGS__) -#define vredsum_vs_u8m8_u8m1_m(...) __riscv_vredsum_vs_u8m8_u8m1_tum(__VA_ARGS__) -#define vredsum_vs_u16mf4_u16m1_m(...) __riscv_vredsum_vs_u16mf4_u16m1_tum(__VA_ARGS__) -#define vredsum_vs_u16mf2_u16m1_m(...) __riscv_vredsum_vs_u16mf2_u16m1_tum(__VA_ARGS__) -#define vredsum_vs_u16m1_u16m1_m(...) __riscv_vredsum_vs_u16m1_u16m1_tum(__VA_ARGS__) -#define vredsum_vs_u16m2_u16m1_m(...) __riscv_vredsum_vs_u16m2_u16m1_tum(__VA_ARGS__) -#define vredsum_vs_u16m4_u16m1_m(...) __riscv_vredsum_vs_u16m4_u16m1_tum(__VA_ARGS__) -#define vredsum_vs_u16m8_u16m1_m(...) __riscv_vredsum_vs_u16m8_u16m1_tum(__VA_ARGS__) -#define vredsum_vs_u32mf2_u32m1_m(...) __riscv_vredsum_vs_u32mf2_u32m1_tum(__VA_ARGS__) -#define vredsum_vs_u32m1_u32m1_m(...) __riscv_vredsum_vs_u32m1_u32m1_tum(__VA_ARGS__) -#define vredsum_vs_u32m2_u32m1_m(...) __riscv_vredsum_vs_u32m2_u32m1_tum(__VA_ARGS__) -#define vredsum_vs_u32m4_u32m1_m(...) __riscv_vredsum_vs_u32m4_u32m1_tum(__VA_ARGS__) -#define vredsum_vs_u32m8_u32m1_m(...) __riscv_vredsum_vs_u32m8_u32m1_tum(__VA_ARGS__) -#define vredsum_vs_u64m1_u64m1_m(...) __riscv_vredsum_vs_u64m1_u64m1_tum(__VA_ARGS__) -#define vredsum_vs_u64m2_u64m1_m(...) __riscv_vredsum_vs_u64m2_u64m1_tum(__VA_ARGS__) -#define vredsum_vs_u64m4_u64m1_m(...) __riscv_vredsum_vs_u64m4_u64m1_tum(__VA_ARGS__) -#define vredsum_vs_u64m8_u64m1_m(...) __riscv_vredsum_vs_u64m8_u64m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u8mf8_u8m1_m(...) __riscv_vredmaxu_vs_u8mf8_u8m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u8mf4_u8m1_m(...) __riscv_vredmaxu_vs_u8mf4_u8m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u8mf2_u8m1_m(...) __riscv_vredmaxu_vs_u8mf2_u8m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u8m1_u8m1_m(...) __riscv_vredmaxu_vs_u8m1_u8m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u8m2_u8m1_m(...) __riscv_vredmaxu_vs_u8m2_u8m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u8m4_u8m1_m(...) __riscv_vredmaxu_vs_u8m4_u8m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u8m8_u8m1_m(...) __riscv_vredmaxu_vs_u8m8_u8m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u16mf4_u16m1_m(...) __riscv_vredmaxu_vs_u16mf4_u16m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u16mf2_u16m1_m(...) __riscv_vredmaxu_vs_u16mf2_u16m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u16m1_u16m1_m(...) __riscv_vredmaxu_vs_u16m1_u16m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u16m2_u16m1_m(...) __riscv_vredmaxu_vs_u16m2_u16m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u16m4_u16m1_m(...) __riscv_vredmaxu_vs_u16m4_u16m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u16m8_u16m1_m(...) __riscv_vredmaxu_vs_u16m8_u16m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u32mf2_u32m1_m(...) __riscv_vredmaxu_vs_u32mf2_u32m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u32m1_u32m1_m(...) __riscv_vredmaxu_vs_u32m1_u32m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u32m2_u32m1_m(...) __riscv_vredmaxu_vs_u32m2_u32m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u32m4_u32m1_m(...) __riscv_vredmaxu_vs_u32m4_u32m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u32m8_u32m1_m(...) __riscv_vredmaxu_vs_u32m8_u32m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u64m1_u64m1_m(...) __riscv_vredmaxu_vs_u64m1_u64m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u64m2_u64m1_m(...) __riscv_vredmaxu_vs_u64m2_u64m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u64m4_u64m1_m(...) __riscv_vredmaxu_vs_u64m4_u64m1_tum(__VA_ARGS__) -#define vredmaxu_vs_u64m8_u64m1_m(...) __riscv_vredmaxu_vs_u64m8_u64m1_tum(__VA_ARGS__) -#define vredminu_vs_u8mf8_u8m1_m(...) __riscv_vredminu_vs_u8mf8_u8m1_tum(__VA_ARGS__) -#define vredminu_vs_u8mf4_u8m1_m(...) __riscv_vredminu_vs_u8mf4_u8m1_tum(__VA_ARGS__) -#define vredminu_vs_u8mf2_u8m1_m(...) __riscv_vredminu_vs_u8mf2_u8m1_tum(__VA_ARGS__) -#define vredminu_vs_u8m1_u8m1_m(...) __riscv_vredminu_vs_u8m1_u8m1_tum(__VA_ARGS__) -#define vredminu_vs_u8m2_u8m1_m(...) __riscv_vredminu_vs_u8m2_u8m1_tum(__VA_ARGS__) -#define vredminu_vs_u8m4_u8m1_m(...) __riscv_vredminu_vs_u8m4_u8m1_tum(__VA_ARGS__) -#define vredminu_vs_u8m8_u8m1_m(...) __riscv_vredminu_vs_u8m8_u8m1_tum(__VA_ARGS__) -#define vredminu_vs_u16mf4_u16m1_m(...) __riscv_vredminu_vs_u16mf4_u16m1_tum(__VA_ARGS__) -#define vredminu_vs_u16mf2_u16m1_m(...) __riscv_vredminu_vs_u16mf2_u16m1_tum(__VA_ARGS__) -#define vredminu_vs_u16m1_u16m1_m(...) __riscv_vredminu_vs_u16m1_u16m1_tum(__VA_ARGS__) -#define vredminu_vs_u16m2_u16m1_m(...) __riscv_vredminu_vs_u16m2_u16m1_tum(__VA_ARGS__) -#define vredminu_vs_u16m4_u16m1_m(...) __riscv_vredminu_vs_u16m4_u16m1_tum(__VA_ARGS__) -#define vredminu_vs_u16m8_u16m1_m(...) __riscv_vredminu_vs_u16m8_u16m1_tum(__VA_ARGS__) -#define vredminu_vs_u32mf2_u32m1_m(...) __riscv_vredminu_vs_u32mf2_u32m1_tum(__VA_ARGS__) -#define vredminu_vs_u32m1_u32m1_m(...) __riscv_vredminu_vs_u32m1_u32m1_tum(__VA_ARGS__) -#define vredminu_vs_u32m2_u32m1_m(...) __riscv_vredminu_vs_u32m2_u32m1_tum(__VA_ARGS__) -#define vredminu_vs_u32m4_u32m1_m(...) __riscv_vredminu_vs_u32m4_u32m1_tum(__VA_ARGS__) -#define vredminu_vs_u32m8_u32m1_m(...) __riscv_vredminu_vs_u32m8_u32m1_tum(__VA_ARGS__) -#define vredminu_vs_u64m1_u64m1_m(...) __riscv_vredminu_vs_u64m1_u64m1_tum(__VA_ARGS__) -#define vredminu_vs_u64m2_u64m1_m(...) __riscv_vredminu_vs_u64m2_u64m1_tum(__VA_ARGS__) -#define vredminu_vs_u64m4_u64m1_m(...) __riscv_vredminu_vs_u64m4_u64m1_tum(__VA_ARGS__) -#define vredminu_vs_u64m8_u64m1_m(...) __riscv_vredminu_vs_u64m8_u64m1_tum(__VA_ARGS__) -#define vredand_vs_u8mf8_u8m1_m(...) __riscv_vredand_vs_u8mf8_u8m1_tum(__VA_ARGS__) -#define vredand_vs_u8mf4_u8m1_m(...) __riscv_vredand_vs_u8mf4_u8m1_tum(__VA_ARGS__) -#define vredand_vs_u8mf2_u8m1_m(...) __riscv_vredand_vs_u8mf2_u8m1_tum(__VA_ARGS__) -#define vredand_vs_u8m1_u8m1_m(...) __riscv_vredand_vs_u8m1_u8m1_tum(__VA_ARGS__) -#define vredand_vs_u8m2_u8m1_m(...) __riscv_vredand_vs_u8m2_u8m1_tum(__VA_ARGS__) -#define vredand_vs_u8m4_u8m1_m(...) __riscv_vredand_vs_u8m4_u8m1_tum(__VA_ARGS__) -#define vredand_vs_u8m8_u8m1_m(...) __riscv_vredand_vs_u8m8_u8m1_tum(__VA_ARGS__) -#define vredand_vs_u16mf4_u16m1_m(...) __riscv_vredand_vs_u16mf4_u16m1_tum(__VA_ARGS__) -#define vredand_vs_u16mf2_u16m1_m(...) __riscv_vredand_vs_u16mf2_u16m1_tum(__VA_ARGS__) -#define vredand_vs_u16m1_u16m1_m(...) __riscv_vredand_vs_u16m1_u16m1_tum(__VA_ARGS__) -#define vredand_vs_u16m2_u16m1_m(...) __riscv_vredand_vs_u16m2_u16m1_tum(__VA_ARGS__) -#define vredand_vs_u16m4_u16m1_m(...) __riscv_vredand_vs_u16m4_u16m1_tum(__VA_ARGS__) -#define vredand_vs_u16m8_u16m1_m(...) __riscv_vredand_vs_u16m8_u16m1_tum(__VA_ARGS__) -#define vredand_vs_u32mf2_u32m1_m(...) __riscv_vredand_vs_u32mf2_u32m1_tum(__VA_ARGS__) -#define vredand_vs_u32m1_u32m1_m(...) __riscv_vredand_vs_u32m1_u32m1_tum(__VA_ARGS__) -#define vredand_vs_u32m2_u32m1_m(...) __riscv_vredand_vs_u32m2_u32m1_tum(__VA_ARGS__) -#define vredand_vs_u32m4_u32m1_m(...) __riscv_vredand_vs_u32m4_u32m1_tum(__VA_ARGS__) -#define vredand_vs_u32m8_u32m1_m(...) __riscv_vredand_vs_u32m8_u32m1_tum(__VA_ARGS__) -#define vredand_vs_u64m1_u64m1_m(...) __riscv_vredand_vs_u64m1_u64m1_tum(__VA_ARGS__) -#define vredand_vs_u64m2_u64m1_m(...) __riscv_vredand_vs_u64m2_u64m1_tum(__VA_ARGS__) -#define vredand_vs_u64m4_u64m1_m(...) __riscv_vredand_vs_u64m4_u64m1_tum(__VA_ARGS__) -#define vredand_vs_u64m8_u64m1_m(...) __riscv_vredand_vs_u64m8_u64m1_tum(__VA_ARGS__) -#define vredor_vs_u8mf8_u8m1_m(...) __riscv_vredor_vs_u8mf8_u8m1_tum(__VA_ARGS__) -#define vredor_vs_u8mf4_u8m1_m(...) __riscv_vredor_vs_u8mf4_u8m1_tum(__VA_ARGS__) -#define vredor_vs_u8mf2_u8m1_m(...) __riscv_vredor_vs_u8mf2_u8m1_tum(__VA_ARGS__) -#define vredor_vs_u8m1_u8m1_m(...) __riscv_vredor_vs_u8m1_u8m1_tum(__VA_ARGS__) -#define vredor_vs_u8m2_u8m1_m(...) __riscv_vredor_vs_u8m2_u8m1_tum(__VA_ARGS__) -#define vredor_vs_u8m4_u8m1_m(...) __riscv_vredor_vs_u8m4_u8m1_tum(__VA_ARGS__) -#define vredor_vs_u8m8_u8m1_m(...) __riscv_vredor_vs_u8m8_u8m1_tum(__VA_ARGS__) -#define vredor_vs_u16mf4_u16m1_m(...) __riscv_vredor_vs_u16mf4_u16m1_tum(__VA_ARGS__) -#define vredor_vs_u16mf2_u16m1_m(...) __riscv_vredor_vs_u16mf2_u16m1_tum(__VA_ARGS__) -#define vredor_vs_u16m1_u16m1_m(...) __riscv_vredor_vs_u16m1_u16m1_tum(__VA_ARGS__) -#define vredor_vs_u16m2_u16m1_m(...) __riscv_vredor_vs_u16m2_u16m1_tum(__VA_ARGS__) -#define vredor_vs_u16m4_u16m1_m(...) __riscv_vredor_vs_u16m4_u16m1_tum(__VA_ARGS__) -#define vredor_vs_u16m8_u16m1_m(...) __riscv_vredor_vs_u16m8_u16m1_tum(__VA_ARGS__) -#define vredor_vs_u32mf2_u32m1_m(...) __riscv_vredor_vs_u32mf2_u32m1_tum(__VA_ARGS__) -#define vredor_vs_u32m1_u32m1_m(...) __riscv_vredor_vs_u32m1_u32m1_tum(__VA_ARGS__) -#define vredor_vs_u32m2_u32m1_m(...) __riscv_vredor_vs_u32m2_u32m1_tum(__VA_ARGS__) -#define vredor_vs_u32m4_u32m1_m(...) __riscv_vredor_vs_u32m4_u32m1_tum(__VA_ARGS__) -#define vredor_vs_u32m8_u32m1_m(...) __riscv_vredor_vs_u32m8_u32m1_tum(__VA_ARGS__) -#define vredor_vs_u64m1_u64m1_m(...) __riscv_vredor_vs_u64m1_u64m1_tum(__VA_ARGS__) -#define vredor_vs_u64m2_u64m1_m(...) __riscv_vredor_vs_u64m2_u64m1_tum(__VA_ARGS__) -#define vredor_vs_u64m4_u64m1_m(...) __riscv_vredor_vs_u64m4_u64m1_tum(__VA_ARGS__) -#define vredor_vs_u64m8_u64m1_m(...) __riscv_vredor_vs_u64m8_u64m1_tum(__VA_ARGS__) -#define vredxor_vs_u8mf8_u8m1_m(...) __riscv_vredxor_vs_u8mf8_u8m1_tum(__VA_ARGS__) -#define vredxor_vs_u8mf4_u8m1_m(...) __riscv_vredxor_vs_u8mf4_u8m1_tum(__VA_ARGS__) -#define vredxor_vs_u8mf2_u8m1_m(...) __riscv_vredxor_vs_u8mf2_u8m1_tum(__VA_ARGS__) -#define vredxor_vs_u8m1_u8m1_m(...) __riscv_vredxor_vs_u8m1_u8m1_tum(__VA_ARGS__) -#define vredxor_vs_u8m2_u8m1_m(...) __riscv_vredxor_vs_u8m2_u8m1_tum(__VA_ARGS__) -#define vredxor_vs_u8m4_u8m1_m(...) __riscv_vredxor_vs_u8m4_u8m1_tum(__VA_ARGS__) -#define vredxor_vs_u8m8_u8m1_m(...) __riscv_vredxor_vs_u8m8_u8m1_tum(__VA_ARGS__) -#define vredxor_vs_u16mf4_u16m1_m(...) __riscv_vredxor_vs_u16mf4_u16m1_tum(__VA_ARGS__) -#define vredxor_vs_u16mf2_u16m1_m(...) __riscv_vredxor_vs_u16mf2_u16m1_tum(__VA_ARGS__) -#define vredxor_vs_u16m1_u16m1_m(...) __riscv_vredxor_vs_u16m1_u16m1_tum(__VA_ARGS__) -#define vredxor_vs_u16m2_u16m1_m(...) __riscv_vredxor_vs_u16m2_u16m1_tum(__VA_ARGS__) -#define vredxor_vs_u16m4_u16m1_m(...) __riscv_vredxor_vs_u16m4_u16m1_tum(__VA_ARGS__) -#define vredxor_vs_u16m8_u16m1_m(...) __riscv_vredxor_vs_u16m8_u16m1_tum(__VA_ARGS__) -#define vredxor_vs_u32mf2_u32m1_m(...) __riscv_vredxor_vs_u32mf2_u32m1_tum(__VA_ARGS__) -#define vredxor_vs_u32m1_u32m1_m(...) __riscv_vredxor_vs_u32m1_u32m1_tum(__VA_ARGS__) -#define vredxor_vs_u32m2_u32m1_m(...) __riscv_vredxor_vs_u32m2_u32m1_tum(__VA_ARGS__) -#define vredxor_vs_u32m4_u32m1_m(...) __riscv_vredxor_vs_u32m4_u32m1_tum(__VA_ARGS__) -#define vredxor_vs_u32m8_u32m1_m(...) __riscv_vredxor_vs_u32m8_u32m1_tum(__VA_ARGS__) -#define vredxor_vs_u64m1_u64m1_m(...) __riscv_vredxor_vs_u64m1_u64m1_tum(__VA_ARGS__) -#define vredxor_vs_u64m2_u64m1_m(...) __riscv_vredxor_vs_u64m2_u64m1_tum(__VA_ARGS__) -#define vredxor_vs_u64m4_u64m1_m(...) __riscv_vredxor_vs_u64m4_u64m1_tum(__VA_ARGS__) -#define vredxor_vs_u64m8_u64m1_m(...) __riscv_vredxor_vs_u64m8_u64m1_tum(__VA_ARGS__) -#define vwredsum_vs_i8mf8_i16m1(...) __riscv_vwredsum_vs_i8mf8_i16m1_tu(__VA_ARGS__) -#define vwredsum_vs_i8mf4_i16m1(...) __riscv_vwredsum_vs_i8mf4_i16m1_tu(__VA_ARGS__) -#define vwredsum_vs_i8mf2_i16m1(...) __riscv_vwredsum_vs_i8mf2_i16m1_tu(__VA_ARGS__) -#define vwredsum_vs_i8m1_i16m1(...) __riscv_vwredsum_vs_i8m1_i16m1_tu(__VA_ARGS__) -#define vwredsum_vs_i8m2_i16m1(...) __riscv_vwredsum_vs_i8m2_i16m1_tu(__VA_ARGS__) -#define vwredsum_vs_i8m4_i16m1(...) __riscv_vwredsum_vs_i8m4_i16m1_tu(__VA_ARGS__) -#define vwredsum_vs_i8m8_i16m1(...) __riscv_vwredsum_vs_i8m8_i16m1_tu(__VA_ARGS__) -#define vwredsum_vs_i16mf4_i32m1(...) __riscv_vwredsum_vs_i16mf4_i32m1_tu(__VA_ARGS__) -#define vwredsum_vs_i16mf2_i32m1(...) __riscv_vwredsum_vs_i16mf2_i32m1_tu(__VA_ARGS__) -#define vwredsum_vs_i16m1_i32m1(...) __riscv_vwredsum_vs_i16m1_i32m1_tu(__VA_ARGS__) -#define vwredsum_vs_i16m2_i32m1(...) __riscv_vwredsum_vs_i16m2_i32m1_tu(__VA_ARGS__) -#define vwredsum_vs_i16m4_i32m1(...) __riscv_vwredsum_vs_i16m4_i32m1_tu(__VA_ARGS__) -#define vwredsum_vs_i16m8_i32m1(...) __riscv_vwredsum_vs_i16m8_i32m1_tu(__VA_ARGS__) -#define vwredsum_vs_i32mf2_i64m1(...) __riscv_vwredsum_vs_i32mf2_i64m1_tu(__VA_ARGS__) -#define vwredsum_vs_i32m1_i64m1(...) __riscv_vwredsum_vs_i32m1_i64m1_tu(__VA_ARGS__) -#define vwredsum_vs_i32m2_i64m1(...) __riscv_vwredsum_vs_i32m2_i64m1_tu(__VA_ARGS__) -#define vwredsum_vs_i32m4_i64m1(...) __riscv_vwredsum_vs_i32m4_i64m1_tu(__VA_ARGS__) -#define vwredsum_vs_i32m8_i64m1(...) __riscv_vwredsum_vs_i32m8_i64m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u8mf8_u16m1(...) __riscv_vwredsumu_vs_u8mf8_u16m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u8mf4_u16m1(...) __riscv_vwredsumu_vs_u8mf4_u16m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u8mf2_u16m1(...) __riscv_vwredsumu_vs_u8mf2_u16m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u8m1_u16m1(...) __riscv_vwredsumu_vs_u8m1_u16m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u8m2_u16m1(...) __riscv_vwredsumu_vs_u8m2_u16m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u8m4_u16m1(...) __riscv_vwredsumu_vs_u8m4_u16m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u8m8_u16m1(...) __riscv_vwredsumu_vs_u8m8_u16m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u16mf4_u32m1(...) __riscv_vwredsumu_vs_u16mf4_u32m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u16mf2_u32m1(...) __riscv_vwredsumu_vs_u16mf2_u32m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u16m1_u32m1(...) __riscv_vwredsumu_vs_u16m1_u32m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u16m2_u32m1(...) __riscv_vwredsumu_vs_u16m2_u32m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u16m4_u32m1(...) __riscv_vwredsumu_vs_u16m4_u32m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u16m8_u32m1(...) __riscv_vwredsumu_vs_u16m8_u32m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u32mf2_u64m1(...) __riscv_vwredsumu_vs_u32mf2_u64m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u32m1_u64m1(...) __riscv_vwredsumu_vs_u32m1_u64m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u32m2_u64m1(...) __riscv_vwredsumu_vs_u32m2_u64m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u32m4_u64m1(...) __riscv_vwredsumu_vs_u32m4_u64m1_tu(__VA_ARGS__) -#define vwredsumu_vs_u32m8_u64m1(...) __riscv_vwredsumu_vs_u32m8_u64m1_tu(__VA_ARGS__) -// masked functions -#define vwredsum_vs_i8mf8_i16m1_m(...) __riscv_vwredsum_vs_i8mf8_i16m1_tum(__VA_ARGS__) -#define vwredsum_vs_i8mf4_i16m1_m(...) __riscv_vwredsum_vs_i8mf4_i16m1_tum(__VA_ARGS__) -#define vwredsum_vs_i8mf2_i16m1_m(...) __riscv_vwredsum_vs_i8mf2_i16m1_tum(__VA_ARGS__) -#define vwredsum_vs_i8m1_i16m1_m(...) __riscv_vwredsum_vs_i8m1_i16m1_tum(__VA_ARGS__) -#define vwredsum_vs_i8m2_i16m1_m(...) __riscv_vwredsum_vs_i8m2_i16m1_tum(__VA_ARGS__) -#define vwredsum_vs_i8m4_i16m1_m(...) __riscv_vwredsum_vs_i8m4_i16m1_tum(__VA_ARGS__) -#define vwredsum_vs_i8m8_i16m1_m(...) __riscv_vwredsum_vs_i8m8_i16m1_tum(__VA_ARGS__) -#define vwredsum_vs_i16mf4_i32m1_m(...) __riscv_vwredsum_vs_i16mf4_i32m1_tum(__VA_ARGS__) -#define vwredsum_vs_i16mf2_i32m1_m(...) __riscv_vwredsum_vs_i16mf2_i32m1_tum(__VA_ARGS__) -#define vwredsum_vs_i16m1_i32m1_m(...) __riscv_vwredsum_vs_i16m1_i32m1_tum(__VA_ARGS__) -#define vwredsum_vs_i16m2_i32m1_m(...) __riscv_vwredsum_vs_i16m2_i32m1_tum(__VA_ARGS__) -#define vwredsum_vs_i16m4_i32m1_m(...) __riscv_vwredsum_vs_i16m4_i32m1_tum(__VA_ARGS__) -#define vwredsum_vs_i16m8_i32m1_m(...) __riscv_vwredsum_vs_i16m8_i32m1_tum(__VA_ARGS__) -#define vwredsum_vs_i32mf2_i64m1_m(...) __riscv_vwredsum_vs_i32mf2_i64m1_tum(__VA_ARGS__) -#define vwredsum_vs_i32m1_i64m1_m(...) __riscv_vwredsum_vs_i32m1_i64m1_tum(__VA_ARGS__) -#define vwredsum_vs_i32m2_i64m1_m(...) __riscv_vwredsum_vs_i32m2_i64m1_tum(__VA_ARGS__) -#define vwredsum_vs_i32m4_i64m1_m(...) __riscv_vwredsum_vs_i32m4_i64m1_tum(__VA_ARGS__) -#define vwredsum_vs_i32m8_i64m1_m(...) __riscv_vwredsum_vs_i32m8_i64m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u8mf8_u16m1_m(...) __riscv_vwredsumu_vs_u8mf8_u16m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u8mf4_u16m1_m(...) __riscv_vwredsumu_vs_u8mf4_u16m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u8mf2_u16m1_m(...) __riscv_vwredsumu_vs_u8mf2_u16m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u8m1_u16m1_m(...) __riscv_vwredsumu_vs_u8m1_u16m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u8m2_u16m1_m(...) __riscv_vwredsumu_vs_u8m2_u16m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u8m4_u16m1_m(...) __riscv_vwredsumu_vs_u8m4_u16m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u8m8_u16m1_m(...) __riscv_vwredsumu_vs_u8m8_u16m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u16mf4_u32m1_m(...) __riscv_vwredsumu_vs_u16mf4_u32m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u16mf2_u32m1_m(...) __riscv_vwredsumu_vs_u16mf2_u32m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u16m1_u32m1_m(...) __riscv_vwredsumu_vs_u16m1_u32m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u16m2_u32m1_m(...) __riscv_vwredsumu_vs_u16m2_u32m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u16m4_u32m1_m(...) __riscv_vwredsumu_vs_u16m4_u32m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u16m8_u32m1_m(...) __riscv_vwredsumu_vs_u16m8_u32m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u32mf2_u64m1_m(...) __riscv_vwredsumu_vs_u32mf2_u64m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u32m1_u64m1_m(...) __riscv_vwredsumu_vs_u32m1_u64m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u32m2_u64m1_m(...) __riscv_vwredsumu_vs_u32m2_u64m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u32m4_u64m1_m(...) __riscv_vwredsumu_vs_u32m4_u64m1_tum(__VA_ARGS__) -#define vwredsumu_vs_u32m8_u64m1_m(...) __riscv_vwredsumu_vs_u32m8_u64m1_tum(__VA_ARGS__) -#define vfredosum_vs_f16mf4_f16m1(...) __riscv_vfredosum_vs_f16mf4_f16m1_tu(__VA_ARGS__) -#define vfredosum_vs_f16mf2_f16m1(...) __riscv_vfredosum_vs_f16mf2_f16m1_tu(__VA_ARGS__) -#define vfredosum_vs_f16m1_f16m1(...) __riscv_vfredosum_vs_f16m1_f16m1_tu(__VA_ARGS__) -#define vfredosum_vs_f16m2_f16m1(...) __riscv_vfredosum_vs_f16m2_f16m1_tu(__VA_ARGS__) -#define vfredosum_vs_f16m4_f16m1(...) __riscv_vfredosum_vs_f16m4_f16m1_tu(__VA_ARGS__) -#define vfredosum_vs_f16m8_f16m1(...) __riscv_vfredosum_vs_f16m8_f16m1_tu(__VA_ARGS__) -#define vfredosum_vs_f32mf2_f32m1(...) __riscv_vfredosum_vs_f32mf2_f32m1_tu(__VA_ARGS__) -#define vfredosum_vs_f32m1_f32m1(...) __riscv_vfredosum_vs_f32m1_f32m1_tu(__VA_ARGS__) -#define vfredosum_vs_f32m2_f32m1(...) __riscv_vfredosum_vs_f32m2_f32m1_tu(__VA_ARGS__) -#define vfredosum_vs_f32m4_f32m1(...) __riscv_vfredosum_vs_f32m4_f32m1_tu(__VA_ARGS__) -#define vfredosum_vs_f32m8_f32m1(...) __riscv_vfredosum_vs_f32m8_f32m1_tu(__VA_ARGS__) -#define vfredosum_vs_f64m1_f64m1(...) __riscv_vfredosum_vs_f64m1_f64m1_tu(__VA_ARGS__) -#define vfredosum_vs_f64m2_f64m1(...) __riscv_vfredosum_vs_f64m2_f64m1_tu(__VA_ARGS__) -#define vfredosum_vs_f64m4_f64m1(...) __riscv_vfredosum_vs_f64m4_f64m1_tu(__VA_ARGS__) -#define vfredosum_vs_f64m8_f64m1(...) __riscv_vfredosum_vs_f64m8_f64m1_tu(__VA_ARGS__) -#define vfredusum_vs_f16mf4_f16m1(...) __riscv_vfredusum_vs_f16mf4_f16m1_tu(__VA_ARGS__) -#define vfredusum_vs_f16mf2_f16m1(...) __riscv_vfredusum_vs_f16mf2_f16m1_tu(__VA_ARGS__) -#define vfredusum_vs_f16m1_f16m1(...) __riscv_vfredusum_vs_f16m1_f16m1_tu(__VA_ARGS__) -#define vfredusum_vs_f16m2_f16m1(...) __riscv_vfredusum_vs_f16m2_f16m1_tu(__VA_ARGS__) -#define vfredusum_vs_f16m4_f16m1(...) __riscv_vfredusum_vs_f16m4_f16m1_tu(__VA_ARGS__) -#define vfredusum_vs_f16m8_f16m1(...) __riscv_vfredusum_vs_f16m8_f16m1_tu(__VA_ARGS__) -#define vfredusum_vs_f32mf2_f32m1(...) __riscv_vfredusum_vs_f32mf2_f32m1_tu(__VA_ARGS__) -#define vfredusum_vs_f32m1_f32m1(...) __riscv_vfredusum_vs_f32m1_f32m1_tu(__VA_ARGS__) -#define vfredusum_vs_f32m2_f32m1(...) __riscv_vfredusum_vs_f32m2_f32m1_tu(__VA_ARGS__) -#define vfredusum_vs_f32m4_f32m1(...) __riscv_vfredusum_vs_f32m4_f32m1_tu(__VA_ARGS__) -#define vfredusum_vs_f32m8_f32m1(...) __riscv_vfredusum_vs_f32m8_f32m1_tu(__VA_ARGS__) -#define vfredusum_vs_f64m1_f64m1(...) __riscv_vfredusum_vs_f64m1_f64m1_tu(__VA_ARGS__) -#define vfredusum_vs_f64m2_f64m1(...) __riscv_vfredusum_vs_f64m2_f64m1_tu(__VA_ARGS__) -#define vfredusum_vs_f64m4_f64m1(...) __riscv_vfredusum_vs_f64m4_f64m1_tu(__VA_ARGS__) -#define vfredusum_vs_f64m8_f64m1(...) __riscv_vfredusum_vs_f64m8_f64m1_tu(__VA_ARGS__) -#define vfredmax_vs_f16mf4_f16m1(...) __riscv_vfredmax_vs_f16mf4_f16m1_tu(__VA_ARGS__) -#define vfredmax_vs_f16mf2_f16m1(...) __riscv_vfredmax_vs_f16mf2_f16m1_tu(__VA_ARGS__) -#define vfredmax_vs_f16m1_f16m1(...) __riscv_vfredmax_vs_f16m1_f16m1_tu(__VA_ARGS__) -#define vfredmax_vs_f16m2_f16m1(...) __riscv_vfredmax_vs_f16m2_f16m1_tu(__VA_ARGS__) -#define vfredmax_vs_f16m4_f16m1(...) __riscv_vfredmax_vs_f16m4_f16m1_tu(__VA_ARGS__) -#define vfredmax_vs_f16m8_f16m1(...) __riscv_vfredmax_vs_f16m8_f16m1_tu(__VA_ARGS__) -#define vfredmax_vs_f32mf2_f32m1(...) __riscv_vfredmax_vs_f32mf2_f32m1_tu(__VA_ARGS__) -#define vfredmax_vs_f32m1_f32m1(...) __riscv_vfredmax_vs_f32m1_f32m1_tu(__VA_ARGS__) -#define vfredmax_vs_f32m2_f32m1(...) __riscv_vfredmax_vs_f32m2_f32m1_tu(__VA_ARGS__) -#define vfredmax_vs_f32m4_f32m1(...) __riscv_vfredmax_vs_f32m4_f32m1_tu(__VA_ARGS__) -#define vfredmax_vs_f32m8_f32m1(...) __riscv_vfredmax_vs_f32m8_f32m1_tu(__VA_ARGS__) -#define vfredmax_vs_f64m1_f64m1(...) __riscv_vfredmax_vs_f64m1_f64m1_tu(__VA_ARGS__) -#define vfredmax_vs_f64m2_f64m1(...) __riscv_vfredmax_vs_f64m2_f64m1_tu(__VA_ARGS__) -#define vfredmax_vs_f64m4_f64m1(...) __riscv_vfredmax_vs_f64m4_f64m1_tu(__VA_ARGS__) -#define vfredmax_vs_f64m8_f64m1(...) __riscv_vfredmax_vs_f64m8_f64m1_tu(__VA_ARGS__) -#define vfredmin_vs_f16mf4_f16m1(...) __riscv_vfredmin_vs_f16mf4_f16m1_tu(__VA_ARGS__) -#define vfredmin_vs_f16mf2_f16m1(...) __riscv_vfredmin_vs_f16mf2_f16m1_tu(__VA_ARGS__) -#define vfredmin_vs_f16m1_f16m1(...) __riscv_vfredmin_vs_f16m1_f16m1_tu(__VA_ARGS__) -#define vfredmin_vs_f16m2_f16m1(...) __riscv_vfredmin_vs_f16m2_f16m1_tu(__VA_ARGS__) -#define vfredmin_vs_f16m4_f16m1(...) __riscv_vfredmin_vs_f16m4_f16m1_tu(__VA_ARGS__) -#define vfredmin_vs_f16m8_f16m1(...) __riscv_vfredmin_vs_f16m8_f16m1_tu(__VA_ARGS__) -#define vfredmin_vs_f32mf2_f32m1(...) __riscv_vfredmin_vs_f32mf2_f32m1_tu(__VA_ARGS__) -#define vfredmin_vs_f32m1_f32m1(...) __riscv_vfredmin_vs_f32m1_f32m1_tu(__VA_ARGS__) -#define vfredmin_vs_f32m2_f32m1(...) __riscv_vfredmin_vs_f32m2_f32m1_tu(__VA_ARGS__) -#define vfredmin_vs_f32m4_f32m1(...) __riscv_vfredmin_vs_f32m4_f32m1_tu(__VA_ARGS__) -#define vfredmin_vs_f32m8_f32m1(...) __riscv_vfredmin_vs_f32m8_f32m1_tu(__VA_ARGS__) -#define vfredmin_vs_f64m1_f64m1(...) __riscv_vfredmin_vs_f64m1_f64m1_tu(__VA_ARGS__) -#define vfredmin_vs_f64m2_f64m1(...) __riscv_vfredmin_vs_f64m2_f64m1_tu(__VA_ARGS__) -#define vfredmin_vs_f64m4_f64m1(...) __riscv_vfredmin_vs_f64m4_f64m1_tu(__VA_ARGS__) -#define vfredmin_vs_f64m8_f64m1(...) __riscv_vfredmin_vs_f64m8_f64m1_tu(__VA_ARGS__) -// masked functions -#define vfredosum_vs_f16mf4_f16m1_m(...) __riscv_vfredosum_vs_f16mf4_f16m1_tum(__VA_ARGS__) -#define vfredosum_vs_f16mf2_f16m1_m(...) __riscv_vfredosum_vs_f16mf2_f16m1_tum(__VA_ARGS__) -#define vfredosum_vs_f16m1_f16m1_m(...) __riscv_vfredosum_vs_f16m1_f16m1_tum(__VA_ARGS__) -#define vfredosum_vs_f16m2_f16m1_m(...) __riscv_vfredosum_vs_f16m2_f16m1_tum(__VA_ARGS__) -#define vfredosum_vs_f16m4_f16m1_m(...) __riscv_vfredosum_vs_f16m4_f16m1_tum(__VA_ARGS__) -#define vfredosum_vs_f16m8_f16m1_m(...) __riscv_vfredosum_vs_f16m8_f16m1_tum(__VA_ARGS__) -#define vfredosum_vs_f32mf2_f32m1_m(...) __riscv_vfredosum_vs_f32mf2_f32m1_tum(__VA_ARGS__) -#define vfredosum_vs_f32m1_f32m1_m(...) __riscv_vfredosum_vs_f32m1_f32m1_tum(__VA_ARGS__) -#define vfredosum_vs_f32m2_f32m1_m(...) __riscv_vfredosum_vs_f32m2_f32m1_tum(__VA_ARGS__) -#define vfredosum_vs_f32m4_f32m1_m(...) __riscv_vfredosum_vs_f32m4_f32m1_tum(__VA_ARGS__) -#define vfredosum_vs_f32m8_f32m1_m(...) __riscv_vfredosum_vs_f32m8_f32m1_tum(__VA_ARGS__) -#define vfredosum_vs_f64m1_f64m1_m(...) __riscv_vfredosum_vs_f64m1_f64m1_tum(__VA_ARGS__) -#define vfredosum_vs_f64m2_f64m1_m(...) __riscv_vfredosum_vs_f64m2_f64m1_tum(__VA_ARGS__) -#define vfredosum_vs_f64m4_f64m1_m(...) __riscv_vfredosum_vs_f64m4_f64m1_tum(__VA_ARGS__) -#define vfredosum_vs_f64m8_f64m1_m(...) __riscv_vfredosum_vs_f64m8_f64m1_tum(__VA_ARGS__) -#define vfredusum_vs_f16mf4_f16m1_m(...) __riscv_vfredusum_vs_f16mf4_f16m1_tum(__VA_ARGS__) -#define vfredusum_vs_f16mf2_f16m1_m(...) __riscv_vfredusum_vs_f16mf2_f16m1_tum(__VA_ARGS__) -#define vfredusum_vs_f16m1_f16m1_m(...) __riscv_vfredusum_vs_f16m1_f16m1_tum(__VA_ARGS__) -#define vfredusum_vs_f16m2_f16m1_m(...) __riscv_vfredusum_vs_f16m2_f16m1_tum(__VA_ARGS__) -#define vfredusum_vs_f16m4_f16m1_m(...) __riscv_vfredusum_vs_f16m4_f16m1_tum(__VA_ARGS__) -#define vfredusum_vs_f16m8_f16m1_m(...) __riscv_vfredusum_vs_f16m8_f16m1_tum(__VA_ARGS__) -#define vfredusum_vs_f32mf2_f32m1_m(...) __riscv_vfredusum_vs_f32mf2_f32m1_tum(__VA_ARGS__) -#define vfredusum_vs_f32m1_f32m1_m(...) __riscv_vfredusum_vs_f32m1_f32m1_tum(__VA_ARGS__) -#define vfredusum_vs_f32m2_f32m1_m(...) __riscv_vfredusum_vs_f32m2_f32m1_tum(__VA_ARGS__) -#define vfredusum_vs_f32m4_f32m1_m(...) __riscv_vfredusum_vs_f32m4_f32m1_tum(__VA_ARGS__) -#define vfredusum_vs_f32m8_f32m1_m(...) __riscv_vfredusum_vs_f32m8_f32m1_tum(__VA_ARGS__) -#define vfredusum_vs_f64m1_f64m1_m(...) __riscv_vfredusum_vs_f64m1_f64m1_tum(__VA_ARGS__) -#define vfredusum_vs_f64m2_f64m1_m(...) __riscv_vfredusum_vs_f64m2_f64m1_tum(__VA_ARGS__) -#define vfredusum_vs_f64m4_f64m1_m(...) __riscv_vfredusum_vs_f64m4_f64m1_tum(__VA_ARGS__) -#define vfredusum_vs_f64m8_f64m1_m(...) __riscv_vfredusum_vs_f64m8_f64m1_tum(__VA_ARGS__) -#define vfredmax_vs_f16mf4_f16m1_m(...) __riscv_vfredmax_vs_f16mf4_f16m1_tum(__VA_ARGS__) -#define vfredmax_vs_f16mf2_f16m1_m(...) __riscv_vfredmax_vs_f16mf2_f16m1_tum(__VA_ARGS__) -#define vfredmax_vs_f16m1_f16m1_m(...) __riscv_vfredmax_vs_f16m1_f16m1_tum(__VA_ARGS__) -#define vfredmax_vs_f16m2_f16m1_m(...) __riscv_vfredmax_vs_f16m2_f16m1_tum(__VA_ARGS__) -#define vfredmax_vs_f16m4_f16m1_m(...) __riscv_vfredmax_vs_f16m4_f16m1_tum(__VA_ARGS__) -#define vfredmax_vs_f16m8_f16m1_m(...) __riscv_vfredmax_vs_f16m8_f16m1_tum(__VA_ARGS__) -#define vfredmax_vs_f32mf2_f32m1_m(...) __riscv_vfredmax_vs_f32mf2_f32m1_tum(__VA_ARGS__) -#define vfredmax_vs_f32m1_f32m1_m(...) __riscv_vfredmax_vs_f32m1_f32m1_tum(__VA_ARGS__) -#define vfredmax_vs_f32m2_f32m1_m(...) __riscv_vfredmax_vs_f32m2_f32m1_tum(__VA_ARGS__) -#define vfredmax_vs_f32m4_f32m1_m(...) __riscv_vfredmax_vs_f32m4_f32m1_tum(__VA_ARGS__) -#define vfredmax_vs_f32m8_f32m1_m(...) __riscv_vfredmax_vs_f32m8_f32m1_tum(__VA_ARGS__) -#define vfredmax_vs_f64m1_f64m1_m(...) __riscv_vfredmax_vs_f64m1_f64m1_tum(__VA_ARGS__) -#define vfredmax_vs_f64m2_f64m1_m(...) __riscv_vfredmax_vs_f64m2_f64m1_tum(__VA_ARGS__) -#define vfredmax_vs_f64m4_f64m1_m(...) __riscv_vfredmax_vs_f64m4_f64m1_tum(__VA_ARGS__) -#define vfredmax_vs_f64m8_f64m1_m(...) __riscv_vfredmax_vs_f64m8_f64m1_tum(__VA_ARGS__) -#define vfredmin_vs_f16mf4_f16m1_m(...) __riscv_vfredmin_vs_f16mf4_f16m1_tum(__VA_ARGS__) -#define vfredmin_vs_f16mf2_f16m1_m(...) __riscv_vfredmin_vs_f16mf2_f16m1_tum(__VA_ARGS__) -#define vfredmin_vs_f16m1_f16m1_m(...) __riscv_vfredmin_vs_f16m1_f16m1_tum(__VA_ARGS__) -#define vfredmin_vs_f16m2_f16m1_m(...) __riscv_vfredmin_vs_f16m2_f16m1_tum(__VA_ARGS__) -#define vfredmin_vs_f16m4_f16m1_m(...) __riscv_vfredmin_vs_f16m4_f16m1_tum(__VA_ARGS__) -#define vfredmin_vs_f16m8_f16m1_m(...) __riscv_vfredmin_vs_f16m8_f16m1_tum(__VA_ARGS__) -#define vfredmin_vs_f32mf2_f32m1_m(...) __riscv_vfredmin_vs_f32mf2_f32m1_tum(__VA_ARGS__) -#define vfredmin_vs_f32m1_f32m1_m(...) __riscv_vfredmin_vs_f32m1_f32m1_tum(__VA_ARGS__) -#define vfredmin_vs_f32m2_f32m1_m(...) __riscv_vfredmin_vs_f32m2_f32m1_tum(__VA_ARGS__) -#define vfredmin_vs_f32m4_f32m1_m(...) __riscv_vfredmin_vs_f32m4_f32m1_tum(__VA_ARGS__) -#define vfredmin_vs_f32m8_f32m1_m(...) __riscv_vfredmin_vs_f32m8_f32m1_tum(__VA_ARGS__) -#define vfredmin_vs_f64m1_f64m1_m(...) __riscv_vfredmin_vs_f64m1_f64m1_tum(__VA_ARGS__) -#define vfredmin_vs_f64m2_f64m1_m(...) __riscv_vfredmin_vs_f64m2_f64m1_tum(__VA_ARGS__) -#define vfredmin_vs_f64m4_f64m1_m(...) __riscv_vfredmin_vs_f64m4_f64m1_tum(__VA_ARGS__) -#define vfredmin_vs_f64m8_f64m1_m(...) __riscv_vfredmin_vs_f64m8_f64m1_tum(__VA_ARGS__) -#define vfwredosum_vs_f16mf4_f32m1(...) __riscv_vfwredosum_vs_f16mf4_f32m1_tu(__VA_ARGS__) -#define vfwredosum_vs_f16mf2_f32m1(...) __riscv_vfwredosum_vs_f16mf2_f32m1_tu(__VA_ARGS__) -#define vfwredosum_vs_f16m1_f32m1(...) __riscv_vfwredosum_vs_f16m1_f32m1_tu(__VA_ARGS__) -#define vfwredosum_vs_f16m2_f32m1(...) __riscv_vfwredosum_vs_f16m2_f32m1_tu(__VA_ARGS__) -#define vfwredosum_vs_f16m4_f32m1(...) __riscv_vfwredosum_vs_f16m4_f32m1_tu(__VA_ARGS__) -#define vfwredosum_vs_f16m8_f32m1(...) __riscv_vfwredosum_vs_f16m8_f32m1_tu(__VA_ARGS__) -#define vfwredosum_vs_f32mf2_f64m1(...) __riscv_vfwredosum_vs_f32mf2_f64m1_tu(__VA_ARGS__) -#define vfwredosum_vs_f32m1_f64m1(...) __riscv_vfwredosum_vs_f32m1_f64m1_tu(__VA_ARGS__) -#define vfwredosum_vs_f32m2_f64m1(...) __riscv_vfwredosum_vs_f32m2_f64m1_tu(__VA_ARGS__) -#define vfwredosum_vs_f32m4_f64m1(...) __riscv_vfwredosum_vs_f32m4_f64m1_tu(__VA_ARGS__) -#define vfwredosum_vs_f32m8_f64m1(...) __riscv_vfwredosum_vs_f32m8_f64m1_tu(__VA_ARGS__) -#define vfwredusum_vs_f16mf4_f32m1(...) __riscv_vfwredusum_vs_f16mf4_f32m1_tu(__VA_ARGS__) -#define vfwredusum_vs_f16mf2_f32m1(...) __riscv_vfwredusum_vs_f16mf2_f32m1_tu(__VA_ARGS__) -#define vfwredusum_vs_f16m1_f32m1(...) __riscv_vfwredusum_vs_f16m1_f32m1_tu(__VA_ARGS__) -#define vfwredusum_vs_f16m2_f32m1(...) __riscv_vfwredusum_vs_f16m2_f32m1_tu(__VA_ARGS__) -#define vfwredusum_vs_f16m4_f32m1(...) __riscv_vfwredusum_vs_f16m4_f32m1_tu(__VA_ARGS__) -#define vfwredusum_vs_f16m8_f32m1(...) __riscv_vfwredusum_vs_f16m8_f32m1_tu(__VA_ARGS__) -#define vfwredusum_vs_f32mf2_f64m1(...) __riscv_vfwredusum_vs_f32mf2_f64m1_tu(__VA_ARGS__) -#define vfwredusum_vs_f32m1_f64m1(...) __riscv_vfwredusum_vs_f32m1_f64m1_tu(__VA_ARGS__) -#define vfwredusum_vs_f32m2_f64m1(...) __riscv_vfwredusum_vs_f32m2_f64m1_tu(__VA_ARGS__) -#define vfwredusum_vs_f32m4_f64m1(...) __riscv_vfwredusum_vs_f32m4_f64m1_tu(__VA_ARGS__) -#define vfwredusum_vs_f32m8_f64m1(...) __riscv_vfwredusum_vs_f32m8_f64m1_tu(__VA_ARGS__) -// masked functions -#define vfwredosum_vs_f16mf4_f32m1_m(...) __riscv_vfwredosum_vs_f16mf4_f32m1_tum(__VA_ARGS__) -#define vfwredosum_vs_f16mf2_f32m1_m(...) __riscv_vfwredosum_vs_f16mf2_f32m1_tum(__VA_ARGS__) -#define vfwredosum_vs_f16m1_f32m1_m(...) __riscv_vfwredosum_vs_f16m1_f32m1_tum(__VA_ARGS__) -#define vfwredosum_vs_f16m2_f32m1_m(...) __riscv_vfwredosum_vs_f16m2_f32m1_tum(__VA_ARGS__) -#define vfwredosum_vs_f16m4_f32m1_m(...) __riscv_vfwredosum_vs_f16m4_f32m1_tum(__VA_ARGS__) -#define vfwredosum_vs_f16m8_f32m1_m(...) __riscv_vfwredosum_vs_f16m8_f32m1_tum(__VA_ARGS__) -#define vfwredosum_vs_f32mf2_f64m1_m(...) __riscv_vfwredosum_vs_f32mf2_f64m1_tum(__VA_ARGS__) -#define vfwredosum_vs_f32m1_f64m1_m(...) __riscv_vfwredosum_vs_f32m1_f64m1_tum(__VA_ARGS__) -#define vfwredosum_vs_f32m2_f64m1_m(...) __riscv_vfwredosum_vs_f32m2_f64m1_tum(__VA_ARGS__) -#define vfwredosum_vs_f32m4_f64m1_m(...) __riscv_vfwredosum_vs_f32m4_f64m1_tum(__VA_ARGS__) -#define vfwredosum_vs_f32m8_f64m1_m(...) __riscv_vfwredosum_vs_f32m8_f64m1_tum(__VA_ARGS__) -#define vfwredusum_vs_f16mf4_f32m1_m(...) __riscv_vfwredusum_vs_f16mf4_f32m1_tum(__VA_ARGS__) -#define vfwredusum_vs_f16mf2_f32m1_m(...) __riscv_vfwredusum_vs_f16mf2_f32m1_tum(__VA_ARGS__) -#define vfwredusum_vs_f16m1_f32m1_m(...) __riscv_vfwredusum_vs_f16m1_f32m1_tum(__VA_ARGS__) -#define vfwredusum_vs_f16m2_f32m1_m(...) __riscv_vfwredusum_vs_f16m2_f32m1_tum(__VA_ARGS__) -#define vfwredusum_vs_f16m4_f32m1_m(...) __riscv_vfwredusum_vs_f16m4_f32m1_tum(__VA_ARGS__) -#define vfwredusum_vs_f16m8_f32m1_m(...) __riscv_vfwredusum_vs_f16m8_f32m1_tum(__VA_ARGS__) -#define vfwredusum_vs_f32mf2_f64m1_m(...) __riscv_vfwredusum_vs_f32mf2_f64m1_tum(__VA_ARGS__) -#define vfwredusum_vs_f32m1_f64m1_m(...) __riscv_vfwredusum_vs_f32m1_f64m1_tum(__VA_ARGS__) -#define vfwredusum_vs_f32m2_f64m1_m(...) __riscv_vfwredusum_vs_f32m2_f64m1_tum(__VA_ARGS__) -#define vfwredusum_vs_f32m4_f64m1_m(...) __riscv_vfwredusum_vs_f32m4_f64m1_tum(__VA_ARGS__) -#define vfwredusum_vs_f32m8_f64m1_m(...) __riscv_vfwredusum_vs_f32m8_f64m1_tum(__VA_ARGS__) -#define vlm_v_b1(...) __riscv_vlm_v_b1(__VA_ARGS__) -#define vlm_v_b2(...) __riscv_vlm_v_b2(__VA_ARGS__) -#define vlm_v_b4(...) __riscv_vlm_v_b4(__VA_ARGS__) -#define vlm_v_b8(...) __riscv_vlm_v_b8(__VA_ARGS__) -#define vlm_v_b16(...) __riscv_vlm_v_b16(__VA_ARGS__) -#define vlm_v_b32(...) __riscv_vlm_v_b32(__VA_ARGS__) -#define vlm_v_b64(...) __riscv_vlm_v_b64(__VA_ARGS__) -#define vsm_v_b1(...) __riscv_vsm_v_b1(__VA_ARGS__) -#define vsm_v_b2(...) __riscv_vsm_v_b2(__VA_ARGS__) -#define vsm_v_b4(...) __riscv_vsm_v_b4(__VA_ARGS__) -#define vsm_v_b8(...) __riscv_vsm_v_b8(__VA_ARGS__) -#define vsm_v_b16(...) __riscv_vsm_v_b16(__VA_ARGS__) -#define vsm_v_b32(...) __riscv_vsm_v_b32(__VA_ARGS__) -#define vsm_v_b64(...) __riscv_vsm_v_b64(__VA_ARGS__) -#define vmand_mm_b1(...) __riscv_vmand_mm_b1(__VA_ARGS__) -#define vmand_mm_b2(...) __riscv_vmand_mm_b2(__VA_ARGS__) -#define vmand_mm_b4(...) __riscv_vmand_mm_b4(__VA_ARGS__) -#define vmand_mm_b8(...) __riscv_vmand_mm_b8(__VA_ARGS__) -#define vmand_mm_b16(...) __riscv_vmand_mm_b16(__VA_ARGS__) -#define vmand_mm_b32(...) __riscv_vmand_mm_b32(__VA_ARGS__) -#define vmand_mm_b64(...) __riscv_vmand_mm_b64(__VA_ARGS__) -#define vmnand_mm_b1(...) __riscv_vmnand_mm_b1(__VA_ARGS__) -#define vmnand_mm_b2(...) __riscv_vmnand_mm_b2(__VA_ARGS__) -#define vmnand_mm_b4(...) __riscv_vmnand_mm_b4(__VA_ARGS__) -#define vmnand_mm_b8(...) __riscv_vmnand_mm_b8(__VA_ARGS__) -#define vmnand_mm_b16(...) __riscv_vmnand_mm_b16(__VA_ARGS__) -#define vmnand_mm_b32(...) __riscv_vmnand_mm_b32(__VA_ARGS__) -#define vmnand_mm_b64(...) __riscv_vmnand_mm_b64(__VA_ARGS__) -#define vmandn_mm_b1(...) __riscv_vmandn_mm_b1(__VA_ARGS__) -#define vmandn_mm_b2(...) __riscv_vmandn_mm_b2(__VA_ARGS__) -#define vmandn_mm_b4(...) __riscv_vmandn_mm_b4(__VA_ARGS__) -#define vmandn_mm_b8(...) __riscv_vmandn_mm_b8(__VA_ARGS__) -#define vmandn_mm_b16(...) __riscv_vmandn_mm_b16(__VA_ARGS__) -#define vmandn_mm_b32(...) __riscv_vmandn_mm_b32(__VA_ARGS__) -#define vmandn_mm_b64(...) __riscv_vmandn_mm_b64(__VA_ARGS__) -#define vmxor_mm_b1(...) __riscv_vmxor_mm_b1(__VA_ARGS__) -#define vmxor_mm_b2(...) __riscv_vmxor_mm_b2(__VA_ARGS__) -#define vmxor_mm_b4(...) __riscv_vmxor_mm_b4(__VA_ARGS__) -#define vmxor_mm_b8(...) __riscv_vmxor_mm_b8(__VA_ARGS__) -#define vmxor_mm_b16(...) __riscv_vmxor_mm_b16(__VA_ARGS__) -#define vmxor_mm_b32(...) __riscv_vmxor_mm_b32(__VA_ARGS__) -#define vmxor_mm_b64(...) __riscv_vmxor_mm_b64(__VA_ARGS__) -#define vmor_mm_b1(...) __riscv_vmor_mm_b1(__VA_ARGS__) -#define vmor_mm_b2(...) __riscv_vmor_mm_b2(__VA_ARGS__) -#define vmor_mm_b4(...) __riscv_vmor_mm_b4(__VA_ARGS__) -#define vmor_mm_b8(...) __riscv_vmor_mm_b8(__VA_ARGS__) -#define vmor_mm_b16(...) __riscv_vmor_mm_b16(__VA_ARGS__) -#define vmor_mm_b32(...) __riscv_vmor_mm_b32(__VA_ARGS__) -#define vmor_mm_b64(...) __riscv_vmor_mm_b64(__VA_ARGS__) -#define vmnor_mm_b1(...) __riscv_vmnor_mm_b1(__VA_ARGS__) -#define vmnor_mm_b2(...) __riscv_vmnor_mm_b2(__VA_ARGS__) -#define vmnor_mm_b4(...) __riscv_vmnor_mm_b4(__VA_ARGS__) -#define vmnor_mm_b8(...) __riscv_vmnor_mm_b8(__VA_ARGS__) -#define vmnor_mm_b16(...) __riscv_vmnor_mm_b16(__VA_ARGS__) -#define vmnor_mm_b32(...) __riscv_vmnor_mm_b32(__VA_ARGS__) -#define vmnor_mm_b64(...) __riscv_vmnor_mm_b64(__VA_ARGS__) -#define vmorn_mm_b1(...) __riscv_vmorn_mm_b1(__VA_ARGS__) -#define vmorn_mm_b2(...) __riscv_vmorn_mm_b2(__VA_ARGS__) -#define vmorn_mm_b4(...) __riscv_vmorn_mm_b4(__VA_ARGS__) -#define vmorn_mm_b8(...) __riscv_vmorn_mm_b8(__VA_ARGS__) -#define vmorn_mm_b16(...) __riscv_vmorn_mm_b16(__VA_ARGS__) -#define vmorn_mm_b32(...) __riscv_vmorn_mm_b32(__VA_ARGS__) -#define vmorn_mm_b64(...) __riscv_vmorn_mm_b64(__VA_ARGS__) -#define vmxnor_mm_b1(...) __riscv_vmxnor_mm_b1(__VA_ARGS__) -#define vmxnor_mm_b2(...) __riscv_vmxnor_mm_b2(__VA_ARGS__) -#define vmxnor_mm_b4(...) __riscv_vmxnor_mm_b4(__VA_ARGS__) -#define vmxnor_mm_b8(...) __riscv_vmxnor_mm_b8(__VA_ARGS__) -#define vmxnor_mm_b16(...) __riscv_vmxnor_mm_b16(__VA_ARGS__) -#define vmxnor_mm_b32(...) __riscv_vmxnor_mm_b32(__VA_ARGS__) -#define vmxnor_mm_b64(...) __riscv_vmxnor_mm_b64(__VA_ARGS__) -#define vmmv_m_b1(...) __riscv_vmmv_m_b1(__VA_ARGS__) -#define vmmv_m_b2(...) __riscv_vmmv_m_b2(__VA_ARGS__) -#define vmmv_m_b4(...) __riscv_vmmv_m_b4(__VA_ARGS__) -#define vmmv_m_b8(...) __riscv_vmmv_m_b8(__VA_ARGS__) -#define vmmv_m_b16(...) __riscv_vmmv_m_b16(__VA_ARGS__) -#define vmmv_m_b32(...) __riscv_vmmv_m_b32(__VA_ARGS__) -#define vmmv_m_b64(...) __riscv_vmmv_m_b64(__VA_ARGS__) -#define vmclr_m_b1(...) __riscv_vmclr_m_b1(__VA_ARGS__) -#define vmclr_m_b2(...) __riscv_vmclr_m_b2(__VA_ARGS__) -#define vmclr_m_b4(...) __riscv_vmclr_m_b4(__VA_ARGS__) -#define vmclr_m_b8(...) __riscv_vmclr_m_b8(__VA_ARGS__) -#define vmclr_m_b16(...) __riscv_vmclr_m_b16(__VA_ARGS__) -#define vmclr_m_b32(...) __riscv_vmclr_m_b32(__VA_ARGS__) -#define vmclr_m_b64(...) __riscv_vmclr_m_b64(__VA_ARGS__) -#define vmset_m_b1(...) __riscv_vmset_m_b1(__VA_ARGS__) -#define vmset_m_b2(...) __riscv_vmset_m_b2(__VA_ARGS__) -#define vmset_m_b4(...) __riscv_vmset_m_b4(__VA_ARGS__) -#define vmset_m_b8(...) __riscv_vmset_m_b8(__VA_ARGS__) -#define vmset_m_b16(...) __riscv_vmset_m_b16(__VA_ARGS__) -#define vmset_m_b32(...) __riscv_vmset_m_b32(__VA_ARGS__) -#define vmset_m_b64(...) __riscv_vmset_m_b64(__VA_ARGS__) -#define vmnot_m_b1(...) __riscv_vmnot_m_b1(__VA_ARGS__) -#define vmnot_m_b2(...) __riscv_vmnot_m_b2(__VA_ARGS__) -#define vmnot_m_b4(...) __riscv_vmnot_m_b4(__VA_ARGS__) -#define vmnot_m_b8(...) __riscv_vmnot_m_b8(__VA_ARGS__) -#define vmnot_m_b16(...) __riscv_vmnot_m_b16(__VA_ARGS__) -#define vmnot_m_b32(...) __riscv_vmnot_m_b32(__VA_ARGS__) -#define vmnot_m_b64(...) __riscv_vmnot_m_b64(__VA_ARGS__) -#define vcpop_m_b1(...) __riscv_vcpop_m_b1(__VA_ARGS__) -#define vcpop_m_b2(...) __riscv_vcpop_m_b2(__VA_ARGS__) -#define vcpop_m_b4(...) __riscv_vcpop_m_b4(__VA_ARGS__) -#define vcpop_m_b8(...) __riscv_vcpop_m_b8(__VA_ARGS__) -#define vcpop_m_b16(...) __riscv_vcpop_m_b16(__VA_ARGS__) -#define vcpop_m_b32(...) __riscv_vcpop_m_b32(__VA_ARGS__) -#define vcpop_m_b64(...) __riscv_vcpop_m_b64(__VA_ARGS__) -// masked functions -#define vcpop_m_b1_m(...) __riscv_vcpop_m_b1_m(__VA_ARGS__) -#define vcpop_m_b2_m(...) __riscv_vcpop_m_b2_m(__VA_ARGS__) -#define vcpop_m_b4_m(...) __riscv_vcpop_m_b4_m(__VA_ARGS__) -#define vcpop_m_b8_m(...) __riscv_vcpop_m_b8_m(__VA_ARGS__) -#define vcpop_m_b16_m(...) __riscv_vcpop_m_b16_m(__VA_ARGS__) -#define vcpop_m_b32_m(...) __riscv_vcpop_m_b32_m(__VA_ARGS__) -#define vcpop_m_b64_m(...) __riscv_vcpop_m_b64_m(__VA_ARGS__) -#define vfirst_m_b1(...) __riscv_vfirst_m_b1(__VA_ARGS__) -#define vfirst_m_b2(...) __riscv_vfirst_m_b2(__VA_ARGS__) -#define vfirst_m_b4(...) __riscv_vfirst_m_b4(__VA_ARGS__) -#define vfirst_m_b8(...) __riscv_vfirst_m_b8(__VA_ARGS__) -#define vfirst_m_b16(...) __riscv_vfirst_m_b16(__VA_ARGS__) -#define vfirst_m_b32(...) __riscv_vfirst_m_b32(__VA_ARGS__) -#define vfirst_m_b64(...) __riscv_vfirst_m_b64(__VA_ARGS__) -// masked functions -#define vfirst_m_b1_m(...) __riscv_vfirst_m_b1_m(__VA_ARGS__) -#define vfirst_m_b2_m(...) __riscv_vfirst_m_b2_m(__VA_ARGS__) -#define vfirst_m_b4_m(...) __riscv_vfirst_m_b4_m(__VA_ARGS__) -#define vfirst_m_b8_m(...) __riscv_vfirst_m_b8_m(__VA_ARGS__) -#define vfirst_m_b16_m(...) __riscv_vfirst_m_b16_m(__VA_ARGS__) -#define vfirst_m_b32_m(...) __riscv_vfirst_m_b32_m(__VA_ARGS__) -#define vfirst_m_b64_m(...) __riscv_vfirst_m_b64_m(__VA_ARGS__) -#define vmsbf_m_b1(...) __riscv_vmsbf_m_b1(__VA_ARGS__) -#define vmsbf_m_b2(...) __riscv_vmsbf_m_b2(__VA_ARGS__) -#define vmsbf_m_b4(...) __riscv_vmsbf_m_b4(__VA_ARGS__) -#define vmsbf_m_b8(...) __riscv_vmsbf_m_b8(__VA_ARGS__) -#define vmsbf_m_b16(...) __riscv_vmsbf_m_b16(__VA_ARGS__) -#define vmsbf_m_b32(...) __riscv_vmsbf_m_b32(__VA_ARGS__) -#define vmsbf_m_b64(...) __riscv_vmsbf_m_b64(__VA_ARGS__) -// masked functions -#define vmsbf_m_b1_m(...) __riscv_vmsbf_m_b1_mu(__VA_ARGS__) -#define vmsbf_m_b2_m(...) __riscv_vmsbf_m_b2_mu(__VA_ARGS__) -#define vmsbf_m_b4_m(...) __riscv_vmsbf_m_b4_mu(__VA_ARGS__) -#define vmsbf_m_b8_m(...) __riscv_vmsbf_m_b8_mu(__VA_ARGS__) -#define vmsbf_m_b16_m(...) __riscv_vmsbf_m_b16_mu(__VA_ARGS__) -#define vmsbf_m_b32_m(...) __riscv_vmsbf_m_b32_mu(__VA_ARGS__) -#define vmsbf_m_b64_m(...) __riscv_vmsbf_m_b64_mu(__VA_ARGS__) -#define vmsif_m_b1(...) __riscv_vmsif_m_b1(__VA_ARGS__) -#define vmsif_m_b2(...) __riscv_vmsif_m_b2(__VA_ARGS__) -#define vmsif_m_b4(...) __riscv_vmsif_m_b4(__VA_ARGS__) -#define vmsif_m_b8(...) __riscv_vmsif_m_b8(__VA_ARGS__) -#define vmsif_m_b16(...) __riscv_vmsif_m_b16(__VA_ARGS__) -#define vmsif_m_b32(...) __riscv_vmsif_m_b32(__VA_ARGS__) -#define vmsif_m_b64(...) __riscv_vmsif_m_b64(__VA_ARGS__) -// masked functions -#define vmsif_m_b1_m(...) __riscv_vmsif_m_b1_mu(__VA_ARGS__) -#define vmsif_m_b2_m(...) __riscv_vmsif_m_b2_mu(__VA_ARGS__) -#define vmsif_m_b4_m(...) __riscv_vmsif_m_b4_mu(__VA_ARGS__) -#define vmsif_m_b8_m(...) __riscv_vmsif_m_b8_mu(__VA_ARGS__) -#define vmsif_m_b16_m(...) __riscv_vmsif_m_b16_mu(__VA_ARGS__) -#define vmsif_m_b32_m(...) __riscv_vmsif_m_b32_mu(__VA_ARGS__) -#define vmsif_m_b64_m(...) __riscv_vmsif_m_b64_mu(__VA_ARGS__) -#define vmsof_m_b1(...) __riscv_vmsof_m_b1(__VA_ARGS__) -#define vmsof_m_b2(...) __riscv_vmsof_m_b2(__VA_ARGS__) -#define vmsof_m_b4(...) __riscv_vmsof_m_b4(__VA_ARGS__) -#define vmsof_m_b8(...) __riscv_vmsof_m_b8(__VA_ARGS__) -#define vmsof_m_b16(...) __riscv_vmsof_m_b16(__VA_ARGS__) -#define vmsof_m_b32(...) __riscv_vmsof_m_b32(__VA_ARGS__) -#define vmsof_m_b64(...) __riscv_vmsof_m_b64(__VA_ARGS__) -// masked functions -#define vmsof_m_b1_m(...) __riscv_vmsof_m_b1_mu(__VA_ARGS__) -#define vmsof_m_b2_m(...) __riscv_vmsof_m_b2_mu(__VA_ARGS__) -#define vmsof_m_b4_m(...) __riscv_vmsof_m_b4_mu(__VA_ARGS__) -#define vmsof_m_b8_m(...) __riscv_vmsof_m_b8_mu(__VA_ARGS__) -#define vmsof_m_b16_m(...) __riscv_vmsof_m_b16_mu(__VA_ARGS__) -#define vmsof_m_b32_m(...) __riscv_vmsof_m_b32_mu(__VA_ARGS__) -#define vmsof_m_b64_m(...) __riscv_vmsof_m_b64_mu(__VA_ARGS__) -#define viota_m_u8mf8(...) __riscv_viota_m_u8mf8(__VA_ARGS__) -#define viota_m_u8mf4(...) __riscv_viota_m_u8mf4(__VA_ARGS__) -#define viota_m_u8mf2(...) __riscv_viota_m_u8mf2(__VA_ARGS__) -#define viota_m_u8m1(...) __riscv_viota_m_u8m1(__VA_ARGS__) -#define viota_m_u8m2(...) __riscv_viota_m_u8m2(__VA_ARGS__) -#define viota_m_u8m4(...) __riscv_viota_m_u8m4(__VA_ARGS__) -#define viota_m_u8m8(...) __riscv_viota_m_u8m8(__VA_ARGS__) -#define viota_m_u16mf4(...) __riscv_viota_m_u16mf4(__VA_ARGS__) -#define viota_m_u16mf2(...) __riscv_viota_m_u16mf2(__VA_ARGS__) -#define viota_m_u16m1(...) __riscv_viota_m_u16m1(__VA_ARGS__) -#define viota_m_u16m2(...) __riscv_viota_m_u16m2(__VA_ARGS__) -#define viota_m_u16m4(...) __riscv_viota_m_u16m4(__VA_ARGS__) -#define viota_m_u16m8(...) __riscv_viota_m_u16m8(__VA_ARGS__) -#define viota_m_u32mf2(...) __riscv_viota_m_u32mf2(__VA_ARGS__) -#define viota_m_u32m1(...) __riscv_viota_m_u32m1(__VA_ARGS__) -#define viota_m_u32m2(...) __riscv_viota_m_u32m2(__VA_ARGS__) -#define viota_m_u32m4(...) __riscv_viota_m_u32m4(__VA_ARGS__) -#define viota_m_u32m8(...) __riscv_viota_m_u32m8(__VA_ARGS__) -#define viota_m_u64m1(...) __riscv_viota_m_u64m1(__VA_ARGS__) -#define viota_m_u64m2(...) __riscv_viota_m_u64m2(__VA_ARGS__) -#define viota_m_u64m4(...) __riscv_viota_m_u64m4(__VA_ARGS__) -#define viota_m_u64m8(...) __riscv_viota_m_u64m8(__VA_ARGS__) -// masked functions -#define viota_m_u8mf8_m(...) __riscv_viota_m_u8mf8_tumu(__VA_ARGS__) -#define viota_m_u8mf4_m(...) __riscv_viota_m_u8mf4_tumu(__VA_ARGS__) -#define viota_m_u8mf2_m(...) __riscv_viota_m_u8mf2_tumu(__VA_ARGS__) -#define viota_m_u8m1_m(...) __riscv_viota_m_u8m1_tumu(__VA_ARGS__) -#define viota_m_u8m2_m(...) __riscv_viota_m_u8m2_tumu(__VA_ARGS__) -#define viota_m_u8m4_m(...) __riscv_viota_m_u8m4_tumu(__VA_ARGS__) -#define viota_m_u8m8_m(...) __riscv_viota_m_u8m8_tumu(__VA_ARGS__) -#define viota_m_u16mf4_m(...) __riscv_viota_m_u16mf4_tumu(__VA_ARGS__) -#define viota_m_u16mf2_m(...) __riscv_viota_m_u16mf2_tumu(__VA_ARGS__) -#define viota_m_u16m1_m(...) __riscv_viota_m_u16m1_tumu(__VA_ARGS__) -#define viota_m_u16m2_m(...) __riscv_viota_m_u16m2_tumu(__VA_ARGS__) -#define viota_m_u16m4_m(...) __riscv_viota_m_u16m4_tumu(__VA_ARGS__) -#define viota_m_u16m8_m(...) __riscv_viota_m_u16m8_tumu(__VA_ARGS__) -#define viota_m_u32mf2_m(...) __riscv_viota_m_u32mf2_tumu(__VA_ARGS__) -#define viota_m_u32m1_m(...) __riscv_viota_m_u32m1_tumu(__VA_ARGS__) -#define viota_m_u32m2_m(...) __riscv_viota_m_u32m2_tumu(__VA_ARGS__) -#define viota_m_u32m4_m(...) __riscv_viota_m_u32m4_tumu(__VA_ARGS__) -#define viota_m_u32m8_m(...) __riscv_viota_m_u32m8_tumu(__VA_ARGS__) -#define viota_m_u64m1_m(...) __riscv_viota_m_u64m1_tumu(__VA_ARGS__) -#define viota_m_u64m2_m(...) __riscv_viota_m_u64m2_tumu(__VA_ARGS__) -#define viota_m_u64m4_m(...) __riscv_viota_m_u64m4_tumu(__VA_ARGS__) -#define viota_m_u64m8_m(...) __riscv_viota_m_u64m8_tumu(__VA_ARGS__) -#define vid_v_u8mf8(...) __riscv_vid_v_u8mf8(__VA_ARGS__) -#define vid_v_u8mf4(...) __riscv_vid_v_u8mf4(__VA_ARGS__) -#define vid_v_u8mf2(...) __riscv_vid_v_u8mf2(__VA_ARGS__) -#define vid_v_u8m1(...) __riscv_vid_v_u8m1(__VA_ARGS__) -#define vid_v_u8m2(...) __riscv_vid_v_u8m2(__VA_ARGS__) -#define vid_v_u8m4(...) __riscv_vid_v_u8m4(__VA_ARGS__) -#define vid_v_u8m8(...) __riscv_vid_v_u8m8(__VA_ARGS__) -#define vid_v_u16mf4(...) __riscv_vid_v_u16mf4(__VA_ARGS__) -#define vid_v_u16mf2(...) __riscv_vid_v_u16mf2(__VA_ARGS__) -#define vid_v_u16m1(...) __riscv_vid_v_u16m1(__VA_ARGS__) -#define vid_v_u16m2(...) __riscv_vid_v_u16m2(__VA_ARGS__) -#define vid_v_u16m4(...) __riscv_vid_v_u16m4(__VA_ARGS__) -#define vid_v_u16m8(...) __riscv_vid_v_u16m8(__VA_ARGS__) -#define vid_v_u32mf2(...) __riscv_vid_v_u32mf2(__VA_ARGS__) -#define vid_v_u32m1(...) __riscv_vid_v_u32m1(__VA_ARGS__) -#define vid_v_u32m2(...) __riscv_vid_v_u32m2(__VA_ARGS__) -#define vid_v_u32m4(...) __riscv_vid_v_u32m4(__VA_ARGS__) -#define vid_v_u32m8(...) __riscv_vid_v_u32m8(__VA_ARGS__) -#define vid_v_u64m1(...) __riscv_vid_v_u64m1(__VA_ARGS__) -#define vid_v_u64m2(...) __riscv_vid_v_u64m2(__VA_ARGS__) -#define vid_v_u64m4(...) __riscv_vid_v_u64m4(__VA_ARGS__) -#define vid_v_u64m8(...) __riscv_vid_v_u64m8(__VA_ARGS__) -// masked functions -#define vid_v_u8mf8_m(...) __riscv_vid_v_u8mf8_tumu(__VA_ARGS__) -#define vid_v_u8mf4_m(...) __riscv_vid_v_u8mf4_tumu(__VA_ARGS__) -#define vid_v_u8mf2_m(...) __riscv_vid_v_u8mf2_tumu(__VA_ARGS__) -#define vid_v_u8m1_m(...) __riscv_vid_v_u8m1_tumu(__VA_ARGS__) -#define vid_v_u8m2_m(...) __riscv_vid_v_u8m2_tumu(__VA_ARGS__) -#define vid_v_u8m4_m(...) __riscv_vid_v_u8m4_tumu(__VA_ARGS__) -#define vid_v_u8m8_m(...) __riscv_vid_v_u8m8_tumu(__VA_ARGS__) -#define vid_v_u16mf4_m(...) __riscv_vid_v_u16mf4_tumu(__VA_ARGS__) -#define vid_v_u16mf2_m(...) __riscv_vid_v_u16mf2_tumu(__VA_ARGS__) -#define vid_v_u16m1_m(...) __riscv_vid_v_u16m1_tumu(__VA_ARGS__) -#define vid_v_u16m2_m(...) __riscv_vid_v_u16m2_tumu(__VA_ARGS__) -#define vid_v_u16m4_m(...) __riscv_vid_v_u16m4_tumu(__VA_ARGS__) -#define vid_v_u16m8_m(...) __riscv_vid_v_u16m8_tumu(__VA_ARGS__) -#define vid_v_u32mf2_m(...) __riscv_vid_v_u32mf2_tumu(__VA_ARGS__) -#define vid_v_u32m1_m(...) __riscv_vid_v_u32m1_tumu(__VA_ARGS__) -#define vid_v_u32m2_m(...) __riscv_vid_v_u32m2_tumu(__VA_ARGS__) -#define vid_v_u32m4_m(...) __riscv_vid_v_u32m4_tumu(__VA_ARGS__) -#define vid_v_u32m8_m(...) __riscv_vid_v_u32m8_tumu(__VA_ARGS__) -#define vid_v_u64m1_m(...) __riscv_vid_v_u64m1_tumu(__VA_ARGS__) -#define vid_v_u64m2_m(...) __riscv_vid_v_u64m2_tumu(__VA_ARGS__) -#define vid_v_u64m4_m(...) __riscv_vid_v_u64m4_tumu(__VA_ARGS__) -#define vid_v_u64m8_m(...) __riscv_vid_v_u64m8_tumu(__VA_ARGS__) -#define vfmv_f_s_f16mf4_f16(...) __riscv_vfmv_f_s_f16mf4_f16(__VA_ARGS__) -#define vfmv_s_f_f16mf4(...) __riscv_vfmv_s_f_f16mf4_tu(__VA_ARGS__) -#define vfmv_f_s_f16mf2_f16(...) __riscv_vfmv_f_s_f16mf2_f16(__VA_ARGS__) -#define vfmv_s_f_f16mf2(...) __riscv_vfmv_s_f_f16mf2_tu(__VA_ARGS__) -#define vfmv_f_s_f16m1_f16(...) __riscv_vfmv_f_s_f16m1_f16(__VA_ARGS__) -#define vfmv_s_f_f16m1(...) __riscv_vfmv_s_f_f16m1_tu(__VA_ARGS__) -#define vfmv_f_s_f16m2_f16(...) __riscv_vfmv_f_s_f16m2_f16(__VA_ARGS__) -#define vfmv_s_f_f16m2(...) __riscv_vfmv_s_f_f16m2_tu(__VA_ARGS__) -#define vfmv_f_s_f16m4_f16(...) __riscv_vfmv_f_s_f16m4_f16(__VA_ARGS__) -#define vfmv_s_f_f16m4(...) __riscv_vfmv_s_f_f16m4_tu(__VA_ARGS__) -#define vfmv_f_s_f16m8_f16(...) __riscv_vfmv_f_s_f16m8_f16(__VA_ARGS__) -#define vfmv_s_f_f16m8(...) __riscv_vfmv_s_f_f16m8_tu(__VA_ARGS__) -#define vfmv_f_s_f32mf2_f32(...) __riscv_vfmv_f_s_f32mf2_f32(__VA_ARGS__) -#define vfmv_s_f_f32mf2(...) __riscv_vfmv_s_f_f32mf2_tu(__VA_ARGS__) -#define vfmv_f_s_f32m1_f32(...) __riscv_vfmv_f_s_f32m1_f32(__VA_ARGS__) -#define vfmv_s_f_f32m1(...) __riscv_vfmv_s_f_f32m1_tu(__VA_ARGS__) -#define vfmv_f_s_f32m2_f32(...) __riscv_vfmv_f_s_f32m2_f32(__VA_ARGS__) -#define vfmv_s_f_f32m2(...) __riscv_vfmv_s_f_f32m2_tu(__VA_ARGS__) -#define vfmv_f_s_f32m4_f32(...) __riscv_vfmv_f_s_f32m4_f32(__VA_ARGS__) -#define vfmv_s_f_f32m4(...) __riscv_vfmv_s_f_f32m4_tu(__VA_ARGS__) -#define vfmv_f_s_f32m8_f32(...) __riscv_vfmv_f_s_f32m8_f32(__VA_ARGS__) -#define vfmv_s_f_f32m8(...) __riscv_vfmv_s_f_f32m8_tu(__VA_ARGS__) -#define vfmv_f_s_f64m1_f64(...) __riscv_vfmv_f_s_f64m1_f64(__VA_ARGS__) -#define vfmv_s_f_f64m1(...) __riscv_vfmv_s_f_f64m1_tu(__VA_ARGS__) -#define vfmv_f_s_f64m2_f64(...) __riscv_vfmv_f_s_f64m2_f64(__VA_ARGS__) -#define vfmv_s_f_f64m2(...) __riscv_vfmv_s_f_f64m2_tu(__VA_ARGS__) -#define vfmv_f_s_f64m4_f64(...) __riscv_vfmv_f_s_f64m4_f64(__VA_ARGS__) -#define vfmv_s_f_f64m4(...) __riscv_vfmv_s_f_f64m4_tu(__VA_ARGS__) -#define vfmv_f_s_f64m8_f64(...) __riscv_vfmv_f_s_f64m8_f64(__VA_ARGS__) -#define vfmv_s_f_f64m8(...) __riscv_vfmv_s_f_f64m8_tu(__VA_ARGS__) -#define vmv_x_s_i8mf8_i8(...) __riscv_vmv_x_s_i8mf8_i8(__VA_ARGS__) -#define vmv_s_x_i8mf8(...) __riscv_vmv_s_x_i8mf8_tu(__VA_ARGS__) -#define vmv_x_s_i8mf4_i8(...) __riscv_vmv_x_s_i8mf4_i8(__VA_ARGS__) -#define vmv_s_x_i8mf4(...) __riscv_vmv_s_x_i8mf4_tu(__VA_ARGS__) -#define vmv_x_s_i8mf2_i8(...) __riscv_vmv_x_s_i8mf2_i8(__VA_ARGS__) -#define vmv_s_x_i8mf2(...) __riscv_vmv_s_x_i8mf2_tu(__VA_ARGS__) -#define vmv_x_s_i8m1_i8(...) __riscv_vmv_x_s_i8m1_i8(__VA_ARGS__) -#define vmv_s_x_i8m1(...) __riscv_vmv_s_x_i8m1_tu(__VA_ARGS__) -#define vmv_x_s_i8m2_i8(...) __riscv_vmv_x_s_i8m2_i8(__VA_ARGS__) -#define vmv_s_x_i8m2(...) __riscv_vmv_s_x_i8m2_tu(__VA_ARGS__) -#define vmv_x_s_i8m4_i8(...) __riscv_vmv_x_s_i8m4_i8(__VA_ARGS__) -#define vmv_s_x_i8m4(...) __riscv_vmv_s_x_i8m4_tu(__VA_ARGS__) -#define vmv_x_s_i8m8_i8(...) __riscv_vmv_x_s_i8m8_i8(__VA_ARGS__) -#define vmv_s_x_i8m8(...) __riscv_vmv_s_x_i8m8_tu(__VA_ARGS__) -#define vmv_x_s_i16mf4_i16(...) __riscv_vmv_x_s_i16mf4_i16(__VA_ARGS__) -#define vmv_s_x_i16mf4(...) __riscv_vmv_s_x_i16mf4_tu(__VA_ARGS__) -#define vmv_x_s_i16mf2_i16(...) __riscv_vmv_x_s_i16mf2_i16(__VA_ARGS__) -#define vmv_s_x_i16mf2(...) __riscv_vmv_s_x_i16mf2_tu(__VA_ARGS__) -#define vmv_x_s_i16m1_i16(...) __riscv_vmv_x_s_i16m1_i16(__VA_ARGS__) -#define vmv_s_x_i16m1(...) __riscv_vmv_s_x_i16m1_tu(__VA_ARGS__) -#define vmv_x_s_i16m2_i16(...) __riscv_vmv_x_s_i16m2_i16(__VA_ARGS__) -#define vmv_s_x_i16m2(...) __riscv_vmv_s_x_i16m2_tu(__VA_ARGS__) -#define vmv_x_s_i16m4_i16(...) __riscv_vmv_x_s_i16m4_i16(__VA_ARGS__) -#define vmv_s_x_i16m4(...) __riscv_vmv_s_x_i16m4_tu(__VA_ARGS__) -#define vmv_x_s_i16m8_i16(...) __riscv_vmv_x_s_i16m8_i16(__VA_ARGS__) -#define vmv_s_x_i16m8(...) __riscv_vmv_s_x_i16m8_tu(__VA_ARGS__) -#define vmv_x_s_i32mf2_i32(...) __riscv_vmv_x_s_i32mf2_i32(__VA_ARGS__) -#define vmv_s_x_i32mf2(...) __riscv_vmv_s_x_i32mf2_tu(__VA_ARGS__) -#define vmv_x_s_i32m1_i32(...) __riscv_vmv_x_s_i32m1_i32(__VA_ARGS__) -#define vmv_s_x_i32m1(...) __riscv_vmv_s_x_i32m1_tu(__VA_ARGS__) -#define vmv_x_s_i32m2_i32(...) __riscv_vmv_x_s_i32m2_i32(__VA_ARGS__) -#define vmv_s_x_i32m2(...) __riscv_vmv_s_x_i32m2_tu(__VA_ARGS__) -#define vmv_x_s_i32m4_i32(...) __riscv_vmv_x_s_i32m4_i32(__VA_ARGS__) -#define vmv_s_x_i32m4(...) __riscv_vmv_s_x_i32m4_tu(__VA_ARGS__) -#define vmv_x_s_i32m8_i32(...) __riscv_vmv_x_s_i32m8_i32(__VA_ARGS__) -#define vmv_s_x_i32m8(...) __riscv_vmv_s_x_i32m8_tu(__VA_ARGS__) -#define vmv_x_s_i64m1_i64(...) __riscv_vmv_x_s_i64m1_i64(__VA_ARGS__) -#define vmv_s_x_i64m1(...) __riscv_vmv_s_x_i64m1_tu(__VA_ARGS__) -#define vmv_x_s_i64m2_i64(...) __riscv_vmv_x_s_i64m2_i64(__VA_ARGS__) -#define vmv_s_x_i64m2(...) __riscv_vmv_s_x_i64m2_tu(__VA_ARGS__) -#define vmv_x_s_i64m4_i64(...) __riscv_vmv_x_s_i64m4_i64(__VA_ARGS__) -#define vmv_s_x_i64m4(...) __riscv_vmv_s_x_i64m4_tu(__VA_ARGS__) -#define vmv_x_s_i64m8_i64(...) __riscv_vmv_x_s_i64m8_i64(__VA_ARGS__) -#define vmv_s_x_i64m8(...) __riscv_vmv_s_x_i64m8_tu(__VA_ARGS__) -#define vmv_x_s_u8mf8_u8(...) __riscv_vmv_x_s_u8mf8_u8(__VA_ARGS__) -#define vmv_s_x_u8mf8(...) __riscv_vmv_s_x_u8mf8_tu(__VA_ARGS__) -#define vmv_x_s_u8mf4_u8(...) __riscv_vmv_x_s_u8mf4_u8(__VA_ARGS__) -#define vmv_s_x_u8mf4(...) __riscv_vmv_s_x_u8mf4_tu(__VA_ARGS__) -#define vmv_x_s_u8mf2_u8(...) __riscv_vmv_x_s_u8mf2_u8(__VA_ARGS__) -#define vmv_s_x_u8mf2(...) __riscv_vmv_s_x_u8mf2_tu(__VA_ARGS__) -#define vmv_x_s_u8m1_u8(...) __riscv_vmv_x_s_u8m1_u8(__VA_ARGS__) -#define vmv_s_x_u8m1(...) __riscv_vmv_s_x_u8m1_tu(__VA_ARGS__) -#define vmv_x_s_u8m2_u8(...) __riscv_vmv_x_s_u8m2_u8(__VA_ARGS__) -#define vmv_s_x_u8m2(...) __riscv_vmv_s_x_u8m2_tu(__VA_ARGS__) -#define vmv_x_s_u8m4_u8(...) __riscv_vmv_x_s_u8m4_u8(__VA_ARGS__) -#define vmv_s_x_u8m4(...) __riscv_vmv_s_x_u8m4_tu(__VA_ARGS__) -#define vmv_x_s_u8m8_u8(...) __riscv_vmv_x_s_u8m8_u8(__VA_ARGS__) -#define vmv_s_x_u8m8(...) __riscv_vmv_s_x_u8m8_tu(__VA_ARGS__) -#define vmv_x_s_u16mf4_u16(...) __riscv_vmv_x_s_u16mf4_u16(__VA_ARGS__) -#define vmv_s_x_u16mf4(...) __riscv_vmv_s_x_u16mf4_tu(__VA_ARGS__) -#define vmv_x_s_u16mf2_u16(...) __riscv_vmv_x_s_u16mf2_u16(__VA_ARGS__) -#define vmv_s_x_u16mf2(...) __riscv_vmv_s_x_u16mf2_tu(__VA_ARGS__) -#define vmv_x_s_u16m1_u16(...) __riscv_vmv_x_s_u16m1_u16(__VA_ARGS__) -#define vmv_s_x_u16m1(...) __riscv_vmv_s_x_u16m1_tu(__VA_ARGS__) -#define vmv_x_s_u16m2_u16(...) __riscv_vmv_x_s_u16m2_u16(__VA_ARGS__) -#define vmv_s_x_u16m2(...) __riscv_vmv_s_x_u16m2_tu(__VA_ARGS__) -#define vmv_x_s_u16m4_u16(...) __riscv_vmv_x_s_u16m4_u16(__VA_ARGS__) -#define vmv_s_x_u16m4(...) __riscv_vmv_s_x_u16m4_tu(__VA_ARGS__) -#define vmv_x_s_u16m8_u16(...) __riscv_vmv_x_s_u16m8_u16(__VA_ARGS__) -#define vmv_s_x_u16m8(...) __riscv_vmv_s_x_u16m8_tu(__VA_ARGS__) -#define vmv_x_s_u32mf2_u32(...) __riscv_vmv_x_s_u32mf2_u32(__VA_ARGS__) -#define vmv_s_x_u32mf2(...) __riscv_vmv_s_x_u32mf2_tu(__VA_ARGS__) -#define vmv_x_s_u32m1_u32(...) __riscv_vmv_x_s_u32m1_u32(__VA_ARGS__) -#define vmv_s_x_u32m1(...) __riscv_vmv_s_x_u32m1_tu(__VA_ARGS__) -#define vmv_x_s_u32m2_u32(...) __riscv_vmv_x_s_u32m2_u32(__VA_ARGS__) -#define vmv_s_x_u32m2(...) __riscv_vmv_s_x_u32m2_tu(__VA_ARGS__) -#define vmv_x_s_u32m4_u32(...) __riscv_vmv_x_s_u32m4_u32(__VA_ARGS__) -#define vmv_s_x_u32m4(...) __riscv_vmv_s_x_u32m4_tu(__VA_ARGS__) -#define vmv_x_s_u32m8_u32(...) __riscv_vmv_x_s_u32m8_u32(__VA_ARGS__) -#define vmv_s_x_u32m8(...) __riscv_vmv_s_x_u32m8_tu(__VA_ARGS__) -#define vmv_x_s_u64m1_u64(...) __riscv_vmv_x_s_u64m1_u64(__VA_ARGS__) -#define vmv_s_x_u64m1(...) __riscv_vmv_s_x_u64m1_tu(__VA_ARGS__) -#define vmv_x_s_u64m2_u64(...) __riscv_vmv_x_s_u64m2_u64(__VA_ARGS__) -#define vmv_s_x_u64m2(...) __riscv_vmv_s_x_u64m2_tu(__VA_ARGS__) -#define vmv_x_s_u64m4_u64(...) __riscv_vmv_x_s_u64m4_u64(__VA_ARGS__) -#define vmv_s_x_u64m4(...) __riscv_vmv_s_x_u64m4_tu(__VA_ARGS__) -#define vmv_x_s_u64m8_u64(...) __riscv_vmv_x_s_u64m8_u64(__VA_ARGS__) -#define vmv_s_x_u64m8(...) __riscv_vmv_s_x_u64m8_tu(__VA_ARGS__) -#define vslideup_vx_f16mf4(...) __riscv_vslideup_vx_f16mf4_tu(__VA_ARGS__) -#define vslideup_vx_f16mf2(...) __riscv_vslideup_vx_f16mf2_tu(__VA_ARGS__) -#define vslideup_vx_f16m1(...) __riscv_vslideup_vx_f16m1_tu(__VA_ARGS__) -#define vslideup_vx_f16m2(...) __riscv_vslideup_vx_f16m2_tu(__VA_ARGS__) -#define vslideup_vx_f16m4(...) __riscv_vslideup_vx_f16m4_tu(__VA_ARGS__) -#define vslideup_vx_f16m8(...) __riscv_vslideup_vx_f16m8_tu(__VA_ARGS__) -#define vslideup_vx_f32mf2(...) __riscv_vslideup_vx_f32mf2_tu(__VA_ARGS__) -#define vslideup_vx_f32m1(...) __riscv_vslideup_vx_f32m1_tu(__VA_ARGS__) -#define vslideup_vx_f32m2(...) __riscv_vslideup_vx_f32m2_tu(__VA_ARGS__) -#define vslideup_vx_f32m4(...) __riscv_vslideup_vx_f32m4_tu(__VA_ARGS__) -#define vslideup_vx_f32m8(...) __riscv_vslideup_vx_f32m8_tu(__VA_ARGS__) -#define vslideup_vx_f64m1(...) __riscv_vslideup_vx_f64m1_tu(__VA_ARGS__) -#define vslideup_vx_f64m2(...) __riscv_vslideup_vx_f64m2_tu(__VA_ARGS__) -#define vslideup_vx_f64m4(...) __riscv_vslideup_vx_f64m4_tu(__VA_ARGS__) -#define vslideup_vx_f64m8(...) __riscv_vslideup_vx_f64m8_tu(__VA_ARGS__) -#define vslideup_vx_i8mf8(...) __riscv_vslideup_vx_i8mf8_tu(__VA_ARGS__) -#define vslideup_vx_i8mf4(...) __riscv_vslideup_vx_i8mf4_tu(__VA_ARGS__) -#define vslideup_vx_i8mf2(...) __riscv_vslideup_vx_i8mf2_tu(__VA_ARGS__) -#define vslideup_vx_i8m1(...) __riscv_vslideup_vx_i8m1_tu(__VA_ARGS__) -#define vslideup_vx_i8m2(...) __riscv_vslideup_vx_i8m2_tu(__VA_ARGS__) -#define vslideup_vx_i8m4(...) __riscv_vslideup_vx_i8m4_tu(__VA_ARGS__) -#define vslideup_vx_i8m8(...) __riscv_vslideup_vx_i8m8_tu(__VA_ARGS__) -#define vslideup_vx_i16mf4(...) __riscv_vslideup_vx_i16mf4_tu(__VA_ARGS__) -#define vslideup_vx_i16mf2(...) __riscv_vslideup_vx_i16mf2_tu(__VA_ARGS__) -#define vslideup_vx_i16m1(...) __riscv_vslideup_vx_i16m1_tu(__VA_ARGS__) -#define vslideup_vx_i16m2(...) __riscv_vslideup_vx_i16m2_tu(__VA_ARGS__) -#define vslideup_vx_i16m4(...) __riscv_vslideup_vx_i16m4_tu(__VA_ARGS__) -#define vslideup_vx_i16m8(...) __riscv_vslideup_vx_i16m8_tu(__VA_ARGS__) -#define vslideup_vx_i32mf2(...) __riscv_vslideup_vx_i32mf2_tu(__VA_ARGS__) -#define vslideup_vx_i32m1(...) __riscv_vslideup_vx_i32m1_tu(__VA_ARGS__) -#define vslideup_vx_i32m2(...) __riscv_vslideup_vx_i32m2_tu(__VA_ARGS__) -#define vslideup_vx_i32m4(...) __riscv_vslideup_vx_i32m4_tu(__VA_ARGS__) -#define vslideup_vx_i32m8(...) __riscv_vslideup_vx_i32m8_tu(__VA_ARGS__) -#define vslideup_vx_i64m1(...) __riscv_vslideup_vx_i64m1_tu(__VA_ARGS__) -#define vslideup_vx_i64m2(...) __riscv_vslideup_vx_i64m2_tu(__VA_ARGS__) -#define vslideup_vx_i64m4(...) __riscv_vslideup_vx_i64m4_tu(__VA_ARGS__) -#define vslideup_vx_i64m8(...) __riscv_vslideup_vx_i64m8_tu(__VA_ARGS__) -#define vslideup_vx_u8mf8(...) __riscv_vslideup_vx_u8mf8_tu(__VA_ARGS__) -#define vslideup_vx_u8mf4(...) __riscv_vslideup_vx_u8mf4_tu(__VA_ARGS__) -#define vslideup_vx_u8mf2(...) __riscv_vslideup_vx_u8mf2_tu(__VA_ARGS__) -#define vslideup_vx_u8m1(...) __riscv_vslideup_vx_u8m1_tu(__VA_ARGS__) -#define vslideup_vx_u8m2(...) __riscv_vslideup_vx_u8m2_tu(__VA_ARGS__) -#define vslideup_vx_u8m4(...) __riscv_vslideup_vx_u8m4_tu(__VA_ARGS__) -#define vslideup_vx_u8m8(...) __riscv_vslideup_vx_u8m8_tu(__VA_ARGS__) -#define vslideup_vx_u16mf4(...) __riscv_vslideup_vx_u16mf4_tu(__VA_ARGS__) -#define vslideup_vx_u16mf2(...) __riscv_vslideup_vx_u16mf2_tu(__VA_ARGS__) -#define vslideup_vx_u16m1(...) __riscv_vslideup_vx_u16m1_tu(__VA_ARGS__) -#define vslideup_vx_u16m2(...) __riscv_vslideup_vx_u16m2_tu(__VA_ARGS__) -#define vslideup_vx_u16m4(...) __riscv_vslideup_vx_u16m4_tu(__VA_ARGS__) -#define vslideup_vx_u16m8(...) __riscv_vslideup_vx_u16m8_tu(__VA_ARGS__) -#define vslideup_vx_u32mf2(...) __riscv_vslideup_vx_u32mf2_tu(__VA_ARGS__) -#define vslideup_vx_u32m1(...) __riscv_vslideup_vx_u32m1_tu(__VA_ARGS__) -#define vslideup_vx_u32m2(...) __riscv_vslideup_vx_u32m2_tu(__VA_ARGS__) -#define vslideup_vx_u32m4(...) __riscv_vslideup_vx_u32m4_tu(__VA_ARGS__) -#define vslideup_vx_u32m8(...) __riscv_vslideup_vx_u32m8_tu(__VA_ARGS__) -#define vslideup_vx_u64m1(...) __riscv_vslideup_vx_u64m1_tu(__VA_ARGS__) -#define vslideup_vx_u64m2(...) __riscv_vslideup_vx_u64m2_tu(__VA_ARGS__) -#define vslideup_vx_u64m4(...) __riscv_vslideup_vx_u64m4_tu(__VA_ARGS__) -#define vslideup_vx_u64m8(...) __riscv_vslideup_vx_u64m8_tu(__VA_ARGS__) -// masked functions -#define vslideup_vx_f16mf4_m(...) __riscv_vslideup_vx_f16mf4_tumu(__VA_ARGS__) -#define vslideup_vx_f16mf2_m(...) __riscv_vslideup_vx_f16mf2_tumu(__VA_ARGS__) -#define vslideup_vx_f16m1_m(...) __riscv_vslideup_vx_f16m1_tumu(__VA_ARGS__) -#define vslideup_vx_f16m2_m(...) __riscv_vslideup_vx_f16m2_tumu(__VA_ARGS__) -#define vslideup_vx_f16m4_m(...) __riscv_vslideup_vx_f16m4_tumu(__VA_ARGS__) -#define vslideup_vx_f16m8_m(...) __riscv_vslideup_vx_f16m8_tumu(__VA_ARGS__) -#define vslideup_vx_f32mf2_m(...) __riscv_vslideup_vx_f32mf2_tumu(__VA_ARGS__) -#define vslideup_vx_f32m1_m(...) __riscv_vslideup_vx_f32m1_tumu(__VA_ARGS__) -#define vslideup_vx_f32m2_m(...) __riscv_vslideup_vx_f32m2_tumu(__VA_ARGS__) -#define vslideup_vx_f32m4_m(...) __riscv_vslideup_vx_f32m4_tumu(__VA_ARGS__) -#define vslideup_vx_f32m8_m(...) __riscv_vslideup_vx_f32m8_tumu(__VA_ARGS__) -#define vslideup_vx_f64m1_m(...) __riscv_vslideup_vx_f64m1_tumu(__VA_ARGS__) -#define vslideup_vx_f64m2_m(...) __riscv_vslideup_vx_f64m2_tumu(__VA_ARGS__) -#define vslideup_vx_f64m4_m(...) __riscv_vslideup_vx_f64m4_tumu(__VA_ARGS__) -#define vslideup_vx_f64m8_m(...) __riscv_vslideup_vx_f64m8_tumu(__VA_ARGS__) -#define vslideup_vx_i8mf8_m(...) __riscv_vslideup_vx_i8mf8_tumu(__VA_ARGS__) -#define vslideup_vx_i8mf4_m(...) __riscv_vslideup_vx_i8mf4_tumu(__VA_ARGS__) -#define vslideup_vx_i8mf2_m(...) __riscv_vslideup_vx_i8mf2_tumu(__VA_ARGS__) -#define vslideup_vx_i8m1_m(...) __riscv_vslideup_vx_i8m1_tumu(__VA_ARGS__) -#define vslideup_vx_i8m2_m(...) __riscv_vslideup_vx_i8m2_tumu(__VA_ARGS__) -#define vslideup_vx_i8m4_m(...) __riscv_vslideup_vx_i8m4_tumu(__VA_ARGS__) -#define vslideup_vx_i8m8_m(...) __riscv_vslideup_vx_i8m8_tumu(__VA_ARGS__) -#define vslideup_vx_i16mf4_m(...) __riscv_vslideup_vx_i16mf4_tumu(__VA_ARGS__) -#define vslideup_vx_i16mf2_m(...) __riscv_vslideup_vx_i16mf2_tumu(__VA_ARGS__) -#define vslideup_vx_i16m1_m(...) __riscv_vslideup_vx_i16m1_tumu(__VA_ARGS__) -#define vslideup_vx_i16m2_m(...) __riscv_vslideup_vx_i16m2_tumu(__VA_ARGS__) -#define vslideup_vx_i16m4_m(...) __riscv_vslideup_vx_i16m4_tumu(__VA_ARGS__) -#define vslideup_vx_i16m8_m(...) __riscv_vslideup_vx_i16m8_tumu(__VA_ARGS__) -#define vslideup_vx_i32mf2_m(...) __riscv_vslideup_vx_i32mf2_tumu(__VA_ARGS__) -#define vslideup_vx_i32m1_m(...) __riscv_vslideup_vx_i32m1_tumu(__VA_ARGS__) -#define vslideup_vx_i32m2_m(...) __riscv_vslideup_vx_i32m2_tumu(__VA_ARGS__) -#define vslideup_vx_i32m4_m(...) __riscv_vslideup_vx_i32m4_tumu(__VA_ARGS__) -#define vslideup_vx_i32m8_m(...) __riscv_vslideup_vx_i32m8_tumu(__VA_ARGS__) -#define vslideup_vx_i64m1_m(...) __riscv_vslideup_vx_i64m1_tumu(__VA_ARGS__) -#define vslideup_vx_i64m2_m(...) __riscv_vslideup_vx_i64m2_tumu(__VA_ARGS__) -#define vslideup_vx_i64m4_m(...) __riscv_vslideup_vx_i64m4_tumu(__VA_ARGS__) -#define vslideup_vx_i64m8_m(...) __riscv_vslideup_vx_i64m8_tumu(__VA_ARGS__) -#define vslideup_vx_u8mf8_m(...) __riscv_vslideup_vx_u8mf8_tumu(__VA_ARGS__) -#define vslideup_vx_u8mf4_m(...) __riscv_vslideup_vx_u8mf4_tumu(__VA_ARGS__) -#define vslideup_vx_u8mf2_m(...) __riscv_vslideup_vx_u8mf2_tumu(__VA_ARGS__) -#define vslideup_vx_u8m1_m(...) __riscv_vslideup_vx_u8m1_tumu(__VA_ARGS__) -#define vslideup_vx_u8m2_m(...) __riscv_vslideup_vx_u8m2_tumu(__VA_ARGS__) -#define vslideup_vx_u8m4_m(...) __riscv_vslideup_vx_u8m4_tumu(__VA_ARGS__) -#define vslideup_vx_u8m8_m(...) __riscv_vslideup_vx_u8m8_tumu(__VA_ARGS__) -#define vslideup_vx_u16mf4_m(...) __riscv_vslideup_vx_u16mf4_tumu(__VA_ARGS__) -#define vslideup_vx_u16mf2_m(...) __riscv_vslideup_vx_u16mf2_tumu(__VA_ARGS__) -#define vslideup_vx_u16m1_m(...) __riscv_vslideup_vx_u16m1_tumu(__VA_ARGS__) -#define vslideup_vx_u16m2_m(...) __riscv_vslideup_vx_u16m2_tumu(__VA_ARGS__) -#define vslideup_vx_u16m4_m(...) __riscv_vslideup_vx_u16m4_tumu(__VA_ARGS__) -#define vslideup_vx_u16m8_m(...) __riscv_vslideup_vx_u16m8_tumu(__VA_ARGS__) -#define vslideup_vx_u32mf2_m(...) __riscv_vslideup_vx_u32mf2_tumu(__VA_ARGS__) -#define vslideup_vx_u32m1_m(...) __riscv_vslideup_vx_u32m1_tumu(__VA_ARGS__) -#define vslideup_vx_u32m2_m(...) __riscv_vslideup_vx_u32m2_tumu(__VA_ARGS__) -#define vslideup_vx_u32m4_m(...) __riscv_vslideup_vx_u32m4_tumu(__VA_ARGS__) -#define vslideup_vx_u32m8_m(...) __riscv_vslideup_vx_u32m8_tumu(__VA_ARGS__) -#define vslideup_vx_u64m1_m(...) __riscv_vslideup_vx_u64m1_tumu(__VA_ARGS__) -#define vslideup_vx_u64m2_m(...) __riscv_vslideup_vx_u64m2_tumu(__VA_ARGS__) -#define vslideup_vx_u64m4_m(...) __riscv_vslideup_vx_u64m4_tumu(__VA_ARGS__) -#define vslideup_vx_u64m8_m(...) __riscv_vslideup_vx_u64m8_tumu(__VA_ARGS__) -#define vslidedown_vx_f16mf4(...) __riscv_vslidedown_vx_f16mf4_tu(__VA_ARGS__) -#define vslidedown_vx_f16mf2(...) __riscv_vslidedown_vx_f16mf2_tu(__VA_ARGS__) -#define vslidedown_vx_f16m1(...) __riscv_vslidedown_vx_f16m1_tu(__VA_ARGS__) -#define vslidedown_vx_f16m2(...) __riscv_vslidedown_vx_f16m2_tu(__VA_ARGS__) -#define vslidedown_vx_f16m4(...) __riscv_vslidedown_vx_f16m4_tu(__VA_ARGS__) -#define vslidedown_vx_f16m8(...) __riscv_vslidedown_vx_f16m8_tu(__VA_ARGS__) -#define vslidedown_vx_f32mf2(...) __riscv_vslidedown_vx_f32mf2_tu(__VA_ARGS__) -#define vslidedown_vx_f32m1(...) __riscv_vslidedown_vx_f32m1_tu(__VA_ARGS__) -#define vslidedown_vx_f32m2(...) __riscv_vslidedown_vx_f32m2_tu(__VA_ARGS__) -#define vslidedown_vx_f32m4(...) __riscv_vslidedown_vx_f32m4_tu(__VA_ARGS__) -#define vslidedown_vx_f32m8(...) __riscv_vslidedown_vx_f32m8_tu(__VA_ARGS__) -#define vslidedown_vx_f64m1(...) __riscv_vslidedown_vx_f64m1_tu(__VA_ARGS__) -#define vslidedown_vx_f64m2(...) __riscv_vslidedown_vx_f64m2_tu(__VA_ARGS__) -#define vslidedown_vx_f64m4(...) __riscv_vslidedown_vx_f64m4_tu(__VA_ARGS__) -#define vslidedown_vx_f64m8(...) __riscv_vslidedown_vx_f64m8_tu(__VA_ARGS__) -#define vslidedown_vx_i8mf8(...) __riscv_vslidedown_vx_i8mf8_tu(__VA_ARGS__) -#define vslidedown_vx_i8mf4(...) __riscv_vslidedown_vx_i8mf4_tu(__VA_ARGS__) -#define vslidedown_vx_i8mf2(...) __riscv_vslidedown_vx_i8mf2_tu(__VA_ARGS__) -#define vslidedown_vx_i8m1(...) __riscv_vslidedown_vx_i8m1_tu(__VA_ARGS__) -#define vslidedown_vx_i8m2(...) __riscv_vslidedown_vx_i8m2_tu(__VA_ARGS__) -#define vslidedown_vx_i8m4(...) __riscv_vslidedown_vx_i8m4_tu(__VA_ARGS__) -#define vslidedown_vx_i8m8(...) __riscv_vslidedown_vx_i8m8_tu(__VA_ARGS__) -#define vslidedown_vx_i16mf4(...) __riscv_vslidedown_vx_i16mf4_tu(__VA_ARGS__) -#define vslidedown_vx_i16mf2(...) __riscv_vslidedown_vx_i16mf2_tu(__VA_ARGS__) -#define vslidedown_vx_i16m1(...) __riscv_vslidedown_vx_i16m1_tu(__VA_ARGS__) -#define vslidedown_vx_i16m2(...) __riscv_vslidedown_vx_i16m2_tu(__VA_ARGS__) -#define vslidedown_vx_i16m4(...) __riscv_vslidedown_vx_i16m4_tu(__VA_ARGS__) -#define vslidedown_vx_i16m8(...) __riscv_vslidedown_vx_i16m8_tu(__VA_ARGS__) -#define vslidedown_vx_i32mf2(...) __riscv_vslidedown_vx_i32mf2_tu(__VA_ARGS__) -#define vslidedown_vx_i32m1(...) __riscv_vslidedown_vx_i32m1_tu(__VA_ARGS__) -#define vslidedown_vx_i32m2(...) __riscv_vslidedown_vx_i32m2_tu(__VA_ARGS__) -#define vslidedown_vx_i32m4(...) __riscv_vslidedown_vx_i32m4_tu(__VA_ARGS__) -#define vslidedown_vx_i32m8(...) __riscv_vslidedown_vx_i32m8_tu(__VA_ARGS__) -#define vslidedown_vx_i64m1(...) __riscv_vslidedown_vx_i64m1_tu(__VA_ARGS__) -#define vslidedown_vx_i64m2(...) __riscv_vslidedown_vx_i64m2_tu(__VA_ARGS__) -#define vslidedown_vx_i64m4(...) __riscv_vslidedown_vx_i64m4_tu(__VA_ARGS__) -#define vslidedown_vx_i64m8(...) __riscv_vslidedown_vx_i64m8_tu(__VA_ARGS__) -#define vslidedown_vx_u8mf8(...) __riscv_vslidedown_vx_u8mf8_tu(__VA_ARGS__) -#define vslidedown_vx_u8mf4(...) __riscv_vslidedown_vx_u8mf4_tu(__VA_ARGS__) -#define vslidedown_vx_u8mf2(...) __riscv_vslidedown_vx_u8mf2_tu(__VA_ARGS__) -#define vslidedown_vx_u8m1(...) __riscv_vslidedown_vx_u8m1_tu(__VA_ARGS__) -#define vslidedown_vx_u8m2(...) __riscv_vslidedown_vx_u8m2_tu(__VA_ARGS__) -#define vslidedown_vx_u8m4(...) __riscv_vslidedown_vx_u8m4_tu(__VA_ARGS__) -#define vslidedown_vx_u8m8(...) __riscv_vslidedown_vx_u8m8_tu(__VA_ARGS__) -#define vslidedown_vx_u16mf4(...) __riscv_vslidedown_vx_u16mf4_tu(__VA_ARGS__) -#define vslidedown_vx_u16mf2(...) __riscv_vslidedown_vx_u16mf2_tu(__VA_ARGS__) -#define vslidedown_vx_u16m1(...) __riscv_vslidedown_vx_u16m1_tu(__VA_ARGS__) -#define vslidedown_vx_u16m2(...) __riscv_vslidedown_vx_u16m2_tu(__VA_ARGS__) -#define vslidedown_vx_u16m4(...) __riscv_vslidedown_vx_u16m4_tu(__VA_ARGS__) -#define vslidedown_vx_u16m8(...) __riscv_vslidedown_vx_u16m8_tu(__VA_ARGS__) -#define vslidedown_vx_u32mf2(...) __riscv_vslidedown_vx_u32mf2_tu(__VA_ARGS__) -#define vslidedown_vx_u32m1(...) __riscv_vslidedown_vx_u32m1_tu(__VA_ARGS__) -#define vslidedown_vx_u32m2(...) __riscv_vslidedown_vx_u32m2_tu(__VA_ARGS__) -#define vslidedown_vx_u32m4(...) __riscv_vslidedown_vx_u32m4_tu(__VA_ARGS__) -#define vslidedown_vx_u32m8(...) __riscv_vslidedown_vx_u32m8_tu(__VA_ARGS__) -#define vslidedown_vx_u64m1(...) __riscv_vslidedown_vx_u64m1_tu(__VA_ARGS__) -#define vslidedown_vx_u64m2(...) __riscv_vslidedown_vx_u64m2_tu(__VA_ARGS__) -#define vslidedown_vx_u64m4(...) __riscv_vslidedown_vx_u64m4_tu(__VA_ARGS__) -#define vslidedown_vx_u64m8(...) __riscv_vslidedown_vx_u64m8_tu(__VA_ARGS__) -// masked functions -#define vslidedown_vx_f16mf4_m(...) __riscv_vslidedown_vx_f16mf4_tumu(__VA_ARGS__) -#define vslidedown_vx_f16mf2_m(...) __riscv_vslidedown_vx_f16mf2_tumu(__VA_ARGS__) -#define vslidedown_vx_f16m1_m(...) __riscv_vslidedown_vx_f16m1_tumu(__VA_ARGS__) -#define vslidedown_vx_f16m2_m(...) __riscv_vslidedown_vx_f16m2_tumu(__VA_ARGS__) -#define vslidedown_vx_f16m4_m(...) __riscv_vslidedown_vx_f16m4_tumu(__VA_ARGS__) -#define vslidedown_vx_f16m8_m(...) __riscv_vslidedown_vx_f16m8_tumu(__VA_ARGS__) -#define vslidedown_vx_f32mf2_m(...) __riscv_vslidedown_vx_f32mf2_tumu(__VA_ARGS__) -#define vslidedown_vx_f32m1_m(...) __riscv_vslidedown_vx_f32m1_tumu(__VA_ARGS__) -#define vslidedown_vx_f32m2_m(...) __riscv_vslidedown_vx_f32m2_tumu(__VA_ARGS__) -#define vslidedown_vx_f32m4_m(...) __riscv_vslidedown_vx_f32m4_tumu(__VA_ARGS__) -#define vslidedown_vx_f32m8_m(...) __riscv_vslidedown_vx_f32m8_tumu(__VA_ARGS__) -#define vslidedown_vx_f64m1_m(...) __riscv_vslidedown_vx_f64m1_tumu(__VA_ARGS__) -#define vslidedown_vx_f64m2_m(...) __riscv_vslidedown_vx_f64m2_tumu(__VA_ARGS__) -#define vslidedown_vx_f64m4_m(...) __riscv_vslidedown_vx_f64m4_tumu(__VA_ARGS__) -#define vslidedown_vx_f64m8_m(...) __riscv_vslidedown_vx_f64m8_tumu(__VA_ARGS__) -#define vslidedown_vx_i8mf8_m(...) __riscv_vslidedown_vx_i8mf8_tumu(__VA_ARGS__) -#define vslidedown_vx_i8mf4_m(...) __riscv_vslidedown_vx_i8mf4_tumu(__VA_ARGS__) -#define vslidedown_vx_i8mf2_m(...) __riscv_vslidedown_vx_i8mf2_tumu(__VA_ARGS__) -#define vslidedown_vx_i8m1_m(...) __riscv_vslidedown_vx_i8m1_tumu(__VA_ARGS__) -#define vslidedown_vx_i8m2_m(...) __riscv_vslidedown_vx_i8m2_tumu(__VA_ARGS__) -#define vslidedown_vx_i8m4_m(...) __riscv_vslidedown_vx_i8m4_tumu(__VA_ARGS__) -#define vslidedown_vx_i8m8_m(...) __riscv_vslidedown_vx_i8m8_tumu(__VA_ARGS__) -#define vslidedown_vx_i16mf4_m(...) __riscv_vslidedown_vx_i16mf4_tumu(__VA_ARGS__) -#define vslidedown_vx_i16mf2_m(...) __riscv_vslidedown_vx_i16mf2_tumu(__VA_ARGS__) -#define vslidedown_vx_i16m1_m(...) __riscv_vslidedown_vx_i16m1_tumu(__VA_ARGS__) -#define vslidedown_vx_i16m2_m(...) __riscv_vslidedown_vx_i16m2_tumu(__VA_ARGS__) -#define vslidedown_vx_i16m4_m(...) __riscv_vslidedown_vx_i16m4_tumu(__VA_ARGS__) -#define vslidedown_vx_i16m8_m(...) __riscv_vslidedown_vx_i16m8_tumu(__VA_ARGS__) -#define vslidedown_vx_i32mf2_m(...) __riscv_vslidedown_vx_i32mf2_tumu(__VA_ARGS__) -#define vslidedown_vx_i32m1_m(...) __riscv_vslidedown_vx_i32m1_tumu(__VA_ARGS__) -#define vslidedown_vx_i32m2_m(...) __riscv_vslidedown_vx_i32m2_tumu(__VA_ARGS__) -#define vslidedown_vx_i32m4_m(...) __riscv_vslidedown_vx_i32m4_tumu(__VA_ARGS__) -#define vslidedown_vx_i32m8_m(...) __riscv_vslidedown_vx_i32m8_tumu(__VA_ARGS__) -#define vslidedown_vx_i64m1_m(...) __riscv_vslidedown_vx_i64m1_tumu(__VA_ARGS__) -#define vslidedown_vx_i64m2_m(...) __riscv_vslidedown_vx_i64m2_tumu(__VA_ARGS__) -#define vslidedown_vx_i64m4_m(...) __riscv_vslidedown_vx_i64m4_tumu(__VA_ARGS__) -#define vslidedown_vx_i64m8_m(...) __riscv_vslidedown_vx_i64m8_tumu(__VA_ARGS__) -#define vslidedown_vx_u8mf8_m(...) __riscv_vslidedown_vx_u8mf8_tumu(__VA_ARGS__) -#define vslidedown_vx_u8mf4_m(...) __riscv_vslidedown_vx_u8mf4_tumu(__VA_ARGS__) -#define vslidedown_vx_u8mf2_m(...) __riscv_vslidedown_vx_u8mf2_tumu(__VA_ARGS__) -#define vslidedown_vx_u8m1_m(...) __riscv_vslidedown_vx_u8m1_tumu(__VA_ARGS__) -#define vslidedown_vx_u8m2_m(...) __riscv_vslidedown_vx_u8m2_tumu(__VA_ARGS__) -#define vslidedown_vx_u8m4_m(...) __riscv_vslidedown_vx_u8m4_tumu(__VA_ARGS__) -#define vslidedown_vx_u8m8_m(...) __riscv_vslidedown_vx_u8m8_tumu(__VA_ARGS__) -#define vslidedown_vx_u16mf4_m(...) __riscv_vslidedown_vx_u16mf4_tumu(__VA_ARGS__) -#define vslidedown_vx_u16mf2_m(...) __riscv_vslidedown_vx_u16mf2_tumu(__VA_ARGS__) -#define vslidedown_vx_u16m1_m(...) __riscv_vslidedown_vx_u16m1_tumu(__VA_ARGS__) -#define vslidedown_vx_u16m2_m(...) __riscv_vslidedown_vx_u16m2_tumu(__VA_ARGS__) -#define vslidedown_vx_u16m4_m(...) __riscv_vslidedown_vx_u16m4_tumu(__VA_ARGS__) -#define vslidedown_vx_u16m8_m(...) __riscv_vslidedown_vx_u16m8_tumu(__VA_ARGS__) -#define vslidedown_vx_u32mf2_m(...) __riscv_vslidedown_vx_u32mf2_tumu(__VA_ARGS__) -#define vslidedown_vx_u32m1_m(...) __riscv_vslidedown_vx_u32m1_tumu(__VA_ARGS__) -#define vslidedown_vx_u32m2_m(...) __riscv_vslidedown_vx_u32m2_tumu(__VA_ARGS__) -#define vslidedown_vx_u32m4_m(...) __riscv_vslidedown_vx_u32m4_tumu(__VA_ARGS__) -#define vslidedown_vx_u32m8_m(...) __riscv_vslidedown_vx_u32m8_tumu(__VA_ARGS__) -#define vslidedown_vx_u64m1_m(...) __riscv_vslidedown_vx_u64m1_tumu(__VA_ARGS__) -#define vslidedown_vx_u64m2_m(...) __riscv_vslidedown_vx_u64m2_tumu(__VA_ARGS__) -#define vslidedown_vx_u64m4_m(...) __riscv_vslidedown_vx_u64m4_tumu(__VA_ARGS__) -#define vslidedown_vx_u64m8_m(...) __riscv_vslidedown_vx_u64m8_tumu(__VA_ARGS__) -#define vfslide1up_vf_f16mf4(...) __riscv_vfslide1up_vf_f16mf4(__VA_ARGS__) -#define vfslide1up_vf_f16mf2(...) __riscv_vfslide1up_vf_f16mf2(__VA_ARGS__) -#define vfslide1up_vf_f16m1(...) __riscv_vfslide1up_vf_f16m1(__VA_ARGS__) -#define vfslide1up_vf_f16m2(...) __riscv_vfslide1up_vf_f16m2(__VA_ARGS__) -#define vfslide1up_vf_f16m4(...) __riscv_vfslide1up_vf_f16m4(__VA_ARGS__) -#define vfslide1up_vf_f16m8(...) __riscv_vfslide1up_vf_f16m8(__VA_ARGS__) -#define vfslide1up_vf_f32mf2(...) __riscv_vfslide1up_vf_f32mf2(__VA_ARGS__) -#define vfslide1up_vf_f32m1(...) __riscv_vfslide1up_vf_f32m1(__VA_ARGS__) -#define vfslide1up_vf_f32m2(...) __riscv_vfslide1up_vf_f32m2(__VA_ARGS__) -#define vfslide1up_vf_f32m4(...) __riscv_vfslide1up_vf_f32m4(__VA_ARGS__) -#define vfslide1up_vf_f32m8(...) __riscv_vfslide1up_vf_f32m8(__VA_ARGS__) -#define vfslide1up_vf_f64m1(...) __riscv_vfslide1up_vf_f64m1(__VA_ARGS__) -#define vfslide1up_vf_f64m2(...) __riscv_vfslide1up_vf_f64m2(__VA_ARGS__) -#define vfslide1up_vf_f64m4(...) __riscv_vfslide1up_vf_f64m4(__VA_ARGS__) -#define vfslide1up_vf_f64m8(...) __riscv_vfslide1up_vf_f64m8(__VA_ARGS__) -#define vfslide1down_vf_f16mf4(...) __riscv_vfslide1down_vf_f16mf4(__VA_ARGS__) -#define vfslide1down_vf_f16mf2(...) __riscv_vfslide1down_vf_f16mf2(__VA_ARGS__) -#define vfslide1down_vf_f16m1(...) __riscv_vfslide1down_vf_f16m1(__VA_ARGS__) -#define vfslide1down_vf_f16m2(...) __riscv_vfslide1down_vf_f16m2(__VA_ARGS__) -#define vfslide1down_vf_f16m4(...) __riscv_vfslide1down_vf_f16m4(__VA_ARGS__) -#define vfslide1down_vf_f16m8(...) __riscv_vfslide1down_vf_f16m8(__VA_ARGS__) -#define vfslide1down_vf_f32mf2(...) __riscv_vfslide1down_vf_f32mf2(__VA_ARGS__) -#define vfslide1down_vf_f32m1(...) __riscv_vfslide1down_vf_f32m1(__VA_ARGS__) -#define vfslide1down_vf_f32m2(...) __riscv_vfslide1down_vf_f32m2(__VA_ARGS__) -#define vfslide1down_vf_f32m4(...) __riscv_vfslide1down_vf_f32m4(__VA_ARGS__) -#define vfslide1down_vf_f32m8(...) __riscv_vfslide1down_vf_f32m8(__VA_ARGS__) -#define vfslide1down_vf_f64m1(...) __riscv_vfslide1down_vf_f64m1(__VA_ARGS__) -#define vfslide1down_vf_f64m2(...) __riscv_vfslide1down_vf_f64m2(__VA_ARGS__) -#define vfslide1down_vf_f64m4(...) __riscv_vfslide1down_vf_f64m4(__VA_ARGS__) -#define vfslide1down_vf_f64m8(...) __riscv_vfslide1down_vf_f64m8(__VA_ARGS__) -#define vslide1up_vx_i8mf8(...) __riscv_vslide1up_vx_i8mf8(__VA_ARGS__) -#define vslide1up_vx_i8mf4(...) __riscv_vslide1up_vx_i8mf4(__VA_ARGS__) -#define vslide1up_vx_i8mf2(...) __riscv_vslide1up_vx_i8mf2(__VA_ARGS__) -#define vslide1up_vx_i8m1(...) __riscv_vslide1up_vx_i8m1(__VA_ARGS__) -#define vslide1up_vx_i8m2(...) __riscv_vslide1up_vx_i8m2(__VA_ARGS__) -#define vslide1up_vx_i8m4(...) __riscv_vslide1up_vx_i8m4(__VA_ARGS__) -#define vslide1up_vx_i8m8(...) __riscv_vslide1up_vx_i8m8(__VA_ARGS__) -#define vslide1up_vx_i16mf4(...) __riscv_vslide1up_vx_i16mf4(__VA_ARGS__) -#define vslide1up_vx_i16mf2(...) __riscv_vslide1up_vx_i16mf2(__VA_ARGS__) -#define vslide1up_vx_i16m1(...) __riscv_vslide1up_vx_i16m1(__VA_ARGS__) -#define vslide1up_vx_i16m2(...) __riscv_vslide1up_vx_i16m2(__VA_ARGS__) -#define vslide1up_vx_i16m4(...) __riscv_vslide1up_vx_i16m4(__VA_ARGS__) -#define vslide1up_vx_i16m8(...) __riscv_vslide1up_vx_i16m8(__VA_ARGS__) -#define vslide1up_vx_i32mf2(...) __riscv_vslide1up_vx_i32mf2(__VA_ARGS__) -#define vslide1up_vx_i32m1(...) __riscv_vslide1up_vx_i32m1(__VA_ARGS__) -#define vslide1up_vx_i32m2(...) __riscv_vslide1up_vx_i32m2(__VA_ARGS__) -#define vslide1up_vx_i32m4(...) __riscv_vslide1up_vx_i32m4(__VA_ARGS__) -#define vslide1up_vx_i32m8(...) __riscv_vslide1up_vx_i32m8(__VA_ARGS__) -#define vslide1up_vx_i64m1(...) __riscv_vslide1up_vx_i64m1(__VA_ARGS__) -#define vslide1up_vx_i64m2(...) __riscv_vslide1up_vx_i64m2(__VA_ARGS__) -#define vslide1up_vx_i64m4(...) __riscv_vslide1up_vx_i64m4(__VA_ARGS__) -#define vslide1up_vx_i64m8(...) __riscv_vslide1up_vx_i64m8(__VA_ARGS__) -#define vslide1down_vx_i8mf8(...) __riscv_vslide1down_vx_i8mf8(__VA_ARGS__) -#define vslide1down_vx_i8mf4(...) __riscv_vslide1down_vx_i8mf4(__VA_ARGS__) -#define vslide1down_vx_i8mf2(...) __riscv_vslide1down_vx_i8mf2(__VA_ARGS__) -#define vslide1down_vx_i8m1(...) __riscv_vslide1down_vx_i8m1(__VA_ARGS__) -#define vslide1down_vx_i8m2(...) __riscv_vslide1down_vx_i8m2(__VA_ARGS__) -#define vslide1down_vx_i8m4(...) __riscv_vslide1down_vx_i8m4(__VA_ARGS__) -#define vslide1down_vx_i8m8(...) __riscv_vslide1down_vx_i8m8(__VA_ARGS__) -#define vslide1down_vx_i16mf4(...) __riscv_vslide1down_vx_i16mf4(__VA_ARGS__) -#define vslide1down_vx_i16mf2(...) __riscv_vslide1down_vx_i16mf2(__VA_ARGS__) -#define vslide1down_vx_i16m1(...) __riscv_vslide1down_vx_i16m1(__VA_ARGS__) -#define vslide1down_vx_i16m2(...) __riscv_vslide1down_vx_i16m2(__VA_ARGS__) -#define vslide1down_vx_i16m4(...) __riscv_vslide1down_vx_i16m4(__VA_ARGS__) -#define vslide1down_vx_i16m8(...) __riscv_vslide1down_vx_i16m8(__VA_ARGS__) -#define vslide1down_vx_i32mf2(...) __riscv_vslide1down_vx_i32mf2(__VA_ARGS__) -#define vslide1down_vx_i32m1(...) __riscv_vslide1down_vx_i32m1(__VA_ARGS__) -#define vslide1down_vx_i32m2(...) __riscv_vslide1down_vx_i32m2(__VA_ARGS__) -#define vslide1down_vx_i32m4(...) __riscv_vslide1down_vx_i32m4(__VA_ARGS__) -#define vslide1down_vx_i32m8(...) __riscv_vslide1down_vx_i32m8(__VA_ARGS__) -#define vslide1down_vx_i64m1(...) __riscv_vslide1down_vx_i64m1(__VA_ARGS__) -#define vslide1down_vx_i64m2(...) __riscv_vslide1down_vx_i64m2(__VA_ARGS__) -#define vslide1down_vx_i64m4(...) __riscv_vslide1down_vx_i64m4(__VA_ARGS__) -#define vslide1down_vx_i64m8(...) __riscv_vslide1down_vx_i64m8(__VA_ARGS__) -#define vslide1up_vx_u8mf8(...) __riscv_vslide1up_vx_u8mf8(__VA_ARGS__) -#define vslide1up_vx_u8mf4(...) __riscv_vslide1up_vx_u8mf4(__VA_ARGS__) -#define vslide1up_vx_u8mf2(...) __riscv_vslide1up_vx_u8mf2(__VA_ARGS__) -#define vslide1up_vx_u8m1(...) __riscv_vslide1up_vx_u8m1(__VA_ARGS__) -#define vslide1up_vx_u8m2(...) __riscv_vslide1up_vx_u8m2(__VA_ARGS__) -#define vslide1up_vx_u8m4(...) __riscv_vslide1up_vx_u8m4(__VA_ARGS__) -#define vslide1up_vx_u8m8(...) __riscv_vslide1up_vx_u8m8(__VA_ARGS__) -#define vslide1up_vx_u16mf4(...) __riscv_vslide1up_vx_u16mf4(__VA_ARGS__) -#define vslide1up_vx_u16mf2(...) __riscv_vslide1up_vx_u16mf2(__VA_ARGS__) -#define vslide1up_vx_u16m1(...) __riscv_vslide1up_vx_u16m1(__VA_ARGS__) -#define vslide1up_vx_u16m2(...) __riscv_vslide1up_vx_u16m2(__VA_ARGS__) -#define vslide1up_vx_u16m4(...) __riscv_vslide1up_vx_u16m4(__VA_ARGS__) -#define vslide1up_vx_u16m8(...) __riscv_vslide1up_vx_u16m8(__VA_ARGS__) -#define vslide1up_vx_u32mf2(...) __riscv_vslide1up_vx_u32mf2(__VA_ARGS__) -#define vslide1up_vx_u32m1(...) __riscv_vslide1up_vx_u32m1(__VA_ARGS__) -#define vslide1up_vx_u32m2(...) __riscv_vslide1up_vx_u32m2(__VA_ARGS__) -#define vslide1up_vx_u32m4(...) __riscv_vslide1up_vx_u32m4(__VA_ARGS__) -#define vslide1up_vx_u32m8(...) __riscv_vslide1up_vx_u32m8(__VA_ARGS__) -#define vslide1up_vx_u64m1(...) __riscv_vslide1up_vx_u64m1(__VA_ARGS__) -#define vslide1up_vx_u64m2(...) __riscv_vslide1up_vx_u64m2(__VA_ARGS__) -#define vslide1up_vx_u64m4(...) __riscv_vslide1up_vx_u64m4(__VA_ARGS__) -#define vslide1up_vx_u64m8(...) __riscv_vslide1up_vx_u64m8(__VA_ARGS__) -#define vslide1down_vx_u8mf8(...) __riscv_vslide1down_vx_u8mf8(__VA_ARGS__) -#define vslide1down_vx_u8mf4(...) __riscv_vslide1down_vx_u8mf4(__VA_ARGS__) -#define vslide1down_vx_u8mf2(...) __riscv_vslide1down_vx_u8mf2(__VA_ARGS__) -#define vslide1down_vx_u8m1(...) __riscv_vslide1down_vx_u8m1(__VA_ARGS__) -#define vslide1down_vx_u8m2(...) __riscv_vslide1down_vx_u8m2(__VA_ARGS__) -#define vslide1down_vx_u8m4(...) __riscv_vslide1down_vx_u8m4(__VA_ARGS__) -#define vslide1down_vx_u8m8(...) __riscv_vslide1down_vx_u8m8(__VA_ARGS__) -#define vslide1down_vx_u16mf4(...) __riscv_vslide1down_vx_u16mf4(__VA_ARGS__) -#define vslide1down_vx_u16mf2(...) __riscv_vslide1down_vx_u16mf2(__VA_ARGS__) -#define vslide1down_vx_u16m1(...) __riscv_vslide1down_vx_u16m1(__VA_ARGS__) -#define vslide1down_vx_u16m2(...) __riscv_vslide1down_vx_u16m2(__VA_ARGS__) -#define vslide1down_vx_u16m4(...) __riscv_vslide1down_vx_u16m4(__VA_ARGS__) -#define vslide1down_vx_u16m8(...) __riscv_vslide1down_vx_u16m8(__VA_ARGS__) -#define vslide1down_vx_u32mf2(...) __riscv_vslide1down_vx_u32mf2(__VA_ARGS__) -#define vslide1down_vx_u32m1(...) __riscv_vslide1down_vx_u32m1(__VA_ARGS__) -#define vslide1down_vx_u32m2(...) __riscv_vslide1down_vx_u32m2(__VA_ARGS__) -#define vslide1down_vx_u32m4(...) __riscv_vslide1down_vx_u32m4(__VA_ARGS__) -#define vslide1down_vx_u32m8(...) __riscv_vslide1down_vx_u32m8(__VA_ARGS__) -#define vslide1down_vx_u64m1(...) __riscv_vslide1down_vx_u64m1(__VA_ARGS__) -#define vslide1down_vx_u64m2(...) __riscv_vslide1down_vx_u64m2(__VA_ARGS__) -#define vslide1down_vx_u64m4(...) __riscv_vslide1down_vx_u64m4(__VA_ARGS__) -#define vslide1down_vx_u64m8(...) __riscv_vslide1down_vx_u64m8(__VA_ARGS__) -// masked functions -#define vfslide1up_vf_f16mf4_m(...) __riscv_vfslide1up_vf_f16mf4_tumu(__VA_ARGS__) -#define vfslide1up_vf_f16mf2_m(...) __riscv_vfslide1up_vf_f16mf2_tumu(__VA_ARGS__) -#define vfslide1up_vf_f16m1_m(...) __riscv_vfslide1up_vf_f16m1_tumu(__VA_ARGS__) -#define vfslide1up_vf_f16m2_m(...) __riscv_vfslide1up_vf_f16m2_tumu(__VA_ARGS__) -#define vfslide1up_vf_f16m4_m(...) __riscv_vfslide1up_vf_f16m4_tumu(__VA_ARGS__) -#define vfslide1up_vf_f16m8_m(...) __riscv_vfslide1up_vf_f16m8_tumu(__VA_ARGS__) -#define vfslide1up_vf_f32mf2_m(...) __riscv_vfslide1up_vf_f32mf2_tumu(__VA_ARGS__) -#define vfslide1up_vf_f32m1_m(...) __riscv_vfslide1up_vf_f32m1_tumu(__VA_ARGS__) -#define vfslide1up_vf_f32m2_m(...) __riscv_vfslide1up_vf_f32m2_tumu(__VA_ARGS__) -#define vfslide1up_vf_f32m4_m(...) __riscv_vfslide1up_vf_f32m4_tumu(__VA_ARGS__) -#define vfslide1up_vf_f32m8_m(...) __riscv_vfslide1up_vf_f32m8_tumu(__VA_ARGS__) -#define vfslide1up_vf_f64m1_m(...) __riscv_vfslide1up_vf_f64m1_tumu(__VA_ARGS__) -#define vfslide1up_vf_f64m2_m(...) __riscv_vfslide1up_vf_f64m2_tumu(__VA_ARGS__) -#define vfslide1up_vf_f64m4_m(...) __riscv_vfslide1up_vf_f64m4_tumu(__VA_ARGS__) -#define vfslide1up_vf_f64m8_m(...) __riscv_vfslide1up_vf_f64m8_tumu(__VA_ARGS__) -#define vfslide1down_vf_f16mf4_m(...) __riscv_vfslide1down_vf_f16mf4_tumu(__VA_ARGS__) -#define vfslide1down_vf_f16mf2_m(...) __riscv_vfslide1down_vf_f16mf2_tumu(__VA_ARGS__) -#define vfslide1down_vf_f16m1_m(...) __riscv_vfslide1down_vf_f16m1_tumu(__VA_ARGS__) -#define vfslide1down_vf_f16m2_m(...) __riscv_vfslide1down_vf_f16m2_tumu(__VA_ARGS__) -#define vfslide1down_vf_f16m4_m(...) __riscv_vfslide1down_vf_f16m4_tumu(__VA_ARGS__) -#define vfslide1down_vf_f16m8_m(...) __riscv_vfslide1down_vf_f16m8_tumu(__VA_ARGS__) -#define vfslide1down_vf_f32mf2_m(...) __riscv_vfslide1down_vf_f32mf2_tumu(__VA_ARGS__) -#define vfslide1down_vf_f32m1_m(...) __riscv_vfslide1down_vf_f32m1_tumu(__VA_ARGS__) -#define vfslide1down_vf_f32m2_m(...) __riscv_vfslide1down_vf_f32m2_tumu(__VA_ARGS__) -#define vfslide1down_vf_f32m4_m(...) __riscv_vfslide1down_vf_f32m4_tumu(__VA_ARGS__) -#define vfslide1down_vf_f32m8_m(...) __riscv_vfslide1down_vf_f32m8_tumu(__VA_ARGS__) -#define vfslide1down_vf_f64m1_m(...) __riscv_vfslide1down_vf_f64m1_tumu(__VA_ARGS__) -#define vfslide1down_vf_f64m2_m(...) __riscv_vfslide1down_vf_f64m2_tumu(__VA_ARGS__) -#define vfslide1down_vf_f64m4_m(...) __riscv_vfslide1down_vf_f64m4_tumu(__VA_ARGS__) -#define vfslide1down_vf_f64m8_m(...) __riscv_vfslide1down_vf_f64m8_tumu(__VA_ARGS__) -#define vslide1up_vx_i8mf8_m(...) __riscv_vslide1up_vx_i8mf8_tumu(__VA_ARGS__) -#define vslide1up_vx_i8mf4_m(...) __riscv_vslide1up_vx_i8mf4_tumu(__VA_ARGS__) -#define vslide1up_vx_i8mf2_m(...) __riscv_vslide1up_vx_i8mf2_tumu(__VA_ARGS__) -#define vslide1up_vx_i8m1_m(...) __riscv_vslide1up_vx_i8m1_tumu(__VA_ARGS__) -#define vslide1up_vx_i8m2_m(...) __riscv_vslide1up_vx_i8m2_tumu(__VA_ARGS__) -#define vslide1up_vx_i8m4_m(...) __riscv_vslide1up_vx_i8m4_tumu(__VA_ARGS__) -#define vslide1up_vx_i8m8_m(...) __riscv_vslide1up_vx_i8m8_tumu(__VA_ARGS__) -#define vslide1up_vx_i16mf4_m(...) __riscv_vslide1up_vx_i16mf4_tumu(__VA_ARGS__) -#define vslide1up_vx_i16mf2_m(...) __riscv_vslide1up_vx_i16mf2_tumu(__VA_ARGS__) -#define vslide1up_vx_i16m1_m(...) __riscv_vslide1up_vx_i16m1_tumu(__VA_ARGS__) -#define vslide1up_vx_i16m2_m(...) __riscv_vslide1up_vx_i16m2_tumu(__VA_ARGS__) -#define vslide1up_vx_i16m4_m(...) __riscv_vslide1up_vx_i16m4_tumu(__VA_ARGS__) -#define vslide1up_vx_i16m8_m(...) __riscv_vslide1up_vx_i16m8_tumu(__VA_ARGS__) -#define vslide1up_vx_i32mf2_m(...) __riscv_vslide1up_vx_i32mf2_tumu(__VA_ARGS__) -#define vslide1up_vx_i32m1_m(...) __riscv_vslide1up_vx_i32m1_tumu(__VA_ARGS__) -#define vslide1up_vx_i32m2_m(...) __riscv_vslide1up_vx_i32m2_tumu(__VA_ARGS__) -#define vslide1up_vx_i32m4_m(...) __riscv_vslide1up_vx_i32m4_tumu(__VA_ARGS__) -#define vslide1up_vx_i32m8_m(...) __riscv_vslide1up_vx_i32m8_tumu(__VA_ARGS__) -#define vslide1up_vx_i64m1_m(...) __riscv_vslide1up_vx_i64m1_tumu(__VA_ARGS__) -#define vslide1up_vx_i64m2_m(...) __riscv_vslide1up_vx_i64m2_tumu(__VA_ARGS__) -#define vslide1up_vx_i64m4_m(...) __riscv_vslide1up_vx_i64m4_tumu(__VA_ARGS__) -#define vslide1up_vx_i64m8_m(...) __riscv_vslide1up_vx_i64m8_tumu(__VA_ARGS__) -#define vslide1down_vx_i8mf8_m(...) __riscv_vslide1down_vx_i8mf8_tumu(__VA_ARGS__) -#define vslide1down_vx_i8mf4_m(...) __riscv_vslide1down_vx_i8mf4_tumu(__VA_ARGS__) -#define vslide1down_vx_i8mf2_m(...) __riscv_vslide1down_vx_i8mf2_tumu(__VA_ARGS__) -#define vslide1down_vx_i8m1_m(...) __riscv_vslide1down_vx_i8m1_tumu(__VA_ARGS__) -#define vslide1down_vx_i8m2_m(...) __riscv_vslide1down_vx_i8m2_tumu(__VA_ARGS__) -#define vslide1down_vx_i8m4_m(...) __riscv_vslide1down_vx_i8m4_tumu(__VA_ARGS__) -#define vslide1down_vx_i8m8_m(...) __riscv_vslide1down_vx_i8m8_tumu(__VA_ARGS__) -#define vslide1down_vx_i16mf4_m(...) __riscv_vslide1down_vx_i16mf4_tumu(__VA_ARGS__) -#define vslide1down_vx_i16mf2_m(...) __riscv_vslide1down_vx_i16mf2_tumu(__VA_ARGS__) -#define vslide1down_vx_i16m1_m(...) __riscv_vslide1down_vx_i16m1_tumu(__VA_ARGS__) -#define vslide1down_vx_i16m2_m(...) __riscv_vslide1down_vx_i16m2_tumu(__VA_ARGS__) -#define vslide1down_vx_i16m4_m(...) __riscv_vslide1down_vx_i16m4_tumu(__VA_ARGS__) -#define vslide1down_vx_i16m8_m(...) __riscv_vslide1down_vx_i16m8_tumu(__VA_ARGS__) -#define vslide1down_vx_i32mf2_m(...) __riscv_vslide1down_vx_i32mf2_tumu(__VA_ARGS__) -#define vslide1down_vx_i32m1_m(...) __riscv_vslide1down_vx_i32m1_tumu(__VA_ARGS__) -#define vslide1down_vx_i32m2_m(...) __riscv_vslide1down_vx_i32m2_tumu(__VA_ARGS__) -#define vslide1down_vx_i32m4_m(...) __riscv_vslide1down_vx_i32m4_tumu(__VA_ARGS__) -#define vslide1down_vx_i32m8_m(...) __riscv_vslide1down_vx_i32m8_tumu(__VA_ARGS__) -#define vslide1down_vx_i64m1_m(...) __riscv_vslide1down_vx_i64m1_tumu(__VA_ARGS__) -#define vslide1down_vx_i64m2_m(...) __riscv_vslide1down_vx_i64m2_tumu(__VA_ARGS__) -#define vslide1down_vx_i64m4_m(...) __riscv_vslide1down_vx_i64m4_tumu(__VA_ARGS__) -#define vslide1down_vx_i64m8_m(...) __riscv_vslide1down_vx_i64m8_tumu(__VA_ARGS__) -#define vslide1up_vx_u8mf8_m(...) __riscv_vslide1up_vx_u8mf8_tumu(__VA_ARGS__) -#define vslide1up_vx_u8mf4_m(...) __riscv_vslide1up_vx_u8mf4_tumu(__VA_ARGS__) -#define vslide1up_vx_u8mf2_m(...) __riscv_vslide1up_vx_u8mf2_tumu(__VA_ARGS__) -#define vslide1up_vx_u8m1_m(...) __riscv_vslide1up_vx_u8m1_tumu(__VA_ARGS__) -#define vslide1up_vx_u8m2_m(...) __riscv_vslide1up_vx_u8m2_tumu(__VA_ARGS__) -#define vslide1up_vx_u8m4_m(...) __riscv_vslide1up_vx_u8m4_tumu(__VA_ARGS__) -#define vslide1up_vx_u8m8_m(...) __riscv_vslide1up_vx_u8m8_tumu(__VA_ARGS__) -#define vslide1up_vx_u16mf4_m(...) __riscv_vslide1up_vx_u16mf4_tumu(__VA_ARGS__) -#define vslide1up_vx_u16mf2_m(...) __riscv_vslide1up_vx_u16mf2_tumu(__VA_ARGS__) -#define vslide1up_vx_u16m1_m(...) __riscv_vslide1up_vx_u16m1_tumu(__VA_ARGS__) -#define vslide1up_vx_u16m2_m(...) __riscv_vslide1up_vx_u16m2_tumu(__VA_ARGS__) -#define vslide1up_vx_u16m4_m(...) __riscv_vslide1up_vx_u16m4_tumu(__VA_ARGS__) -#define vslide1up_vx_u16m8_m(...) __riscv_vslide1up_vx_u16m8_tumu(__VA_ARGS__) -#define vslide1up_vx_u32mf2_m(...) __riscv_vslide1up_vx_u32mf2_tumu(__VA_ARGS__) -#define vslide1up_vx_u32m1_m(...) __riscv_vslide1up_vx_u32m1_tumu(__VA_ARGS__) -#define vslide1up_vx_u32m2_m(...) __riscv_vslide1up_vx_u32m2_tumu(__VA_ARGS__) -#define vslide1up_vx_u32m4_m(...) __riscv_vslide1up_vx_u32m4_tumu(__VA_ARGS__) -#define vslide1up_vx_u32m8_m(...) __riscv_vslide1up_vx_u32m8_tumu(__VA_ARGS__) -#define vslide1up_vx_u64m1_m(...) __riscv_vslide1up_vx_u64m1_tumu(__VA_ARGS__) -#define vslide1up_vx_u64m2_m(...) __riscv_vslide1up_vx_u64m2_tumu(__VA_ARGS__) -#define vslide1up_vx_u64m4_m(...) __riscv_vslide1up_vx_u64m4_tumu(__VA_ARGS__) -#define vslide1up_vx_u64m8_m(...) __riscv_vslide1up_vx_u64m8_tumu(__VA_ARGS__) -#define vslide1down_vx_u8mf8_m(...) __riscv_vslide1down_vx_u8mf8_tumu(__VA_ARGS__) -#define vslide1down_vx_u8mf4_m(...) __riscv_vslide1down_vx_u8mf4_tumu(__VA_ARGS__) -#define vslide1down_vx_u8mf2_m(...) __riscv_vslide1down_vx_u8mf2_tumu(__VA_ARGS__) -#define vslide1down_vx_u8m1_m(...) __riscv_vslide1down_vx_u8m1_tumu(__VA_ARGS__) -#define vslide1down_vx_u8m2_m(...) __riscv_vslide1down_vx_u8m2_tumu(__VA_ARGS__) -#define vslide1down_vx_u8m4_m(...) __riscv_vslide1down_vx_u8m4_tumu(__VA_ARGS__) -#define vslide1down_vx_u8m8_m(...) __riscv_vslide1down_vx_u8m8_tumu(__VA_ARGS__) -#define vslide1down_vx_u16mf4_m(...) __riscv_vslide1down_vx_u16mf4_tumu(__VA_ARGS__) -#define vslide1down_vx_u16mf2_m(...) __riscv_vslide1down_vx_u16mf2_tumu(__VA_ARGS__) -#define vslide1down_vx_u16m1_m(...) __riscv_vslide1down_vx_u16m1_tumu(__VA_ARGS__) -#define vslide1down_vx_u16m2_m(...) __riscv_vslide1down_vx_u16m2_tumu(__VA_ARGS__) -#define vslide1down_vx_u16m4_m(...) __riscv_vslide1down_vx_u16m4_tumu(__VA_ARGS__) -#define vslide1down_vx_u16m8_m(...) __riscv_vslide1down_vx_u16m8_tumu(__VA_ARGS__) -#define vslide1down_vx_u32mf2_m(...) __riscv_vslide1down_vx_u32mf2_tumu(__VA_ARGS__) -#define vslide1down_vx_u32m1_m(...) __riscv_vslide1down_vx_u32m1_tumu(__VA_ARGS__) -#define vslide1down_vx_u32m2_m(...) __riscv_vslide1down_vx_u32m2_tumu(__VA_ARGS__) -#define vslide1down_vx_u32m4_m(...) __riscv_vslide1down_vx_u32m4_tumu(__VA_ARGS__) -#define vslide1down_vx_u32m8_m(...) __riscv_vslide1down_vx_u32m8_tumu(__VA_ARGS__) -#define vslide1down_vx_u64m1_m(...) __riscv_vslide1down_vx_u64m1_tumu(__VA_ARGS__) -#define vslide1down_vx_u64m2_m(...) __riscv_vslide1down_vx_u64m2_tumu(__VA_ARGS__) -#define vslide1down_vx_u64m4_m(...) __riscv_vslide1down_vx_u64m4_tumu(__VA_ARGS__) -#define vslide1down_vx_u64m8_m(...) __riscv_vslide1down_vx_u64m8_tumu(__VA_ARGS__) -#define vrgather_vv_f16mf4(...) __riscv_vrgather_vv_f16mf4(__VA_ARGS__) -#define vrgather_vx_f16mf4(...) __riscv_vrgather_vx_f16mf4(__VA_ARGS__) -#define vrgather_vv_f16mf2(...) __riscv_vrgather_vv_f16mf2(__VA_ARGS__) -#define vrgather_vx_f16mf2(...) __riscv_vrgather_vx_f16mf2(__VA_ARGS__) -#define vrgather_vv_f16m1(...) __riscv_vrgather_vv_f16m1(__VA_ARGS__) -#define vrgather_vx_f16m1(...) __riscv_vrgather_vx_f16m1(__VA_ARGS__) -#define vrgather_vv_f16m2(...) __riscv_vrgather_vv_f16m2(__VA_ARGS__) -#define vrgather_vx_f16m2(...) __riscv_vrgather_vx_f16m2(__VA_ARGS__) -#define vrgather_vv_f16m4(...) __riscv_vrgather_vv_f16m4(__VA_ARGS__) -#define vrgather_vx_f16m4(...) __riscv_vrgather_vx_f16m4(__VA_ARGS__) -#define vrgather_vv_f16m8(...) __riscv_vrgather_vv_f16m8(__VA_ARGS__) -#define vrgather_vx_f16m8(...) __riscv_vrgather_vx_f16m8(__VA_ARGS__) -#define vrgather_vv_f32mf2(...) __riscv_vrgather_vv_f32mf2(__VA_ARGS__) -#define vrgather_vx_f32mf2(...) __riscv_vrgather_vx_f32mf2(__VA_ARGS__) -#define vrgather_vv_f32m1(...) __riscv_vrgather_vv_f32m1(__VA_ARGS__) -#define vrgather_vx_f32m1(...) __riscv_vrgather_vx_f32m1(__VA_ARGS__) -#define vrgather_vv_f32m2(...) __riscv_vrgather_vv_f32m2(__VA_ARGS__) -#define vrgather_vx_f32m2(...) __riscv_vrgather_vx_f32m2(__VA_ARGS__) -#define vrgather_vv_f32m4(...) __riscv_vrgather_vv_f32m4(__VA_ARGS__) -#define vrgather_vx_f32m4(...) __riscv_vrgather_vx_f32m4(__VA_ARGS__) -#define vrgather_vv_f32m8(...) __riscv_vrgather_vv_f32m8(__VA_ARGS__) -#define vrgather_vx_f32m8(...) __riscv_vrgather_vx_f32m8(__VA_ARGS__) -#define vrgather_vv_f64m1(...) __riscv_vrgather_vv_f64m1(__VA_ARGS__) -#define vrgather_vx_f64m1(...) __riscv_vrgather_vx_f64m1(__VA_ARGS__) -#define vrgather_vv_f64m2(...) __riscv_vrgather_vv_f64m2(__VA_ARGS__) -#define vrgather_vx_f64m2(...) __riscv_vrgather_vx_f64m2(__VA_ARGS__) -#define vrgather_vv_f64m4(...) __riscv_vrgather_vv_f64m4(__VA_ARGS__) -#define vrgather_vx_f64m4(...) __riscv_vrgather_vx_f64m4(__VA_ARGS__) -#define vrgather_vv_f64m8(...) __riscv_vrgather_vv_f64m8(__VA_ARGS__) -#define vrgather_vx_f64m8(...) __riscv_vrgather_vx_f64m8(__VA_ARGS__) -#define vrgatherei16_vv_f16mf4(...) __riscv_vrgatherei16_vv_f16mf4(__VA_ARGS__) -#define vrgatherei16_vv_f16mf2(...) __riscv_vrgatherei16_vv_f16mf2(__VA_ARGS__) -#define vrgatherei16_vv_f16m1(...) __riscv_vrgatherei16_vv_f16m1(__VA_ARGS__) -#define vrgatherei16_vv_f16m2(...) __riscv_vrgatherei16_vv_f16m2(__VA_ARGS__) -#define vrgatherei16_vv_f16m4(...) __riscv_vrgatherei16_vv_f16m4(__VA_ARGS__) -#define vrgatherei16_vv_f16m8(...) __riscv_vrgatherei16_vv_f16m8(__VA_ARGS__) -#define vrgatherei16_vv_f32mf2(...) __riscv_vrgatherei16_vv_f32mf2(__VA_ARGS__) -#define vrgatherei16_vv_f32m1(...) __riscv_vrgatherei16_vv_f32m1(__VA_ARGS__) -#define vrgatherei16_vv_f32m2(...) __riscv_vrgatherei16_vv_f32m2(__VA_ARGS__) -#define vrgatherei16_vv_f32m4(...) __riscv_vrgatherei16_vv_f32m4(__VA_ARGS__) -#define vrgatherei16_vv_f32m8(...) __riscv_vrgatherei16_vv_f32m8(__VA_ARGS__) -#define vrgatherei16_vv_f64m1(...) __riscv_vrgatherei16_vv_f64m1(__VA_ARGS__) -#define vrgatherei16_vv_f64m2(...) __riscv_vrgatherei16_vv_f64m2(__VA_ARGS__) -#define vrgatherei16_vv_f64m4(...) __riscv_vrgatherei16_vv_f64m4(__VA_ARGS__) -#define vrgatherei16_vv_f64m8(...) __riscv_vrgatherei16_vv_f64m8(__VA_ARGS__) -#define vrgather_vv_i8mf8(...) __riscv_vrgather_vv_i8mf8(__VA_ARGS__) -#define vrgather_vx_i8mf8(...) __riscv_vrgather_vx_i8mf8(__VA_ARGS__) -#define vrgather_vv_i8mf4(...) __riscv_vrgather_vv_i8mf4(__VA_ARGS__) -#define vrgather_vx_i8mf4(...) __riscv_vrgather_vx_i8mf4(__VA_ARGS__) -#define vrgather_vv_i8mf2(...) __riscv_vrgather_vv_i8mf2(__VA_ARGS__) -#define vrgather_vx_i8mf2(...) __riscv_vrgather_vx_i8mf2(__VA_ARGS__) -#define vrgather_vv_i8m1(...) __riscv_vrgather_vv_i8m1(__VA_ARGS__) -#define vrgather_vx_i8m1(...) __riscv_vrgather_vx_i8m1(__VA_ARGS__) -#define vrgather_vv_i8m2(...) __riscv_vrgather_vv_i8m2(__VA_ARGS__) -#define vrgather_vx_i8m2(...) __riscv_vrgather_vx_i8m2(__VA_ARGS__) -#define vrgather_vv_i8m4(...) __riscv_vrgather_vv_i8m4(__VA_ARGS__) -#define vrgather_vx_i8m4(...) __riscv_vrgather_vx_i8m4(__VA_ARGS__) -#define vrgather_vv_i8m8(...) __riscv_vrgather_vv_i8m8(__VA_ARGS__) -#define vrgather_vx_i8m8(...) __riscv_vrgather_vx_i8m8(__VA_ARGS__) -#define vrgather_vv_i16mf4(...) __riscv_vrgather_vv_i16mf4(__VA_ARGS__) -#define vrgather_vx_i16mf4(...) __riscv_vrgather_vx_i16mf4(__VA_ARGS__) -#define vrgather_vv_i16mf2(...) __riscv_vrgather_vv_i16mf2(__VA_ARGS__) -#define vrgather_vx_i16mf2(...) __riscv_vrgather_vx_i16mf2(__VA_ARGS__) -#define vrgather_vv_i16m1(...) __riscv_vrgather_vv_i16m1(__VA_ARGS__) -#define vrgather_vx_i16m1(...) __riscv_vrgather_vx_i16m1(__VA_ARGS__) -#define vrgather_vv_i16m2(...) __riscv_vrgather_vv_i16m2(__VA_ARGS__) -#define vrgather_vx_i16m2(...) __riscv_vrgather_vx_i16m2(__VA_ARGS__) -#define vrgather_vv_i16m4(...) __riscv_vrgather_vv_i16m4(__VA_ARGS__) -#define vrgather_vx_i16m4(...) __riscv_vrgather_vx_i16m4(__VA_ARGS__) -#define vrgather_vv_i16m8(...) __riscv_vrgather_vv_i16m8(__VA_ARGS__) -#define vrgather_vx_i16m8(...) __riscv_vrgather_vx_i16m8(__VA_ARGS__) -#define vrgather_vv_i32mf2(...) __riscv_vrgather_vv_i32mf2(__VA_ARGS__) -#define vrgather_vx_i32mf2(...) __riscv_vrgather_vx_i32mf2(__VA_ARGS__) -#define vrgather_vv_i32m1(...) __riscv_vrgather_vv_i32m1(__VA_ARGS__) -#define vrgather_vx_i32m1(...) __riscv_vrgather_vx_i32m1(__VA_ARGS__) -#define vrgather_vv_i32m2(...) __riscv_vrgather_vv_i32m2(__VA_ARGS__) -#define vrgather_vx_i32m2(...) __riscv_vrgather_vx_i32m2(__VA_ARGS__) -#define vrgather_vv_i32m4(...) __riscv_vrgather_vv_i32m4(__VA_ARGS__) -#define vrgather_vx_i32m4(...) __riscv_vrgather_vx_i32m4(__VA_ARGS__) -#define vrgather_vv_i32m8(...) __riscv_vrgather_vv_i32m8(__VA_ARGS__) -#define vrgather_vx_i32m8(...) __riscv_vrgather_vx_i32m8(__VA_ARGS__) -#define vrgather_vv_i64m1(...) __riscv_vrgather_vv_i64m1(__VA_ARGS__) -#define vrgather_vx_i64m1(...) __riscv_vrgather_vx_i64m1(__VA_ARGS__) -#define vrgather_vv_i64m2(...) __riscv_vrgather_vv_i64m2(__VA_ARGS__) -#define vrgather_vx_i64m2(...) __riscv_vrgather_vx_i64m2(__VA_ARGS__) -#define vrgather_vv_i64m4(...) __riscv_vrgather_vv_i64m4(__VA_ARGS__) -#define vrgather_vx_i64m4(...) __riscv_vrgather_vx_i64m4(__VA_ARGS__) -#define vrgather_vv_i64m8(...) __riscv_vrgather_vv_i64m8(__VA_ARGS__) -#define vrgather_vx_i64m8(...) __riscv_vrgather_vx_i64m8(__VA_ARGS__) -#define vrgatherei16_vv_i8mf8(...) __riscv_vrgatherei16_vv_i8mf8(__VA_ARGS__) -#define vrgatherei16_vv_i8mf4(...) __riscv_vrgatherei16_vv_i8mf4(__VA_ARGS__) -#define vrgatherei16_vv_i8mf2(...) __riscv_vrgatherei16_vv_i8mf2(__VA_ARGS__) -#define vrgatherei16_vv_i8m1(...) __riscv_vrgatherei16_vv_i8m1(__VA_ARGS__) -#define vrgatherei16_vv_i8m2(...) __riscv_vrgatherei16_vv_i8m2(__VA_ARGS__) -#define vrgatherei16_vv_i8m4(...) __riscv_vrgatherei16_vv_i8m4(__VA_ARGS__) -#define vrgatherei16_vv_i16mf4(...) __riscv_vrgatherei16_vv_i16mf4(__VA_ARGS__) -#define vrgatherei16_vv_i16mf2(...) __riscv_vrgatherei16_vv_i16mf2(__VA_ARGS__) -#define vrgatherei16_vv_i16m1(...) __riscv_vrgatherei16_vv_i16m1(__VA_ARGS__) -#define vrgatherei16_vv_i16m2(...) __riscv_vrgatherei16_vv_i16m2(__VA_ARGS__) -#define vrgatherei16_vv_i16m4(...) __riscv_vrgatherei16_vv_i16m4(__VA_ARGS__) -#define vrgatherei16_vv_i16m8(...) __riscv_vrgatherei16_vv_i16m8(__VA_ARGS__) -#define vrgatherei16_vv_i32mf2(...) __riscv_vrgatherei16_vv_i32mf2(__VA_ARGS__) -#define vrgatherei16_vv_i32m1(...) __riscv_vrgatherei16_vv_i32m1(__VA_ARGS__) -#define vrgatherei16_vv_i32m2(...) __riscv_vrgatherei16_vv_i32m2(__VA_ARGS__) -#define vrgatherei16_vv_i32m4(...) __riscv_vrgatherei16_vv_i32m4(__VA_ARGS__) -#define vrgatherei16_vv_i32m8(...) __riscv_vrgatherei16_vv_i32m8(__VA_ARGS__) -#define vrgatherei16_vv_i64m1(...) __riscv_vrgatherei16_vv_i64m1(__VA_ARGS__) -#define vrgatherei16_vv_i64m2(...) __riscv_vrgatherei16_vv_i64m2(__VA_ARGS__) -#define vrgatherei16_vv_i64m4(...) __riscv_vrgatherei16_vv_i64m4(__VA_ARGS__) -#define vrgatherei16_vv_i64m8(...) __riscv_vrgatherei16_vv_i64m8(__VA_ARGS__) -#define vrgather_vv_u8mf8(...) __riscv_vrgather_vv_u8mf8(__VA_ARGS__) -#define vrgather_vx_u8mf8(...) __riscv_vrgather_vx_u8mf8(__VA_ARGS__) -#define vrgather_vv_u8mf4(...) __riscv_vrgather_vv_u8mf4(__VA_ARGS__) -#define vrgather_vx_u8mf4(...) __riscv_vrgather_vx_u8mf4(__VA_ARGS__) -#define vrgather_vv_u8mf2(...) __riscv_vrgather_vv_u8mf2(__VA_ARGS__) -#define vrgather_vx_u8mf2(...) __riscv_vrgather_vx_u8mf2(__VA_ARGS__) -#define vrgather_vv_u8m1(...) __riscv_vrgather_vv_u8m1(__VA_ARGS__) -#define vrgather_vx_u8m1(...) __riscv_vrgather_vx_u8m1(__VA_ARGS__) -#define vrgather_vv_u8m2(...) __riscv_vrgather_vv_u8m2(__VA_ARGS__) -#define vrgather_vx_u8m2(...) __riscv_vrgather_vx_u8m2(__VA_ARGS__) -#define vrgather_vv_u8m4(...) __riscv_vrgather_vv_u8m4(__VA_ARGS__) -#define vrgather_vx_u8m4(...) __riscv_vrgather_vx_u8m4(__VA_ARGS__) -#define vrgather_vv_u8m8(...) __riscv_vrgather_vv_u8m8(__VA_ARGS__) -#define vrgather_vx_u8m8(...) __riscv_vrgather_vx_u8m8(__VA_ARGS__) -#define vrgather_vv_u16mf4(...) __riscv_vrgather_vv_u16mf4(__VA_ARGS__) -#define vrgather_vx_u16mf4(...) __riscv_vrgather_vx_u16mf4(__VA_ARGS__) -#define vrgather_vv_u16mf2(...) __riscv_vrgather_vv_u16mf2(__VA_ARGS__) -#define vrgather_vx_u16mf2(...) __riscv_vrgather_vx_u16mf2(__VA_ARGS__) -#define vrgather_vv_u16m1(...) __riscv_vrgather_vv_u16m1(__VA_ARGS__) -#define vrgather_vx_u16m1(...) __riscv_vrgather_vx_u16m1(__VA_ARGS__) -#define vrgather_vv_u16m2(...) __riscv_vrgather_vv_u16m2(__VA_ARGS__) -#define vrgather_vx_u16m2(...) __riscv_vrgather_vx_u16m2(__VA_ARGS__) -#define vrgather_vv_u16m4(...) __riscv_vrgather_vv_u16m4(__VA_ARGS__) -#define vrgather_vx_u16m4(...) __riscv_vrgather_vx_u16m4(__VA_ARGS__) -#define vrgather_vv_u16m8(...) __riscv_vrgather_vv_u16m8(__VA_ARGS__) -#define vrgather_vx_u16m8(...) __riscv_vrgather_vx_u16m8(__VA_ARGS__) -#define vrgather_vv_u32mf2(...) __riscv_vrgather_vv_u32mf2(__VA_ARGS__) -#define vrgather_vx_u32mf2(...) __riscv_vrgather_vx_u32mf2(__VA_ARGS__) -#define vrgather_vv_u32m1(...) __riscv_vrgather_vv_u32m1(__VA_ARGS__) -#define vrgather_vx_u32m1(...) __riscv_vrgather_vx_u32m1(__VA_ARGS__) -#define vrgather_vv_u32m2(...) __riscv_vrgather_vv_u32m2(__VA_ARGS__) -#define vrgather_vx_u32m2(...) __riscv_vrgather_vx_u32m2(__VA_ARGS__) -#define vrgather_vv_u32m4(...) __riscv_vrgather_vv_u32m4(__VA_ARGS__) -#define vrgather_vx_u32m4(...) __riscv_vrgather_vx_u32m4(__VA_ARGS__) -#define vrgather_vv_u32m8(...) __riscv_vrgather_vv_u32m8(__VA_ARGS__) -#define vrgather_vx_u32m8(...) __riscv_vrgather_vx_u32m8(__VA_ARGS__) -#define vrgather_vv_u64m1(...) __riscv_vrgather_vv_u64m1(__VA_ARGS__) -#define vrgather_vx_u64m1(...) __riscv_vrgather_vx_u64m1(__VA_ARGS__) -#define vrgather_vv_u64m2(...) __riscv_vrgather_vv_u64m2(__VA_ARGS__) -#define vrgather_vx_u64m2(...) __riscv_vrgather_vx_u64m2(__VA_ARGS__) -#define vrgather_vv_u64m4(...) __riscv_vrgather_vv_u64m4(__VA_ARGS__) -#define vrgather_vx_u64m4(...) __riscv_vrgather_vx_u64m4(__VA_ARGS__) -#define vrgather_vv_u64m8(...) __riscv_vrgather_vv_u64m8(__VA_ARGS__) -#define vrgather_vx_u64m8(...) __riscv_vrgather_vx_u64m8(__VA_ARGS__) -#define vrgatherei16_vv_u8mf8(...) __riscv_vrgatherei16_vv_u8mf8(__VA_ARGS__) -#define vrgatherei16_vv_u8mf4(...) __riscv_vrgatherei16_vv_u8mf4(__VA_ARGS__) -#define vrgatherei16_vv_u8mf2(...) __riscv_vrgatherei16_vv_u8mf2(__VA_ARGS__) -#define vrgatherei16_vv_u8m1(...) __riscv_vrgatherei16_vv_u8m1(__VA_ARGS__) -#define vrgatherei16_vv_u8m2(...) __riscv_vrgatherei16_vv_u8m2(__VA_ARGS__) -#define vrgatherei16_vv_u8m4(...) __riscv_vrgatherei16_vv_u8m4(__VA_ARGS__) -#define vrgatherei16_vv_u16mf4(...) __riscv_vrgatherei16_vv_u16mf4(__VA_ARGS__) -#define vrgatherei16_vv_u16mf2(...) __riscv_vrgatherei16_vv_u16mf2(__VA_ARGS__) -#define vrgatherei16_vv_u16m1(...) __riscv_vrgatherei16_vv_u16m1(__VA_ARGS__) -#define vrgatherei16_vv_u16m2(...) __riscv_vrgatherei16_vv_u16m2(__VA_ARGS__) -#define vrgatherei16_vv_u16m4(...) __riscv_vrgatherei16_vv_u16m4(__VA_ARGS__) -#define vrgatherei16_vv_u16m8(...) __riscv_vrgatherei16_vv_u16m8(__VA_ARGS__) -#define vrgatherei16_vv_u32mf2(...) __riscv_vrgatherei16_vv_u32mf2(__VA_ARGS__) -#define vrgatherei16_vv_u32m1(...) __riscv_vrgatherei16_vv_u32m1(__VA_ARGS__) -#define vrgatherei16_vv_u32m2(...) __riscv_vrgatherei16_vv_u32m2(__VA_ARGS__) -#define vrgatherei16_vv_u32m4(...) __riscv_vrgatherei16_vv_u32m4(__VA_ARGS__) -#define vrgatherei16_vv_u32m8(...) __riscv_vrgatherei16_vv_u32m8(__VA_ARGS__) -#define vrgatherei16_vv_u64m1(...) __riscv_vrgatherei16_vv_u64m1(__VA_ARGS__) -#define vrgatherei16_vv_u64m2(...) __riscv_vrgatherei16_vv_u64m2(__VA_ARGS__) -#define vrgatherei16_vv_u64m4(...) __riscv_vrgatherei16_vv_u64m4(__VA_ARGS__) -#define vrgatherei16_vv_u64m8(...) __riscv_vrgatherei16_vv_u64m8(__VA_ARGS__) -// masked functions -#define vrgather_vv_f16mf4_m(...) __riscv_vrgather_vv_f16mf4_tumu(__VA_ARGS__) -#define vrgather_vx_f16mf4_m(...) __riscv_vrgather_vx_f16mf4_tumu(__VA_ARGS__) -#define vrgather_vv_f16mf2_m(...) __riscv_vrgather_vv_f16mf2_tumu(__VA_ARGS__) -#define vrgather_vx_f16mf2_m(...) __riscv_vrgather_vx_f16mf2_tumu(__VA_ARGS__) -#define vrgather_vv_f16m1_m(...) __riscv_vrgather_vv_f16m1_tumu(__VA_ARGS__) -#define vrgather_vx_f16m1_m(...) __riscv_vrgather_vx_f16m1_tumu(__VA_ARGS__) -#define vrgather_vv_f16m2_m(...) __riscv_vrgather_vv_f16m2_tumu(__VA_ARGS__) -#define vrgather_vx_f16m2_m(...) __riscv_vrgather_vx_f16m2_tumu(__VA_ARGS__) -#define vrgather_vv_f16m4_m(...) __riscv_vrgather_vv_f16m4_tumu(__VA_ARGS__) -#define vrgather_vx_f16m4_m(...) __riscv_vrgather_vx_f16m4_tumu(__VA_ARGS__) -#define vrgather_vv_f16m8_m(...) __riscv_vrgather_vv_f16m8_tumu(__VA_ARGS__) -#define vrgather_vx_f16m8_m(...) __riscv_vrgather_vx_f16m8_tumu(__VA_ARGS__) -#define vrgather_vv_f32mf2_m(...) __riscv_vrgather_vv_f32mf2_tumu(__VA_ARGS__) -#define vrgather_vx_f32mf2_m(...) __riscv_vrgather_vx_f32mf2_tumu(__VA_ARGS__) -#define vrgather_vv_f32m1_m(...) __riscv_vrgather_vv_f32m1_tumu(__VA_ARGS__) -#define vrgather_vx_f32m1_m(...) __riscv_vrgather_vx_f32m1_tumu(__VA_ARGS__) -#define vrgather_vv_f32m2_m(...) __riscv_vrgather_vv_f32m2_tumu(__VA_ARGS__) -#define vrgather_vx_f32m2_m(...) __riscv_vrgather_vx_f32m2_tumu(__VA_ARGS__) -#define vrgather_vv_f32m4_m(...) __riscv_vrgather_vv_f32m4_tumu(__VA_ARGS__) -#define vrgather_vx_f32m4_m(...) __riscv_vrgather_vx_f32m4_tumu(__VA_ARGS__) -#define vrgather_vv_f32m8_m(...) __riscv_vrgather_vv_f32m8_tumu(__VA_ARGS__) -#define vrgather_vx_f32m8_m(...) __riscv_vrgather_vx_f32m8_tumu(__VA_ARGS__) -#define vrgather_vv_f64m1_m(...) __riscv_vrgather_vv_f64m1_tumu(__VA_ARGS__) -#define vrgather_vx_f64m1_m(...) __riscv_vrgather_vx_f64m1_tumu(__VA_ARGS__) -#define vrgather_vv_f64m2_m(...) __riscv_vrgather_vv_f64m2_tumu(__VA_ARGS__) -#define vrgather_vx_f64m2_m(...) __riscv_vrgather_vx_f64m2_tumu(__VA_ARGS__) -#define vrgather_vv_f64m4_m(...) __riscv_vrgather_vv_f64m4_tumu(__VA_ARGS__) -#define vrgather_vx_f64m4_m(...) __riscv_vrgather_vx_f64m4_tumu(__VA_ARGS__) -#define vrgather_vv_f64m8_m(...) __riscv_vrgather_vv_f64m8_tumu(__VA_ARGS__) -#define vrgather_vx_f64m8_m(...) __riscv_vrgather_vx_f64m8_tumu(__VA_ARGS__) -#define vrgatherei16_vv_f16mf4_m(...) __riscv_vrgatherei16_vv_f16mf4_tumu(__VA_ARGS__) -#define vrgatherei16_vv_f16mf2_m(...) __riscv_vrgatherei16_vv_f16mf2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_f16m1_m(...) __riscv_vrgatherei16_vv_f16m1_tumu(__VA_ARGS__) -#define vrgatherei16_vv_f16m2_m(...) __riscv_vrgatherei16_vv_f16m2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_f16m4_m(...) __riscv_vrgatherei16_vv_f16m4_tumu(__VA_ARGS__) -#define vrgatherei16_vv_f16m8_m(...) __riscv_vrgatherei16_vv_f16m8_tumu(__VA_ARGS__) -#define vrgatherei16_vv_f32mf2_m(...) __riscv_vrgatherei16_vv_f32mf2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_f32m1_m(...) __riscv_vrgatherei16_vv_f32m1_tumu(__VA_ARGS__) -#define vrgatherei16_vv_f32m2_m(...) __riscv_vrgatherei16_vv_f32m2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_f32m4_m(...) __riscv_vrgatherei16_vv_f32m4_tumu(__VA_ARGS__) -#define vrgatherei16_vv_f32m8_m(...) __riscv_vrgatherei16_vv_f32m8_tumu(__VA_ARGS__) -#define vrgatherei16_vv_f64m1_m(...) __riscv_vrgatherei16_vv_f64m1_tumu(__VA_ARGS__) -#define vrgatherei16_vv_f64m2_m(...) __riscv_vrgatherei16_vv_f64m2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_f64m4_m(...) __riscv_vrgatherei16_vv_f64m4_tumu(__VA_ARGS__) -#define vrgatherei16_vv_f64m8_m(...) __riscv_vrgatherei16_vv_f64m8_tumu(__VA_ARGS__) -#define vrgather_vv_i8mf8_m(...) __riscv_vrgather_vv_i8mf8_tumu(__VA_ARGS__) -#define vrgather_vx_i8mf8_m(...) __riscv_vrgather_vx_i8mf8_tumu(__VA_ARGS__) -#define vrgather_vv_i8mf4_m(...) __riscv_vrgather_vv_i8mf4_tumu(__VA_ARGS__) -#define vrgather_vx_i8mf4_m(...) __riscv_vrgather_vx_i8mf4_tumu(__VA_ARGS__) -#define vrgather_vv_i8mf2_m(...) __riscv_vrgather_vv_i8mf2_tumu(__VA_ARGS__) -#define vrgather_vx_i8mf2_m(...) __riscv_vrgather_vx_i8mf2_tumu(__VA_ARGS__) -#define vrgather_vv_i8m1_m(...) __riscv_vrgather_vv_i8m1_tumu(__VA_ARGS__) -#define vrgather_vx_i8m1_m(...) __riscv_vrgather_vx_i8m1_tumu(__VA_ARGS__) -#define vrgather_vv_i8m2_m(...) __riscv_vrgather_vv_i8m2_tumu(__VA_ARGS__) -#define vrgather_vx_i8m2_m(...) __riscv_vrgather_vx_i8m2_tumu(__VA_ARGS__) -#define vrgather_vv_i8m4_m(...) __riscv_vrgather_vv_i8m4_tumu(__VA_ARGS__) -#define vrgather_vx_i8m4_m(...) __riscv_vrgather_vx_i8m4_tumu(__VA_ARGS__) -#define vrgather_vv_i8m8_m(...) __riscv_vrgather_vv_i8m8_tumu(__VA_ARGS__) -#define vrgather_vx_i8m8_m(...) __riscv_vrgather_vx_i8m8_tumu(__VA_ARGS__) -#define vrgather_vv_i16mf4_m(...) __riscv_vrgather_vv_i16mf4_tumu(__VA_ARGS__) -#define vrgather_vx_i16mf4_m(...) __riscv_vrgather_vx_i16mf4_tumu(__VA_ARGS__) -#define vrgather_vv_i16mf2_m(...) __riscv_vrgather_vv_i16mf2_tumu(__VA_ARGS__) -#define vrgather_vx_i16mf2_m(...) __riscv_vrgather_vx_i16mf2_tumu(__VA_ARGS__) -#define vrgather_vv_i16m1_m(...) __riscv_vrgather_vv_i16m1_tumu(__VA_ARGS__) -#define vrgather_vx_i16m1_m(...) __riscv_vrgather_vx_i16m1_tumu(__VA_ARGS__) -#define vrgather_vv_i16m2_m(...) __riscv_vrgather_vv_i16m2_tumu(__VA_ARGS__) -#define vrgather_vx_i16m2_m(...) __riscv_vrgather_vx_i16m2_tumu(__VA_ARGS__) -#define vrgather_vv_i16m4_m(...) __riscv_vrgather_vv_i16m4_tumu(__VA_ARGS__) -#define vrgather_vx_i16m4_m(...) __riscv_vrgather_vx_i16m4_tumu(__VA_ARGS__) -#define vrgather_vv_i16m8_m(...) __riscv_vrgather_vv_i16m8_tumu(__VA_ARGS__) -#define vrgather_vx_i16m8_m(...) __riscv_vrgather_vx_i16m8_tumu(__VA_ARGS__) -#define vrgather_vv_i32mf2_m(...) __riscv_vrgather_vv_i32mf2_tumu(__VA_ARGS__) -#define vrgather_vx_i32mf2_m(...) __riscv_vrgather_vx_i32mf2_tumu(__VA_ARGS__) -#define vrgather_vv_i32m1_m(...) __riscv_vrgather_vv_i32m1_tumu(__VA_ARGS__) -#define vrgather_vx_i32m1_m(...) __riscv_vrgather_vx_i32m1_tumu(__VA_ARGS__) -#define vrgather_vv_i32m2_m(...) __riscv_vrgather_vv_i32m2_tumu(__VA_ARGS__) -#define vrgather_vx_i32m2_m(...) __riscv_vrgather_vx_i32m2_tumu(__VA_ARGS__) -#define vrgather_vv_i32m4_m(...) __riscv_vrgather_vv_i32m4_tumu(__VA_ARGS__) -#define vrgather_vx_i32m4_m(...) __riscv_vrgather_vx_i32m4_tumu(__VA_ARGS__) -#define vrgather_vv_i32m8_m(...) __riscv_vrgather_vv_i32m8_tumu(__VA_ARGS__) -#define vrgather_vx_i32m8_m(...) __riscv_vrgather_vx_i32m8_tumu(__VA_ARGS__) -#define vrgather_vv_i64m1_m(...) __riscv_vrgather_vv_i64m1_tumu(__VA_ARGS__) -#define vrgather_vx_i64m1_m(...) __riscv_vrgather_vx_i64m1_tumu(__VA_ARGS__) -#define vrgather_vv_i64m2_m(...) __riscv_vrgather_vv_i64m2_tumu(__VA_ARGS__) -#define vrgather_vx_i64m2_m(...) __riscv_vrgather_vx_i64m2_tumu(__VA_ARGS__) -#define vrgather_vv_i64m4_m(...) __riscv_vrgather_vv_i64m4_tumu(__VA_ARGS__) -#define vrgather_vx_i64m4_m(...) __riscv_vrgather_vx_i64m4_tumu(__VA_ARGS__) -#define vrgather_vv_i64m8_m(...) __riscv_vrgather_vv_i64m8_tumu(__VA_ARGS__) -#define vrgather_vx_i64m8_m(...) __riscv_vrgather_vx_i64m8_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i8mf8_m(...) __riscv_vrgatherei16_vv_i8mf8_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i8mf4_m(...) __riscv_vrgatherei16_vv_i8mf4_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i8mf2_m(...) __riscv_vrgatherei16_vv_i8mf2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i8m1_m(...) __riscv_vrgatherei16_vv_i8m1_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i8m2_m(...) __riscv_vrgatherei16_vv_i8m2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i8m4_m(...) __riscv_vrgatherei16_vv_i8m4_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i16mf4_m(...) __riscv_vrgatherei16_vv_i16mf4_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i16mf2_m(...) __riscv_vrgatherei16_vv_i16mf2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i16m1_m(...) __riscv_vrgatherei16_vv_i16m1_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i16m2_m(...) __riscv_vrgatherei16_vv_i16m2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i16m4_m(...) __riscv_vrgatherei16_vv_i16m4_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i16m8_m(...) __riscv_vrgatherei16_vv_i16m8_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i32mf2_m(...) __riscv_vrgatherei16_vv_i32mf2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i32m1_m(...) __riscv_vrgatherei16_vv_i32m1_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i32m2_m(...) __riscv_vrgatherei16_vv_i32m2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i32m4_m(...) __riscv_vrgatherei16_vv_i32m4_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i32m8_m(...) __riscv_vrgatherei16_vv_i32m8_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i64m1_m(...) __riscv_vrgatherei16_vv_i64m1_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i64m2_m(...) __riscv_vrgatherei16_vv_i64m2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i64m4_m(...) __riscv_vrgatherei16_vv_i64m4_tumu(__VA_ARGS__) -#define vrgatherei16_vv_i64m8_m(...) __riscv_vrgatherei16_vv_i64m8_tumu(__VA_ARGS__) -#define vrgather_vv_u8mf8_m(...) __riscv_vrgather_vv_u8mf8_tumu(__VA_ARGS__) -#define vrgather_vx_u8mf8_m(...) __riscv_vrgather_vx_u8mf8_tumu(__VA_ARGS__) -#define vrgather_vv_u8mf4_m(...) __riscv_vrgather_vv_u8mf4_tumu(__VA_ARGS__) -#define vrgather_vx_u8mf4_m(...) __riscv_vrgather_vx_u8mf4_tumu(__VA_ARGS__) -#define vrgather_vv_u8mf2_m(...) __riscv_vrgather_vv_u8mf2_tumu(__VA_ARGS__) -#define vrgather_vx_u8mf2_m(...) __riscv_vrgather_vx_u8mf2_tumu(__VA_ARGS__) -#define vrgather_vv_u8m1_m(...) __riscv_vrgather_vv_u8m1_tumu(__VA_ARGS__) -#define vrgather_vx_u8m1_m(...) __riscv_vrgather_vx_u8m1_tumu(__VA_ARGS__) -#define vrgather_vv_u8m2_m(...) __riscv_vrgather_vv_u8m2_tumu(__VA_ARGS__) -#define vrgather_vx_u8m2_m(...) __riscv_vrgather_vx_u8m2_tumu(__VA_ARGS__) -#define vrgather_vv_u8m4_m(...) __riscv_vrgather_vv_u8m4_tumu(__VA_ARGS__) -#define vrgather_vx_u8m4_m(...) __riscv_vrgather_vx_u8m4_tumu(__VA_ARGS__) -#define vrgather_vv_u8m8_m(...) __riscv_vrgather_vv_u8m8_tumu(__VA_ARGS__) -#define vrgather_vx_u8m8_m(...) __riscv_vrgather_vx_u8m8_tumu(__VA_ARGS__) -#define vrgather_vv_u16mf4_m(...) __riscv_vrgather_vv_u16mf4_tumu(__VA_ARGS__) -#define vrgather_vx_u16mf4_m(...) __riscv_vrgather_vx_u16mf4_tumu(__VA_ARGS__) -#define vrgather_vv_u16mf2_m(...) __riscv_vrgather_vv_u16mf2_tumu(__VA_ARGS__) -#define vrgather_vx_u16mf2_m(...) __riscv_vrgather_vx_u16mf2_tumu(__VA_ARGS__) -#define vrgather_vv_u16m1_m(...) __riscv_vrgather_vv_u16m1_tumu(__VA_ARGS__) -#define vrgather_vx_u16m1_m(...) __riscv_vrgather_vx_u16m1_tumu(__VA_ARGS__) -#define vrgather_vv_u16m2_m(...) __riscv_vrgather_vv_u16m2_tumu(__VA_ARGS__) -#define vrgather_vx_u16m2_m(...) __riscv_vrgather_vx_u16m2_tumu(__VA_ARGS__) -#define vrgather_vv_u16m4_m(...) __riscv_vrgather_vv_u16m4_tumu(__VA_ARGS__) -#define vrgather_vx_u16m4_m(...) __riscv_vrgather_vx_u16m4_tumu(__VA_ARGS__) -#define vrgather_vv_u16m8_m(...) __riscv_vrgather_vv_u16m8_tumu(__VA_ARGS__) -#define vrgather_vx_u16m8_m(...) __riscv_vrgather_vx_u16m8_tumu(__VA_ARGS__) -#define vrgather_vv_u32mf2_m(...) __riscv_vrgather_vv_u32mf2_tumu(__VA_ARGS__) -#define vrgather_vx_u32mf2_m(...) __riscv_vrgather_vx_u32mf2_tumu(__VA_ARGS__) -#define vrgather_vv_u32m1_m(...) __riscv_vrgather_vv_u32m1_tumu(__VA_ARGS__) -#define vrgather_vx_u32m1_m(...) __riscv_vrgather_vx_u32m1_tumu(__VA_ARGS__) -#define vrgather_vv_u32m2_m(...) __riscv_vrgather_vv_u32m2_tumu(__VA_ARGS__) -#define vrgather_vx_u32m2_m(...) __riscv_vrgather_vx_u32m2_tumu(__VA_ARGS__) -#define vrgather_vv_u32m4_m(...) __riscv_vrgather_vv_u32m4_tumu(__VA_ARGS__) -#define vrgather_vx_u32m4_m(...) __riscv_vrgather_vx_u32m4_tumu(__VA_ARGS__) -#define vrgather_vv_u32m8_m(...) __riscv_vrgather_vv_u32m8_tumu(__VA_ARGS__) -#define vrgather_vx_u32m8_m(...) __riscv_vrgather_vx_u32m8_tumu(__VA_ARGS__) -#define vrgather_vv_u64m1_m(...) __riscv_vrgather_vv_u64m1_tumu(__VA_ARGS__) -#define vrgather_vx_u64m1_m(...) __riscv_vrgather_vx_u64m1_tumu(__VA_ARGS__) -#define vrgather_vv_u64m2_m(...) __riscv_vrgather_vv_u64m2_tumu(__VA_ARGS__) -#define vrgather_vx_u64m2_m(...) __riscv_vrgather_vx_u64m2_tumu(__VA_ARGS__) -#define vrgather_vv_u64m4_m(...) __riscv_vrgather_vv_u64m4_tumu(__VA_ARGS__) -#define vrgather_vx_u64m4_m(...) __riscv_vrgather_vx_u64m4_tumu(__VA_ARGS__) -#define vrgather_vv_u64m8_m(...) __riscv_vrgather_vv_u64m8_tumu(__VA_ARGS__) -#define vrgather_vx_u64m8_m(...) __riscv_vrgather_vx_u64m8_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u8mf8_m(...) __riscv_vrgatherei16_vv_u8mf8_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u8mf4_m(...) __riscv_vrgatherei16_vv_u8mf4_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u8mf2_m(...) __riscv_vrgatherei16_vv_u8mf2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u8m1_m(...) __riscv_vrgatherei16_vv_u8m1_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u8m2_m(...) __riscv_vrgatherei16_vv_u8m2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u8m4_m(...) __riscv_vrgatherei16_vv_u8m4_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u16mf4_m(...) __riscv_vrgatherei16_vv_u16mf4_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u16mf2_m(...) __riscv_vrgatherei16_vv_u16mf2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u16m1_m(...) __riscv_vrgatherei16_vv_u16m1_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u16m2_m(...) __riscv_vrgatherei16_vv_u16m2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u16m4_m(...) __riscv_vrgatherei16_vv_u16m4_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u16m8_m(...) __riscv_vrgatherei16_vv_u16m8_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u32mf2_m(...) __riscv_vrgatherei16_vv_u32mf2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u32m1_m(...) __riscv_vrgatherei16_vv_u32m1_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u32m2_m(...) __riscv_vrgatherei16_vv_u32m2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u32m4_m(...) __riscv_vrgatherei16_vv_u32m4_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u32m8_m(...) __riscv_vrgatherei16_vv_u32m8_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u64m1_m(...) __riscv_vrgatherei16_vv_u64m1_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u64m2_m(...) __riscv_vrgatherei16_vv_u64m2_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u64m4_m(...) __riscv_vrgatherei16_vv_u64m4_tumu(__VA_ARGS__) -#define vrgatherei16_vv_u64m8_m(...) __riscv_vrgatherei16_vv_u64m8_tumu(__VA_ARGS__) -#define vcompress_vm_f16mf4(mask, dest, src, vl) __riscv_vcompress_vm_f16mf4_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_f16mf2(mask, dest, src, vl) __riscv_vcompress_vm_f16mf2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_f16m1(mask, dest, src, vl) __riscv_vcompress_vm_f16m1_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_f16m2(mask, dest, src, vl) __riscv_vcompress_vm_f16m2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_f16m4(mask, dest, src, vl) __riscv_vcompress_vm_f16m4_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_f16m8(mask, dest, src, vl) __riscv_vcompress_vm_f16m8_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_f32mf2(mask, dest, src, vl) __riscv_vcompress_vm_f32mf2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_f32m1(mask, dest, src, vl) __riscv_vcompress_vm_f32m1_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_f32m2(mask, dest, src, vl) __riscv_vcompress_vm_f32m2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_f32m4(mask, dest, src, vl) __riscv_vcompress_vm_f32m4_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_f32m8(mask, dest, src, vl) __riscv_vcompress_vm_f32m8_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_f64m1(mask, dest, src, vl) __riscv_vcompress_vm_f64m1_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_f64m2(mask, dest, src, vl) __riscv_vcompress_vm_f64m2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_f64m4(mask, dest, src, vl) __riscv_vcompress_vm_f64m4_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_f64m8(mask, dest, src, vl) __riscv_vcompress_vm_f64m8_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i8mf8(mask, dest, src, vl) __riscv_vcompress_vm_i8mf8_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i8mf4(mask, dest, src, vl) __riscv_vcompress_vm_i8mf4_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i8mf2(mask, dest, src, vl) __riscv_vcompress_vm_i8mf2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i8m1(mask, dest, src, vl) __riscv_vcompress_vm_i8m1_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i8m2(mask, dest, src, vl) __riscv_vcompress_vm_i8m2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i8m4(mask, dest, src, vl) __riscv_vcompress_vm_i8m4_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i8m8(mask, dest, src, vl) __riscv_vcompress_vm_i8m8_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i16mf4(mask, dest, src, vl) __riscv_vcompress_vm_i16mf4_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i16mf2(mask, dest, src, vl) __riscv_vcompress_vm_i16mf2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i16m1(mask, dest, src, vl) __riscv_vcompress_vm_i16m1_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i16m2(mask, dest, src, vl) __riscv_vcompress_vm_i16m2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i16m4(mask, dest, src, vl) __riscv_vcompress_vm_i16m4_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i16m8(mask, dest, src, vl) __riscv_vcompress_vm_i16m8_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i32mf2(mask, dest, src, vl) __riscv_vcompress_vm_i32mf2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i32m1(mask, dest, src, vl) __riscv_vcompress_vm_i32m1_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i32m2(mask, dest, src, vl) __riscv_vcompress_vm_i32m2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i32m4(mask, dest, src, vl) __riscv_vcompress_vm_i32m4_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i32m8(mask, dest, src, vl) __riscv_vcompress_vm_i32m8_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i64m1(mask, dest, src, vl) __riscv_vcompress_vm_i64m1_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i64m2(mask, dest, src, vl) __riscv_vcompress_vm_i64m2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i64m4(mask, dest, src, vl) __riscv_vcompress_vm_i64m4_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_i64m8(mask, dest, src, vl) __riscv_vcompress_vm_i64m8_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u8mf8(mask, dest, src, vl) __riscv_vcompress_vm_u8mf8_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u8mf4(mask, dest, src, vl) __riscv_vcompress_vm_u8mf4_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u8mf2(mask, dest, src, vl) __riscv_vcompress_vm_u8mf2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u8m1(mask, dest, src, vl) __riscv_vcompress_vm_u8m1_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u8m2(mask, dest, src, vl) __riscv_vcompress_vm_u8m2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u8m4(mask, dest, src, vl) __riscv_vcompress_vm_u8m4_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u8m8(mask, dest, src, vl) __riscv_vcompress_vm_u8m8_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u16mf4(mask, dest, src, vl) __riscv_vcompress_vm_u16mf4_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u16mf2(mask, dest, src, vl) __riscv_vcompress_vm_u16mf2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u16m1(mask, dest, src, vl) __riscv_vcompress_vm_u16m1_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u16m2(mask, dest, src, vl) __riscv_vcompress_vm_u16m2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u16m4(mask, dest, src, vl) __riscv_vcompress_vm_u16m4_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u16m8(mask, dest, src, vl) __riscv_vcompress_vm_u16m8_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u32mf2(mask, dest, src, vl) __riscv_vcompress_vm_u32mf2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u32m1(mask, dest, src, vl) __riscv_vcompress_vm_u32m1_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u32m2(mask, dest, src, vl) __riscv_vcompress_vm_u32m2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u32m4(mask, dest, src, vl) __riscv_vcompress_vm_u32m4_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u32m8(mask, dest, src, vl) __riscv_vcompress_vm_u32m8_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u64m1(mask, dest, src, vl) __riscv_vcompress_vm_u64m1_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u64m2(mask, dest, src, vl) __riscv_vcompress_vm_u64m2_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u64m4(mask, dest, src, vl) __riscv_vcompress_vm_u64m4_tu((dest), (src), (mask), (vl)) -#define vcompress_vm_u64m8(mask, dest, src, vl) __riscv_vcompress_vm_u64m8_tu((dest), (src), (mask), (vl)) -// Reinterpret between different type under the same SEW/LMUL -#define vreinterpret_v_i8mf8_u8mf8(...) __riscv_vreinterpret_v_i8mf8_u8mf8(__VA_ARGS__) -#define vreinterpret_v_i8mf4_u8mf4(...) __riscv_vreinterpret_v_i8mf4_u8mf4(__VA_ARGS__) -#define vreinterpret_v_i8mf2_u8mf2(...) __riscv_vreinterpret_v_i8mf2_u8mf2(__VA_ARGS__) -#define vreinterpret_v_i8m1_u8m1(...) __riscv_vreinterpret_v_i8m1_u8m1(__VA_ARGS__) -#define vreinterpret_v_i8m2_u8m2(...) __riscv_vreinterpret_v_i8m2_u8m2(__VA_ARGS__) -#define vreinterpret_v_i8m4_u8m4(...) __riscv_vreinterpret_v_i8m4_u8m4(__VA_ARGS__) -#define vreinterpret_v_i8m8_u8m8(...) __riscv_vreinterpret_v_i8m8_u8m8(__VA_ARGS__) -#define vreinterpret_v_u8mf8_i8mf8(...) __riscv_vreinterpret_v_u8mf8_i8mf8(__VA_ARGS__) -#define vreinterpret_v_u8mf4_i8mf4(...) __riscv_vreinterpret_v_u8mf4_i8mf4(__VA_ARGS__) -#define vreinterpret_v_u8mf2_i8mf2(...) __riscv_vreinterpret_v_u8mf2_i8mf2(__VA_ARGS__) -#define vreinterpret_v_u8m1_i8m1(...) __riscv_vreinterpret_v_u8m1_i8m1(__VA_ARGS__) -#define vreinterpret_v_u8m2_i8m2(...) __riscv_vreinterpret_v_u8m2_i8m2(__VA_ARGS__) -#define vreinterpret_v_u8m4_i8m4(...) __riscv_vreinterpret_v_u8m4_i8m4(__VA_ARGS__) -#define vreinterpret_v_u8m8_i8m8(...) __riscv_vreinterpret_v_u8m8_i8m8(__VA_ARGS__) -#define vreinterpret_v_i16mf4_f16mf4(...) __riscv_vreinterpret_v_i16mf4_f16mf4(__VA_ARGS__) -#define vreinterpret_v_i16mf2_f16mf2(...) __riscv_vreinterpret_v_i16mf2_f16mf2(__VA_ARGS__) -#define vreinterpret_v_i16m1_f16m1(...) __riscv_vreinterpret_v_i16m1_f16m1(__VA_ARGS__) -#define vreinterpret_v_i16m2_f16m2(...) __riscv_vreinterpret_v_i16m2_f16m2(__VA_ARGS__) -#define vreinterpret_v_i16m4_f16m4(...) __riscv_vreinterpret_v_i16m4_f16m4(__VA_ARGS__) -#define vreinterpret_v_i16m8_f16m8(...) __riscv_vreinterpret_v_i16m8_f16m8(__VA_ARGS__) -#define vreinterpret_v_u16mf4_f16mf4(...) __riscv_vreinterpret_v_u16mf4_f16mf4(__VA_ARGS__) -#define vreinterpret_v_u16mf2_f16mf2(...) __riscv_vreinterpret_v_u16mf2_f16mf2(__VA_ARGS__) -#define vreinterpret_v_u16m1_f16m1(...) __riscv_vreinterpret_v_u16m1_f16m1(__VA_ARGS__) -#define vreinterpret_v_u16m2_f16m2(...) __riscv_vreinterpret_v_u16m2_f16m2(__VA_ARGS__) -#define vreinterpret_v_u16m4_f16m4(...) __riscv_vreinterpret_v_u16m4_f16m4(__VA_ARGS__) -#define vreinterpret_v_u16m8_f16m8(...) __riscv_vreinterpret_v_u16m8_f16m8(__VA_ARGS__) -#define vreinterpret_v_i16mf4_u16mf4(...) __riscv_vreinterpret_v_i16mf4_u16mf4(__VA_ARGS__) -#define vreinterpret_v_i16mf2_u16mf2(...) __riscv_vreinterpret_v_i16mf2_u16mf2(__VA_ARGS__) -#define vreinterpret_v_i16m1_u16m1(...) __riscv_vreinterpret_v_i16m1_u16m1(__VA_ARGS__) -#define vreinterpret_v_i16m2_u16m2(...) __riscv_vreinterpret_v_i16m2_u16m2(__VA_ARGS__) -#define vreinterpret_v_i16m4_u16m4(...) __riscv_vreinterpret_v_i16m4_u16m4(__VA_ARGS__) -#define vreinterpret_v_i16m8_u16m8(...) __riscv_vreinterpret_v_i16m8_u16m8(__VA_ARGS__) -#define vreinterpret_v_u16mf4_i16mf4(...) __riscv_vreinterpret_v_u16mf4_i16mf4(__VA_ARGS__) -#define vreinterpret_v_u16mf2_i16mf2(...) __riscv_vreinterpret_v_u16mf2_i16mf2(__VA_ARGS__) -#define vreinterpret_v_u16m1_i16m1(...) __riscv_vreinterpret_v_u16m1_i16m1(__VA_ARGS__) -#define vreinterpret_v_u16m2_i16m2(...) __riscv_vreinterpret_v_u16m2_i16m2(__VA_ARGS__) -#define vreinterpret_v_u16m4_i16m4(...) __riscv_vreinterpret_v_u16m4_i16m4(__VA_ARGS__) -#define vreinterpret_v_u16m8_i16m8(...) __riscv_vreinterpret_v_u16m8_i16m8(__VA_ARGS__) -#define vreinterpret_v_f16mf4_i16mf4(...) __riscv_vreinterpret_v_f16mf4_i16mf4(__VA_ARGS__) -#define vreinterpret_v_f16mf2_i16mf2(...) __riscv_vreinterpret_v_f16mf2_i16mf2(__VA_ARGS__) -#define vreinterpret_v_f16m1_i16m1(...) __riscv_vreinterpret_v_f16m1_i16m1(__VA_ARGS__) -#define vreinterpret_v_f16m2_i16m2(...) __riscv_vreinterpret_v_f16m2_i16m2(__VA_ARGS__) -#define vreinterpret_v_f16m4_i16m4(...) __riscv_vreinterpret_v_f16m4_i16m4(__VA_ARGS__) -#define vreinterpret_v_f16m8_i16m8(...) __riscv_vreinterpret_v_f16m8_i16m8(__VA_ARGS__) -#define vreinterpret_v_f16mf4_u16mf4(...) __riscv_vreinterpret_v_f16mf4_u16mf4(__VA_ARGS__) -#define vreinterpret_v_f16mf2_u16mf2(...) __riscv_vreinterpret_v_f16mf2_u16mf2(__VA_ARGS__) -#define vreinterpret_v_f16m1_u16m1(...) __riscv_vreinterpret_v_f16m1_u16m1(__VA_ARGS__) -#define vreinterpret_v_f16m2_u16m2(...) __riscv_vreinterpret_v_f16m2_u16m2(__VA_ARGS__) -#define vreinterpret_v_f16m4_u16m4(...) __riscv_vreinterpret_v_f16m4_u16m4(__VA_ARGS__) -#define vreinterpret_v_f16m8_u16m8(...) __riscv_vreinterpret_v_f16m8_u16m8(__VA_ARGS__) -#define vreinterpret_v_i32mf2_f32mf2(...) __riscv_vreinterpret_v_i32mf2_f32mf2(__VA_ARGS__) -#define vreinterpret_v_i32m1_f32m1(...) __riscv_vreinterpret_v_i32m1_f32m1(__VA_ARGS__) -#define vreinterpret_v_i32m2_f32m2(...) __riscv_vreinterpret_v_i32m2_f32m2(__VA_ARGS__) -#define vreinterpret_v_i32m4_f32m4(...) __riscv_vreinterpret_v_i32m4_f32m4(__VA_ARGS__) -#define vreinterpret_v_i32m8_f32m8(...) __riscv_vreinterpret_v_i32m8_f32m8(__VA_ARGS__) -#define vreinterpret_v_u32mf2_f32mf2(...) __riscv_vreinterpret_v_u32mf2_f32mf2(__VA_ARGS__) -#define vreinterpret_v_u32m1_f32m1(...) __riscv_vreinterpret_v_u32m1_f32m1(__VA_ARGS__) -#define vreinterpret_v_u32m2_f32m2(...) __riscv_vreinterpret_v_u32m2_f32m2(__VA_ARGS__) -#define vreinterpret_v_u32m4_f32m4(...) __riscv_vreinterpret_v_u32m4_f32m4(__VA_ARGS__) -#define vreinterpret_v_u32m8_f32m8(...) __riscv_vreinterpret_v_u32m8_f32m8(__VA_ARGS__) -#define vreinterpret_v_i32mf2_u32mf2(...) __riscv_vreinterpret_v_i32mf2_u32mf2(__VA_ARGS__) -#define vreinterpret_v_i32m1_u32m1(...) __riscv_vreinterpret_v_i32m1_u32m1(__VA_ARGS__) -#define vreinterpret_v_i32m2_u32m2(...) __riscv_vreinterpret_v_i32m2_u32m2(__VA_ARGS__) -#define vreinterpret_v_i32m4_u32m4(...) __riscv_vreinterpret_v_i32m4_u32m4(__VA_ARGS__) -#define vreinterpret_v_i32m8_u32m8(...) __riscv_vreinterpret_v_i32m8_u32m8(__VA_ARGS__) -#define vreinterpret_v_u32mf2_i32mf2(...) __riscv_vreinterpret_v_u32mf2_i32mf2(__VA_ARGS__) -#define vreinterpret_v_u32m1_i32m1(...) __riscv_vreinterpret_v_u32m1_i32m1(__VA_ARGS__) -#define vreinterpret_v_u32m2_i32m2(...) __riscv_vreinterpret_v_u32m2_i32m2(__VA_ARGS__) -#define vreinterpret_v_u32m4_i32m4(...) __riscv_vreinterpret_v_u32m4_i32m4(__VA_ARGS__) -#define vreinterpret_v_u32m8_i32m8(...) __riscv_vreinterpret_v_u32m8_i32m8(__VA_ARGS__) -#define vreinterpret_v_f32mf2_i32mf2(...) __riscv_vreinterpret_v_f32mf2_i32mf2(__VA_ARGS__) -#define vreinterpret_v_f32m1_i32m1(...) __riscv_vreinterpret_v_f32m1_i32m1(__VA_ARGS__) -#define vreinterpret_v_f32m2_i32m2(...) __riscv_vreinterpret_v_f32m2_i32m2(__VA_ARGS__) -#define vreinterpret_v_f32m4_i32m4(...) __riscv_vreinterpret_v_f32m4_i32m4(__VA_ARGS__) -#define vreinterpret_v_f32m8_i32m8(...) __riscv_vreinterpret_v_f32m8_i32m8(__VA_ARGS__) -#define vreinterpret_v_f32mf2_u32mf2(...) __riscv_vreinterpret_v_f32mf2_u32mf2(__VA_ARGS__) -#define vreinterpret_v_f32m1_u32m1(...) __riscv_vreinterpret_v_f32m1_u32m1(__VA_ARGS__) -#define vreinterpret_v_f32m2_u32m2(...) __riscv_vreinterpret_v_f32m2_u32m2(__VA_ARGS__) -#define vreinterpret_v_f32m4_u32m4(...) __riscv_vreinterpret_v_f32m4_u32m4(__VA_ARGS__) -#define vreinterpret_v_f32m8_u32m8(...) __riscv_vreinterpret_v_f32m8_u32m8(__VA_ARGS__) -#define vreinterpret_v_i64m1_f64m1(...) __riscv_vreinterpret_v_i64m1_f64m1(__VA_ARGS__) -#define vreinterpret_v_i64m2_f64m2(...) __riscv_vreinterpret_v_i64m2_f64m2(__VA_ARGS__) -#define vreinterpret_v_i64m4_f64m4(...) __riscv_vreinterpret_v_i64m4_f64m4(__VA_ARGS__) -#define vreinterpret_v_i64m8_f64m8(...) __riscv_vreinterpret_v_i64m8_f64m8(__VA_ARGS__) -#define vreinterpret_v_u64m1_f64m1(...) __riscv_vreinterpret_v_u64m1_f64m1(__VA_ARGS__) -#define vreinterpret_v_u64m2_f64m2(...) __riscv_vreinterpret_v_u64m2_f64m2(__VA_ARGS__) -#define vreinterpret_v_u64m4_f64m4(...) __riscv_vreinterpret_v_u64m4_f64m4(__VA_ARGS__) -#define vreinterpret_v_u64m8_f64m8(...) __riscv_vreinterpret_v_u64m8_f64m8(__VA_ARGS__) -#define vreinterpret_v_i64m1_u64m1(...) __riscv_vreinterpret_v_i64m1_u64m1(__VA_ARGS__) -#define vreinterpret_v_i64m2_u64m2(...) __riscv_vreinterpret_v_i64m2_u64m2(__VA_ARGS__) -#define vreinterpret_v_i64m4_u64m4(...) __riscv_vreinterpret_v_i64m4_u64m4(__VA_ARGS__) -#define vreinterpret_v_i64m8_u64m8(...) __riscv_vreinterpret_v_i64m8_u64m8(__VA_ARGS__) -#define vreinterpret_v_u64m1_i64m1(...) __riscv_vreinterpret_v_u64m1_i64m1(__VA_ARGS__) -#define vreinterpret_v_u64m2_i64m2(...) __riscv_vreinterpret_v_u64m2_i64m2(__VA_ARGS__) -#define vreinterpret_v_u64m4_i64m4(...) __riscv_vreinterpret_v_u64m4_i64m4(__VA_ARGS__) -#define vreinterpret_v_u64m8_i64m8(...) __riscv_vreinterpret_v_u64m8_i64m8(__VA_ARGS__) -#define vreinterpret_v_f64m1_i64m1(...) __riscv_vreinterpret_v_f64m1_i64m1(__VA_ARGS__) -#define vreinterpret_v_f64m2_i64m2(...) __riscv_vreinterpret_v_f64m2_i64m2(__VA_ARGS__) -#define vreinterpret_v_f64m4_i64m4(...) __riscv_vreinterpret_v_f64m4_i64m4(__VA_ARGS__) -#define vreinterpret_v_f64m8_i64m8(...) __riscv_vreinterpret_v_f64m8_i64m8(__VA_ARGS__) -#define vreinterpret_v_f64m1_u64m1(...) __riscv_vreinterpret_v_f64m1_u64m1(__VA_ARGS__) -#define vreinterpret_v_f64m2_u64m2(...) __riscv_vreinterpret_v_f64m2_u64m2(__VA_ARGS__) -#define vreinterpret_v_f64m4_u64m4(...) __riscv_vreinterpret_v_f64m4_u64m4(__VA_ARGS__) -#define vreinterpret_v_f64m8_u64m8(...) __riscv_vreinterpret_v_f64m8_u64m8(__VA_ARGS__) -// Reinterpret between different SEW under the same LMUL -#define vreinterpret_v_i8mf4_i16mf4(...) __riscv_vreinterpret_v_i8mf4_i16mf4(__VA_ARGS__) -#define vreinterpret_v_i8mf2_i16mf2(...) __riscv_vreinterpret_v_i8mf2_i16mf2(__VA_ARGS__) -#define vreinterpret_v_i8m1_i16m1(...) __riscv_vreinterpret_v_i8m1_i16m1(__VA_ARGS__) -#define vreinterpret_v_i8m2_i16m2(...) __riscv_vreinterpret_v_i8m2_i16m2(__VA_ARGS__) -#define vreinterpret_v_i8m4_i16m4(...) __riscv_vreinterpret_v_i8m4_i16m4(__VA_ARGS__) -#define vreinterpret_v_i8m8_i16m8(...) __riscv_vreinterpret_v_i8m8_i16m8(__VA_ARGS__) -#define vreinterpret_v_u8mf4_u16mf4(...) __riscv_vreinterpret_v_u8mf4_u16mf4(__VA_ARGS__) -#define vreinterpret_v_u8mf2_u16mf2(...) __riscv_vreinterpret_v_u8mf2_u16mf2(__VA_ARGS__) -#define vreinterpret_v_u8m1_u16m1(...) __riscv_vreinterpret_v_u8m1_u16m1(__VA_ARGS__) -#define vreinterpret_v_u8m2_u16m2(...) __riscv_vreinterpret_v_u8m2_u16m2(__VA_ARGS__) -#define vreinterpret_v_u8m4_u16m4(...) __riscv_vreinterpret_v_u8m4_u16m4(__VA_ARGS__) -#define vreinterpret_v_u8m8_u16m8(...) __riscv_vreinterpret_v_u8m8_u16m8(__VA_ARGS__) -#define vreinterpret_v_i8mf2_i32mf2(...) __riscv_vreinterpret_v_i8mf2_i32mf2(__VA_ARGS__) -#define vreinterpret_v_i8m1_i32m1(...) __riscv_vreinterpret_v_i8m1_i32m1(__VA_ARGS__) -#define vreinterpret_v_i8m2_i32m2(...) __riscv_vreinterpret_v_i8m2_i32m2(__VA_ARGS__) -#define vreinterpret_v_i8m4_i32m4(...) __riscv_vreinterpret_v_i8m4_i32m4(__VA_ARGS__) -#define vreinterpret_v_i8m8_i32m8(...) __riscv_vreinterpret_v_i8m8_i32m8(__VA_ARGS__) -#define vreinterpret_v_u8mf2_u32mf2(...) __riscv_vreinterpret_v_u8mf2_u32mf2(__VA_ARGS__) -#define vreinterpret_v_u8m1_u32m1(...) __riscv_vreinterpret_v_u8m1_u32m1(__VA_ARGS__) -#define vreinterpret_v_u8m2_u32m2(...) __riscv_vreinterpret_v_u8m2_u32m2(__VA_ARGS__) -#define vreinterpret_v_u8m4_u32m4(...) __riscv_vreinterpret_v_u8m4_u32m4(__VA_ARGS__) -#define vreinterpret_v_u8m8_u32m8(...) __riscv_vreinterpret_v_u8m8_u32m8(__VA_ARGS__) -#define vreinterpret_v_i8m1_i64m1(...) __riscv_vreinterpret_v_i8m1_i64m1(__VA_ARGS__) -#define vreinterpret_v_i8m2_i64m2(...) __riscv_vreinterpret_v_i8m2_i64m2(__VA_ARGS__) -#define vreinterpret_v_i8m4_i64m4(...) __riscv_vreinterpret_v_i8m4_i64m4(__VA_ARGS__) -#define vreinterpret_v_i8m8_i64m8(...) __riscv_vreinterpret_v_i8m8_i64m8(__VA_ARGS__) -#define vreinterpret_v_u8m1_u64m1(...) __riscv_vreinterpret_v_u8m1_u64m1(__VA_ARGS__) -#define vreinterpret_v_u8m2_u64m2(...) __riscv_vreinterpret_v_u8m2_u64m2(__VA_ARGS__) -#define vreinterpret_v_u8m4_u64m4(...) __riscv_vreinterpret_v_u8m4_u64m4(__VA_ARGS__) -#define vreinterpret_v_u8m8_u64m8(...) __riscv_vreinterpret_v_u8m8_u64m8(__VA_ARGS__) -#define vreinterpret_v_i16mf4_i8mf4(...) __riscv_vreinterpret_v_i16mf4_i8mf4(__VA_ARGS__) -#define vreinterpret_v_i16mf2_i8mf2(...) __riscv_vreinterpret_v_i16mf2_i8mf2(__VA_ARGS__) -#define vreinterpret_v_i16m1_i8m1(...) __riscv_vreinterpret_v_i16m1_i8m1(__VA_ARGS__) -#define vreinterpret_v_i16m2_i8m2(...) __riscv_vreinterpret_v_i16m2_i8m2(__VA_ARGS__) -#define vreinterpret_v_i16m4_i8m4(...) __riscv_vreinterpret_v_i16m4_i8m4(__VA_ARGS__) -#define vreinterpret_v_i16m8_i8m8(...) __riscv_vreinterpret_v_i16m8_i8m8(__VA_ARGS__) -#define vreinterpret_v_u16mf4_u8mf4(...) __riscv_vreinterpret_v_u16mf4_u8mf4(__VA_ARGS__) -#define vreinterpret_v_u16mf2_u8mf2(...) __riscv_vreinterpret_v_u16mf2_u8mf2(__VA_ARGS__) -#define vreinterpret_v_u16m1_u8m1(...) __riscv_vreinterpret_v_u16m1_u8m1(__VA_ARGS__) -#define vreinterpret_v_u16m2_u8m2(...) __riscv_vreinterpret_v_u16m2_u8m2(__VA_ARGS__) -#define vreinterpret_v_u16m4_u8m4(...) __riscv_vreinterpret_v_u16m4_u8m4(__VA_ARGS__) -#define vreinterpret_v_u16m8_u8m8(...) __riscv_vreinterpret_v_u16m8_u8m8(__VA_ARGS__) -#define vreinterpret_v_i16mf2_i32mf2(...) __riscv_vreinterpret_v_i16mf2_i32mf2(__VA_ARGS__) -#define vreinterpret_v_i16m1_i32m1(...) __riscv_vreinterpret_v_i16m1_i32m1(__VA_ARGS__) -#define vreinterpret_v_i16m2_i32m2(...) __riscv_vreinterpret_v_i16m2_i32m2(__VA_ARGS__) -#define vreinterpret_v_i16m4_i32m4(...) __riscv_vreinterpret_v_i16m4_i32m4(__VA_ARGS__) -#define vreinterpret_v_i16m8_i32m8(...) __riscv_vreinterpret_v_i16m8_i32m8(__VA_ARGS__) -#define vreinterpret_v_u16mf2_u32mf2(...) __riscv_vreinterpret_v_u16mf2_u32mf2(__VA_ARGS__) -#define vreinterpret_v_u16m1_u32m1(...) __riscv_vreinterpret_v_u16m1_u32m1(__VA_ARGS__) -#define vreinterpret_v_u16m2_u32m2(...) __riscv_vreinterpret_v_u16m2_u32m2(__VA_ARGS__) -#define vreinterpret_v_u16m4_u32m4(...) __riscv_vreinterpret_v_u16m4_u32m4(__VA_ARGS__) -#define vreinterpret_v_u16m8_u32m8(...) __riscv_vreinterpret_v_u16m8_u32m8(__VA_ARGS__) -#define vreinterpret_v_i16m1_i64m1(...) __riscv_vreinterpret_v_i16m1_i64m1(__VA_ARGS__) -#define vreinterpret_v_i16m2_i64m2(...) __riscv_vreinterpret_v_i16m2_i64m2(__VA_ARGS__) -#define vreinterpret_v_i16m4_i64m4(...) __riscv_vreinterpret_v_i16m4_i64m4(__VA_ARGS__) -#define vreinterpret_v_i16m8_i64m8(...) __riscv_vreinterpret_v_i16m8_i64m8(__VA_ARGS__) -#define vreinterpret_v_u16m1_u64m1(...) __riscv_vreinterpret_v_u16m1_u64m1(__VA_ARGS__) -#define vreinterpret_v_u16m2_u64m2(...) __riscv_vreinterpret_v_u16m2_u64m2(__VA_ARGS__) -#define vreinterpret_v_u16m4_u64m4(...) __riscv_vreinterpret_v_u16m4_u64m4(__VA_ARGS__) -#define vreinterpret_v_u16m8_u64m8(...) __riscv_vreinterpret_v_u16m8_u64m8(__VA_ARGS__) -#define vreinterpret_v_i32mf2_i8mf2(...) __riscv_vreinterpret_v_i32mf2_i8mf2(__VA_ARGS__) -#define vreinterpret_v_i32m1_i8m1(...) __riscv_vreinterpret_v_i32m1_i8m1(__VA_ARGS__) -#define vreinterpret_v_i32m2_i8m2(...) __riscv_vreinterpret_v_i32m2_i8m2(__VA_ARGS__) -#define vreinterpret_v_i32m4_i8m4(...) __riscv_vreinterpret_v_i32m4_i8m4(__VA_ARGS__) -#define vreinterpret_v_i32m8_i8m8(...) __riscv_vreinterpret_v_i32m8_i8m8(__VA_ARGS__) -#define vreinterpret_v_u32mf2_u8mf2(...) __riscv_vreinterpret_v_u32mf2_u8mf2(__VA_ARGS__) -#define vreinterpret_v_u32m1_u8m1(...) __riscv_vreinterpret_v_u32m1_u8m1(__VA_ARGS__) -#define vreinterpret_v_u32m2_u8m2(...) __riscv_vreinterpret_v_u32m2_u8m2(__VA_ARGS__) -#define vreinterpret_v_u32m4_u8m4(...) __riscv_vreinterpret_v_u32m4_u8m4(__VA_ARGS__) -#define vreinterpret_v_u32m8_u8m8(...) __riscv_vreinterpret_v_u32m8_u8m8(__VA_ARGS__) -#define vreinterpret_v_i32mf2_i16mf2(...) __riscv_vreinterpret_v_i32mf2_i16mf2(__VA_ARGS__) -#define vreinterpret_v_i32m1_i16m1(...) __riscv_vreinterpret_v_i32m1_i16m1(__VA_ARGS__) -#define vreinterpret_v_i32m2_i16m2(...) __riscv_vreinterpret_v_i32m2_i16m2(__VA_ARGS__) -#define vreinterpret_v_i32m4_i16m4(...) __riscv_vreinterpret_v_i32m4_i16m4(__VA_ARGS__) -#define vreinterpret_v_i32m8_i16m8(...) __riscv_vreinterpret_v_i32m8_i16m8(__VA_ARGS__) -#define vreinterpret_v_u32mf2_u16mf2(...) __riscv_vreinterpret_v_u32mf2_u16mf2(__VA_ARGS__) -#define vreinterpret_v_u32m1_u16m1(...) __riscv_vreinterpret_v_u32m1_u16m1(__VA_ARGS__) -#define vreinterpret_v_u32m2_u16m2(...) __riscv_vreinterpret_v_u32m2_u16m2(__VA_ARGS__) -#define vreinterpret_v_u32m4_u16m4(...) __riscv_vreinterpret_v_u32m4_u16m4(__VA_ARGS__) -#define vreinterpret_v_u32m8_u16m8(...) __riscv_vreinterpret_v_u32m8_u16m8(__VA_ARGS__) -#define vreinterpret_v_i32m1_i64m1(...) __riscv_vreinterpret_v_i32m1_i64m1(__VA_ARGS__) -#define vreinterpret_v_i32m2_i64m2(...) __riscv_vreinterpret_v_i32m2_i64m2(__VA_ARGS__) -#define vreinterpret_v_i32m4_i64m4(...) __riscv_vreinterpret_v_i32m4_i64m4(__VA_ARGS__) -#define vreinterpret_v_i32m8_i64m8(...) __riscv_vreinterpret_v_i32m8_i64m8(__VA_ARGS__) -#define vreinterpret_v_u32m1_u64m1(...) __riscv_vreinterpret_v_u32m1_u64m1(__VA_ARGS__) -#define vreinterpret_v_u32m2_u64m2(...) __riscv_vreinterpret_v_u32m2_u64m2(__VA_ARGS__) -#define vreinterpret_v_u32m4_u64m4(...) __riscv_vreinterpret_v_u32m4_u64m4(__VA_ARGS__) -#define vreinterpret_v_u32m8_u64m8(...) __riscv_vreinterpret_v_u32m8_u64m8(__VA_ARGS__) -#define vreinterpret_v_i64m1_i8m1(...) __riscv_vreinterpret_v_i64m1_i8m1(__VA_ARGS__) -#define vreinterpret_v_i64m2_i8m2(...) __riscv_vreinterpret_v_i64m2_i8m2(__VA_ARGS__) -#define vreinterpret_v_i64m4_i8m4(...) __riscv_vreinterpret_v_i64m4_i8m4(__VA_ARGS__) -#define vreinterpret_v_i64m8_i8m8(...) __riscv_vreinterpret_v_i64m8_i8m8(__VA_ARGS__) -#define vreinterpret_v_u64m1_u8m1(...) __riscv_vreinterpret_v_u64m1_u8m1(__VA_ARGS__) -#define vreinterpret_v_u64m2_u8m2(...) __riscv_vreinterpret_v_u64m2_u8m2(__VA_ARGS__) -#define vreinterpret_v_u64m4_u8m4(...) __riscv_vreinterpret_v_u64m4_u8m4(__VA_ARGS__) -#define vreinterpret_v_u64m8_u8m8(...) __riscv_vreinterpret_v_u64m8_u8m8(__VA_ARGS__) -#define vreinterpret_v_i64m1_i16m1(...) __riscv_vreinterpret_v_i64m1_i16m1(__VA_ARGS__) -#define vreinterpret_v_i64m2_i16m2(...) __riscv_vreinterpret_v_i64m2_i16m2(__VA_ARGS__) -#define vreinterpret_v_i64m4_i16m4(...) __riscv_vreinterpret_v_i64m4_i16m4(__VA_ARGS__) -#define vreinterpret_v_i64m8_i16m8(...) __riscv_vreinterpret_v_i64m8_i16m8(__VA_ARGS__) -#define vreinterpret_v_u64m1_u16m1(...) __riscv_vreinterpret_v_u64m1_u16m1(__VA_ARGS__) -#define vreinterpret_v_u64m2_u16m2(...) __riscv_vreinterpret_v_u64m2_u16m2(__VA_ARGS__) -#define vreinterpret_v_u64m4_u16m4(...) __riscv_vreinterpret_v_u64m4_u16m4(__VA_ARGS__) -#define vreinterpret_v_u64m8_u16m8(...) __riscv_vreinterpret_v_u64m8_u16m8(__VA_ARGS__) -#define vreinterpret_v_i64m1_i32m1(...) __riscv_vreinterpret_v_i64m1_i32m1(__VA_ARGS__) -#define vreinterpret_v_i64m2_i32m2(...) __riscv_vreinterpret_v_i64m2_i32m2(__VA_ARGS__) -#define vreinterpret_v_i64m4_i32m4(...) __riscv_vreinterpret_v_i64m4_i32m4(__VA_ARGS__) -#define vreinterpret_v_i64m8_i32m8(...) __riscv_vreinterpret_v_i64m8_i32m8(__VA_ARGS__) -#define vreinterpret_v_u64m1_u32m1(...) __riscv_vreinterpret_v_u64m1_u32m1(__VA_ARGS__) -#define vreinterpret_v_u64m2_u32m2(...) __riscv_vreinterpret_v_u64m2_u32m2(__VA_ARGS__) -#define vreinterpret_v_u64m4_u32m4(...) __riscv_vreinterpret_v_u64m4_u32m4(__VA_ARGS__) -#define vreinterpret_v_u64m8_u32m8(...) __riscv_vreinterpret_v_u64m8_u32m8(__VA_ARGS__) -#define vlmul_ext_v_f16mf4_f16mf2(...) __riscv_vlmul_ext_v_f16mf4_f16mf2(__VA_ARGS__) -#define vlmul_ext_v_f16mf4_f16m1(...) __riscv_vlmul_ext_v_f16mf4_f16m1(__VA_ARGS__) -#define vlmul_ext_v_f16mf4_f16m2(...) __riscv_vlmul_ext_v_f16mf4_f16m2(__VA_ARGS__) -#define vlmul_ext_v_f16mf4_f16m4(...) __riscv_vlmul_ext_v_f16mf4_f16m4(__VA_ARGS__) -#define vlmul_ext_v_f16mf4_f16m8(...) __riscv_vlmul_ext_v_f16mf4_f16m8(__VA_ARGS__) -#define vlmul_ext_v_f16mf2_f16m1(...) __riscv_vlmul_ext_v_f16mf2_f16m1(__VA_ARGS__) -#define vlmul_ext_v_f16mf2_f16m2(...) __riscv_vlmul_ext_v_f16mf2_f16m2(__VA_ARGS__) -#define vlmul_ext_v_f16mf2_f16m4(...) __riscv_vlmul_ext_v_f16mf2_f16m4(__VA_ARGS__) -#define vlmul_ext_v_f16mf2_f16m8(...) __riscv_vlmul_ext_v_f16mf2_f16m8(__VA_ARGS__) -#define vlmul_ext_v_f16m1_f16m2(...) __riscv_vlmul_ext_v_f16m1_f16m2(__VA_ARGS__) -#define vlmul_ext_v_f16m1_f16m4(...) __riscv_vlmul_ext_v_f16m1_f16m4(__VA_ARGS__) -#define vlmul_ext_v_f16m1_f16m8(...) __riscv_vlmul_ext_v_f16m1_f16m8(__VA_ARGS__) -#define vlmul_ext_v_f16m2_f16m4(...) __riscv_vlmul_ext_v_f16m2_f16m4(__VA_ARGS__) -#define vlmul_ext_v_f16m2_f16m8(...) __riscv_vlmul_ext_v_f16m2_f16m8(__VA_ARGS__) -#define vlmul_ext_v_f16m4_f16m8(...) __riscv_vlmul_ext_v_f16m4_f16m8(__VA_ARGS__) -#define vlmul_ext_v_f32mf2_f32m1(...) __riscv_vlmul_ext_v_f32mf2_f32m1(__VA_ARGS__) -#define vlmul_ext_v_f32mf2_f32m2(...) __riscv_vlmul_ext_v_f32mf2_f32m2(__VA_ARGS__) -#define vlmul_ext_v_f32mf2_f32m4(...) __riscv_vlmul_ext_v_f32mf2_f32m4(__VA_ARGS__) -#define vlmul_ext_v_f32mf2_f32m8(...) __riscv_vlmul_ext_v_f32mf2_f32m8(__VA_ARGS__) -#define vlmul_ext_v_f32m1_f32m2(...) __riscv_vlmul_ext_v_f32m1_f32m2(__VA_ARGS__) -#define vlmul_ext_v_f32m1_f32m4(...) __riscv_vlmul_ext_v_f32m1_f32m4(__VA_ARGS__) -#define vlmul_ext_v_f32m1_f32m8(...) __riscv_vlmul_ext_v_f32m1_f32m8(__VA_ARGS__) -#define vlmul_ext_v_f32m2_f32m4(...) __riscv_vlmul_ext_v_f32m2_f32m4(__VA_ARGS__) -#define vlmul_ext_v_f32m2_f32m8(...) __riscv_vlmul_ext_v_f32m2_f32m8(__VA_ARGS__) -#define vlmul_ext_v_f32m4_f32m8(...) __riscv_vlmul_ext_v_f32m4_f32m8(__VA_ARGS__) -#define vlmul_ext_v_f64m1_f64m2(...) __riscv_vlmul_ext_v_f64m1_f64m2(__VA_ARGS__) -#define vlmul_ext_v_f64m1_f64m4(...) __riscv_vlmul_ext_v_f64m1_f64m4(__VA_ARGS__) -#define vlmul_ext_v_f64m1_f64m8(...) __riscv_vlmul_ext_v_f64m1_f64m8(__VA_ARGS__) -#define vlmul_ext_v_f64m2_f64m4(...) __riscv_vlmul_ext_v_f64m2_f64m4(__VA_ARGS__) -#define vlmul_ext_v_f64m2_f64m8(...) __riscv_vlmul_ext_v_f64m2_f64m8(__VA_ARGS__) -#define vlmul_ext_v_f64m4_f64m8(...) __riscv_vlmul_ext_v_f64m4_f64m8(__VA_ARGS__) -#define vlmul_ext_v_i8mf8_i8mf4(...) __riscv_vlmul_ext_v_i8mf8_i8mf4(__VA_ARGS__) -#define vlmul_ext_v_i8mf8_i8mf2(...) __riscv_vlmul_ext_v_i8mf8_i8mf2(__VA_ARGS__) -#define vlmul_ext_v_i8mf8_i8m1(...) __riscv_vlmul_ext_v_i8mf8_i8m1(__VA_ARGS__) -#define vlmul_ext_v_i8mf8_i8m2(...) __riscv_vlmul_ext_v_i8mf8_i8m2(__VA_ARGS__) -#define vlmul_ext_v_i8mf8_i8m4(...) __riscv_vlmul_ext_v_i8mf8_i8m4(__VA_ARGS__) -#define vlmul_ext_v_i8mf8_i8m8(...) __riscv_vlmul_ext_v_i8mf8_i8m8(__VA_ARGS__) -#define vlmul_ext_v_i8mf4_i8mf2(...) __riscv_vlmul_ext_v_i8mf4_i8mf2(__VA_ARGS__) -#define vlmul_ext_v_i8mf4_i8m1(...) __riscv_vlmul_ext_v_i8mf4_i8m1(__VA_ARGS__) -#define vlmul_ext_v_i8mf4_i8m2(...) __riscv_vlmul_ext_v_i8mf4_i8m2(__VA_ARGS__) -#define vlmul_ext_v_i8mf4_i8m4(...) __riscv_vlmul_ext_v_i8mf4_i8m4(__VA_ARGS__) -#define vlmul_ext_v_i8mf4_i8m8(...) __riscv_vlmul_ext_v_i8mf4_i8m8(__VA_ARGS__) -#define vlmul_ext_v_i8mf2_i8m1(...) __riscv_vlmul_ext_v_i8mf2_i8m1(__VA_ARGS__) -#define vlmul_ext_v_i8mf2_i8m2(...) __riscv_vlmul_ext_v_i8mf2_i8m2(__VA_ARGS__) -#define vlmul_ext_v_i8mf2_i8m4(...) __riscv_vlmul_ext_v_i8mf2_i8m4(__VA_ARGS__) -#define vlmul_ext_v_i8mf2_i8m8(...) __riscv_vlmul_ext_v_i8mf2_i8m8(__VA_ARGS__) -#define vlmul_ext_v_i8m1_i8m2(...) __riscv_vlmul_ext_v_i8m1_i8m2(__VA_ARGS__) -#define vlmul_ext_v_i8m1_i8m4(...) __riscv_vlmul_ext_v_i8m1_i8m4(__VA_ARGS__) -#define vlmul_ext_v_i8m1_i8m8(...) __riscv_vlmul_ext_v_i8m1_i8m8(__VA_ARGS__) -#define vlmul_ext_v_i8m2_i8m4(...) __riscv_vlmul_ext_v_i8m2_i8m4(__VA_ARGS__) -#define vlmul_ext_v_i8m2_i8m8(...) __riscv_vlmul_ext_v_i8m2_i8m8(__VA_ARGS__) -#define vlmul_ext_v_i8m4_i8m8(...) __riscv_vlmul_ext_v_i8m4_i8m8(__VA_ARGS__) -#define vlmul_ext_v_i16mf4_i16mf2(...) __riscv_vlmul_ext_v_i16mf4_i16mf2(__VA_ARGS__) -#define vlmul_ext_v_i16mf4_i16m1(...) __riscv_vlmul_ext_v_i16mf4_i16m1(__VA_ARGS__) -#define vlmul_ext_v_i16mf4_i16m2(...) __riscv_vlmul_ext_v_i16mf4_i16m2(__VA_ARGS__) -#define vlmul_ext_v_i16mf4_i16m4(...) __riscv_vlmul_ext_v_i16mf4_i16m4(__VA_ARGS__) -#define vlmul_ext_v_i16mf4_i16m8(...) __riscv_vlmul_ext_v_i16mf4_i16m8(__VA_ARGS__) -#define vlmul_ext_v_i16mf2_i16m1(...) __riscv_vlmul_ext_v_i16mf2_i16m1(__VA_ARGS__) -#define vlmul_ext_v_i16mf2_i16m2(...) __riscv_vlmul_ext_v_i16mf2_i16m2(__VA_ARGS__) -#define vlmul_ext_v_i16mf2_i16m4(...) __riscv_vlmul_ext_v_i16mf2_i16m4(__VA_ARGS__) -#define vlmul_ext_v_i16mf2_i16m8(...) __riscv_vlmul_ext_v_i16mf2_i16m8(__VA_ARGS__) -#define vlmul_ext_v_i16m1_i16m2(...) __riscv_vlmul_ext_v_i16m1_i16m2(__VA_ARGS__) -#define vlmul_ext_v_i16m1_i16m4(...) __riscv_vlmul_ext_v_i16m1_i16m4(__VA_ARGS__) -#define vlmul_ext_v_i16m1_i16m8(...) __riscv_vlmul_ext_v_i16m1_i16m8(__VA_ARGS__) -#define vlmul_ext_v_i16m2_i16m4(...) __riscv_vlmul_ext_v_i16m2_i16m4(__VA_ARGS__) -#define vlmul_ext_v_i16m2_i16m8(...) __riscv_vlmul_ext_v_i16m2_i16m8(__VA_ARGS__) -#define vlmul_ext_v_i16m4_i16m8(...) __riscv_vlmul_ext_v_i16m4_i16m8(__VA_ARGS__) -#define vlmul_ext_v_i32mf2_i32m1(...) __riscv_vlmul_ext_v_i32mf2_i32m1(__VA_ARGS__) -#define vlmul_ext_v_i32mf2_i32m2(...) __riscv_vlmul_ext_v_i32mf2_i32m2(__VA_ARGS__) -#define vlmul_ext_v_i32mf2_i32m4(...) __riscv_vlmul_ext_v_i32mf2_i32m4(__VA_ARGS__) -#define vlmul_ext_v_i32mf2_i32m8(...) __riscv_vlmul_ext_v_i32mf2_i32m8(__VA_ARGS__) -#define vlmul_ext_v_i32m1_i32m2(...) __riscv_vlmul_ext_v_i32m1_i32m2(__VA_ARGS__) -#define vlmul_ext_v_i32m1_i32m4(...) __riscv_vlmul_ext_v_i32m1_i32m4(__VA_ARGS__) -#define vlmul_ext_v_i32m1_i32m8(...) __riscv_vlmul_ext_v_i32m1_i32m8(__VA_ARGS__) -#define vlmul_ext_v_i32m2_i32m4(...) __riscv_vlmul_ext_v_i32m2_i32m4(__VA_ARGS__) -#define vlmul_ext_v_i32m2_i32m8(...) __riscv_vlmul_ext_v_i32m2_i32m8(__VA_ARGS__) -#define vlmul_ext_v_i32m4_i32m8(...) __riscv_vlmul_ext_v_i32m4_i32m8(__VA_ARGS__) -#define vlmul_ext_v_i64m1_i64m2(...) __riscv_vlmul_ext_v_i64m1_i64m2(__VA_ARGS__) -#define vlmul_ext_v_i64m1_i64m4(...) __riscv_vlmul_ext_v_i64m1_i64m4(__VA_ARGS__) -#define vlmul_ext_v_i64m1_i64m8(...) __riscv_vlmul_ext_v_i64m1_i64m8(__VA_ARGS__) -#define vlmul_ext_v_i64m2_i64m4(...) __riscv_vlmul_ext_v_i64m2_i64m4(__VA_ARGS__) -#define vlmul_ext_v_i64m2_i64m8(...) __riscv_vlmul_ext_v_i64m2_i64m8(__VA_ARGS__) -#define vlmul_ext_v_i64m4_i64m8(...) __riscv_vlmul_ext_v_i64m4_i64m8(__VA_ARGS__) -#define vlmul_ext_v_u8mf8_u8mf4(...) __riscv_vlmul_ext_v_u8mf8_u8mf4(__VA_ARGS__) -#define vlmul_ext_v_u8mf8_u8mf2(...) __riscv_vlmul_ext_v_u8mf8_u8mf2(__VA_ARGS__) -#define vlmul_ext_v_u8mf8_u8m1(...) __riscv_vlmul_ext_v_u8mf8_u8m1(__VA_ARGS__) -#define vlmul_ext_v_u8mf8_u8m2(...) __riscv_vlmul_ext_v_u8mf8_u8m2(__VA_ARGS__) -#define vlmul_ext_v_u8mf8_u8m4(...) __riscv_vlmul_ext_v_u8mf8_u8m4(__VA_ARGS__) -#define vlmul_ext_v_u8mf8_u8m8(...) __riscv_vlmul_ext_v_u8mf8_u8m8(__VA_ARGS__) -#define vlmul_ext_v_u8mf4_u8mf2(...) __riscv_vlmul_ext_v_u8mf4_u8mf2(__VA_ARGS__) -#define vlmul_ext_v_u8mf4_u8m1(...) __riscv_vlmul_ext_v_u8mf4_u8m1(__VA_ARGS__) -#define vlmul_ext_v_u8mf4_u8m2(...) __riscv_vlmul_ext_v_u8mf4_u8m2(__VA_ARGS__) -#define vlmul_ext_v_u8mf4_u8m4(...) __riscv_vlmul_ext_v_u8mf4_u8m4(__VA_ARGS__) -#define vlmul_ext_v_u8mf4_u8m8(...) __riscv_vlmul_ext_v_u8mf4_u8m8(__VA_ARGS__) -#define vlmul_ext_v_u8mf2_u8m1(...) __riscv_vlmul_ext_v_u8mf2_u8m1(__VA_ARGS__) -#define vlmul_ext_v_u8mf2_u8m2(...) __riscv_vlmul_ext_v_u8mf2_u8m2(__VA_ARGS__) -#define vlmul_ext_v_u8mf2_u8m4(...) __riscv_vlmul_ext_v_u8mf2_u8m4(__VA_ARGS__) -#define vlmul_ext_v_u8mf2_u8m8(...) __riscv_vlmul_ext_v_u8mf2_u8m8(__VA_ARGS__) -#define vlmul_ext_v_u8m1_u8m2(...) __riscv_vlmul_ext_v_u8m1_u8m2(__VA_ARGS__) -#define vlmul_ext_v_u8m1_u8m4(...) __riscv_vlmul_ext_v_u8m1_u8m4(__VA_ARGS__) -#define vlmul_ext_v_u8m1_u8m8(...) __riscv_vlmul_ext_v_u8m1_u8m8(__VA_ARGS__) -#define vlmul_ext_v_u8m2_u8m4(...) __riscv_vlmul_ext_v_u8m2_u8m4(__VA_ARGS__) -#define vlmul_ext_v_u8m2_u8m8(...) __riscv_vlmul_ext_v_u8m2_u8m8(__VA_ARGS__) -#define vlmul_ext_v_u8m4_u8m8(...) __riscv_vlmul_ext_v_u8m4_u8m8(__VA_ARGS__) -#define vlmul_ext_v_u16mf4_u16mf2(...) __riscv_vlmul_ext_v_u16mf4_u16mf2(__VA_ARGS__) -#define vlmul_ext_v_u16mf4_u16m1(...) __riscv_vlmul_ext_v_u16mf4_u16m1(__VA_ARGS__) -#define vlmul_ext_v_u16mf4_u16m2(...) __riscv_vlmul_ext_v_u16mf4_u16m2(__VA_ARGS__) -#define vlmul_ext_v_u16mf4_u16m4(...) __riscv_vlmul_ext_v_u16mf4_u16m4(__VA_ARGS__) -#define vlmul_ext_v_u16mf4_u16m8(...) __riscv_vlmul_ext_v_u16mf4_u16m8(__VA_ARGS__) -#define vlmul_ext_v_u16mf2_u16m1(...) __riscv_vlmul_ext_v_u16mf2_u16m1(__VA_ARGS__) -#define vlmul_ext_v_u16mf2_u16m2(...) __riscv_vlmul_ext_v_u16mf2_u16m2(__VA_ARGS__) -#define vlmul_ext_v_u16mf2_u16m4(...) __riscv_vlmul_ext_v_u16mf2_u16m4(__VA_ARGS__) -#define vlmul_ext_v_u16mf2_u16m8(...) __riscv_vlmul_ext_v_u16mf2_u16m8(__VA_ARGS__) -#define vlmul_ext_v_u16m1_u16m2(...) __riscv_vlmul_ext_v_u16m1_u16m2(__VA_ARGS__) -#define vlmul_ext_v_u16m1_u16m4(...) __riscv_vlmul_ext_v_u16m1_u16m4(__VA_ARGS__) -#define vlmul_ext_v_u16m1_u16m8(...) __riscv_vlmul_ext_v_u16m1_u16m8(__VA_ARGS__) -#define vlmul_ext_v_u16m2_u16m4(...) __riscv_vlmul_ext_v_u16m2_u16m4(__VA_ARGS__) -#define vlmul_ext_v_u16m2_u16m8(...) __riscv_vlmul_ext_v_u16m2_u16m8(__VA_ARGS__) -#define vlmul_ext_v_u16m4_u16m8(...) __riscv_vlmul_ext_v_u16m4_u16m8(__VA_ARGS__) -#define vlmul_ext_v_u32mf2_u32m1(...) __riscv_vlmul_ext_v_u32mf2_u32m1(__VA_ARGS__) -#define vlmul_ext_v_u32mf2_u32m2(...) __riscv_vlmul_ext_v_u32mf2_u32m2(__VA_ARGS__) -#define vlmul_ext_v_u32mf2_u32m4(...) __riscv_vlmul_ext_v_u32mf2_u32m4(__VA_ARGS__) -#define vlmul_ext_v_u32mf2_u32m8(...) __riscv_vlmul_ext_v_u32mf2_u32m8(__VA_ARGS__) -#define vlmul_ext_v_u32m1_u32m2(...) __riscv_vlmul_ext_v_u32m1_u32m2(__VA_ARGS__) -#define vlmul_ext_v_u32m1_u32m4(...) __riscv_vlmul_ext_v_u32m1_u32m4(__VA_ARGS__) -#define vlmul_ext_v_u32m1_u32m8(...) __riscv_vlmul_ext_v_u32m1_u32m8(__VA_ARGS__) -#define vlmul_ext_v_u32m2_u32m4(...) __riscv_vlmul_ext_v_u32m2_u32m4(__VA_ARGS__) -#define vlmul_ext_v_u32m2_u32m8(...) __riscv_vlmul_ext_v_u32m2_u32m8(__VA_ARGS__) -#define vlmul_ext_v_u32m4_u32m8(...) __riscv_vlmul_ext_v_u32m4_u32m8(__VA_ARGS__) -#define vlmul_ext_v_u64m1_u64m2(...) __riscv_vlmul_ext_v_u64m1_u64m2(__VA_ARGS__) -#define vlmul_ext_v_u64m1_u64m4(...) __riscv_vlmul_ext_v_u64m1_u64m4(__VA_ARGS__) -#define vlmul_ext_v_u64m1_u64m8(...) __riscv_vlmul_ext_v_u64m1_u64m8(__VA_ARGS__) -#define vlmul_ext_v_u64m2_u64m4(...) __riscv_vlmul_ext_v_u64m2_u64m4(__VA_ARGS__) -#define vlmul_ext_v_u64m2_u64m8(...) __riscv_vlmul_ext_v_u64m2_u64m8(__VA_ARGS__) -#define vlmul_ext_v_u64m4_u64m8(...) __riscv_vlmul_ext_v_u64m4_u64m8(__VA_ARGS__) -#define vlmul_trunc_v_f16mf2_f16mf4(...) __riscv_vlmul_trunc_v_f16mf2_f16mf4(__VA_ARGS__) -#define vlmul_trunc_v_f16m1_f16mf4(...) __riscv_vlmul_trunc_v_f16m1_f16mf4(__VA_ARGS__) -#define vlmul_trunc_v_f16m1_f16mf2(...) __riscv_vlmul_trunc_v_f16m1_f16mf2(__VA_ARGS__) -#define vlmul_trunc_v_f16m2_f16mf4(...) __riscv_vlmul_trunc_v_f16m2_f16mf4(__VA_ARGS__) -#define vlmul_trunc_v_f16m2_f16mf2(...) __riscv_vlmul_trunc_v_f16m2_f16mf2(__VA_ARGS__) -#define vlmul_trunc_v_f16m2_f16m1(...) __riscv_vlmul_trunc_v_f16m2_f16m1(__VA_ARGS__) -#define vlmul_trunc_v_f16m4_f16mf4(...) __riscv_vlmul_trunc_v_f16m4_f16mf4(__VA_ARGS__) -#define vlmul_trunc_v_f16m4_f16mf2(...) __riscv_vlmul_trunc_v_f16m4_f16mf2(__VA_ARGS__) -#define vlmul_trunc_v_f16m4_f16m1(...) __riscv_vlmul_trunc_v_f16m4_f16m1(__VA_ARGS__) -#define vlmul_trunc_v_f16m4_f16m2(...) __riscv_vlmul_trunc_v_f16m4_f16m2(__VA_ARGS__) -#define vlmul_trunc_v_f16m8_f16mf4(...) __riscv_vlmul_trunc_v_f16m8_f16mf4(__VA_ARGS__) -#define vlmul_trunc_v_f16m8_f16mf2(...) __riscv_vlmul_trunc_v_f16m8_f16mf2(__VA_ARGS__) -#define vlmul_trunc_v_f16m8_f16m1(...) __riscv_vlmul_trunc_v_f16m8_f16m1(__VA_ARGS__) -#define vlmul_trunc_v_f16m8_f16m2(...) __riscv_vlmul_trunc_v_f16m8_f16m2(__VA_ARGS__) -#define vlmul_trunc_v_f16m8_f16m4(...) __riscv_vlmul_trunc_v_f16m8_f16m4(__VA_ARGS__) -#define vlmul_trunc_v_f32m1_f32mf2(...) __riscv_vlmul_trunc_v_f32m1_f32mf2(__VA_ARGS__) -#define vlmul_trunc_v_f32m2_f32mf2(...) __riscv_vlmul_trunc_v_f32m2_f32mf2(__VA_ARGS__) -#define vlmul_trunc_v_f32m2_f32m1(...) __riscv_vlmul_trunc_v_f32m2_f32m1(__VA_ARGS__) -#define vlmul_trunc_v_f32m4_f32mf2(...) __riscv_vlmul_trunc_v_f32m4_f32mf2(__VA_ARGS__) -#define vlmul_trunc_v_f32m4_f32m1(...) __riscv_vlmul_trunc_v_f32m4_f32m1(__VA_ARGS__) -#define vlmul_trunc_v_f32m4_f32m2(...) __riscv_vlmul_trunc_v_f32m4_f32m2(__VA_ARGS__) -#define vlmul_trunc_v_f32m8_f32mf2(...) __riscv_vlmul_trunc_v_f32m8_f32mf2(__VA_ARGS__) -#define vlmul_trunc_v_f32m8_f32m1(...) __riscv_vlmul_trunc_v_f32m8_f32m1(__VA_ARGS__) -#define vlmul_trunc_v_f32m8_f32m2(...) __riscv_vlmul_trunc_v_f32m8_f32m2(__VA_ARGS__) -#define vlmul_trunc_v_f32m8_f32m4(...) __riscv_vlmul_trunc_v_f32m8_f32m4(__VA_ARGS__) -#define vlmul_trunc_v_f64m2_f64m1(...) __riscv_vlmul_trunc_v_f64m2_f64m1(__VA_ARGS__) -#define vlmul_trunc_v_f64m4_f64m1(...) __riscv_vlmul_trunc_v_f64m4_f64m1(__VA_ARGS__) -#define vlmul_trunc_v_f64m4_f64m2(...) __riscv_vlmul_trunc_v_f64m4_f64m2(__VA_ARGS__) -#define vlmul_trunc_v_f64m8_f64m1(...) __riscv_vlmul_trunc_v_f64m8_f64m1(__VA_ARGS__) -#define vlmul_trunc_v_f64m8_f64m2(...) __riscv_vlmul_trunc_v_f64m8_f64m2(__VA_ARGS__) -#define vlmul_trunc_v_f64m8_f64m4(...) __riscv_vlmul_trunc_v_f64m8_f64m4(__VA_ARGS__) -#define vlmul_trunc_v_i8mf4_i8mf8(...) __riscv_vlmul_trunc_v_i8mf4_i8mf8(__VA_ARGS__) -#define vlmul_trunc_v_i8mf2_i8mf8(...) __riscv_vlmul_trunc_v_i8mf2_i8mf8(__VA_ARGS__) -#define vlmul_trunc_v_i8mf2_i8mf4(...) __riscv_vlmul_trunc_v_i8mf2_i8mf4(__VA_ARGS__) -#define vlmul_trunc_v_i8m1_i8mf8(...) __riscv_vlmul_trunc_v_i8m1_i8mf8(__VA_ARGS__) -#define vlmul_trunc_v_i8m1_i8mf4(...) __riscv_vlmul_trunc_v_i8m1_i8mf4(__VA_ARGS__) -#define vlmul_trunc_v_i8m1_i8mf2(...) __riscv_vlmul_trunc_v_i8m1_i8mf2(__VA_ARGS__) -#define vlmul_trunc_v_i8m2_i8mf8(...) __riscv_vlmul_trunc_v_i8m2_i8mf8(__VA_ARGS__) -#define vlmul_trunc_v_i8m2_i8mf4(...) __riscv_vlmul_trunc_v_i8m2_i8mf4(__VA_ARGS__) -#define vlmul_trunc_v_i8m2_i8mf2(...) __riscv_vlmul_trunc_v_i8m2_i8mf2(__VA_ARGS__) -#define vlmul_trunc_v_i8m2_i8m1(...) __riscv_vlmul_trunc_v_i8m2_i8m1(__VA_ARGS__) -#define vlmul_trunc_v_i8m4_i8mf8(...) __riscv_vlmul_trunc_v_i8m4_i8mf8(__VA_ARGS__) -#define vlmul_trunc_v_i8m4_i8mf4(...) __riscv_vlmul_trunc_v_i8m4_i8mf4(__VA_ARGS__) -#define vlmul_trunc_v_i8m4_i8mf2(...) __riscv_vlmul_trunc_v_i8m4_i8mf2(__VA_ARGS__) -#define vlmul_trunc_v_i8m4_i8m1(...) __riscv_vlmul_trunc_v_i8m4_i8m1(__VA_ARGS__) -#define vlmul_trunc_v_i8m4_i8m2(...) __riscv_vlmul_trunc_v_i8m4_i8m2(__VA_ARGS__) -#define vlmul_trunc_v_i8m8_i8mf8(...) __riscv_vlmul_trunc_v_i8m8_i8mf8(__VA_ARGS__) -#define vlmul_trunc_v_i8m8_i8mf4(...) __riscv_vlmul_trunc_v_i8m8_i8mf4(__VA_ARGS__) -#define vlmul_trunc_v_i8m8_i8mf2(...) __riscv_vlmul_trunc_v_i8m8_i8mf2(__VA_ARGS__) -#define vlmul_trunc_v_i8m8_i8m1(...) __riscv_vlmul_trunc_v_i8m8_i8m1(__VA_ARGS__) -#define vlmul_trunc_v_i8m8_i8m2(...) __riscv_vlmul_trunc_v_i8m8_i8m2(__VA_ARGS__) -#define vlmul_trunc_v_i8m8_i8m4(...) __riscv_vlmul_trunc_v_i8m8_i8m4(__VA_ARGS__) -#define vlmul_trunc_v_i16mf2_i16mf4(...) __riscv_vlmul_trunc_v_i16mf2_i16mf4(__VA_ARGS__) -#define vlmul_trunc_v_i16m1_i16mf4(...) __riscv_vlmul_trunc_v_i16m1_i16mf4(__VA_ARGS__) -#define vlmul_trunc_v_i16m1_i16mf2(...) __riscv_vlmul_trunc_v_i16m1_i16mf2(__VA_ARGS__) -#define vlmul_trunc_v_i16m2_i16mf4(...) __riscv_vlmul_trunc_v_i16m2_i16mf4(__VA_ARGS__) -#define vlmul_trunc_v_i16m2_i16mf2(...) __riscv_vlmul_trunc_v_i16m2_i16mf2(__VA_ARGS__) -#define vlmul_trunc_v_i16m2_i16m1(...) __riscv_vlmul_trunc_v_i16m2_i16m1(__VA_ARGS__) -#define vlmul_trunc_v_i16m4_i16mf4(...) __riscv_vlmul_trunc_v_i16m4_i16mf4(__VA_ARGS__) -#define vlmul_trunc_v_i16m4_i16mf2(...) __riscv_vlmul_trunc_v_i16m4_i16mf2(__VA_ARGS__) -#define vlmul_trunc_v_i16m4_i16m1(...) __riscv_vlmul_trunc_v_i16m4_i16m1(__VA_ARGS__) -#define vlmul_trunc_v_i16m4_i16m2(...) __riscv_vlmul_trunc_v_i16m4_i16m2(__VA_ARGS__) -#define vlmul_trunc_v_i16m8_i16mf4(...) __riscv_vlmul_trunc_v_i16m8_i16mf4(__VA_ARGS__) -#define vlmul_trunc_v_i16m8_i16mf2(...) __riscv_vlmul_trunc_v_i16m8_i16mf2(__VA_ARGS__) -#define vlmul_trunc_v_i16m8_i16m1(...) __riscv_vlmul_trunc_v_i16m8_i16m1(__VA_ARGS__) -#define vlmul_trunc_v_i16m8_i16m2(...) __riscv_vlmul_trunc_v_i16m8_i16m2(__VA_ARGS__) -#define vlmul_trunc_v_i16m8_i16m4(...) __riscv_vlmul_trunc_v_i16m8_i16m4(__VA_ARGS__) -#define vlmul_trunc_v_i32m1_i32mf2(...) __riscv_vlmul_trunc_v_i32m1_i32mf2(__VA_ARGS__) -#define vlmul_trunc_v_i32m2_i32mf2(...) __riscv_vlmul_trunc_v_i32m2_i32mf2(__VA_ARGS__) -#define vlmul_trunc_v_i32m2_i32m1(...) __riscv_vlmul_trunc_v_i32m2_i32m1(__VA_ARGS__) -#define vlmul_trunc_v_i32m4_i32mf2(...) __riscv_vlmul_trunc_v_i32m4_i32mf2(__VA_ARGS__) -#define vlmul_trunc_v_i32m4_i32m1(...) __riscv_vlmul_trunc_v_i32m4_i32m1(__VA_ARGS__) -#define vlmul_trunc_v_i32m4_i32m2(...) __riscv_vlmul_trunc_v_i32m4_i32m2(__VA_ARGS__) -#define vlmul_trunc_v_i32m8_i32mf2(...) __riscv_vlmul_trunc_v_i32m8_i32mf2(__VA_ARGS__) -#define vlmul_trunc_v_i32m8_i32m1(...) __riscv_vlmul_trunc_v_i32m8_i32m1(__VA_ARGS__) -#define vlmul_trunc_v_i32m8_i32m2(...) __riscv_vlmul_trunc_v_i32m8_i32m2(__VA_ARGS__) -#define vlmul_trunc_v_i32m8_i32m4(...) __riscv_vlmul_trunc_v_i32m8_i32m4(__VA_ARGS__) -#define vlmul_trunc_v_i64m2_i64m1(...) __riscv_vlmul_trunc_v_i64m2_i64m1(__VA_ARGS__) -#define vlmul_trunc_v_i64m4_i64m1(...) __riscv_vlmul_trunc_v_i64m4_i64m1(__VA_ARGS__) -#define vlmul_trunc_v_i64m4_i64m2(...) __riscv_vlmul_trunc_v_i64m4_i64m2(__VA_ARGS__) -#define vlmul_trunc_v_i64m8_i64m1(...) __riscv_vlmul_trunc_v_i64m8_i64m1(__VA_ARGS__) -#define vlmul_trunc_v_i64m8_i64m2(...) __riscv_vlmul_trunc_v_i64m8_i64m2(__VA_ARGS__) -#define vlmul_trunc_v_i64m8_i64m4(...) __riscv_vlmul_trunc_v_i64m8_i64m4(__VA_ARGS__) -#define vlmul_trunc_v_u8mf4_u8mf8(...) __riscv_vlmul_trunc_v_u8mf4_u8mf8(__VA_ARGS__) -#define vlmul_trunc_v_u8mf2_u8mf8(...) __riscv_vlmul_trunc_v_u8mf2_u8mf8(__VA_ARGS__) -#define vlmul_trunc_v_u8mf2_u8mf4(...) __riscv_vlmul_trunc_v_u8mf2_u8mf4(__VA_ARGS__) -#define vlmul_trunc_v_u8m1_u8mf8(...) __riscv_vlmul_trunc_v_u8m1_u8mf8(__VA_ARGS__) -#define vlmul_trunc_v_u8m1_u8mf4(...) __riscv_vlmul_trunc_v_u8m1_u8mf4(__VA_ARGS__) -#define vlmul_trunc_v_u8m1_u8mf2(...) __riscv_vlmul_trunc_v_u8m1_u8mf2(__VA_ARGS__) -#define vlmul_trunc_v_u8m2_u8mf8(...) __riscv_vlmul_trunc_v_u8m2_u8mf8(__VA_ARGS__) -#define vlmul_trunc_v_u8m2_u8mf4(...) __riscv_vlmul_trunc_v_u8m2_u8mf4(__VA_ARGS__) -#define vlmul_trunc_v_u8m2_u8mf2(...) __riscv_vlmul_trunc_v_u8m2_u8mf2(__VA_ARGS__) -#define vlmul_trunc_v_u8m2_u8m1(...) __riscv_vlmul_trunc_v_u8m2_u8m1(__VA_ARGS__) -#define vlmul_trunc_v_u8m4_u8mf8(...) __riscv_vlmul_trunc_v_u8m4_u8mf8(__VA_ARGS__) -#define vlmul_trunc_v_u8m4_u8mf4(...) __riscv_vlmul_trunc_v_u8m4_u8mf4(__VA_ARGS__) -#define vlmul_trunc_v_u8m4_u8mf2(...) __riscv_vlmul_trunc_v_u8m4_u8mf2(__VA_ARGS__) -#define vlmul_trunc_v_u8m4_u8m1(...) __riscv_vlmul_trunc_v_u8m4_u8m1(__VA_ARGS__) -#define vlmul_trunc_v_u8m4_u8m2(...) __riscv_vlmul_trunc_v_u8m4_u8m2(__VA_ARGS__) -#define vlmul_trunc_v_u8m8_u8mf8(...) __riscv_vlmul_trunc_v_u8m8_u8mf8(__VA_ARGS__) -#define vlmul_trunc_v_u8m8_u8mf4(...) __riscv_vlmul_trunc_v_u8m8_u8mf4(__VA_ARGS__) -#define vlmul_trunc_v_u8m8_u8mf2(...) __riscv_vlmul_trunc_v_u8m8_u8mf2(__VA_ARGS__) -#define vlmul_trunc_v_u8m8_u8m1(...) __riscv_vlmul_trunc_v_u8m8_u8m1(__VA_ARGS__) -#define vlmul_trunc_v_u8m8_u8m2(...) __riscv_vlmul_trunc_v_u8m8_u8m2(__VA_ARGS__) -#define vlmul_trunc_v_u8m8_u8m4(...) __riscv_vlmul_trunc_v_u8m8_u8m4(__VA_ARGS__) -#define vlmul_trunc_v_u16mf2_u16mf4(...) __riscv_vlmul_trunc_v_u16mf2_u16mf4(__VA_ARGS__) -#define vlmul_trunc_v_u16m1_u16mf4(...) __riscv_vlmul_trunc_v_u16m1_u16mf4(__VA_ARGS__) -#define vlmul_trunc_v_u16m1_u16mf2(...) __riscv_vlmul_trunc_v_u16m1_u16mf2(__VA_ARGS__) -#define vlmul_trunc_v_u16m2_u16mf4(...) __riscv_vlmul_trunc_v_u16m2_u16mf4(__VA_ARGS__) -#define vlmul_trunc_v_u16m2_u16mf2(...) __riscv_vlmul_trunc_v_u16m2_u16mf2(__VA_ARGS__) -#define vlmul_trunc_v_u16m2_u16m1(...) __riscv_vlmul_trunc_v_u16m2_u16m1(__VA_ARGS__) -#define vlmul_trunc_v_u16m4_u16mf4(...) __riscv_vlmul_trunc_v_u16m4_u16mf4(__VA_ARGS__) -#define vlmul_trunc_v_u16m4_u16mf2(...) __riscv_vlmul_trunc_v_u16m4_u16mf2(__VA_ARGS__) -#define vlmul_trunc_v_u16m4_u16m1(...) __riscv_vlmul_trunc_v_u16m4_u16m1(__VA_ARGS__) -#define vlmul_trunc_v_u16m4_u16m2(...) __riscv_vlmul_trunc_v_u16m4_u16m2(__VA_ARGS__) -#define vlmul_trunc_v_u16m8_u16mf4(...) __riscv_vlmul_trunc_v_u16m8_u16mf4(__VA_ARGS__) -#define vlmul_trunc_v_u16m8_u16mf2(...) __riscv_vlmul_trunc_v_u16m8_u16mf2(__VA_ARGS__) -#define vlmul_trunc_v_u16m8_u16m1(...) __riscv_vlmul_trunc_v_u16m8_u16m1(__VA_ARGS__) -#define vlmul_trunc_v_u16m8_u16m2(...) __riscv_vlmul_trunc_v_u16m8_u16m2(__VA_ARGS__) -#define vlmul_trunc_v_u16m8_u16m4(...) __riscv_vlmul_trunc_v_u16m8_u16m4(__VA_ARGS__) -#define vlmul_trunc_v_u32m1_u32mf2(...) __riscv_vlmul_trunc_v_u32m1_u32mf2(__VA_ARGS__) -#define vlmul_trunc_v_u32m2_u32mf2(...) __riscv_vlmul_trunc_v_u32m2_u32mf2(__VA_ARGS__) -#define vlmul_trunc_v_u32m2_u32m1(...) __riscv_vlmul_trunc_v_u32m2_u32m1(__VA_ARGS__) -#define vlmul_trunc_v_u32m4_u32mf2(...) __riscv_vlmul_trunc_v_u32m4_u32mf2(__VA_ARGS__) -#define vlmul_trunc_v_u32m4_u32m1(...) __riscv_vlmul_trunc_v_u32m4_u32m1(__VA_ARGS__) -#define vlmul_trunc_v_u32m4_u32m2(...) __riscv_vlmul_trunc_v_u32m4_u32m2(__VA_ARGS__) -#define vlmul_trunc_v_u32m8_u32mf2(...) __riscv_vlmul_trunc_v_u32m8_u32mf2(__VA_ARGS__) -#define vlmul_trunc_v_u32m8_u32m1(...) __riscv_vlmul_trunc_v_u32m8_u32m1(__VA_ARGS__) -#define vlmul_trunc_v_u32m8_u32m2(...) __riscv_vlmul_trunc_v_u32m8_u32m2(__VA_ARGS__) -#define vlmul_trunc_v_u32m8_u32m4(...) __riscv_vlmul_trunc_v_u32m8_u32m4(__VA_ARGS__) -#define vlmul_trunc_v_u64m2_u64m1(...) __riscv_vlmul_trunc_v_u64m2_u64m1(__VA_ARGS__) -#define vlmul_trunc_v_u64m4_u64m1(...) __riscv_vlmul_trunc_v_u64m4_u64m1(__VA_ARGS__) -#define vlmul_trunc_v_u64m4_u64m2(...) __riscv_vlmul_trunc_v_u64m4_u64m2(__VA_ARGS__) -#define vlmul_trunc_v_u64m8_u64m1(...) __riscv_vlmul_trunc_v_u64m8_u64m1(__VA_ARGS__) -#define vlmul_trunc_v_u64m8_u64m2(...) __riscv_vlmul_trunc_v_u64m8_u64m2(__VA_ARGS__) -#define vlmul_trunc_v_u64m8_u64m4(...) __riscv_vlmul_trunc_v_u64m8_u64m4(__VA_ARGS__) -#define vundefined_f16mf4(...) __riscv_vundefined_f16mf4(__VA_ARGS__) -#define vundefined_f16mf2(...) __riscv_vundefined_f16mf2(__VA_ARGS__) -#define vundefined_f16m1(...) __riscv_vundefined_f16m1(__VA_ARGS__) -#define vundefined_f16m2(...) __riscv_vundefined_f16m2(__VA_ARGS__) -#define vundefined_f16m4(...) __riscv_vundefined_f16m4(__VA_ARGS__) -#define vundefined_f16m8(...) __riscv_vundefined_f16m8(__VA_ARGS__) -#define vundefined_f32mf2(...) __riscv_vundefined_f32mf2(__VA_ARGS__) -#define vundefined_f32m1(...) __riscv_vundefined_f32m1(__VA_ARGS__) -#define vundefined_f32m2(...) __riscv_vundefined_f32m2(__VA_ARGS__) -#define vundefined_f32m4(...) __riscv_vundefined_f32m4(__VA_ARGS__) -#define vundefined_f32m8(...) __riscv_vundefined_f32m8(__VA_ARGS__) -#define vundefined_f64m1(...) __riscv_vundefined_f64m1(__VA_ARGS__) -#define vundefined_f64m2(...) __riscv_vundefined_f64m2(__VA_ARGS__) -#define vundefined_f64m4(...) __riscv_vundefined_f64m4(__VA_ARGS__) -#define vundefined_f64m8(...) __riscv_vundefined_f64m8(__VA_ARGS__) -#define vundefined_i8mf8(...) __riscv_vundefined_i8mf8(__VA_ARGS__) -#define vundefined_i8mf4(...) __riscv_vundefined_i8mf4(__VA_ARGS__) -#define vundefined_i8mf2(...) __riscv_vundefined_i8mf2(__VA_ARGS__) -#define vundefined_i8m1(...) __riscv_vundefined_i8m1(__VA_ARGS__) -#define vundefined_i8m2(...) __riscv_vundefined_i8m2(__VA_ARGS__) -#define vundefined_i8m4(...) __riscv_vundefined_i8m4(__VA_ARGS__) -#define vundefined_i8m8(...) __riscv_vundefined_i8m8(__VA_ARGS__) -#define vundefined_i16mf4(...) __riscv_vundefined_i16mf4(__VA_ARGS__) -#define vundefined_i16mf2(...) __riscv_vundefined_i16mf2(__VA_ARGS__) -#define vundefined_i16m1(...) __riscv_vundefined_i16m1(__VA_ARGS__) -#define vundefined_i16m2(...) __riscv_vundefined_i16m2(__VA_ARGS__) -#define vundefined_i16m4(...) __riscv_vundefined_i16m4(__VA_ARGS__) -#define vundefined_i16m8(...) __riscv_vundefined_i16m8(__VA_ARGS__) -#define vundefined_i32mf2(...) __riscv_vundefined_i32mf2(__VA_ARGS__) -#define vundefined_i32m1(...) __riscv_vundefined_i32m1(__VA_ARGS__) -#define vundefined_i32m2(...) __riscv_vundefined_i32m2(__VA_ARGS__) -#define vundefined_i32m4(...) __riscv_vundefined_i32m4(__VA_ARGS__) -#define vundefined_i32m8(...) __riscv_vundefined_i32m8(__VA_ARGS__) -#define vundefined_i64m1(...) __riscv_vundefined_i64m1(__VA_ARGS__) -#define vundefined_i64m2(...) __riscv_vundefined_i64m2(__VA_ARGS__) -#define vundefined_i64m4(...) __riscv_vundefined_i64m4(__VA_ARGS__) -#define vundefined_i64m8(...) __riscv_vundefined_i64m8(__VA_ARGS__) -#define vundefined_u8mf8(...) __riscv_vundefined_u8mf8(__VA_ARGS__) -#define vundefined_u8mf4(...) __riscv_vundefined_u8mf4(__VA_ARGS__) -#define vundefined_u8mf2(...) __riscv_vundefined_u8mf2(__VA_ARGS__) -#define vundefined_u8m1(...) __riscv_vundefined_u8m1(__VA_ARGS__) -#define vundefined_u8m2(...) __riscv_vundefined_u8m2(__VA_ARGS__) -#define vundefined_u8m4(...) __riscv_vundefined_u8m4(__VA_ARGS__) -#define vundefined_u8m8(...) __riscv_vundefined_u8m8(__VA_ARGS__) -#define vundefined_u16mf4(...) __riscv_vundefined_u16mf4(__VA_ARGS__) -#define vundefined_u16mf2(...) __riscv_vundefined_u16mf2(__VA_ARGS__) -#define vundefined_u16m1(...) __riscv_vundefined_u16m1(__VA_ARGS__) -#define vundefined_u16m2(...) __riscv_vundefined_u16m2(__VA_ARGS__) -#define vundefined_u16m4(...) __riscv_vundefined_u16m4(__VA_ARGS__) -#define vundefined_u16m8(...) __riscv_vundefined_u16m8(__VA_ARGS__) -#define vundefined_u32mf2(...) __riscv_vundefined_u32mf2(__VA_ARGS__) -#define vundefined_u32m1(...) __riscv_vundefined_u32m1(__VA_ARGS__) -#define vundefined_u32m2(...) __riscv_vundefined_u32m2(__VA_ARGS__) -#define vundefined_u32m4(...) __riscv_vundefined_u32m4(__VA_ARGS__) -#define vundefined_u32m8(...) __riscv_vundefined_u32m8(__VA_ARGS__) -#define vundefined_u64m1(...) __riscv_vundefined_u64m1(__VA_ARGS__) -#define vundefined_u64m2(...) __riscv_vundefined_u64m2(__VA_ARGS__) -#define vundefined_u64m4(...) __riscv_vundefined_u64m4(__VA_ARGS__) -#define vundefined_u64m8(...) __riscv_vundefined_u64m8(__VA_ARGS__) -#define vset_v_f16m1_f16m2(...) __riscv_vset_v_f16m1_f16m2(__VA_ARGS__) -#define vset_v_f16m1_f16m4(...) __riscv_vset_v_f16m1_f16m4(__VA_ARGS__) -#define vset_v_f16m2_f16m4(...) __riscv_vset_v_f16m2_f16m4(__VA_ARGS__) -#define vset_v_f16m1_f16m8(...) __riscv_vset_v_f16m1_f16m8(__VA_ARGS__) -#define vset_v_f16m2_f16m8(...) __riscv_vset_v_f16m2_f16m8(__VA_ARGS__) -#define vset_v_f16m4_f16m8(...) __riscv_vset_v_f16m4_f16m8(__VA_ARGS__) -#define vset_v_f32m1_f32m2(...) __riscv_vset_v_f32m1_f32m2(__VA_ARGS__) -#define vset_v_f32m1_f32m4(...) __riscv_vset_v_f32m1_f32m4(__VA_ARGS__) -#define vset_v_f32m2_f32m4(...) __riscv_vset_v_f32m2_f32m4(__VA_ARGS__) -#define vset_v_f32m1_f32m8(...) __riscv_vset_v_f32m1_f32m8(__VA_ARGS__) -#define vset_v_f32m2_f32m8(...) __riscv_vset_v_f32m2_f32m8(__VA_ARGS__) -#define vset_v_f32m4_f32m8(...) __riscv_vset_v_f32m4_f32m8(__VA_ARGS__) -#define vset_v_f64m1_f64m2(...) __riscv_vset_v_f64m1_f64m2(__VA_ARGS__) -#define vset_v_f64m1_f64m4(...) __riscv_vset_v_f64m1_f64m4(__VA_ARGS__) -#define vset_v_f64m2_f64m4(...) __riscv_vset_v_f64m2_f64m4(__VA_ARGS__) -#define vset_v_f64m1_f64m8(...) __riscv_vset_v_f64m1_f64m8(__VA_ARGS__) -#define vset_v_f64m2_f64m8(...) __riscv_vset_v_f64m2_f64m8(__VA_ARGS__) -#define vset_v_f64m4_f64m8(...) __riscv_vset_v_f64m4_f64m8(__VA_ARGS__) -#define vset_v_i8m1_i8m2(...) __riscv_vset_v_i8m1_i8m2(__VA_ARGS__) -#define vset_v_i8m1_i8m4(...) __riscv_vset_v_i8m1_i8m4(__VA_ARGS__) -#define vset_v_i8m2_i8m4(...) __riscv_vset_v_i8m2_i8m4(__VA_ARGS__) -#define vset_v_i8m1_i8m8(...) __riscv_vset_v_i8m1_i8m8(__VA_ARGS__) -#define vset_v_i8m2_i8m8(...) __riscv_vset_v_i8m2_i8m8(__VA_ARGS__) -#define vset_v_i8m4_i8m8(...) __riscv_vset_v_i8m4_i8m8(__VA_ARGS__) -#define vset_v_i16m1_i16m2(...) __riscv_vset_v_i16m1_i16m2(__VA_ARGS__) -#define vset_v_i16m1_i16m4(...) __riscv_vset_v_i16m1_i16m4(__VA_ARGS__) -#define vset_v_i16m2_i16m4(...) __riscv_vset_v_i16m2_i16m4(__VA_ARGS__) -#define vset_v_i16m1_i16m8(...) __riscv_vset_v_i16m1_i16m8(__VA_ARGS__) -#define vset_v_i16m2_i16m8(...) __riscv_vset_v_i16m2_i16m8(__VA_ARGS__) -#define vset_v_i16m4_i16m8(...) __riscv_vset_v_i16m4_i16m8(__VA_ARGS__) -#define vset_v_i32m1_i32m2(...) __riscv_vset_v_i32m1_i32m2(__VA_ARGS__) -#define vset_v_i32m1_i32m4(...) __riscv_vset_v_i32m1_i32m4(__VA_ARGS__) -#define vset_v_i32m2_i32m4(...) __riscv_vset_v_i32m2_i32m4(__VA_ARGS__) -#define vset_v_i32m1_i32m8(...) __riscv_vset_v_i32m1_i32m8(__VA_ARGS__) -#define vset_v_i32m2_i32m8(...) __riscv_vset_v_i32m2_i32m8(__VA_ARGS__) -#define vset_v_i32m4_i32m8(...) __riscv_vset_v_i32m4_i32m8(__VA_ARGS__) -#define vset_v_i64m1_i64m2(...) __riscv_vset_v_i64m1_i64m2(__VA_ARGS__) -#define vset_v_i64m1_i64m4(...) __riscv_vset_v_i64m1_i64m4(__VA_ARGS__) -#define vset_v_i64m2_i64m4(...) __riscv_vset_v_i64m2_i64m4(__VA_ARGS__) -#define vset_v_i64m1_i64m8(...) __riscv_vset_v_i64m1_i64m8(__VA_ARGS__) -#define vset_v_i64m2_i64m8(...) __riscv_vset_v_i64m2_i64m8(__VA_ARGS__) -#define vset_v_i64m4_i64m8(...) __riscv_vset_v_i64m4_i64m8(__VA_ARGS__) -#define vset_v_u8m1_u8m2(...) __riscv_vset_v_u8m1_u8m2(__VA_ARGS__) -#define vset_v_u8m1_u8m4(...) __riscv_vset_v_u8m1_u8m4(__VA_ARGS__) -#define vset_v_u8m2_u8m4(...) __riscv_vset_v_u8m2_u8m4(__VA_ARGS__) -#define vset_v_u8m1_u8m8(...) __riscv_vset_v_u8m1_u8m8(__VA_ARGS__) -#define vset_v_u8m2_u8m8(...) __riscv_vset_v_u8m2_u8m8(__VA_ARGS__) -#define vset_v_u8m4_u8m8(...) __riscv_vset_v_u8m4_u8m8(__VA_ARGS__) -#define vset_v_u16m1_u16m2(...) __riscv_vset_v_u16m1_u16m2(__VA_ARGS__) -#define vset_v_u16m1_u16m4(...) __riscv_vset_v_u16m1_u16m4(__VA_ARGS__) -#define vset_v_u16m2_u16m4(...) __riscv_vset_v_u16m2_u16m4(__VA_ARGS__) -#define vset_v_u16m1_u16m8(...) __riscv_vset_v_u16m1_u16m8(__VA_ARGS__) -#define vset_v_u16m2_u16m8(...) __riscv_vset_v_u16m2_u16m8(__VA_ARGS__) -#define vset_v_u16m4_u16m8(...) __riscv_vset_v_u16m4_u16m8(__VA_ARGS__) -#define vset_v_u32m1_u32m2(...) __riscv_vset_v_u32m1_u32m2(__VA_ARGS__) -#define vset_v_u32m1_u32m4(...) __riscv_vset_v_u32m1_u32m4(__VA_ARGS__) -#define vset_v_u32m2_u32m4(...) __riscv_vset_v_u32m2_u32m4(__VA_ARGS__) -#define vset_v_u32m1_u32m8(...) __riscv_vset_v_u32m1_u32m8(__VA_ARGS__) -#define vset_v_u32m2_u32m8(...) __riscv_vset_v_u32m2_u32m8(__VA_ARGS__) -#define vset_v_u32m4_u32m8(...) __riscv_vset_v_u32m4_u32m8(__VA_ARGS__) -#define vset_v_u64m1_u64m2(...) __riscv_vset_v_u64m1_u64m2(__VA_ARGS__) -#define vset_v_u64m1_u64m4(...) __riscv_vset_v_u64m1_u64m4(__VA_ARGS__) -#define vset_v_u64m2_u64m4(...) __riscv_vset_v_u64m2_u64m4(__VA_ARGS__) -#define vset_v_u64m1_u64m8(...) __riscv_vset_v_u64m1_u64m8(__VA_ARGS__) -#define vset_v_u64m2_u64m8(...) __riscv_vset_v_u64m2_u64m8(__VA_ARGS__) -#define vset_v_u64m4_u64m8(...) __riscv_vset_v_u64m4_u64m8(__VA_ARGS__) -#define vget_v_f16m2_f16m1(...) __riscv_vget_v_f16m2_f16m1(__VA_ARGS__) -#define vget_v_f16m4_f16m1(...) __riscv_vget_v_f16m4_f16m1(__VA_ARGS__) -#define vget_v_f16m8_f16m1(...) __riscv_vget_v_f16m8_f16m1(__VA_ARGS__) -#define vget_v_f16m4_f16m2(...) __riscv_vget_v_f16m4_f16m2(__VA_ARGS__) -#define vget_v_f16m8_f16m2(...) __riscv_vget_v_f16m8_f16m2(__VA_ARGS__) -#define vget_v_f16m8_f16m4(...) __riscv_vget_v_f16m8_f16m4(__VA_ARGS__) -#define vget_v_f32m2_f32m1(...) __riscv_vget_v_f32m2_f32m1(__VA_ARGS__) -#define vget_v_f32m4_f32m1(...) __riscv_vget_v_f32m4_f32m1(__VA_ARGS__) -#define vget_v_f32m8_f32m1(...) __riscv_vget_v_f32m8_f32m1(__VA_ARGS__) -#define vget_v_f32m4_f32m2(...) __riscv_vget_v_f32m4_f32m2(__VA_ARGS__) -#define vget_v_f32m8_f32m2(...) __riscv_vget_v_f32m8_f32m2(__VA_ARGS__) -#define vget_v_f32m8_f32m4(...) __riscv_vget_v_f32m8_f32m4(__VA_ARGS__) -#define vget_v_f64m2_f64m1(...) __riscv_vget_v_f64m2_f64m1(__VA_ARGS__) -#define vget_v_f64m4_f64m1(...) __riscv_vget_v_f64m4_f64m1(__VA_ARGS__) -#define vget_v_f64m8_f64m1(...) __riscv_vget_v_f64m8_f64m1(__VA_ARGS__) -#define vget_v_f64m4_f64m2(...) __riscv_vget_v_f64m4_f64m2(__VA_ARGS__) -#define vget_v_f64m8_f64m2(...) __riscv_vget_v_f64m8_f64m2(__VA_ARGS__) -#define vget_v_f64m8_f64m4(...) __riscv_vget_v_f64m8_f64m4(__VA_ARGS__) -#define vget_v_i8m2_i8m1(...) __riscv_vget_v_i8m2_i8m1(__VA_ARGS__) -#define vget_v_i8m4_i8m1(...) __riscv_vget_v_i8m4_i8m1(__VA_ARGS__) -#define vget_v_i8m8_i8m1(...) __riscv_vget_v_i8m8_i8m1(__VA_ARGS__) -#define vget_v_i8m4_i8m2(...) __riscv_vget_v_i8m4_i8m2(__VA_ARGS__) -#define vget_v_i8m8_i8m2(...) __riscv_vget_v_i8m8_i8m2(__VA_ARGS__) -#define vget_v_i8m8_i8m4(...) __riscv_vget_v_i8m8_i8m4(__VA_ARGS__) -#define vget_v_i16m2_i16m1(...) __riscv_vget_v_i16m2_i16m1(__VA_ARGS__) -#define vget_v_i16m4_i16m1(...) __riscv_vget_v_i16m4_i16m1(__VA_ARGS__) -#define vget_v_i16m8_i16m1(...) __riscv_vget_v_i16m8_i16m1(__VA_ARGS__) -#define vget_v_i16m4_i16m2(...) __riscv_vget_v_i16m4_i16m2(__VA_ARGS__) -#define vget_v_i16m8_i16m2(...) __riscv_vget_v_i16m8_i16m2(__VA_ARGS__) -#define vget_v_i16m8_i16m4(...) __riscv_vget_v_i16m8_i16m4(__VA_ARGS__) -#define vget_v_i32m2_i32m1(...) __riscv_vget_v_i32m2_i32m1(__VA_ARGS__) -#define vget_v_i32m4_i32m1(...) __riscv_vget_v_i32m4_i32m1(__VA_ARGS__) -#define vget_v_i32m8_i32m1(...) __riscv_vget_v_i32m8_i32m1(__VA_ARGS__) -#define vget_v_i32m4_i32m2(...) __riscv_vget_v_i32m4_i32m2(__VA_ARGS__) -#define vget_v_i32m8_i32m2(...) __riscv_vget_v_i32m8_i32m2(__VA_ARGS__) -#define vget_v_i32m8_i32m4(...) __riscv_vget_v_i32m8_i32m4(__VA_ARGS__) -#define vget_v_i64m2_i64m1(...) __riscv_vget_v_i64m2_i64m1(__VA_ARGS__) -#define vget_v_i64m4_i64m1(...) __riscv_vget_v_i64m4_i64m1(__VA_ARGS__) -#define vget_v_i64m8_i64m1(...) __riscv_vget_v_i64m8_i64m1(__VA_ARGS__) -#define vget_v_i64m4_i64m2(...) __riscv_vget_v_i64m4_i64m2(__VA_ARGS__) -#define vget_v_i64m8_i64m2(...) __riscv_vget_v_i64m8_i64m2(__VA_ARGS__) -#define vget_v_i64m8_i64m4(...) __riscv_vget_v_i64m8_i64m4(__VA_ARGS__) -#define vget_v_u8m2_u8m1(...) __riscv_vget_v_u8m2_u8m1(__VA_ARGS__) -#define vget_v_u8m4_u8m1(...) __riscv_vget_v_u8m4_u8m1(__VA_ARGS__) -#define vget_v_u8m8_u8m1(...) __riscv_vget_v_u8m8_u8m1(__VA_ARGS__) -#define vget_v_u8m4_u8m2(...) __riscv_vget_v_u8m4_u8m2(__VA_ARGS__) -#define vget_v_u8m8_u8m2(...) __riscv_vget_v_u8m8_u8m2(__VA_ARGS__) -#define vget_v_u8m8_u8m4(...) __riscv_vget_v_u8m8_u8m4(__VA_ARGS__) -#define vget_v_u16m2_u16m1(...) __riscv_vget_v_u16m2_u16m1(__VA_ARGS__) -#define vget_v_u16m4_u16m1(...) __riscv_vget_v_u16m4_u16m1(__VA_ARGS__) -#define vget_v_u16m8_u16m1(...) __riscv_vget_v_u16m8_u16m1(__VA_ARGS__) -#define vget_v_u16m4_u16m2(...) __riscv_vget_v_u16m4_u16m2(__VA_ARGS__) -#define vget_v_u16m8_u16m2(...) __riscv_vget_v_u16m8_u16m2(__VA_ARGS__) -#define vget_v_u16m8_u16m4(...) __riscv_vget_v_u16m8_u16m4(__VA_ARGS__) -#define vget_v_u32m2_u32m1(...) __riscv_vget_v_u32m2_u32m1(__VA_ARGS__) -#define vget_v_u32m4_u32m1(...) __riscv_vget_v_u32m4_u32m1(__VA_ARGS__) -#define vget_v_u32m8_u32m1(...) __riscv_vget_v_u32m8_u32m1(__VA_ARGS__) -#define vget_v_u32m4_u32m2(...) __riscv_vget_v_u32m4_u32m2(__VA_ARGS__) -#define vget_v_u32m8_u32m2(...) __riscv_vget_v_u32m8_u32m2(__VA_ARGS__) -#define vget_v_u32m8_u32m4(...) __riscv_vget_v_u32m8_u32m4(__VA_ARGS__) -#define vget_v_u64m2_u64m1(...) __riscv_vget_v_u64m2_u64m1(__VA_ARGS__) -#define vget_v_u64m4_u64m1(...) __riscv_vget_v_u64m4_u64m1(__VA_ARGS__) -#define vget_v_u64m8_u64m1(...) __riscv_vget_v_u64m8_u64m1(__VA_ARGS__) -#define vget_v_u64m4_u64m2(...) __riscv_vget_v_u64m4_u64m2(__VA_ARGS__) -#define vget_v_u64m8_u64m2(...) __riscv_vget_v_u64m8_u64m2(__VA_ARGS__) -#define vget_v_u64m8_u64m4(...) __riscv_vget_v_u64m8_u64m4(__VA_ARGS__) -#endif diff --git a/modules/core/include/opencv2/core/hal/intrin_rvv_010_compat_overloaded-non-policy.hpp b/modules/core/include/opencv2/core/hal/intrin_rvv_010_compat_overloaded-non-policy.hpp deleted file mode 100644 index 12a34d20d4..0000000000 --- a/modules/core/include/opencv2/core/hal/intrin_rvv_010_compat_overloaded-non-policy.hpp +++ /dev/null @@ -1,768 +0,0 @@ -// This file is part of OpenCV project. -// It is subject to the license terms in the LICENSE file found in the top-level directory -// of this distribution and at http://opencv.org/license.html. - -// Copied from -// https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/master/auto-generated/rvv-v0p10-compatible-headers - -#ifndef __RVV_0P10_COMPATIBLE_HEADERS_OVERLOADED_NON_POLICY_H -#define __RVV_0P10_COMPATIBLE_HEADERS_OVERLOADED_NON_POLICY_H - - -// The maximum number of parameters is 20, this is held by segment load -// instructions with a NFIELD (NF) of 8. 20 is contributed by 8 vector register -// pointers passed, 1 vector mask register, 8 passthrough register for -// undisturbed policy, and 3 for address base, byte index, vl. -#define _GET_OVERRIDE(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13,\ -_14, _15, _16, _17, _18, _19, _20, NAME, ...) NAME - - -#if __has_include ("riscv_vector.h") -#include -#endif -#ifndef __RISCV_VECTOR_H -#include_next -#endif - -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -#define vmerge(mask, op1, op2, vl) __riscv_vmerge((op1), (op2), (mask), (vl)) -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -#define vfmerge(mask, op1, op2, vl) __riscv_vfmerge((op1), (op2), (mask), (vl)) -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -// masked functions -#define vcompress(mask, dest, src, vl) __riscv_vcompress_tu((dest), (src), (mask), (vl)) -// Reinterpret between different type under the same SEW/LMUL -// Reinterpret between different SEW under the same LMUL -#define vse16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vse16, __riscv_vse16, 2, 1)(__VA_ARGS__) -#define vse32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vse32, __riscv_vse32, 2, 1)(__VA_ARGS__) -#define vse64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vse64, __riscv_vse64, 2, 1)(__VA_ARGS__) -#define vse8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vse8, __riscv_vse8, 2, 1)(__VA_ARGS__) -#define vsse16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsse16, __riscv_vsse16, 3, 2, 1)(__VA_ARGS__) -#define vsse32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsse32, __riscv_vsse32, 3, 2, 1)(__VA_ARGS__) -#define vsse64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsse64, __riscv_vsse64, 3, 2, 1)(__VA_ARGS__) -#define vsse8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsse8, __riscv_vsse8, 3, 2, 1)(__VA_ARGS__) -#define vloxei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vloxei8_tumu, 4, __riscv_vloxei8, 2, 1)(__VA_ARGS__) -#define vloxei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vloxei16_tumu, 4, __riscv_vloxei16, 2, 1)(__VA_ARGS__) -#define vloxei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vloxei32_tumu, 4, __riscv_vloxei32, 2, 1)(__VA_ARGS__) -#define vloxei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vloxei64_tumu, 4, __riscv_vloxei64, 2, 1)(__VA_ARGS__) -#define vluxei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vluxei8_tumu, 4, __riscv_vluxei8, 2, 1)(__VA_ARGS__) -#define vluxei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vluxei16_tumu, 4, __riscv_vluxei16, 2, 1)(__VA_ARGS__) -#define vluxei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vluxei32_tumu, 4, __riscv_vluxei32, 2, 1)(__VA_ARGS__) -#define vluxei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vluxei64_tumu, 4, __riscv_vluxei64, 2, 1)(__VA_ARGS__) -#define vsoxei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsoxei8, __riscv_vsoxei8, 3, 2, 1)(__VA_ARGS__) -#define vsoxei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsoxei16, __riscv_vsoxei16, 3, 2, 1)(__VA_ARGS__) -#define vsoxei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsoxei32, __riscv_vsoxei32, 3, 2, 1)(__VA_ARGS__) -#define vsoxei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsoxei64, __riscv_vsoxei64, 3, 2, 1)(__VA_ARGS__) -#define vsuxei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsuxei8, __riscv_vsuxei8, 3, 2, 1)(__VA_ARGS__) -#define vsuxei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsuxei16, __riscv_vsuxei16, 3, 2, 1)(__VA_ARGS__) -#define vsuxei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsuxei32, __riscv_vsuxei32, 3, 2, 1)(__VA_ARGS__) -#define vsuxei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsuxei64, __riscv_vsuxei64, 3, 2, 1)(__VA_ARGS__) -#define vsseg2e16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsseg2e16, __riscv_vsseg2e16, 3, 2, 1)(__VA_ARGS__) -#define vsseg3e16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, __riscv_vsseg3e16, __riscv_vsseg3e16, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg4e16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, __riscv_vsseg4e16, __riscv_vsseg4e16, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg5e16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vsseg5e16, __riscv_vsseg5e16, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg6e16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, __riscv_vsseg6e16, __riscv_vsseg6e16, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg7e16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vsseg7e16, __riscv_vsseg7e16, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg8e16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vsseg8e16, __riscv_vsseg8e16, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg2e32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsseg2e32, __riscv_vsseg2e32, 3, 2, 1)(__VA_ARGS__) -#define vsseg3e32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, __riscv_vsseg3e32, __riscv_vsseg3e32, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg4e32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, __riscv_vsseg4e32, __riscv_vsseg4e32, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg5e32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vsseg5e32, __riscv_vsseg5e32, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg6e32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, __riscv_vsseg6e32, __riscv_vsseg6e32, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg7e32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vsseg7e32, __riscv_vsseg7e32, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg8e32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vsseg8e32, __riscv_vsseg8e32, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg2e64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsseg2e64, __riscv_vsseg2e64, 3, 2, 1)(__VA_ARGS__) -#define vsseg3e64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, __riscv_vsseg3e64, __riscv_vsseg3e64, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg4e64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, __riscv_vsseg4e64, __riscv_vsseg4e64, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg5e64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vsseg5e64, __riscv_vsseg5e64, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg6e64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, __riscv_vsseg6e64, __riscv_vsseg6e64, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg7e64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vsseg7e64, __riscv_vsseg7e64, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg8e64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vsseg8e64, __riscv_vsseg8e64, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg2e8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsseg2e8, __riscv_vsseg2e8, 3, 2, 1)(__VA_ARGS__) -#define vsseg3e8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, __riscv_vsseg3e8, __riscv_vsseg3e8, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg4e8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, __riscv_vsseg4e8, __riscv_vsseg4e8, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg5e8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vsseg5e8, __riscv_vsseg5e8, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg6e8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, __riscv_vsseg6e8, __riscv_vsseg6e8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg7e8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vsseg7e8, __riscv_vsseg7e8, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsseg8e8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vsseg8e8, __riscv_vsseg8e8, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg2e16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, __riscv_vssseg2e16, __riscv_vssseg2e16, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg3e16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, __riscv_vssseg3e16, __riscv_vssseg3e16, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg4e16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vssseg4e16, __riscv_vssseg4e16, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg5e16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, __riscv_vssseg5e16, __riscv_vssseg5e16, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg6e16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vssseg6e16, __riscv_vssseg6e16, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg7e16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vssseg7e16, __riscv_vssseg7e16, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg8e16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vssseg8e16, __riscv_vssseg8e16, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg2e32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, __riscv_vssseg2e32, __riscv_vssseg2e32, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg3e32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, __riscv_vssseg3e32, __riscv_vssseg3e32, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg4e32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vssseg4e32, __riscv_vssseg4e32, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg5e32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, __riscv_vssseg5e32, __riscv_vssseg5e32, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg6e32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vssseg6e32, __riscv_vssseg6e32, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg7e32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vssseg7e32, __riscv_vssseg7e32, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg8e32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vssseg8e32, __riscv_vssseg8e32, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg2e64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, __riscv_vssseg2e64, __riscv_vssseg2e64, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg3e64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, __riscv_vssseg3e64, __riscv_vssseg3e64, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg4e64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vssseg4e64, __riscv_vssseg4e64, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg5e64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, __riscv_vssseg5e64, __riscv_vssseg5e64, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg6e64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vssseg6e64, __riscv_vssseg6e64, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg7e64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vssseg7e64, __riscv_vssseg7e64, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg8e64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vssseg8e64, __riscv_vssseg8e64, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg2e8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, __riscv_vssseg2e8, __riscv_vssseg2e8, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg3e8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, __riscv_vssseg3e8, __riscv_vssseg3e8, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg4e8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vssseg4e8, __riscv_vssseg4e8, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg5e8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, __riscv_vssseg5e8, __riscv_vssseg5e8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg6e8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vssseg6e8, __riscv_vssseg6e8, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg7e8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vssseg7e8, __riscv_vssseg7e8, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vssseg8e8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vssseg8e8, __riscv_vssseg8e8, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg2ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vloxseg2ei8_tumu, 7, 6, __riscv_vloxseg2ei8, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg3ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vloxseg3ei8_tumu, 9, 8, 7, __riscv_vloxseg3ei8, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg4ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vloxseg4ei8_tumu, 11, 10, 9, 8, __riscv_vloxseg4ei8, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg5ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, __riscv_vloxseg5ei8_tumu, 13, 12, 11, 10, 9, __riscv_vloxseg5ei8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg6ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, __riscv_vloxseg6ei8_tumu, 15, 14, 13, 12, 11, 10, __riscv_vloxseg6ei8, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg7ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, __riscv_vloxseg7ei8_tumu, 17, 16, 15, 14, 13, 12, 11, __riscv_vloxseg7ei8, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg8ei8(...) _GET_OVERRIDE(__VA_ARGS__, __riscv_vloxseg8ei8_tumu, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vloxseg8ei8, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg2ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vloxseg2ei16_tumu, 7, 6, __riscv_vloxseg2ei16, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg3ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vloxseg3ei16_tumu, 9, 8, 7, __riscv_vloxseg3ei16, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg4ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vloxseg4ei16_tumu, 11, 10, 9, 8, __riscv_vloxseg4ei16, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg5ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, __riscv_vloxseg5ei16_tumu, 13, 12, 11, 10, 9, __riscv_vloxseg5ei16, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg6ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, __riscv_vloxseg6ei16_tumu, 15, 14, 13, 12, 11, 10, __riscv_vloxseg6ei16, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg7ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, __riscv_vloxseg7ei16_tumu, 17, 16, 15, 14, 13, 12, 11, __riscv_vloxseg7ei16, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg8ei16(...) _GET_OVERRIDE(__VA_ARGS__, __riscv_vloxseg8ei16_tumu, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vloxseg8ei16, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg2ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vloxseg2ei32_tumu, 7, 6, __riscv_vloxseg2ei32, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg3ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vloxseg3ei32_tumu, 9, 8, 7, __riscv_vloxseg3ei32, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg4ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vloxseg4ei32_tumu, 11, 10, 9, 8, __riscv_vloxseg4ei32, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg5ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, __riscv_vloxseg5ei32_tumu, 13, 12, 11, 10, 9, __riscv_vloxseg5ei32, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg6ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, __riscv_vloxseg6ei32_tumu, 15, 14, 13, 12, 11, 10, __riscv_vloxseg6ei32, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg7ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, __riscv_vloxseg7ei32_tumu, 17, 16, 15, 14, 13, 12, 11, __riscv_vloxseg7ei32, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg8ei32(...) _GET_OVERRIDE(__VA_ARGS__, __riscv_vloxseg8ei32_tumu, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vloxseg8ei32, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg2ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vloxseg2ei64_tumu, 7, 6, __riscv_vloxseg2ei64, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg3ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vloxseg3ei64_tumu, 9, 8, 7, __riscv_vloxseg3ei64, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg4ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vloxseg4ei64_tumu, 11, 10, 9, 8, __riscv_vloxseg4ei64, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg5ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, __riscv_vloxseg5ei64_tumu, 13, 12, 11, 10, 9, __riscv_vloxseg5ei64, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg6ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, __riscv_vloxseg6ei64_tumu, 15, 14, 13, 12, 11, 10, __riscv_vloxseg6ei64, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg7ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, __riscv_vloxseg7ei64_tumu, 17, 16, 15, 14, 13, 12, 11, __riscv_vloxseg7ei64, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vloxseg8ei64(...) _GET_OVERRIDE(__VA_ARGS__, __riscv_vloxseg8ei64_tumu, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vloxseg8ei64, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg2ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vluxseg2ei8_tumu, 7, 6, __riscv_vluxseg2ei8, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg3ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vluxseg3ei8_tumu, 9, 8, 7, __riscv_vluxseg3ei8, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg4ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vluxseg4ei8_tumu, 11, 10, 9, 8, __riscv_vluxseg4ei8, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg5ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, __riscv_vluxseg5ei8_tumu, 13, 12, 11, 10, 9, __riscv_vluxseg5ei8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg6ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, __riscv_vluxseg6ei8_tumu, 15, 14, 13, 12, 11, 10, __riscv_vluxseg6ei8, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg7ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, __riscv_vluxseg7ei8_tumu, 17, 16, 15, 14, 13, 12, 11, __riscv_vluxseg7ei8, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg8ei8(...) _GET_OVERRIDE(__VA_ARGS__, __riscv_vluxseg8ei8_tumu, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vluxseg8ei8, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg2ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vluxseg2ei16_tumu, 7, 6, __riscv_vluxseg2ei16, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg3ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vluxseg3ei16_tumu, 9, 8, 7, __riscv_vluxseg3ei16, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg4ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vluxseg4ei16_tumu, 11, 10, 9, 8, __riscv_vluxseg4ei16, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg5ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, __riscv_vluxseg5ei16_tumu, 13, 12, 11, 10, 9, __riscv_vluxseg5ei16, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg6ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, __riscv_vluxseg6ei16_tumu, 15, 14, 13, 12, 11, 10, __riscv_vluxseg6ei16, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg7ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, __riscv_vluxseg7ei16_tumu, 17, 16, 15, 14, 13, 12, 11, __riscv_vluxseg7ei16, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg8ei16(...) _GET_OVERRIDE(__VA_ARGS__, __riscv_vluxseg8ei16_tumu, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vluxseg8ei16, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg2ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vluxseg2ei32_tumu, 7, 6, __riscv_vluxseg2ei32, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg3ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vluxseg3ei32_tumu, 9, 8, 7, __riscv_vluxseg3ei32, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg4ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vluxseg4ei32_tumu, 11, 10, 9, 8, __riscv_vluxseg4ei32, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg5ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, __riscv_vluxseg5ei32_tumu, 13, 12, 11, 10, 9, __riscv_vluxseg5ei32, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg6ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, __riscv_vluxseg6ei32_tumu, 15, 14, 13, 12, 11, 10, __riscv_vluxseg6ei32, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg7ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, __riscv_vluxseg7ei32_tumu, 17, 16, 15, 14, 13, 12, 11, __riscv_vluxseg7ei32, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg8ei32(...) _GET_OVERRIDE(__VA_ARGS__, __riscv_vluxseg8ei32_tumu, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vluxseg8ei32, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg2ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vluxseg2ei64_tumu, 7, 6, __riscv_vluxseg2ei64, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg3ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vluxseg3ei64_tumu, 9, 8, 7, __riscv_vluxseg3ei64, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg4ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vluxseg4ei64_tumu, 11, 10, 9, 8, __riscv_vluxseg4ei64, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg5ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, __riscv_vluxseg5ei64_tumu, 13, 12, 11, 10, 9, __riscv_vluxseg5ei64, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg6ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, __riscv_vluxseg6ei64_tumu, 15, 14, 13, 12, 11, 10, __riscv_vluxseg6ei64, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg7ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, __riscv_vluxseg7ei64_tumu, 17, 16, 15, 14, 13, 12, 11, __riscv_vluxseg7ei64, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vluxseg8ei64(...) _GET_OVERRIDE(__VA_ARGS__, __riscv_vluxseg8ei64_tumu, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vluxseg8ei64, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg2ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, __riscv_vsoxseg2ei8, __riscv_vsoxseg2ei8, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg3ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, __riscv_vsoxseg3ei8, __riscv_vsoxseg3ei8, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg4ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vsoxseg4ei8, __riscv_vsoxseg4ei8, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg5ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, __riscv_vsoxseg5ei8, __riscv_vsoxseg5ei8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg6ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vsoxseg6ei8, __riscv_vsoxseg6ei8, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg7ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vsoxseg7ei8, __riscv_vsoxseg7ei8, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg8ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vsoxseg8ei8, __riscv_vsoxseg8ei8, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg2ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, __riscv_vsoxseg2ei16, __riscv_vsoxseg2ei16, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg3ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, __riscv_vsoxseg3ei16, __riscv_vsoxseg3ei16, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg4ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vsoxseg4ei16, __riscv_vsoxseg4ei16, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg5ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, __riscv_vsoxseg5ei16, __riscv_vsoxseg5ei16, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg6ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vsoxseg6ei16, __riscv_vsoxseg6ei16, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg7ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vsoxseg7ei16, __riscv_vsoxseg7ei16, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg8ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vsoxseg8ei16, __riscv_vsoxseg8ei16, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg2ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, __riscv_vsoxseg2ei32, __riscv_vsoxseg2ei32, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg3ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, __riscv_vsoxseg3ei32, __riscv_vsoxseg3ei32, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg4ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vsoxseg4ei32, __riscv_vsoxseg4ei32, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg5ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, __riscv_vsoxseg5ei32, __riscv_vsoxseg5ei32, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg6ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vsoxseg6ei32, __riscv_vsoxseg6ei32, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg7ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vsoxseg7ei32, __riscv_vsoxseg7ei32, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg8ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vsoxseg8ei32, __riscv_vsoxseg8ei32, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg2ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, __riscv_vsoxseg2ei64, __riscv_vsoxseg2ei64, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg3ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, __riscv_vsoxseg3ei64, __riscv_vsoxseg3ei64, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg4ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vsoxseg4ei64, __riscv_vsoxseg4ei64, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg5ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, __riscv_vsoxseg5ei64, __riscv_vsoxseg5ei64, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg6ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vsoxseg6ei64, __riscv_vsoxseg6ei64, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg7ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vsoxseg7ei64, __riscv_vsoxseg7ei64, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsoxseg8ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vsoxseg8ei64, __riscv_vsoxseg8ei64, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg2ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, __riscv_vsuxseg2ei8, __riscv_vsuxseg2ei8, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg3ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, __riscv_vsuxseg3ei8, __riscv_vsuxseg3ei8, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg4ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vsuxseg4ei8, __riscv_vsuxseg4ei8, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg5ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, __riscv_vsuxseg5ei8, __riscv_vsuxseg5ei8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg6ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vsuxseg6ei8, __riscv_vsuxseg6ei8, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg7ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vsuxseg7ei8, __riscv_vsuxseg7ei8, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg8ei8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vsuxseg8ei8, __riscv_vsuxseg8ei8, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg2ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, __riscv_vsuxseg2ei16, __riscv_vsuxseg2ei16, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg3ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, __riscv_vsuxseg3ei16, __riscv_vsuxseg3ei16, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg4ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vsuxseg4ei16, __riscv_vsuxseg4ei16, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg5ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, __riscv_vsuxseg5ei16, __riscv_vsuxseg5ei16, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg6ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vsuxseg6ei16, __riscv_vsuxseg6ei16, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg7ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vsuxseg7ei16, __riscv_vsuxseg7ei16, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg8ei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vsuxseg8ei16, __riscv_vsuxseg8ei16, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg2ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, __riscv_vsuxseg2ei32, __riscv_vsuxseg2ei32, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg3ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, __riscv_vsuxseg3ei32, __riscv_vsuxseg3ei32, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg4ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vsuxseg4ei32, __riscv_vsuxseg4ei32, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg5ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, __riscv_vsuxseg5ei32, __riscv_vsuxseg5ei32, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg6ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vsuxseg6ei32, __riscv_vsuxseg6ei32, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg7ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vsuxseg7ei32, __riscv_vsuxseg7ei32, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg8ei32(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vsuxseg8ei32, __riscv_vsuxseg8ei32, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg2ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, __riscv_vsuxseg2ei64, __riscv_vsuxseg2ei64, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg3ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, __riscv_vsuxseg3ei64, __riscv_vsuxseg3ei64, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg4ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, __riscv_vsuxseg4ei64, __riscv_vsuxseg4ei64, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg5ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, __riscv_vsuxseg5ei64, __riscv_vsuxseg5ei64, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg6ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, __riscv_vsuxseg6ei64, __riscv_vsuxseg6ei64, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg7ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, __riscv_vsuxseg7ei64, __riscv_vsuxseg7ei64, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vsuxseg8ei64(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, __riscv_vsuxseg8ei64, __riscv_vsuxseg8ei64, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)(__VA_ARGS__) -#define vadd(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vadd_tumu, 4, __riscv_vadd, 2, 1)(__VA_ARGS__) -#define vsub(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsub_tumu, 4, __riscv_vsub, 2, 1)(__VA_ARGS__) -#define vrsub(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vrsub_tumu, 4, __riscv_vrsub, 2, 1)(__VA_ARGS__) -#define vneg(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vneg_tumu, 3, __riscv_vneg, 1)(__VA_ARGS__) -#define vwadd_vv(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwadd_vv_tumu, 4, __riscv_vwadd_vv, 2, 1)(__VA_ARGS__) -#define vwadd_vx(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwadd_vx_tumu, 4, __riscv_vwadd_vx, 2, 1)(__VA_ARGS__) -#define vwadd_wv(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwadd_wv_tumu, 4, __riscv_vwadd_wv, 2, 1)(__VA_ARGS__) -#define vwadd_wx(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwadd_wx_tumu, 4, __riscv_vwadd_wx, 2, 1)(__VA_ARGS__) -#define vwsub_vv(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwsub_vv_tumu, 4, __riscv_vwsub_vv, 2, 1)(__VA_ARGS__) -#define vwsub_vx(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwsub_vx_tumu, 4, __riscv_vwsub_vx, 2, 1)(__VA_ARGS__) -#define vwsub_wv(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwsub_wv_tumu, 4, __riscv_vwsub_wv, 2, 1)(__VA_ARGS__) -#define vwsub_wx(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwsub_wx_tumu, 4, __riscv_vwsub_wx, 2, 1)(__VA_ARGS__) -#define vwaddu_vv(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwaddu_vv_tumu, 4, __riscv_vwaddu_vv, 2, 1)(__VA_ARGS__) -#define vwaddu_vx(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwaddu_vx_tumu, 4, __riscv_vwaddu_vx, 2, 1)(__VA_ARGS__) -#define vwaddu_wv(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwaddu_wv_tumu, 4, __riscv_vwaddu_wv, 2, 1)(__VA_ARGS__) -#define vwaddu_wx(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwaddu_wx_tumu, 4, __riscv_vwaddu_wx, 2, 1)(__VA_ARGS__) -#define vwsubu_vv(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwsubu_vv_tumu, 4, __riscv_vwsubu_vv, 2, 1)(__VA_ARGS__) -#define vwsubu_vx(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwsubu_vx_tumu, 4, __riscv_vwsubu_vx, 2, 1)(__VA_ARGS__) -#define vwsubu_wv(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwsubu_wv_tumu, 4, __riscv_vwsubu_wv, 2, 1)(__VA_ARGS__) -#define vwsubu_wx(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwsubu_wx_tumu, 4, __riscv_vwsubu_wx, 2, 1)(__VA_ARGS__) -#define vsext_vf2(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vsext_vf2_tumu, 3, __riscv_vsext_vf2, 1)(__VA_ARGS__) -#define vsext_vf4(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vsext_vf4_tumu, 3, __riscv_vsext_vf4, 1)(__VA_ARGS__) -#define vsext_vf8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vsext_vf8_tumu, 3, __riscv_vsext_vf8, 1)(__VA_ARGS__) -#define vzext_vf2(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vzext_vf2_tumu, 3, __riscv_vzext_vf2, 1)(__VA_ARGS__) -#define vzext_vf4(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vzext_vf4_tumu, 3, __riscv_vzext_vf4, 1)(__VA_ARGS__) -#define vzext_vf8(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vzext_vf8_tumu, 3, __riscv_vzext_vf8, 1)(__VA_ARGS__) -#define vadc(...) __riscv_vadc(__VA_ARGS__) -#define vsbc(...) __riscv_vsbc(__VA_ARGS__) -#define vmadc(...) __riscv_vmadc(__VA_ARGS__) -#define vmsbc(...) __riscv_vmsbc(__VA_ARGS__) -#define vand(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vand_tumu, 4, __riscv_vand, 2, 1)(__VA_ARGS__) -#define vor(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vor_tumu, 4, __riscv_vor, 2, 1)(__VA_ARGS__) -#define vxor(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vxor_tumu, 4, __riscv_vxor, 2, 1)(__VA_ARGS__) -#define vnot(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vnot_tumu, 3, __riscv_vnot, 1)(__VA_ARGS__) -#define vsll(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsll_tumu, 4, __riscv_vsll, 2, 1)(__VA_ARGS__) -#define vsra(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsra_tumu, 4, __riscv_vsra, 2, 1)(__VA_ARGS__) -#define vsrl(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsrl_tumu, 4, __riscv_vsrl, 2, 1)(__VA_ARGS__) -#define vnsra(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vnsra_tumu, 4, __riscv_vnsra, 2, 1)(__VA_ARGS__) -#define vnsrl(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vnsrl_tumu, 4, __riscv_vnsrl, 2, 1)(__VA_ARGS__) -#define vmseq(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmseq_mu, 4, __riscv_vmseq, 2, 1)(__VA_ARGS__) -#define vmsne(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmsne_mu, 4, __riscv_vmsne, 2, 1)(__VA_ARGS__) -#define vmslt(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmslt_mu, 4, __riscv_vmslt, 2, 1)(__VA_ARGS__) -#define vmsle(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmsle_mu, 4, __riscv_vmsle, 2, 1)(__VA_ARGS__) -#define vmsgt(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmsgt_mu, 4, __riscv_vmsgt, 2, 1)(__VA_ARGS__) -#define vmsge(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmsge_mu, 4, __riscv_vmsge, 2, 1)(__VA_ARGS__) -#define vmsltu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmsltu_mu, 4, __riscv_vmsltu, 2, 1)(__VA_ARGS__) -#define vmsleu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmsleu_mu, 4, __riscv_vmsleu, 2, 1)(__VA_ARGS__) -#define vmsgtu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmsgtu_mu, 4, __riscv_vmsgtu, 2, 1)(__VA_ARGS__) -#define vmsgeu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmsgeu_mu, 4, __riscv_vmsgeu, 2, 1)(__VA_ARGS__) -#define vmin(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmin_tumu, 4, __riscv_vmin, 2, 1)(__VA_ARGS__) -#define vmax(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmax_tumu, 4, __riscv_vmax, 2, 1)(__VA_ARGS__) -#define vminu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vminu_tumu, 4, __riscv_vminu, 2, 1)(__VA_ARGS__) -#define vmaxu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmaxu_tumu, 4, __riscv_vmaxu, 2, 1)(__VA_ARGS__) -#define vmul(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmul_tumu, 4, __riscv_vmul, 2, 1)(__VA_ARGS__) -#define vmulh(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmulh_tumu, 4, __riscv_vmulh, 2, 1)(__VA_ARGS__) -#define vmulhsu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmulhsu_tumu, 4, __riscv_vmulhsu, 2, 1)(__VA_ARGS__) -#define vmulhu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmulhu_tumu, 4, __riscv_vmulhu, 2, 1)(__VA_ARGS__) -#define vdiv(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vdiv_tumu, 4, __riscv_vdiv, 2, 1)(__VA_ARGS__) -#define vrem(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vrem_tumu, 4, __riscv_vrem, 2, 1)(__VA_ARGS__) -#define vdivu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vdivu_tumu, 4, __riscv_vdivu, 2, 1)(__VA_ARGS__) -#define vremu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vremu_tumu, 4, __riscv_vremu, 2, 1)(__VA_ARGS__) -#define vwmul(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwmul_tumu, 4, __riscv_vwmul, 2, 1)(__VA_ARGS__) -#define vwmulsu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwmulsu_tumu, 4, __riscv_vwmulsu, 2, 1)(__VA_ARGS__) -#define vwmulu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwmulu_tumu, 4, __riscv_vwmulu, 2, 1)(__VA_ARGS__) -#define vmacc(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmacc_tumu, __riscv_vmacc_tu, 3, 2, 1)(__VA_ARGS__) -#define vnmsac(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vnmsac_tumu, __riscv_vnmsac_tu, 3, 2, 1)(__VA_ARGS__) -#define vmadd(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmadd_tumu, __riscv_vmadd_tu, 3, 2, 1)(__VA_ARGS__) -#define vnmsub(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vnmsub_tumu, __riscv_vnmsub_tu, 3, 2, 1)(__VA_ARGS__) -#define vwmacc(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwmacc_tumu, __riscv_vwmacc_tu, 3, 2, 1)(__VA_ARGS__) -#define vwmaccsu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwmaccsu_tumu, __riscv_vwmaccsu_tu, 3, 2, 1)(__VA_ARGS__) -#define vwmaccus(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwmaccus_tumu, __riscv_vwmaccus_tu, 3, 2, 1)(__VA_ARGS__) -#define vwmaccu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwmaccu_tumu, __riscv_vwmaccu_tu, 3, 2, 1)(__VA_ARGS__) -#define vmv_v(...) __riscv_vmv_v(__VA_ARGS__) -#define vsadd(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsadd_tumu, 4, __riscv_vsadd, 2, 1)(__VA_ARGS__) -#define vssub(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vssub_tumu, 4, __riscv_vssub, 2, 1)(__VA_ARGS__) -#define vsaddu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsaddu_tumu, 4, __riscv_vsaddu, 2, 1)(__VA_ARGS__) -#define vssubu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vssubu_tumu, 4, __riscv_vssubu, 2, 1)(__VA_ARGS__) -#define vaadd(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vaadd_tumu, 4, __riscv_vaadd, 2, 1)(__VA_ARGS__) -#define vasub(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vasub_tumu, 4, __riscv_vasub, 2, 1)(__VA_ARGS__) -#define vaaddu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vaaddu_tumu, 4, __riscv_vaaddu, 2, 1)(__VA_ARGS__) -#define vasubu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vasubu_tumu, 4, __riscv_vasubu, 2, 1)(__VA_ARGS__) -#define vsmul(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vsmul_mu, 4, __riscv_vsmul, 2, 1)(__VA_ARGS__) -#define vssra(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vssra_tumu, 4, __riscv_vssra, 2, 1)(__VA_ARGS__) -#define vssrl(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vssrl_tumu, 4, __riscv_vssrl, 2, 1)(__VA_ARGS__) -#define vnclip(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vnclip_tumu, 4, __riscv_vnclip, 2, 1)(__VA_ARGS__) -#define vnclipu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vnclipu_tumu, 4, __riscv_vnclipu, 2, 1)(__VA_ARGS__) -#define vfadd(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfadd_tumu, 4, __riscv_vfadd, 2, 1)(__VA_ARGS__) -#define vfsub(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfsub_tumu, 4, __riscv_vfsub, 2, 1)(__VA_ARGS__) -#define vfrsub(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfrsub_tumu, 4, __riscv_vfrsub, 2, 1)(__VA_ARGS__) -#define vfneg(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfneg_tumu, 3, __riscv_vfneg, 1)(__VA_ARGS__) -#define vfwadd_vv(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfwadd_vv_tumu, 4, __riscv_vfwadd_vv, 2, 1)(__VA_ARGS__) -#define vfwadd_vf(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfwadd_vf_tumu, 4, __riscv_vfwadd_vf, 2, 1)(__VA_ARGS__) -#define vfwadd_wv(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfwadd_wv_tumu, 4, __riscv_vfwadd_wv, 2, 1)(__VA_ARGS__) -#define vfwadd_wf(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfwadd_wf_tumu, 4, __riscv_vfwadd_wf, 2, 1)(__VA_ARGS__) -#define vfwsub_vv(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfwsub_vv_tumu, 4, __riscv_vfwsub_vv, 2, 1)(__VA_ARGS__) -#define vfwsub_vf(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfwsub_vf_tumu, 4, __riscv_vfwsub_vf, 2, 1)(__VA_ARGS__) -#define vfwsub_wv(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfwsub_wv_tumu, 4, __riscv_vfwsub_wv, 2, 1)(__VA_ARGS__) -#define vfwsub_wf(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfwsub_wf_tumu, 4, __riscv_vfwsub_wf, 2, 1)(__VA_ARGS__) -#define vfmul(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfmul_tumu, 4, __riscv_vfmul, 2, 1)(__VA_ARGS__) -#define vfdiv(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfdiv_tumu, 4, __riscv_vfdiv, 2, 1)(__VA_ARGS__) -#define vfrdiv(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfrdiv_tumu, 4, __riscv_vfrdiv, 2, 1)(__VA_ARGS__) -#define vfwmul(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfwmul_tumu, 4, __riscv_vfwmul, 2, 1)(__VA_ARGS__) -#define vfmacc(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfmacc_tumu, __riscv_vfmacc_tu, 3, 2, 1)(__VA_ARGS__) -#define vfnmacc(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfnmacc_tumu, __riscv_vfnmacc_tu, 3, 2, 1)(__VA_ARGS__) -#define vfmsac(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfmsac_tumu, __riscv_vfmsac_tu, 3, 2, 1)(__VA_ARGS__) -#define vfnmsac(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfnmsac_tumu, __riscv_vfnmsac_tu, 3, 2, 1)(__VA_ARGS__) -#define vfmadd(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfmadd_tumu, __riscv_vfmadd_tu, 3, 2, 1)(__VA_ARGS__) -#define vfnmadd(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfnmadd_tumu, __riscv_vfnmadd_tu, 3, 2, 1)(__VA_ARGS__) -#define vfmsub(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfmsub_tumu, __riscv_vfmsub_tu, 3, 2, 1)(__VA_ARGS__) -#define vfnmsub(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfnmsub_tumu, __riscv_vfnmsub_tu, 3, 2, 1)(__VA_ARGS__) -#define vfwmacc(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfwmacc_tumu, __riscv_vfwmacc_tu, 3, 2, 1)(__VA_ARGS__) -#define vfwnmacc(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfwnmacc_tumu, __riscv_vfwnmacc_tu, 3, 2, 1)(__VA_ARGS__) -#define vfwmsac(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfwmsac_tumu, __riscv_vfwmsac_tu, 3, 2, 1)(__VA_ARGS__) -#define vfwnmsac(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfwnmsac_tumu, __riscv_vfwnmsac_tu, 3, 2, 1)(__VA_ARGS__) -#define vfsqrt(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfsqrt_tumu, 3, __riscv_vfsqrt, 1)(__VA_ARGS__) -#define vfrsqrt7(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfrsqrt7_tumu, 3, __riscv_vfrsqrt7, 1)(__VA_ARGS__) -#define vfrec7(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfrec7_tumu, 3, __riscv_vfrec7, 1)(__VA_ARGS__) -#define vfmin(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfmin_tumu, 4, __riscv_vfmin, 2, 1)(__VA_ARGS__) -#define vfmax(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfmax_tumu, 4, __riscv_vfmax, 2, 1)(__VA_ARGS__) -#define vfsgnj(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfsgnj_tumu, 4, __riscv_vfsgnj, 2, 1)(__VA_ARGS__) -#define vfsgnjn(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfsgnjn_tumu, 4, __riscv_vfsgnjn, 2, 1)(__VA_ARGS__) -#define vfsgnjx(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfsgnjx_tumu, 4, __riscv_vfsgnjx, 2, 1)(__VA_ARGS__) -#define vfabs(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfabs_tumu, 3, __riscv_vfabs, 1)(__VA_ARGS__) -#define vmfeq(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmfeq_mu, 4, __riscv_vmfeq, 2, 1)(__VA_ARGS__) -#define vmfne(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmfne_mu, 4, __riscv_vmfne, 2, 1)(__VA_ARGS__) -#define vmflt(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmflt_mu, 4, __riscv_vmflt, 2, 1)(__VA_ARGS__) -#define vmfle(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmfle_mu, 4, __riscv_vmfle, 2, 1)(__VA_ARGS__) -#define vmfgt(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmfgt_mu, 4, __riscv_vmfgt, 2, 1)(__VA_ARGS__) -#define vmfge(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vmfge_mu, 4, __riscv_vmfge, 2, 1)(__VA_ARGS__) -#define vfclass(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfclass_tumu, 3, __riscv_vfclass, 1)(__VA_ARGS__) -#define vfcvt_x(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfcvt_x_tumu, 3, __riscv_vfcvt_x, 1)(__VA_ARGS__) -#define vfcvt_rtz_x(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfcvt_rtz_x_tumu, 3, __riscv_vfcvt_rtz_x, 1)(__VA_ARGS__) -#define vfcvt_xu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfcvt_xu_tumu, 3, __riscv_vfcvt_xu, 1)(__VA_ARGS__) -#define vfcvt_rtz_xu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfcvt_rtz_xu_tumu, 3, __riscv_vfcvt_rtz_xu, 1)(__VA_ARGS__) -#define vfcvt_f(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfcvt_f_tumu, 3, __riscv_vfcvt_f, 1)(__VA_ARGS__) -#define vwcvt_x(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vwcvt_x_tumu, 3, __riscv_vwcvt_x, 1)(__VA_ARGS__) -#define vwcvtu_x(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vwcvtu_x_tumu, 3, __riscv_vwcvtu_x, 1)(__VA_ARGS__) -#define vfwcvt_f(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfwcvt_f_tumu, 3, __riscv_vfwcvt_f, 1)(__VA_ARGS__) -#define vfwcvt_x(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfwcvt_x_tumu, 3, __riscv_vfwcvt_x, 1)(__VA_ARGS__) -#define vfwcvt_rtz_x(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfwcvt_rtz_x_tumu, 3, __riscv_vfwcvt_rtz_x, 1)(__VA_ARGS__) -#define vfwcvt_xu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfwcvt_xu_tumu, 3, __riscv_vfwcvt_xu, 1)(__VA_ARGS__) -#define vfwcvt_rtz_xu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfwcvt_rtz_xu_tumu, 3, __riscv_vfwcvt_rtz_xu, 1)(__VA_ARGS__) -#define vfncvt_x(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfncvt_x_tumu, 3, __riscv_vfncvt_x, 1)(__VA_ARGS__) -#define vfncvt_rtz_x(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfncvt_rtz_x_tumu, 3, __riscv_vfncvt_rtz_x, 1)(__VA_ARGS__) -#define vncvt_x(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vncvt_x_tumu, 3, __riscv_vncvt_x, 1)(__VA_ARGS__) -#define vfncvt_xu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfncvt_xu_tumu, 3, __riscv_vfncvt_xu, 1)(__VA_ARGS__) -#define vfncvt_rtz_xu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfncvt_rtz_xu_tumu, 3, __riscv_vfncvt_rtz_xu, 1)(__VA_ARGS__) -#define vfncvt_f(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfncvt_f_tumu, 3, __riscv_vfncvt_f, 1)(__VA_ARGS__) -#define vfncvt_rod_f(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vfncvt_rod_f_tumu, 3, __riscv_vfncvt_rod_f, 1)(__VA_ARGS__) -#define vredsum(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vredsum_tum, __riscv_vredsum_tu, 3, 2, 1)(__VA_ARGS__) -#define vredmax(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vredmax_tum, __riscv_vredmax_tu, 3, 2, 1)(__VA_ARGS__) -#define vredmin(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vredmin_tum, __riscv_vredmin_tu, 3, 2, 1)(__VA_ARGS__) -#define vredand(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vredand_tum, __riscv_vredand_tu, 3, 2, 1)(__VA_ARGS__) -#define vredor(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vredor_tum, __riscv_vredor_tu, 3, 2, 1)(__VA_ARGS__) -#define vredxor(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vredxor_tum, __riscv_vredxor_tu, 3, 2, 1)(__VA_ARGS__) -#define vredmaxu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vredmaxu_tum, __riscv_vredmaxu_tu, 3, 2, 1)(__VA_ARGS__) -#define vredminu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vredminu_tum, __riscv_vredminu_tu, 3, 2, 1)(__VA_ARGS__) -#define vwredsum(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwredsum_tum, __riscv_vwredsum_tu, 3, 2, 1)(__VA_ARGS__) -#define vwredsumu(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vwredsumu_tum, __riscv_vwredsumu_tu, 3, 2, 1)(__VA_ARGS__) -#define vfredosum(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfredosum_tum, __riscv_vfredosum_tu, 3, 2, 1)(__VA_ARGS__) -#define vfredusum(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfredusum_tum, __riscv_vfredusum_tu, 3, 2, 1)(__VA_ARGS__) -#define vfredmax(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfredmax_tum, __riscv_vfredmax_tu, 3, 2, 1)(__VA_ARGS__) -#define vfredmin(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfredmin_tum, __riscv_vfredmin_tu, 3, 2, 1)(__VA_ARGS__) -#define vfwredosum(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfwredosum_tum, __riscv_vfwredosum_tu, 3, 2, 1)(__VA_ARGS__) -#define vfwredusum(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfwredusum_tum, __riscv_vfwredusum_tu, 3, 2, 1)(__VA_ARGS__) -#define vsm(...) __riscv_vsm(__VA_ARGS__) -#define vmand(...) __riscv_vmand(__VA_ARGS__) -#define vmnand(...) __riscv_vmnand(__VA_ARGS__) -#define vmandn(...) __riscv_vmandn(__VA_ARGS__) -#define vmxor(...) __riscv_vmxor(__VA_ARGS__) -#define vmor(...) __riscv_vmor(__VA_ARGS__) -#define vmnor(...) __riscv_vmnor(__VA_ARGS__) -#define vmorn(...) __riscv_vmorn(__VA_ARGS__) -#define vmxnor(...) __riscv_vmxnor(__VA_ARGS__) -#define vmmv(...) __riscv_vmmv(__VA_ARGS__) -#define vmnot(...) __riscv_vmnot(__VA_ARGS__) -#define vcpop(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, __riscv_vcpop, __riscv_vcpop, 1)(__VA_ARGS__) -#define vfirst(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, __riscv_vfirst, __riscv_vfirst, 1)(__VA_ARGS__) -#define vmsbf(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vmsbf_mu, 3, __riscv_vmsbf, 1)(__VA_ARGS__) -#define vmsif(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vmsif_mu, 3, __riscv_vmsif, 1)(__VA_ARGS__) -#define vmsof(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, __riscv_vmsof_mu, 3, __riscv_vmsof, 1)(__VA_ARGS__) -#define vfmv_f(...) __riscv_vfmv_f(__VA_ARGS__) -#define vfmv_s(...) __riscv_vfmv_s_tu(__VA_ARGS__) -#define vmv_x(...) __riscv_vmv_x(__VA_ARGS__) -#define vmv_s(...) __riscv_vmv_s_tu(__VA_ARGS__) -#define vslideup(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vslideup_tumu, __riscv_vslideup_tu, 3, 2, 1)(__VA_ARGS__) -#define vslidedown(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vslidedown_tumu, __riscv_vslidedown_tu, 3, 2, 1)(__VA_ARGS__) -#define vfslide1up(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfslide1up_tumu, 4, __riscv_vfslide1up, 2, 1)(__VA_ARGS__) -#define vfslide1down(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vfslide1down_tumu, 4, __riscv_vfslide1down, 2, 1)(__VA_ARGS__) -#define vslide1up(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vslide1up_tumu, 4, __riscv_vslide1up, 2, 1)(__VA_ARGS__) -#define vslide1down(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vslide1down_tumu, 4, __riscv_vslide1down, 2, 1)(__VA_ARGS__) -#define vrgather(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vrgather_tumu, 4, __riscv_vrgather, 2, 1)(__VA_ARGS__) -#define vrgatherei16(...) _GET_OVERRIDE(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, __riscv_vrgatherei16_tumu, 4, __riscv_vrgatherei16, 2, 1)(__VA_ARGS__) -#define vreinterpret_u8mf8(...) __riscv_vreinterpret_u8mf8(__VA_ARGS__) -#define vreinterpret_u8mf4(...) __riscv_vreinterpret_u8mf4(__VA_ARGS__) -#define vreinterpret_u8mf2(...) __riscv_vreinterpret_u8mf2(__VA_ARGS__) -#define vreinterpret_u8m1(...) __riscv_vreinterpret_u8m1(__VA_ARGS__) -#define vreinterpret_u8m2(...) __riscv_vreinterpret_u8m2(__VA_ARGS__) -#define vreinterpret_u8m4(...) __riscv_vreinterpret_u8m4(__VA_ARGS__) -#define vreinterpret_u8m8(...) __riscv_vreinterpret_u8m8(__VA_ARGS__) -#define vreinterpret_i8mf8(...) __riscv_vreinterpret_i8mf8(__VA_ARGS__) -#define vreinterpret_i8mf4(...) __riscv_vreinterpret_i8mf4(__VA_ARGS__) -#define vreinterpret_i8mf2(...) __riscv_vreinterpret_i8mf2(__VA_ARGS__) -#define vreinterpret_i8m1(...) __riscv_vreinterpret_i8m1(__VA_ARGS__) -#define vreinterpret_i8m2(...) __riscv_vreinterpret_i8m2(__VA_ARGS__) -#define vreinterpret_i8m4(...) __riscv_vreinterpret_i8m4(__VA_ARGS__) -#define vreinterpret_i8m8(...) __riscv_vreinterpret_i8m8(__VA_ARGS__) -#define vreinterpret_f16mf4(...) __riscv_vreinterpret_f16mf4(__VA_ARGS__) -#define vreinterpret_f16mf2(...) __riscv_vreinterpret_f16mf2(__VA_ARGS__) -#define vreinterpret_f16m1(...) __riscv_vreinterpret_f16m1(__VA_ARGS__) -#define vreinterpret_f16m2(...) __riscv_vreinterpret_f16m2(__VA_ARGS__) -#define vreinterpret_f16m4(...) __riscv_vreinterpret_f16m4(__VA_ARGS__) -#define vreinterpret_f16m8(...) __riscv_vreinterpret_f16m8(__VA_ARGS__) -#define vreinterpret_u16mf4(...) __riscv_vreinterpret_u16mf4(__VA_ARGS__) -#define vreinterpret_u16mf2(...) __riscv_vreinterpret_u16mf2(__VA_ARGS__) -#define vreinterpret_u16m1(...) __riscv_vreinterpret_u16m1(__VA_ARGS__) -#define vreinterpret_u16m2(...) __riscv_vreinterpret_u16m2(__VA_ARGS__) -#define vreinterpret_u16m4(...) __riscv_vreinterpret_u16m4(__VA_ARGS__) -#define vreinterpret_u16m8(...) __riscv_vreinterpret_u16m8(__VA_ARGS__) -#define vreinterpret_i16mf4(...) __riscv_vreinterpret_i16mf4(__VA_ARGS__) -#define vreinterpret_i16mf2(...) __riscv_vreinterpret_i16mf2(__VA_ARGS__) -#define vreinterpret_i16m1(...) __riscv_vreinterpret_i16m1(__VA_ARGS__) -#define vreinterpret_i16m2(...) __riscv_vreinterpret_i16m2(__VA_ARGS__) -#define vreinterpret_i16m4(...) __riscv_vreinterpret_i16m4(__VA_ARGS__) -#define vreinterpret_i16m8(...) __riscv_vreinterpret_i16m8(__VA_ARGS__) -#define vreinterpret_f32mf2(...) __riscv_vreinterpret_f32mf2(__VA_ARGS__) -#define vreinterpret_f32m1(...) __riscv_vreinterpret_f32m1(__VA_ARGS__) -#define vreinterpret_f32m2(...) __riscv_vreinterpret_f32m2(__VA_ARGS__) -#define vreinterpret_f32m4(...) __riscv_vreinterpret_f32m4(__VA_ARGS__) -#define vreinterpret_f32m8(...) __riscv_vreinterpret_f32m8(__VA_ARGS__) -#define vreinterpret_u32mf2(...) __riscv_vreinterpret_u32mf2(__VA_ARGS__) -#define vreinterpret_u32m1(...) __riscv_vreinterpret_u32m1(__VA_ARGS__) -#define vreinterpret_u32m2(...) __riscv_vreinterpret_u32m2(__VA_ARGS__) -#define vreinterpret_u32m4(...) __riscv_vreinterpret_u32m4(__VA_ARGS__) -#define vreinterpret_u32m8(...) __riscv_vreinterpret_u32m8(__VA_ARGS__) -#define vreinterpret_i32mf2(...) __riscv_vreinterpret_i32mf2(__VA_ARGS__) -#define vreinterpret_i32m1(...) __riscv_vreinterpret_i32m1(__VA_ARGS__) -#define vreinterpret_i32m2(...) __riscv_vreinterpret_i32m2(__VA_ARGS__) -#define vreinterpret_i32m4(...) __riscv_vreinterpret_i32m4(__VA_ARGS__) -#define vreinterpret_i32m8(...) __riscv_vreinterpret_i32m8(__VA_ARGS__) -#define vreinterpret_f64m1(...) __riscv_vreinterpret_f64m1(__VA_ARGS__) -#define vreinterpret_f64m2(...) __riscv_vreinterpret_f64m2(__VA_ARGS__) -#define vreinterpret_f64m4(...) __riscv_vreinterpret_f64m4(__VA_ARGS__) -#define vreinterpret_f64m8(...) __riscv_vreinterpret_f64m8(__VA_ARGS__) -#define vreinterpret_u64m1(...) __riscv_vreinterpret_u64m1(__VA_ARGS__) -#define vreinterpret_u64m2(...) __riscv_vreinterpret_u64m2(__VA_ARGS__) -#define vreinterpret_u64m4(...) __riscv_vreinterpret_u64m4(__VA_ARGS__) -#define vreinterpret_u64m8(...) __riscv_vreinterpret_u64m8(__VA_ARGS__) -#define vreinterpret_i64m1(...) __riscv_vreinterpret_i64m1(__VA_ARGS__) -#define vreinterpret_i64m2(...) __riscv_vreinterpret_i64m2(__VA_ARGS__) -#define vreinterpret_i64m4(...) __riscv_vreinterpret_i64m4(__VA_ARGS__) -#define vreinterpret_i64m8(...) __riscv_vreinterpret_i64m8(__VA_ARGS__) -#define vlmul_ext_f16mf2(...) __riscv_vlmul_ext_f16mf2(__VA_ARGS__) -#define vlmul_ext_f16m1(...) __riscv_vlmul_ext_f16m1(__VA_ARGS__) -#define vlmul_ext_f16m2(...) __riscv_vlmul_ext_f16m2(__VA_ARGS__) -#define vlmul_ext_f16m4(...) __riscv_vlmul_ext_f16m4(__VA_ARGS__) -#define vlmul_ext_f16m8(...) __riscv_vlmul_ext_f16m8(__VA_ARGS__) -#define vlmul_ext_f32m1(...) __riscv_vlmul_ext_f32m1(__VA_ARGS__) -#define vlmul_ext_f32m2(...) __riscv_vlmul_ext_f32m2(__VA_ARGS__) -#define vlmul_ext_f32m4(...) __riscv_vlmul_ext_f32m4(__VA_ARGS__) -#define vlmul_ext_f32m8(...) __riscv_vlmul_ext_f32m8(__VA_ARGS__) -#define vlmul_ext_f64m2(...) __riscv_vlmul_ext_f64m2(__VA_ARGS__) -#define vlmul_ext_f64m4(...) __riscv_vlmul_ext_f64m4(__VA_ARGS__) -#define vlmul_ext_f64m8(...) __riscv_vlmul_ext_f64m8(__VA_ARGS__) -#define vlmul_ext_i8mf4(...) __riscv_vlmul_ext_i8mf4(__VA_ARGS__) -#define vlmul_ext_i8mf2(...) __riscv_vlmul_ext_i8mf2(__VA_ARGS__) -#define vlmul_ext_i8m1(...) __riscv_vlmul_ext_i8m1(__VA_ARGS__) -#define vlmul_ext_i8m2(...) __riscv_vlmul_ext_i8m2(__VA_ARGS__) -#define vlmul_ext_i8m4(...) __riscv_vlmul_ext_i8m4(__VA_ARGS__) -#define vlmul_ext_i8m8(...) __riscv_vlmul_ext_i8m8(__VA_ARGS__) -#define vlmul_ext_i16mf2(...) __riscv_vlmul_ext_i16mf2(__VA_ARGS__) -#define vlmul_ext_i16m1(...) __riscv_vlmul_ext_i16m1(__VA_ARGS__) -#define vlmul_ext_i16m2(...) __riscv_vlmul_ext_i16m2(__VA_ARGS__) -#define vlmul_ext_i16m4(...) __riscv_vlmul_ext_i16m4(__VA_ARGS__) -#define vlmul_ext_i16m8(...) __riscv_vlmul_ext_i16m8(__VA_ARGS__) -#define vlmul_ext_i32m1(...) __riscv_vlmul_ext_i32m1(__VA_ARGS__) -#define vlmul_ext_i32m2(...) __riscv_vlmul_ext_i32m2(__VA_ARGS__) -#define vlmul_ext_i32m4(...) __riscv_vlmul_ext_i32m4(__VA_ARGS__) -#define vlmul_ext_i32m8(...) __riscv_vlmul_ext_i32m8(__VA_ARGS__) -#define vlmul_ext_i64m2(...) __riscv_vlmul_ext_i64m2(__VA_ARGS__) -#define vlmul_ext_i64m4(...) __riscv_vlmul_ext_i64m4(__VA_ARGS__) -#define vlmul_ext_i64m8(...) __riscv_vlmul_ext_i64m8(__VA_ARGS__) -#define vlmul_ext_u8mf4(...) __riscv_vlmul_ext_u8mf4(__VA_ARGS__) -#define vlmul_ext_u8mf2(...) __riscv_vlmul_ext_u8mf2(__VA_ARGS__) -#define vlmul_ext_u8m1(...) __riscv_vlmul_ext_u8m1(__VA_ARGS__) -#define vlmul_ext_u8m2(...) __riscv_vlmul_ext_u8m2(__VA_ARGS__) -#define vlmul_ext_u8m4(...) __riscv_vlmul_ext_u8m4(__VA_ARGS__) -#define vlmul_ext_u8m8(...) __riscv_vlmul_ext_u8m8(__VA_ARGS__) -#define vlmul_ext_u16mf2(...) __riscv_vlmul_ext_u16mf2(__VA_ARGS__) -#define vlmul_ext_u16m1(...) __riscv_vlmul_ext_u16m1(__VA_ARGS__) -#define vlmul_ext_u16m2(...) __riscv_vlmul_ext_u16m2(__VA_ARGS__) -#define vlmul_ext_u16m4(...) __riscv_vlmul_ext_u16m4(__VA_ARGS__) -#define vlmul_ext_u16m8(...) __riscv_vlmul_ext_u16m8(__VA_ARGS__) -#define vlmul_ext_u32m1(...) __riscv_vlmul_ext_u32m1(__VA_ARGS__) -#define vlmul_ext_u32m2(...) __riscv_vlmul_ext_u32m2(__VA_ARGS__) -#define vlmul_ext_u32m4(...) __riscv_vlmul_ext_u32m4(__VA_ARGS__) -#define vlmul_ext_u32m8(...) __riscv_vlmul_ext_u32m8(__VA_ARGS__) -#define vlmul_ext_u64m2(...) __riscv_vlmul_ext_u64m2(__VA_ARGS__) -#define vlmul_ext_u64m4(...) __riscv_vlmul_ext_u64m4(__VA_ARGS__) -#define vlmul_ext_u64m8(...) __riscv_vlmul_ext_u64m8(__VA_ARGS__) -#define vlmul_trunc_f16mf4(...) __riscv_vlmul_trunc_f16mf4(__VA_ARGS__) -#define vlmul_trunc_f16mf2(...) __riscv_vlmul_trunc_f16mf2(__VA_ARGS__) -#define vlmul_trunc_f16m1(...) __riscv_vlmul_trunc_f16m1(__VA_ARGS__) -#define vlmul_trunc_f16m2(...) __riscv_vlmul_trunc_f16m2(__VA_ARGS__) -#define vlmul_trunc_f16m4(...) __riscv_vlmul_trunc_f16m4(__VA_ARGS__) -#define vlmul_trunc_f32mf2(...) __riscv_vlmul_trunc_f32mf2(__VA_ARGS__) -#define vlmul_trunc_f32m1(...) __riscv_vlmul_trunc_f32m1(__VA_ARGS__) -#define vlmul_trunc_f32m2(...) __riscv_vlmul_trunc_f32m2(__VA_ARGS__) -#define vlmul_trunc_f32m4(...) __riscv_vlmul_trunc_f32m4(__VA_ARGS__) -#define vlmul_trunc_f64m1(...) __riscv_vlmul_trunc_f64m1(__VA_ARGS__) -#define vlmul_trunc_f64m2(...) __riscv_vlmul_trunc_f64m2(__VA_ARGS__) -#define vlmul_trunc_f64m4(...) __riscv_vlmul_trunc_f64m4(__VA_ARGS__) -#define vlmul_trunc_i8mf8(...) __riscv_vlmul_trunc_i8mf8(__VA_ARGS__) -#define vlmul_trunc_i8mf4(...) __riscv_vlmul_trunc_i8mf4(__VA_ARGS__) -#define vlmul_trunc_i8mf2(...) __riscv_vlmul_trunc_i8mf2(__VA_ARGS__) -#define vlmul_trunc_i8m1(...) __riscv_vlmul_trunc_i8m1(__VA_ARGS__) -#define vlmul_trunc_i8m2(...) __riscv_vlmul_trunc_i8m2(__VA_ARGS__) -#define vlmul_trunc_i8m4(...) __riscv_vlmul_trunc_i8m4(__VA_ARGS__) -#define vlmul_trunc_i16mf4(...) __riscv_vlmul_trunc_i16mf4(__VA_ARGS__) -#define vlmul_trunc_i16mf2(...) __riscv_vlmul_trunc_i16mf2(__VA_ARGS__) -#define vlmul_trunc_i16m1(...) __riscv_vlmul_trunc_i16m1(__VA_ARGS__) -#define vlmul_trunc_i16m2(...) __riscv_vlmul_trunc_i16m2(__VA_ARGS__) -#define vlmul_trunc_i16m4(...) __riscv_vlmul_trunc_i16m4(__VA_ARGS__) -#define vlmul_trunc_i32mf2(...) __riscv_vlmul_trunc_i32mf2(__VA_ARGS__) -#define vlmul_trunc_i32m1(...) __riscv_vlmul_trunc_i32m1(__VA_ARGS__) -#define vlmul_trunc_i32m2(...) __riscv_vlmul_trunc_i32m2(__VA_ARGS__) -#define vlmul_trunc_i32m4(...) __riscv_vlmul_trunc_i32m4(__VA_ARGS__) -#define vlmul_trunc_i64m1(...) __riscv_vlmul_trunc_i64m1(__VA_ARGS__) -#define vlmul_trunc_i64m2(...) __riscv_vlmul_trunc_i64m2(__VA_ARGS__) -#define vlmul_trunc_i64m4(...) __riscv_vlmul_trunc_i64m4(__VA_ARGS__) -#define vlmul_trunc_u8mf8(...) __riscv_vlmul_trunc_u8mf8(__VA_ARGS__) -#define vlmul_trunc_u8mf4(...) __riscv_vlmul_trunc_u8mf4(__VA_ARGS__) -#define vlmul_trunc_u8mf2(...) __riscv_vlmul_trunc_u8mf2(__VA_ARGS__) -#define vlmul_trunc_u8m1(...) __riscv_vlmul_trunc_u8m1(__VA_ARGS__) -#define vlmul_trunc_u8m2(...) __riscv_vlmul_trunc_u8m2(__VA_ARGS__) -#define vlmul_trunc_u8m4(...) __riscv_vlmul_trunc_u8m4(__VA_ARGS__) -#define vlmul_trunc_u16mf4(...) __riscv_vlmul_trunc_u16mf4(__VA_ARGS__) -#define vlmul_trunc_u16mf2(...) __riscv_vlmul_trunc_u16mf2(__VA_ARGS__) -#define vlmul_trunc_u16m1(...) __riscv_vlmul_trunc_u16m1(__VA_ARGS__) -#define vlmul_trunc_u16m2(...) __riscv_vlmul_trunc_u16m2(__VA_ARGS__) -#define vlmul_trunc_u16m4(...) __riscv_vlmul_trunc_u16m4(__VA_ARGS__) -#define vlmul_trunc_u32mf2(...) __riscv_vlmul_trunc_u32mf2(__VA_ARGS__) -#define vlmul_trunc_u32m1(...) __riscv_vlmul_trunc_u32m1(__VA_ARGS__) -#define vlmul_trunc_u32m2(...) __riscv_vlmul_trunc_u32m2(__VA_ARGS__) -#define vlmul_trunc_u32m4(...) __riscv_vlmul_trunc_u32m4(__VA_ARGS__) -#define vlmul_trunc_u64m1(...) __riscv_vlmul_trunc_u64m1(__VA_ARGS__) -#define vlmul_trunc_u64m2(...) __riscv_vlmul_trunc_u64m2(__VA_ARGS__) -#define vlmul_trunc_u64m4(...) __riscv_vlmul_trunc_u64m4(__VA_ARGS__) -#define vset(...) __riscv_vset(__VA_ARGS__) -#define vget_f16m1(...) __riscv_vget_f16m1(__VA_ARGS__) -#define vget_f16m2(...) __riscv_vget_f16m2(__VA_ARGS__) -#define vget_f16m4(...) __riscv_vget_f16m4(__VA_ARGS__) -#define vget_f32m1(...) __riscv_vget_f32m1(__VA_ARGS__) -#define vget_f32m2(...) __riscv_vget_f32m2(__VA_ARGS__) -#define vget_f32m4(...) __riscv_vget_f32m4(__VA_ARGS__) -#define vget_f64m1(...) __riscv_vget_f64m1(__VA_ARGS__) -#define vget_f64m2(...) __riscv_vget_f64m2(__VA_ARGS__) -#define vget_f64m4(...) __riscv_vget_f64m4(__VA_ARGS__) -#define vget_i8m1(...) __riscv_vget_i8m1(__VA_ARGS__) -#define vget_i8m2(...) __riscv_vget_i8m2(__VA_ARGS__) -#define vget_i8m4(...) __riscv_vget_i8m4(__VA_ARGS__) -#define vget_i16m1(...) __riscv_vget_i16m1(__VA_ARGS__) -#define vget_i16m2(...) __riscv_vget_i16m2(__VA_ARGS__) -#define vget_i16m4(...) __riscv_vget_i16m4(__VA_ARGS__) -#define vget_i32m1(...) __riscv_vget_i32m1(__VA_ARGS__) -#define vget_i32m2(...) __riscv_vget_i32m2(__VA_ARGS__) -#define vget_i32m4(...) __riscv_vget_i32m4(__VA_ARGS__) -#define vget_i64m1(...) __riscv_vget_i64m1(__VA_ARGS__) -#define vget_i64m2(...) __riscv_vget_i64m2(__VA_ARGS__) -#define vget_i64m4(...) __riscv_vget_i64m4(__VA_ARGS__) -#define vget_u8m1(...) __riscv_vget_u8m1(__VA_ARGS__) -#define vget_u8m2(...) __riscv_vget_u8m2(__VA_ARGS__) -#define vget_u8m4(...) __riscv_vget_u8m4(__VA_ARGS__) -#define vget_u16m1(...) __riscv_vget_u16m1(__VA_ARGS__) -#define vget_u16m2(...) __riscv_vget_u16m2(__VA_ARGS__) -#define vget_u16m4(...) __riscv_vget_u16m4(__VA_ARGS__) -#define vget_u32m1(...) __riscv_vget_u32m1(__VA_ARGS__) -#define vget_u32m2(...) __riscv_vget_u32m2(__VA_ARGS__) -#define vget_u32m4(...) __riscv_vget_u32m4(__VA_ARGS__) -#define vget_u64m1(...) __riscv_vget_u64m1(__VA_ARGS__) -#define vget_u64m2(...) __riscv_vget_u64m2(__VA_ARGS__) -#define vget_u64m4(...) __riscv_vget_u64m4(__VA_ARGS__) -#define vle16(...) __riscv_vle16_tumu(__VA_ARGS__) -#define vle32(...) __riscv_vle32_tumu(__VA_ARGS__) -#define vle64(...) __riscv_vle64_tumu(__VA_ARGS__) -#define vle8(...) __riscv_vle8_tumu(__VA_ARGS__) -#define vlse16(...) __riscv_vlse16_tumu(__VA_ARGS__) -#define vlse32(...) __riscv_vlse32_tumu(__VA_ARGS__) -#define vlse64(...) __riscv_vlse64_tumu(__VA_ARGS__) -#define vlse8(...) __riscv_vlse8_tumu(__VA_ARGS__) -#define vle16ff(...) __riscv_vle16ff_tumu(__VA_ARGS__) -#define vle32ff(...) __riscv_vle32ff_tumu(__VA_ARGS__) -#define vle64ff(...) __riscv_vle64ff_tumu(__VA_ARGS__) -#define vle8ff(...) __riscv_vle8ff_tumu(__VA_ARGS__) -#define vlseg2e16(...) __riscv_vlseg2e16_tumu(__VA_ARGS__) -#define vlseg3e16(...) __riscv_vlseg3e16_tumu(__VA_ARGS__) -#define vlseg4e16(...) __riscv_vlseg4e16_tumu(__VA_ARGS__) -#define vlseg5e16(...) __riscv_vlseg5e16_tumu(__VA_ARGS__) -#define vlseg6e16(...) __riscv_vlseg6e16_tumu(__VA_ARGS__) -#define vlseg7e16(...) __riscv_vlseg7e16_tumu(__VA_ARGS__) -#define vlseg8e16(...) __riscv_vlseg8e16_tumu(__VA_ARGS__) -#define vlseg2e32(...) __riscv_vlseg2e32_tumu(__VA_ARGS__) -#define vlseg3e32(...) __riscv_vlseg3e32_tumu(__VA_ARGS__) -#define vlseg4e32(...) __riscv_vlseg4e32_tumu(__VA_ARGS__) -#define vlseg5e32(...) __riscv_vlseg5e32_tumu(__VA_ARGS__) -#define vlseg6e32(...) __riscv_vlseg6e32_tumu(__VA_ARGS__) -#define vlseg7e32(...) __riscv_vlseg7e32_tumu(__VA_ARGS__) -#define vlseg8e32(...) __riscv_vlseg8e32_tumu(__VA_ARGS__) -#define vlseg2e64(...) __riscv_vlseg2e64_tumu(__VA_ARGS__) -#define vlseg3e64(...) __riscv_vlseg3e64_tumu(__VA_ARGS__) -#define vlseg4e64(...) __riscv_vlseg4e64_tumu(__VA_ARGS__) -#define vlseg5e64(...) __riscv_vlseg5e64_tumu(__VA_ARGS__) -#define vlseg6e64(...) __riscv_vlseg6e64_tumu(__VA_ARGS__) -#define vlseg7e64(...) __riscv_vlseg7e64_tumu(__VA_ARGS__) -#define vlseg8e64(...) __riscv_vlseg8e64_tumu(__VA_ARGS__) -#define vlseg2e16ff(...) __riscv_vlseg2e16ff_tumu(__VA_ARGS__) -#define vlseg3e16ff(...) __riscv_vlseg3e16ff_tumu(__VA_ARGS__) -#define vlseg4e16ff(...) __riscv_vlseg4e16ff_tumu(__VA_ARGS__) -#define vlseg5e16ff(...) __riscv_vlseg5e16ff_tumu(__VA_ARGS__) -#define vlseg6e16ff(...) __riscv_vlseg6e16ff_tumu(__VA_ARGS__) -#define vlseg7e16ff(...) __riscv_vlseg7e16ff_tumu(__VA_ARGS__) -#define vlseg8e16ff(...) __riscv_vlseg8e16ff_tumu(__VA_ARGS__) -#define vlseg2e32ff(...) __riscv_vlseg2e32ff_tumu(__VA_ARGS__) -#define vlseg3e32ff(...) __riscv_vlseg3e32ff_tumu(__VA_ARGS__) -#define vlseg4e32ff(...) __riscv_vlseg4e32ff_tumu(__VA_ARGS__) -#define vlseg5e32ff(...) __riscv_vlseg5e32ff_tumu(__VA_ARGS__) -#define vlseg6e32ff(...) __riscv_vlseg6e32ff_tumu(__VA_ARGS__) -#define vlseg7e32ff(...) __riscv_vlseg7e32ff_tumu(__VA_ARGS__) -#define vlseg8e32ff(...) __riscv_vlseg8e32ff_tumu(__VA_ARGS__) -#define vlseg2e64ff(...) __riscv_vlseg2e64ff_tumu(__VA_ARGS__) -#define vlseg3e64ff(...) __riscv_vlseg3e64ff_tumu(__VA_ARGS__) -#define vlseg4e64ff(...) __riscv_vlseg4e64ff_tumu(__VA_ARGS__) -#define vlseg5e64ff(...) __riscv_vlseg5e64ff_tumu(__VA_ARGS__) -#define vlseg6e64ff(...) __riscv_vlseg6e64ff_tumu(__VA_ARGS__) -#define vlseg7e64ff(...) __riscv_vlseg7e64ff_tumu(__VA_ARGS__) -#define vlseg8e64ff(...) __riscv_vlseg8e64ff_tumu(__VA_ARGS__) -#define vlseg2e8(...) __riscv_vlseg2e8_tumu(__VA_ARGS__) -#define vlseg3e8(...) __riscv_vlseg3e8_tumu(__VA_ARGS__) -#define vlseg4e8(...) __riscv_vlseg4e8_tumu(__VA_ARGS__) -#define vlseg5e8(...) __riscv_vlseg5e8_tumu(__VA_ARGS__) -#define vlseg6e8(...) __riscv_vlseg6e8_tumu(__VA_ARGS__) -#define vlseg7e8(...) __riscv_vlseg7e8_tumu(__VA_ARGS__) -#define vlseg8e8(...) __riscv_vlseg8e8_tumu(__VA_ARGS__) -#define vlseg2e8ff(...) __riscv_vlseg2e8ff_tumu(__VA_ARGS__) -#define vlseg3e8ff(...) __riscv_vlseg3e8ff_tumu(__VA_ARGS__) -#define vlseg4e8ff(...) __riscv_vlseg4e8ff_tumu(__VA_ARGS__) -#define vlseg5e8ff(...) __riscv_vlseg5e8ff_tumu(__VA_ARGS__) -#define vlseg6e8ff(...) __riscv_vlseg6e8ff_tumu(__VA_ARGS__) -#define vlseg7e8ff(...) __riscv_vlseg7e8ff_tumu(__VA_ARGS__) -#define vlseg8e8ff(...) __riscv_vlseg8e8ff_tumu(__VA_ARGS__) -#define vlsseg2e16(...) __riscv_vlsseg2e16_tumu(__VA_ARGS__) -#define vlsseg3e16(...) __riscv_vlsseg3e16_tumu(__VA_ARGS__) -#define vlsseg4e16(...) __riscv_vlsseg4e16_tumu(__VA_ARGS__) -#define vlsseg5e16(...) __riscv_vlsseg5e16_tumu(__VA_ARGS__) -#define vlsseg6e16(...) __riscv_vlsseg6e16_tumu(__VA_ARGS__) -#define vlsseg7e16(...) __riscv_vlsseg7e16_tumu(__VA_ARGS__) -#define vlsseg8e16(...) __riscv_vlsseg8e16_tumu(__VA_ARGS__) -#define vlsseg2e32(...) __riscv_vlsseg2e32_tumu(__VA_ARGS__) -#define vlsseg3e32(...) __riscv_vlsseg3e32_tumu(__VA_ARGS__) -#define vlsseg4e32(...) __riscv_vlsseg4e32_tumu(__VA_ARGS__) -#define vlsseg5e32(...) __riscv_vlsseg5e32_tumu(__VA_ARGS__) -#define vlsseg6e32(...) __riscv_vlsseg6e32_tumu(__VA_ARGS__) -#define vlsseg7e32(...) __riscv_vlsseg7e32_tumu(__VA_ARGS__) -#define vlsseg8e32(...) __riscv_vlsseg8e32_tumu(__VA_ARGS__) -#define vlsseg2e64(...) __riscv_vlsseg2e64_tumu(__VA_ARGS__) -#define vlsseg3e64(...) __riscv_vlsseg3e64_tumu(__VA_ARGS__) -#define vlsseg4e64(...) __riscv_vlsseg4e64_tumu(__VA_ARGS__) -#define vlsseg5e64(...) __riscv_vlsseg5e64_tumu(__VA_ARGS__) -#define vlsseg6e64(...) __riscv_vlsseg6e64_tumu(__VA_ARGS__) -#define vlsseg7e64(...) __riscv_vlsseg7e64_tumu(__VA_ARGS__) -#define vlsseg8e64(...) __riscv_vlsseg8e64_tumu(__VA_ARGS__) -#define vlsseg2e8(...) __riscv_vlsseg2e8_tumu(__VA_ARGS__) -#define vlsseg3e8(...) __riscv_vlsseg3e8_tumu(__VA_ARGS__) -#define vlsseg4e8(...) __riscv_vlsseg4e8_tumu(__VA_ARGS__) -#define vlsseg5e8(...) __riscv_vlsseg5e8_tumu(__VA_ARGS__) -#define vlsseg6e8(...) __riscv_vlsseg6e8_tumu(__VA_ARGS__) -#define vlsseg7e8(...) __riscv_vlsseg7e8_tumu(__VA_ARGS__) -#define vlsseg8e8(...) __riscv_vlsseg8e8_tumu(__VA_ARGS__) -#define viota(...) __riscv_viota_tumu(__VA_ARGS__) -#define vid(...) __riscv_vid_tumu(__VA_ARGS__) -#endif diff --git a/modules/core/include/opencv2/core/hal/intrin_rvv_011_compat.hpp b/modules/core/include/opencv2/core/hal/intrin_rvv_011_compat.hpp deleted file mode 100644 index da5e0fdd57..0000000000 --- a/modules/core/include/opencv2/core/hal/intrin_rvv_011_compat.hpp +++ /dev/null @@ -1,33 +0,0 @@ -// This file is part of OpenCV project. -// It is subject to the license terms in the LICENSE file found in the top-level directory -// of this distribution and at http://opencv.org/license.html. - -// 0.11 -> 0.12 compatibility - -#ifndef _RVV_IMPLICIT_VXRM -#define _RVV_IMPLICIT_VXRM __RISCV_VXRM_RNU -#endif - -// NOTE: masked should go first to avoid extra substitution (3 arg -> 4 arg -> 5 arg) - -// masked -#define __riscv_vaadd(_1, _2, _3, _4) __riscv_vaadd(_1, _2, _3, _RVV_IMPLICIT_VXRM, _4) -#define __riscv_vasub(_1, _2, _3, _4) __riscv_vasub(_1, _2, _3, _RVV_IMPLICIT_VXRM, _4) -#define __riscv_vaaddu(_1, _2, _3, _4) __riscv_vaaddu(_1, _2, _3, _RVV_IMPLICIT_VXRM, _4) -#define __riscv_vasubu(_1, _2, _3, _4) __riscv_vasubu(_1, _2, _3, _RVV_IMPLICIT_VXRM, _4) -#define __riscv_vsmul(_1, _2, _3, _4) __riscv_vsmul(_1, _2, _3, _RVV_IMPLICIT_VXRM, _4) -#define __riscv_vssra(_1, _2, _3, _4) __riscv_vssra(_1, _2, _3, _RVV_IMPLICIT_VXRM, _4) -#define __riscv_vssrl(_1, _2, _3, _4) __riscv_vssrl(_1, _2, _3, _RVV_IMPLICIT_VXRM, _4) -#define __riscv_vnclip(_1, _2, _3, _4) __riscv_vnclip(_1, _2, _3, _RVV_IMPLICIT_VXRM, _4) -#define __riscv_vnclipu(_1, _2, _3, _4) __riscv_vnclipu(_1, _2, _3, _RVV_IMPLICIT_VXRM, _4) - -// unmasked -#define __riscv_vaadd(_1, _2, _3) __riscv_vaadd(_1, _2, _RVV_IMPLICIT_VXRM, _3) -#define __riscv_vasub(_1, _2, _3) __riscv_vasub(_1, _2, _RVV_IMPLICIT_VXRM, _3) -#define __riscv_vaaddu(_1, _2, _3) __riscv_vaaddu(_1, _2, _RVV_IMPLICIT_VXRM, _3) -#define __riscv_vasubu(_1, _2, _3) __riscv_vasubu(_1, _2, _RVV_IMPLICIT_VXRM, _3) -#define __riscv_vsmul(_1, _2, _3) __riscv_vsmul(_1, _2, _RVV_IMPLICIT_VXRM, _3) -#define __riscv_vssra(_1, _2, _3) __riscv_vssra(_1, _2, _RVV_IMPLICIT_VXRM, _3) -#define __riscv_vssrl(_1, _2, _3) __riscv_vssrl(_1, _2, _RVV_IMPLICIT_VXRM, _3) -#define __riscv_vnclip(_1, _2, _3) __riscv_vnclip(_1, _2, _RVV_IMPLICIT_VXRM, _3) -#define __riscv_vnclipu(_1, _2, _3) __riscv_vnclipu(_1, _2, _RVV_IMPLICIT_VXRM, _3) diff --git a/modules/core/include/opencv2/core/hal/intrin_rvv_compat_overloaded.hpp b/modules/core/include/opencv2/core/hal/intrin_rvv_compat_overloaded.hpp deleted file mode 100644 index 2a323069fd..0000000000 --- a/modules/core/include/opencv2/core/hal/intrin_rvv_compat_overloaded.hpp +++ /dev/null @@ -1,213 +0,0 @@ -// This file is part of OpenCV project. -// It is subject to the license terms in the LICENSE file found in the top-level directory -// of this distribution and at http://opencv.org/license.html. - -#ifndef OPENCV_HAL_INTRIN_RVV_COMPAT_OVERLOAD_HPP -#define OPENCV_HAL_INTRIN_RVV_COMPAT_OVERLOAD_HPP - -// This file requires VTraits to be defined for vector types - -#define OPENCV_HAL_IMPL_RVV_FUN_AND(REG, SUF) \ -inline static REG vand(const REG & op1, const REG & op2, size_t vl) \ -{ \ - return vand_vv_##SUF(op1, op2, vl); \ -} - -OPENCV_HAL_IMPL_RVV_FUN_AND(vint8m1_t, i8m1) -OPENCV_HAL_IMPL_RVV_FUN_AND(vuint8m1_t, u8m1) -OPENCV_HAL_IMPL_RVV_FUN_AND(vint16m1_t, i16m1) -OPENCV_HAL_IMPL_RVV_FUN_AND(vuint16m1_t, u16m1) -OPENCV_HAL_IMPL_RVV_FUN_AND(vint32m1_t, i32m1) -OPENCV_HAL_IMPL_RVV_FUN_AND(vuint32m1_t, u32m1) -OPENCV_HAL_IMPL_RVV_FUN_AND(vint64m1_t, i64m1) -OPENCV_HAL_IMPL_RVV_FUN_AND(vuint64m1_t, u64m1) - -#define OPENCV_HAL_IMPL_RVV_FUN_LOXEI(REG, SUF, INDX, ISUF) \ -inline static REG vloxe##ISUF(const VTraits::lane_type *base, INDX bindex, size_t vl) \ -{ \ - return vloxe##ISUF##_v_##SUF(base, bindex, vl); \ -} - -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vint8m1_t, i8m1, vuint8m1_t, i8) -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vint8m2_t, i8m2, vuint8m2_t, i8) -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vint8m4_t, i8m4, vuint8m4_t, i8) -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vint8m8_t, i8m8, vuint8m8_t, i8) -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vint8m1_t, i8m1, vuint32m4_t, i32) -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vint8m2_t, i8m2, vuint32m8_t, i32) -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vint16m1_t, i16m1, vuint32m2_t, i32) -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vint32m1_t, i32m1, vuint32m1_t, i32) -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vint32m2_t, i32m2, vuint32m2_t, i32) -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vint32m4_t, i32m4, vuint32m4_t, i32) -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vint32m8_t, i32m8, vuint32m8_t, i32) -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vint64m1_t, i64m1, vuint32mf2_t, i32) -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vuint8m1_t, u8m1, vuint8m1_t, i8) -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vuint8m2_t, u8m2, vuint8m2_t, i8) -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vuint8m4_t, u8m4, vuint8m4_t, i8) -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vuint8m8_t, u8m8, vuint8m8_t, i8) -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vfloat32m1_t, f32m1, vuint32m1_t, i32) -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vuint32m1_t, u32m1, vuint32m1_t, i32) -#if CV_SIMD_SCALABLE_64F -OPENCV_HAL_IMPL_RVV_FUN_LOXEI(vfloat64m1_t, f64m1, vuint32mf2_t, i32) -#endif - -#define OPENCV_HAL_IMPL_RVV_FUN_MUL(REG, SUF) \ -inline static REG##m1_t vmul(const REG##m1_t & op1, const REG##m1_t & op2, size_t vl) \ -{ \ - return vmul_vv_##SUF##m1(op1, op2, vl); \ -} \ -inline static REG##m1_t vmul(const REG##m1_t & op1, VTraits::lane_type op2, size_t vl) \ -{ \ - return vmul_vx_##SUF##m1(op1, op2, vl); \ -} \ -inline static REG##m2_t vmul(const REG##m2_t & op1, const REG##m2_t & op2, size_t vl) \ -{ \ - return vmul_vv_##SUF##m2(op1, op2, vl); \ -} \ -inline static REG##m2_t vmul(const REG##m2_t & op1, VTraits::lane_type op2, size_t vl) \ -{ \ - return vmul_vx_##SUF##m2(op1, op2, vl); \ -} \ -inline static REG##m4_t vmul(const REG##m4_t & op1, const REG##m4_t & op2, size_t vl) \ -{ \ - return vmul_vv_##SUF##m4(op1, op2, vl); \ -} \ -inline static REG##m4_t vmul(const REG##m4_t & op1, VTraits::lane_type op2, size_t vl) \ -{ \ - return vmul_vx_##SUF##m4(op1, op2, vl); \ -} \ -inline static REG##m8_t vmul(const REG##m8_t & op1, const REG##m8_t & op2, size_t vl) \ -{ \ - return vmul_vv_##SUF##m8(op1, op2, vl); \ -} \ -inline static REG##m8_t vmul(const REG##m8_t & op1, VTraits::lane_type op2, size_t vl) \ -{ \ - return vmul_vx_##SUF##m8(op1, op2, vl); \ -} - -OPENCV_HAL_IMPL_RVV_FUN_MUL(vint8, i8) -OPENCV_HAL_IMPL_RVV_FUN_MUL(vuint8, u8) -OPENCV_HAL_IMPL_RVV_FUN_MUL(vint16, i16) -OPENCV_HAL_IMPL_RVV_FUN_MUL(vuint16, u16) -OPENCV_HAL_IMPL_RVV_FUN_MUL(vint32, i32) -OPENCV_HAL_IMPL_RVV_FUN_MUL(vuint32, u32) - -#define OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(REG1, SUF1, REG2, SUF2) \ -inline static REG1##m1_t vreinterpret_##SUF1##m1(const REG2##m1_t & src) \ -{\ - return vreinterpret_v_##SUF2##m1_##SUF1##m1(src); \ -} \ -inline static REG1##m2_t vreinterpret_##SUF1##m2(const REG2##m2_t & src) \ -{\ - return vreinterpret_v_##SUF2##m2_##SUF1##m2(src); \ -} \ -inline static REG1##m4_t vreinterpret_##SUF1##m4(const REG2##m4_t & src) \ -{\ - return vreinterpret_v_##SUF2##m4_##SUF1##m4(src); \ -} \ -inline static REG1##m8_t vreinterpret_##SUF1##m8(const REG2##m8_t & src) \ -{\ - return vreinterpret_v_##SUF2##m8_##SUF1##m8(src); \ -} - -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vint8, i8, vuint8, u8) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vint16, i16, vuint16, u16) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vint32, i32, vuint32, u32) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vfloat32, f32, vuint32, u32) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vfloat32, f32, vint32, i32) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vuint32, u32, vfloat32, f32) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vint32, i32, vfloat32, f32) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vuint8, u8, vint8, i8) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vuint8, u8, vuint16, u16) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vuint8, u8, vuint32, u32) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vuint8, u8, vuint64, u64) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vuint16, u16, vint16, i16) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vuint16, u16, vuint8, u8) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vuint16, u16, vuint32, u32) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vuint16, u16, vuint64, u64) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vuint32, u32, vint32, i32) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vuint32, u32, vuint8, u8) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vuint32, u32, vuint16, u16) -OPENCV_HAL_IMPL_RVV_FUN_REINTERPRET(vuint32, u32, vuint64, u64) - -#define OPENCV_HAL_IMPL_RVV_FUN_STORE(REG, SUF, SZ) \ -inline static void vse##SZ(VTraits::lane_type *base, REG value, size_t vl) \ -{ \ - return vse##SZ##_v_##SUF##m1(base, value, vl); \ -} - -OPENCV_HAL_IMPL_RVV_FUN_STORE(v_uint8, u8, 8) -OPENCV_HAL_IMPL_RVV_FUN_STORE(v_int8, i8, 8) -OPENCV_HAL_IMPL_RVV_FUN_STORE(v_uint16, u16, 16) -OPENCV_HAL_IMPL_RVV_FUN_STORE(v_int16, i16, 16) -OPENCV_HAL_IMPL_RVV_FUN_STORE(v_uint32, u32, 32) -OPENCV_HAL_IMPL_RVV_FUN_STORE(v_int32, i32, 32) -OPENCV_HAL_IMPL_RVV_FUN_STORE(v_uint64, u64, 64) -OPENCV_HAL_IMPL_RVV_FUN_STORE(v_int64, i64, 64) -OPENCV_HAL_IMPL_RVV_FUN_STORE(v_float32, f32, 32) -#if CV_SIMD_SCALABLE_64F -OPENCV_HAL_IMPL_RVV_FUN_STORE(v_float64, f64, 64) -#endif - -#define OPENCV_HAL_IMPL_RVV_FUN_EXTRACT(REG, SUF) \ -inline static VTraits::lane_type vmv_x(const REG & reg) \ -{\ - return vmv_x_s_##SUF##m1_##SUF(reg); \ -} -#define OPENCV_HAL_IMPL_RVV_FUN_EXTRACT_F(REG, SUF) \ -inline static VTraits::lane_type vfmv_f(const REG & reg) \ -{\ - return vfmv_f_s_##SUF##m1_##SUF(reg); \ -} - -OPENCV_HAL_IMPL_RVV_FUN_EXTRACT(v_uint8, u8) -OPENCV_HAL_IMPL_RVV_FUN_EXTRACT(v_int8, i8) -OPENCV_HAL_IMPL_RVV_FUN_EXTRACT(v_uint16, u16) -OPENCV_HAL_IMPL_RVV_FUN_EXTRACT(v_int16, i16) -OPENCV_HAL_IMPL_RVV_FUN_EXTRACT(v_uint32, u32) -OPENCV_HAL_IMPL_RVV_FUN_EXTRACT(v_int32, i32) -OPENCV_HAL_IMPL_RVV_FUN_EXTRACT(v_uint64, u64) -OPENCV_HAL_IMPL_RVV_FUN_EXTRACT(v_int64, i64) -OPENCV_HAL_IMPL_RVV_FUN_EXTRACT_F(v_float32, f32) -#if CV_SIMD_SCALABLE_64F -OPENCV_HAL_IMPL_RVV_FUN_EXTRACT_F(v_float64, f64) -#endif - -#define OPENCV_HAL_IMPL_RVV_FUN_SLIDE(REG, SUF) \ -inline static REG vslidedown(const REG & dst, const REG & src, size_t offset, size_t vl) \ -{ \ - return vslidedown_vx_##SUF##m1(dst, src, offset, vl); \ -} \ -inline static REG vslideup(const REG & dst, const REG & src, size_t offset, size_t vl) \ -{ \ - return vslideup_vx_##SUF##m1(dst, src, offset, vl); \ -} - -OPENCV_HAL_IMPL_RVV_FUN_SLIDE(v_uint8, u8) -OPENCV_HAL_IMPL_RVV_FUN_SLIDE(v_int8, i8) -OPENCV_HAL_IMPL_RVV_FUN_SLIDE(v_uint16, u16) -OPENCV_HAL_IMPL_RVV_FUN_SLIDE(v_int16, i16) -OPENCV_HAL_IMPL_RVV_FUN_SLIDE(v_uint32, u32) -OPENCV_HAL_IMPL_RVV_FUN_SLIDE(v_int32, i32) -OPENCV_HAL_IMPL_RVV_FUN_SLIDE(v_float32, f32) -OPENCV_HAL_IMPL_RVV_FUN_SLIDE(v_uint64, u64) -OPENCV_HAL_IMPL_RVV_FUN_SLIDE(v_int64, i64) -#if CV_SIMD_SCALABLE_64F -OPENCV_HAL_IMPL_RVV_FUN_SLIDE(v_float64, f64) -#endif - -inline static vuint32mf2_t vmul(const vuint32mf2_t & op1, uint32_t op2, size_t vl) -{ - return vmul_vx_u32mf2(op1, op2, vl); -} - -inline static vuint32mf2_t vreinterpret_u32mf2(const vint32mf2_t& val) -{ - return vreinterpret_v_i32mf2_u32mf2(val); -} - -inline static vuint32mf2_t vreinterpret_u32mf2(const vuint16mf2_t& val) -{ - return vreinterpret_v_u16mf2_u32mf2(val); -} - -#endif //OPENCV_HAL_INTRIN_RVV_COMPAT_OVERLOAD_HPP diff --git a/modules/core/include/opencv2/core/hal/intrin_rvv_scalable.hpp b/modules/core/include/opencv2/core/hal/intrin_rvv_scalable.hpp index 0159e4325a..c8d4ec37b5 100644 --- a/modules/core/include/opencv2/core/hal/intrin_rvv_scalable.hpp +++ b/modules/core/include/opencv2/core/hal/intrin_rvv_scalable.hpp @@ -10,18 +10,6 @@ #include -// RVV intrinsics have been renamed in version 0.11, so we need to include -// compatibility headers: -// https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/master/auto-generated/rvv-v0p10-compatible-headers -#if defined(__riscv_v_intrinsic) && __riscv_v_intrinsic>10999 -#include "intrin_rvv_010_compat_non-policy.hpp" -#include "intrin_rvv_010_compat_overloaded-non-policy.hpp" -#endif - -#if defined(__riscv_v_intrinsic) && __riscv_v_intrinsic>11999 -#include "intrin_rvv_011_compat.hpp" -#endif - #if defined(__GNUC__) && !defined(__clang__) // FIXIT: eliminate massive warnigs from templates // GCC from 'rvv-next': riscv64-unknown-linux-gnu-g++ (g42df3464463) 12.0.1 20220505 (prerelease) @@ -64,22 +52,22 @@ using uint = unsigned int; using uint64 = unsigned long int; using int64 = long int; -static const int __cv_rvv_e8m1_nlanes = vsetvlmax_e8m1(); -static const int __cv_rvv_e16m1_nlanes = vsetvlmax_e16m1(); -static const int __cv_rvv_e32m1_nlanes = vsetvlmax_e32m1(); -static const int __cv_rvv_e64m1_nlanes = vsetvlmax_e64m1(); -static const int __cv_rvv_e8m2_nlanes = vsetvlmax_e8m2(); -static const int __cv_rvv_e16m2_nlanes = vsetvlmax_e16m2(); -static const int __cv_rvv_e32m2_nlanes = vsetvlmax_e32m2(); -static const int __cv_rvv_e64m2_nlanes = vsetvlmax_e64m2(); -static const int __cv_rvv_e8m4_nlanes = vsetvlmax_e8m4(); -static const int __cv_rvv_e16m4_nlanes = vsetvlmax_e16m4(); -static const int __cv_rvv_e32m4_nlanes = vsetvlmax_e32m4(); -static const int __cv_rvv_e64m4_nlanes = vsetvlmax_e64m4(); -static const int __cv_rvv_e8m8_nlanes = vsetvlmax_e8m8(); -static const int __cv_rvv_e16m8_nlanes = vsetvlmax_e16m8(); -static const int __cv_rvv_e32m8_nlanes = vsetvlmax_e32m8(); -static const int __cv_rvv_e64m8_nlanes = vsetvlmax_e64m8(); +static const int __cv_rvv_e8m1_nlanes = __riscv_vsetvlmax_e8m1(); +static const int __cv_rvv_e16m1_nlanes = __riscv_vsetvlmax_e16m1(); +static const int __cv_rvv_e32m1_nlanes = __riscv_vsetvlmax_e32m1(); +static const int __cv_rvv_e64m1_nlanes = __riscv_vsetvlmax_e64m1(); +static const int __cv_rvv_e8m2_nlanes = __riscv_vsetvlmax_e8m2(); +static const int __cv_rvv_e16m2_nlanes = __riscv_vsetvlmax_e16m2(); +static const int __cv_rvv_e32m2_nlanes = __riscv_vsetvlmax_e32m2(); +static const int __cv_rvv_e64m2_nlanes = __riscv_vsetvlmax_e64m2(); +static const int __cv_rvv_e8m4_nlanes = __riscv_vsetvlmax_e8m4(); +static const int __cv_rvv_e16m4_nlanes = __riscv_vsetvlmax_e16m4(); +static const int __cv_rvv_e32m4_nlanes = __riscv_vsetvlmax_e32m4(); +static const int __cv_rvv_e64m4_nlanes = __riscv_vsetvlmax_e64m4(); +static const int __cv_rvv_e8m8_nlanes = __riscv_vsetvlmax_e8m8(); +static const int __cv_rvv_e16m8_nlanes = __riscv_vsetvlmax_e16m8(); +static const int __cv_rvv_e32m8_nlanes = __riscv_vsetvlmax_e32m8(); +static const int __cv_rvv_e64m8_nlanes = __riscv_vsetvlmax_e64m8(); template struct VTraits; @@ -146,16 +134,16 @@ OPENCV_HAL_IMPL_RVV_TRAITS(vfloat64m8_t, double, e64m8, 64) // GCC does not have these functions, so we need to implement them manually // We implement only selected subset required to build current state of the code // Included inside namespace cv:: -#ifndef __riscv_v_intrinsic_overloading -#include "intrin_rvv_compat_overloaded.hpp" -#endif // __riscv_v_intrinsic_overloading +// #ifndef __riscv_v_intrinsic_overloading +// #include "intrin_rvv_compat_overloaded.hpp" +// #endif // __riscv_v_intrinsic_overloading //////////// get0 //////////// #define OPENCV_HAL_IMPL_RVV_GRT0_INT(_Tpvec, _Tp) \ inline _Tp v_get0(const v_##_Tpvec& v) \ { \ - return vmv_x(v); \ + return __riscv_vmv_x(v); \ } OPENCV_HAL_IMPL_RVV_GRT0_INT(uint8, uchar) @@ -169,12 +157,12 @@ OPENCV_HAL_IMPL_RVV_GRT0_INT(int64, int64) inline float v_get0(const v_float32& v) \ { \ - return vfmv_f(v); \ + return __riscv_vfmv_f(v); \ } #if CV_SIMD_SCALABLE_64F inline double v_get0(const v_float64& v) \ { \ - return vfmv_f(v); \ + return __riscv_vfmv_f(v); \ } #endif @@ -183,14 +171,14 @@ inline double v_get0(const v_float64& v) \ #define OPENCV_HAL_IMPL_RVV_INIT_INTEGER(_Tpvec, _Tp, suffix1, suffix2, vl) \ inline v_##_Tpvec v_setzero_##suffix1() \ { \ - return vmv_v_x_##suffix2##m1(0, vl); \ + return __riscv_vmv_v_x_##suffix2##m1(0, vl); \ } \ inline v_##_Tpvec v_setall_##suffix1(_Tp v) \ { \ - return vmv_v_x_##suffix2##m1(v, vl); \ + return __riscv_vmv_v_x_##suffix2##m1(v, vl); \ } -OPENCV_HAL_IMPL_RVV_INIT_INTEGER(uint8, uchar, u8, u8, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_INIT_INTEGER(uint8, uchar, u8, u8, VTraits::vlanes()) OPENCV_HAL_IMPL_RVV_INIT_INTEGER(int8, schar, s8, i8, VTraits::vlanes()) OPENCV_HAL_IMPL_RVV_INIT_INTEGER(uint16, ushort, u16, u16, VTraits::vlanes()) OPENCV_HAL_IMPL_RVV_INIT_INTEGER(int16, short, s16, i16, VTraits::vlanes()) @@ -202,11 +190,11 @@ OPENCV_HAL_IMPL_RVV_INIT_INTEGER(int64, int64, s64, i64, VTraits::vlane #define OPENCV_HAL_IMPL_RVV_INIT_FP(_Tpv, _Tp, suffix, vl) \ inline v_##_Tpv v_setzero_##suffix() \ { \ - return vfmv_v_f_##suffix##m1(0, vl); \ + return __riscv_vfmv_v_f_##suffix##m1(0, vl); \ } \ inline v_##_Tpv v_setall_##suffix(_Tp v) \ { \ - return vfmv_v_f_##suffix##m1(v, vl); \ + return __riscv_vfmv_v_f_##suffix##m1(v, vl); \ } OPENCV_HAL_IMPL_RVV_INIT_FP(float32, float, f32, VTraits::vlanes()) @@ -236,11 +224,11 @@ OPENCV_HAL_IMPL_RVV_NOTHING_REINTERPRET(float64, f64) #define OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(_Tpvec1, _Tpvec2, suffix1, suffix2, nsuffix1, nsuffix2) \ inline v_##_Tpvec1 v_reinterpret_as_##suffix1(const v_##_Tpvec2& v) \ { \ - return v_##_Tpvec1(vreinterpret_v_##nsuffix2##m1_##nsuffix1##m1(v));\ + return v_##_Tpvec1(__riscv_vreinterpret_v_##nsuffix2##m1_##nsuffix1##m1(v));\ } \ inline v_##_Tpvec2 v_reinterpret_as_##suffix2(const v_##_Tpvec1& v) \ { \ - return v_##_Tpvec2(vreinterpret_v_##nsuffix1##m1_##nsuffix2##m1(v));\ + return v_##_Tpvec2(__riscv_vreinterpret_v_##nsuffix1##m1_##nsuffix2##m1(v));\ } OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(uint8, int8, u8, s8, u8, i8) @@ -270,11 +258,11 @@ OPENCV_HAL_IMPL_RVV_NATIVE_REINTERPRET(int32, int64, s32, s64, i32, i64) #define OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(_Tpvec1, _Tpvec2, suffix1, suffix2, nsuffix1, nsuffix2, width1, width2) \ inline v_##_Tpvec1 v_reinterpret_as_##suffix1(const v_##_Tpvec2& v) \ { \ - return vreinterpret_v_##nsuffix1##width2##m1_##nsuffix1##width1##m1(vreinterpret_v_##nsuffix2##width2##m1_##nsuffix1##width2##m1(v));\ + return __riscv_vreinterpret_v_##nsuffix1##width2##m1_##nsuffix1##width1##m1(__riscv_vreinterpret_v_##nsuffix2##width2##m1_##nsuffix1##width2##m1(v));\ } \ inline v_##_Tpvec2 v_reinterpret_as_##suffix2(const v_##_Tpvec1& v) \ { \ - return vreinterpret_v_##nsuffix1##width2##m1_##nsuffix2##width2##m1(vreinterpret_v_##nsuffix1##width1##m1_##nsuffix1##width2##m1(v));\ + return __riscv_vreinterpret_v_##nsuffix1##width2##m1_##nsuffix2##width2##m1(__riscv_vreinterpret_v_##nsuffix1##width1##m1_##nsuffix1##width2##m1(v));\ } OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(uint8, int16, u8, s16, u, i, 8, 16) @@ -305,52 +293,51 @@ OPENCV_HAL_IMPL_RVV_TWO_TIMES_REINTERPRET(int32, float64, s32, f64, i, f, 32, 64 // Three times reinterpret inline v_float32 v_reinterpret_as_f32(const v_float64& v) \ { \ - return vreinterpret_v_u32m1_f32m1(vreinterpret_v_u64m1_u32m1(vreinterpret_v_f64m1_u64m1(v)));\ + return __riscv_vreinterpret_v_u32m1_f32m1(__riscv_vreinterpret_v_u64m1_u32m1(__riscv_vreinterpret_v_f64m1_u64m1(v)));\ } inline v_float64 v_reinterpret_as_f64(const v_float32& v) \ { \ - return vreinterpret_v_u64m1_f64m1(vreinterpret_v_u32m1_u64m1(vreinterpret_v_f32m1_u32m1(v)));\ + return __riscv_vreinterpret_v_u64m1_f64m1(__riscv_vreinterpret_v_u32m1_u64m1(__riscv_vreinterpret_v_f32m1_u32m1(v)));\ } #endif //////////// Extract ////////////// -#define OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(_Tpvec, _Tp, suffix, vl) \ +#define OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(_Tpvec, _Tp, vl) \ template \ inline _Tpvec v_extract(const _Tpvec& a, const _Tpvec& b, int i = s) \ { \ - return vslideup(vslidedown(v_setzero_##suffix(), a, i, vl), b, VTraits<_Tpvec>::vlanes() - i, vl); \ + return __riscv_vslideup(__riscv_vslidedown(a, i, vl), b, VTraits<_Tpvec>::vlanes() - i, vl); \ } \ template inline _Tp v_extract_n(_Tpvec v, int i = s) \ { \ - return vmv_x(vslidedown(v_setzero_##suffix(), v, i, vl)); \ + return __riscv_vmv_x(__riscv_vslidedown(v, i, vl)); \ } +OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_uint8, uchar, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_int8, schar, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_uint16, ushort, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_int16, short, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_uint32, unsigned int, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_int32, int, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_uint64, uint64, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_int64, int64, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_uint8, uchar, u8, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_int8, schar, s8, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_uint16, ushort, u16, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_int16, short, s16, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_uint32, unsigned int, u32, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_int32, int, s32, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_uint64, uint64, u64, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_EXTRACT_INTEGER(v_int64, int64, s64, VTraits::vlanes()) - -#define OPENCV_HAL_IMPL_RVV_EXTRACT_FP(_Tpvec, _Tp, suffix, vl) \ +#define OPENCV_HAL_IMPL_RVV_EXTRACT_FP(_Tpvec, _Tp, vl) \ template \ inline _Tpvec v_extract(const _Tpvec& a, const _Tpvec& b, int i = s) \ { \ - return vslideup(vslidedown(v_setzero_##suffix(), a, i, vl), b, VTraits<_Tpvec>::vlanes() - i, vl); \ + return __riscv_vslideup(__riscv_vslidedown(a, i, vl), b, VTraits<_Tpvec>::vlanes() - i, vl); \ } \ template inline _Tp v_extract_n(_Tpvec v, int i = s) \ { \ - return vfmv_f(vslidedown(v_setzero_##suffix(), v, i, vl)); \ + return __riscv_vfmv_f(__riscv_vslidedown(v, i, vl)); \ } -OPENCV_HAL_IMPL_RVV_EXTRACT_FP(v_float32, float, f32, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_EXTRACT_FP(v_float32, float, VTraits::vlanes()) #if CV_SIMD_SCALABLE_64F -OPENCV_HAL_IMPL_RVV_EXTRACT_FP(v_float64, double, f64, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_EXTRACT_FP(v_float64, double, VTraits::vlanes()) #endif #define OPENCV_HAL_IMPL_RVV_EXTRACT(_Tpvec, _Tp, vl) \ @@ -374,46 +361,46 @@ OPENCV_HAL_IMPL_RVV_EXTRACT(v_float64, double, VTraits::vlanes()) ////////////// Load/Store ////////////// -#define OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(_Tpvec, _nTpvec, _Tp, hvl, vl, width, suffix, vmv) \ +#define OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(_Tpvec, _nTpvec, _Tp, hvl, vl, width, suffix) \ inline _Tpvec v_load(const _Tp* ptr) \ { \ - return vle##width##_v_##suffix##m1(ptr, vl); \ + return __riscv_vle##width##_v_##suffix##m1(ptr, vl); \ } \ inline _Tpvec v_load_aligned(const _Tp* ptr) \ { \ - return vle##width##_v_##suffix##m1(ptr, vl); \ + return __riscv_vle##width##_v_##suffix##m1(ptr, vl); \ } \ inline void v_store(_Tp* ptr, const _Tpvec& a, hal::StoreMode /*mode*/) \ { \ - vse##width##_v_##suffix##m1(ptr, a, vl); \ + __riscv_vse##width##_v_##suffix##m1(ptr, a, vl); \ } \ inline _Tpvec v_load_low(const _Tp* ptr) \ { \ - return vle##width##_v_##suffix##m1(ptr, hvl); \ + return __riscv_vle##width##_v_##suffix##m1(ptr, hvl); \ } \ inline _Tpvec v_load_halves(const _Tp* ptr0, const _Tp* ptr1) \ { \ - return vslideup(vle##width##_v_##suffix##m1(ptr0, hvl), vle##width##_v_##suffix##m1(ptr1, hvl), hvl, vl); \ + return __riscv_vslideup(__riscv_vle##width##_v_##suffix##m1(ptr0, hvl), __riscv_vle##width##_v_##suffix##m1(ptr1, hvl), hvl, vl); \ } \ inline void v_store(_Tp* ptr, const _Tpvec& a) \ { \ - vse##width(ptr, a, vl); \ + __riscv_vse##width(ptr, a, vl); \ } \ inline void v_store_aligned(_Tp* ptr, const _Tpvec& a) \ { \ - vse##width(ptr, a, vl); \ + __riscv_vse##width(ptr, a, vl); \ } \ inline void v_store_aligned_nocache(_Tp* ptr, const _Tpvec& a) \ { \ - vse##width(ptr, a, vl); \ + __riscv_vse##width(ptr, a, vl); \ } \ inline void v_store_low(_Tp* ptr, const _Tpvec& a) \ { \ - vse##width(ptr, a, hvl); \ + __riscv_vse##width(ptr, a, hvl); \ } \ inline void v_store_high(_Tp* ptr, const _Tpvec& a) \ { \ - vse##width(ptr, vslidedown_vx_##suffix##m1(vmv(0, vl), a, hvl, vl), hvl); \ + __riscv_vse##width(ptr, __riscv_vslidedown_vx_##suffix##m1(a, hvl, vl), hvl); \ } \ template \ _Tpvec v_load_##suffix(Targs... nScalars) \ @@ -422,26 +409,26 @@ _Tpvec v_load_##suffix(Targs... nScalars) \ } -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_uint8, vuint8m1_t, uchar, VTraits::vlanes() / 2, VTraits::vlanes(), 8, u8, vmv_v_x_u8m1) -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_int8, vint8m1_t, schar, VTraits::vlanes() / 2, VTraits::vlanes(), 8, i8, vmv_v_x_i8m1) -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_uint16, vuint16m1_t, ushort, VTraits::vlanes() / 2, VTraits::vlanes(), 16, u16, vmv_v_x_u16m1) -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_int16, vint16m1_t, short, VTraits::vlanes() / 2, VTraits::vlanes(), 16, i16, vmv_v_x_i16m1) -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_uint32, vuint32m1_t, unsigned int, VTraits::vlanes() / 2, VTraits::vlanes(), 32, u32, vmv_v_x_u32m1) -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_int32, vint32m1_t, int, VTraits::vlanes() / 2, VTraits::vlanes(), 32, i32, vmv_v_x_i32m1) -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_uint64, vuint64m1_t, uint64, VTraits::vlanes() / 2, VTraits::vlanes(), 64, u64, vmv_v_x_u64m1) -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_int64, vint64m1_t, int64, VTraits::vlanes() / 2, VTraits::vlanes(), 64, i64, vmv_v_x_i64m1) -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_float32, vfloat32m1_t, float, VTraits::vlanes() /2 , VTraits::vlanes(), 32, f32, vfmv_v_f_f32m1) +OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_uint8, vuint8m1_t, uchar, VTraits::vlanes() / 2, VTraits::vlanes(), 8, u8) +OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_int8, vint8m1_t, schar, VTraits::vlanes() / 2, VTraits::vlanes(), 8, i8) +OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_uint16, vuint16m1_t, ushort, VTraits::vlanes() / 2, VTraits::vlanes(), 16, u16) +OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_int16, vint16m1_t, short, VTraits::vlanes() / 2, VTraits::vlanes(), 16, i16) +OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_uint32, vuint32m1_t, unsigned int, VTraits::vlanes() / 2, VTraits::vlanes(), 32, u32) +OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_int32, vint32m1_t, int, VTraits::vlanes() / 2, VTraits::vlanes(), 32, i32) +OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_uint64, vuint64m1_t, uint64, VTraits::vlanes() / 2, VTraits::vlanes(), 64, u64) +OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_int64, vint64m1_t, int64, VTraits::vlanes() / 2, VTraits::vlanes(), 64, i64) +OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_float32, vfloat32m1_t, float, VTraits::vlanes() /2 , VTraits::vlanes(), 32, f32) #if CV_SIMD_SCALABLE_64F -OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_float64, vfloat64m1_t, double, VTraits::vlanes() / 2, VTraits::vlanes(), 64, f64, vfmv_v_f_f64m1) +OPENCV_HAL_IMPL_RVV_LOADSTORE_OP(v_float64, vfloat64m1_t, double, VTraits::vlanes() / 2, VTraits::vlanes(), 64, f64) #endif ////////////// Lookup table access //////////////////// #define OPENCV_HAL_IMPL_RVV_LUT(_Tpvec, _Tp, suffix) \ inline _Tpvec v_lut(const _Tp* tab, const int* idx) \ { \ - auto vidx = vmul(vreinterpret_u32##suffix(vle32_v_i32##suffix(idx, VTraits<_Tpvec>::vlanes())), sizeof(_Tp), VTraits<_Tpvec>::vlanes()); \ - return vloxei32(tab, vidx, VTraits<_Tpvec>::vlanes()); \ + auto vidx = __riscv_vmul(__riscv_vreinterpret_u32##suffix(__riscv_vle32_v_i32##suffix(idx, VTraits<_Tpvec>::vlanes())), sizeof(_Tp), VTraits<_Tpvec>::vlanes()); \ + return __riscv_vloxei32(tab, vidx, VTraits<_Tpvec>::vlanes()); \ } OPENCV_HAL_IMPL_RVV_LUT(v_int8, schar, m4) OPENCV_HAL_IMPL_RVV_LUT(v_int16, short, m2) @@ -455,57 +442,57 @@ OPENCV_HAL_IMPL_RVV_LUT(v_float64, double, mf2) #define OPENCV_HAL_IMPL_RVV_LUT_PAIRS(_Tpvec, _Tp, suffix1, suffix2, v_trunc) \ inline _Tpvec v_lut_pairs(const _Tp* tab, const int* idx) \ { \ - auto v0 = vle32_v_u32##suffix1((unsigned*)idx, VTraits<_Tpvec>::vlanes()/2); \ - auto v1 = vadd(v0, 1, VTraits<_Tpvec>::vlanes()/2); \ - auto w0 = vwcvtu_x(v0, VTraits<_Tpvec>::vlanes()/2); \ - auto w1 = vwcvtu_x(v1, VTraits<_Tpvec>::vlanes()/2); \ - auto sh1 = vslide1up(v_trunc(vreinterpret_u32##suffix2(w1)),0, VTraits<_Tpvec>::vlanes()); \ - auto vid = vor(sh1, v_trunc(vreinterpret_u32##suffix2(w0)), VTraits<_Tpvec>::vlanes()); \ - auto vidx = vmul(vid, sizeof(_Tp), VTraits<_Tpvec>::vlanes()); \ - return vloxei32(tab, vidx, VTraits<_Tpvec>::vlanes()); \ + auto v0 = __riscv_vle32_v_u32##suffix1((unsigned*)idx, VTraits<_Tpvec>::vlanes()/2); \ + auto v1 = __riscv_vadd(v0, 1, VTraits<_Tpvec>::vlanes()/2); \ + auto w0 = __riscv_vwcvtu_x(v0, VTraits<_Tpvec>::vlanes()/2); \ + auto w1 = __riscv_vwcvtu_x(v1, VTraits<_Tpvec>::vlanes()/2); \ + auto sh1 = __riscv_vslide1up(v_trunc(__riscv_vreinterpret_u32##suffix2(w1)),0, VTraits<_Tpvec>::vlanes()); \ + auto vid = __riscv_vor(sh1, v_trunc(__riscv_vreinterpret_u32##suffix2(w0)), VTraits<_Tpvec>::vlanes()); \ + auto vidx = __riscv_vmul(vid, sizeof(_Tp), VTraits<_Tpvec>::vlanes()); \ + return __riscv_vloxei32(tab, vidx, VTraits<_Tpvec>::vlanes()); \ } OPENCV_HAL_IMPL_RVV_LUT_PAIRS(v_int8, schar, m2, m4, OPENCV_HAL_NOP) OPENCV_HAL_IMPL_RVV_LUT_PAIRS(v_int16, short, m1, m2, OPENCV_HAL_NOP) OPENCV_HAL_IMPL_RVV_LUT_PAIRS(v_int32, int, mf2, m1, OPENCV_HAL_NOP) OPENCV_HAL_IMPL_RVV_LUT_PAIRS(v_float32, float, mf2, m1, OPENCV_HAL_NOP) -OPENCV_HAL_IMPL_RVV_LUT_PAIRS(v_int64, int64_t, mf2, m1, vlmul_trunc_u32mf2) +OPENCV_HAL_IMPL_RVV_LUT_PAIRS(v_int64, int64_t, mf2, m1, __riscv_vlmul_trunc_u32mf2) #if CV_SIMD_SCALABLE_64F -OPENCV_HAL_IMPL_RVV_LUT_PAIRS(v_float64, double, mf2, m1, vlmul_trunc_u32mf2) +OPENCV_HAL_IMPL_RVV_LUT_PAIRS(v_float64, double, mf2, m1, __riscv_vlmul_trunc_u32mf2) #endif #define OPENCV_HAL_IMPL_RVV_LUT_QUADS(_Tpvec, _Tp, suffix0, suffix1, suffix2, v_trunc) \ inline _Tpvec v_lut_quads(const _Tp* tab, const int* idx) \ { \ - auto v0 = vle32_v_u32##suffix0((unsigned*)idx, VTraits<_Tpvec>::vlanes()/4); \ - auto v1 = vadd(v0, 1, VTraits<_Tpvec>::vlanes()/4); \ - auto v2 = vadd(v0, 2, VTraits<_Tpvec>::vlanes()/4); \ - auto v3 = vadd(v0, 3, VTraits<_Tpvec>::vlanes()/4); \ - auto w0 = vwcvtu_x(v0, VTraits<_Tpvec>::vlanes()/4); \ - auto w1 = vwcvtu_x(v1, VTraits<_Tpvec>::vlanes()/4); \ - auto w2 = vwcvtu_x(v2, VTraits<_Tpvec>::vlanes()/4); \ - auto w3 = vwcvtu_x(v3, VTraits<_Tpvec>::vlanes()/4); \ - auto sh2 = vslide1up(vreinterpret_u32##suffix1(w2),0, VTraits<_Tpvec>::vlanes()/2); \ - auto sh3 = vslide1up(vreinterpret_u32##suffix1(w3),0, VTraits<_Tpvec>::vlanes()/2); \ - auto vid0 = vor(sh2, vreinterpret_u32##suffix1(w0), VTraits<_Tpvec>::vlanes()/2); \ - auto vid1 = vor(sh3, vreinterpret_u32##suffix1(w1), VTraits<_Tpvec>::vlanes()/2); \ - auto wid0 = vwcvtu_x(v_trunc(vid0), VTraits<_Tpvec>::vlanes()/2); \ - auto wid1 = vwcvtu_x(v_trunc(vid1), VTraits<_Tpvec>::vlanes()/2); \ - auto shwid1 = vslide1up(vreinterpret_u32##suffix2(wid1),0, VTraits<_Tpvec>::vlanes()); \ - auto vid = vor(shwid1, vreinterpret_u32##suffix2(wid0), VTraits<_Tpvec>::vlanes()); \ - auto vidx = vmul(vid, sizeof(_Tp), VTraits<_Tpvec>::vlanes()); \ - return vloxei32(tab, vidx, VTraits<_Tpvec>::vlanes()); \ + auto v0 = __riscv_vle32_v_u32##suffix0((unsigned*)idx, VTraits<_Tpvec>::vlanes()/4); \ + auto v1 = __riscv_vadd(v0, 1, VTraits<_Tpvec>::vlanes()/4); \ + auto v2 = __riscv_vadd(v0, 2, VTraits<_Tpvec>::vlanes()/4); \ + auto v3 = __riscv_vadd(v0, 3, VTraits<_Tpvec>::vlanes()/4); \ + auto w0 = __riscv_vwcvtu_x(v0, VTraits<_Tpvec>::vlanes()/4); \ + auto w1 = __riscv_vwcvtu_x(v1, VTraits<_Tpvec>::vlanes()/4); \ + auto w2 = __riscv_vwcvtu_x(v2, VTraits<_Tpvec>::vlanes()/4); \ + auto w3 = __riscv_vwcvtu_x(v3, VTraits<_Tpvec>::vlanes()/4); \ + auto sh2 = __riscv_vslide1up(__riscv_vreinterpret_u32##suffix1(w2),0, VTraits<_Tpvec>::vlanes()/2); \ + auto sh3 = __riscv_vslide1up(__riscv_vreinterpret_u32##suffix1(w3),0, VTraits<_Tpvec>::vlanes()/2); \ + auto vid0 = __riscv_vor(sh2, __riscv_vreinterpret_u32##suffix1(w0), VTraits<_Tpvec>::vlanes()/2); \ + auto vid1 = __riscv_vor(sh3, __riscv_vreinterpret_u32##suffix1(w1), VTraits<_Tpvec>::vlanes()/2); \ + auto wid0 = __riscv_vwcvtu_x(v_trunc(vid0), VTraits<_Tpvec>::vlanes()/2); \ + auto wid1 = __riscv_vwcvtu_x(v_trunc(vid1), VTraits<_Tpvec>::vlanes()/2); \ + auto shwid1 = __riscv_vslide1up(__riscv_vreinterpret_u32##suffix2(wid1),0, VTraits<_Tpvec>::vlanes()); \ + auto vid = __riscv_vor(shwid1, __riscv_vreinterpret_u32##suffix2(wid0), VTraits<_Tpvec>::vlanes()); \ + auto vidx = __riscv_vmul(vid, sizeof(_Tp), VTraits<_Tpvec>::vlanes()); \ + return __riscv_vloxei32(tab, vidx, VTraits<_Tpvec>::vlanes()); \ } OPENCV_HAL_IMPL_RVV_LUT_QUADS(v_int8, schar, m1, m2, m4, OPENCV_HAL_NOP) OPENCV_HAL_IMPL_RVV_LUT_QUADS(v_int16, short, mf2 , m1, m2, OPENCV_HAL_NOP) -OPENCV_HAL_IMPL_RVV_LUT_QUADS(v_int32, int, mf2, m1, m1, vlmul_trunc_u32mf2) -OPENCV_HAL_IMPL_RVV_LUT_QUADS(v_float32, float, mf2, m1, m1, vlmul_trunc_u32mf2) +OPENCV_HAL_IMPL_RVV_LUT_QUADS(v_int32, int, mf2, m1, m1, __riscv_vlmul_trunc_u32mf2) +OPENCV_HAL_IMPL_RVV_LUT_QUADS(v_float32, float, mf2, m1, m1, __riscv_vlmul_trunc_u32mf2) #define OPENCV_HAL_IMPL_RVV_LUT_VEC(_Tpvec, _Tp) \ inline _Tpvec v_lut(const _Tp* tab, const v_int32& vidx) \ { \ - v_uint32 vidx_ = vmul(vreinterpret_u32m1(vidx), sizeof(_Tp), VTraits::vlanes()); \ - return vloxei32(tab, vidx_, VTraits<_Tpvec>::vlanes()); \ + v_uint32 vidx_ = __riscv_vmul(__riscv_vreinterpret_u32m1(vidx), sizeof(_Tp), VTraits::vlanes()); \ + return __riscv_vloxei32(tab, vidx_, VTraits<_Tpvec>::vlanes()); \ } OPENCV_HAL_IMPL_RVV_LUT_VEC(v_float32, float) OPENCV_HAL_IMPL_RVV_LUT_VEC(v_int32, int) @@ -514,8 +501,8 @@ OPENCV_HAL_IMPL_RVV_LUT_VEC(v_uint32, unsigned) #if CV_SIMD_SCALABLE_64F inline v_float64 v_lut(const double* tab, const v_int32& vidx) \ { \ - vuint32mf2_t vidx_ = vmul(vlmul_trunc_u32mf2(vreinterpret_u32m1(vidx)), sizeof(double), VTraits::vlanes()); \ - return vloxei32(tab, vidx_, VTraits::vlanes()); \ + vuint32mf2_t vidx_ = __riscv_vmul(__riscv_vlmul_trunc_u32mf2(__riscv_vreinterpret_u32m1(vidx)), sizeof(double), VTraits::vlanes()); \ + return __riscv_vloxei32(tab, vidx_, VTraits::vlanes()); \ } #endif @@ -535,22 +522,22 @@ inline v_uint64 v_lut_pairs(const uint64* tab, const int* idx) { return v_reinte ////////////// Pack boolean //////////////////// inline v_uint8 v_pack_b(const v_uint16& a, const v_uint16& b) { - return vnsrl(vset(vlmul_ext_v_u16m1_u16m2(a),1,b), 0, VTraits::vlanes()); + return __riscv_vnsrl(__riscv_vset(__riscv_vlmul_ext_v_u16m1_u16m2(a),1,b), 0, VTraits::vlanes()); } inline v_uint8 v_pack_b(const v_uint32& a, const v_uint32& b, const v_uint32& c, const v_uint32& d) { - return vnsrl(vnsrl(vset(vset(vset(vlmul_ext_u32m4(a),1,b),2,c),3,d), 0, VTraits::vlanes()), 0, VTraits::vlanes()); + return __riscv_vnsrl(__riscv_vnsrl(__riscv_vset(__riscv_vset(__riscv_vset(__riscv_vlmul_ext_u32m4(a),1,b),2,c),3,d), 0, VTraits::vlanes()), 0, VTraits::vlanes()); } inline v_uint8 v_pack_b(const v_uint64& a, const v_uint64& b, const v_uint64& c, const v_uint64& d, const v_uint64& e, const v_uint64& f, const v_uint64& g, const v_uint64& h) { - return vnsrl(vnsrl(vnsrl( - vset(vset(vset(vset(vset(vset(vset(vlmul_ext_u64m8(a), + return __riscv_vnsrl(__riscv_vnsrl(__riscv_vnsrl( + __riscv_vset(__riscv_vset(__riscv_vset(__riscv_vset(__riscv_vset(__riscv_vset(__riscv_vset(__riscv_vlmul_ext_u64m8(a), 1,b),2,c),3,d),4,e),5,f),6,g),7,h), 0, VTraits::vlanes()), 0, VTraits::vlanes()), 0, VTraits::vlanes()); } @@ -562,34 +549,34 @@ inline _Tpvec v_##ocv_intrin(const _Tpvec& a, const _Tpvec& b) \ return rvv_intrin(a, b, VTraits<_Tpvec>::vlanes()); \ } -OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint8, add, vsaddu) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint8, sub, vssubu) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_int8, add, vsadd) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_int8, sub, vssub) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint16, add, vsaddu) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint16, sub, vssubu) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_int16, add, vsadd) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_int16, sub, vssub) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint32, add, vadd) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint32, sub, vsub) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint32, mul, vmul) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_int32, add, vadd) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_int32, sub, vsub) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_int32, mul, vmul) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_float32, add, vfadd) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_float32, sub, vfsub) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_float32, mul, vfmul) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_float32, div, vfdiv) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint64, add, vadd) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint64, sub, vsub) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_int64, add, vadd) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_int64, sub, vsub) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint8, add, __riscv_vsaddu) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint8, sub, __riscv_vssubu) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_int8, add, __riscv_vsadd) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_int8, sub, __riscv_vssub) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint16, add, __riscv_vsaddu) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint16, sub, __riscv_vssubu) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_int16, add, __riscv_vsadd) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_int16, sub, __riscv_vssub) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint32, add, __riscv_vadd) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint32, sub, __riscv_vsub) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint32, mul, __riscv_vmul) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_int32, add, __riscv_vadd) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_int32, sub, __riscv_vsub) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_int32, mul, __riscv_vmul) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_float32, add, __riscv_vfadd) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_float32, sub, __riscv_vfsub) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_float32, mul, __riscv_vfmul) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_float32, div, __riscv_vfdiv) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint64, add, __riscv_vadd) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint64, sub, __riscv_vsub) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_int64, add, __riscv_vadd) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_int64, sub, __riscv_vsub) #if CV_SIMD_SCALABLE_64F -OPENCV_HAL_IMPL_RVV_BIN_OP(v_float64, add, vfadd) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_float64, sub, vfsub) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_float64, mul, vfmul) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_float64, div, vfdiv) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_float64, add, __riscv_vfadd) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_float64, sub, __riscv_vfsub) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_float64, mul, __riscv_vfmul) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_float64, div, __riscv_vfdiv) #endif #define OPENCV_HAL_IMPL_RVV_BIN_MADD(_Tpvec, rvv_add) \ @@ -602,95 +589,95 @@ template \ inline _Tpvec v_mul(const _Tpvec& f1, const _Tpvec& f2, const Args&... vf) { \ return v_mul(rvv_mul(f1, f2, VTraits<_Tpvec>::vlanes()), vf...); \ } -OPENCV_HAL_IMPL_RVV_BIN_MADD(v_uint8, vsaddu) -OPENCV_HAL_IMPL_RVV_BIN_MADD(v_int8, vsadd) -OPENCV_HAL_IMPL_RVV_BIN_MADD(v_uint16, vsaddu) -OPENCV_HAL_IMPL_RVV_BIN_MADD(v_int16, vsadd) -OPENCV_HAL_IMPL_RVV_BIN_MADD(v_uint32, vadd) -OPENCV_HAL_IMPL_RVV_BIN_MADD(v_int32, vadd) -OPENCV_HAL_IMPL_RVV_BIN_MADD(v_float32, vfadd) -OPENCV_HAL_IMPL_RVV_BIN_MADD(v_uint64, vadd) -OPENCV_HAL_IMPL_RVV_BIN_MADD(v_int64, vadd) - -OPENCV_HAL_IMPL_RVV_BIN_MMUL(v_uint32, vmul) -OPENCV_HAL_IMPL_RVV_BIN_MMUL(v_int32, vmul) -OPENCV_HAL_IMPL_RVV_BIN_MMUL(v_float32, vfmul) +OPENCV_HAL_IMPL_RVV_BIN_MADD(v_uint8, __riscv_vsaddu) +OPENCV_HAL_IMPL_RVV_BIN_MADD(v_int8, __riscv_vsadd) +OPENCV_HAL_IMPL_RVV_BIN_MADD(v_uint16, __riscv_vsaddu) +OPENCV_HAL_IMPL_RVV_BIN_MADD(v_int16, __riscv_vsadd) +OPENCV_HAL_IMPL_RVV_BIN_MADD(v_uint32, __riscv_vadd) +OPENCV_HAL_IMPL_RVV_BIN_MADD(v_int32, __riscv_vadd) +OPENCV_HAL_IMPL_RVV_BIN_MADD(v_float32, __riscv_vfadd) +OPENCV_HAL_IMPL_RVV_BIN_MADD(v_uint64, __riscv_vadd) +OPENCV_HAL_IMPL_RVV_BIN_MADD(v_int64, __riscv_vadd) + +OPENCV_HAL_IMPL_RVV_BIN_MMUL(v_uint32, __riscv_vmul) +OPENCV_HAL_IMPL_RVV_BIN_MMUL(v_int32, __riscv_vmul) +OPENCV_HAL_IMPL_RVV_BIN_MMUL(v_float32, __riscv_vfmul) #if CV_SIMD_SCALABLE_64F -OPENCV_HAL_IMPL_RVV_BIN_MADD(v_float64, vfadd) -OPENCV_HAL_IMPL_RVV_BIN_MMUL(v_float64, vfmul) +OPENCV_HAL_IMPL_RVV_BIN_MADD(v_float64, __riscv_vfadd) +OPENCV_HAL_IMPL_RVV_BIN_MMUL(v_float64, __riscv_vfmul) #endif #define OPENCV_HAL_IMPL_RVV_MUL_EXPAND(_Tpvec, _Tpwvec, _TpwvecM2, suffix, wmul) \ inline void v_mul_expand(const _Tpvec& a, const _Tpvec& b, _Tpwvec& c, _Tpwvec& d) \ { \ _TpwvecM2 temp = wmul(a, b, VTraits<_Tpvec>::vlanes()); \ - c = vget_##suffix##m1(temp, 0); \ - d = vget_##suffix##m1(temp, 1); \ + c = __riscv_vget_##suffix##m1(temp, 0); \ + d = __riscv_vget_##suffix##m1(temp, 1); \ } -OPENCV_HAL_IMPL_RVV_MUL_EXPAND(v_uint8, v_uint16, vuint16m2_t, u16, vwmulu) -OPENCV_HAL_IMPL_RVV_MUL_EXPAND(v_int8, v_int16, vint16m2_t, i16, vwmul) -OPENCV_HAL_IMPL_RVV_MUL_EXPAND(v_uint16, v_uint32, vuint32m2_t, u32, vwmulu) -OPENCV_HAL_IMPL_RVV_MUL_EXPAND(v_int16, v_int32, vint32m2_t, i32, vwmul) -OPENCV_HAL_IMPL_RVV_MUL_EXPAND(v_uint32, v_uint64, vuint64m2_t, u64, vwmulu) +OPENCV_HAL_IMPL_RVV_MUL_EXPAND(v_uint8, v_uint16, vuint16m2_t, u16, __riscv_vwmulu) +OPENCV_HAL_IMPL_RVV_MUL_EXPAND(v_int8, v_int16, vint16m2_t, i16, __riscv_vwmul) +OPENCV_HAL_IMPL_RVV_MUL_EXPAND(v_uint16, v_uint32, vuint32m2_t, u32, __riscv_vwmulu) +OPENCV_HAL_IMPL_RVV_MUL_EXPAND(v_int16, v_int32, vint32m2_t, i32, __riscv_vwmul) +OPENCV_HAL_IMPL_RVV_MUL_EXPAND(v_uint32, v_uint64, vuint64m2_t, u64, __riscv_vwmulu) inline v_int16 v_mul_hi(const v_int16& a, const v_int16& b) { - return vmulh(a, b, VTraits::vlanes()); + return __riscv_vmulh(a, b, VTraits::vlanes()); } inline v_uint16 v_mul_hi(const v_uint16& a, const v_uint16& b) { - return vmulhu(a, b, VTraits::vlanes()); + return __riscv_vmulhu(a, b, VTraits::vlanes()); } ////////////// Arithmetics (wrap)////////////// -OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint8, add_wrap, vadd) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_int8, add_wrap, vadd) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint16, add_wrap, vadd) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_int16, add_wrap, vadd) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint8, sub_wrap, vsub) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_int8, sub_wrap, vsub) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint16, sub_wrap, vsub) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_int16, sub_wrap, vsub) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint8, mul_wrap, vmul) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_int8, mul_wrap, vmul) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint16, mul_wrap, vmul) -OPENCV_HAL_IMPL_RVV_BIN_OP(v_int16, mul_wrap, vmul) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint8, add_wrap, __riscv_vadd) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_int8, add_wrap, __riscv_vadd) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint16, add_wrap, __riscv_vadd) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_int16, add_wrap, __riscv_vadd) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint8, sub_wrap, __riscv_vsub) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_int8, sub_wrap, __riscv_vsub) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint16, sub_wrap, __riscv_vsub) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_int16, sub_wrap, __riscv_vsub) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint8, mul_wrap, __riscv_vmul) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_int8, mul_wrap, __riscv_vmul) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_uint16, mul_wrap, __riscv_vmul) +OPENCV_HAL_IMPL_RVV_BIN_OP(v_int16, mul_wrap, __riscv_vmul) //////// Saturating Multiply //////// #define OPENCV_HAL_IMPL_RVV_MUL_SAT(_Tpvec, _clip, _wmul) \ inline _Tpvec v_mul(const _Tpvec& a, const _Tpvec& b) \ { \ - return _clip(_wmul(a, b, VTraits<_Tpvec>::vlanes()), 0, VTraits<_Tpvec>::vlanes()); \ + return _clip(_wmul(a, b, VTraits<_Tpvec>::vlanes()), 0, 0, VTraits<_Tpvec>::vlanes()); \ } \ template \ inline _Tpvec v_mul(const _Tpvec& a1, const _Tpvec& a2, const Args&... va) { \ - return v_mul(_clip(_wmul(a1, a2, VTraits<_Tpvec>::vlanes()), 0, VTraits<_Tpvec>::vlanes()), va...); \ + return v_mul(_clip(_wmul(a1, a2, VTraits<_Tpvec>::vlanes()), 0, 0, VTraits<_Tpvec>::vlanes()), va...); \ } -OPENCV_HAL_IMPL_RVV_MUL_SAT(v_uint8, vnclipu, vwmulu) -OPENCV_HAL_IMPL_RVV_MUL_SAT(v_int8, vnclip, vwmul) -OPENCV_HAL_IMPL_RVV_MUL_SAT(v_uint16, vnclipu, vwmulu) -OPENCV_HAL_IMPL_RVV_MUL_SAT(v_int16, vnclip, vwmul) +OPENCV_HAL_IMPL_RVV_MUL_SAT(v_uint8, __riscv_vnclipu, __riscv_vwmulu) +OPENCV_HAL_IMPL_RVV_MUL_SAT(v_int8, __riscv_vnclip, __riscv_vwmul) +OPENCV_HAL_IMPL_RVV_MUL_SAT(v_uint16, __riscv_vnclipu, __riscv_vwmulu) +OPENCV_HAL_IMPL_RVV_MUL_SAT(v_int16, __riscv_vnclip, __riscv_vwmul) ////////////// Bitwise logic ////////////// #define OPENCV_HAL_IMPL_RVV_LOGIC_OP(_Tpvec, vl) \ inline _Tpvec v_and(const _Tpvec& a, const _Tpvec& b) \ { \ - return vand(a, b, vl); \ + return __riscv_vand(a, b, vl); \ } \ inline _Tpvec v_or(const _Tpvec& a, const _Tpvec& b) \ { \ - return vor(a, b, vl); \ + return __riscv_vor(a, b, vl); \ } \ inline _Tpvec v_xor(const _Tpvec& a, const _Tpvec& b) \ { \ - return vxor(a, b, vl); \ + return __riscv_vxor(a, b, vl); \ } \ inline _Tpvec v_not (const _Tpvec& a) \ { \ - return vnot(a, vl); \ + return __riscv_vnot(a, vl); \ } OPENCV_HAL_IMPL_RVV_LOGIC_OP(v_uint8, VTraits::vlanes()) @@ -705,7 +692,7 @@ OPENCV_HAL_IMPL_RVV_LOGIC_OP(v_int64, VTraits::vlanes()) #define OPENCV_HAL_IMPL_RVV_FLT_BIT_OP(intrin) \ inline v_float32 intrin (const v_float32& a, const v_float32& b) \ { \ - return vreinterpret_f32m1(intrin(vreinterpret_i32m1(a), vreinterpret_i32m1(b))); \ + return __riscv_vreinterpret_f32m1(intrin(__riscv_vreinterpret_i32m1(a), __riscv_vreinterpret_i32m1(b))); \ } OPENCV_HAL_IMPL_RVV_FLT_BIT_OP(v_and) OPENCV_HAL_IMPL_RVV_FLT_BIT_OP(v_or) @@ -713,14 +700,14 @@ OPENCV_HAL_IMPL_RVV_FLT_BIT_OP(v_xor) inline v_float32 v_not (const v_float32& a) \ { \ - return vreinterpret_f32m1(v_not(vreinterpret_i32m1(a))); \ + return __riscv_vreinterpret_f32m1(v_not(__riscv_vreinterpret_i32m1(a))); \ } #if CV_SIMD_SCALABLE_64F #define OPENCV_HAL_IMPL_RVV_FLT64_BIT_OP(intrin) \ inline v_float64 intrin (const v_float64& a, const v_float64& b) \ { \ - return vreinterpret_f64m1(intrin(vreinterpret_i64m1(a), vreinterpret_i64m1(b))); \ + return __riscv_vreinterpret_f64m1(intrin(__riscv_vreinterpret_i64m1(a), __riscv_vreinterpret_i64m1(b))); \ } OPENCV_HAL_IMPL_RVV_FLT64_BIT_OP(v_and) OPENCV_HAL_IMPL_RVV_FLT64_BIT_OP(v_or) @@ -728,7 +715,7 @@ OPENCV_HAL_IMPL_RVV_FLT64_BIT_OP(v_xor) inline v_float64 v_not (const v_float64& a) \ { \ - return vreinterpret_f64m1(v_not(vreinterpret_i64m1(a))); \ + return __riscv_vreinterpret_f64m1(v_not(__riscv_vreinterpret_i64m1(a))); \ } #endif @@ -742,21 +729,21 @@ inline v_float64 v_not (const v_float64& a) \ #define OPENCV_HAL_IMPL_RVV_UNSIGNED_SHIFT_OP(_Tpvec, vl) \ template inline _Tpvec v_shl(const _Tpvec& a, int n = s) \ { \ - return _Tpvec(vsll(a, uint8_t(n), vl)); \ + return _Tpvec(__riscv_vsll(a, uint8_t(n), vl)); \ } \ template inline _Tpvec v_shr(const _Tpvec& a, int n = s) \ { \ - return _Tpvec(vsrl(a, uint8_t(n), vl)); \ + return _Tpvec(__riscv_vsrl(a, uint8_t(n), vl)); \ } #define OPENCV_HAL_IMPL_RVV_SIGNED_SHIFT_OP(_Tpvec, vl) \ template inline _Tpvec v_shl(const _Tpvec& a, int n = s) \ { \ - return _Tpvec(vsll(a, uint8_t(n), vl)); \ + return _Tpvec(__riscv_vsll(a, uint8_t(n), vl)); \ } \ template inline _Tpvec v_shr(const _Tpvec& a, int n = s) \ { \ - return _Tpvec(vsra(a, uint8_t(n), vl)); \ + return _Tpvec(__riscv_vsra(a, uint8_t(n), vl)); \ } OPENCV_HAL_IMPL_RVV_UNSIGNED_SHIFT_OP(v_uint16, VTraits::vlanes()) @@ -772,7 +759,7 @@ inline _Tpvec v_##op(const _Tpvec& a, const _Tpvec& b) \ { \ size_t VLEN = VTraits<_Tpvec>::vlanes(); \ uint64_t ones = -1; \ - return vmerge(intrin(a, b, VLEN), vmv_v_x_##suffix##m1(0, VLEN), ones, VLEN); \ + return __riscv_vmerge(__riscv_vmv_v_x_##suffix##m1(0, VLEN), ones, intrin(a, b, VLEN), VLEN); \ } #define OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, op, intrin, suffix) \ @@ -782,34 +769,34 @@ inline _Tpvec v_##op (const _Tpvec& a, const _Tpvec& b) \ union { uint64_t u; VTraits<_Tpvec>::lane_type d; } ones; \ ones.u = -1; \ auto diff = intrin(a, b, VLEN); \ - auto z = vfmv_v_f_##suffix##m1(0, VLEN); \ - auto res = vfmerge(diff, z, ones.d, VLEN); \ + auto z = __riscv_vfmv_v_f_##suffix##m1(0, VLEN); \ + auto res = __riscv_vfmerge(z, ones.d, diff, VLEN); \ return _Tpvec(res); \ } //TODO #define OPENCV_HAL_IMPL_RVV_UNSIGNED_CMP(_Tpvec, suffix) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, eq, vmseq, suffix) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, ne, vmsne, suffix) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, lt, vmsltu, suffix) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, gt, vmsgtu, suffix) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, le, vmsleu, suffix) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, ge, vmsgeu, suffix) +OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, eq, __riscv_vmseq, suffix) \ +OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, ne, __riscv_vmsne, suffix) \ +OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, lt, __riscv_vmsltu, suffix) \ +OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, gt, __riscv_vmsgtu, suffix) \ +OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, le, __riscv_vmsleu, suffix) \ +OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, ge, __riscv_vmsgeu, suffix) #define OPENCV_HAL_IMPL_RVV_SIGNED_CMP(_Tpvec, suffix) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, eq, vmseq, suffix) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, ne, vmsne, suffix) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, lt, vmslt, suffix) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, gt, vmsgt, suffix) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, le, vmsle, suffix) \ -OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, ge, vmsge, suffix) +OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, eq, __riscv_vmseq, suffix) \ +OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, ne, __riscv_vmsne, suffix) \ +OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, lt, __riscv_vmslt, suffix) \ +OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, gt, __riscv_vmsgt, suffix) \ +OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, le, __riscv_vmsle, suffix) \ +OPENCV_HAL_IMPL_RVV_INT_CMP_OP(_Tpvec, ge, __riscv_vmsge, suffix) #define OPENCV_HAL_IMPL_RVV_FLOAT_CMP(_Tpvec, suffix) \ -OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, eq, vmfeq, suffix) \ -OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, ne, vmfne, suffix) \ -OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, lt, vmflt, suffix) \ -OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, gt, vmfgt, suffix) \ -OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, le, vmfle, suffix) \ -OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, ge, vmfge, suffix) +OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, eq, __riscv_vmfeq, suffix) \ +OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, ne, __riscv_vmfne, suffix) \ +OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, lt, __riscv_vmflt, suffix) \ +OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, gt, __riscv_vmfgt, suffix) \ +OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, le, __riscv_vmfle, suffix) \ +OPENCV_HAL_IMPL_RVV_FLOAT_CMP_OP(_Tpvec, ge, __riscv_vmfge, suffix) OPENCV_HAL_IMPL_RVV_UNSIGNED_CMP(v_uint8, u8) @@ -841,98 +828,98 @@ inline _Tpvec func(const _Tpvec& a, const _Tpvec& b) \ return intrin(a, b, vl); \ } -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint8, v_min, vminu, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint8, v_max, vmaxu, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int8, v_min, vmin, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int8, v_max, vmax, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint16, v_min, vminu, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint16, v_max, vmaxu, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int16, v_min, vmin, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int16, v_max, vmax, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint32, v_min, vminu, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint32, v_max, vmaxu, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int32, v_min, vmin, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int32, v_max, vmax, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_float32, v_min, vfmin, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_float32, v_max, vfmax, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint8, v_min, __riscv_vminu, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint8, v_max, __riscv_vmaxu, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int8, v_min, __riscv_vmin, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int8, v_max, __riscv_vmax, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint16, v_min, __riscv_vminu, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint16, v_max, __riscv_vmaxu, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int16, v_min, __riscv_vmin, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int16, v_max, __riscv_vmax, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint32, v_min, __riscv_vminu, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_uint32, v_max, __riscv_vmaxu, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int32, v_min, __riscv_vmin, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_int32, v_max, __riscv_vmax, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_float32, v_min, __riscv_vfmin, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_float32, v_max, __riscv_vfmax, VTraits::vlanes()) #if CV_SIMD_SCALABLE_64F -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_float64, v_min, vfmin, VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_float64, v_max, vfmax, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_float64, v_min, __riscv_vfmin, VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_BIN_FUNC(v_float64, v_max, __riscv_vfmax, VTraits::vlanes()) #endif ////////////// Transpose4x4 ////////////// #define OPENCV_HAL_IMPL_RVV_ZIP4(_Tpvec, _wTpvec, suffix, convert2u, convert) \ inline void v_zip4(const _Tpvec& a0, const _Tpvec& a1, _Tpvec& b0, _Tpvec& b1) { \ int vl = 4; \ - _wTpvec temp = vreinterpret_##suffix##m2(convert2u( \ - vor(vzext_vf2(convert(a0), vl), \ - vreinterpret_u64m2(vslide1up(vreinterpret_u32m2(vzext_vf2(convert(a1), vl)), 0, vl*2)), \ + _wTpvec temp = __riscv_vreinterpret_##suffix##m2(convert2u( \ + __riscv_vor(__riscv_vzext_vf2(convert(a0), vl), \ + __riscv_vreinterpret_u64m2(__riscv_vslide1up(__riscv_vreinterpret_u32m2(__riscv_vzext_vf2(convert(a1), vl)), 0, vl*2)), \ vl))); \ - b0 = vget_##suffix##m1(temp, 0); \ - b1 = vget_##suffix##m1(vrgather(temp, vadd(vid_v_u32m2(vl), 4, vl)/*{4,5,6,7} */, vl) ,0); \ + b0 = __riscv_vget_##suffix##m1(temp, 0); \ + b1 = __riscv_vget_##suffix##m1(__riscv_vrgather(temp, __riscv_vadd(__riscv_vid_v_u32m2(vl), 4, vl)/*{4,5,6,7} */, vl) ,0); \ } OPENCV_HAL_IMPL_RVV_ZIP4(v_uint32, vuint32m2_t, u32, OPENCV_HAL_NOP, OPENCV_HAL_NOP) -OPENCV_HAL_IMPL_RVV_ZIP4(v_int32, vint32m2_t, i32, vreinterpret_u32m2, vreinterpret_u32m1) -OPENCV_HAL_IMPL_RVV_ZIP4(v_float32, vfloat32m2_t, f32, vreinterpret_u32m2, vreinterpret_u32m1) +OPENCV_HAL_IMPL_RVV_ZIP4(v_int32, vint32m2_t, i32, __riscv_vreinterpret_u32m2, __riscv_vreinterpret_u32m1) +OPENCV_HAL_IMPL_RVV_ZIP4(v_float32, vfloat32m2_t, f32, __riscv_vreinterpret_u32m2, __riscv_vreinterpret_u32m1) #if 0 // this is v_zip4 and v_tranpose4x4 for scalable VLEN, costs more instruction than current 128-bit only version. inline void v_zip4(const v_float32& a0, const v_float32& a1, v_float32& b0, v_float32& b1) { - vuint64m1_t vid1 = vid_v_u64m1(VTraits::vlanes()); - vuint16m1_t t1 = vreinterpret_u16m1(vid1); - vuint16m1_t t2 = vslide1up(t1, 0, VTraits::vlanes()); - vuint16m1_t t3 = vslide1up(t2, 0, VTraits::vlanes()); - vuint16m1_t t4 = vslide1up(t3, 0, VTraits::vlanes()); - t1 = vor( - vor(t1, t2, VTraits::vlanes()), - vor(t3, t4, VTraits::vlanes()), + vuint64m1_t vid1 = __riscv_vid_v_u64m1(VTraits::vlanes()); + vuint16m1_t t1 = __riscv_vreinterpret_u16m1(vid1); + vuint16m1_t t2 = __riscv_vslide1up(t1, 0, VTraits::vlanes()); + vuint16m1_t t3 = __riscv_vslide1up(t2, 0, VTraits::vlanes()); + vuint16m1_t t4 = __riscv_vslide1up(t3, 0, VTraits::vlanes()); + t1 = __riscv_vor( + __riscv_vor(t1, t2, VTraits::vlanes()), + __riscv_vor(t3, t4, VTraits::vlanes()), VTraits::vlanes() ); - vuint32m2_t vidx0 = vwmulu(t1, 4, VTraits::vlanes()); - vidx0 = vadd(vidx0, vid_v_u32m2(VTraits::vlanes()), VTraits::vlanes()); - vuint32m2_t vidx1 = vadd(vidx0, 4, VTraits::vlanes()); - vfloat32m2_t temp = vreinterpret_f32m2(vreinterpret_u32m2( - vor(vzext_vf2(vreinterpret_u32m1(a0), VTraits::vlanes()), - vreinterpret_u64m2(vslide1up(vreinterpret_u32m2(vzext_vf2(vreinterpret_u32m1(a1), VTraits::vlanes())), 0, VTraits::vlanes()*2)), + vuint32m2_t vidx0 = __riscv_vwmulu(t1, 4, VTraits::vlanes()); + vidx0 = __riscv_vadd(vidx0, __riscv_vid_v_u32m2(VTraits::vlanes()), VTraits::vlanes()); + vuint32m2_t vidx1 = __riscv_vadd(vidx0, 4, VTraits::vlanes()); + vfloat32m2_t temp = __riscv_vreinterpret_f32m2(__riscv_vreinterpret_u32m2( + __riscv_vor(__riscv_vzext_vf2(__riscv_vreinterpret_u32m1(a0), VTraits::vlanes()), + __riscv_vreinterpret_u64m2(__riscv_vslide1up(__riscv_vreinterpret_u32m2(__riscv_vzext_vf2(__riscv_vreinterpret_u32m1(a1), VTraits::vlanes())), 0, VTraits::vlanes()*2)), VTraits::vlanes()))); - b0 = vlmul_trunc_f32m1(vrgather(temp, vidx0, VTraits::vlanes())); - b1 = vlmul_trunc_f32m1(vrgather(temp, vidx1, VTraits::vlanes())); + b0 = __riscv_vlmul_trunc_f32m1(__riscv_vrgather(temp, vidx0, VTraits::vlanes())); + b1 = __riscv_vlmul_trunc_f32m1(__riscv_vrgather(temp, vidx1, VTraits::vlanes())); } inline void v_transpose4x4(const v_float32& a0, const v_float32& a1, const v_float32& a2, const v_float32& a3,\ v_float32& b0, v_float32& b1, v_float32& b2, v_float32& b3) { \ - vuint64m2_t vid1 = vid_v_u64m2(VTraits::vlanes()); - vuint16m2_t t1 = vreinterpret_u16m2(vid1); - vuint16m2_t t2 = vslide1up(t1, 0, VTraits::vlanes()); - vuint16m2_t t3 = vslide1up(t2, 0, VTraits::vlanes()); - vuint16m2_t t4 = vslide1up(t3, 0, VTraits::vlanes()); - t1 = vor( - vor(t1, t2, VTraits::vlanes()), - vor(t3, t4, VTraits::vlanes()), + vuint64m2_t vid1 = __riscv_vid_v_u64m2(VTraits::vlanes()); + vuint16m2_t t1 = __riscv_vreinterpret_u16m2(vid1); + vuint16m2_t t2 = __riscv_vslide1up(t1, 0, VTraits::vlanes()); + vuint16m2_t t3 = __riscv_vslide1up(t2, 0, VTraits::vlanes()); + vuint16m2_t t4 = __riscv_vslide1up(t3, 0, VTraits::vlanes()); + t1 = __riscv_vor( + __riscv_vor(t1, t2, VTraits::vlanes()), + __riscv_vor(t3, t4, VTraits::vlanes()), VTraits::vlanes() ); - vuint16m2_t vidx0 = vmul(t1, 12, VTraits::vlanes()); - vidx0 = vadd(vidx0, vid_v_u16m2(VTraits::vlanes()), VTraits::vlanes()); - vuint16m2_t vidx1 = vadd(vidx0, 4, VTraits::vlanes()); - vuint16m2_t vidx2 = vadd(vidx0, 8, VTraits::vlanes()); - vuint16m2_t vidx3 = vadd(vidx0, 12, VTraits::vlanes()); - vuint32m2_t tempA = vreinterpret_u32m2( \ - vor(vzext_vf2(vreinterpret_u32m1(a0), VTraits::vlanes()), \ - vreinterpret_u64m2(vslide1up(vreinterpret_u32m2(vzext_vf2(vreinterpret_u32m1(a2), VTraits::vlanes())), 0, VTraits::vlanes())), \ + vuint16m2_t vidx0 = __riscv_vmul(t1, 12, VTraits::vlanes()); + vidx0 = __riscv_vadd(vidx0, __riscv_vid_v_u16m2(VTraits::vlanes()), VTraits::vlanes()); + vuint16m2_t vidx1 = __riscv_vadd(vidx0, 4, VTraits::vlanes()); + vuint16m2_t vidx2 = __riscv_vadd(vidx0, 8, VTraits::vlanes()); + vuint16m2_t vidx3 = __riscv_vadd(vidx0, 12, VTraits::vlanes()); + vuint32m2_t tempA = __riscv_vreinterpret_u32m2( \ + __riscv_vor(__riscv_vzext_vf2(__riscv_vreinterpret_u32m1(a0), VTraits::vlanes()), \ + __riscv_vreinterpret_u64m2(__riscv_vslide1up(__riscv_vreinterpret_u32m2(__riscv_vzext_vf2(__riscv_vreinterpret_u32m1(a2), VTraits::vlanes())), 0, VTraits::vlanes())), \ VTraits::vlanes())); \ - vuint32m2_t tempB = vreinterpret_u32m2( \ - vor(vzext_vf2(vreinterpret_u32m1(a1), VTraits::vlanes()), \ - vreinterpret_u64m2(vslide1up(vreinterpret_u32m2(vzext_vf2(vreinterpret_u32m1(a3), VTraits::vlanes())), 0, VTraits::vlanes())), \ + vuint32m2_t tempB = __riscv_vreinterpret_u32m2( \ + __riscv_vor(__riscv_vzext_vf2(__riscv_vreinterpret_u32m1(a1), VTraits::vlanes()), \ + __riscv_vreinterpret_u64m2(__riscv_vslide1up(__riscv_vreinterpret_u32m2(__riscv_vzext_vf2(__riscv_vreinterpret_u32m1(a3), VTraits::vlanes())), 0, VTraits::vlanes())), \ VTraits::vlanes())); \ - vfloat32m4_t temp = vreinterpret_f32m4(vreinterpret_u32m4( \ - vor(vzext_vf2(tempA, VTraits::vlanes()), \ - vreinterpret_u64m4(vslide1up(vreinterpret_u32m4(vzext_vf2(tempB, VTraits::vlanes())), 0, VTraits::vlanes())), \ + vfloat32m4_t temp = __riscv_vreinterpret_f32m4(__riscv_vreinterpret_u32m4( \ + __riscv_vor(__riscv_vzext_vf2(tempA, VTraits::vlanes()), \ + __riscv_vreinterpret_u64m4(__riscv_vslide1up(__riscv_vreinterpret_u32m4(__riscv_vzext_vf2(tempB, VTraits::vlanes())), 0, VTraits::vlanes())), \ VTraits::vlanes()))); \ - b0 = vlmul_trunc_f32m1(vrgatherei16(temp, vidx0, VTraits::vlanes())); - b1 = vlmul_trunc_f32m1(vrgatherei16(temp, vidx1, VTraits::vlanes())); - b2 = vlmul_trunc_f32m1(vrgatherei16(temp, vidx2, VTraits::vlanes())); - b3 = vlmul_trunc_f32m1(vrgatherei16(temp, vidx3, VTraits::vlanes())); + b0 = __riscv_vlmul_trunc_f32m1(__riscv_vrgatherei16(temp, vidx0, VTraits::vlanes())); + b1 = __riscv_vlmul_trunc_f32m1(__riscv_vrgatherei16(temp, vidx1, VTraits::vlanes())); + b2 = __riscv_vlmul_trunc_f32m1(__riscv_vrgatherei16(temp, vidx2, VTraits::vlanes())); + b3 = __riscv_vlmul_trunc_f32m1(__riscv_vrgatherei16(temp, vidx3, VTraits::vlanes())); } #endif @@ -954,9 +941,9 @@ OPENCV_HAL_IMPL_RVV_TRANSPOSE4x4(v_float32, f32) #define OPENCV_HAL_IMPL_RVV_REDUCE_SUM(_Tpvec, _wTpvec, _nwTpvec, scalartype, wsuffix, vl, red) \ inline scalartype v_reduce_sum(const _Tpvec& a) \ { \ - _nwTpvec zero = vmv_v_x_##wsuffix##m1(0, vl); \ - _nwTpvec res = vmv_v_x_##wsuffix##m1(0, vl); \ - res = v##red(res, a, zero, vl); \ + _nwTpvec zero = __riscv_vmv_v_x_##wsuffix##m1(0, vl); \ + _nwTpvec res = __riscv_vmv_v_x_##wsuffix##m1(0, vl); \ + res = __riscv_v##red(a, zero, vl); \ return (scalartype)v_get0(res); \ } OPENCV_HAL_IMPL_RVV_REDUCE_SUM(v_uint8, v_uint16, vuint16m1_t, unsigned, u16, VTraits::vlanes(), wredsumu) @@ -972,9 +959,9 @@ OPENCV_HAL_IMPL_RVV_REDUCE_SUM(v_int64, v_int64, vint64m1_t, int64, i64, VTraits #define OPENCV_HAL_IMPL_RVV_REDUCE_SUM_FP(_Tpvec, _wTpvec, _nwTpvec, scalartype, wsuffix, vl) \ inline scalartype v_reduce_sum(const _Tpvec& a) \ { \ - _nwTpvec zero = vfmv_v_f_##wsuffix##m1(0, vl); \ - _nwTpvec res = vfmv_v_f_##wsuffix##m1(0, vl); \ - res = vfredosum(res, a, zero, vl); \ + _nwTpvec zero = __riscv_vfmv_v_f_##wsuffix##m1(0, vl); \ + _nwTpvec res = __riscv_vfmv_v_f_##wsuffix##m1(0, vl); \ + res = __riscv_vfredusum(a, zero, vl); \ return (scalartype)v_get0(res); \ } OPENCV_HAL_IMPL_RVV_REDUCE_SUM_FP(v_float32, v_float32, vfloat32m1_t, float, f32, VTraits::vlanes()) @@ -985,7 +972,7 @@ OPENCV_HAL_IMPL_RVV_REDUCE_SUM_FP(v_float64, v_float64, vfloat64m1_t, float, f64 #define OPENCV_HAL_IMPL_RVV_REDUCE(_Tpvec, func, scalartype, suffix, vl, red) \ inline scalartype v_reduce_##func(const _Tpvec& a) \ { \ - _Tpvec res = _Tpvec(v##red(a, a, a, vl)); \ + _Tpvec res = _Tpvec(__riscv_v##red(a, a, vl)); \ return (scalartype)v_get0(res); \ } @@ -1008,48 +995,48 @@ inline v_float32 v_reduce_sum4(const v_float32& a, const v_float32& b, const v_float32& c, const v_float32& d) { // 0000 1111 2222 3333 .... - vuint64m2_t vid1 = vid_v_u64m2(VTraits::vlanes()); - vuint16m2_t t1 = vreinterpret_u16m2(vid1); - vuint16m2_t t2 = vslide1up(t1, 0, VTraits::vlanes()); - vuint16m2_t t3 = vslide1up(t2, 0, VTraits::vlanes()); - vuint16m2_t t4 = vslide1up(t3, 0, VTraits::vlanes()); - t1 = vor( - vor(t1, t2, VTraits::vlanes()), - vor(t3, t4, VTraits::vlanes()), + vuint64m2_t vid1 = __riscv_vid_v_u64m2(VTraits::vlanes()); + vuint16m2_t t1 = __riscv_vreinterpret_u16m2(vid1); + vuint16m2_t t2 = __riscv_vslide1up(t1, 0, VTraits::vlanes()); + vuint16m2_t t3 = __riscv_vslide1up(t2, 0, VTraits::vlanes()); + vuint16m2_t t4 = __riscv_vslide1up(t3, 0, VTraits::vlanes()); + t1 = __riscv_vor( + __riscv_vor(t1, t2, VTraits::vlanes()), + __riscv_vor(t3, t4, VTraits::vlanes()), VTraits::vlanes() ); // index for transpose4X4 - vuint16m2_t vidx0 = vmul(t1, 12, VTraits::vlanes()); - vidx0 = vadd(vidx0, vid_v_u16m2(VTraits::vlanes()), VTraits::vlanes()); - vuint16m2_t vidx1 = vadd(vidx0, 4, VTraits::vlanes()); - vuint16m2_t vidx2 = vadd(vidx0, 8, VTraits::vlanes()); - vuint16m2_t vidx3 = vadd(vidx0, 12, VTraits::vlanes()); + vuint16m2_t vidx0 = __riscv_vmul(t1, 12, VTraits::vlanes()); + vidx0 = __riscv_vadd(vidx0, __riscv_vid_v_u16m2(VTraits::vlanes()), VTraits::vlanes()); + vuint16m2_t vidx1 = __riscv_vadd(vidx0, 4, VTraits::vlanes()); + vuint16m2_t vidx2 = __riscv_vadd(vidx0, 8, VTraits::vlanes()); + vuint16m2_t vidx3 = __riscv_vadd(vidx0, 12, VTraits::vlanes()); // zip - vuint32m2_t tempA = vreinterpret_u32m2( \ - vor(vzext_vf2(vreinterpret_u32m1(a), VTraits::vlanes()), \ - vreinterpret_u64m2(vslide1up(vreinterpret_u32m2(vzext_vf2(vreinterpret_u32m1(c), VTraits::vlanes())), 0, VTraits::vlanes())), \ + vuint32m2_t tempA = __riscv_vreinterpret_u32m2( \ + __riscv_vor(__riscv_vzext_vf2(__riscv_vreinterpret_u32m1(a), VTraits::vlanes()), \ + __riscv_vreinterpret_u64m2(__riscv_vslide1up(__riscv_vreinterpret_u32m2(__riscv_vzext_vf2(__riscv_vreinterpret_u32m1(c), VTraits::vlanes())), 0, VTraits::vlanes())), \ VTraits::vlanes())); \ - vuint32m2_t tempB = vreinterpret_u32m2( \ - vor(vzext_vf2(vreinterpret_u32m1(b), VTraits::vlanes()), \ - vreinterpret_u64m2(vslide1up(vreinterpret_u32m2(vzext_vf2(vreinterpret_u32m1(d), VTraits::vlanes())), 0, VTraits::vlanes())), \ + vuint32m2_t tempB = __riscv_vreinterpret_u32m2( \ + __riscv_vor(__riscv_vzext_vf2(__riscv_vreinterpret_u32m1(b), VTraits::vlanes()), \ + __riscv_vreinterpret_u64m2(__riscv_vslide1up(__riscv_vreinterpret_u32m2(__riscv_vzext_vf2(__riscv_vreinterpret_u32m1(d), VTraits::vlanes())), 0, VTraits::vlanes())), \ VTraits::vlanes())); \ - vfloat32m4_t temp = vreinterpret_f32m4(vreinterpret_u32m4( \ - vor(vzext_vf2(tempA, VTraits::vlanes()), \ - vreinterpret_u64m4(vslide1up(vreinterpret_u32m4(vzext_vf2(tempB, VTraits::vlanes())), 0, VTraits::vlanes())), \ + vfloat32m4_t temp = __riscv_vreinterpret_f32m4(__riscv_vreinterpret_u32m4( \ + __riscv_vor(__riscv_vzext_vf2(tempA, VTraits::vlanes()), \ + __riscv_vreinterpret_u64m4(__riscv_vslide1up(__riscv_vreinterpret_u32m4(__riscv_vzext_vf2(tempB, VTraits::vlanes())), 0, VTraits::vlanes())), \ VTraits::vlanes()))); // transpose - vfloat32m1_t b0 = vlmul_trunc_f32m1(vrgatherei16(temp, vidx0, VTraits::vlanes())); - vfloat32m1_t b1 = vlmul_trunc_f32m1(vrgatherei16(temp, vidx1, VTraits::vlanes())); - vfloat32m1_t b2 = vlmul_trunc_f32m1(vrgatherei16(temp, vidx2, VTraits::vlanes())); - vfloat32m1_t b3 = vlmul_trunc_f32m1(vrgatherei16(temp, vidx3, VTraits::vlanes())); + vfloat32m1_t b0 = __riscv_vlmul_trunc_f32m1(__riscv_vrgatherei16(temp, vidx0, VTraits::vlanes())); + vfloat32m1_t b1 = __riscv_vlmul_trunc_f32m1(__riscv_vrgatherei16(temp, vidx1, VTraits::vlanes())); + vfloat32m1_t b2 = __riscv_vlmul_trunc_f32m1(__riscv_vrgatherei16(temp, vidx2, VTraits::vlanes())); + vfloat32m1_t b3 = __riscv_vlmul_trunc_f32m1(__riscv_vrgatherei16(temp, vidx3, VTraits::vlanes())); // vector add - v_float32 res = vfadd( - vfadd(b0, b1, VTraits::vlanes()), - vfadd(b2, b3, VTraits::vlanes()), + v_float32 res = __riscv_vfadd( + __riscv_vfadd(b0, b1, VTraits::vlanes()), + __riscv_vfadd(b2, b3, VTraits::vlanes()), VTraits::vlanes() ); return res; @@ -1059,7 +1046,7 @@ inline v_float32 v_reduce_sum4(const v_float32& a, const v_float32& b, inline v_float32 v_sqrt(const v_float32& x) { - return vfsqrt(x, VTraits::vlanes()); + return __riscv_vfsqrt(x, VTraits::vlanes()); } inline v_float32 v_invsqrt(const v_float32& x) @@ -1071,7 +1058,7 @@ inline v_float32 v_invsqrt(const v_float32& x) #if CV_SIMD_SCALABLE_64F inline v_float64 v_sqrt(const v_float64& x) { - return vfsqrt(x, VTraits::vlanes()); + return __riscv_vfsqrt(x, VTraits::vlanes()); } inline v_float64 v_invsqrt(const v_float64& x) @@ -1083,25 +1070,25 @@ inline v_float64 v_invsqrt(const v_float64& x) inline v_float32 v_magnitude(const v_float32& a, const v_float32& b) { - v_float32 x = vfmacc(vfmul(a, a, VTraits::vlanes()), b, b, VTraits::vlanes()); + v_float32 x = __riscv_vfmacc(__riscv_vfmul(a, a, VTraits::vlanes()), b, b, VTraits::vlanes()); return v_sqrt(x); } inline v_float32 v_sqr_magnitude(const v_float32& a, const v_float32& b) { - return v_float32(vfmacc(vfmul(a, a, VTraits::vlanes()), b, b, VTraits::vlanes())); + return v_float32(__riscv_vfmacc(__riscv_vfmul(a, a, VTraits::vlanes()), b, b, VTraits::vlanes())); } #if CV_SIMD_SCALABLE_64F inline v_float64 v_magnitude(const v_float64& a, const v_float64& b) { - v_float64 x = vfmacc(vfmul(a, a, VTraits::vlanes()), b, b, VTraits::vlanes()); + v_float64 x = __riscv_vfmacc(__riscv_vfmul(a, a, VTraits::vlanes()), b, b, VTraits::vlanes()); return v_sqrt(x); } inline v_float64 v_sqr_magnitude(const v_float64& a, const v_float64& b) { - return vfmacc(vfmul(a, a, VTraits::vlanes()), b, b, VTraits::vlanes()); + return __riscv_vfmacc(__riscv_vfmul(a, a, VTraits::vlanes()), b, b, VTraits::vlanes()); } #endif @@ -1109,11 +1096,11 @@ inline v_float64 v_sqr_magnitude(const v_float64& a, const v_float64& b) inline v_float32 v_fma(const v_float32& a, const v_float32& b, const v_float32& c) { - return vfmacc(c, a, b, VTraits::vlanes()); + return __riscv_vfmacc(c, a, b, VTraits::vlanes()); } inline v_int32 v_fma(const v_int32& a, const v_int32& b, const v_int32& c) { - return vmacc(c, a, b, VTraits::vlanes()); + return __riscv_vmacc(c, a, b, VTraits::vlanes()); } inline v_float32 v_muladd(const v_float32& a, const v_float32& b, const v_float32& c) @@ -1129,7 +1116,7 @@ inline v_int32 v_muladd(const v_int32& a, const v_int32& b, const v_int32& c) #if CV_SIMD_SCALABLE_64F inline v_float64 v_fma(const v_float64& a, const v_float64& b, const v_float64& c) { - return vfmacc_vv_f64m1(c, a, b, VTraits::vlanes()); + return __riscv_vfmacc_vv_f64m1(c, a, b, VTraits::vlanes()); } inline v_float64 v_muladd(const v_float64& a, const v_float64& b, const v_float64& c) @@ -1143,11 +1130,11 @@ inline v_float64 v_muladd(const v_float64& a, const v_float64& b, const v_float6 #define OPENCV_HAL_IMPL_RVV_CHECK_ALLANY(_Tpvec, vl) \ inline bool v_check_all(const _Tpvec& a) \ { \ - return (int)vcpop(vmslt(a, 0, vl), vl) == vl; \ + return (int)__riscv_vcpop(__riscv_vmslt(a, 0, vl), vl) == vl; \ } \ inline bool v_check_any(const _Tpvec& a) \ { \ - return (int)vcpop(vmslt(a, 0, vl), vl) != 0; \ + return (int)__riscv_vcpop(__riscv_vmslt(a, 0, vl), vl) != 0; \ } OPENCV_HAL_IMPL_RVV_CHECK_ALLANY(v_int8, VTraits::vlanes()) @@ -1209,7 +1196,7 @@ OPENCV_HAL_IMPL_RVV_ABSDIFF(v_int16, absdiffs) #define OPENCV_HAL_IMPL_RVV_ABSDIFF_S(_Tpvec, _rTpvec, width) \ inline _rTpvec v_absdiff(const _Tpvec& a, const _Tpvec& b) \ { \ - return vnclipu(vreinterpret_u##width##m2(vwsub_vv(v_max(a, b), v_min(a, b), VTraits<_Tpvec>::vlanes())), 0, VTraits<_Tpvec>::vlanes()); \ + return __riscv_vnclipu(__riscv_vreinterpret_u##width##m2(__riscv_vwsub_vv(v_max(a, b), v_min(a, b), VTraits<_Tpvec>::vlanes())), 0, 0, VTraits<_Tpvec>::vlanes()); \ } OPENCV_HAL_IMPL_RVV_ABSDIFF_S(v_int8, v_uint8, 16) @@ -1250,7 +1237,7 @@ OPENCV_HAL_IMPL_RVV_REDUCE_SAD(v_float32, float) #define OPENCV_HAL_IMPL_RVV_SELECT(_Tpvec, vl) \ inline _Tpvec v_select(const _Tpvec& mask, const _Tpvec& a, const _Tpvec& b) \ { \ - return vmerge(vmsne(mask, 0, vl), b, a, vl); \ + return __riscv_vmerge(b, a, __riscv_vmsne(mask, 0, vl), vl); \ } OPENCV_HAL_IMPL_RVV_SELECT(v_uint8, VTraits::vlanes()) @@ -1262,13 +1249,13 @@ OPENCV_HAL_IMPL_RVV_SELECT(v_int32, VTraits::vlanes()) inline v_float32 v_select(const v_float32& mask, const v_float32& a, const v_float32& b) \ { \ - return vmerge(vmfne(mask, 0, VTraits::vlanes()), b, a, VTraits::vlanes()); \ + return __riscv_vmerge(b, a, __riscv_vmfne(mask, 0, VTraits::vlanes()), VTraits::vlanes()); \ } #if CV_SIMD_SCALABLE_64F inline v_float64 v_select(const v_float64& mask, const v_float64& a, const v_float64& b) \ { \ - return vmerge(vmfne(mask, 0, VTraits::vlanes()), b, a, VTraits::vlanes()); \ + return __riscv_vmerge(b, a, __riscv_vmfne(mask, 0, VTraits::vlanes()), VTraits::vlanes()); \ } #endif @@ -1277,21 +1264,21 @@ inline v_float64 v_select(const v_float64& mask, const v_float64& a, const v_flo #define OPENCV_HAL_IMPL_RVV_ROTATE_INTEGER(_Tpvec, suffix, vl) \ template inline _Tpvec v_rotate_right(const _Tpvec& a) \ { \ - return vslidedown(vmv_v_x_##suffix##m1(0, vl), a, n, vl); \ + return __riscv_vslidedown(a, n, vl); \ } \ template inline _Tpvec v_rotate_left(const _Tpvec& a) \ { \ - return vslideup(vmv_v_x_##suffix##m1(0, vl), a, n, vl); \ + return __riscv_vslideup(__riscv_vmv_v_x_##suffix##m1(0, vl), a, n, vl); \ } \ template<> inline _Tpvec v_rotate_left<0>(const _Tpvec& a) \ { return a; } \ template inline _Tpvec v_rotate_right(const _Tpvec& a, const _Tpvec& b) \ { \ - return vslideup(vslidedown(vmv_v_x_##suffix##m1(0, vl), a, n, vl), b, VTraits<_Tpvec>::vlanes() - n, vl); \ + return __riscv_vslideup(__riscv_vslidedown(a, n, vl), b, VTraits<_Tpvec>::vlanes() - n, vl); \ } \ template inline _Tpvec v_rotate_left(const _Tpvec& a, const _Tpvec& b) \ { \ - return vslideup(vslidedown(vmv_v_x_##suffix##m1(0, vl), b, VTraits<_Tpvec>::vlanes() - n, vl), a, n, vl); \ + return __riscv_vslideup(__riscv_vslidedown(b, VTraits<_Tpvec>::vlanes() - n, vl), a, n, vl); \ } \ template<> inline _Tpvec v_rotate_left<0>(const _Tpvec& a, const _Tpvec& b) \ { CV_UNUSED(b); return a; } @@ -1308,21 +1295,21 @@ OPENCV_HAL_IMPL_RVV_ROTATE_INTEGER(v_int64, i64, VTraits::vlanes()) #define OPENCV_HAL_IMPL_RVV_ROTATE_FP(_Tpvec, suffix, vl) \ template inline _Tpvec v_rotate_right(const _Tpvec& a) \ { \ - return vslidedown(vfmv_v_f_##suffix##m1(0, vl), a, n, vl); \ + return __riscv_vslidedown(a, n, vl); \ } \ template inline _Tpvec v_rotate_left(const _Tpvec& a) \ { \ - return vslideup(vfmv_v_f_##suffix##m1(0, vl), a, n, vl); \ + return __riscv_vslideup(__riscv_vfmv_v_f_##suffix##m1(0, vl), a, n, vl); \ } \ template<> inline _Tpvec v_rotate_left<0>(const _Tpvec& a) \ { return a; } \ template inline _Tpvec v_rotate_right(const _Tpvec& a, const _Tpvec& b) \ { \ - return vslideup(vslidedown(vfmv_v_f_##suffix##m1(0, vl), a, n, vl), b, VTraits<_Tpvec>::vlanes() - n, vl); \ + return __riscv_vslideup(__riscv_vslidedown(a, n, vl), b, VTraits<_Tpvec>::vlanes() - n, vl); \ } \ template inline _Tpvec v_rotate_left(const _Tpvec& a, const _Tpvec& b) \ { \ - return vslideup(vslidedown(vfmv_v_f_##suffix##m1(0, vl), b, VTraits<_Tpvec>::vlanes() - n, vl), a, n, vl); \ + return __riscv_vslideup(__riscv_vslidedown(b, VTraits<_Tpvec>::vlanes() - n, vl), a, n, vl); \ } \ template<> inline _Tpvec v_rotate_left<0>(const _Tpvec& a, const _Tpvec& b) \ { CV_UNUSED(b); return a; } @@ -1335,43 +1322,43 @@ OPENCV_HAL_IMPL_RVV_ROTATE_FP(v_float64, f64, VTraits::vlanes()) ////////////// Convert to float ////////////// inline v_float32 v_cvt_f32(const v_int32& a) { - return vfcvt_f_x_v_f32m1(a, VTraits::vlanes()); + return __riscv_vfcvt_f_x_v_f32m1(a, VTraits::vlanes()); } #if CV_SIMD_SCALABLE_64F inline v_float32 v_cvt_f32(const v_float64& a) { - return vfncvt_f(vlmul_ext_f64m2(a), VTraits::vlanes()); + return __riscv_vfncvt_f(__riscv_vlmul_ext_f64m2(a), VTraits::vlanes()); } inline v_float32 v_cvt_f32(const v_float64& a, const v_float64& b) { - return vfncvt_f(vset(vlmul_ext_f64m2(a),1,b), VTraits::vlanes()); + return __riscv_vfncvt_f(__riscv_vset(__riscv_vlmul_ext_f64m2(a),1,b), VTraits::vlanes()); } inline v_float64 v_cvt_f64(const v_int32& a) { - return vget_f64m1(vfwcvt_f(a, VTraits::vlanes()), 0); + return __riscv_vget_f64m1(__riscv_vfwcvt_f(a, VTraits::vlanes()), 0); } inline v_float64 v_cvt_f64_high(const v_int32& a) { - return vget_f64m1(vfwcvt_f(a, VTraits::vlanes()), 1); + return __riscv_vget_f64m1(__riscv_vfwcvt_f(a, VTraits::vlanes()), 1); } inline v_float64 v_cvt_f64(const v_float32& a) { - return vget_f64m1(vfwcvt_f(a, VTraits::vlanes()), 0); + return __riscv_vget_f64m1(__riscv_vfwcvt_f(a, VTraits::vlanes()), 0); } inline v_float64 v_cvt_f64_high(const v_float32& a) { - return vget_f64m1(vfwcvt_f(a, VTraits::vlanes()), 1); + return __riscv_vget_f64m1(__riscv_vfwcvt_f(a, VTraits::vlanes()), 1); } inline v_float64 v_cvt_f64(const v_int64& a) { - return vfcvt_f(a, VTraits::vlanes()); + return __riscv_vfcvt_f(a, VTraits::vlanes()); } #endif @@ -1396,8 +1383,8 @@ OPENCV_HAL_IMPL_RVV_BROADCAST(v_float32, f32) #define OPENCV_HAL_IMPL_RVV_REVERSE(_Tpvec, width) \ inline _Tpvec v_reverse(const _Tpvec& a) \ { \ - vuint##width##m1_t vidx = vrsub(vid_v_u##width##m1(VTraits<_Tpvec>::vlanes()), VTraits<_Tpvec>::vlanes()-1, VTraits<_Tpvec>::vlanes()); \ - return vrgather(a, vidx, VTraits<_Tpvec>::vlanes()); \ + vuint##width##m1_t vidx = __riscv_vrsub(__riscv_vid_v_u##width##m1(VTraits<_Tpvec>::vlanes()), VTraits<_Tpvec>::vlanes()-1, VTraits<_Tpvec>::vlanes()); \ + return __riscv_vrgather(a, vidx, VTraits<_Tpvec>::vlanes()); \ } OPENCV_HAL_IMPL_RVV_REVERSE(v_uint8, 8) OPENCV_HAL_IMPL_RVV_REVERSE(v_int8, 8) @@ -1418,90 +1405,110 @@ OPENCV_HAL_IMPL_RVV_REVERSE(v_float64, 64) inline void v_expand(const _Tpvec& a, _Tpwvec& b0, _Tpwvec& b1) \ { \ _Tpwvec_m2 temp = cvt(a, VTraits<_Tpvec>::vlanes()); \ - b0 = vget_##suffix##m1(temp, 0); \ - b1 = vget_##suffix##m1(temp, 1); \ + b0 = __riscv_vget_##suffix##m1(temp, 0); \ + b1 = __riscv_vget_##suffix##m1(temp, 1); \ } \ inline _Tpwvec v_expand_low(const _Tpvec& a) \ { \ _Tpwvec_m2 temp = cvt(a, VTraits<_Tpvec>::vlanes()); \ - return vget_##suffix##m1(temp, 0); \ + return __riscv_vget_##suffix##m1(temp, 0); \ } \ inline _Tpwvec v_expand_high(const _Tpvec& a) \ { \ _Tpwvec_m2 temp = cvt(a, VTraits<_Tpvec>::vlanes()); \ - return vget_##suffix##m1(temp, 1); \ + return __riscv_vget_##suffix##m1(temp, 1); \ } \ inline _Tpwvec v_load_expand(const _Tp* ptr) \ { \ - return cvt(vle##width##_v_##suffix2##mf2(ptr, VTraits<_Tpvec>::vlanes()), VTraits<_Tpvec>::vlanes()); \ + return cvt(__riscv_vle##width##_v_##suffix2##mf2(ptr, VTraits<_Tpvec>::vlanes()), VTraits<_Tpvec>::vlanes()); \ } -OPENCV_HAL_IMPL_RVV_EXPAND(uchar, v_uint16, vuint16m2_t, v_uint8, 8, u16, u8, vwcvtu_x) -OPENCV_HAL_IMPL_RVV_EXPAND(schar, v_int16, vint16m2_t, v_int8, 8, i16, i8, vwcvt_x) -OPENCV_HAL_IMPL_RVV_EXPAND(ushort, v_uint32, vuint32m2_t, v_uint16, 16, u32, u16, vwcvtu_x) -OPENCV_HAL_IMPL_RVV_EXPAND(short, v_int32, vint32m2_t, v_int16, 16, i32, i16, vwcvt_x) -OPENCV_HAL_IMPL_RVV_EXPAND(uint, v_uint64, vuint64m2_t, v_uint32, 32, u64, u32, vwcvtu_x) -OPENCV_HAL_IMPL_RVV_EXPAND(int, v_int64, vint64m2_t, v_int32, 32, i64, i32, vwcvt_x) +OPENCV_HAL_IMPL_RVV_EXPAND(uchar, v_uint16, vuint16m2_t, v_uint8, 8, u16, u8, __riscv_vwcvtu_x) +OPENCV_HAL_IMPL_RVV_EXPAND(schar, v_int16, vint16m2_t, v_int8, 8, i16, i8, __riscv_vwcvt_x) +OPENCV_HAL_IMPL_RVV_EXPAND(ushort, v_uint32, vuint32m2_t, v_uint16, 16, u32, u16, __riscv_vwcvtu_x) +OPENCV_HAL_IMPL_RVV_EXPAND(short, v_int32, vint32m2_t, v_int16, 16, i32, i16, __riscv_vwcvt_x) +OPENCV_HAL_IMPL_RVV_EXPAND(uint, v_uint64, vuint64m2_t, v_uint32, 32, u64, u32, __riscv_vwcvtu_x) +OPENCV_HAL_IMPL_RVV_EXPAND(int, v_int64, vint64m2_t, v_int32, 32, i64, i32, __riscv_vwcvt_x) inline v_uint32 v_load_expand_q(const uchar* ptr) { - return vwcvtu_x(vwcvtu_x(vle8_v_u8mf4(ptr, VTraits::vlanes()), VTraits::vlanes()), VTraits::vlanes()); + return __riscv_vwcvtu_x(__riscv_vwcvtu_x(__riscv_vle8_v_u8mf4(ptr, VTraits::vlanes()), VTraits::vlanes()), VTraits::vlanes()); } inline v_int32 v_load_expand_q(const schar* ptr) { - return vwcvt_x(vwcvt_x(vle8_v_i8mf4(ptr, VTraits::vlanes()), VTraits::vlanes()), VTraits::vlanes()); + return __riscv_vwcvt_x(__riscv_vwcvt_x(__riscv_vle8_v_i8mf4(ptr, VTraits::vlanes()), VTraits::vlanes()), VTraits::vlanes()); } #define OPENCV_HAL_IMPL_RVV_PACK(_Tpvec, _Tp, _wTpvec, hwidth, hsuffix, suffix, rshr, shr) \ inline _Tpvec v_pack(const _wTpvec& a, const _wTpvec& b) \ { \ - return shr(vset(vlmul_ext_##suffix##m2(a), 1, b), 0, VTraits<_Tpvec>::vlanes()); \ + return shr(__riscv_vset(__riscv_vlmul_ext_##suffix##m2(a), 1, b), 0, 0, VTraits<_Tpvec>::vlanes()); \ +} \ +inline void v_pack_store(_Tp* ptr, const _wTpvec& a) \ +{ \ + __riscv_vse##hwidth##_v_##hsuffix##mf2(ptr, shr(a, 0, 0, VTraits<_Tpvec>::vlanes()), VTraits<_wTpvec>::vlanes()); \ +} \ +template inline \ +_Tpvec v_rshr_pack(const _wTpvec& a, const _wTpvec& b, int N = n) \ +{ \ + return rshr(__riscv_vset(__riscv_vlmul_ext_##suffix##m2(a), 1, b), N, 0, VTraits<_Tpvec>::vlanes()); \ +} \ +template inline \ +void v_rshr_pack_store(_Tp* ptr, const _wTpvec& a, int N = n) \ +{ \ + __riscv_vse##hwidth##_v_##hsuffix##mf2(ptr, rshr(a, N, 0, VTraits<_Tpvec>::vlanes()), VTraits<_wTpvec>::vlanes()); \ +} + +#define OPENCV_HAL_IMPL_RVV_PACK_32(_Tpvec, _Tp, _wTpvec, hwidth, hsuffix, suffix, rshr, shr) \ +inline _Tpvec v_pack(const _wTpvec& a, const _wTpvec& b) \ +{ \ + return shr(__riscv_vset(__riscv_vlmul_ext_##suffix##m2(a), 1, b), 0, VTraits<_Tpvec>::vlanes()); \ } \ inline void v_pack_store(_Tp* ptr, const _wTpvec& a) \ { \ - vse##hwidth##_v_##hsuffix##mf2(ptr, shr(a, 0, VTraits<_Tpvec>::vlanes()), VTraits<_wTpvec>::vlanes()); \ + __riscv_vse##hwidth##_v_##hsuffix##mf2(ptr, shr(a, 0, VTraits<_Tpvec>::vlanes()), VTraits<_wTpvec>::vlanes()); \ } \ template inline \ _Tpvec v_rshr_pack(const _wTpvec& a, const _wTpvec& b, int N = n) \ { \ - return rshr(vset(vlmul_ext_##suffix##m2(a), 1, b), N, VTraits<_Tpvec>::vlanes()); \ + return rshr(__riscv_vset(__riscv_vlmul_ext_##suffix##m2(a), 1, b), N, 0, VTraits<_Tpvec>::vlanes()); \ } \ template inline \ void v_rshr_pack_store(_Tp* ptr, const _wTpvec& a, int N = n) \ { \ - vse##hwidth##_v_##hsuffix##mf2(ptr, rshr(a, N, VTraits<_Tpvec>::vlanes()), VTraits<_wTpvec>::vlanes()); \ + __riscv_vse##hwidth##_v_##hsuffix##mf2(ptr, rshr(a, N, 0, VTraits<_Tpvec>::vlanes()), VTraits<_wTpvec>::vlanes()); \ } -OPENCV_HAL_IMPL_RVV_PACK(v_uint8, uchar, v_uint16, 8, u8, u16, vnclipu, vnclipu) -OPENCV_HAL_IMPL_RVV_PACK(v_int8, schar, v_int16, 8, i8, i16, vnclip, vnclip) -OPENCV_HAL_IMPL_RVV_PACK(v_uint16, ushort, v_uint32, 16, u16, u32, vnclipu, vnclipu) -OPENCV_HAL_IMPL_RVV_PACK(v_int16, short, v_int32, 16, i16, i32, vnclip, vnclip) -OPENCV_HAL_IMPL_RVV_PACK(v_uint32, unsigned, v_uint64, 32, u32, u64, vnclipu, vnsrl) -OPENCV_HAL_IMPL_RVV_PACK(v_int32, int, v_int64, 32, i32, i64, vnclip, vnsra) +OPENCV_HAL_IMPL_RVV_PACK(v_uint8, uchar, v_uint16, 8, u8, u16, __riscv_vnclipu, __riscv_vnclipu) +OPENCV_HAL_IMPL_RVV_PACK(v_int8, schar, v_int16, 8, i8, i16, __riscv_vnclip, __riscv_vnclip) +OPENCV_HAL_IMPL_RVV_PACK(v_uint16, ushort, v_uint32, 16, u16, u32, __riscv_vnclipu, __riscv_vnclipu) +OPENCV_HAL_IMPL_RVV_PACK(v_int16, short, v_int32, 16, i16, i32, __riscv_vnclip, __riscv_vnclip) +OPENCV_HAL_IMPL_RVV_PACK_32(v_uint32, unsigned, v_uint64, 32, u32, u64, __riscv_vnclipu, __riscv_vnsrl) +OPENCV_HAL_IMPL_RVV_PACK_32(v_int32, int, v_int64, 32, i32, i64, __riscv_vnclip, __riscv_vnsra) -#define OPENCV_HAL_IMPL_RVV_PACK_U(_Tpvec, _Tp, _wTpvec, _wTp, hwidth, width, hsuffix, suffix, rshr, cast, hvl, vl) \ +#define OPENCV_HAL_IMPL_RVV_PACK_U(_Tpvec, _Tp, _wTpvec, _wTp, hwidth, width, hsuffix, suffix, cast, hvl, vl) \ inline _Tpvec v_pack_u(const _wTpvec& a, const _wTpvec& b) \ { \ - return vnclipu(cast(vmax(vset(vlmul_ext_##suffix##m2(a), 1, b), 0, vl)), 0, vl); \ + return __riscv_vnclipu(cast(__riscv_vmax(__riscv_vset(__riscv_vlmul_ext_##suffix##m2(a), 1, b), 0, vl)), 0, 0, vl); \ } \ inline void v_pack_u_store(_Tp* ptr, const _wTpvec& a) \ { \ - vse##hwidth##_v_##hsuffix##mf2(ptr, vnclipu(vreinterpret_u##width##m1(vmax(a, 0, vl)), 0, vl), hvl); \ + __riscv_vse##hwidth##_v_##hsuffix##mf2(ptr, __riscv_vnclipu(__riscv_vreinterpret_u##width##m1(__riscv_vmax(a, 0, vl)), 0, 0, vl), hvl); \ } \ template inline \ _Tpvec v_rshr_pack_u(const _wTpvec& a, const _wTpvec& b, int n = N) \ { \ - return vnclipu(cast(vmax(vset(vlmul_ext_##suffix##m2(a), 1, b), 0, vl)), n, vl); \ + return __riscv_vnclipu(cast(__riscv_vmax(__riscv_vset(__riscv_vlmul_ext_##suffix##m2(a), 1, b), 0, vl)), n, 0, vl); \ } \ template inline \ void v_rshr_pack_u_store(_Tp* ptr, const _wTpvec& a, int n = N) \ { \ - vse##hwidth##_v_##hsuffix##mf2(ptr, vnclipu(vreinterpret_u##width##m1(vmax(a, 0, vl)), n, vl), hvl); \ + __riscv_vse##hwidth##_v_##hsuffix##mf2(ptr, __riscv_vnclipu(__riscv_vreinterpret_u##width##m1(__riscv_vmax(a, 0, vl)), n, 0, vl), hvl); \ } -OPENCV_HAL_IMPL_RVV_PACK_U(v_uint8, uchar, v_int16, short, 8, 16, u8, i16, vnclipu_wx_u8m1, vreinterpret_v_i16m2_u16m2, VTraits::vlanes(), VTraits::vlanes()) -OPENCV_HAL_IMPL_RVV_PACK_U(v_uint16, ushort, v_int32, int, 16, 32, u16, i32, vnclipu_wx_u16m1, vreinterpret_v_i32m2_u32m2, VTraits::vlanes(), VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_PACK_U(v_uint8, uchar, v_int16, short, 8, 16, u8, i16, __riscv_vreinterpret_v_i16m2_u16m2, VTraits::vlanes(), VTraits::vlanes()) +OPENCV_HAL_IMPL_RVV_PACK_U(v_uint16, ushort, v_int32, int, 16, 32, u16, i32, __riscv_vreinterpret_v_i32m2_u32m2, VTraits::vlanes(), VTraits::vlanes()) /* void v_zip(const _Tpvec& a0, const _Tpvec& a1, _Tpvec& b0, _Tpvec& b1) @@ -1513,51 +1520,51 @@ OPENCV_HAL_IMPL_RVV_PACK_U(v_uint16, ushort, v_int32, int, 16, 32, u16, i32, vnc #define OPENCV_HAL_IMPL_RVV_ZIP(_Tpvec, _wTpvec, suffix, width, width2, convert2um2, convert2um1) \ inline void v_zip(const _Tpvec& a0, const _Tpvec& a1, _Tpvec& b0, _Tpvec& b1) { \ - _wTpvec temp = vreinterpret_##suffix##m2(convert2um2( \ - vor(vzext_vf2(convert2um1(a0), VTraits<_Tpvec>::vlanes()*2), \ - vreinterpret_u##width2##m2(vslide1up(vreinterpret_u##width##m2(vzext_vf2(convert2um1(a1), VTraits<_Tpvec>::vlanes()*2)), 0, VTraits<_Tpvec>::vlanes()*2)), \ + _wTpvec temp = __riscv_vreinterpret_##suffix##m2(convert2um2( \ + __riscv_vor(__riscv_vzext_vf2(convert2um1(a0), VTraits<_Tpvec>::vlanes()*2), \ + __riscv_vreinterpret_u##width2##m2(__riscv_vslide1up(__riscv_vreinterpret_u##width##m2(__riscv_vzext_vf2(convert2um1(a1), VTraits<_Tpvec>::vlanes()*2)), 0, VTraits<_Tpvec>::vlanes()*2)), \ VTraits<_Tpvec>::vlanes()))); \ - b0 = vget_##suffix##m1(temp, 0); \ - b1 = vget_##suffix##m1(temp, 1); \ + b0 = __riscv_vget_##suffix##m1(temp, 0); \ + b1 = __riscv_vget_##suffix##m1(temp, 1); \ } OPENCV_HAL_IMPL_RVV_ZIP(v_uint8, vuint8m2_t, u8, 8, 16, OPENCV_HAL_NOP, OPENCV_HAL_NOP) -OPENCV_HAL_IMPL_RVV_ZIP(v_int8, vint8m2_t, i8, 8, 16, vreinterpret_u8m2, vreinterpret_u8m1) +OPENCV_HAL_IMPL_RVV_ZIP(v_int8, vint8m2_t, i8, 8, 16, __riscv_vreinterpret_u8m2, __riscv_vreinterpret_u8m1) OPENCV_HAL_IMPL_RVV_ZIP(v_uint16, vuint16m2_t, u16, 16, 32, OPENCV_HAL_NOP, OPENCV_HAL_NOP) -OPENCV_HAL_IMPL_RVV_ZIP(v_int16, vint16m2_t, i16, 16, 32, vreinterpret_u16m2, vreinterpret_u16m1) +OPENCV_HAL_IMPL_RVV_ZIP(v_int16, vint16m2_t, i16, 16, 32, __riscv_vreinterpret_u16m2, __riscv_vreinterpret_u16m1) OPENCV_HAL_IMPL_RVV_ZIP(v_uint32, vuint32m2_t, u32, 32, 64, OPENCV_HAL_NOP, OPENCV_HAL_NOP) -OPENCV_HAL_IMPL_RVV_ZIP(v_int32, vint32m2_t, i32, 32, 64, vreinterpret_u32m2, vreinterpret_u32m1) -OPENCV_HAL_IMPL_RVV_ZIP(v_float32, vfloat32m2_t, f32, 32, 64, vreinterpret_u32m2, vreinterpret_u32m1) +OPENCV_HAL_IMPL_RVV_ZIP(v_int32, vint32m2_t, i32, 32, 64, __riscv_vreinterpret_u32m2, __riscv_vreinterpret_u32m1) +OPENCV_HAL_IMPL_RVV_ZIP(v_float32, vfloat32m2_t, f32, 32, 64, __riscv_vreinterpret_u32m2, __riscv_vreinterpret_u32m1) #if CV_SIMD_SCALABLE_64F inline void v_zip(const v_float64& a0, const v_float64& a1, v_float64& b0, v_float64& b1) { \ - vuint16mf4_t idx0 = vid_v_u16mf4(VTraits::vlanes()); - vuint16mf4_t idx1 = vadd(idx0, VTraits::vlanes(), VTraits::vlanes()); - vuint16mf2_t idx = vreinterpret_u16mf2(( \ - vor(vzext_vf2(idx0, VTraits::vlanes()), \ - vreinterpret_u32mf2(vslide1up(vreinterpret_u16mf2(vzext_vf2(idx1, VTraits::vlanes())), 0, VTraits::vlanes())), \ + vuint16mf4_t idx0 = __riscv_vid_v_u16mf4(VTraits::vlanes()); + vuint16mf4_t idx1 = __riscv_vadd(idx0, VTraits::vlanes(), VTraits::vlanes()); + vuint16mf2_t idx = __riscv_vreinterpret_u16mf2(( \ + __riscv_vor(__riscv_vzext_vf2(idx0, VTraits::vlanes()), \ + __riscv_vreinterpret_u32mf2(__riscv_vslide1up(__riscv_vreinterpret_u16mf2(__riscv_vzext_vf2(idx1, VTraits::vlanes())), 0, VTraits::vlanes())), \ VTraits::vlanes()))); #if 0 vfloat64m2_t temp = __riscv_vcreate_v_f64m1_f64m2(a0, a1); #else // TODO: clean up when RVV Intrinsic is frozen. - vfloat64m2_t temp = vlmul_ext_f64m2(a0); - temp = vset(temp, 1, a1); + vfloat64m2_t temp = __riscv_vlmul_ext_f64m2(a0); + temp = __riscv_vset(temp, 1, a1); #endif - temp = vrgatherei16(temp, idx, VTraits::vlanes()*2); - b0 = vget_f64m1(temp, 0); \ - b1 = vget_f64m1(temp, 1); \ + temp = __riscv_vrgatherei16(temp, idx, VTraits::vlanes()*2); + b0 = __riscv_vget_f64m1(temp, 0); \ + b1 = __riscv_vget_f64m1(temp, 1); \ } #endif #define OPENCV_HAL_IMPL_RVV_UNPACKS(_Tpvec, width) \ inline _Tpvec v_combine_low(const _Tpvec& a, const _Tpvec& b) \ { \ - return vslideup(a, b, VTraits<_Tpvec>::vlanes()/2, VTraits<_Tpvec>::vlanes());\ + return __riscv_vslideup(a, b, VTraits<_Tpvec>::vlanes()/2, VTraits<_Tpvec>::vlanes());\ } \ inline _Tpvec v_combine_high(const _Tpvec& a, const _Tpvec& b) \ { \ - return vslideup( \ - vslidedown(a, a, VTraits<_Tpvec>::vlanes()/2, VTraits<_Tpvec>::vlanes()), \ - vslidedown(b, b, VTraits<_Tpvec>::vlanes()/2, VTraits<_Tpvec>::vlanes()), \ + return __riscv_vslideup( \ + __riscv_vslidedown(a, VTraits<_Tpvec>::vlanes()/2, VTraits<_Tpvec>::vlanes()), \ + __riscv_vslidedown(b, VTraits<_Tpvec>::vlanes()/2, VTraits<_Tpvec>::vlanes()), \ VTraits<_Tpvec>::vlanes()/2, \ VTraits<_Tpvec>::vlanes()); \ } \ @@ -1581,45 +1588,45 @@ OPENCV_HAL_IMPL_RVV_UNPACKS(v_float64, 64) #define OPENCV_HAL_IMPL_RVV_INTERLEAVED(_Tpvec, _Tp, suffix, width, hwidth, vl) \ inline void v_load_deinterleave(const _Tp* ptr, v_##_Tpvec& a, v_##_Tpvec& b) \ { \ - a = vlse##width##_v_##suffix##m1(ptr , sizeof(_Tp)*2, VTraits::vlanes()); \ - b = vlse##width##_v_##suffix##m1(ptr+1, sizeof(_Tp)*2, VTraits::vlanes()); \ + a = __riscv_vlse##width##_v_##suffix##m1(ptr , sizeof(_Tp)*2, VTraits::vlanes()); \ + b = __riscv_vlse##width##_v_##suffix##m1(ptr+1, sizeof(_Tp)*2, VTraits::vlanes()); \ }\ inline void v_load_deinterleave(const _Tp* ptr, v_##_Tpvec& a, v_##_Tpvec& b, v_##_Tpvec& c) \ { \ - a = vlse##width##_v_##suffix##m1(ptr , sizeof(_Tp)*3, VTraits::vlanes()); \ - b = vlse##width##_v_##suffix##m1(ptr+1, sizeof(_Tp)*3, VTraits::vlanes()); \ - c = vlse##width##_v_##suffix##m1(ptr+2, sizeof(_Tp)*3, VTraits::vlanes()); \ + a = __riscv_vlse##width##_v_##suffix##m1(ptr , sizeof(_Tp)*3, VTraits::vlanes()); \ + b = __riscv_vlse##width##_v_##suffix##m1(ptr+1, sizeof(_Tp)*3, VTraits::vlanes()); \ + c = __riscv_vlse##width##_v_##suffix##m1(ptr+2, sizeof(_Tp)*3, VTraits::vlanes()); \ } \ inline void v_load_deinterleave(const _Tp* ptr, v_##_Tpvec& a, v_##_Tpvec& b, \ v_##_Tpvec& c, v_##_Tpvec& d) \ { \ \ - a = vlse##width##_v_##suffix##m1(ptr , sizeof(_Tp)*4, VTraits::vlanes()); \ - b = vlse##width##_v_##suffix##m1(ptr+1, sizeof(_Tp)*4, VTraits::vlanes()); \ - c = vlse##width##_v_##suffix##m1(ptr+2, sizeof(_Tp)*4, VTraits::vlanes()); \ - d = vlse##width##_v_##suffix##m1(ptr+3, sizeof(_Tp)*4, VTraits::vlanes()); \ + a = __riscv_vlse##width##_v_##suffix##m1(ptr , sizeof(_Tp)*4, VTraits::vlanes()); \ + b = __riscv_vlse##width##_v_##suffix##m1(ptr+1, sizeof(_Tp)*4, VTraits::vlanes()); \ + c = __riscv_vlse##width##_v_##suffix##m1(ptr+2, sizeof(_Tp)*4, VTraits::vlanes()); \ + d = __riscv_vlse##width##_v_##suffix##m1(ptr+3, sizeof(_Tp)*4, VTraits::vlanes()); \ } \ inline void v_store_interleave( _Tp* ptr, const v_##_Tpvec& a, const v_##_Tpvec& b, \ hal::StoreMode /*mode*/=hal::STORE_UNALIGNED) \ { \ - vsse##width(ptr, sizeof(_Tp)*2, a, VTraits::vlanes()); \ - vsse##width(ptr+1, sizeof(_Tp)*2, b, VTraits::vlanes()); \ + __riscv_vsse##width(ptr, sizeof(_Tp)*2, a, VTraits::vlanes()); \ + __riscv_vsse##width(ptr+1, sizeof(_Tp)*2, b, VTraits::vlanes()); \ } \ inline void v_store_interleave( _Tp* ptr, const v_##_Tpvec& a, const v_##_Tpvec& b, \ const v_##_Tpvec& c, hal::StoreMode /*mode*/=hal::STORE_UNALIGNED) \ { \ - vsse##width(ptr, sizeof(_Tp)*3, a, VTraits::vlanes()); \ - vsse##width(ptr+1, sizeof(_Tp)*3, b, VTraits::vlanes()); \ - vsse##width(ptr+2, sizeof(_Tp)*3, c, VTraits::vlanes()); \ + __riscv_vsse##width(ptr, sizeof(_Tp)*3, a, VTraits::vlanes()); \ + __riscv_vsse##width(ptr+1, sizeof(_Tp)*3, b, VTraits::vlanes()); \ + __riscv_vsse##width(ptr+2, sizeof(_Tp)*3, c, VTraits::vlanes()); \ } \ inline void v_store_interleave( _Tp* ptr, const v_##_Tpvec& a, const v_##_Tpvec& b, \ const v_##_Tpvec& c, const v_##_Tpvec& d, \ hal::StoreMode /*mode*/=hal::STORE_UNALIGNED ) \ { \ - vsse##width(ptr, sizeof(_Tp)*4, a, VTraits::vlanes()); \ - vsse##width(ptr+1, sizeof(_Tp)*4, b, VTraits::vlanes()); \ - vsse##width(ptr+2, sizeof(_Tp)*4, c, VTraits::vlanes()); \ - vsse##width(ptr+3, sizeof(_Tp)*4, d, VTraits::vlanes()); \ + __riscv_vsse##width(ptr, sizeof(_Tp)*4, a, VTraits::vlanes()); \ + __riscv_vsse##width(ptr+1, sizeof(_Tp)*4, b, VTraits::vlanes()); \ + __riscv_vsse##width(ptr+2, sizeof(_Tp)*4, c, VTraits::vlanes()); \ + __riscv_vsse##width(ptr+3, sizeof(_Tp)*4, d, VTraits::vlanes()); \ } OPENCV_HAL_IMPL_RVV_INTERLEAVED(uint8, uchar, u8, 8, 4, VTraits::vlanes()) @@ -1650,9 +1657,9 @@ static uint64_t idx_interleave_quads[] = { \ #define OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ_NOEXPEND(_Tpvec, func) \ inline _Tpvec v_interleave_##func(const _Tpvec& vec) { \ CV_CheckLE(VTraits<_Tpvec>::vlanes(), VTraits<_Tpvec>::max_nlanes, "RVV implementation only supports VLEN in the range [128, 1024]"); \ - vuint8m1_t vidx = vundefined_u8m1();\ - vidx = vreinterpret_u8m1(vle64_v_u64m1(idx_interleave_##func, 16)); \ - return vrgather(vec, vidx, VTraits::vlanes()); \ + vuint8m1_t vidx = __riscv_vundefined_u8m1();\ + vidx = __riscv_vreinterpret_u8m1(__riscv_vle64_v_u64m1(idx_interleave_##func, 16)); \ + return __riscv_vrgather(vec, vidx, VTraits::vlanes()); \ } OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ_NOEXPEND(v_uint8, pairs) OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ_NOEXPEND(v_int8, pairs) @@ -1662,22 +1669,22 @@ OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ_NOEXPEND(v_int8, quads) #define OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(_Tpvec, width, vzext_vfx, func) \ inline _Tpvec v_interleave_##func(const _Tpvec& vec) { \ CV_CheckLE(VTraits<_Tpvec>::vlanes(), VTraits<_Tpvec>::max_nlanes, "RVV implementation only supports VLEN in the range [128, 1024]"); \ - vuint##width##m1_t vidx = vundefined_u##width##m1();\ - vidx = vget_u##width##m1(vzext_vfx(vreinterpret_u8m1(vle64_v_u64m1(idx_interleave_##func, 16)), VTraits::vlanes()), 0); \ - return vrgather(vec, vidx, VTraits<_Tpvec>::vlanes()); \ + vuint##width##m1_t vidx = __riscv_vundefined_u##width##m1();\ + vidx = __riscv_vget_u##width##m1(vzext_vfx(__riscv_vreinterpret_u8m1(__riscv_vle64_v_u64m1(idx_interleave_##func, 16)), VTraits::vlanes()), 0); \ + return __riscv_vrgather(vec, vidx, VTraits<_Tpvec>::vlanes()); \ } -OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_uint16, 16, vzext_vf2, pairs) -OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_int16, 16, vzext_vf2, pairs) -OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_uint32, 32, vzext_vf4, pairs) -OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_int32, 32, vzext_vf4, pairs) -OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_float32, 32, vzext_vf4, pairs) +OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_uint16, 16, __riscv_vzext_vf2, pairs) +OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_int16, 16, __riscv_vzext_vf2, pairs) +OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_uint32, 32, __riscv_vzext_vf4, pairs) +OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_int32, 32, __riscv_vzext_vf4, pairs) +OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_float32, 32, __riscv_vzext_vf4, pairs) -OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_uint16, 16, vzext_vf2, quads) -OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_int16, 16, vzext_vf2, quads) -OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_uint32, 32, vzext_vf4, quads) -OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_int32, 32, vzext_vf4, quads) -OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_float32, 32, vzext_vf4, quads) +OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_uint16, 16, __riscv_vzext_vf2, quads) +OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_int16, 16, __riscv_vzext_vf2, quads) +OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_uint32, 32, __riscv_vzext_vf4, quads) +OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_int32, 32, __riscv_vzext_vf4, quads) +OPENCV_HAL_IMPL_RVV_INTERLEAVED_PQ(v_float32, 32, __riscv_vzext_vf4, quads) //////////// PopCount ////////// static const unsigned char popCountTable[256] = @@ -1701,36 +1708,36 @@ static const unsigned char popCountTable[256] = }; #define OPENCV_HAL_IMPL_RVV_HADD(_Tpvec, _Tpvec2, _Tm2, width, width2, suffix, add) \ static inline _Tpvec2 v_hadd(_Tpvec a) { \ - vuint##width2##m1_t oneX2 = vmv_v_x_u##width2##m1(1, VTraits::vlanes()); \ - vuint##width##m1_t one = vreinterpret_u##width##m1(oneX2); \ - _Tm2 res = add(a, vslide1down(a, 0, VTraits::vlanes()), VTraits::vlanes()); \ - return vget_##suffix##m1(vcompress(vmseq(one, 1, VTraits::vlanes()), res, res, VTraits::vlanes()), 0); \ + vuint##width2##m1_t oneX2 = __riscv_vmv_v_x_u##width2##m1(1, VTraits::vlanes()); \ + vuint##width##m1_t one = __riscv_vreinterpret_u##width##m1(oneX2); \ + _Tm2 res = add(a, __riscv_vslide1down(a, 0, VTraits::vlanes()), VTraits::vlanes()); \ + return __riscv_vget_##suffix##m1(__riscv_vcompress(res, __riscv_vmseq(one, 1, VTraits::vlanes()), VTraits::vlanes()), 0); \ } -OPENCV_HAL_IMPL_RVV_HADD(v_uint8, v_uint16, vuint16m2_t, 8, 16, u16, vwaddu_vv) -OPENCV_HAL_IMPL_RVV_HADD(v_uint16, v_uint32, vuint32m2_t, 16, 32, u32, vwaddu_vv) -OPENCV_HAL_IMPL_RVV_HADD(v_uint32, v_uint64, vuint64m2_t, 32, 64, u64, vwaddu_vv) -OPENCV_HAL_IMPL_RVV_HADD(v_int8, v_int16, vint16m2_t, 8, 16, i16, vwadd_vv) -OPENCV_HAL_IMPL_RVV_HADD(v_int16, v_int32, vint32m2_t, 16, 32, i32, vwadd_vv) -OPENCV_HAL_IMPL_RVV_HADD(v_int32, v_int64, vint64m2_t, 32, 64, i64, vwadd_vv) +OPENCV_HAL_IMPL_RVV_HADD(v_uint8, v_uint16, vuint16m2_t, 8, 16, u16, __riscv_vwaddu_vv) +OPENCV_HAL_IMPL_RVV_HADD(v_uint16, v_uint32, vuint32m2_t, 16, 32, u32, __riscv_vwaddu_vv) +OPENCV_HAL_IMPL_RVV_HADD(v_uint32, v_uint64, vuint64m2_t, 32, 64, u64, __riscv_vwaddu_vv) +OPENCV_HAL_IMPL_RVV_HADD(v_int8, v_int16, vint16m2_t, 8, 16, i16, __riscv_vwadd_vv) +OPENCV_HAL_IMPL_RVV_HADD(v_int16, v_int32, vint32m2_t, 16, 32, i32, __riscv_vwadd_vv) +OPENCV_HAL_IMPL_RVV_HADD(v_int32, v_int64, vint64m2_t, 32, 64, i64, __riscv_vwadd_vv) -OPENCV_HAL_IMPL_RVV_HADD(vint32m2_t, v_int32, vint32m2_t, 16, 32, i32, vadd) -OPENCV_HAL_IMPL_RVV_HADD(vint64m2_t, v_int64, vint64m2_t, 32, 64, i64, vadd) +OPENCV_HAL_IMPL_RVV_HADD(vint32m2_t, v_int32, vint32m2_t, 16, 32, i32, __riscv_vadd) +OPENCV_HAL_IMPL_RVV_HADD(vint64m2_t, v_int64, vint64m2_t, 32, 64, i64, __riscv_vadd) inline v_uint8 v_popcount(const v_uint8& a) { - return vloxei8(popCountTable, a, VTraits::vlanes()); + return __riscv_vloxei8(popCountTable, a, VTraits::vlanes()); } inline v_uint16 v_popcount(const v_uint16& a) { - return v_hadd(v_popcount(vreinterpret_u8m1(a))); + return v_hadd(v_popcount(__riscv_vreinterpret_u8m1(a))); } inline v_uint32 v_popcount(const v_uint32& a) { - return v_hadd(v_hadd(v_popcount(vreinterpret_u8m1(a)))); + return v_hadd(v_hadd(v_popcount(__riscv_vreinterpret_u8m1(a)))); } inline v_uint64 v_popcount(const v_uint64& a) { - return v_hadd(v_hadd(v_hadd(v_popcount(vreinterpret_u8m1(a))))); + return v_hadd(v_hadd(v_hadd(v_popcount(__riscv_vreinterpret_u8m1(a))))); } inline v_uint8 v_popcount(const v_int8& a) @@ -1748,7 +1755,7 @@ inline v_uint32 v_popcount(const v_int32& a) inline v_uint64 v_popcount(const v_int64& a) { // max(0 - a) is used, since v_abs does not support 64-bit integers. - return v_popcount(v_reinterpret_as_u64(vmax(a, v_sub(v_setzero_s64(), a), VTraits::vlanes()))); + return v_popcount(v_reinterpret_as_u64(__riscv_vmax(a, v_sub(v_setzero_s64(), a), VTraits::vlanes()))); } @@ -1757,12 +1764,12 @@ inline v_uint64 v_popcount(const v_int64& a) inline int v_signmask(const _Tpvec& a) \ { \ uint8_t ans[4] = {0}; \ - vsm(ans, vmslt(a, 0, VTraits<_Tpvec>::vlanes()), VTraits<_Tpvec>::vlanes()); \ + __riscv_vsm(ans, __riscv_vmslt(a, 0, VTraits<_Tpvec>::vlanes()), VTraits<_Tpvec>::vlanes()); \ return *(reinterpret_cast(ans)) & (((__int128_t)1 << VTraits<_Tpvec>::vlanes()) - 1); \ } \ inline int v_scan_forward(const _Tpvec& a) \ { \ - return (int)vfirst(vmslt(a, 0, VTraits<_Tpvec>::vlanes()), VTraits<_Tpvec>::vlanes()); \ + return (int)__riscv_vfirst(__riscv_vmslt(a, 0, VTraits<_Tpvec>::vlanes()), VTraits<_Tpvec>::vlanes()); \ } OPENCV_HAL_IMPL_RVV_SIGNMASK_OP(v_int8) @@ -1807,23 +1814,23 @@ inline int v_scan_forward(const v_float64& a) #define OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(_Tpvec, v_trunc) \ inline _Tpvec v_pack_triplets(const _Tpvec& vec) { \ size_t vl = __cv_rvv_e8m1_nlanes; \ - vuint32m1_t one = vmv_v_x_u32m1(1, __cv_rvv_e32m1_nlanes); \ - vuint8m1_t zero = vmv_v_x_u8m1(0, vl); \ - vuint8m1_t mask = vreinterpret_u8m1(one); \ - return vcompress(vmseq(v_trunc(vslideup(zero, mask, 3, vl)), 0, vl), vec, vec, VTraits<_Tpvec>::vlanes()); \ + vuint32m1_t one = __riscv_vmv_v_x_u32m1(1, __cv_rvv_e32m1_nlanes); \ + vuint8m1_t zero = __riscv_vmv_v_x_u8m1(0, vl); \ + vuint8m1_t mask = __riscv_vreinterpret_u8m1(one); \ + return __riscv_vcompress(vec, __riscv_vmseq(v_trunc(__riscv_vslideup(zero, mask, 3, vl)), 0, vl), VTraits<_Tpvec>::vlanes()); \ } OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_uint8, OPENCV_HAL_NOP) OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_int8, OPENCV_HAL_NOP) -OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_uint16, vlmul_trunc_u8mf2) -OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_int16, vlmul_trunc_u8mf2) -OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_uint32, vlmul_trunc_u8mf4) -OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_int32, vlmul_trunc_u8mf4) -OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_float32, vlmul_trunc_u8mf4) -OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_uint64, vlmul_trunc_u8mf8) -OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_int64, vlmul_trunc_u8mf8) +OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_uint16, __riscv_vlmul_trunc_u8mf2) +OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_int16, __riscv_vlmul_trunc_u8mf2) +OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_uint32, __riscv_vlmul_trunc_u8mf4) +OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_int32, __riscv_vlmul_trunc_u8mf4) +OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_float32, __riscv_vlmul_trunc_u8mf4) +OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_uint64, __riscv_vlmul_trunc_u8mf8) +OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_int64, __riscv_vlmul_trunc_u8mf8) #if CV_SIMD_SCALABLE_64F -OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_float64, vlmul_trunc_u8mf8) +OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_float64, __riscv_vlmul_trunc_u8mf8) #endif @@ -1832,12 +1839,12 @@ OPENCV_HAL_IMPL_RVV_PACK_TRIPLETS(v_float64, vlmul_trunc_u8mf8) #if defined(__riscv_zfh) && __riscv_zfh inline v_float32 v_load_expand(const hfloat* ptr) { - return vfwcvt_f(vle16_v_f16mf2((_Float16*)ptr, VTraits::vlanes()) ,VTraits::vlanes());; + return __riscv_vfwcvt_f(__riscv_vle16_v_f16mf2((_Float16*)ptr, VTraits::vlanes()) ,VTraits::vlanes());; } inline void v_pack_store(hfloat* ptr, const v_float32& v) { - vse16_v_f16mf2((_Float16*)ptr, vfncvt_f_f_w_f16mf2(v, VTraits::vlanes()), VTraits::vlanes()); + __riscv_vse16_v_f16mf2((_Float16*)ptr, __riscv_vfncvt_f_f_w_f16mf2(v, VTraits::vlanes()), VTraits::vlanes()); } #else inline v_float32 v_load_expand(const hfloat* ptr) @@ -1858,50 +1865,50 @@ inline void v_pack_store(hfloat* ptr, const v_float32& v) inline v_int32 v_round(const v_float32& a) { // return vfcvt_x(vfadd(a, 1e-6, VTraits::vlanes()), VTraits::vlanes()); - return vfcvt_x(a, VTraits::vlanes()); + return __riscv_vfcvt_x(a, VTraits::vlanes()); } inline v_int32 v_floor(const v_float32& a) { - return vfcvt_x(vfsub(a, 0.5f - 1e-5, VTraits::vlanes()), VTraits::vlanes()); + return __riscv_vfcvt_x(__riscv_vfsub(a, 0.5f - 1e-5, VTraits::vlanes()), VTraits::vlanes()); // return vfcvt_x(a, VTraits::vlanes()); } inline v_int32 v_ceil(const v_float32& a) { - return vfcvt_x(vfadd(a, 0.5f - 1e-5, VTraits::vlanes()), VTraits::vlanes()); + return __riscv_vfcvt_x(__riscv_vfadd(a, 0.5f - 1e-5, VTraits::vlanes()), VTraits::vlanes()); } inline v_int32 v_trunc(const v_float32& a) { - return vfcvt_rtz_x(a, VTraits::vlanes()); + return __riscv_vfcvt_rtz_x(a, VTraits::vlanes()); } #if CV_SIMD_SCALABLE_64F inline v_int32 v_round(const v_float64& a) { - return vfncvt_x(vlmul_ext_f64m2(a), VTraits::vlanes()); + return __riscv_vfncvt_x(__riscv_vlmul_ext_f64m2(a), VTraits::vlanes()); } inline v_int32 v_round(const v_float64& a, const v_float64& b) { // return vfncvt_x(vset(vlmul_ext_f64m2(vfadd(a, 1e-6, VTraits::vlanes())), 1, b), VTraits::vlanes()); // Fix https://github.com/opencv/opencv/issues/24746 - return vfncvt_x(vset(vlmul_ext_f64m2(a), 1, b), VTraits::vlanes()); + return __riscv_vfncvt_x(__riscv_vset(__riscv_vlmul_ext_f64m2(a), 1, b), VTraits::vlanes()); } inline v_int32 v_floor(const v_float64& a) { - return vfncvt_x(vlmul_ext_f64m2(vfsub(a, 0.5f - 1e-6, VTraits::vlanes())), VTraits::vlanes()); + return __riscv_vfncvt_x(__riscv_vlmul_ext_f64m2(__riscv_vfsub(a, 0.5f - 1e-6, VTraits::vlanes())), VTraits::vlanes()); } inline v_int32 v_ceil(const v_float64& a) { - return vfncvt_x(vlmul_ext_f64m2(vfadd(a, 0.5f - 1e-6, VTraits::vlanes())), VTraits::vlanes()); + return __riscv_vfncvt_x(__riscv_vlmul_ext_f64m2(__riscv_vfadd(a, 0.5f - 1e-6, VTraits::vlanes())), VTraits::vlanes()); } inline v_int32 v_trunc(const v_float64& a) { - return vfncvt_rtz_x(vlmul_ext_f64m2(a), VTraits::vlanes()); + return __riscv_vfncvt_rtz_x(__riscv_vlmul_ext_f64m2(a), VTraits::vlanes()); } #endif @@ -1910,154 +1917,154 @@ inline v_int32 v_trunc(const v_float64& a) // 16 >> 32 inline v_int32 v_dotprod(const v_int16& a, const v_int16& b) { - vint32m2_t temp1 = vwmul(a, b, VTraits::vlanes()); + vint32m2_t temp1 = __riscv_vwmul(a, b, VTraits::vlanes()); return v_hadd(temp1); } inline v_int32 v_dotprod(const v_int16& a, const v_int16& b, const v_int32& c) { - vint32m2_t temp1 = vwmul(a, b, VTraits::vlanes()); - return vadd(v_hadd(temp1), c, VTraits::vlanes()); + vint32m2_t temp1 = __riscv_vwmul(a, b, VTraits::vlanes()); + return __riscv_vadd(v_hadd(temp1), c, VTraits::vlanes()); } // 32 >> 64 inline v_int64 v_dotprod(const v_int32& a, const v_int32& b) { - vuint64m1_t one64 = vmv_v_x_u64m1(1, VTraits::vlanes()); \ - vuint32m1_t one32 = vreinterpret_u32m1(one64); \ - vbool32_t mask = vmseq(one32, 1, VTraits::vlanes()); \ - vint64m2_t temp1 = vwmul(a, b, VTraits::vlanes()); \ - vint64m2_t temp2 = vslide1down(temp1, 0, VTraits::vlanes()); - vint64m2_t res = vadd(temp1, temp2, VTraits::vlanes()); - res = vcompress(mask, res, res, VTraits::vlanes()); \ - return vlmul_trunc_i64m1(res); \ + vuint64m1_t one64 = __riscv_vmv_v_x_u64m1(1, VTraits::vlanes()); \ + vuint32m1_t one32 = __riscv_vreinterpret_u32m1(one64); \ + vbool32_t mask = __riscv_vmseq(one32, 1, VTraits::vlanes()); \ + vint64m2_t temp1 = __riscv_vwmul(a, b, VTraits::vlanes()); \ + vint64m2_t temp2 = __riscv_vslide1down(temp1, 0, VTraits::vlanes()); + vint64m2_t res = __riscv_vadd(temp1, temp2, VTraits::vlanes()); + res = __riscv_vcompress(res, mask, VTraits::vlanes()); \ + return __riscv_vlmul_trunc_i64m1(res); \ } inline v_int64 v_dotprod(const v_int32& a, const v_int32& b, const v_int64& c) { - vuint64m1_t one64 = vmv_v_x_u64m1(1, VTraits::vlanes()); \ - vuint32m1_t one32 = vreinterpret_u32m1(one64); \ - vbool32_t mask = vmseq(one32, 1, VTraits::vlanes()); \ - vint64m2_t temp1 = vwmul(a, b, VTraits::vlanes()); \ - vint64m2_t temp2 = vslide1down(temp1, 0, VTraits::vlanes()); - vint64m2_t res = vadd(temp1, temp2, VTraits::vlanes()); - res = vcompress(mask, res, res, VTraits::vlanes()); \ - return vadd(vlmul_trunc_i64m1(res), c, VTraits::vlanes()); \ + vuint64m1_t one64 = __riscv_vmv_v_x_u64m1(1, VTraits::vlanes()); \ + vuint32m1_t one32 = __riscv_vreinterpret_u32m1(one64); \ + vbool32_t mask = __riscv_vmseq(one32, 1, VTraits::vlanes()); \ + vint64m2_t temp1 = __riscv_vwmul(a, b, VTraits::vlanes()); \ + vint64m2_t temp2 = __riscv_vslide1down(temp1, 0, VTraits::vlanes()); + vint64m2_t res = __riscv_vadd(temp1, temp2, VTraits::vlanes()); + res = __riscv_vcompress(res, mask, VTraits::vlanes()); \ + return __riscv_vadd(__riscv_vlmul_trunc_i64m1(res), c, VTraits::vlanes()); \ } // 8 >> 32 inline v_uint32 v_dotprod_expand(const v_uint8& a, const v_uint8& b) { - vuint32m1_t one32 = vmv_v_x_u32m1(1, VTraits::vlanes()); \ - vuint8m1_t one8 = vreinterpret_u8m1(one32); \ - vbool8_t mask = vmseq(one8, 1, VTraits::vlanes()); \ - vuint16m2_t t0 = vwmulu(a, b, VTraits::vlanes()); \ - vuint16m2_t t1= vslide1down(t0, 0, VTraits::vlanes()); - vuint16m2_t t2= vslide1down(t1, 0, VTraits::vlanes()); - vuint16m2_t t3= vslide1down(t2, 0, VTraits::vlanes()); - vuint32m4_t res = vadd(vwaddu_vv(t2, t3, VTraits::vlanes()), vwaddu_vv(t0, t1, VTraits::vlanes()), VTraits::vlanes()); - res = vcompress(mask, res, res, VTraits::vlanes()); \ - return vlmul_trunc_u32m1(res); + vuint32m1_t one32 = __riscv_vmv_v_x_u32m1(1, VTraits::vlanes()); \ + vuint8m1_t one8 = __riscv_vreinterpret_u8m1(one32); \ + vbool8_t mask = __riscv_vmseq(one8, 1, VTraits::vlanes()); \ + vuint16m2_t t0 = __riscv_vwmulu(a, b, VTraits::vlanes()); \ + vuint16m2_t t1= __riscv_vslide1down(t0, 0, VTraits::vlanes()); + vuint16m2_t t2= __riscv_vslide1down(t1, 0, VTraits::vlanes()); + vuint16m2_t t3= __riscv_vslide1down(t2, 0, VTraits::vlanes()); + vuint32m4_t res = __riscv_vadd(__riscv_vwaddu_vv(t2, t3, VTraits::vlanes()), __riscv_vwaddu_vv(t0, t1, VTraits::vlanes()), VTraits::vlanes()); + res = __riscv_vcompress(res, mask, VTraits::vlanes()); \ + return __riscv_vlmul_trunc_u32m1(res); } inline v_uint32 v_dotprod_expand(const v_uint8& a, const v_uint8& b, const v_uint32& c) { - vuint32m1_t one32 = vmv_v_x_u32m1(1, VTraits::vlanes()); \ - vuint8m1_t one8 = vreinterpret_u8m1(one32); \ - vbool8_t mask = vmseq(one8, 1, VTraits::vlanes()); \ - vuint16m2_t t0 = vwmulu(a, b, VTraits::vlanes()); \ - vuint16m2_t t1= vslide1down(t0, 0, VTraits::vlanes()); - vuint16m2_t t2= vslide1down(t1, 0, VTraits::vlanes()); - vuint16m2_t t3= vslide1down(t2, 0, VTraits::vlanes()); - vuint32m4_t res = vadd(vwaddu_vv(t2, t3, VTraits::vlanes()), vwaddu_vv(t0, t1, VTraits::vlanes()), VTraits::vlanes()); - res = vcompress(mask, res, res, VTraits::vlanes()); \ - return vadd(vlmul_trunc_u32m1(res), c, VTraits::vlanes()); + vuint32m1_t one32 = __riscv_vmv_v_x_u32m1(1, VTraits::vlanes()); \ + vuint8m1_t one8 = __riscv_vreinterpret_u8m1(one32); \ + vbool8_t mask = __riscv_vmseq(one8, 1, VTraits::vlanes()); \ + vuint16m2_t t0 = __riscv_vwmulu(a, b, VTraits::vlanes()); \ + vuint16m2_t t1= __riscv_vslide1down(t0, 0, VTraits::vlanes()); + vuint16m2_t t2= __riscv_vslide1down(t1, 0, VTraits::vlanes()); + vuint16m2_t t3= __riscv_vslide1down(t2, 0, VTraits::vlanes()); + vuint32m4_t res = __riscv_vadd(__riscv_vwaddu_vv(t2, t3, VTraits::vlanes()), __riscv_vwaddu_vv(t0, t1, VTraits::vlanes()), VTraits::vlanes()); + res = __riscv_vcompress(res, mask, VTraits::vlanes()); \ + return __riscv_vadd(__riscv_vlmul_trunc_u32m1(res), c, VTraits::vlanes()); } inline v_int32 v_dotprod_expand(const v_int8& a, const v_int8& b) { - vuint32m1_t one32 = vmv_v_x_u32m1(1, VTraits::vlanes()); \ - vuint8m1_t one8 = vreinterpret_u8m1(one32); \ - vbool8_t mask = vmseq(one8, 1, VTraits::vlanes()); \ - vint16m2_t t0 = vwmul(a, b, VTraits::vlanes()); \ - vint16m2_t t1= vslide1down(t0, 0, VTraits::vlanes()); - vint16m2_t t2= vslide1down(t1, 0, VTraits::vlanes()); - vint16m2_t t3= vslide1down(t2, 0, VTraits::vlanes()); - vint32m4_t res = vadd(vwadd_vv(t2, t3, VTraits::vlanes()), vwadd_vv(t0, t1, VTraits::vlanes()), VTraits::vlanes()); - res = vcompress(mask, res, res, VTraits::vlanes()); \ - return vlmul_trunc_i32m1(res); + vuint32m1_t one32 = __riscv_vmv_v_x_u32m1(1, VTraits::vlanes()); \ + vuint8m1_t one8 = __riscv_vreinterpret_u8m1(one32); \ + vbool8_t mask = __riscv_vmseq(one8, 1, VTraits::vlanes()); \ + vint16m2_t t0 = __riscv_vwmul(a, b, VTraits::vlanes()); \ + vint16m2_t t1= __riscv_vslide1down(t0, 0, VTraits::vlanes()); + vint16m2_t t2= __riscv_vslide1down(t1, 0, VTraits::vlanes()); + vint16m2_t t3= __riscv_vslide1down(t2, 0, VTraits::vlanes()); + vint32m4_t res = __riscv_vadd(__riscv_vwadd_vv(t2, t3, VTraits::vlanes()), __riscv_vwadd_vv(t0, t1, VTraits::vlanes()), VTraits::vlanes()); + res = __riscv_vcompress(res, mask, VTraits::vlanes()); \ + return __riscv_vlmul_trunc_i32m1(res); } inline v_int32 v_dotprod_expand(const v_int8& a, const v_int8& b, const v_int32& c) { - vuint32m1_t one32 = vmv_v_x_u32m1(1, VTraits::vlanes()); \ - vuint8m1_t one8 = vreinterpret_u8m1(one32); \ - vbool8_t mask = vmseq(one8, 1, VTraits::vlanes()); \ - vint16m2_t t0 = vwmul(a, b, VTraits::vlanes()); \ - vint16m2_t t1= vslide1down(t0, 0, VTraits::vlanes()); - vint16m2_t t2= vslide1down(t1, 0, VTraits::vlanes()); - vint16m2_t t3= vslide1down(t2, 0, VTraits::vlanes()); - vint32m4_t res = vadd(vwadd_vv(t2, t3, VTraits::vlanes()), vwadd_vv(t0, t1, VTraits::vlanes()), VTraits::vlanes()); - res = vcompress(mask, res, res, VTraits::vlanes()); \ - return vadd(vlmul_trunc_i32m1(res), c, VTraits::vlanes()); + vuint32m1_t one32 = __riscv_vmv_v_x_u32m1(1, VTraits::vlanes()); \ + vuint8m1_t one8 = __riscv_vreinterpret_u8m1(one32); \ + vbool8_t mask = __riscv_vmseq(one8, 1, VTraits::vlanes()); \ + vint16m2_t t0 = __riscv_vwmul(a, b, VTraits::vlanes()); \ + vint16m2_t t1= __riscv_vslide1down(t0, 0, VTraits::vlanes()); + vint16m2_t t2= __riscv_vslide1down(t1, 0, VTraits::vlanes()); + vint16m2_t t3= __riscv_vslide1down(t2, 0, VTraits::vlanes()); + vint32m4_t res = __riscv_vadd(__riscv_vwadd_vv(t2, t3, VTraits::vlanes()), __riscv_vwadd_vv(t0, t1, VTraits::vlanes()), VTraits::vlanes()); + res = __riscv_vcompress(res, mask, VTraits::vlanes()); \ + return __riscv_vadd(__riscv_vlmul_trunc_i32m1(res), c, VTraits::vlanes()); } // // 16 >> 64 inline v_uint64 v_dotprod_expand(const v_uint16& a, const v_uint16& b) { - vuint64m1_t one64 = vmv_v_x_u64m1(1, VTraits::vlanes()); \ - vuint16m1_t one16 = vreinterpret_u16m1(one64); \ - vbool16_t mask = vmseq(one16, 1, VTraits::vlanes()); \ - vuint32m2_t t0 = vwmulu(a, b, VTraits::vlanes()); \ - vuint32m2_t t1= vslide1down(t0, 0, VTraits::vlanes()); - vuint32m2_t t2= vslide1down(t1, 0, VTraits::vlanes()); - vuint32m2_t t3= vslide1down(t2, 0, VTraits::vlanes()); - vuint64m4_t res = vadd(vwaddu_vv(t2, t3, VTraits::vlanes()), vwaddu_vv(t0, t1, VTraits::vlanes()), VTraits::vlanes()); - res = vcompress(mask, res, res, VTraits::vlanes()); \ - return vlmul_trunc_u64m1(res); + vuint64m1_t one64 = __riscv_vmv_v_x_u64m1(1, VTraits::vlanes()); \ + vuint16m1_t one16 = __riscv_vreinterpret_u16m1(one64); \ + vbool16_t mask = __riscv_vmseq(one16, 1, VTraits::vlanes()); \ + vuint32m2_t t0 = __riscv_vwmulu(a, b, VTraits::vlanes()); \ + vuint32m2_t t1= __riscv_vslide1down(t0, 0, VTraits::vlanes()); + vuint32m2_t t2= __riscv_vslide1down(t1, 0, VTraits::vlanes()); + vuint32m2_t t3= __riscv_vslide1down(t2, 0, VTraits::vlanes()); + vuint64m4_t res = __riscv_vadd(__riscv_vwaddu_vv(t2, t3, VTraits::vlanes()), __riscv_vwaddu_vv(t0, t1, VTraits::vlanes()), VTraits::vlanes()); + res = __riscv_vcompress(res, mask, VTraits::vlanes()); \ + return __riscv_vlmul_trunc_u64m1(res); } inline v_uint64 v_dotprod_expand(const v_uint16& a, const v_uint16& b, const v_uint64& c) { - vuint64m1_t one64 = vmv_v_x_u64m1(1, VTraits::vlanes()); \ - vuint16m1_t one16 = vreinterpret_u16m1(one64); \ - vbool16_t mask = vmseq(one16, 1, VTraits::vlanes()); \ - vuint32m2_t t0 = vwmulu(a, b, VTraits::vlanes()); \ - vuint32m2_t t1= vslide1down(t0, 0, VTraits::vlanes()); - vuint32m2_t t2= vslide1down(t1, 0, VTraits::vlanes()); - vuint32m2_t t3= vslide1down(t2, 0, VTraits::vlanes()); - vuint64m4_t res = vadd(vwaddu_vv(t2, t3, VTraits::vlanes()), vwaddu_vv(t0, t1, VTraits::vlanes()), VTraits::vlanes()); - res = vcompress(mask, res, res, VTraits::vlanes()); \ - return vadd(vlmul_trunc_u64m1(res), c, VTraits::vlanes()); + vuint64m1_t one64 = __riscv_vmv_v_x_u64m1(1, VTraits::vlanes()); \ + vuint16m1_t one16 = __riscv_vreinterpret_u16m1(one64); \ + vbool16_t mask = __riscv_vmseq(one16, 1, VTraits::vlanes()); \ + vuint32m2_t t0 = __riscv_vwmulu(a, b, VTraits::vlanes()); \ + vuint32m2_t t1= __riscv_vslide1down(t0, 0, VTraits::vlanes()); + vuint32m2_t t2= __riscv_vslide1down(t1, 0, VTraits::vlanes()); + vuint32m2_t t3= __riscv_vslide1down(t2, 0, VTraits::vlanes()); + vuint64m4_t res = __riscv_vadd(__riscv_vwaddu_vv(t2, t3, VTraits::vlanes()), __riscv_vwaddu_vv(t0, t1, VTraits::vlanes()), VTraits::vlanes()); + res = __riscv_vcompress(res, mask, VTraits::vlanes()); \ + return __riscv_vadd(__riscv_vlmul_trunc_u64m1(res), c, VTraits::vlanes()); } inline v_int64 v_dotprod_expand(const v_int16& a, const v_int16& b) { - vuint64m1_t one64 = vmv_v_x_u64m1(1, VTraits::vlanes()); \ - vuint16m1_t one16 = vreinterpret_u16m1(one64); \ - vbool16_t mask = vmseq(one16, 1, VTraits::vlanes()); \ - vint32m2_t t0 = vwmul(a, b, VTraits::vlanes()); \ - vint32m2_t t1= vslide1down(t0, 0, VTraits::vlanes()); - vint32m2_t t2= vslide1down(t1, 0, VTraits::vlanes()); - vint32m2_t t3= vslide1down(t2, 0, VTraits::vlanes()); - vint64m4_t res = vadd(vwadd_vv(t2, t3, VTraits::vlanes()), vwadd_vv(t0, t1, VTraits::vlanes()), VTraits::vlanes()); - res = vcompress(mask, res, res, VTraits::vlanes()); \ - return vlmul_trunc_i64m1(res); + vuint64m1_t one64 = __riscv_vmv_v_x_u64m1(1, VTraits::vlanes()); \ + vuint16m1_t one16 = __riscv_vreinterpret_u16m1(one64); \ + vbool16_t mask = __riscv_vmseq(one16, 1, VTraits::vlanes()); \ + vint32m2_t t0 = __riscv_vwmul(a, b, VTraits::vlanes()); \ + vint32m2_t t1= __riscv_vslide1down(t0, 0, VTraits::vlanes()); + vint32m2_t t2= __riscv_vslide1down(t1, 0, VTraits::vlanes()); + vint32m2_t t3= __riscv_vslide1down(t2, 0, VTraits::vlanes()); + vint64m4_t res = __riscv_vadd(__riscv_vwadd_vv(t2, t3, VTraits::vlanes()), __riscv_vwadd_vv(t0, t1, VTraits::vlanes()), VTraits::vlanes()); + res = __riscv_vcompress(res, mask, VTraits::vlanes()); \ + return __riscv_vlmul_trunc_i64m1(res); } inline v_int64 v_dotprod_expand(const v_int16& a, const v_int16& b, const v_int64& c) { - vuint64m1_t one64 = vmv_v_x_u64m1(1, VTraits::vlanes()); \ - vuint16m1_t one16 = vreinterpret_u16m1(one64); \ - vbool16_t mask = vmseq(one16, 1, VTraits::vlanes()); \ - vint32m2_t t0 = vwmul(a, b, VTraits::vlanes()); \ - vint32m2_t t1= vslide1down(t0, 0, VTraits::vlanes()); - vint32m2_t t2= vslide1down(t1, 0, VTraits::vlanes()); - vint32m2_t t3= vslide1down(t2, 0, VTraits::vlanes()); - vint64m4_t res = vadd(vwadd_vv(t2, t3, VTraits::vlanes()), vwadd_vv(t0, t1, VTraits::vlanes()), VTraits::vlanes()); - res = vcompress(mask, res, res, VTraits::vlanes()); \ - return vadd(vlmul_trunc_i64m1(res), c, VTraits::vlanes()); + vuint64m1_t one64 = __riscv_vmv_v_x_u64m1(1, VTraits::vlanes()); \ + vuint16m1_t one16 = __riscv_vreinterpret_u16m1(one64); \ + vbool16_t mask = __riscv_vmseq(one16, 1, VTraits::vlanes()); \ + vint32m2_t t0 = __riscv_vwmul(a, b, VTraits::vlanes()); \ + vint32m2_t t1= __riscv_vslide1down(t0, 0, VTraits::vlanes()); + vint32m2_t t2= __riscv_vslide1down(t1, 0, VTraits::vlanes()); + vint32m2_t t3= __riscv_vslide1down(t2, 0, VTraits::vlanes()); + vint64m4_t res = __riscv_vadd(__riscv_vwadd_vv(t2, t3, VTraits::vlanes()), __riscv_vwadd_vv(t0, t1, VTraits::vlanes()), VTraits::vlanes()); + res = __riscv_vcompress(res, mask, VTraits::vlanes()); \ + return __riscv_vadd(__riscv_vlmul_trunc_i64m1(res), c, VTraits::vlanes()); } // // 32 >> 64f @@ -2074,24 +2081,24 @@ inline v_float64 v_dotprod_expand(const v_int32& a, const v_int32& b, inline v_int32 v_dotprod_fast(const v_int16& a, const v_int16& b) { v_int32 zero = v_setzero_s32(); - return vredsum(zero, vwmul(a, b, VTraits::vlanes()), zero, VTraits::vlanes()); + return __riscv_vredsum_tu(zero, __riscv_vwmul(a, b, VTraits::vlanes()), zero, VTraits::vlanes()); } inline v_int32 v_dotprod_fast(const v_int16& a, const v_int16& b, const v_int32& c) { v_int32 zero = v_setzero_s32(); - return vredsum(zero, vwmul(a, b, VTraits::vlanes()), vredsum(zero, c, zero, VTraits::vlanes()), VTraits::vlanes()); + return __riscv_vredsum_tu(zero, __riscv_vwmul(a, b, VTraits::vlanes()), __riscv_vredsum_tu(zero,c, zero, VTraits::vlanes()), VTraits::vlanes()); } // 32 >> 64 inline v_int64 v_dotprod_fast(const v_int32& a, const v_int32& b) { v_int64 zero = v_setzero_s64(); - return vredsum(zero, vwmul(a, b, VTraits::vlanes()), zero, VTraits::vlanes()); + return __riscv_vredsum_tu(zero, __riscv_vwmul(a, b, VTraits::vlanes()), zero, VTraits::vlanes()); } inline v_int64 v_dotprod_fast(const v_int32& a, const v_int32& b, const v_int64& c) { v_int64 zero = v_setzero_s64(); - return vadd(vredsum(zero, vwmul(a, b, VTraits::vlanes()), zero, VTraits::vlanes()) , vredsum(zero, c, zero, VTraits::vlanes()), VTraits::vlanes()); + return __riscv_vadd(__riscv_vredsum_tu(zero,__riscv_vwmul(a, b, VTraits::vlanes()), zero, VTraits::vlanes()) , __riscv_vredsum_tu(zero,c, zero, VTraits::vlanes()), VTraits::vlanes()); } @@ -2099,44 +2106,44 @@ inline v_int64 v_dotprod_fast(const v_int32& a, const v_int32& b, const v_int64& inline v_uint32 v_dotprod_expand_fast(const v_uint8& a, const v_uint8& b) { v_uint32 zero = v_setzero_u32(); - return vwredsumu(zero, vwmulu(a, b, VTraits::vlanes()), zero, VTraits::vlanes()); + return __riscv_vwredsumu_tu(zero, __riscv_vwmulu(a, b, VTraits::vlanes()), zero, VTraits::vlanes()); } inline v_uint32 v_dotprod_expand_fast(const v_uint8& a, const v_uint8& b, const v_uint32& c) { v_uint32 zero = v_setzero_u32(); - return vadd(vwredsumu(zero, vwmulu(a, b, VTraits::vlanes()), zero, VTraits::vlanes()) , vredsum(zero, c, zero, VTraits::vlanes()), VTraits::vlanes()); + return __riscv_vadd(__riscv_vwredsumu_tu(zero, __riscv_vwmulu(a, b, VTraits::vlanes()), zero, VTraits::vlanes()) , __riscv_vredsum_tu(zero, c, zero, VTraits::vlanes()), VTraits::vlanes()); } inline v_int32 v_dotprod_expand_fast(const v_int8& a, const v_int8& b) { v_int32 zero = v_setzero_s32(); - return vwredsum(zero, vwmul(a, b, VTraits::vlanes()), zero, VTraits::vlanes()); + return __riscv_vwredsum_tu(zero, __riscv_vwmul(a, b, VTraits::vlanes()), zero, VTraits::vlanes()); } inline v_int32 v_dotprod_expand_fast(const v_int8& a, const v_int8& b, const v_int32& c) { v_int32 zero = v_setzero_s32(); - return vadd(vwredsum(zero, vwmul(a, b, VTraits::vlanes()), zero, VTraits::vlanes()) , vredsum(zero, c, zero, VTraits::vlanes()), VTraits::vlanes()); + return __riscv_vadd(__riscv_vwredsum_tu(zero, __riscv_vwmul(a, b, VTraits::vlanes()), zero, VTraits::vlanes()) , __riscv_vredsum_tu(zero,c, zero, VTraits::vlanes()), VTraits::vlanes()); } // 16 >> 64 inline v_uint64 v_dotprod_expand_fast(const v_uint16& a, const v_uint16& b) { v_uint64 zero = v_setzero_u64(); - return vwredsumu(zero, vwmulu(a, b, VTraits::vlanes()), zero, VTraits::vlanes()); + return __riscv_vwredsumu_tu(zero, __riscv_vwmulu(a, b, VTraits::vlanes()), zero, VTraits::vlanes()); } inline v_uint64 v_dotprod_expand_fast(const v_uint16& a, const v_uint16& b, const v_uint64& c) { v_uint64 zero = v_setzero_u64(); - return vadd(vwredsumu(zero, vwmulu(a, b, VTraits::vlanes()), zero, VTraits::vlanes()), vredsum(zero, c, zero, VTraits::vlanes()), VTraits::vlanes()); + return __riscv_vadd(__riscv_vwredsumu_tu(zero, __riscv_vwmulu(a, b, VTraits::vlanes()), zero, VTraits::vlanes()), __riscv_vredsum_tu(zero,c, zero, VTraits::vlanes()), VTraits::vlanes()); } inline v_int64 v_dotprod_expand_fast(const v_int16& a, const v_int16& b) { v_int64 zero = v_setzero_s64(); - return vwredsum(zero, vwmul(a, b, VTraits::vlanes()), zero, VTraits::vlanes()); + return __riscv_vwredsum_tu(zero, __riscv_vwmul(a, b, VTraits::vlanes()), zero, VTraits::vlanes()); } inline v_int64 v_dotprod_expand_fast(const v_int16& a, const v_int16& b, const v_int64& c) { v_int64 zero = v_setzero_s64(); - return vadd(vwredsum(zero, vwmul(a, b, VTraits::vlanes()), zero, VTraits::vlanes()), vredsum(zero, c, zero, VTraits::vlanes()), VTraits::vlanes()); + return __riscv_vadd(__riscv_vwredsum_tu(zero, __riscv_vwmul(a, b, VTraits::vlanes()), zero, VTraits::vlanes()), __riscv_vredsum_tu(zero, c, zero, VTraits::vlanes()), VTraits::vlanes()); } // 32 >> 64f @@ -2153,10 +2160,10 @@ inline v_float32 v_matmul(const v_float32& v, const v_float32& m0, const v_float32& m3) { vfloat32m1_t res; - res = vfmul_vf_f32m1(m0, v_extract_n(v, 0), VTraits::vlanes()); - res = vfmacc_vf_f32m1(res, v_extract_n(v, 1), m1, VTraits::vlanes()); - res = vfmacc_vf_f32m1(res, v_extract_n(v, 2), m2, VTraits::vlanes()); - res = vfmacc_vf_f32m1(res, v_extract_n(v, 3), m3, VTraits::vlanes()); + res = __riscv_vfmul_vf_f32m1(m0, v_extract_n(v, 0), VTraits::vlanes()); + res = __riscv_vfmacc_vf_f32m1(res, v_extract_n(v, 1), m1, VTraits::vlanes()); + res = __riscv_vfmacc_vf_f32m1(res, v_extract_n(v, 2), m2, VTraits::vlanes()); + res = __riscv_vfmacc_vf_f32m1(res, v_extract_n(v, 3), m3, VTraits::vlanes()); return res; } @@ -2165,10 +2172,10 @@ inline v_float32 v_matmuladd(const v_float32& v, const v_float32& m0, const v_float32& m1, const v_float32& m2, const v_float32& a) { - vfloat32m1_t res = vfmul_vf_f32m1(m0, v_extract_n(v,0), VTraits::vlanes()); - res = vfmacc_vf_f32m1(res, v_extract_n(v,1), m1, VTraits::vlanes()); - res = vfmacc_vf_f32m1(res, v_extract_n(v,2), m2, VTraits::vlanes()); - return vfadd(res, a, VTraits::vlanes()); + vfloat32m1_t res = __riscv_vfmul_vf_f32m1(m0, v_extract_n(v,0), VTraits::vlanes()); + res = __riscv_vfmacc_vf_f32m1(res, v_extract_n(v,1), m1, VTraits::vlanes()); + res = __riscv_vfmacc_vf_f32m1(res, v_extract_n(v,2), m2, VTraits::vlanes()); + return __riscv_vfadd(res, a, VTraits::vlanes()); } inline void v_cleanup() {} diff --git a/modules/dnn/src/int8layers/fully_connected_layer.cpp b/modules/dnn/src/int8layers/fully_connected_layer.cpp index 105b2dbaac..033c3309ec 100644 --- a/modules/dnn/src/int8layers/fully_connected_layer.cpp +++ b/modules/dnn/src/int8layers/fully_connected_layer.cpp @@ -304,8 +304,8 @@ public: opt_LASX::fastGEMM1T( sptr, wptr, wstep, biasptr, multptr, dptr, nw, vecsize, outZp ); else #endif - #if CV_TRY_RVV && defined(__riscv_v_intrinsic) && __riscv_v_intrinsic>=11000 - if( useRVV) + #if CV_TRY_RVV && CV_RVV + if( useRVV ) opt_RVV::fastGEMM1T( sptr, wptr, wstep, biasptr, multptr, dptr, nw, vecsize, outZp ); else #endif diff --git a/modules/dnn/src/int8layers/layers_common.simd.hpp b/modules/dnn/src/int8layers/layers_common.simd.hpp index 7f9dca505e..281e7c586b 100644 --- a/modules/dnn/src/int8layers/layers_common.simd.hpp +++ b/modules/dnn/src/int8layers/layers_common.simd.hpp @@ -1257,7 +1257,7 @@ void fastGEMM1T( const int8_t* vec, const int8_t* weights, } #endif // CV_LASX -#if !defined(CV_CPU_OPTIMIZATION_DECLARATIONS_ONLY) && CV_RVV && defined(__riscv_v_intrinsic) && __riscv_v_intrinsic>=11000 +#if !defined(CV_CPU_OPTIMIZATION_DECLARATIONS_ONLY) && CV_RVV static const size_t __cv_rvv_e8m1_max = __riscv_vsetvlmax_e8m1(); static const size_t __cv_rvv_e16m1_max = __riscv_vsetvlmax_e16m1(); diff --git a/modules/dnn/src/layers/convolution_layer.cpp b/modules/dnn/src/layers/convolution_layer.cpp index d0791ecddd..3b8da372c9 100644 --- a/modules/dnn/src/layers/convolution_layer.cpp +++ b/modules/dnn/src/layers/convolution_layer.cpp @@ -1667,7 +1667,7 @@ public: opt_AVX::fastGEMM( aptr, astep, bptr, bstep, cptr, cstep, mmax, kmax, nmax ); else #endif - #if CV_TRY_RVV + #if CV_TRY_RVV && CV_RVV if( useRVV ) { opt_RVV::fastGEMM( aptr, astep, bptr, bstep, cptr, cstep, mmax, kmax, nmax ); } diff --git a/modules/dnn/src/layers/cpu_kernels/conv_depthwise.cpp b/modules/dnn/src/layers/cpu_kernels/conv_depthwise.cpp index 8c1c643abe..bfaf431d06 100644 --- a/modules/dnn/src/layers/cpu_kernels/conv_depthwise.cpp +++ b/modules/dnn/src/layers/cpu_kernels/conv_depthwise.cpp @@ -119,7 +119,7 @@ void runDepthwise(InputArray _input, OutputArray _output, const Ptr& c pad_top, pad_left, bias, relu, inptr0, Hi, Wi, outptr0, c, H0, W0); else #endif -#if CV_TRY_RVV +#if CV_TRY_RVV && CV_RVV if(canRunOpt && conv->useRVV) opt_RVV::fastDepthwiseConv(weights, Hk, Wk, stride_h, stride_w, dilation_h, dilation_w, pad_top, pad_left, bias, relu, inptr0, Hi, Wi, outptr0, c, H0, W0); diff --git a/modules/dnn/src/layers/cpu_kernels/conv_depthwise.simd.hpp b/modules/dnn/src/layers/cpu_kernels/conv_depthwise.simd.hpp index 6d4b211b8c..bd5dec0cb1 100644 --- a/modules/dnn/src/layers/cpu_kernels/conv_depthwise.simd.hpp +++ b/modules/dnn/src/layers/cpu_kernels/conv_depthwise.simd.hpp @@ -264,48 +264,48 @@ void fastDepthwiseConv( const float* wptr, if( stride_w == 1 ) for( ; out_j < outW1; out_j += vl, avl -= vl) { - vl = vsetvl_e32m8(avl); + vl = __riscv_vsetvl_e32m8(avl); int in_j = out_j * stride_w - pad_l; - vfloat32m8_t vout0 = vfmacc_vf_f32m8(vfmv_v_f_f32m8(bias, vl), w00, vle32_v_f32m8(imgptr0 + in_j, vl), vl); - vout0 = vfmacc_vf_f32m8(vout0, w01, vle32_v_f32m8(imgptr0 + in_j + dilation_w, vl), vl); - vout0 = vfmacc_vf_f32m8(vout0, w02, vle32_v_f32m8(imgptr0 + in_j + dilation_w*2, vl), vl); - vout0 = vfmacc_vf_f32m8(vout0, w10, vle32_v_f32m8(imgptr1 + in_j, vl),vl); - vout0 = vfmacc_vf_f32m8(vout0, w11, vle32_v_f32m8(imgptr1 + in_j + dilation_w, vl),vl); - vout0 = vfmacc_vf_f32m8(vout0, w12, vle32_v_f32m8(imgptr1 + in_j + dilation_w*2, vl),vl); - vout0 = vfmacc_vf_f32m8(vout0, w20, vle32_v_f32m8(imgptr2 + in_j, vl), vl); - vout0 = vfmacc_vf_f32m8(vout0, w21, vle32_v_f32m8(imgptr2 + in_j + dilation_w, vl), vl); - vout0 = vfmacc_vf_f32m8(vout0, w22, vle32_v_f32m8(imgptr2 + in_j + dilation_w*2, vl), vl); + vfloat32m8_t vout0 = __riscv_vfmacc_vf_f32m8(__riscv_vfmv_v_f_f32m8(bias, vl), w00, __riscv_vle32_v_f32m8(imgptr0 + in_j, vl), vl); + vout0 = __riscv_vfmacc_vf_f32m8(vout0, w01, __riscv_vle32_v_f32m8(imgptr0 + in_j + dilation_w, vl), vl); + vout0 = __riscv_vfmacc_vf_f32m8(vout0, w02, __riscv_vle32_v_f32m8(imgptr0 + in_j + dilation_w*2, vl), vl); + vout0 = __riscv_vfmacc_vf_f32m8(vout0, w10, __riscv_vle32_v_f32m8(imgptr1 + in_j, vl),vl); + vout0 = __riscv_vfmacc_vf_f32m8(vout0, w11, __riscv_vle32_v_f32m8(imgptr1 + in_j + dilation_w, vl),vl); + vout0 = __riscv_vfmacc_vf_f32m8(vout0, w12, __riscv_vle32_v_f32m8(imgptr1 + in_j + dilation_w*2, vl),vl); + vout0 = __riscv_vfmacc_vf_f32m8(vout0, w20, __riscv_vle32_v_f32m8(imgptr2 + in_j, vl), vl); + vout0 = __riscv_vfmacc_vf_f32m8(vout0, w21, __riscv_vle32_v_f32m8(imgptr2 + in_j + dilation_w, vl), vl); + vout0 = __riscv_vfmacc_vf_f32m8(vout0, w22, __riscv_vle32_v_f32m8(imgptr2 + in_j + dilation_w*2, vl), vl); if (relu) { - vbool4_t m = vmfgt_vf_f32m8_b4(vout0, 0, vl); - vout0 = vmerge_vvm_f32m8(m, vfmul_vf_f32m8(vout0, relu_coeff, vl), vout0, vl); + vbool4_t m = __riscv_vmfgt_vf_f32m8_b4(vout0, 0, vl); + vout0 = __riscv_vmerge_vvm_f32m8(__riscv_vfmul_vf_f32m8(vout0, relu_coeff, vl), vout0, m, vl); } - vse32_v_f32m8(outptr + out_j, vout0, vl); + __riscv_vse32_v_f32m8(outptr + out_j, vout0, vl); } else //stride_w == 2 && dilation_w == 1 for( ; out_j < outW1; out_j += vl, avl -= vl) { - vl = vsetvl_e32m2(avl); + vl = __riscv_vsetvl_e32m2(avl); int in_j = out_j * stride_w - pad_l; - vfloat32m2_t vout0 = vfmacc_vf_f32m2(vfmv_v_f_f32m2(bias, vl), w00, vlse32_v_f32m2(imgptr0+in_j , 8, vl), vl); - vfloat32m2_t vout1 = vfmul_vf_f32m2(vlse32_v_f32m2(imgptr0+in_j+1, 8, vl), w01, vl); - vfloat32m2_t vout2 = vfmul_vf_f32m2(vlse32_v_f32m2(imgptr0+in_j+2, 8, vl), w02, vl); + vfloat32m2_t vout0 = __riscv_vfmacc_vf_f32m2(__riscv_vfmv_v_f_f32m2(bias, vl), w00, __riscv_vlse32_v_f32m2(imgptr0+in_j , 8, vl), vl); + vfloat32m2_t vout1 = __riscv_vfmul_vf_f32m2(__riscv_vlse32_v_f32m2(imgptr0+in_j+1, 8, vl), w01, vl); + vfloat32m2_t vout2 = __riscv_vfmul_vf_f32m2(__riscv_vlse32_v_f32m2(imgptr0+in_j+2, 8, vl), w02, vl); - vout0 = vfmacc_vf_f32m2(vout0, w10, vlse32_v_f32m2(imgptr1+in_j , 8, vl), vl); - vout1 = vfmacc_vf_f32m2(vout1, w11, vlse32_v_f32m2(imgptr1+in_j+1, 8, vl), vl); - vout2 = vfmacc_vf_f32m2(vout2, w12, vlse32_v_f32m2(imgptr1+in_j+2, 8, vl), vl); + vout0 = __riscv_vfmacc_vf_f32m2(vout0, w10, __riscv_vlse32_v_f32m2(imgptr1+in_j , 8, vl), vl); + vout1 = __riscv_vfmacc_vf_f32m2(vout1, w11, __riscv_vlse32_v_f32m2(imgptr1+in_j+1, 8, vl), vl); + vout2 = __riscv_vfmacc_vf_f32m2(vout2, w12, __riscv_vlse32_v_f32m2(imgptr1+in_j+2, 8, vl), vl); - vout0 = vfmacc_vf_f32m2(vout0, w20, vlse32_v_f32m2(imgptr2+in_j , 8, vl), vl); - vout1 = vfmacc_vf_f32m2(vout1, w21, vlse32_v_f32m2(imgptr2+in_j+1, 8, vl), vl); - vout2 = vfmacc_vf_f32m2(vout2, w22, vlse32_v_f32m2(imgptr2+in_j+2, 8, vl), vl); + vout0 = __riscv_vfmacc_vf_f32m2(vout0, w20, __riscv_vlse32_v_f32m2(imgptr2+in_j , 8, vl), vl); + vout1 = __riscv_vfmacc_vf_f32m2(vout1, w21, __riscv_vlse32_v_f32m2(imgptr2+in_j+1, 8, vl), vl); + vout2 = __riscv_vfmacc_vf_f32m2(vout2, w22, __riscv_vlse32_v_f32m2(imgptr2+in_j+2, 8, vl), vl); - vout0 = vfadd_vv_f32m2(vfadd_vv_f32m2(vout0, vout1, vl), vout2, vl); + vout0 = __riscv_vfadd_vv_f32m2(__riscv_vfadd_vv_f32m2(vout0, vout1, vl), vout2, vl); if (relu) { - vbool16_t m = vmfgt_vf_f32m2_b16(vout0, 0, vl); - vout0 = vmerge_vvm_f32m2(m, vfmul_vf_f32m2(vout0, relu_coeff, vl), vout0, vl); + vbool16_t m = __riscv_vmfgt_vf_f32m2_b16(vout0, 0, vl); + vout0 = __riscv_vmerge_vvm_f32m2(__riscv_vfmul_vf_f32m2(vout0, relu_coeff, vl), vout0, m, vl); } - vse32_v_f32m2(outptr + out_j, vout0, vl); + __riscv_vse32_v_f32m2(outptr + out_j, vout0, vl); } } diff --git a/modules/dnn/src/layers/fully_connected_layer.cpp b/modules/dnn/src/layers/fully_connected_layer.cpp index 4ff6fc74a4..df540bf2bb 100644 --- a/modules/dnn/src/layers/fully_connected_layer.cpp +++ b/modules/dnn/src/layers/fully_connected_layer.cpp @@ -277,7 +277,7 @@ public: opt_AVX::fastGEMM1T( sptr, wptr, wstep, biasptr, dptr, nw, vecsize_aligned); else #endif - #if CV_TRY_RVV + #if CV_TRY_RVV && CV_RVV if( useRVV ) opt_RVV::fastGEMM1T( sptr, wptr, wstep, biasptr, dptr, nw, vecsize); else diff --git a/modules/dnn/src/layers/layers_common.simd.hpp b/modules/dnn/src/layers/layers_common.simd.hpp index 4bae86911c..8882168ce8 100644 --- a/modules/dnn/src/layers/layers_common.simd.hpp +++ b/modules/dnn/src/layers/layers_common.simd.hpp @@ -295,7 +295,7 @@ void fastGEMM( const float* aptr, size_t astep, const float* bptr, int avl = nb, vl; for(int n = 0; n < nb; n += vl, avl -= vl) { - vl = vsetvl_e32m4(avl); + vl = __riscv_vsetvl_e32m4(avl); for( int m = 0; m < ma; m += 7 ) { const float* aptr0 = aptr + astep*m; @@ -314,13 +314,13 @@ void fastGEMM( const float* aptr, size_t astep, const float* bptr, float* cptr5 = cptr + cstep*std::min(m+5, ma-1); float* cptr6 = cptr + cstep*std::min(m+6, ma-1); - vfloat32m4_t d0 = vfmv_v_f_f32m4(0, vl); - vfloat32m4_t d1 = vfmv_v_f_f32m4(0, vl); - vfloat32m4_t d2 = vfmv_v_f_f32m4(0, vl); - vfloat32m4_t d3 = vfmv_v_f_f32m4(0, vl); - vfloat32m4_t d4 = vfmv_v_f_f32m4(0, vl); - vfloat32m4_t d5 = vfmv_v_f_f32m4(0, vl); - vfloat32m4_t d6 = vfmv_v_f_f32m4(0, vl); + vfloat32m4_t d0 = __riscv_vfmv_v_f_f32m4(0, vl); + vfloat32m4_t d1 = __riscv_vfmv_v_f_f32m4(0, vl); + vfloat32m4_t d2 = __riscv_vfmv_v_f_f32m4(0, vl); + vfloat32m4_t d3 = __riscv_vfmv_v_f_f32m4(0, vl); + vfloat32m4_t d4 = __riscv_vfmv_v_f_f32m4(0, vl); + vfloat32m4_t d5 = __riscv_vfmv_v_f_f32m4(0, vl); + vfloat32m4_t d6 = __riscv_vfmv_v_f_f32m4(0, vl); for( int k = 0; k < na; k++ ) { @@ -332,22 +332,22 @@ void fastGEMM( const float* aptr, size_t astep, const float* bptr, float a5 = aptr5[k]; float a6 = aptr6[k]; - vfloat32m4_t b = vle32_v_f32m4(bptr + k*bstep + n, vl); - d0 = vfmacc_vf_f32m4(d0, a0, b, vl); - d1 = vfmacc_vf_f32m4(d1, a1, b, vl); - d2 = vfmacc_vf_f32m4(d2, a2, b, vl); - d3 = vfmacc_vf_f32m4(d3, a3, b, vl); - d4 = vfmacc_vf_f32m4(d4, a4, b, vl); - d5 = vfmacc_vf_f32m4(d5, a5, b, vl); - d6 = vfmacc_vf_f32m4(d6, a6, b, vl); + vfloat32m4_t b = __riscv_vle32_v_f32m4(bptr + k*bstep + n, vl); + d0 = __riscv_vfmacc_vf_f32m4(d0, a0, b, vl); + d1 = __riscv_vfmacc_vf_f32m4(d1, a1, b, vl); + d2 = __riscv_vfmacc_vf_f32m4(d2, a2, b, vl); + d3 = __riscv_vfmacc_vf_f32m4(d3, a3, b, vl); + d4 = __riscv_vfmacc_vf_f32m4(d4, a4, b, vl); + d5 = __riscv_vfmacc_vf_f32m4(d5, a5, b, vl); + d6 = __riscv_vfmacc_vf_f32m4(d6, a6, b, vl); } - vse32_v_f32m4(cptr0 + n, d0, vl); - vse32_v_f32m4(cptr1 + n, d1, vl); - vse32_v_f32m4(cptr2 + n, d2, vl); - vse32_v_f32m4(cptr3 + n, d3, vl); - vse32_v_f32m4(cptr4 + n, d4, vl); - vse32_v_f32m4(cptr5 + n, d5, vl); - vse32_v_f32m4(cptr6 + n, d6, vl); + __riscv_vse32_v_f32m4(cptr0 + n, d0, vl); + __riscv_vse32_v_f32m4(cptr1 + n, d1, vl); + __riscv_vse32_v_f32m4(cptr2 + n, d2, vl); + __riscv_vse32_v_f32m4(cptr3 + n, d3, vl); + __riscv_vse32_v_f32m4(cptr4 + n, d4, vl); + __riscv_vse32_v_f32m4(cptr5 + n, d5, vl); + __riscv_vse32_v_f32m4(cptr6 + n, d6, vl); } } } @@ -356,112 +356,112 @@ void fastGEMM1T( const float* vec, const float* weights, size_t wstep, const float* bias, float* dst, int nvecs, int vecsize ) { - const int vlm2 = vsetvlmax_e32m2(); + const int vlm2 = __riscv_vsetvlmax_e32m2(); int i = 0; for( ; i <= nvecs - 15; i += 15 ) { const float* wptr = weights + i*wstep; vfloat32m2_t - vs0 = vfmv_v_f_f32m2(0, vlm2), vs1 = vfmv_v_f_f32m2(0, vlm2), vs2 = vfmv_v_f_f32m2(0, vlm2), - vs3 = vfmv_v_f_f32m2(0, vlm2), vs4 = vfmv_v_f_f32m2(0, vlm2), vs5 = vfmv_v_f_f32m2(0, vlm2), - vs6 = vfmv_v_f_f32m2(0, vlm2), vs7 = vfmv_v_f_f32m2(0, vlm2), vs8 = vfmv_v_f_f32m2(0, vlm2), - vs9 = vfmv_v_f_f32m2(0, vlm2), vs10 = vfmv_v_f_f32m2(0, vlm2), vs11 = vfmv_v_f_f32m2(0, vlm2), - vs12 = vfmv_v_f_f32m2(0, vlm2), vs13 = vfmv_v_f_f32m2(0, vlm2), vs14 = vfmv_v_f_f32m2(0, vlm2); + vs0 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs1 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs2 = __riscv_vfmv_v_f_f32m2(0, vlm2), + vs3 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs4 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs5 = __riscv_vfmv_v_f_f32m2(0, vlm2), + vs6 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs7 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs8 = __riscv_vfmv_v_f_f32m2(0, vlm2), + vs9 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs10 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs11 = __riscv_vfmv_v_f_f32m2(0, vlm2), + vs12 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs13 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs14 = __riscv_vfmv_v_f_f32m2(0, vlm2); int avl = vecsize, vl; for(int k = 0 ; k < vecsize; k += vl, wptr += vl, avl -= vl) { - vl = vsetvl_e32m2(avl); - vfloat32m2_t v = vle32_v_f32m2(vec + k, vl); - vs0 = vfmacc_vv_f32m2(vs0, vle32_v_f32m2(wptr, vl), v, vl); - vs1 = vfmacc_vv_f32m2(vs1, vle32_v_f32m2(wptr + wstep, vl), v, vl); - vs2 = vfmacc_vv_f32m2(vs2, vle32_v_f32m2(wptr + wstep*2, vl), v, vl); - vs3 = vfmacc_vv_f32m2(vs3, vle32_v_f32m2(wptr + wstep*3, vl), v, vl); - vs4 = vfmacc_vv_f32m2(vs4, vle32_v_f32m2(wptr + wstep*4, vl), v, vl); - vs5 = vfmacc_vv_f32m2(vs5, vle32_v_f32m2(wptr + wstep*5, vl), v, vl); - vs6 = vfmacc_vv_f32m2(vs6, vle32_v_f32m2(wptr + wstep*6, vl), v, vl); - vs7 = vfmacc_vv_f32m2(vs7, vle32_v_f32m2(wptr + wstep*7, vl), v, vl); - vs8 = vfmacc_vv_f32m2(vs8, vle32_v_f32m2(wptr + wstep*8, vl), v, vl); - vs9 = vfmacc_vv_f32m2(vs9, vle32_v_f32m2(wptr + wstep*9, vl), v, vl); - vs10 = vfmacc_vv_f32m2(vs10, vle32_v_f32m2(wptr + wstep*10, vl), v, vl); - vs11 = vfmacc_vv_f32m2(vs11, vle32_v_f32m2(wptr + wstep*11, vl), v, vl); - vs12 = vfmacc_vv_f32m2(vs12, vle32_v_f32m2(wptr + wstep*12, vl), v, vl); - vs13 = vfmacc_vv_f32m2(vs13, vle32_v_f32m2(wptr + wstep*13, vl), v, vl); - vs14 = vfmacc_vv_f32m2(vs14, vle32_v_f32m2(wptr + wstep*14, vl), v, vl); + vl = __riscv_vsetvl_e32m2(avl); + vfloat32m2_t v = __riscv_vle32_v_f32m2(vec + k, vl); + vs0 = __riscv_vfmacc_vv_f32m2(vs0, __riscv_vle32_v_f32m2(wptr, vl), v, vl); + vs1 = __riscv_vfmacc_vv_f32m2(vs1, __riscv_vle32_v_f32m2(wptr + wstep, vl), v, vl); + vs2 = __riscv_vfmacc_vv_f32m2(vs2, __riscv_vle32_v_f32m2(wptr + wstep*2, vl), v, vl); + vs3 = __riscv_vfmacc_vv_f32m2(vs3, __riscv_vle32_v_f32m2(wptr + wstep*3, vl), v, vl); + vs4 = __riscv_vfmacc_vv_f32m2(vs4, __riscv_vle32_v_f32m2(wptr + wstep*4, vl), v, vl); + vs5 = __riscv_vfmacc_vv_f32m2(vs5, __riscv_vle32_v_f32m2(wptr + wstep*5, vl), v, vl); + vs6 = __riscv_vfmacc_vv_f32m2(vs6, __riscv_vle32_v_f32m2(wptr + wstep*6, vl), v, vl); + vs7 = __riscv_vfmacc_vv_f32m2(vs7, __riscv_vle32_v_f32m2(wptr + wstep*7, vl), v, vl); + vs8 = __riscv_vfmacc_vv_f32m2(vs8, __riscv_vle32_v_f32m2(wptr + wstep*8, vl), v, vl); + vs9 = __riscv_vfmacc_vv_f32m2(vs9, __riscv_vle32_v_f32m2(wptr + wstep*9, vl), v, vl); + vs10 = __riscv_vfmacc_vv_f32m2(vs10, __riscv_vle32_v_f32m2(wptr + wstep*10, vl), v, vl); + vs11 = __riscv_vfmacc_vv_f32m2(vs11, __riscv_vle32_v_f32m2(wptr + wstep*11, vl), v, vl); + vs12 = __riscv_vfmacc_vv_f32m2(vs12, __riscv_vle32_v_f32m2(wptr + wstep*12, vl), v, vl); + vs13 = __riscv_vfmacc_vv_f32m2(vs13, __riscv_vle32_v_f32m2(wptr + wstep*13, vl), v, vl); + vs14 = __riscv_vfmacc_vv_f32m2(vs14, __riscv_vle32_v_f32m2(wptr + wstep*14, vl), v, vl); } // Calculate the sum of each vector float sum[15]; - vfloat32m1_t zero = vfmv_v_f_f32m1(0, vlm2); - sum[0] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs0, zero, vlm2)); - sum[1] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs1, zero, vlm2)); - sum[2] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs2, zero, vlm2)); - sum[3] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs3, zero, vlm2)); - sum[4] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs4, zero, vlm2)); - sum[5] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs5, zero, vlm2)); - sum[6] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs6, zero, vlm2)); - sum[7] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs7, zero, vlm2)); - sum[8] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs8, zero, vlm2)); - sum[9] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs9, zero, vlm2)); - sum[10] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs10, zero, vlm2)); - sum[11] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs11, zero, vlm2)); - sum[12] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs12, zero, vlm2)); - sum[13] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs13, zero, vlm2)); - sum[14] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs14, zero, vlm2)); - - vfloat32m4_t s0 = vfadd_vv_f32m4(vle32_v_f32m4(sum, 15), vle32_v_f32m4(bias + i, 15), 15); - vse32_v_f32m4(dst + i, s0, 15); + vfloat32m1_t zero = __riscv_vfmv_v_f_f32m1(0, vlm2); + sum[0] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs0, zero, vlm2)); + sum[1] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs1, zero, vlm2)); + sum[2] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs2, zero, vlm2)); + sum[3] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs3, zero, vlm2)); + sum[4] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs4, zero, vlm2)); + sum[5] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs5, zero, vlm2)); + sum[6] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs6, zero, vlm2)); + sum[7] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs7, zero, vlm2)); + sum[8] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs8, zero, vlm2)); + sum[9] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs9, zero, vlm2)); + sum[10] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs10, zero, vlm2)); + sum[11] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs11, zero, vlm2)); + sum[12] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs12, zero, vlm2)); + sum[13] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs13, zero, vlm2)); + sum[14] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs14, zero, vlm2)); + + vfloat32m4_t s0 = __riscv_vfadd_vv_f32m4(__riscv_vle32_v_f32m4(sum, 15), __riscv_vle32_v_f32m4(bias + i, 15), 15); + __riscv_vse32_v_f32m4(dst + i, s0, 15); } int unroll_tail = nvecs - i; if (unroll_tail > 0) { const float* wptr = weights + i*wstep; vfloat32m2_t - vs0 = vfmv_v_f_f32m2(0, vlm2), vs1 = vfmv_v_f_f32m2(0, vlm2), vs2 = vfmv_v_f_f32m2(0, vlm2), - vs3 = vfmv_v_f_f32m2(0, vlm2), vs4 = vfmv_v_f_f32m2(0, vlm2), vs5 = vfmv_v_f_f32m2(0, vlm2), - vs6 = vfmv_v_f_f32m2(0, vlm2), vs7 = vfmv_v_f_f32m2(0, vlm2), vs8 = vfmv_v_f_f32m2(0, vlm2), - vs9 = vfmv_v_f_f32m2(0, vlm2), vs10 = vfmv_v_f_f32m2(0, vlm2), vs11 = vfmv_v_f_f32m2(0, vlm2), - vs12 = vfmv_v_f_f32m2(0, vlm2), vs13 = vfmv_v_f_f32m2(0, vlm2); + vs0 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs1 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs2 = __riscv_vfmv_v_f_f32m2(0, vlm2), + vs3 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs4 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs5 = __riscv_vfmv_v_f_f32m2(0, vlm2), + vs6 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs7 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs8 = __riscv_vfmv_v_f_f32m2(0, vlm2), + vs9 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs10 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs11 = __riscv_vfmv_v_f_f32m2(0, vlm2), + vs12 = __riscv_vfmv_v_f_f32m2(0, vlm2), vs13 = __riscv_vfmv_v_f_f32m2(0, vlm2); int avl = vecsize, vl; for(int k = 0; k < vecsize; k += vl, wptr += vl, avl -= vl) { - vl = vsetvl_e32m2(avl); - vfloat32m2_t v = vle32_v_f32m2(vec + k, vl); - vs0 = vfmacc_vv_f32m2(vs0, vle32_v_f32m2(wptr, vl), v, vl); - vs1 = vfmacc_vv_f32m2(vs1, vle32_v_f32m2(wptr + wstep*std::min(1, unroll_tail-1), vl), v, vl); - vs2 = vfmacc_vv_f32m2(vs2, vle32_v_f32m2(wptr + wstep*std::min(2, unroll_tail-1), vl), v, vl); - vs3 = vfmacc_vv_f32m2(vs3, vle32_v_f32m2(wptr + wstep*std::min(3, unroll_tail-1), vl), v, vl); - vs4 = vfmacc_vv_f32m2(vs4, vle32_v_f32m2(wptr + wstep*std::min(4, unroll_tail-1), vl), v, vl); - vs5 = vfmacc_vv_f32m2(vs5, vle32_v_f32m2(wptr + wstep*std::min(5, unroll_tail-1), vl), v, vl); - vs6 = vfmacc_vv_f32m2(vs6, vle32_v_f32m2(wptr + wstep*std::min(6, unroll_tail-1), vl), v, vl); - vs7 = vfmacc_vv_f32m2(vs7, vle32_v_f32m2(wptr + wstep*std::min(7, unroll_tail-1), vl), v, vl); - vs8 = vfmacc_vv_f32m2(vs8, vle32_v_f32m2(wptr + wstep*std::min(8, unroll_tail-1), vl), v, vl); - vs9 = vfmacc_vv_f32m2(vs9, vle32_v_f32m2(wptr + wstep*std::min(9, unroll_tail-1), vl), v, vl); - vs10 = vfmacc_vv_f32m2(vs10, vle32_v_f32m2(wptr + wstep*std::min(10, unroll_tail-1), vl), v, vl); - vs11 = vfmacc_vv_f32m2(vs11, vle32_v_f32m2(wptr + wstep*std::min(11, unroll_tail-1), vl), v, vl); - vs12 = vfmacc_vv_f32m2(vs12, vle32_v_f32m2(wptr + wstep*std::min(12, unroll_tail-1), vl), v, vl); - vs13 = vfmacc_vv_f32m2(vs13, vle32_v_f32m2(wptr + wstep*std::min(13, unroll_tail-1), vl), v, vl); + vl = __riscv_vsetvl_e32m2(avl); + vfloat32m2_t v = __riscv_vle32_v_f32m2(vec + k, vl); + vs0 = __riscv_vfmacc_vv_f32m2(vs0, __riscv_vle32_v_f32m2(wptr, vl), v, vl); + vs1 = __riscv_vfmacc_vv_f32m2(vs1, __riscv_vle32_v_f32m2(wptr + wstep*std::min(1, unroll_tail-1), vl), v, vl); + vs2 = __riscv_vfmacc_vv_f32m2(vs2, __riscv_vle32_v_f32m2(wptr + wstep*std::min(2, unroll_tail-1), vl), v, vl); + vs3 = __riscv_vfmacc_vv_f32m2(vs3, __riscv_vle32_v_f32m2(wptr + wstep*std::min(3, unroll_tail-1), vl), v, vl); + vs4 = __riscv_vfmacc_vv_f32m2(vs4, __riscv_vle32_v_f32m2(wptr + wstep*std::min(4, unroll_tail-1), vl), v, vl); + vs5 = __riscv_vfmacc_vv_f32m2(vs5, __riscv_vle32_v_f32m2(wptr + wstep*std::min(5, unroll_tail-1), vl), v, vl); + vs6 = __riscv_vfmacc_vv_f32m2(vs6, __riscv_vle32_v_f32m2(wptr + wstep*std::min(6, unroll_tail-1), vl), v, vl); + vs7 = __riscv_vfmacc_vv_f32m2(vs7, __riscv_vle32_v_f32m2(wptr + wstep*std::min(7, unroll_tail-1), vl), v, vl); + vs8 = __riscv_vfmacc_vv_f32m2(vs8, __riscv_vle32_v_f32m2(wptr + wstep*std::min(8, unroll_tail-1), vl), v, vl); + vs9 = __riscv_vfmacc_vv_f32m2(vs9, __riscv_vle32_v_f32m2(wptr + wstep*std::min(9, unroll_tail-1), vl), v, vl); + vs10 = __riscv_vfmacc_vv_f32m2(vs10, __riscv_vle32_v_f32m2(wptr + wstep*std::min(10, unroll_tail-1), vl), v, vl); + vs11 = __riscv_vfmacc_vv_f32m2(vs11, __riscv_vle32_v_f32m2(wptr + wstep*std::min(11, unroll_tail-1), vl), v, vl); + vs12 = __riscv_vfmacc_vv_f32m2(vs12, __riscv_vle32_v_f32m2(wptr + wstep*std::min(12, unroll_tail-1), vl), v, vl); + vs13 = __riscv_vfmacc_vv_f32m2(vs13, __riscv_vle32_v_f32m2(wptr + wstep*std::min(13, unroll_tail-1), vl), v, vl); } // Calculate the sum of each vector float sum[14]; - vfloat32m1_t zero = vfmv_v_f_f32m1(0, vlm2); - sum[0] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs0, zero, vlm2)); - sum[1] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs1, zero, vlm2)); - sum[2] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs2, zero, vlm2)); - sum[3] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs3, zero, vlm2)); - sum[4] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs4, zero, vlm2)); - sum[5] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs5, zero, vlm2)); - sum[6] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs6, zero, vlm2)); - sum[7] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs7, zero, vlm2)); - sum[8] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs8, zero, vlm2)); - sum[9] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs9, zero, vlm2)); - sum[10] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs10, zero, vlm2)); - sum[11] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs11, zero, vlm2)); - sum[12] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs12, zero, vlm2)); - sum[13] = vfmv_f_s_f32m1_f32(vfredosum_vs_f32m2_f32m1(zero, vs13, zero, vlm2)); - - vfloat32m4_t s0 = vfadd_vv_f32m4(vle32_v_f32m4(sum, unroll_tail), vle32_v_f32m4(bias + i, unroll_tail), unroll_tail); - vse32_v_f32m4(dst + i, s0, unroll_tail); + vfloat32m1_t zero = __riscv_vfmv_v_f_f32m1(0, vlm2); + sum[0] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs0, zero, vlm2)); + sum[1] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs1, zero, vlm2)); + sum[2] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs2, zero, vlm2)); + sum[3] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs3, zero, vlm2)); + sum[4] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs4, zero, vlm2)); + sum[5] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs5, zero, vlm2)); + sum[6] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs6, zero, vlm2)); + sum[7] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs7, zero, vlm2)); + sum[8] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs8, zero, vlm2)); + sum[9] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs9, zero, vlm2)); + sum[10] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs10, zero, vlm2)); + sum[11] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs11, zero, vlm2)); + sum[12] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs12, zero, vlm2)); + sum[13] = __riscv_vfmv_f_s_f32m1_f32(__riscv_vfredusum_vs_f32m2_f32m1(vs13, zero, vlm2)); + + vfloat32m4_t s0 = __riscv_vfadd_vv_f32m4(__riscv_vle32_v_f32m4(sum, unroll_tail), __riscv_vle32_v_f32m4(bias + i, unroll_tail), unroll_tail); + __riscv_vse32_v_f32m4(dst + i, s0, unroll_tail); } } From 23b244d3a336111c5205c1514b8ef263fac7d808 Mon Sep 17 00:00:00 2001 From: Yuantao Feng Date: Fri, 19 Jul 2024 21:03:19 +0800 Subject: [PATCH 11/18] Merge pull request #25881 from fengyuentau:dnn/cpu/optimize_activations_with_v_exp dnn: optimize activations with v_exp #25881 Merge with https://github.com/opencv/opencv_extra/pull/1191. This PR optimizes the following activations: - [x] Swish - [x] Mish - [x] Elu - [x] Celu - [x] Selu - [x] HardSwish ### Performance (Updated on 2024-07-18) #### AmLogic A311D2 (ARM Cortex A73 + A53) ``` Geometric mean (ms) Name of Test activations activations.patch activations.patch vs activations (x-factor) Celu::Layer_Elementwise::OCV/CPU 115.859 27.930 4.15 Elu::Layer_Elementwise::OCV/CPU 27.846 27.003 1.03 Gelu::Layer_Elementwise::OCV/CPU 0.657 0.602 1.09 HardSwish::Layer_Elementwise::OCV/CPU 31.885 6.781 4.70 Mish::Layer_Elementwise::OCV/CPU 35.729 32.089 1.11 Selu::Layer_Elementwise::OCV/CPU 61.955 27.850 2.22 Swish::Layer_Elementwise::OCV/CPU 30.819 26.688 1.15 ``` #### Apple M1 ``` Geometric mean (ms) Name of Test activations activations.patch activations.patch vs activations (x-factor) Celu::Layer_Elementwise::OCV/CPU 16.184 2.118 7.64 Celu::Layer_Elementwise::OCV/CPU_FP16 16.280 2.123 7.67 Elu::Layer_Elementwise::OCV/CPU 9.123 1.878 4.86 Elu::Layer_Elementwise::OCV/CPU_FP16 9.085 1.897 4.79 Gelu::Layer_Elementwise::OCV/CPU 0.089 0.081 1.11 Gelu::Layer_Elementwise::OCV/CPU_FP16 0.086 0.074 1.17 HardSwish::Layer_Elementwise::OCV/CPU 1.560 1.555 1.00 HardSwish::Layer_Elementwise::OCV/CPU_FP16 1.536 1.523 1.01 Mish::Layer_Elementwise::OCV/CPU 6.077 2.476 2.45 Mish::Layer_Elementwise::OCV/CPU_FP16 5.990 2.496 2.40 Selu::Layer_Elementwise::OCV/CPU 11.351 1.976 5.74 Selu::Layer_Elementwise::OCV/CPU_FP16 11.533 1.985 5.81 Swish::Layer_Elementwise::OCV/CPU 4.687 1.890 2.48 Swish::Layer_Elementwise::OCV/CPU_FP16 4.715 1.873 2.52 ``` #### Intel i7-12700K ``` Geometric mean (ms) Name of Test activations activations.patch activations.patch vs activations (x-factor) Celu::Layer_Elementwise::OCV/CPU 17.106 3.560 4.81 Elu::Layer_Elementwise::OCV/CPU 5.064 3.478 1.46 Gelu::Layer_Elementwise::OCV/CPU 0.036 0.035 1.04 HardSwish::Layer_Elementwise::OCV/CPU 2.914 2.893 1.01 Mish::Layer_Elementwise::OCV/CPU 3.820 3.529 1.08 Selu::Layer_Elementwise::OCV/CPU 10.799 3.593 3.01 Swish::Layer_Elementwise::OCV/CPU 3.651 3.473 1.05 ``` ### Pull Request Readiness Checklist See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request - [x] I agree to contribute to the project under Apache 2 License. - [x] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV - [x] The PR is proposed to the proper branch - [x] There is a reference to the original bug report and related work - [x] There is accuracy test, performance test and test data in opencv_extra repository, if applicable Patch to opencv_extra has the same branch name. - [x] The feature is well documented and sample code can be built with the project CMake --- modules/dnn/perf/perf_layer.cpp | 93 ++++--- modules/dnn/src/layers/elementwise_layers.cpp | 243 ++++++++++++++++-- modules/dnn/test/test_onnx_conformance.cpp | 8 + ...conformance_layer_filter__openvino.inl.hpp | 16 ++ ..._conformance_layer_parser_denylist.inl.hpp | 6 + 5 files changed, 306 insertions(+), 60 deletions(-) diff --git a/modules/dnn/perf/perf_layer.cpp b/modules/dnn/perf/perf_layer.cpp index ea1e70ae30..98adc56ffb 100644 --- a/modules/dnn/perf/perf_layer.cpp +++ b/modules/dnn/perf/perf_layer.cpp @@ -975,49 +975,72 @@ INSTANTIATE_TEST_CASE_P(/**/, Layer_Softmax, Combine( /* withCann= */ false) // only test on CPU )); -using Layer_Elementwise = TestBaseWithParam, std::string, tuple>>; -PERF_TEST_P_(Layer_Elementwise, elementwise) { - std::vector input_shape = get<0>(GetParam()); - std::string op = get<1>(GetParam()); - int backend_id = get<0>(get<2>(GetParam())); - int target_id = get<1>(get<2>(GetParam())); +struct Layer_Elementwise : public TestBaseWithParam> { + void test_layer(const std::string &op_type, const std::vector &input_shape) { + int backend_id = get<0>(GetParam()); + int target_id = get<1>(GetParam()); - Mat input(input_shape, CV_32F); - randn(input, 0.f, 1.f); + Mat input(input_shape, CV_32F); + randu(input, -10.0f, 10.f); - LayerParams lp; - lp.type = op; - lp.name = "TestLayer"; + LayerParams lp; + lp.type = op_type; + lp.name = cv::format("PerfLayer/%s", op_type.c_str()); - Net net; - net.addLayerToPrev(lp.name, lp.type, lp); + Net net; + net.addLayerToPrev(lp.name, lp.type, lp); - // Warmup - { - net.setInput(input); - net.setPreferableBackend(backend_id); - net.setPreferableTarget(target_id); - Mat out = net.forward(); - } + // Warmup + { + net.setInput(input); + net.setPreferableBackend(backend_id); + net.setPreferableTarget(target_id); + net.forward(); + } - TEST_CYCLE() { - net.forward(); + TEST_CYCLE() { + net.forward(); + } + + SANITY_CHECK_NOTHING(); } - SANITY_CHECK_NOTHING(); + int N = 2; + int C = 32; + int H = 416; + int W = 416; +}; + +PERF_TEST_P_(Layer_Elementwise, Gelu) { + test_layer("Gelu", std::vector{1, 50, 3072}); +} +PERF_TEST_P_(Layer_Elementwise, Swish) { + test_layer("Swish", std::vector{N, C, H, W}); +} +PERF_TEST_P_(Layer_Elementwise, Mish) { + test_layer("Mish", std::vector{N, C, H, W}); +} +PERF_TEST_P_(Layer_Elementwise, Elu) { + test_layer("ELU", std::vector{N, C, H, W}); +} +PERF_TEST_P_(Layer_Elementwise, Celu) { + test_layer("Celu", std::vector{N, C, H, W}); +} +PERF_TEST_P_(Layer_Elementwise, Selu) { + test_layer("Selu", std::vector{N, C, H, W}); +} +PERF_TEST_P_(Layer_Elementwise, HardSwish) { + test_layer("HardSwish", std::vector{N, C, H, W}); } -INSTANTIATE_TEST_CASE_P(/**/, Layer_Elementwise, testing::Combine( - testing::Values(std::vector{1, 50, 3072}), - testing::Values(std::string{"Gelu"}), - dnnBackendsAndTargets(/* withInferenceEngine= */ true, - /* withHalide= */ false, - /* withCpuOCV= */ true, - /* withVkCom= */ false, - /* withCUDA= */ true, - /* withNgraph= */ true, - /* withWebnn= */ false, - /* withCann= */ false) // only test on CPU -)); +INSTANTIATE_TEST_CASE_P(/**/, Layer_Elementwise, + dnnBackendsAndTargets(/* withInferenceEngine= */ true, + /* withHalide= */ false, + /* withCpuOCV= */ true, + /* withVkCom= */ false, + /* withCUDA= */ true, + /* withNgraph= */ true, + /* withWebnn= */ false, + /* withCann= */ false)); } // namespace diff --git a/modules/dnn/src/layers/elementwise_layers.cpp b/modules/dnn/src/layers/elementwise_layers.cpp index 477aad88be..6c06554d5f 100644 --- a/modules/dnn/src/layers/elementwise_layers.cpp +++ b/modules/dnn/src/layers/elementwise_layers.cpp @@ -859,12 +859,6 @@ struct GeluFunctor : public BaseFunctor { one = vx_setall_f32(1.0f), reciprocal_sqrt2 = vx_setall_f32(M_SQRT1_2); for (; i <= len - vlanes; i += vlanes) { - if (i + vlanes > len) { - if (i == 0 || i == len) { - break; - } - i = len - vlanes; - } v_float32 x0 = vx_load(srcptr + i); // t = x * M_SQRT1_2 @@ -1048,7 +1042,17 @@ const char* const TanHFunctor::BaseDefaultFunctor::ocl_kernel_name struct SwishFunctor : public BaseDefaultFunctor { - typedef SwishLayer Layer; + using Layer = SwishLayer; + + int vlanes; + + explicit SwishFunctor() { +#if (CV_SIMD || CV_SIMD_SCALABLE) + vlanes = VTraits::vlanes(); +#else + vlanes = 1; +#endif + } bool supportBackend(int backendId, int) { @@ -1064,6 +1068,32 @@ struct SwishFunctor : public BaseDefaultFunctor return x / (1.f + exp(-x)); } + void apply(const float* srcptr, float* dstptr, int stripeStart, int len, size_t planeSize, int cn0, int cn1) const { + CV_UNUSED(stripeStart); + for (int cn = cn0; cn < cn1; cn++, srcptr += planeSize, dstptr += planeSize) { + int i = 0; +#if (CV_SIMD || CV_SIMD_SCALABLE) + // x / (1.f + exp(-x)); + v_float32 one = vx_setall_f32(1.0f), + zero = vx_setzero_f32(); + for (; i <= len - vlanes; i += vlanes) { + v_float32 x = vx_load(srcptr + i); + + v_float32 t = v_sub(zero, x); + t = v_exp(t); + t = v_add(one, t); + t = v_div(x, t); + + vx_store(dstptr + i, t); + } +#endif + // In case SIMD is not available or len < vlanes + for (; i < len; i++) { + dstptr[i] = calculate(srcptr[i]); + } + } + } + #ifdef HAVE_CUDA Ptr initCUDA(int target, csl::Stream stream) { @@ -1116,9 +1146,27 @@ struct SwishFunctor : public BaseDefaultFunctor template<> const char* const SwishFunctor::BaseDefaultFunctor::ocl_kernel_name = "SwishForward"; +namespace { + constexpr float MISH_THRESHOLD = -36.73f; +} + +/* + This implementation is derived from + https://github.com/vpisarev/ficus/blob/3c9a8b78f49e17489c5e1fd6dd5dd487348c99c2/lib/NN/OpElemwise.fx#L110 +*/ struct MishFunctor : public BaseDefaultFunctor { - typedef MishLayer Layer; + using Layer = MishLayer; + + int vlanes; + + explicit MishFunctor() { +#if (CV_SIMD || CV_SIMD_SCALABLE) + vlanes = VTraits::vlanes(); +#else + vlanes = 1; +#endif + } bool supportBackend(int backendId, int) { @@ -1131,15 +1179,34 @@ struct MishFunctor : public BaseDefaultFunctor inline float calculate(float x) const { - // Use fast approximation introduced in https://github.com/opencv/opencv/pull/17200 - if (x >= 8.f) - { - return x; - } + float y = x > MISH_THRESHOLD ? std::exp(-x) : 1.f; + x *= x > MISH_THRESHOLD ? 1.f : 0.f; + return x * (1 + 2 * y) / (1 + 2 * y + 2 * y * y); + } - float eX = exp(x); - float n = (eX + 2.f) * eX; - return (x * n) / (n + 2.f); + void apply(const float* srcptr, float* dstptr, int stripeStart, int len, size_t planeSize, int cn0, int cn1) const { + CV_UNUSED(stripeStart); + for (int cn = cn0; cn < cn1; cn++, srcptr += planeSize, dstptr += planeSize) { + int i = 0; +#if (CV_SIMD || CV_SIMD_SCALABLE) + v_float32 v_threshold = vx_setall_f32(MISH_THRESHOLD), one = vx_setall_f32(1.f), z = vx_setzero_f32(); + for (; i <= len - vlanes; i += vlanes) { + v_float32 x = vx_load(srcptr + i); + + x = v_select(v_le(x, v_threshold), z, x); + v_float32 y = v_exp(v_sub(z, x)); + v_float32 _2y = v_add(y, y), + _2ya1 = v_add(_2y, one); + x = v_div(v_mul(x, _2ya1), v_add(_2ya1, v_mul(_2y, y))); + + vx_store(dstptr + i, x); + } +#endif + // In case SIMD is not available or len < vlanes + for (; i < len; i++) { + dstptr[i] = calculate(srcptr[i]); + } + } } #ifdef HAVE_CUDA @@ -1270,10 +1337,18 @@ const char* const SigmoidFunctor::BaseDefaultFunctor::ocl_kernel struct ELUFunctor : public BaseDefaultFunctor { - typedef ELULayer Layer; + using Layer = ELULayer; + float alpha; + int vlanes; - explicit ELUFunctor(float alpha_ = 1.f) : alpha(alpha_) {} + explicit ELUFunctor(float alpha_ = 1.f) : alpha(alpha_) { +#if (CV_SIMD || CV_SIMD_SCALABLE) + vlanes = VTraits::vlanes(); +#else + vlanes = 1; +#endif + } bool supportBackend(int backendId, int) { @@ -1292,6 +1367,28 @@ struct ELUFunctor : public BaseDefaultFunctor return x >= 0.f ? x : alpha * (exp(x) - 1.f); } + void apply(const float* srcptr, float* dstptr, int stripeStart, int len, size_t planeSize, int cn0, int cn1) const { + CV_UNUSED(stripeStart); + for (int cn = cn0; cn < cn1; cn++, srcptr += planeSize, dstptr += planeSize) { + int i = 0; +#if (CV_SIMD || CV_SIMD_SCALABLE) + v_float32 z = vx_setzero_f32(), v_alpha = vx_setall_f32(alpha), one = vx_setall_f32(1.0f); + for (; i <= len - vlanes; i += vlanes) { + v_float32 x = vx_load(srcptr + i); + + v_float32 t = v_mul(v_alpha, v_sub(v_exp(x), one)); + x = v_select(v_ge(x, z), x, t); + + vx_store(dstptr + i, x); + } +#endif + // In case SIMD is not available or len < vlanes + for (; i < len; i++) { + dstptr[i] = calculate(srcptr[i]); + } + } + } + inline void setKernelParams(ocl::Kernel& kernel) const { kernel.set(3, alpha); @@ -1991,7 +2088,16 @@ const char* const BaseDefaultFunctor::ocl_kernel_name = "ErfForward" struct HardSwishFunctor : public BaseDefaultFunctor { - typedef HardSwishLayer Layer; + using Layer = HardSwishLayer; + int vlanes; + + explicit HardSwishFunctor() { +#if (CV_SIMD || CV_SIMD_SCALABLE) + vlanes = VTraits::vlanes(); +#else + vlanes = 1; +#endif + } bool supportBackend(int backendId, int) { @@ -2002,7 +2108,32 @@ struct HardSwishFunctor : public BaseDefaultFunctor inline float calculate(float x) const { - return x * max(0.f, min(1.f, x / 6.f + 0.5f)); + return x * std::max(0.f, std::min(1.f, x / 6.f + 0.5f)); + } + + void apply(const float* srcptr, float* dstptr, int stripeStart, int len, size_t planeSize, int cn0, int cn1) const { + CV_UNUSED(stripeStart); + for (int cn = cn0; cn < cn1; cn++, srcptr += planeSize, dstptr += planeSize) { + int i = 0; +#if (CV_SIMD || CV_SIMD_SCALABLE) + v_float32 zero = vx_setzero_f32(), one = vx_setall_f32(1.0f), + half = vx_setall_f32(0.5f), sixth = vx_setall_f32(1 / 6.0f); + for (; i <= len - vlanes; i += vlanes) { + v_float32 x = vx_load(srcptr + i); + + v_float32 t = v_add(v_mul(x, sixth), half); + t = v_min(one, t); + t = v_max(zero, t); + t = v_mul(x, t); + + vx_store(dstptr + i, t); + } +#endif + // In case SIMD is not available or len > vlanes + for (; i < len; i++) { + dstptr[i] = calculate(srcptr[i]); + } + } } #ifdef HAVE_CUDA @@ -2176,11 +2307,18 @@ const char* const BaseDefaultFunctor::ocl_kernel_name = "TanForward" struct CeluFunctor : public BaseDefaultFunctor { - typedef CeluLayer Layer; + using Layer = CeluLayer; float alpha; + int vlanes; - explicit CeluFunctor(float alpha_ = 1.f) : alpha(alpha_) {} + explicit CeluFunctor(float alpha_ = 1.f) : alpha(alpha_) { +#if (CV_SIMD || CV_SIMD_SCALABLE) + vlanes = VTraits::vlanes(); +#else + vlanes = 1; +#endif + } bool supportBackend(int backendId, int) { @@ -2189,7 +2327,30 @@ struct CeluFunctor : public BaseDefaultFunctor inline float calculate(float x) const { - return max(0.f, x) + min(0.f, alpha * expm1(x / alpha)); + return std::max(0.f, x) + std::min(0.f, alpha * expm1(x / alpha)); + } + + void apply(const float* srcptr, float* dstptr, int stripeStart, int len, size_t planeSize, int cn0, int cn1) const { + CV_UNUSED(stripeStart); + for (int cn = cn0; cn < cn1; cn++, srcptr += planeSize, dstptr += planeSize) { + int i = 0; +#if (CV_SIMD || CV_SIMD_SCALABLE) + v_float32 zero = vx_setzero_f32(), v_alpha = vx_setall_f32(alpha), + one = vx_setall_f32(1.0f), v_ralpha = vx_setall_f32(1.0f / alpha); + for (; i <= len - vlanes; i += vlanes) { + v_float32 x = vx_load(srcptr + i); + + v_float32 t = v_min(zero, v_mul(v_alpha, v_sub(v_exp(v_mul(x, v_ralpha)), one))); + t = v_add(v_max(zero, x), t); + + vx_store(dstptr + i, t); + } +#endif + // In case SIMD is not available or len < vlanes + for (; i < len; i++) { + dstptr[i] = calculate(srcptr[i]); + } + } } inline void setKernelParams(ocl::Kernel& kernel) const @@ -2250,13 +2411,21 @@ const char* const BaseDefaultFunctor::ocl_kernel_name = "Har struct SeluFunctor : public BaseDefaultFunctor { - typedef SeluLayer Layer; + using Layer = SeluLayer; float alpha; float gamma; + int vlanes; explicit SeluFunctor(float alpha_ = 1.67326319217681884765625f, - float gamma_ = 1.05070102214813232421875f) : alpha(alpha_), gamma(gamma_) {} + float gamma_ = 1.05070102214813232421875f) + : alpha(alpha_), gamma(gamma_) { +#if (CV_SIMD || CV_SIMD_SCALABLE) + vlanes = VTraits::vlanes(); +#else + vlanes = 1; +#endif + } bool supportBackend(int backendId, int) { @@ -2268,6 +2437,30 @@ struct SeluFunctor : public BaseDefaultFunctor return gamma * (x > 0.f ? x : alpha * expm1(x)); } + void apply(const float* srcptr, float* dstptr, int stripeStart, int len, size_t planeSize, int cn0, int cn1) const { + CV_UNUSED(stripeStart); + for (int cn = cn0; cn < cn1; cn++, srcptr += planeSize, dstptr += planeSize) { + int i = 0; +#if (CV_SIMD || CV_SIMD_SCALABLE) + v_float32 z = vx_setzero_f32(), one = vx_setall_f32(1.0f), + v_alpha = vx_setall_f32(alpha), v_gamma = vx_setall_f32(gamma); + for (; i <= len - vlanes; i += vlanes) { + v_float32 x = vx_load(srcptr + i); + + v_float32 t = v_mul(v_alpha, v_sub(v_exp(x), one)); + x = v_select(v_le(x, z), t, x); + x = v_mul(v_gamma, x); + + vx_store(dstptr + i, x); + } +#endif + // In case SIMD is not available or len > vlanes + for (; i < len; i++) { + dstptr[i] = calculate(srcptr[i]); + } + } + } + inline void setKernelParams(ocl::Kernel& kernel) const { kernel.set(3, alpha); diff --git a/modules/dnn/test/test_onnx_conformance.cpp b/modules/dnn/test/test_onnx_conformance.cpp index 47e6f22fce..57969ced87 100644 --- a/modules/dnn/test/test_onnx_conformance.cpp +++ b/modules/dnn/test/test_onnx_conformance.cpp @@ -250,7 +250,10 @@ static const TestCase testConformanceConfig[] = { {"test_einsum_transpose", 1, 1}, {"test_elu", 1, 1}, {"test_elu_default", 1, 1}, + {"test_elu_default_expanded_ver18", 1, 1}, {"test_elu_example", 1, 1}, + {"test_elu_example_expanded_ver18", 1, 1}, + {"test_elu_expanded_ver18", 1, 1}, {"test_equal", 2, 1}, {"test_equal_bcast", 2, 1}, {"test_erf", 1, 1}, @@ -454,6 +457,8 @@ static const TestCase testConformanceConfig[] = { {"test_min_uint32", 2, 1}, {"test_min_uint64", 2, 1}, {"test_min_uint8", 2, 1}, + {"test_mish", 1, 1}, + {"test_mish_expanded", 1, 1}, {"test_mod_broadcast", 2, 1}, {"test_mod_int64_fmod", 2, 1}, {"test_mod_mixed_sign_float16", 2, 1}, @@ -775,7 +780,10 @@ static const TestCase testConformanceConfig[] = { {"test_sce_sum_log_prob_expanded", 2, 2}, {"test_selu", 1, 1}, {"test_selu_default", 1, 1}, + {"test_selu_default_expanded_ver18", 1, 1}, {"test_selu_example", 1, 1}, + {"test_selu_example_expanded_ver18", 1, 1}, + {"test_selu_expanded_ver18", 1, 1}, {"test_sequence_insert_at_back", 2, 1}, {"test_sequence_insert_at_front", 3, 1}, {"test_shape", 1, 1}, diff --git a/modules/dnn/test/test_onnx_conformance_layer_filter__openvino.inl.hpp b/modules/dnn/test/test_onnx_conformance_layer_filter__openvino.inl.hpp index cbbc349bda..9b2a2f4f2d 100644 --- a/modules/dnn/test/test_onnx_conformance_layer_filter__openvino.inl.hpp +++ b/modules/dnn/test/test_onnx_conformance_layer_filter__openvino.inl.hpp @@ -624,8 +624,14 @@ CASE(test_elu) // no filter CASE(test_elu_default) // no filter +CASE(test_elu_default_expanded_ver18) + // no filter CASE(test_elu_example) // no filter +CASE(test_elu_example_expanded_ver18) + // no filter +CASE(test_elu_expanded_ver18) + // no filter CASE(test_equal) // no filter CASE(test_equal_bcast) @@ -1098,6 +1104,10 @@ CASE(test_min_uint64) // no filter CASE(test_min_uint8) // no filter +CASE(test_mish) + // no filter +CASE(test_mish_expanded) + // no filter CASE(test_mod_broadcast) // no filter CASE(test_mod_int64_fmod) @@ -1851,8 +1861,14 @@ CASE(test_selu) // no filter CASE(test_selu_default) // no filter +CASE(test_selu_default_expanded_ver18) + // no filter CASE(test_selu_example) // no filter +CASE(test_selu_example_expanded_ver18) + // no filter +CASE(test_selu_expanded_ver18) + // no filter CASE(test_sequence_insert_at_back) // no filter CASE(test_sequence_insert_at_front) diff --git a/modules/dnn/test/test_onnx_conformance_layer_parser_denylist.inl.hpp b/modules/dnn/test/test_onnx_conformance_layer_parser_denylist.inl.hpp index 7253a64cef..78c26eeea2 100644 --- a/modules/dnn/test/test_onnx_conformance_layer_parser_denylist.inl.hpp +++ b/modules/dnn/test/test_onnx_conformance_layer_parser_denylist.inl.hpp @@ -103,6 +103,9 @@ "test_dynamicquantizelinear_min_adjusted_expanded", "test_edge_pad", "test_einsum_inner_prod", +"test_elu_default_expanded_ver18", +"test_elu_example_expanded_ver18", +"test_elu_expanded_ver18", "test_equal", "test_equal_bcast", "test_expand_dim_changed", @@ -412,6 +415,9 @@ "test_sce_sum_expanded", "test_sce_sum_log_prob", "test_sce_sum_log_prob_expanded", +"test_selu_default_expanded_ver18", +"test_selu_example_expanded_ver18", +"test_selu_expanded_ver18", "test_sequence_insert_at_back", "test_sequence_insert_at_front", "test_shape", From c9b57819b1efd8ee667be7408840a3aaa64962a1 Mon Sep 17 00:00:00 2001 From: cudawarped <12133430+cudawarped@users.noreply.github.com> Date: Mon, 22 Jul 2024 17:41:39 +0300 Subject: [PATCH 12/18] Merge pull request #25874 from cudawarped:videoio_ffmpeg_fix_encapsulate_ts videoio: fix cv::VideoWriter with FFmpeg encapsulation timestamps #25874 Fix https://github.com/opencv/opencv/issues/25873 by modifying `cv::VideoWriter` to use provided presentation indices (pts). ### Pull Request Readiness Checklist See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request - [x] I agree to contribute to the project under Apache 2 License. - [x] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV - [x] The PR is proposed to the proper branch - [x] There is a reference to the original bug report and related work - [x] There is accuracy test, performance test and test data in opencv_extra repository, if applicable Patch to opencv_extra has the same branch name. - [x] The feature is well documented and sample code can be built with the project CMake --- modules/videoio/include/opencv2/videoio.hpp | 8 ++- modules/videoio/src/cap_ffmpeg_impl.hpp | 42 +++++++++++-- modules/videoio/test/test_ffmpeg.cpp | 70 +++++++++++++-------- 3 files changed, 88 insertions(+), 32 deletions(-) diff --git a/modules/videoio/include/opencv2/videoio.hpp b/modules/videoio/include/opencv2/videoio.hpp index fb47036bbf..e5935b7ad5 100644 --- a/modules/videoio/include/opencv2/videoio.hpp +++ b/modules/videoio/include/opencv2/videoio.hpp @@ -211,6 +211,8 @@ enum VideoCaptureProperties { CAP_PROP_CODEC_EXTRADATA_INDEX = 68, //!< Positive index indicates that returning extra data is supported by the video back end. This can be retrieved as cap.retrieve(data, ). E.g. When reading from a h264 encoded RTSP stream, the FFmpeg backend could return the SPS and/or PPS if available (if sent in reply to a DESCRIBE request), from calls to cap.retrieve(data, ). CAP_PROP_FRAME_TYPE = 69, //!< (read-only) FFmpeg back-end only - Frame type ascii code (73 = 'I', 80 = 'P', 66 = 'B' or 63 = '?' if unknown) of the most recently read frame. CAP_PROP_N_THREADS = 70, //!< (**open-only**) Set the maximum number of threads to use. Use 0 to use as many threads as CPU cores (applicable for FFmpeg back-end only). + CAP_PROP_PTS = 71, //!< (read-only) FFmpeg back-end only - presentation timestamp of the most recently read frame using the FPS time base. e.g. fps = 25, VideoCapture::get(\ref CAP_PROP_PTS) = 3, presentation time = 3/25 seconds. + CAP_PROP_DTS_DELAY = 72, //!< (read-only) FFmpeg back-end only - maximum difference between presentation (pts) and decompression timestamps (dts) using FPS time base. e.g. delay is maximum when frame_num = 0, if true, VideoCapture::get(\ref CAP_PROP_PTS) = 0 and VideoCapture::get(\ref CAP_PROP_DTS_DELAY) = 2, dts = -2. Non zero values usually imply the stream is encoded using B-frames which are not decoded in presentation order. #ifndef CV_DOXYGEN CV__CAP_PROP_LATEST #endif @@ -230,8 +232,10 @@ enum VideoWriterProperties { VIDEOWRITER_PROP_HW_DEVICE = 7, //!< (**open-only**) Hardware device index (select GPU if multiple available). Device enumeration is acceleration type specific. VIDEOWRITER_PROP_HW_ACCELERATION_USE_OPENCL= 8, //!< (**open-only**) If non-zero, create new OpenCL context and bind it to current thread. The OpenCL context created with Video Acceleration context attached it (if not attached yet) for optimized GPU data copy between cv::UMat and HW accelerated encoder. VIDEOWRITER_PROP_RAW_VIDEO = 9, //!< (**open-only**) Set to non-zero to enable encapsulation of an encoded raw video stream. Each raw encoded video frame should be passed to VideoWriter::write() as single row or column of a \ref CV_8UC1 Mat. \note If the key frame interval is not 1 then it must be manually specified by the user. This can either be performed during initialization passing \ref VIDEOWRITER_PROP_KEY_INTERVAL as one of the extra encoder params to \ref VideoWriter::VideoWriter(const String &, int, double, const Size &, const std::vector< int > ¶ms) or afterwards by setting the \ref VIDEOWRITER_PROP_KEY_FLAG with \ref VideoWriter::set() before writing each frame. FFMpeg backend only. - VIDEOWRITER_PROP_KEY_INTERVAL = 10, //!< (**open-only**) Set the key frame interval using raw video encapsulation (\ref VIDEOWRITER_PROP_RAW_VIDEO != 0). Defaults to 1 when not set. FFMpeg backend only. - VIDEOWRITER_PROP_KEY_FLAG = 11, //!< Set to non-zero to signal that the following frames are key frames or zero if not, when encapsulating raw video (\ref VIDEOWRITER_PROP_RAW_VIDEO != 0). FFMpeg backend only. + VIDEOWRITER_PROP_KEY_INTERVAL = 10, //!< (**open-only**) Set the key frame interval using raw video encapsulation (\ref VIDEOWRITER_PROP_RAW_VIDEO != 0). Defaults to 1 when not set. FFmpeg back-end only. + VIDEOWRITER_PROP_KEY_FLAG = 11, //!< Set to non-zero to signal that the following frames are key frames or zero if not, when encapsulating raw video (\ref VIDEOWRITER_PROP_RAW_VIDEO != 0). FFmpeg back-end only. + VIDEOWRITER_PROP_PTS = 12, //!< Specifies the frame presentation timestamp for each frame using the FPS time base. This property is **only** necessary when encapsulating **externally** encoded video where the decoding order differs from the presentation order, such as in GOP patterns with bi-directional B-frames. The value should be provided by your external encoder and for video sources with fixed frame rates it is equivalent to dividing the current frame's presentation time (\ref CAP_PROP_POS_MSEC) by the frame duration (1000.0 / VideoCapture::get(\ref CAP_PROP_FPS)). It can be queried from the resulting encapsulated video file using VideoCapture::get(\ref CAP_PROP_PTS). FFmpeg back-end only. + VIDEOWRITER_PROP_DTS_DELAY = 13, //!< Specifies the maximum difference between presentation (pts) and decompression timestamps (dts) using the FPS time base. This property is necessary **only** when encapsulating **externally** encoded video where the decoding order differs from the presentation order, such as in GOP patterns with bi-directional B-frames. The value should be calculated based on the specific GOP pattern used during encoding. For example, in a GOP with presentation order IBP and decoding order IPB, this value would be 1, as the B-frame is the second frame presented but the third to be decoded. It can be queried from the resulting encapsulated video file using VideoCapture::get(\ref CAP_PROP_DTS_DELAY). Non-zero values usually imply the stream is encoded using B-frames. FFmpeg back-end only. #ifndef CV_DOXYGEN CV__VIDEOWRITER_PROP_LATEST #endif diff --git a/modules/videoio/src/cap_ffmpeg_impl.hpp b/modules/videoio/src/cap_ffmpeg_impl.hpp index 1a4aa36d22..c49452bcee 100644 --- a/modules/videoio/src/cap_ffmpeg_impl.hpp +++ b/modules/videoio/src/cap_ffmpeg_impl.hpp @@ -560,6 +560,8 @@ struct CvCapture_FFMPEG AVFrame * picture; AVFrame rgb_picture; int64_t picture_pts; + int64_t pts_in_fps_time_base; + int64_t dts_delay_in_fps_time_base; AVPacket packet; Image_FFMPEG frame; @@ -615,6 +617,8 @@ void CvCapture_FFMPEG::init() video_st = 0; picture = 0; picture_pts = AV_NOPTS_VALUE_; + pts_in_fps_time_base = 0; + dts_delay_in_fps_time_base = 0; first_frame_number = -1; memset( &rgb_picture, 0, sizeof(rgb_picture) ); memset( &frame, 0, sizeof(frame) ); @@ -1581,13 +1585,26 @@ bool CvCapture_FFMPEG::grabFrame() if (valid) { if (picture_pts == AV_NOPTS_VALUE_) { - if (!rawMode) + int64_t dts = 0; + if (!rawMode) { picture_pts = picture->CV_FFMPEG_PTS_FIELD != AV_NOPTS_VALUE_ && picture->CV_FFMPEG_PTS_FIELD != 0 ? picture->CV_FFMPEG_PTS_FIELD : picture->pkt_dts; + if(frame_number == 0) dts = picture->pkt_dts; + } else { const AVPacket& packet_raw = packet.data != 0 ? packet : packet_filtered; picture_pts = packet_raw.pts != AV_NOPTS_VALUE_ && packet_raw.pts != 0 ? packet_raw.pts : packet_raw.dts; + if (frame_number == 0) dts = packet_raw.dts; if (picture_pts < 0) picture_pts = 0; } +#if LIBAVCODEC_BUILD >= CALC_FFMPEG_VERSION(54, 1, 0) || LIBAVFORMAT_BUILD >= CALC_FFMPEG_VERSION(52, 111, 0) + AVRational frame_rate = video_st->avg_frame_rate; +#else + AVRational frame_rate = video_st->r_frame_rate; +#endif + if (picture_pts != AV_NOPTS_VALUE_) + pts_in_fps_time_base = av_rescale_q(picture_pts, video_st->time_base, AVRational{ frame_rate.den, frame_rate.num }); + if (frame_number == 0 && dts != AV_NOPTS_VALUE_) + dts_delay_in_fps_time_base = -av_rescale_q(dts, video_st->time_base, AVRational{ frame_rate.den, frame_rate.num }); frame_number++; } } @@ -1855,6 +1872,11 @@ double CvCapture_FFMPEG::getProperty( int property_id ) const case CAP_PROP_N_THREADS: if (!rawMode) return static_cast(context->thread_count); + break; + case CAP_PROP_PTS: + return static_cast(pts_in_fps_time_base); + case CAP_PROP_DTS_DELAY: + return static_cast(dts_delay_in_fps_time_base); default: break; } @@ -2107,6 +2129,8 @@ struct CvVideoWriter_FFMPEG bool encode_video; int idr_period; bool key_frame; + int pts_index; + int b_frame_dts_delay; }; static const char * icvFFMPEGErrStr(int err) @@ -2175,6 +2199,8 @@ void CvVideoWriter_FFMPEG::init() encode_video = true; idr_period = 0; key_frame = false; + pts_index = -1; + b_frame_dts_delay = 0; } /** @@ -2343,7 +2369,7 @@ static AVCodecContext * icv_configure_video_stream_FFMPEG(AVFormatContext *oc, static const int OPENCV_NO_FRAMES_WRITTEN_CODE = 1000; static int icv_av_encapsulate_video_FFMPEG(AVFormatContext* oc, AVStream* video_st, AVCodecContext* c, - uint8_t* data, int sz, const int frame_idx, const bool key_frame) + uint8_t* data, int sz, const int frame_idx, const int pts_index, const int b_frame_dts_delay, const bool key_frame) { #if LIBAVFORMAT_BUILD < CALC_FFMPEG_VERSION(57, 0, 0) AVPacket pkt_; @@ -2354,7 +2380,9 @@ static int icv_av_encapsulate_video_FFMPEG(AVFormatContext* oc, AVStream* video_ #endif if(key_frame) pkt->flags |= PKT_FLAG_KEY; - pkt->pts = frame_idx; + pkt->pts = pts_index == -1 ? frame_idx : pts_index; + pkt->dts = frame_idx - b_frame_dts_delay; + pkt->duration = 1; pkt->size = sz; pkt->data = data; av_packet_rescale_ts(pkt, c->time_base, video_st->time_base); @@ -2449,7 +2477,7 @@ bool CvVideoWriter_FFMPEG::writeFrame( const unsigned char* data, int step, int if (!encode_video) { CV_Assert(cn == 1 && ((width > 0 && height == 1) || (width == 1 && height > 0 && step == 1))); const bool set_key_frame = key_frame ? key_frame : idr_period ? frame_idx % idr_period == 0 : 1; - bool ret = icv_av_encapsulate_video_FFMPEG(oc, video_st, context, (uint8_t*)data, width, frame_idx, set_key_frame); + bool ret = icv_av_encapsulate_video_FFMPEG(oc, video_st, context, (uint8_t*)data, width, frame_idx, pts_index, b_frame_dts_delay, set_key_frame); frame_idx++; return ret; } @@ -2651,6 +2679,12 @@ bool CvVideoWriter_FFMPEG::setProperty(int property_id, double value) case VIDEOWRITER_PROP_KEY_FLAG: key_frame = static_cast(value); break; + case VIDEOWRITER_PROP_PTS: + pts_index = static_cast(value); + break; + case VIDEOWRITER_PROP_DTS_DELAY: + b_frame_dts_delay = static_cast(value); + break; default: return false; } diff --git a/modules/videoio/test/test_ffmpeg.cpp b/modules/videoio/test/test_ffmpeg.cpp index f4920e75c2..daf1736e62 100644 --- a/modules/videoio/test/test_ffmpeg.cpp +++ b/modules/videoio/test/test_ffmpeg.cpp @@ -293,9 +293,13 @@ const videoio_container_get_params_t videoio_container_get_params[] = INSTANTIATE_TEST_CASE_P(/**/, videoio_container_get, testing::ValuesIn(videoio_container_get_params)); -typedef tuple videoio_encapsulate_params_t; +typedef tuple videoio_encapsulate_params_t; typedef testing::TestWithParam< videoio_encapsulate_params_t > videoio_encapsulate; +#if defined(WIN32) // remove when FFmpeg wrapper includes PR25874 +#define WIN32_WAIT_FOR_FFMPEG_WRAPPER_UPDATE +#endif + TEST_P(videoio_encapsulate, write) { const VideoCaptureAPIs api = CAP_FFMPEG; @@ -307,6 +311,8 @@ TEST_P(videoio_encapsulate, write) const int idrPeriod = get<2>(GetParam()); const int nFrames = get<3>(GetParam()); const string fileNameOut = tempfile(cv::format("test_encapsulated_stream.%s", ext.c_str()).c_str()); + const bool setPts = get<4>(GetParam()); + const bool tsWorking = get<5>(GetParam()); // Use VideoWriter to encapsulate encoded video read with VideoReader { @@ -320,12 +326,16 @@ TEST_P(videoio_encapsulate, write) capRaw.retrieve(extraData, codecExtradataIndex); const int fourcc = static_cast(capRaw.get(CAP_PROP_FOURCC)); const bool mpeg4 = (fourcc == fourccFromString("FMP4")); - VideoWriter container(fileNameOut, api, fourcc, fps, { width, height }, { VideoWriterProperties::VIDEOWRITER_PROP_RAW_VIDEO, 1, VideoWriterProperties::VIDEOWRITER_PROP_KEY_INTERVAL, idrPeriod }); ASSERT_TRUE(container.isOpened()); Mat rawFrame; for (int i = 0; i < nFrames; i++) { ASSERT_TRUE(capRaw.read(rawFrame)); +#if !defined(WIN32_WAIT_FOR_FFMPEG_WRAPPER_UPDATE) + if (setPts && i == 0) { + ASSERT_TRUE(container.set(VIDEOWRITER_PROP_DTS_DELAY, capRaw.get(CAP_PROP_DTS_DELAY))); + } +#endif ASSERT_FALSE(rawFrame.empty()); if (i == 0 && mpeg4) { Mat tmp = rawFrame.clone(); @@ -336,6 +346,11 @@ TEST_P(videoio_encapsulate, write) memcpy(rawFrame.data, extraData.data, extraData.total()); memcpy(rawFrame.data + extraData.total(), tmp.data, tmp.total()); } +#if !defined(WIN32_WAIT_FOR_FFMPEG_WRAPPER_UPDATE) + if (setPts) { + ASSERT_TRUE(container.set(VIDEOWRITER_PROP_PTS, capRaw.get(CAP_PROP_PTS))); + } +#endif container.write(rawFrame); } container.release(); @@ -362,11 +377,15 @@ TEST_P(videoio_encapsulate, write) ASSERT_TRUE(capActual.read(actual)); ASSERT_FALSE(actual.empty()); ASSERT_EQ(0, cvtest::norm(reference, actual, NORM_INF)); - ASSERT_TRUE(capActualRaw.grab()); const bool keyFrameActual = capActualRaw.get(CAP_PROP_LRF_HAS_KEY_FRAME) == 1.; const bool keyFrameReference = idrPeriod ? i % idrPeriod == 0 : 1; ASSERT_EQ(keyFrameReference, keyFrameActual); +#if !defined(WIN32_WAIT_FOR_FFMPEG_WRAPPER_UPDATE) + if (tsWorking) { + ASSERT_EQ(round(capReference.get(CAP_PROP_POS_MSEC)), round(capActual.get(CAP_PROP_POS_MSEC))); + } +#endif } } @@ -375,30 +394,29 @@ TEST_P(videoio_encapsulate, write) const videoio_encapsulate_params_t videoio_encapsulate_params[] = { - videoio_encapsulate_params_t("video/big_buck_bunny.h264", "avi", 125, 125), - videoio_encapsulate_params_t("video/big_buck_bunny.h265", "mp4", 125, 125), - videoio_encapsulate_params_t("video/big_buck_bunny.wmv", "wmv", 12, 13), - videoio_encapsulate_params_t("video/big_buck_bunny.mp4", "mp4", 12, 13), - videoio_encapsulate_params_t("video/big_buck_bunny.mjpg.avi", "mp4", 0, 4), - videoio_encapsulate_params_t("video/big_buck_bunny.mov", "mp4", 12, 13), - videoio_encapsulate_params_t("video/big_buck_bunny.avi", "mp4", 125, 125), - videoio_encapsulate_params_t("video/big_buck_bunny.mpg", "mp4", 12, 13), - videoio_encapsulate_params_t("video/VID00003-20100701-2204.wmv", "wmv", 12, 13), - videoio_encapsulate_params_t("video/VID00003-20100701-2204.mpg", "mp4", 12,13), - videoio_encapsulate_params_t("video/VID00003-20100701-2204.avi", "mp4", 12, 13), - videoio_encapsulate_params_t("video/VID00003-20100701-2204.3GP", "mp4", 51, 52), - videoio_encapsulate_params_t("video/sample_sorenson.avi", "mp4", 12, 13), - videoio_encapsulate_params_t("video/sample_322x242_15frames.yuv420p.libxvid.mp4", "mp4", 3, 4), - videoio_encapsulate_params_t("video/sample_322x242_15frames.yuv420p.mpeg2video.mp4", "mp4", 12, 13), - videoio_encapsulate_params_t("video/sample_322x242_15frames.yuv420p.mjpeg.mp4", "mp4", 0, 5), - videoio_encapsulate_params_t("video/sample_322x242_15frames.yuv420p.libx264.mp4", "avi", 15, 15), - videoio_encapsulate_params_t("../cv/tracking/faceocc2/data/faceocc2.webm", "webm", 128, 129), - videoio_encapsulate_params_t("../cv/video/1920x1080.avi", "mp4", 12, 13), - videoio_encapsulate_params_t("../cv/video/768x576.avi", "avi", 15, 16) + videoio_encapsulate_params_t("video/big_buck_bunny.h264", "avi", 125, 125, false, false), // tsWorking = false: no timestamp information + videoio_encapsulate_params_t("video/big_buck_bunny.h265", "mp4", 125, 125, false, false), // tsWorking = false: no timestamp information + videoio_encapsulate_params_t("video/big_buck_bunny.wmv", "wmv", 12, 13, false, true), + videoio_encapsulate_params_t("video/big_buck_bunny.mp4", "mp4", 12, 13, false, true), + videoio_encapsulate_params_t("video/big_buck_bunny.mjpg.avi", "mp4", 0, 4, false, true), + videoio_encapsulate_params_t("video/big_buck_bunny.mov", "mp4", 12, 13, false, true), + videoio_encapsulate_params_t("video/big_buck_bunny.avi", "mp4", 125, 125, false, false), // tsWorking = false: PTS not available for all frames + videoio_encapsulate_params_t("video/big_buck_bunny.mpg", "mp4", 12, 13, true, true), + videoio_encapsulate_params_t("video/VID00003-20100701-2204.wmv", "wmv", 12, 13, false, true), + videoio_encapsulate_params_t("video/VID00003-20100701-2204.mpg", "mp4", 12, 13, false, false), // tsWorking = false: PTS not available for all frames + videoio_encapsulate_params_t("video/VID00003-20100701-2204.avi", "mp4", 12, 13, false, false), // tsWorking = false: Unable to correctly set PTS when writing + videoio_encapsulate_params_t("video/VID00003-20100701-2204.3GP", "mp4", 51, 52, false, false), // tsWorking = false: Source with variable fps + videoio_encapsulate_params_t("video/sample_sorenson.avi", "mp4", 12, 13, false, true), + videoio_encapsulate_params_t("video/sample_322x242_15frames.yuv420p.libxvid.mp4", "mp4", 3, 4, false, true), + videoio_encapsulate_params_t("video/sample_322x242_15frames.yuv420p.mpeg2video.mp4", "mpg", 12, 13, false, true), + videoio_encapsulate_params_t("video/sample_322x242_15frames.yuv420p.mjpeg.mp4", "mp4", 0, 5, false, true), + videoio_encapsulate_params_t("video/sample_322x242_15frames.yuv420p.libx264.mp4", "ts", 15, 15, true, true), + videoio_encapsulate_params_t("../cv/tracking/faceocc2/data/faceocc2.webm", "webm", 128, 129, false, true), + videoio_encapsulate_params_t("../cv/video/1920x1080.avi", "mp4", 12, 13, false, true), + videoio_encapsulate_params_t("../cv/video/768x576.avi", "avi", 15, 16, false, true), // Not supported by with FFmpeg: - //videoio_encapsulate_params_t("video/sample_322x242_15frames.yuv420p.libx265.mp4", "mp4", 15, 15), - //videoio_encapsulate_params_t("video/sample_322x242_15frames.yuv420p.libvpx-vp9.mp4", "mp4", 15, 15), - + //videoio_encapsulate_params_t("video/sample_322x242_15frames.yuv420p.libx265.mp4", "mp4", 15, 15, true, true), + //videoio_encapsulate_params_t("video/sample_322x242_15frames.yuv420p.libvpx-vp9.mp4", "mp4", 15, 15, false, true), }; INSTANTIATE_TEST_CASE_P(/**/, videoio_encapsulate, testing::ValuesIn(videoio_encapsulate_params)); From 012d8534745fb2261943d90bf6026fca2001357a Mon Sep 17 00:00:00 2001 From: cudawarped <12133430+cudawarped@users.noreply.github.com> Date: Mon, 22 Jul 2024 18:00:36 +0300 Subject: [PATCH 13/18] cuda: prevent CMAKE_CUDA_ARCHITECTURES default from overiding OpenCV architecture search --- CMakeLists.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 939ce79631..0693731a8b 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -726,7 +726,13 @@ if(ENABLE_CUDA_FIRST_CLASS_LANGUAGE) cmake_policy(SET CMP0092 NEW) # CMake 3.15+: leave warning flags out of default CMAKE__FLAGS flags. if(CMAKE_CUDA_COMPILER) + if(CMAKE_CUDA_ARCHITECTURES) + set(USER_DEFINED_CMAKE_CUDA_ARCHITECTURES TRUE) + endif() enable_language(CUDA) + if(NOT USER_DEFINED_CMAKE_CUDA_ARCHITECTURES) + set(CMAKE_CUDA_ARCHITECTURES "") + endif() elseif(UNIX) message(WARNING "CUDA: Not detected! If you are not using the default host compiler (g++) then you need to specify both CMAKE_CUDA_HOST_COMPILER and CMAKE_CUDA_COMPILER. e.g. -DCMAKE_CUDA_HOST_COMPILER=/usr/bin/clang++ -DCMAKE_CUDA_COMPILER=/usr/local/cuda/bin/nvcc.") endif() From 44c814e3340151b36343e218ceead1790661b8b5 Mon Sep 17 00:00:00 2001 From: Rostislav Vasilikhin Date: Tue, 23 Jul 2024 07:06:15 +0200 Subject: [PATCH 14/18] Merge pull request #25936 from savuor:rv/hal_dot HAL for dot product added #25936 ### Pull Request Readiness Checklist See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request - [x] I agree to contribute to the project under Apache 2 License. - [x] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV - [x] The PR is proposed to the proper branch - [ ] There is a reference to the original bug report and related work - [ ] There is accuracy test, performance test and test data in opencv_extra repository, if applicable Patch to opencv_extra has the same branch name. - [x] The feature is well documented and sample code can be built with the project CMake --- modules/core/src/hal_replacement.hpp | 21 +++++++++++++++++++++ modules/core/src/matmul.dispatch.cpp | 11 ++++++++++- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/modules/core/src/hal_replacement.hpp b/modules/core/src/hal_replacement.hpp index f78608dbad..67f3ac7141 100644 --- a/modules/core/src/hal_replacement.hpp +++ b/modules/core/src/hal_replacement.hpp @@ -899,6 +899,27 @@ inline int hal_ni_meanStdDev(const uchar* src_data, size_t src_step, int width, #define cv_hal_meanStdDev hal_ni_meanStdDev //! @endcond +/** + * @brief calculates dot product of two vectors (represented as 2d images) + * + * @param a_data Pointer to 1st 2nd image data + * @param a_step Stride of 1st 2nd image + * @param b_data Pointer to 1st 2nd image data + * @param b_step Stride of 1st 2nd image + * @param width Width of both images + * @param height Height of both images + * @param type Data type of both images, for example CV_8U or CV_32F + * @param dot_val Pointer to resulting dot product value + * @return int + */ +inline int hal_ni_dotProduct(const uchar* a_data, size_t a_step, const uchar* b_data, size_t b_step, int width, int height, + int type, double *dot_val) +{ return CV_HAL_ERROR_NOT_IMPLEMENTED; } + +//! @cond IGNORED +#define cv_hal_dotProduct hal_ni_dotProduct +//! @endcond + /** @brief hal_flip @param src_type source and destination image type diff --git a/modules/core/src/matmul.dispatch.cpp b/modules/core/src/matmul.dispatch.cpp index 81953265d7..35b7ad54c4 100644 --- a/modules/core/src/matmul.dispatch.cpp +++ b/modules/core/src/matmul.dispatch.cpp @@ -995,9 +995,18 @@ double Mat::dot(InputArray _mat) const CV_INSTRUMENT_REGION(); Mat mat = _mat.getMat(); + CV_Assert_N( mat.type() == type(), mat.size == size); + int cn = channels(); + if (this->dims <= 2) + { + double product = 0; + CALL_HAL_RET(dotProduct, cv_hal_dotProduct, product, this->data, this->step, mat.data, mat.step, + this->cols * cn, this->rows, this->depth()); + } + DotProdFunc func = getDotProdFunc(depth()); - CV_Assert_N( mat.type() == type(), mat.size == size, func != 0 ); + CV_Assert(func != 0 ); if( isContinuous() && mat.isContinuous() ) { From 38cfea981f0f8d6d59b214e37e597c7dceac4793 Mon Sep 17 00:00:00 2001 From: Alexander Smorkalov Date: Tue, 23 Jul 2024 12:03:39 +0300 Subject: [PATCH 15/18] Report used HAL to test log and xml --- modules/ts/src/ts.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/modules/ts/src/ts.cpp b/modules/ts/src/ts.cpp index 9fe5cb3937..f60ba9dd2b 100644 --- a/modules/ts/src/ts.cpp +++ b/modules/ts/src/ts.cpp @@ -1127,6 +1127,7 @@ void SystemInfoCollector::OnTestProgramStart(const testing::UnitTest&) recordPropertyVerbose("cv_build_type", "Build type", getSnippetFromConfig("Configuration:", "\n"), CV_TEST_BUILD_CONFIG); recordPropertyVerbose("cv_compiler", "Compiler", getSnippetFromConfig("C++ Compiler:", "\n")); recordPropertyVerbose("implementation_hint", "Algorithm hint", getSnippetFromConfig("Algorithm Hint:", "\n")); + recordPropertyVerbose("hal", "HAL", getSnippetFromConfig("Custom HAL:", "\n")); const char* parallelFramework = cv::currentParallelFramework(); if (parallelFramework) { From e1b57057bf1eed3cb50be1786d592f255f24b4b5 Mon Sep 17 00:00:00 2001 From: Vincent Rabaud Date: Tue, 23 Jul 2024 16:22:55 +0200 Subject: [PATCH 16/18] Avoid future integer overflow in _OutputArray::create This fix is useless in 4.x and fixes harmless overflows in 5.x This belongs to 4.x as it is closer to the intended meaning. --- modules/core/src/matrix_wrap.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/core/src/matrix_wrap.cpp b/modules/core/src/matrix_wrap.cpp index 238fc642fd..b72fdbe784 100644 --- a/modules/core/src/matrix_wrap.cpp +++ b/modules/core/src/matrix_wrap.cpp @@ -1294,7 +1294,7 @@ void _OutputArray::create(int d, const int* sizes, int mtype, int i, if(fixedType()) { - if(CV_MAT_CN(mtype) == m.channels() && ((1 << CV_MAT_TYPE(flags)) & fixedDepthMask) != 0 ) + if(CV_MAT_CN(mtype) == m.channels() && ((1 << CV_MAT_DEPTH(flags)) & fixedDepthMask) != 0 ) mtype = m.type(); else CV_CheckTypeEQ(m.type(), CV_MAT_TYPE(mtype), "Can't reallocate Mat with locked type (probably due to misused 'const' modifier)"); From c16927605da799effea827345dbc116086e38891 Mon Sep 17 00:00:00 2001 From: Vincent Rabaud Date: Wed, 24 Jul 2024 08:27:07 +0200 Subject: [PATCH 17/18] Merge pull request #25938 from vrabaud:charuco Properly check markers when none are provided. #25938 CharucoDetectorImpl::detectBoard finds temporary markers when none are provided but those are discarded when charucoDetectorImpl::checkBoard is called. ### Pull Request Readiness Checklist See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request - [x] I agree to contribute to the project under Apache 2 License. - [x] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV - [x] The PR is proposed to the proper branch - [x] There is a reference to the original bug report and related work - [x] There is accuracy test, performance test and test data in opencv_extra repository, if applicable Patch to opencv_extra has the same branch name. - [x] The feature is well documented and sample code can be built with the project CMake --- .../objdetect/src/aruco/charuco_detector.cpp | 24 ++++++++++------ .../objdetect/test/test_charucodetection.cpp | 28 +++++++++++-------- 2 files changed, 33 insertions(+), 19 deletions(-) diff --git a/modules/objdetect/src/aruco/charuco_detector.cpp b/modules/objdetect/src/aruco/charuco_detector.cpp index 4f08747289..77f614d4d0 100644 --- a/modules/objdetect/src/aruco/charuco_detector.cpp +++ b/modules/objdetect/src/aruco/charuco_detector.cpp @@ -326,8 +326,21 @@ struct CharucoDetector::CharucoDetectorImpl { interpolateCornersCharucoLocalHom(_markerCorners, _markerIds, image, charucoCorners, charucoIds); // to return a charuco corner, its closest aruco markers should have been detected filterCornersWithoutMinMarkers(charucoCorners, charucoIds, _markerIds, charucoCorners, charucoIds); -} + } + void detectBoardWithCheck(InputArray image, OutputArray charucoCorners, OutputArray charucoIds, + InputOutputArrayOfArrays markerCorners, InputOutputArray markerIds) { + vector> tmpMarkerCorners; + vector tmpMarkerIds; + InputOutputArrayOfArrays _markerCorners = markerCorners.needed() ? markerCorners : tmpMarkerCorners; + InputOutputArray _markerIds = markerIds.needed() ? markerIds : tmpMarkerIds; + detectBoard(image, charucoCorners, charucoIds, _markerCorners, _markerIds); + if (checkBoard(_markerCorners, _markerIds, charucoCorners, charucoIds) == false) { + CV_LOG_DEBUG(NULL, "ChArUco board is built incorrectly"); + charucoCorners.release(); + charucoIds.release(); + } + } }; CharucoDetector::CharucoDetector(const CharucoBoard &board, const CharucoParameters &charucoParams, @@ -370,12 +383,7 @@ void CharucoDetector::setRefineParameters(const RefineParameters& refineParamete void CharucoDetector::detectBoard(InputArray image, OutputArray charucoCorners, OutputArray charucoIds, InputOutputArrayOfArrays markerCorners, InputOutputArray markerIds) const { - charucoDetectorImpl->detectBoard(image, charucoCorners, charucoIds, markerCorners, markerIds); - if (charucoDetectorImpl->checkBoard(markerCorners, markerIds, charucoCorners, charucoIds) == false) { - CV_LOG_DEBUG(NULL, "ChArUco board is built incorrectly"); - charucoCorners.release(); - charucoIds.release(); - } + charucoDetectorImpl->detectBoardWithCheck(image, charucoCorners, charucoIds, markerCorners, markerIds); } void CharucoDetector::detectDiamonds(InputArray image, OutputArrayOfArrays _diamondCorners, OutputArray _diamondIds, @@ -480,7 +488,7 @@ void CharucoDetector::detectDiamonds(InputArray image, OutputArrayOfArrays _diam // interpolate the charuco corners of the diamond vector currentMarkerCorners; Mat aux; - charucoDetectorImpl->detectBoard(grey, currentMarkerCorners, aux, currentMarker, currentMarkerId); + charucoDetectorImpl->detectBoardWithCheck(grey, currentMarkerCorners, aux, currentMarker, currentMarkerId); // if everything is ok, save the diamond if(currentMarkerCorners.size() > 0ull) { diff --git a/modules/objdetect/test/test_charucodetection.cpp b/modules/objdetect/test/test_charucodetection.cpp index ab66e77665..4738c74acb 100644 --- a/modules/objdetect/test/test_charucodetection.cpp +++ b/modules/objdetect/test/test_charucodetection.cpp @@ -762,23 +762,29 @@ TEST_P(CharucoBoard, testWrongSizeDetection) ASSERT_FALSE(boardSize.width == boardSize.height); aruco::CharucoBoard board(boardSize, 1.f, 0.5f, aruco::getPredefinedDictionary(aruco::DICT_4X4_50)); - vector detectedCharucoIds, detectedArucoIds; - vector detectedCharucoCorners; - vector> detectedArucoCorners; Mat boardImage; board.generateImage(boardSize*40, boardImage); swap(boardSize.width, boardSize.height); aruco::CharucoDetector detector(aruco::CharucoBoard(boardSize, 1.f, 0.5f, aruco::getPredefinedDictionary(aruco::DICT_4X4_50))); // try detect board with wrong size - detector.detectBoard(boardImage, detectedCharucoCorners, detectedCharucoIds, detectedArucoCorners, detectedArucoIds); - - // aruco markers must be found - ASSERT_EQ(detectedArucoIds.size(), board.getIds().size()); - ASSERT_EQ(detectedArucoCorners.size(), board.getIds().size()); - // charuco corners should not be found in board with wrong size - ASSERT_TRUE(detectedCharucoCorners.empty()); - ASSERT_TRUE(detectedCharucoIds.empty()); + for(int i: {0, 1}) { + vector detectedCharucoIds, detectedArucoIds; + vector detectedCharucoCorners; + vector> detectedArucoCorners; + if (i == 0) { + detector.detectBoard(boardImage, detectedCharucoCorners, detectedCharucoIds, detectedArucoCorners, detectedArucoIds); + // aruco markers must be found + ASSERT_EQ(detectedArucoIds.size(), board.getIds().size()); + ASSERT_EQ(detectedArucoCorners.size(), board.getIds().size()); + } else { + detector.detectBoard(boardImage, detectedCharucoCorners, detectedCharucoIds); + } + + // charuco corners should not be found in board with wrong size + ASSERT_TRUE(detectedCharucoCorners.empty()); + ASSERT_TRUE(detectedCharucoIds.empty()); + } } From 160879c100baca7caedc44786cc17de52c2a472d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=AD=A6=E5=A3=AB=E9=A3=8E=E5=BA=A6=E7=9A=84=E7=89=9B?= <1085968073@qq.com> Date: Wed, 24 Jul 2024 20:29:13 +0800 Subject: [PATCH 18/18] Merge pull request #25807 from spdfghi:4.x Search in two directions when try to add new quad in addOuterQuad #25807 In ChessBoardDetector::addOuterQuad, previous code try to connect new quad with inner quad, if possible, but only search for one direction. I have made three test images, one is normal(a.jpg), one lossed an outer quad(b.jpg), and then i flipped it vertically(c.jpg). Only last one fails. I fixed it by check two directions and row/col. Here is the test code and images: ``` Mat img; vector corners; auto size = cv::Size(6, 6); img = imread("D:/tmp/a.jpg", 0); std::cout<ordered && - quad_prev->neighbors[i] && - quad_prev->neighbors[i]->ordered ) + for (int k = 1; k <= 3; k += 2) { - ChessBoardQuad* qn = quad_prev->neighbors[i]; - q.count = 2; - q.neighbors[prev_i] = qn; - qn->neighbors[next_i] = &q; - qn->count += 1; - // have to set exact corner - q.corners[prev_i] = qn->corners[next_i]; + int next_i = (i + k) % 4; + int prev_i = (i + k + 2) % 4; + ChessBoardQuad* quad_prev = quad.neighbors[prev_i]; + if (quad_prev && + quad_prev->ordered && + quad_prev->neighbors[i] && + quad_prev->neighbors[i]->ordered && + std::abs(quad_prev->neighbors[i]->col - q.col) == 1 && + std::abs(quad_prev->neighbors[i]->row - q.row) == 1) + { + ChessBoardQuad* qn = quad_prev->neighbors[i]; + q.count = 2; + q.neighbors[prev_i] = qn; + qn->neighbors[next_i] = &q; + qn->count += 1; + // have to set exact corner + q.corners[prev_i] = qn->corners[next_i]; + } } } }