Merge pull request #19778 from damonyu1989:master-riscv-0.7.1

* Add the support for riscv64 vector 0.7.1.

* fixed GCC warnings

* cleaned whitespaces

* Remove the worning by the use of internal API of compiler.

* Update the license header.

* removed trailing whitespaces

Co-authored-by: Vadim Pisarevsky <vadim.pisarevsky@me.com>
Co-authored-by: yulj <linjie.ylj@alibaba-inc.com>
Co-authored-by: Vadim Pisarevsky <vadim.pisarevsky@gmail.com>

modules/core/include/opencv2/core/cv_cpu_dispatch.h

@@ -142,6 +142,11 @@
 #  define CV_NEON 1
 #endif
 
+#if defined(__riscv) && defined(__riscv_vector)
+# include<riscv-vector.h>
+# define CV_RVV071 1
+#endif
+
 #if defined(__ARM_NEON__) || defined(__aarch64__)
 #  include <arm_neon.h>
 #endif
@@ -338,6 +343,10 @@ struct VZeroUpperGuard {
 #  define CV_NEON 0
 #endif
 
+#ifndef CV_RVV071
+#  define CV_RVV071 0
+#endif
+
 #ifndef CV_VSX
 #  define CV_VSX 0
 #endif

modules/core/include/opencv2/core/cvdef.h

@@ -271,6 +271,8 @@ namespace cv {
 
 #define CV_CPU_MSA              150
 
+#define CV_CPU_RISCVV           170
+
 #define CV_CPU_VSX              200
 #define CV_CPU_VSX3             201
 
@@ -325,6 +327,8 @@ enum CpuFeatures {
 
     CPU_MSA             = 150,
 
+    CPU_RISCVV          = 170,
+
     CPU_VSX             = 200,
     CPU_VSX3            = 201,
 

modules/core/include/opencv2/core/hal/intrin.hpp

@@ -200,7 +200,7 @@ using namespace CV_CPU_OPTIMIZATION_HAL_NAMESPACE;
 #   undef CV_RVV
 #endif
 
-#if (CV_SSE2 || CV_NEON || CV_VSX || CV_MSA || CV_WASM_SIMD || CV_RVV) && !defined(CV_FORCE_SIMD128_CPP)
+#if (CV_SSE2 || CV_NEON || CV_VSX || CV_MSA || CV_WASM_SIMD || CV_RVV071 || CV_RVV) && !defined(CV_FORCE_SIMD128_CPP)
 #define CV__SIMD_FORWARD 128
 #include "opencv2/core/hal/intrin_forward.hpp"
 #endif
@@ -214,6 +214,10 @@ using namespace CV_CPU_OPTIMIZATION_HAL_NAMESPACE;
 
 #include "opencv2/core/hal/intrin_neon.hpp"
 
+#elif CV_RVV071 && !defined(CV_FORCE_SIMD128_CPP)
+#define CV_SIMD128_CPP 0
+#include "opencv2/core/hal/intrin_rvv071.hpp"
+
 #elif CV_VSX && !defined(CV_FORCE_SIMD128_CPP)
 
 #include "opencv2/core/hal/intrin_vsx.hpp"

modules/core/src/arithm.simd.hpp

@@ -1910,4 +1910,4 @@ DEFINE_SIMD_ALL(recip, recip_loop)
     #define SIMD_GUARD
 #endif
 
-}} // cv::hal::
+}} // cv::hal::

modules/core/src/system.cpp

@@ -395,6 +395,7 @@ struct HWFeatures
         g_hwFeatureNames[CPU_VSX3] = "VSX3";
 
         g_hwFeatureNames[CPU_MSA] = "CPU_MSA";
+        g_hwFeatureNames[CPU_RISCVV] = "RISCVV";
 
         g_hwFeatureNames[CPU_AVX512_COMMON] = "AVX512-COMMON";
         g_hwFeatureNames[CPU_AVX512_SKX] = "AVX512-SKX";
@@ -590,6 +591,9 @@ struct HWFeatures
     #if defined _ARM_ && (defined(_WIN32_WCE) && _WIN32_WCE >= 0x800)
         have[CV_CPU_NEON] = true;
     #endif
+    #ifdef __riscv_vector
+        have[CV_CPU_RISCVV] = true;
+    #endif
     #ifdef __mips_msa
         have[CV_CPU_MSA] = true;
     #endif

platforms/linux/riscv64-071-gcc.toolchain.cmake

@@ -0,0 +1,9 @@
+set(CMAKE_SYSTEM_NAME "Linux")
+set(CMAKE_C_COMPILER  riscv64-unknown-linux-gnu-gcc)
+set(CMAKE_CXX_COMPILER riscv64-unknown-linux-gnu-g++)
+
+set(CMAKE_CXX_FLAGS ""    CACHE STRING "")
+set(CMAKE_C_FLAGS ""    CACHE STRING "")
+
+set(CMAKE_CXX_FLAGS "-static -march=rv64gcvxthead -mabi=lp64v -pthread")
+set(CMAKE_C_FLAGS "-static -march=rv64gcvxthead -mabi=lp64v -pthread")