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@ -83,7 +83,7 @@ MUL_SIMD(float, float) |
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#define ADDC_SIMD(SRC, DST) \ |
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#define ADDC_SIMD(SRC, DST) \ |
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int addc_simd(const SRC in[], const float scalar[], DST out[], \
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int addc_simd(const SRC in[], const float scalar[], DST out[], \
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const int width, const int chan); |
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const int length, const int chan); |
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ADDC_SIMD(uchar, uchar) |
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ADDC_SIMD(uchar, uchar) |
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ADDC_SIMD(ushort, uchar) |
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ADDC_SIMD(ushort, uchar) |
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@ -104,6 +104,29 @@ ADDC_SIMD(float, float) |
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#undef ADDC_SIMD |
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#undef ADDC_SIMD |
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#define SUBC_SIMD(SRC, DST) \ |
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int subc_simd(const SRC in[], const float scalar[], DST out[], \
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const int length, const int chan); |
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SUBC_SIMD(uchar, uchar) |
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SUBC_SIMD(ushort, uchar) |
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SUBC_SIMD(short, uchar) |
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SUBC_SIMD(float, uchar) |
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SUBC_SIMD(short, short) |
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SUBC_SIMD(ushort, short) |
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SUBC_SIMD(uchar, short) |
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SUBC_SIMD(float, short) |
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SUBC_SIMD(ushort, ushort) |
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SUBC_SIMD(uchar, ushort) |
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SUBC_SIMD(short, ushort) |
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SUBC_SIMD(float, ushort) |
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SUBC_SIMD(uchar, float) |
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SUBC_SIMD(ushort, float) |
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SUBC_SIMD(short, float) |
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SUBC_SIMD(float, float) |
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#undef SUBC_SIMD |
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#ifndef CV_CPU_OPTIMIZATION_DECLARATIONS_ONLY |
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#ifndef CV_CPU_OPTIMIZATION_DECLARATIONS_ONLY |
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struct scale_tag {}; |
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struct scale_tag {}; |
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@ -851,10 +874,13 @@ MUL_SIMD(float, float) |
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//
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//
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//-------------------------
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//-------------------------
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CV_ALWAYS_INLINE void addc_pack_store_c3(short* outx, const v_int32& c1, |
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struct add_tag {}; |
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const v_int32& c2, const v_int32& c3, |
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struct sub_tag {}; |
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const v_int32& c4, const v_int32& c5, |
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const v_int32& c6) |
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CV_ALWAYS_INLINE void arithmOpScalar_pack_store_c3(short* outx, const v_int32& c1, |
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const v_int32& c2, const v_int32& c3, |
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const v_int32& c4, const v_int32& c5, |
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const v_int32& c6) |
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{ |
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{ |
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constexpr int nlanes = v_int16::nlanes; |
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constexpr int nlanes = v_int16::nlanes; |
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vx_store(outx, v_pack(c1, c2)); |
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vx_store(outx, v_pack(c1, c2)); |
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@ -862,10 +888,10 @@ CV_ALWAYS_INLINE void addc_pack_store_c3(short* outx, const v_int32& c1, |
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vx_store(&outx[2*nlanes], v_pack(c5, c6)); |
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vx_store(&outx[2*nlanes], v_pack(c5, c6)); |
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} |
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} |
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CV_ALWAYS_INLINE void addc_pack_store_c3(ushort* outx, const v_int32& c1, |
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CV_ALWAYS_INLINE void arithmOpScalar_pack_store_c3(ushort* outx, const v_int32& c1, |
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const v_int32& c2, const v_int32& c3, |
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const v_int32& c2, const v_int32& c3, |
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const v_int32& c4, const v_int32& c5, |
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const v_int32& c4, const v_int32& c5, |
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const v_int32& c6) |
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const v_int32& c6) |
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{ |
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{ |
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constexpr int nlanes = v_uint16::nlanes; |
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constexpr int nlanes = v_uint16::nlanes; |
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vx_store(outx, v_pack_u(c1, c2)); |
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vx_store(outx, v_pack_u(c1, c2)); |
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@ -873,50 +899,64 @@ CV_ALWAYS_INLINE void addc_pack_store_c3(ushort* outx, const v_int32& c1, |
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vx_store(&outx[2*nlanes], v_pack_u(c5, c6)); |
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vx_store(&outx[2*nlanes], v_pack_u(c5, c6)); |
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} |
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} |
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template<typename SRC, typename DST> |
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CV_ALWAYS_INLINE v_float32 oper(add_tag, const v_float32& a, const v_float32& sc) |
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{ |
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return a + sc; |
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} |
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CV_ALWAYS_INLINE v_float32 oper(sub_tag, const v_float32& a, const v_float32& sc) |
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{ |
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return a - sc; |
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} |
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template<typename oper_tag, typename SRC, typename DST> |
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CV_ALWAYS_INLINE |
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CV_ALWAYS_INLINE |
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typename std::enable_if<(std::is_same<DST, ushort>::value || |
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typename std::enable_if<(std::is_same<DST, ushort>::value || |
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std::is_same<DST, short>::value), void>::type |
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std::is_same<DST, short>::value), void>::type |
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addc_simd_common_impl(const SRC* inx, DST* outx, const v_float32& sc, const int nlanes) |
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arithmOpScalar_simd_common_impl(oper_tag t, const SRC* inx, DST* outx, |
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const v_float32& sc, const int nlanes) |
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{ |
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{ |
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v_float32 a1 = vg_load_f32(inx); |
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v_float32 a1 = vg_load_f32(inx); |
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v_float32 a2 = vg_load_f32(&inx[nlanes/2]); |
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v_float32 a2 = vg_load_f32(&inx[nlanes/2]); |
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v_store_i16(outx, v_round(a1 + sc), v_round(a2 + sc)); |
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v_store_i16(outx, v_round(oper(t, a1, sc)), v_round(oper(t, a2, sc))); |
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} |
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} |
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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template<typename SRC> |
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template<typename oper_tag, typename SRC> |
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CV_ALWAYS_INLINE void addc_simd_common_impl(const SRC* inx, uchar* outx, const v_float32& sc, const int nlanes) |
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CV_ALWAYS_INLINE void arithmOpScalar_simd_common_impl(oper_tag t, const SRC* inx, |
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uchar* outx, const v_float32& sc, |
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const int nlanes) |
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{ |
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{ |
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v_float32 a1 = vg_load_f32(inx); |
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v_float32 a1 = vg_load_f32(inx); |
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v_float32 a2 = vg_load_f32(&inx[nlanes/4]); |
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v_float32 a2 = vg_load_f32(&inx[nlanes/4]); |
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v_float32 a3 = vg_load_f32(&inx[nlanes/2]); |
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v_float32 a3 = vg_load_f32(&inx[nlanes/2]); |
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v_float32 a4 = vg_load_f32(&inx[3 * nlanes/4]); |
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v_float32 a4 = vg_load_f32(&inx[3 * nlanes/4]); |
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vx_store(outx, v_pack_u(v_pack(v_round(a1 + sc), |
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vx_store(outx, v_pack_u(v_pack(v_round(oper(t, a1, sc)), |
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v_round(a2 + sc)), |
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v_round(oper(t, a2, sc))), |
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v_pack(v_round(a3 + sc), |
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v_pack(v_round(oper(t, a3, sc)), |
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v_round(a4 + sc)))); |
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v_round(oper(t, a4, sc))))); |
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} |
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} |
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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template<typename SRC> |
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template<typename oper_tag, typename SRC> |
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CV_ALWAYS_INLINE void addc_simd_common_impl(const SRC* inx, float* outx, const v_float32& sc, const int) |
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CV_ALWAYS_INLINE void arithmOpScalar_simd_common_impl(oper_tag t, const SRC* inx, |
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float* outx, const v_float32& sc, const int) |
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{ |
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{ |
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v_float32 a1 = vg_load_f32(inx); |
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v_float32 a1 = vg_load_f32(inx); |
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vx_store(outx, a1 + sc); |
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vx_store(outx, oper(t, a1, sc)); |
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} |
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} |
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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template<typename SRC, typename DST> |
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template<typename oper_tag, typename SRC, typename DST> |
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CV_ALWAYS_INLINE |
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CV_ALWAYS_INLINE |
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typename std::enable_if<std::is_same<DST, short>::value || |
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typename std::enable_if<std::is_same<DST, short>::value || |
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std::is_same<DST, ushort>::value, void>::type |
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std::is_same<DST, ushort>::value, void>::type |
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addc_simd_c3_impl(const SRC* inx, DST* outx, const v_float32& s1, const v_float32& s2, |
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arithmOpScalar_simd_c3_impl(oper_tag t, const SRC* inx, DST* outx, const v_float32& s1, const v_float32& s2, |
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const v_float32& s3, const int nlanes) |
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const v_float32& s3, const int nlanes) |
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{ |
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{ |
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v_float32 a1 = vg_load_f32(inx); |
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v_float32 a1 = vg_load_f32(inx); |
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@ -926,60 +966,62 @@ addc_simd_c3_impl(const SRC* inx, DST* outx, const v_float32& s1, const v_float3 |
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v_float32 a5 = vg_load_f32(&inx[2 * nlanes]); |
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v_float32 a5 = vg_load_f32(&inx[2 * nlanes]); |
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v_float32 a6 = vg_load_f32(&inx[5 * nlanes / 2]); |
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v_float32 a6 = vg_load_f32(&inx[5 * nlanes / 2]); |
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addc_pack_store_c3(outx, v_round(a1 + s1), |
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arithmOpScalar_pack_store_c3(outx, v_round(oper(t, a1, s1)), |
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v_round(a2 + s2), |
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v_round(oper(t, a2, s2)), |
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v_round(a3 + s3), |
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v_round(oper(t, a3, s3)), |
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v_round(a4 + s1), |
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v_round(oper(t, a4, s1)), |
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v_round(a5 + s2), |
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v_round(oper(t, a5, s2)), |
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v_round(a6 + s3)); |
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v_round(oper(t, a6, s3))); |
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} |
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} |
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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template<typename SRC> |
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template<typename oper_tag, typename SRC> |
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CV_ALWAYS_INLINE void addc_simd_c3_impl(const SRC* inx, uchar* outx, |
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CV_ALWAYS_INLINE void arithmOpScalar_simd_c3_impl(oper_tag t, const SRC* inx, uchar* outx, |
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const v_float32& s1, const v_float32& s2, |
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const v_float32& s1, const v_float32& s2, |
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const v_float32& s3, const int nlanes) |
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const v_float32& s3, const int nlanes) |
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{ |
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{ |
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vx_store(outx, |
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vx_store(outx, |
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v_pack_u(v_pack(v_round(vg_load_f32(inx) + s1), |
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v_pack_u(v_pack(v_round(oper(t, vg_load_f32(inx), s1)), |
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v_round(vg_load_f32(&inx[nlanes/4]) + s2)), |
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v_round(oper(t, vg_load_f32(&inx[nlanes/4]), s2))), |
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v_pack(v_round(vg_load_f32(&inx[nlanes/2]) + s3), |
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v_pack(v_round(oper(t, vg_load_f32(&inx[nlanes/2]), s3)), |
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v_round(vg_load_f32(&inx[3*nlanes/4]) + s1)))); |
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v_round(oper(t, vg_load_f32(&inx[3*nlanes/4]), s1))))); |
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vx_store(&outx[nlanes], |
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vx_store(&outx[nlanes], |
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v_pack_u(v_pack(v_round(vg_load_f32(&inx[nlanes]) + s2), |
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v_pack_u(v_pack(v_round(oper(t, vg_load_f32(&inx[nlanes]), s2)), |
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v_round(vg_load_f32(&inx[5*nlanes/4]) + s3)), |
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v_round(oper(t, vg_load_f32(&inx[5*nlanes/4]), s3))), |
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v_pack(v_round(vg_load_f32(&inx[3*nlanes/2]) + s1), |
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v_pack(v_round(oper(t, vg_load_f32(&inx[3*nlanes/2]), s1)), |
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v_round(vg_load_f32(&inx[7*nlanes/4]) + s2)))); |
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v_round(oper(t, vg_load_f32(&inx[7*nlanes/4]), s2))))); |
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vx_store(&outx[2 * nlanes], |
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vx_store(&outx[2 * nlanes], |
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v_pack_u(v_pack(v_round(vg_load_f32(&inx[2*nlanes]) + s3), |
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v_pack_u(v_pack(v_round(oper(t, vg_load_f32(&inx[2*nlanes]), s3)), |
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v_round(vg_load_f32(&inx[9*nlanes/4]) + s1)), |
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v_round(oper(t, vg_load_f32(&inx[9*nlanes/4]), s1))), |
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v_pack(v_round(vg_load_f32(&inx[5*nlanes/2]) + s2), |
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v_pack(v_round(oper(t, vg_load_f32(&inx[5*nlanes/2]), s2)), |
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v_round(vg_load_f32(&inx[11*nlanes/4]) + s3)))); |
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v_round(oper(t, vg_load_f32(&inx[11*nlanes/4]), s3))))); |
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} |
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} |
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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template<typename SRC> |
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template<typename oper_tag, typename SRC> |
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CV_ALWAYS_INLINE void addc_simd_c3_impl(const SRC* in, float* out, |
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CV_ALWAYS_INLINE void arithmOpScalar_simd_c3_impl(oper_tag t, const SRC* in, float* out, |
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const v_float32& s1, const v_float32& s2, |
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const v_float32& s1, const v_float32& s2, |
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const v_float32& s3, const int nlanes) |
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const v_float32& s3, const int nlanes) |
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{ |
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{ |
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v_float32 a1 = vg_load_f32(in); |
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v_float32 a1 = vg_load_f32(in); |
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v_float32 a2 = vg_load_f32(&in[nlanes]); |
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v_float32 a2 = vg_load_f32(&in[nlanes]); |
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v_float32 a3 = vg_load_f32(&in[2*nlanes]); |
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v_float32 a3 = vg_load_f32(&in[2*nlanes]); |
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vx_store(out, a1 + s1); |
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vx_store(out, oper(t, a1, s1)); |
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vx_store(&out[nlanes], a2 + s2); |
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vx_store(&out[nlanes], oper(t, a2, s2)); |
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vx_store(&out[2*nlanes], a3 + s3); |
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vx_store(&out[2*nlanes], oper(t, a3, s3)); |
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} |
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} |
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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template<typename SRC, typename DST> |
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template<typename oper_tag, typename SRC, typename DST> |
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CV_ALWAYS_INLINE int addc_simd_c3(const SRC in[], const float scalar[], DST out[], const int length) |
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CV_ALWAYS_INLINE int arithmOpScalar_simd_c3(oper_tag t, const SRC in[], |
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const float scalar[], DST out[], |
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const int length) |
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{ |
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{ |
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constexpr int chan = 3; |
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constexpr int chan = 3; |
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constexpr int nlanes = vector_type_of_t<DST>::nlanes; |
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constexpr int nlanes = vector_type_of_t<DST>::nlanes; |
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@ -1002,7 +1044,7 @@ CV_ALWAYS_INLINE int addc_simd_c3(const SRC in[], const float scalar[], DST out[ |
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{ |
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{ |
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for (; x <= length - lanes; x += lanes) |
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for (; x <= length - lanes; x += lanes) |
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{ |
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{ |
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addc_simd_c3_impl(&in[x], &out[x], s1, s2, s3, nlanes); |
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arithmOpScalar_simd_c3_impl(t, &in[x], &out[x], s1, s2, s3, nlanes); |
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} |
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} |
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if (x < length) |
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if (x < length) |
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@ -1015,8 +1057,12 @@ CV_ALWAYS_INLINE int addc_simd_c3(const SRC in[], const float scalar[], DST out[ |
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return x; |
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return x; |
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} |
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} |
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template<typename SRC, typename DST> |
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//-------------------------------------------------------------------------------------------------
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CV_ALWAYS_INLINE int addc_simd_common(const SRC in[], const float scalar[], DST out[], const int length) |
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template<typename oper_tag, typename SRC, typename DST> |
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CV_ALWAYS_INLINE int arithmOpScalar_simd_common(oper_tag t, const SRC in[], |
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const float scalar[], DST out[], |
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const int length) |
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{ |
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{ |
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constexpr int nlanes = vector_type_of_t<DST>::nlanes; |
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constexpr int nlanes = vector_type_of_t<DST>::nlanes; |
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@ -1030,7 +1076,7 @@ CV_ALWAYS_INLINE int addc_simd_common(const SRC in[], const float scalar[], DST |
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{ |
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{ |
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for (; x <= length - nlanes; x += nlanes) |
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for (; x <= length - nlanes; x += nlanes) |
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{ |
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{ |
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addc_simd_common_impl(&in[x], &out[x], sc, nlanes); |
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arithmOpScalar_simd_common_impl(t, &in[x], &out[x], sc, nlanes); |
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} |
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} |
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if (x < length) |
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if (x < length) |
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@ -1043,24 +1089,25 @@ CV_ALWAYS_INLINE int addc_simd_common(const SRC in[], const float scalar[], DST |
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return x; |
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return x; |
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} |
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} |
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#define ADDC_SIMD(SRC, DST) \ |
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int addc_simd(const SRC in[], const float scalar[], DST out[], \
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const int width, const int chan) \
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#define ADDC_SIMD(SRC, DST) \ |
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{ \
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int addc_simd(const SRC in[], const float scalar[], DST out[], \
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const int length = width * chan; \
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const int length, const int chan) \
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switch (chan) \
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{ \
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{ \
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switch (chan) \
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case 1: \
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{ \
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case 2: \
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case 1: \
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case 4: \
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case 2: \
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return addc_simd_common(in, scalar, out, length); \
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case 4: \
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case 3: \
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return arithmOpScalar_simd_common(add_tag{}, in, scalar, out, length); \
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return addc_simd_c3(in, scalar, out, length); \
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case 3: \
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default: \
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return arithmOpScalar_simd_c3(add_tag{}, in, scalar, out, length); \
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GAPI_Assert(chan <= 4); \
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default: \
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break; \
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GAPI_Assert(chan <= 4); \
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} \
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break; \
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return 0; \
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} \
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return 0; \
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} |
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} |
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ADDC_SIMD(uchar, uchar) |
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ADDC_SIMD(uchar, uchar) |
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@ -1082,6 +1129,44 @@ ADDC_SIMD(float, float) |
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#undef ADDC_SIMD |
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#undef ADDC_SIMD |
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#define SUBC_SIMD(SRC, DST) \ |
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int subc_simd(const SRC in[], const float scalar[], DST out[], \
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const int length, const int chan) \
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{ \
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switch (chan) \
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{ \
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case 1: \
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case 2: \
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case 4: \
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return arithmOpScalar_simd_common(sub_tag{}, in, scalar, out, length); \
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case 3: \
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return arithmOpScalar_simd_c3(sub_tag{}, in, scalar, out, length); \
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default: \
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GAPI_Assert(chan <= 4); \
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break; \
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} \
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return 0; \
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} |
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SUBC_SIMD(uchar, uchar) |
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SUBC_SIMD(ushort, uchar) |
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SUBC_SIMD(short, uchar) |
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SUBC_SIMD(float, uchar) |
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SUBC_SIMD(short, short) |
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SUBC_SIMD(ushort, short) |
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SUBC_SIMD(uchar, short) |
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SUBC_SIMD(float, short) |
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SUBC_SIMD(ushort, ushort) |
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SUBC_SIMD(uchar, ushort) |
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SUBC_SIMD(short, ushort) |
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SUBC_SIMD(float, ushort) |
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SUBC_SIMD(uchar, float) |
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SUBC_SIMD(ushort, float) |
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SUBC_SIMD(short, float) |
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SUBC_SIMD(float, float) |
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#undef SUBC_SIMD |
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#endif // CV_CPU_OPTIMIZATION_DECLARATIONS_ONLY
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#endif // CV_CPU_OPTIMIZATION_DECLARATIONS_ONLY
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CV_CPU_OPTIMIZATION_NAMESPACE_END |
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CV_CPU_OPTIMIZATION_NAMESPACE_END |
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