mirror of https://github.com/opencv/opencv.git
Merge pull request #8838 from tomoaki0705:dispatchFp16
Alexander Alekhin
8 years ago
commit
125abe2fe4
4 changed files with 371 additions and 238 deletions
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/*M///////////////////////////////////////////////////////////////////////////////////////
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//
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// IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING.
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//
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// By downloading, copying, installing or using the software you agree to this license.
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// If you do not agree to this license, do not download, install,
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// copy or use the software.
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//
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//
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// License Agreement
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// For Open Source Computer Vision Library
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//
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// Copyright (C) 2000-2008, Intel Corporation, all rights reserved.
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// Copyright (C) 2009-2011, Willow Garage Inc., all rights reserved.
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// Copyright (C) 2014-2015, Itseez Inc., all rights reserved.
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// Third party copyrights are property of their respective owners.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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//
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// * Redistribution's of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// * Redistribution's in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// * The name of the copyright holders may not be used to endorse or promote products
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// derived from this software without specific prior written permission.
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//
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// This software is provided by the copyright holders and contributors "as is" and
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// any express or implied warranties, including, but not limited to, the implied
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// warranties of merchantability and fitness for a particular purpose are disclaimed.
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// In no event shall the Intel Corporation or contributors be liable for any direct,
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// indirect, incidental, special, exemplary, or consequential damages
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// (including, but not limited to, procurement of substitute goods or services;
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// loss of use, data, or profits; or business interruption) however caused
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// and on any theory of liability, whether in contract, strict liability,
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// or tort (including negligence or otherwise) arising in any way out of
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// the use of this software, even if advised of the possibility of such damage.
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//
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//M*/
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#include "precomp.hpp" |
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#include "convert.hpp" |
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namespace cv |
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{ |
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namespace opt_FP16 |
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{ |
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#if !defined(CV_NEON) || !CV_NEON |
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const static int cVectorWidth = 8; |
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void cvtScaleHalf_SIMD32f16f( const float* src, size_t sstep, short* dst, size_t dstep, cv::Size size ) |
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{ |
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CV_INSTRUMENT_REGION() |
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sstep /= sizeof(src[0]); |
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dstep /= sizeof(dst[0]); |
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for( ; size.height--; src += sstep, dst += dstep ) |
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{ |
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int x = 0; |
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for ( ; x <= size.width - cVectorWidth ; x += cVectorWidth ) |
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{ |
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__m256 v_src = _mm256_loadu_ps(src + x); |
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// round to nearest even
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__m128i v_dst = _mm256_cvtps_ph(v_src, 0); |
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_mm_storeu_si128((__m128i*)(dst + x), v_dst); |
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} |
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for ( ; x < size.width; x++ ) |
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{ |
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dst[x] = convertFp16SW(src[x]); |
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} |
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} |
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} |
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void cvtScaleHalf_SIMD16f32f( const short* src, size_t sstep, float* dst, size_t dstep, cv::Size size ) |
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{ |
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CV_INSTRUMENT_REGION() |
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sstep /= sizeof(src[0]); |
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dstep /= sizeof(dst[0]); |
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for( ; size.height--; src += sstep, dst += dstep ) |
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{ |
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int x = 0; |
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for ( ; x <= size.width - cVectorWidth ; x += cVectorWidth ) |
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{ |
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__m128i v_src = _mm_loadu_si128((__m128i*)(src + x)); |
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__m256 v_dst = _mm256_cvtph_ps(v_src); |
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_mm256_storeu_ps(dst + x, v_dst); |
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} |
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for ( ; x < size.width; x++ ) |
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{ |
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dst[x] = convertFp16SW(src[x]); |
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} |
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} |
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} |
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#elif CV_NEON |
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const static int cVectorWidth = 4; |
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template <typename T> static inline float16x4_t vld1_f16(const T* ptr) |
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{ return (float16x4_t)vld1_s16((const short*)ptr); } |
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template <typename T> static inline void vst1_f16(T* ptr, float16x4_t a) |
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{ vst1_s16((short*)ptr, a); } |
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void cvtScaleHalf_SIMD32f16f( const float* src, size_t sstep, short* dst, size_t dstep, cv::Size size ) |
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{ |
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CV_INSTRUMENT_REGION() |
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sstep /= sizeof(src[0]); |
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dstep /= sizeof(dst[0]); |
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for( ; size.height--; src += sstep, dst += dstep ) |
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{ |
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int x = 0; |
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for ( ; x <= size.width - cVectorWidth ; x += cVectorWidth) |
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{ |
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float32x4_t v_src = vld1q_f32(src + x); |
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float16x4_t v_dst = vcvt_f16_f32(v_src); |
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vst1_f16((__fp16*)dst + x, v_dst); |
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} |
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for ( ; x < size.width; x++ ) |
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{ |
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dst[x] = convertFp16SW(src[x]); |
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} |
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} |
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} |
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void cvtScaleHalf_SIMD16f32f( const short* src, size_t sstep, float* dst, size_t dstep, cv::Size size ) |
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{ |
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CV_INSTRUMENT_REGION() |
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sstep /= sizeof(src[0]); |
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dstep /= sizeof(dst[0]); |
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for( ; size.height--; src += sstep, dst += dstep ) |
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{ |
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int x = 0; |
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for ( ; x <= size.width - cVectorWidth ; x += cVectorWidth ) |
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{ |
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float16x4_t v_src = vld1_f16((__fp16*)src + x); |
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float32x4_t v_dst = vcvt_f32_f16(v_src); |
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vst1q_f32(dst + x, v_dst); |
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} |
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for ( ; x < size.width; x++ ) |
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{ |
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dst[x] = convertFp16SW(src[x]); |
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} |
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} |
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} |
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#else |
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#error "Unsupported build configuration" |
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#endif |
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} |
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} |
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/* End of file. */ |
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@ -0,0 +1,173 @@ |
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namespace |
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{ |
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float convertFp16SW(short fp16); |
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short convertFp16SW(float fp32); |
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#if !CV_FP16_TYPE |
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// const numbers for floating points format
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const unsigned int kShiftSignificand = 13; |
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const unsigned int kMaskFp16Significand = 0x3ff; |
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const unsigned int kBiasFp16Exponent = 15; |
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const unsigned int kBiasFp32Exponent = 127; |
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#endif |
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#if CV_FP16_TYPE |
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float convertFp16SW(short fp16) |
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{ |
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// Fp16 -> Fp32
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Cv16suf a; |
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a.i = fp16; |
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return (float)a.h; |
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} |
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#else |
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float convertFp16SW(short fp16) |
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{ |
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// Fp16 -> Fp32
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Cv16suf b; |
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b.i = fp16; |
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int exponent = b.fmt.exponent - kBiasFp16Exponent; |
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int significand = b.fmt.significand; |
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Cv32suf a; |
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a.i = 0; |
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a.fmt.sign = b.fmt.sign; // sign bit
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if( exponent == 16 ) |
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{ |
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// Inf or NaN
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a.i = a.i | 0x7F800000; |
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if( significand != 0 ) |
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{ |
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// NaN
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#if defined(__x86_64__) || defined(_M_X64) |
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// 64bit
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a.i = a.i | 0x7FC00000; |
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#endif |
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a.fmt.significand = a.fmt.significand | (significand << kShiftSignificand); |
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} |
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return a.f; |
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} |
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else if ( exponent == -(int)kBiasFp16Exponent ) |
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{ |
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// subnormal in Fp16
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if( significand == 0 ) |
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{ |
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// zero
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return a.f; |
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} |
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else |
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{ |
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int shift = -1; |
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while( ( significand & 0x400 ) == 0 ) |
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{ |
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significand = significand << 1; |
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shift++; |
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} |
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significand = significand & kMaskFp16Significand; |
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exponent -= shift; |
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} |
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} |
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a.fmt.exponent = (exponent+kBiasFp32Exponent); |
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a.fmt.significand = significand << kShiftSignificand; |
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return a.f; |
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} |
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#endif |
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#if CV_FP16_TYPE |
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short convertFp16SW(float fp32) |
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{ |
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// Fp32 -> Fp16
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Cv16suf a; |
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a.h = (__fp16)fp32; |
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return a.i; |
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} |
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#else |
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short convertFp16SW(float fp32) |
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{ |
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// Fp32 -> Fp16
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Cv32suf a; |
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a.f = fp32; |
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int exponent = a.fmt.exponent - kBiasFp32Exponent; |
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int significand = a.fmt.significand; |
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Cv16suf result; |
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result.i = 0; |
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unsigned int absolute = a.i & 0x7fffffff; |
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if( 0x477ff000 <= absolute ) |
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{ |
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// Inf in Fp16
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result.i = result.i | 0x7C00; |
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if( exponent == 128 && significand != 0 ) |
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{ |
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// NaN
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result.i = (short)( result.i | 0x200 | ( significand >> kShiftSignificand ) ); |
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} |
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} |
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else if ( absolute < 0x33000001 ) |
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{ |
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// too small for fp16
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result.i = 0; |
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} |
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else if ( absolute < 0x387fe000 ) |
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{ |
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// subnormal in Fp16
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int fp16Significand = significand | 0x800000; |
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int bitShift = (-exponent) - 1; |
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fp16Significand = fp16Significand >> bitShift; |
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// special cases to round up
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bitShift = exponent + 24; |
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int threshold = ( ( 0x400000 >> bitShift ) | ( ( ( significand & ( 0x800000 >> bitShift ) ) >> ( 126 - a.fmt.exponent ) ) ^ 1 ) ); |
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if( absolute == 0x33c00000 ) |
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{ |
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result.i = 2; |
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} |
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else |
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{ |
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if( threshold <= ( significand & ( 0xffffff >> ( exponent + 25 ) ) ) ) |
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{ |
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fp16Significand++; |
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} |
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result.i = (short)fp16Significand; |
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} |
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} |
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else |
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{ |
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// usual situation
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// exponent
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result.fmt.exponent = ( exponent + kBiasFp16Exponent ); |
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// significand;
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short fp16Significand = (short)(significand >> kShiftSignificand); |
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result.fmt.significand = fp16Significand; |
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// special cases to round up
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short lsb10bitsFp32 = (significand & 0x1fff); |
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short threshold = 0x1000 + ( ( fp16Significand & 0x1 ) ? 0 : 1 ); |
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if( threshold <= lsb10bitsFp32 ) |
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{ |
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result.i++; |
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} |
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else if ( fp16Significand == kMaskFp16Significand && exponent == -15) |
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{ |
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result.i++; |
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} |
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} |
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// sign bit
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result.fmt.sign = a.fmt.sign; |
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return result.i; |
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} |
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#endif |
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} |
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namespace cv |
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{ |
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namespace opt_FP16 |
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{ |
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void cvtScaleHalf_SIMD32f16f( const float* src, size_t sstep, short* dst, size_t dstep, cv::Size size ); |
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void cvtScaleHalf_SIMD16f32f( const short* src, size_t sstep, float* dst, size_t dstep, cv::Size size ); |
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} |
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} |
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