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// This file is part of OpenCV project.
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// It is subject to the license terms in the LICENSE file found in the top-level directory
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// of this distribution and at http://opencv.org/license.html.
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#include "perf_precomp.hpp"
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#include <opencv2/dnn/shape_utils.hpp>
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namespace opencv_test {
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struct Conv3DParam_t {
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int kernel[3];
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struct BlobShape { int dims[5]; } shapeIn;
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int outCN;
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int groups;
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int stride[3];
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int dilation[3];
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int pad[6];
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const char* padMode;
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bool hasBias;
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double declared_flops;
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};
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// Details: #12142
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static const Conv3DParam_t testConvolution3DConfigs[] = {
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{{3, 3, 3}, {{1, 6, 10, 38, 50}}, 6, 1, {1, 1, 1}, {1, 1, 1}, {0, 0, 0, 0, 0, 0}, "VALID", true, 26956800.},
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{{3, 3, 3}, {{1, 2, 19, 19, 19}}, 2, 2, {2, 2, 2}, {1, 1, 1}, {1, 1, 1, 1, 1, 1}, "", true, 218000.},
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{{3, 3, 3}, {{1, 2, 25, 19, 19}}, 2, 2, {1, 2, 2}, {1, 1, 1}, {2, 2, 2, 2, 2, 2}, "SAME", false, 545000.},
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{{3, 3, 3}, {{1, 11, 9, 150, 200}}, 11, 1, {1, 1, 1}, {1, 1, 1}, {0, 0, 0, 0, 0, 0}, "VALID", true, 1342562760.},
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{{3, 3, 3}, {{1, 10, 98, 10, 10}}, 10, 1, {1, 1, 1}, {1, 1, 1}, {1, 0, 1, 1, 0,1}, "SAME", false, 53018000.},
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{{5, 5, 5}, {{1, 6, 19, 19, 19}}, 6, 2, {1, 1, 1}, {1, 1, 1}, {0, 0, 0, 0, 0, 0}, "", false, 30395250.},
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{{5, 5, 5}, {{1, 4, 50, 19, 19}}, 4, 1, {2, 2, 2}, {1, 1, 1}, {1, 1, 1, 1, 1, 1}, "VALID", false, 5893888.},
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{{5, 5, 5}, {{1, 3, 75, 75, 100}}, 3, 1, {1, 1, 1}, {1, 1, 1}, {0, 0, 0, 0, 0, 0}, "SAME", true, 1267312500.},
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{{5, 5, 5}, {{1, 2, 21, 75, 100}}, 2, 1, {1, 1, 1}, {1, 1, 1}, {0, 0, 0, 0, 0, 0}, "", true, 116103744.},
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{{5, 5, 5}, {{1, 4, 40, 75, 75}}, 4, 1, {2, 2, 2}, {1, 1, 1}, {0, 0, 0, 0, 0, 0}, "", false, 93405312.},
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{{7, 7, 7}, {{1, 6, 15, 19, 19}}, 6, 1, {2, 1, 1}, {1, 1, 1}, {3, 3, 3, 3, 3, 3}, "SAME", true, 71339376.},
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{{7, 7, 7}, {{1, 2, 38, 38, 38}}, 2, 1, {1, 2, 1}, {1, 1, 1}, {0, 0, 0, 0, 0, 0}, "", false, 44990464.},
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{{1, 1, 1}, {{1, 4, 9, 10, 10}}, 4, 1, {1, 1, 2}, {1, 1, 1}, {1, 1, 1, 1, 1, 1}, "VALID", false, 16200.},
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{{3, 1, 4}, {{1, 14, 5, 10, 10}}, 14, 1, {1, 1, 1}, {1, 1, 1}, {0, 0, 0, 0, 0, 0}, "SAME", false, 2359000.},
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{{1, 1, 1}, {{1, 8, 1, 10, 10}}, 8, 8, {1, 1, 1}, {1, 1, 1}, {1, 1, 1, 1, 1, 1}, "", true, 58752.},
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{{3, 4, 2}, {{1, 4, 8, 10, 10}}, 4, 4, {1, 2, 1}, {1, 1, 1}, {0, 0, 0, 0, 0, 0}, "", true, 166752.}
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};
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struct Conv3DParamID
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{
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enum {
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CONV_0 = 0,
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CONV_100 = 16,
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CONV_LAST = sizeof(testConvolution3DConfigs) / sizeof(testConvolution3DConfigs[0])
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};
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int val_;
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Conv3DParamID(int val = 0) : val_(val) {}
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operator int() const { return val_; }
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static ::testing::internal::ParamGenerator<Conv3DParamID> all()
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{
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#if 0
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enum { NUM = (int)CONV_LAST };
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#else
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enum { NUM = (int)CONV_100 };
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#endif
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Conv3DParamID v_[NUM]; for (int i = 0; i < NUM; ++i) { v_[i] = Conv3DParamID(i); } // reduce generated code size
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return ::testing::ValuesIn(v_, v_ + NUM);
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}
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};
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static inline void PrintTo(const Conv3DParamID& v, std::ostream* os)
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{
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CV_Assert((int)v >= 0); CV_Assert((int)v < Conv3DParamID::CONV_LAST);
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const Conv3DParam_t& p = testConvolution3DConfigs[(int)v];
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*os << "GFLOPS=" << cv::format("%.3f", p.declared_flops * 1e-9)
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<< ", K=[" << p.kernel[0] << " x " << p.kernel[1] << " x " << p.kernel[2] << "]"
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<< ", IN={" << p.shapeIn.dims[0] << ", " << p.shapeIn.dims[1] << ", " << p.shapeIn.dims[2] << ", " << p.shapeIn.dims[3] << ", " << p.shapeIn.dims[4] << "}"
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<< ", OCN=" << p.outCN;
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if (p.groups > 1)
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*os << ", G=" << p.groups;
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if (p.stride[0] * p.stride[1] * p.stride[2] != 1)
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*os << ", S=[" << p.stride[0] << " x " << p.stride[1] << " x " << p.stride[2] << "]";
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if (p.dilation[0] * p.dilation[1] * p.dilation[2] != 1)
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*os << ", D=[" << p.dilation[0] << " x " << p.dilation[1] << " x " << p.dilation[2] << "]";
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if (p.pad[0] != 0 && p.pad[1] != 0 && p.pad[2] != 0 &&
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p.pad[3] != 0 && p.pad[4] != 0 && p.pad[5] != 0)
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*os << ", P=(" << p.pad[0] << ", " << p.pad[3] << ") x ("
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<< p.pad[1] << ", " << p.pad[4] << ") x ("
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<< p.pad[2] << ", " << p.pad[5] << ")";
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if (!((std::string)p.padMode).empty())
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*os << ", PM=" << ((std::string)p.padMode);
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if (p.hasBias)
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*os << ", BIAS";
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}
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typedef tuple<Conv3DParamID, tuple<Backend, Target> > Conv3DTestParam_t;
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typedef TestBaseWithParam<Conv3DTestParam_t> Conv3D;
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PERF_TEST_P_(Conv3D, conv3d)
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{
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int test_id = (int)get<0>(GetParam());
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ASSERT_GE(test_id, 0); ASSERT_LT(test_id, Conv3DParamID::CONV_LAST);
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const Conv3DParam_t& params = testConvolution3DConfigs[test_id];
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double declared_flops = params.declared_flops;
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DictValue kernel = DictValue::arrayInt(¶ms.kernel[0], 3);
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DictValue stride = DictValue::arrayInt(¶ms.stride[0], 3);
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DictValue pad = DictValue::arrayInt(¶ms.pad[0], 6);
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DictValue dilation = DictValue::arrayInt(¶ms.dilation[0], 3);
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MatShape inputShape = MatShape(params.shapeIn.dims, params.shapeIn.dims + 5);
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int outChannels = params.outCN;
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int groups = params.groups;
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std::string padMode(params.padMode);
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bool hasBias = params.hasBias;
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Backend backendId = get<0>(get<1>(GetParam()));
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Target targetId = get<1>(get<1>(GetParam()));
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Merge pull request #14827 from YashasSamaga:cuda4dnn-csl-low
CUDA backend for the DNN module
* stub cuda4dnn design
* minor fixes for tests and doxygen
* add csl public api directory to module headers
* add low-level CSL components
* add high-level CSL components
* integrate csl::Tensor into backbone code
* switch to CPU iff unsupported; otherwise, fail on error
* add fully connected layer
* add softmax layer
* add activation layers
* support arbitary rank TensorDescriptor
* pass input wrappers to `initCUDA()`
* add 1d/2d/3d-convolution
* add pooling layer
* reorganize and refactor code
* fixes for gcc, clang and doxygen; remove cxx14/17 code
* add blank_layer
* add LRN layer
* add rounding modes for pooling layer
* split tensor.hpp into tensor.hpp and tensor_ops.hpp
* add concat layer
* add scale layer
* add batch normalization layer
* split math.cu into activations.cu and math.hpp
* add eltwise layer
* add flatten layer
* add tensor transform api
* add asymmetric padding support for convolution layer
* add reshape layer
* fix rebase issues
* add permute layer
* add padding support for concat layer
* refactor and reorganize code
* add normalize layer
* optimize bias addition in scale layer
* add prior box layer
* fix and optimize normalize layer
* add asymmetric padding support for pooling layer
* add event API
* improve pooling performance for some padding scenarios
* avoid over-allocation of compute resources to kernels
* improve prior box performance
* enable layer fusion
* add const layer
* add resize layer
* add slice layer
* add padding layer
* add deconvolution layer
* fix channelwise ReLU initialization
* add vector traits
* add vectorized versions of relu, clipped_relu, power
* add vectorized concat kernels
* improve concat_with_offsets performance
* vectorize scale and bias kernels
* add support for multi-billion element tensors
* vectorize prior box kernels
* fix address alignment check
* improve bias addition performance of conv/deconv/fc layers
* restructure code for supporting multiple targets
* add DNN_TARGET_CUDA_FP64
* add DNN_TARGET_FP16
* improve vectorization
* add region layer
* improve tensor API, add dynamic ranks
1. use ManagedPtr instead of a Tensor in backend wrapper
2. add new methods to tensor classes
- size_range: computes the combined size of for a given axis range
- tensor span/view can be constructed from a raw pointer and shape
3. the tensor classes can change their rank at runtime (previously rank was fixed at compile-time)
4. remove device code from tensor classes (as they are unused)
5. enforce strict conditions on tensor class APIs to improve debugging ability
* fix parametric relu activation
* add squeeze/unsqueeze tensor API
* add reorg layer
* optimize permute and enable 2d permute
* enable 1d and 2d slice
* add split layer
* add shuffle channel layer
* allow tensors of different ranks in reshape primitive
* patch SliceOp to allow Crop Layer
* allow extra shape inputs in reshape layer
* use `std::move_backward` instead of `std::move` for insert in resizable_static_array
* improve workspace management
* add spatial LRN
* add nms (cpu) to region layer
* add max pooling with argmax ( and a fix to limits.hpp)
* add max unpooling layer
* rename DNN_TARGET_CUDA_FP32 to DNN_TARGET_CUDA
* update supportBackend to be more rigorous
* remove stray include from preventing non-cuda build
* include op_cuda.hpp outside condition #if
* refactoring, fixes and many optimizations
* drop DNN_TARGET_CUDA_FP64
* fix gcc errors
* increase max. tensor rank limit to six
* add Interp layer
* drop custom layers; use BackendNode
* vectorize activation kernels
* fixes for gcc
* remove wrong assertion
* fix broken assertion in unpooling primitive
* fix build errors in non-CUDA build
* completely remove workspace from public API
* fix permute layer
* enable accuracy and perf. tests for DNN_TARGET_CUDA
* add asynchronous forward
* vectorize eltwise ops
* vectorize fill kernel
* fixes for gcc
* remove CSL headers from public API
* remove csl header source group from cmake
* update min. cudnn version in cmake
* add numerically stable FP32 log1pexp
* refactor code
* add FP16 specialization to cudnn based tensor addition
* vectorize scale1 and bias1 + minor refactoring
* fix doxygen build
* fix invalid alignment assertion
* clear backend wrappers before allocateLayers
* ignore memory lock failures
* do not allocate internal blobs
* integrate NVTX
* add numerically stable half precision log1pexp
* fix indentation, following coding style, improve docs
* remove accidental modification of IE code
* Revert "add asynchronous forward"
This reverts commit 1154b9da9da07e9b52f8a81bdcea48cf31c56f70.
* [cmake] throw error for unsupported CC versions
* fix rebase issues
* add more docs, refactor code, fix bugs
* minor refactoring and fixes
* resolve warnings/errors from clang
* remove haveCUDA() checks from supportBackend()
* remove NVTX integration
* changes based on review comments
* avoid exception when no CUDA device is present
* add color code for CUDA in Net::dump
5 years ago
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if (targetId != DNN_TARGET_CPU && backendId != DNN_BACKEND_CUDA)
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throw SkipTestException("Only CPU and CUDA is supported");
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int inChannels = inputShape[1];
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int sz[] = {outChannels, inChannels / groups, params.kernel[0], params.kernel[1], params.kernel[2]};
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Mat weights(5, &sz[0], CV_32F);
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randu(weights, -1.0f, 1.0f);
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LayerParams lp;
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lp.set("kernel_size", kernel);
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lp.set("pad", pad);
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if (!padMode.empty())
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lp.set("pad_mode", padMode);
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lp.set("stride", stride);
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lp.set("dilation", dilation);
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lp.set("num_output", outChannels);
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lp.set("group", groups);
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lp.set("bias_term", hasBias);
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lp.type = "Convolution";
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lp.name = "testLayer";
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lp.blobs.push_back(weights);
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if (hasBias)
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{
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Mat bias(1, outChannels, CV_32F);
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randu(bias, -1.0f, 1.0f);
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lp.blobs.push_back(bias);
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}
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int inpSz[] = {1, inChannels, inputShape[2], inputShape[3], inputShape[4]};
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Mat input(5, &inpSz[0], CV_32F);
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randu(input, -1.0f, 1.0f);
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Net net;
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net.addLayerToPrev(lp.name, lp.type, lp);
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net.setInput(input);
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net.setPreferableBackend(backendId);
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net.setPreferableTarget(targetId);
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Mat output = net.forward();
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MatShape netInputShape = shape(input);
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size_t weightsMemory = 0, blobsMemory = 0;
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net.getMemoryConsumption(netInputShape, weightsMemory, blobsMemory);
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int64 flops = net.getFLOPS(netInputShape);
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CV_Assert(flops > 0);
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std::cout
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<< "IN=" << divUp(input.total() * input.elemSize(), 1u<<10) << " Kb " << netInputShape
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<< " OUT=" << divUp(output.total() * output.elemSize(), 1u<<10) << " Kb " << shape(output)
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<< " Weights(parameters): " << divUp(weightsMemory, 1u<<10) << " Kb"
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<< " MFLOPS=" << flops * 1e-6 << std::endl;
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TEST_CYCLE()
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{
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Mat res = net.forward();
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}
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EXPECT_NEAR(flops, declared_flops, declared_flops * 1e-6);
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SANITY_CHECK_NOTHING();
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}
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INSTANTIATE_TEST_CASE_P(/**/, Conv3D, Combine(
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Conv3DParamID::all(),
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dnnBackendsAndTargets(false, false) // defined in ../test/test_common.hpp
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));
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} // namespace
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