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## Experimental FPGA support |
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|
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This version adds support for generating, analysing and uploading FPGA |
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programs using the [IceStorm |
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toolchain](http://www.clifford.at/icestorm/). This support is |
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experimental and is currently limited to the `iCE 40` series of FPGA |
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chips. |
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|
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FPGA generation integrates with other parts of Meson seamlessly. As an |
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example, [here](https://github.com/jpakkane/lm32) is an example |
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project that compiles a simple firmware into Verilog and combines that |
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with an lm32 softcore processor. |
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# Copyright 2017 The Meson development team |
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|
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# Licensed under the Apache License, Version 2.0 (the "License"); |
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# you may not use this file except in compliance with the License. |
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# You may obtain a copy of the License at |
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|
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# http://www.apache.org/licenses/LICENSE-2.0 |
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# Unless required by applicable law or agreed to in writing, software |
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# distributed under the License is distributed on an "AS IS" BASIS, |
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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# See the License for the specific language governing permissions and |
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# limitations under the License. |
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|
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from .. import mesonlib, compilers, mlog |
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from . import ExtensionModule |
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class IceStormModule(ExtensionModule): |
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def __init__(self): |
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super().__init__() |
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self.snippets.add('project') |
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self.yosys_bin = None |
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|
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def detect_binaries(self, interpreter): |
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self.yosys_bin = interpreter.func_find_program(None, ['yosys'], {}) |
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self.arachne_bin = interpreter.func_find_program(None, ['arachne-pnr'], {}) |
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self.icepack_bin = interpreter.func_find_program(None, ['icepack'], {}) |
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self.iceprog_bin = interpreter.func_find_program(None, ['iceprog'], {}) |
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self.icetime_bin = interpreter.func_find_program(None, ['icetime'], {}) |
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|
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def project(self, interpreter, state, args, kwargs): |
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if not self.yosys_bin: |
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self.detect_binaries(interpreter) |
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result = [] |
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if not len(args): |
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raise mesonlib.MesonException('Project requires at least one argument, which is the project name.') |
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proj_name = args[0] |
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arg_sources = args[1:] |
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if not isinstance(proj_name, str): |
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raise mesonlib.MesonException('Argument must be a string.') |
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kwarg_sources = kwargs.get('sources', []) |
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if not isinstance(kwarg_sources, list): |
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kwarg_sources = [kwarg_sources] |
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all_sources = interpreter.source_strings_to_files(interpreter.flatten(arg_sources + kwarg_sources)) |
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if 'constraint_file' not in kwargs: |
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raise mesonlib.MesonException('Constraint file not specified.') |
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|
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constraint_file = interpreter.source_strings_to_files(kwargs['constraint_file']) |
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if len(constraint_file) != 1: |
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raise mesonlib.MesonException('Constraint file must contain one and only one entry.') |
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blif_name = proj_name + '_blif' |
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blif_fname = proj_name + '.blif' |
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asc_name = proj_name + '_asc' |
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asc_fname = proj_name + '.asc' |
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bin_name = proj_name + '_bin' |
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bin_fname = proj_name + '.bin' |
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time_name = proj_name + '-time' |
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upload_name = proj_name + '-upload' |
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blif_target = interpreter.func_custom_target(None, [blif_name], { |
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'input': all_sources, |
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'output': blif_fname, |
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'command': [self.yosys_bin, '-q', '-p', 'synth_ice40 -blif @OUTPUT@', '@INPUT@']}) |
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asc_target = interpreter.func_custom_target(None, [asc_name], { |
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'input': blif_target, |
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'output': asc_fname, |
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'command': [self.arachne_bin, '-q', '-d', '1k', '-p', constraint_file, '@INPUT@', '-o', '@OUTPUT@']}) |
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bin_target = interpreter.func_custom_target(None, [bin_name], { |
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'input': asc_target, |
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'output': bin_fname, |
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'command': [self.icepack_bin, '@INPUT@', '@OUTPUT@'], |
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'build_by_default' : True}) |
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up_target = interpreter.func_run_target(None, [upload_name], { |
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'command': [self.iceprog_bin, bin_target]}) |
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time_target = interpreter.func_run_target(None, [time_name], { |
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'command' : [self.icetime_bin, bin_target]}) |
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def initialize(): |
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return IceStormModule() |
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project('lattice', 'c') |
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is = import('unstable_icestorm') |
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is.project('spin', |
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'spin.v', |
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constraint_file : 'spin.pcf', |
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) |
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set_io LED1 99 |
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set_io LED2 98 |
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set_io LED3 97 |
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set_io LED4 96 |
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set_io LED5 95 |
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set_io clk 21 |
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module top(input clk, output LED1, output LED2, output LED3, output LED4, output LED5); |
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reg ready = 0; |
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reg [23:0] divider; |
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reg [3:0] spin; |
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always @(posedge clk) begin |
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if (ready) |
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begin |
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if (divider == 6000000) |
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begin |
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divider <= 0; |
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spin <= {spin[2], spin[3], spin[0], spin[1]}; |
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end |
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else |
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divider <= divider + 1; |
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end |
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else |
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begin |
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ready <= 1; |
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spin <= 4'b1010; |
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divider <= 0; |
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end |
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end |
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assign LED1 = spin[0]; |
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assign LED2 = spin[1]; |
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assign LED3 = spin[2]; |
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assign LED4 = spin[3]; |
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assign LED5 = 1; |
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endmodule |
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