Hardcode processor features on OSX because it ships a broken __builtin_cpu_supports.

test cases/common/139 simd/meson.build

@@ -12,7 +12,7 @@ if not meson.is_cross_build() and host_machine.cpu_family() == 'arm' and cc.get_
   add_project_arguments('-march=armv7', language : 'c')
 endif
 
-if cc.get_id() == 'msvc' and version_compare(cc.version(), '<17')
+if cc.get_id() == 'msvc' and cc.version().version_compare('<17')
   error('MESON_SKIP_TEST VS2010 produces broken binaries on x86.')
 endif
 

test cases/common/139 simd/simd_avx.c

@@ -8,14 +8,18 @@ int avx_available() {
   return 1;
 }
 #else
-
 #include<immintrin.h>
 #include<cpuid.h>
 
+#ifdef __APPLE__
+int avx_available() { return 1; }
+#else
+
 int avx_available() {
     return __builtin_cpu_supports("avx");
 }
 #endif
+#endif
 
 void increment_avx(float arr[4]) {
     double darr[4];

test cases/common/139 simd/simd_avx2.c

@@ -15,10 +15,14 @@ int avx2_available() {
 #include<immintrin.h>
 #include<cpuid.h>
 
+#if defined(__APPLE__)
+int avx2_available() { return 0; }
+#else
 int avx2_available() {
     return __builtin_cpu_supports("avx2");
 }
 #endif
+#endif
 
 void increment_avx2(float arr[4]) {
     double darr[4];

test cases/common/139 simd/simd_mmx.c

@@ -32,10 +32,14 @@ void increment_mmx(float arr[4]) {
 #else
 #include<mmintrin.h>
 #include<cpuid.h>
+
+#if defined(__APPLE__)
+int mmx_available() { return 1; }
+#else
 int mmx_available() {
     return __builtin_cpu_supports("mmx");
 }
-
+#endif
 void increment_mmx(float arr[4]) {
     /* Super ugly but we know that values in arr are always small
      * enough to fit in int16;

test cases/common/139 simd/simd_sse.c

@@ -7,14 +7,19 @@ int sse_available() {
   return 1;
 }
 #else
+
 #include<xmmintrin.h>
 #include<cpuid.h>
 #include<stdint.h>
 
+#if defined(__APPLE__)
+int sse_available() { return 1; }
+#else
 int sse_available() {
     return __builtin_cpu_supports("sse");
 }
 #endif
+#endif
 
 void increment_sse(float arr[4]) {
     __m128 val = _mm_load_ps(arr);

test cases/common/139 simd/simd_sse2.c

@@ -11,10 +11,14 @@ int sse2_available() {
 #include<cpuid.h>
 #include<stdint.h>
 
+#if defined(__APPLE__)
+int sse2_available() { return 1; }
+#else
 int sse2_available() {
     return __builtin_cpu_supports("sse2");
 }
 #endif
+#endif
 
 void increment_sse2(float arr[4]) {
     double darr[4];

test cases/common/139 simd/simd_sse3.c

@@ -7,14 +7,19 @@ int sse3_available() {
     return 1;
 }
 #else
+
 #include<pmmintrin.h>
 #include<cpuid.h>
 #include<stdint.h>
 
+#if defined(__APPLE__)
+int sse3_available() { return 1; }
+#else
 int sse3_available() {
     return __builtin_cpu_supports("sse3");
 }
 #endif
+#endif
 
 void increment_sse3(float arr[4]) {
     double darr[4];

test cases/common/139 simd/simd_sse41.c

@@ -14,10 +14,13 @@ int sse41_available() {
 #include<smmintrin.h>
 #include<cpuid.h>
 
+#if defined(__APPLE__)
+int sse41_available() { return 1; }
+#else
 int sse41_available() {
     return __builtin_cpu_supports("sse4.1");
 }
-
+#endif
 #endif
 
 void increment_sse41(float arr[4]) {

test cases/common/139 simd/simd_sse42.c

@@ -14,11 +14,18 @@ int sse42_available() {
 #include<nmmintrin.h>
 #include<cpuid.h>
 
+#ifdef __APPLE__
+int sse42_available() {
+    return 1;
+}
+#else
 int sse42_available() {
     return __builtin_cpu_supports("sse4.2");
 }
 #endif
 
+#endif
+
 void increment_sse42(float arr[4]) {
     double darr[4];
     __m128d val1 = _mm_set_pd(arr[0], arr[1]);