diff --git a/test cases/common/139 simd/meson.build b/test cases/common/139 simd/meson.build index 7769bfdb6..1d23ffb78 100644 --- a/test cases/common/139 simd/meson.build +++ b/test cases/common/139 simd/meson.build @@ -18,7 +18,6 @@ cdata = configuration_data() # The following headers need to be added. Also Thumb and Altivec. # AES -# AVX # AVX512 simdlibs = [] @@ -30,6 +29,7 @@ simdarr = [['-mmmx', 'HAVE_MMX', 'simd_mmx', 'simd_mmx.c'], ['-mssse3', 'HAVE_SSSE3', 'simd_ssse3', 'simd_ssse3.c'], ['-msse4.1', 'HAVE_SSE41', 'simd_sse41', 'simd_sse41.c'], ['-msse4.2', 'HAVE_SSE42', 'simd_sse42', 'simd_sse42.c'], + ['-mavx', 'HAVE_AVX', 'simd_avx', 'simd_avx.c'], ] foreach ia : simdarr diff --git a/test cases/common/139 simd/simd_avx.c b/test cases/common/139 simd/simd_avx.c new file mode 100644 index 000000000..26d76a008 --- /dev/null +++ b/test cases/common/139 simd/simd_avx.c @@ -0,0 +1,26 @@ +#include +#include + +#include +#include +#include + +int avx_available() { + return __builtin_cpu_supports("avx"); +} + +void increment_avx(float arr[4]) { + double darr[4]; + darr[0] = arr[0]; + darr[1] = arr[1]; + darr[2] = arr[2]; + darr[3] = arr[3]; + __m256d val = _mm256_loadu_pd(darr); + __m256d one = _mm256_set1_pd(1.0); + __m256d result = _mm256_add_pd(val, one); + _mm256_storeu_pd(darr, result); + arr[0] = (float)darr[0]; + arr[1] = (float)darr[1]; + arr[2] = (float)darr[2]; + arr[3] = (float)darr[3]; +} diff --git a/test cases/common/139 simd/simdchecker.c b/test cases/common/139 simd/simdchecker.c index 62841b04f..da53f0ada 100644 --- a/test cases/common/139 simd/simdchecker.c +++ b/test cases/common/139 simd/simdchecker.c @@ -17,6 +17,12 @@ int main(int argc, char **argv) { /* Add here. The first matched one is used so put "better" instruction * sets at the top. */ +#if HAVE_AVX + if(fptr == NULL && avx_available()) { + fptr = increment_avx; + type = "AVX"; + } +#endif #if HAVE_SSE42 if(fptr == NULL && sse42_available()) { fptr = increment_sse42;