Created sample project for IceStorm FPGA development.

test cases/fpga/1 simple/meson.build

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+project('lattice', 'c')
+
+yosys_bin = find_program('yosys')
+arachne_bin = find_program('arachne-pnr')
+icepack_bin = find_program('icepack')
+iceprog_bin = find_program('iceprog')
+icetime_bin = find_program('icetime')
+
+pcffile = files('spin.pcf')
+
+blif = custom_target('spin_blif',
+  input : 'spin.v',
+  output : 'spin.blif',
+  command : [yosys_bin, '-q', '-p', 'synth_ice40 -blif @OUTPUT@', '@INPUT@'],
+  )
+
+asc = custom_target('spin_asc',
+  input : blif,
+  output : 'spin.asc',
+  command : [arachne_bin, '-q', '-d', '1k', '-p', pcffile, '@INPUT@', '-o', '@OUTPUT@'],
+  )
+
+bin = custom_target('spin-bin',
+  input : asc,
+  output : 'spin.bin',
+  command : [icepack_bin, '@INPUT@', '@OUTPUT@'],
+  build_by_default : true
+  )
+
+run_target('spin-time',
+  command : [icetime_bin, '-tmd', 'hx1k', asc],
+  )
+
+run_target('spin-upload',
+  command : [iceprog_bin, bin]
+  )

test cases/fpga/1 simple/spin.pcf

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+set_io LED1 99
+set_io LED2 98
+set_io LED3 97
+set_io LED4 96
+set_io LED5 95
+set_io clk 21

test cases/fpga/1 simple/spin.v

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+
+module top(input clk, output LED1, output LED2, output LED3, output LED4, output LED5);
+   
+   reg ready = 0;
+   reg [23:0] divider;
+   reg [3:0] spin;
+   
+   always @(posedge clk) begin
+      if (ready) 
+        begin
+           if (divider == 6000000) 
+             begin
+                divider <= 0;
+                spin <= {spin[2], spin[3], spin[0], spin[1]};
+             end
+           else 
+             divider <= divider + 1;
+        end
+      else 
+        begin
+           ready <= 1;
+           spin <= 4'b1010;
+           divider <= 0;
+        end
+   end
+   
+   assign LED1 = spin[0];
+   assign LED2 = spin[1];
+   assign LED3 = spin[2];
+   assign LED4 = spin[3];
+   assign LED5 = 1;
+endmodule