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# Unstable SIMD module
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This module provides is available since version 0.45.0.
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**Note**: this module is unstable. It is only provided as a technology
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preview. Its API may change in arbitrary ways between releases or it
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might be removed from Meson altogether.
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## Usage
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This module provides an experimental to create FPGA bitstreams using
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the [IceStorm](http://www.clifford.at/icestorm/) suite of tools.
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The module exposes only one method called `project` and it is used
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like this:
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is.project('projname',
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<verilog files>,
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constraint_file : <pcf file>,
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)
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The input to this function is the set of Verilog files and a
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constraint file. This produces output files called `projname.asc`,
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`projname.blif` and `projname.bin`. In addition it creates two run
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targets called `projname-time` for running timing analysis and
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`projname-upload` that uploads the generated bitstream to an FPGA
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devide using the `iceprog` programming executable.
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