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410 lines
12 KiB
410 lines
12 KiB
//===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===// |
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// |
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// The LLVM Compiler Infrastructure |
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// |
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// This file is distributed under the University of Illinois Open Source |
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// License. See LICENSE.TXT for details. |
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// |
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//===----------------------------------------------------------------------===// |
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// |
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// This file includes code for rendering MCInst instances as AT&T-style |
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// assembly. |
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// |
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//===----------------------------------------------------------------------===// |
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/* Capstone Disassembler Engine */ |
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */ |
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#include <ctype.h> |
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#include <inttypes.h> |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include "../../utils.h" |
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#include "../../MCInst.h" |
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#include "../../SStream.h" |
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#include "../../MCRegisterInfo.h" |
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#include "mapping.h" |
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#define markup(x) "" |
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const char *X86ATT_getRegisterName(unsigned RegNo); |
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static void printMemReference(MCInst *MI, unsigned Op, SStream *O); |
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static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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SStream_concat(O, "OPAQUE PTR "); |
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printMemReference(MI, OpNo, O); |
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} |
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static void printi8mem(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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SStream_concat(O, "BYTE PTR "); |
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printMemReference(MI, OpNo, O); |
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} |
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static void printi16mem(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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SStream_concat(O, "WORD PTR "); |
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printMemReference(MI, OpNo, O); |
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} |
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static void printi32mem(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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SStream_concat(O, "DWORD PTR "); |
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printMemReference(MI, OpNo, O); |
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} |
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static void printi64mem(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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SStream_concat(O, "QWORD PTR "); |
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printMemReference(MI, OpNo, O); |
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} |
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static void printi128mem(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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SStream_concat(O, "XMMWORD PTR "); |
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printMemReference(MI, OpNo, O); |
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} |
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static void printi256mem(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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SStream_concat(O, "YMMWORD PTR "); |
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printMemReference(MI, OpNo, O); |
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} |
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static void printi512mem(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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printMemReference(MI, OpNo, O); |
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} |
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static void printf32mem(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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SStream_concat(O, "DWORD PTR "); |
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printMemReference(MI, OpNo, O); |
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} |
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static void printf64mem(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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SStream_concat(O, "QWORD PTR "); |
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printMemReference(MI, OpNo, O); |
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} |
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static void printf80mem(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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SStream_concat(O, "XWORD PTR "); |
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printMemReference(MI, OpNo, O); |
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} |
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static void printf128mem(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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SStream_concat(O, "XMMWORD PTR "); |
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printMemReference(MI, OpNo, O); |
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} |
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static void printf256mem(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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SStream_concat(O, "YMMWORD PTR "); |
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printMemReference(MI, OpNo, O); |
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} |
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static void printf512mem(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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printMemReference(MI, OpNo, O); |
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} |
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static void printMemOffset(MCInst *MI, unsigned Op, SStream *O) |
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{ |
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MCOperand *DispSpec = MCInst_getOperand(MI, Op); |
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SStream_concat(O, "%s", markup("<mem:")); |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_MEM; |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.base = X86_REG_INVALID; |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.index = X86_REG_INVALID; |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.scale = 1; |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.disp = 0; |
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if (MCOperand_isImm(DispSpec)) { |
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int64_t imm = MCOperand_getImm(DispSpec); |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.disp = imm; |
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if (imm < 0) |
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SStream_concat(O, "-0x%"PRIx64, -imm); |
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else |
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SStream_concat(O, "0x%"PRIx64, imm); |
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} |
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SStream_concat(O, "%s", markup(">")); |
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MI->pub_insn.x86.op_count++; |
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} |
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static void printMemOffs8(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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printMemOffset(MI, OpNo, O); |
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} |
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static void printMemOffs16(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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printMemOffset(MI, OpNo, O); |
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} |
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static void printMemOffs32(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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printMemOffset(MI, OpNo, O); |
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} |
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static void printMemOffs64(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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printMemOffset(MI, OpNo, O); |
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} |
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static void printRegName(SStream *OS, unsigned RegNo); |
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static void printSSECC(MCInst *MI, unsigned Op, SStream *OS) |
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{ |
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int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0xf; |
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switch (Imm) { |
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default: break; // never reach |
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case 0: SStream_concat(OS, "eq"); break; |
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case 1: SStream_concat(OS, "lt"); break; |
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case 2: SStream_concat(OS, "le"); break; |
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case 3: SStream_concat(OS, "unord"); break; |
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case 4: SStream_concat(OS, "neq"); break; |
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case 5: SStream_concat(OS, "nlt"); break; |
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case 6: SStream_concat(OS, "nle"); break; |
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case 7: SStream_concat(OS, "ord"); break; |
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case 8: SStream_concat(OS, "eq_uq"); break; |
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case 9: SStream_concat(OS, "nge"); break; |
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case 0xa: SStream_concat(OS, "ngt"); break; |
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case 0xb: SStream_concat(OS, "false"); break; |
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case 0xc: SStream_concat(OS, "neq_oq"); break; |
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case 0xd: SStream_concat(OS, "ge"); break; |
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case 0xe: SStream_concat(OS, "gt"); break; |
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case 0xf: SStream_concat(OS, "true"); break; |
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} |
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} |
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static void printAVXCC(MCInst *MI, unsigned Op, SStream *O) |
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{ |
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int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f; |
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switch (Imm) { |
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default: printf("Invalid avxcc argument!\n"); break; |
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case 0: SStream_concat(O, "eq"); break; |
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case 1: SStream_concat(O, "lt"); break; |
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case 2: SStream_concat(O, "le"); break; |
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case 3: SStream_concat(O, "unord"); break; |
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case 4: SStream_concat(O, "neq"); break; |
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case 5: SStream_concat(O, "nlt"); break; |
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case 6: SStream_concat(O, "nle"); break; |
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case 7: SStream_concat(O, "ord"); break; |
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case 8: SStream_concat(O, "eq_uq"); break; |
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case 9: SStream_concat(O, "nge"); break; |
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case 0xa: SStream_concat(O, "ngt"); break; |
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case 0xb: SStream_concat(O, "false"); break; |
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case 0xc: SStream_concat(O, "neq_oq"); break; |
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case 0xd: SStream_concat(O, "ge"); break; |
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case 0xe: SStream_concat(O, "gt"); break; |
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case 0xf: SStream_concat(O, "true"); break; |
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case 0x10: SStream_concat(O, "eq_os"); break; |
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case 0x11: SStream_concat(O, "lt_oq"); break; |
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case 0x12: SStream_concat(O, "le_oq"); break; |
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case 0x13: SStream_concat(O, "unord_s"); break; |
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case 0x14: SStream_concat(O, "neq_us"); break; |
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case 0x15: SStream_concat(O, "nlt_uq"); break; |
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case 0x16: SStream_concat(O, "nle_uq"); break; |
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case 0x17: SStream_concat(O, "ord_s"); break; |
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case 0x18: SStream_concat(O, "eq_us"); break; |
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case 0x19: SStream_concat(O, "nge_uq"); break; |
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case 0x1a: SStream_concat(O, "ngt_uq"); break; |
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case 0x1b: SStream_concat(O, "false_os"); break; |
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case 0x1c: SStream_concat(O, "neq_os"); break; |
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case 0x1d: SStream_concat(O, "ge_oq"); break; |
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case 0x1e: SStream_concat(O, "gt_oq"); break; |
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case 0x1f: SStream_concat(O, "true_us"); break; |
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} |
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} |
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/// printPCRelImm - This is used to print an immediate value that ends up |
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/// being encoded as a pc-relative value (e.g. for jumps and calls). These |
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/// print slightly differently than normal immediates. For example, a $ is not |
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/// emitted. |
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static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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MCOperand *Op = MCInst_getOperand(MI, OpNo); |
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if (MCOperand_isImm(Op)) { |
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int64_t imm = MCOperand_getImm(Op) + MI->pub_insn.size + MI->pub_insn.address; |
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if (imm < 0) |
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SStream_concat(O, "-0x%"PRIx64, -imm); |
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else |
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SStream_concat(O, "0x%"PRIx64, imm); |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_IMM; |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].imm = imm; |
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MI->pub_insn.x86.op_count++; |
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} |
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} |
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static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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MCOperand *Op = MCInst_getOperand(MI, OpNo); |
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if (MCOperand_isReg(Op)) { |
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printRegName(O, MCOperand_getReg(Op)); |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_REG; |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].reg = MCOperand_getReg(Op); |
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MI->pub_insn.x86.op_count++; |
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} else if (MCOperand_isImm(Op)) { |
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// Print X86 immediates as signed values. |
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int64_t imm = MCOperand_getImm(Op); |
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if (imm < 0) |
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SStream_concat(O, "%s$-0x%"PRIx64"%s", markup("<imm:"), -imm, markup(">")); |
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else |
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SStream_concat(O, "%s$0x%"PRIx64"%s", markup("<imm:"), imm, markup(">")); |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_IMM; |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].imm = imm; |
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MI->pub_insn.x86.op_count++; |
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} |
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} |
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// local printOperand, without updating public operands |
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static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O) |
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{ |
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MCOperand *Op = MCInst_getOperand(MI, OpNo); |
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if (MCOperand_isReg(Op)) { |
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printRegName(O, MCOperand_getReg(Op)); |
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} else if (MCOperand_isImm(Op)) { |
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// Print X86 immediates as signed values. |
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int64_t imm = MCOperand_getImm(Op); |
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if (imm < 0) |
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SStream_concat(O, "%s$-0x%"PRIx64"%s", markup("<imm:"), -imm, markup(">")); |
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else |
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SStream_concat(O, "%s$0x%"PRIx64"%s", markup("<imm:"), imm, markup(">")); |
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} |
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} |
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static void printMemReference(MCInst *MI, unsigned Op, SStream *O) |
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{ |
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MCOperand *BaseReg = MCInst_getOperand(MI, Op); |
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MCOperand *IndexReg = MCInst_getOperand(MI, Op+2); |
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MCOperand *DispSpec = MCInst_getOperand(MI, Op+3); |
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MCOperand *SegReg = MCInst_getOperand(MI, Op+4); |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_MEM; |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.base = MCOperand_getReg(BaseReg); |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.index = MCOperand_getReg(IndexReg); |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.scale = 1; |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.disp = 0; |
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SStream_concat(O, markup("<mem:")); |
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// If this has a segment register, print it. |
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if (MCOperand_getReg(SegReg)) { |
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_printOperand(MI, Op+4, O); |
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SStream_concat(O, ":"); |
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} |
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if (MCOperand_isImm(DispSpec)) { |
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int64_t DispVal = MCOperand_getImm(DispSpec); |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.disp = DispVal; |
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if (DispVal || (!MCOperand_getReg(IndexReg) && !MCOperand_getReg(BaseReg))) { |
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if (DispVal < 0) |
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SStream_concat(O, "-0x%"PRIx64, -DispVal); |
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else |
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SStream_concat(O, "0x%"PRIx64, DispVal); |
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} |
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} |
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if (MCOperand_getReg(IndexReg) || MCOperand_getReg(BaseReg)) { |
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SStream_concat(O, "("); |
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if (MCOperand_getReg(BaseReg)) |
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_printOperand(MI, Op, O); |
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if (MCOperand_getReg(IndexReg)) { |
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SStream_concat(O, ", "); |
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_printOperand(MI, Op+2, O); |
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unsigned ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op+1)); |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].mem.scale = ScaleVal; |
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if (ScaleVal != 1) { |
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SStream_concat(O, ", %s%u%s", markup("<imm:"), ScaleVal, markup(">")); |
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} |
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} |
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SStream_concat(O, ")"); |
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} |
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SStream_concat(O, markup(">")); |
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MI->pub_insn.x86.op_count++; |
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} |
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#include "X86InstPrinter.h" |
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#define GET_INSTRINFO_ENUM |
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#include "X86GenInstrInfo.inc" |
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#define GET_REGINFO_ENUM |
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#include "X86GenRegisterInfo.inc" |
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// Include the auto-generated portion of the assembly writer. |
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#define PRINT_ALIAS_INSTR |
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#include "X86GenAsmWriter.inc" |
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static void printRegName(SStream *OS, unsigned RegNo) |
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{ |
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SStream_concat(OS, "%s%%%s%s", markup("<reg:"), getRegisterName(RegNo), markup(">")); |
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} |
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// get the first op from the asm buffer |
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// NOTE: make sure firstop is big enough to contain the resulted string |
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static void get_last_op(char *buffer, char *lastop) |
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{ |
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char *comma = strrchr(buffer, ','); |
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if (comma) { |
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// skip a space after the comma |
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strcpy(lastop, comma + 2); |
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} else // no op |
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lastop[0] = '\0'; |
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} |
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void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info) |
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{ |
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// FIXME |
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//const MCInstrDesc *Desc = MII.get(MI->getOpcode()); |
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//uint64_t TSFlags = Desc.TSFlags; |
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//if (TSFlags & X86II::LOCK) |
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// OS << "\tlock\n"; |
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// Try to print any aliases first. |
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if (printAliasInstr(MI, OS)) { |
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char *mnem = strdup(OS->buffer); |
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char *tab = strchr(mnem, '\t'); |
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if (tab) |
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*tab = '\0'; |
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// reflect the new insn name (alias) in the opcode |
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MCInst_setOpcode(MI, X86_get_insn_id2(X86_map_insn(mnem))); |
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free(mnem); |
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} else |
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printInstruction(MI, OS); |
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// first op can be embedded in the asm by llvm. |
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// so we have to handle that case to not miss the first op. |
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char lastop[32]; |
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get_last_op(OS->buffer, lastop); |
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char *acc_regs[] = {"rax", "eax", "ax", "al", NULL}; |
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if (lastop[0] == '%' && str_in_list(acc_regs, lastop+1)) { |
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// this is one of the registers AL, AX, EAX, RAX |
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// canonicalize the register name first |
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//int i; |
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//for (i = 1; lastop[i]; i++) |
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// lastop[i] = tolower(lastop[i]); |
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if (MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count - 1].type != X86_OP_REG) { |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_REG; |
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MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].reg = x86_map_regname(lastop + 1); |
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MI->pub_insn.x86.op_count++; |
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} |
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} |
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} |
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