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110 lines
3.1 KiB
110 lines
3.1 KiB
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
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|* *| |
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|*Target Register Enum Values *| |
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|* *| |
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|* Automatically generated file, do not edit! *| |
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|* *| |
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\*===----------------------------------------------------------------------===*/ |
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/* Capstone Disassembly Engine */ |
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ |
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#ifdef GET_REGINFO_ENUM |
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#undef GET_REGINFO_ENUM |
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enum { |
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XCore_NoRegister, |
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XCore_CP = 1, |
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XCore_DP = 2, |
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XCore_LR = 3, |
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XCore_SP = 4, |
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XCore_R0 = 5, |
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XCore_R1 = 6, |
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XCore_R2 = 7, |
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XCore_R3 = 8, |
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XCore_R4 = 9, |
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XCore_R5 = 10, |
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XCore_R6 = 11, |
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XCore_R7 = 12, |
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XCore_R8 = 13, |
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XCore_R9 = 14, |
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XCore_R10 = 15, |
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XCore_R11 = 16, |
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XCore_NUM_TARGET_REGS // 17 |
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}; |
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// Register classes |
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enum { |
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XCore_RRegsRegClassID = 0, |
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XCore_GRRegsRegClassID = 1 |
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}; |
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#endif // GET_REGINFO_ENUM |
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
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|* *| |
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|*MC Register Information *| |
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|* *| |
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|* Automatically generated file, do not edit! *| |
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|* *| |
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\*===----------------------------------------------------------------------===*/ |
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#ifdef GET_REGINFO_MC_DESC |
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#undef GET_REGINFO_MC_DESC |
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static MCPhysReg XCoreRegDiffLists[] = { |
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/* 0 */ 65535, 0, |
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}; |
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static uint16_t XCoreSubRegIdxLists[] = { |
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/* 0 */ 0, |
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}; |
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static MCRegisterDesc XCoreRegDesc[] = { // Descriptors |
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{ 3, 0, 0, 0, 0 }, |
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{ 38, 1, 1, 0, 1 }, |
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{ 41, 1, 1, 0, 1 }, |
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{ 47, 1, 1, 0, 1 }, |
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{ 44, 1, 1, 0, 1 }, |
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{ 4, 1, 1, 0, 1 }, |
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{ 11, 1, 1, 0, 1 }, |
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{ 14, 1, 1, 0, 1 }, |
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{ 17, 1, 1, 0, 1 }, |
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{ 20, 1, 1, 0, 1 }, |
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{ 23, 1, 1, 0, 1 }, |
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{ 26, 1, 1, 0, 1 }, |
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{ 29, 1, 1, 0, 1 }, |
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{ 32, 1, 1, 0, 1 }, |
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{ 35, 1, 1, 0, 1 }, |
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{ 0, 1, 1, 0, 1 }, |
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{ 7, 1, 1, 0, 1 }, |
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}; |
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// RRegs Register Class... |
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static MCPhysReg RRegs[] = { |
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XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, XCore_CP, XCore_DP, XCore_SP, XCore_LR, |
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}; |
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// RRegs Bit set. |
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static uint8_t RRegsBits[] = { |
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0xfe, 0xff, 0x01, |
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}; |
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// GRRegs Register Class... |
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static MCPhysReg GRRegs[] = { |
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XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, |
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}; |
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// GRRegs Bit set. |
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static uint8_t GRRegsBits[] = { |
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0xe0, 0xff, 0x01, |
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}; |
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static MCRegisterClass XCoreMCRegisterClasses[] = { |
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{ "RRegs", RRegs, RRegsBits, 16, sizeof(RRegsBits), XCore_RRegsRegClassID, 4, 4, 1, 0 }, |
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{ "GRRegs", GRRegs, GRRegsBits, 12, sizeof(GRRegsBits), XCore_GRRegsRegClassID, 4, 4, 1, 1 }, |
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}; |
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#endif // GET_REGINFO_MC_DESC
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