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740 lines
22 KiB
740 lines
22 KiB
//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===// |
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// |
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// The LLVM Compiler Infrastructure |
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// |
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// This file is distributed under the University of Illinois Open Source |
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// License. See LICENSE.TXT for details. |
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// |
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//===----------------------------------------------------------------------===// |
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// |
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// This file is part of the Mips Disassembler. |
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// |
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//===----------------------------------------------------------------------===// |
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/* Capstone Disassembler Engine */ |
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */ |
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#include <stdio.h> |
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#include <string.h> |
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#include <stdbool.h> |
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#include <inttypes.h> |
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#include "../../cs_priv.h" |
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#include "../../SubtargetFeature.h" |
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#include "../../MCInst.h" |
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#include "../../MCRegisterInfo.h" |
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#include "../../SStream.h" |
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#include "../../MathExtras.h" |
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#include "../../utils.h" |
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//#include "Mips.h" |
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//#include "MipsRegisterInfo.h" |
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//#include "MipsSubtarget.h" |
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#include "../../MCFixedLenDisassembler.h" |
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#include "../../MCInst.h" |
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//#include "llvm/MC/MCSubtargetInfo.h" |
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#include "../../MCRegisterInfo.h" |
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#include "../../MCDisassembler.h" |
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// Forward declare these because the autogenerated code will reference them. |
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// Definitions are further down. |
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static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeFGRH32RegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, |
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeBranchTarget(MCInst *Inst, |
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unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeJumpTarget(MCInst *Inst, |
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
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// DecodeBranchTargetMM - Decode microMIPS branch offset, which is |
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// shifted left by 1 bit. |
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static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, |
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unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder); |
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// DecodeJumpTargetMM - Decode microMIPS jump target, which is |
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// shifted left by 1 bit. |
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static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, |
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeMem(MCInst *Inst, |
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeMSA128Mem(MCInst *Inst, |
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeMemMMImm12(MCInst *Inst, |
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeMemMMImm16(MCInst *Inst, |
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn, |
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uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeSimm16(MCInst *Inst, |
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
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// Decode the immediate field of an LSA instruction which |
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// is off by one. |
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static DecodeStatus DecodeLSAImm(MCInst *Inst, |
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeInsSize(MCInst *Inst, |
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
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static DecodeStatus DecodeExtSize(MCInst *Inst, |
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder); |
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#define GET_SUBTARGETINFO_ENUM |
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#include "MipsGenSubtargetInfo.inc" |
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// Hacky: enable all features for disassembler |
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static uint64_t Mips_getFeatureBits(int mode) |
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{ |
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uint64_t Bits = -1; // include every features by default |
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// ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate() |
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// some features are mutually execlusive |
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if (mode & CS_MODE_16) { |
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Bits &= ~Mips_FeatureMips32r2; |
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Bits &= ~Mips_FeatureMips32; |
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Bits &= ~Mips_FeatureFPIdx; |
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Bits &= ~Mips_FeatureBitCount; |
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Bits &= ~Mips_FeatureSwap; |
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Bits &= ~Mips_FeatureSEInReg; |
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Bits &= ~Mips_FeatureMips64r2; |
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Bits &= ~Mips_FeatureFP64Bit; |
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} else if (mode & CS_MODE_32) { |
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Bits &= ~Mips_FeatureMips16; |
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Bits &= ~Mips_FeatureFP64Bit; |
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} else if (mode & CS_MODE_64) { |
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Bits &= ~Mips_FeatureMips16; |
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} |
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if (mode & CS_MODE_MICRO) |
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Bits |= Mips_FeatureMicroMips; |
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else |
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Bits &= ~Mips_FeatureMicroMips; |
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return Bits; |
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} |
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#include "MipsGenDisassemblerTables.inc" |
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#define GET_REGINFO_ENUM |
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#include "MipsGenRegisterInfo.inc" |
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#define GET_REGINFO_MC_DESC |
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#include "MipsGenRegisterInfo.inc" |
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#define GET_INSTRINFO_ENUM |
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#include "MipsGenInstrInfo.inc" |
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void Mips_init(MCRegisterInfo *MRI) |
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{ |
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// InitMCRegisterInfo(MipsRegDesc, 317, |
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// RA, PC, |
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// MipsMCRegisterClasses, 34, |
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// MipsRegUnitRoots, 196, |
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// MipsRegDiffLists, |
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// MipsRegStrings, |
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// MipsSubRegIdxLists, 12, |
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// MipsSubRegIdxRanges, MipsRegEncodingTable); |
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MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 317, |
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0, 0, |
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MipsMCRegisterClasses, 34, |
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0, 0, |
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MipsRegDiffLists, |
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0, |
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MipsSubRegIdxLists, 12, |
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0); |
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} |
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/// readInstruction - read four bytes from the MemoryObject |
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/// and return 32 bit word sorted according to the given endianess |
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static DecodeStatus readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips) |
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{ |
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// We want to read exactly 4 Bytes of data. |
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if (isBigEndian) { |
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// Encoded as a big-endian 32-bit word in the stream. |
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*insn = (code[3] << 0) | |
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(code[2] << 8) | |
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(code[1] << 16) | |
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(code[0] << 24); |
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} else { |
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// Encoded as a small-endian 32-bit word in the stream. |
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// Little-endian byte ordering: |
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// mips32r2: 4 | 3 | 2 | 1 |
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// microMIPS: 2 | 1 | 4 | 3 |
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if (isMicroMips) { |
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*insn = (code[2] << 0) | |
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(code[3] << 8) | |
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(code[0] << 16) | |
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(code[1] << 24); |
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} else { |
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*insn = (code[0] << 0) | |
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(code[1] << 8) | |
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(code[2] << 16) | |
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(code[3] << 24); |
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} |
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} |
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return MCDisassembler_Success; |
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} |
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static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr, |
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const uint8_t *code, size_t code_len, |
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uint16_t *Size, |
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uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI) |
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{ |
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uint32_t Insn; |
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if (code_len < 4) |
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// not enough data |
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return MCDisassembler_Fail; |
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DecodeStatus Result = readInstruction32((unsigned char*)code, &Insn, isBigEndian, |
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mode & CS_MODE_MICRO); |
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if (Result == MCDisassembler_Fail) |
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return MCDisassembler_Fail; |
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if (mode & CS_MODE_MICRO) { |
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// Calling the auto-generated decoder function. |
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Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, MRI, mode); |
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if (Result != MCDisassembler_Fail) { |
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*Size = 4; |
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return Result; |
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} |
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return MCDisassembler_Fail; |
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} |
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// Calling the auto-generated decoder function. |
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Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode); |
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if (Result != MCDisassembler_Fail) { |
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*Size = 4; |
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return Result; |
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} |
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return MCDisassembler_Fail; |
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} |
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bool Mips_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, |
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uint16_t *size, uint64_t address, void *info) |
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{ |
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cs_struct *handle = (cs_struct *)(uintptr_t)ud; |
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DecodeStatus status = MipsDisassembler_getInstruction(handle->mode, instr, |
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code, code_len, |
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size, |
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address, handle->big_endian, (MCRegisterInfo *)info); |
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return status == MCDisassembler_Success; |
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} |
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static DecodeStatus Mips64Disassembler_getInstruction(int mode, MCInst *instr, |
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unsigned char *code, size_t code_len, |
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uint16_t *Size, |
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uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI) |
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{ |
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uint32_t Insn; |
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DecodeStatus Result = readInstruction32((unsigned char*)code, &Insn, isBigEndian, false); |
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if (Result == MCDisassembler_Fail) |
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return MCDisassembler_Fail; |
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// Calling the auto-generated decoder function. |
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Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address, MRI, mode); |
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if (Result != MCDisassembler_Fail) { |
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*Size = 4; |
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return Result; |
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} |
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// If we fail to decode in Mips64 decoder space we can try in Mips32 |
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Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode); |
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if (Result != MCDisassembler_Fail) { |
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*Size = 4; |
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return Result; |
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} |
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return MCDisassembler_Fail; |
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} |
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bool Mips64_getInstruction(csh ud, unsigned char *code, size_t code_len, MCInst *instr, |
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uint16_t *size, uint64_t address, void *info) |
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{ |
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cs_struct *handle = (cs_struct *)(uintptr_t)ud; |
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DecodeStatus status = Mips64Disassembler_getInstruction(handle->mode, instr, |
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code, code_len, |
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size, |
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address, handle->big_endian, (MCRegisterInfo *)info); |
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return status == MCDisassembler_Success; |
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} |
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static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) |
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{ |
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//MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D); |
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//return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo); |
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MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC); |
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return rc->RegsBegin[RegNo]; |
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} |
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static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
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{ |
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return MCDisassembler_Fail; |
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} |
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static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
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{ |
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if (RegNo > 31) |
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return MCDisassembler_Fail; |
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unsigned Reg = getReg(Decoder, Mips_GPR64RegClassID, RegNo); |
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MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
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return MCDisassembler_Success; |
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} |
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static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
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{ |
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if (RegNo > 31) |
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return MCDisassembler_Fail; |
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unsigned Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo); |
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MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
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return MCDisassembler_Success; |
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} |
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static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
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{ |
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if (Inst->mode & CS_MODE_N64) |
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return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); |
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return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); |
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} |
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static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
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{ |
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return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); |
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} |
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static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
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{ |
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if (RegNo > 31) |
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return MCDisassembler_Fail; |
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unsigned Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo); |
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MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
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return MCDisassembler_Success; |
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} |
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static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
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{ |
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if (RegNo > 31) |
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return MCDisassembler_Fail; |
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unsigned Reg = getReg(Decoder, Mips_FGR32RegClassID, RegNo); |
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MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
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return MCDisassembler_Success; |
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} |
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static DecodeStatus DecodeFGRH32RegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
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{ |
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if (RegNo > 31) |
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return MCDisassembler_Fail; |
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unsigned Reg = getReg(Decoder, Mips_FGRH32RegClassID, RegNo); |
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MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
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return MCDisassembler_Success; |
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} |
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static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
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{ |
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if (RegNo > 31) |
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return MCDisassembler_Fail; |
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unsigned Reg = getReg(Decoder, Mips_CCRRegClassID, RegNo); |
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MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
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return MCDisassembler_Success; |
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} |
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static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, |
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unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
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{ |
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if (RegNo > 7) |
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return MCDisassembler_Fail; |
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unsigned Reg = getReg(Decoder, Mips_FCCRegClassID, RegNo); |
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MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
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return MCDisassembler_Success; |
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} |
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static DecodeStatus DecodeMem(MCInst *Inst, |
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
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{ |
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int Offset = SignExtend32(Insn & 0xffff, 16); |
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unsigned Reg = fieldFromInstruction(Insn, 16, 5); |
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unsigned Base = fieldFromInstruction(Insn, 21, 5); |
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Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); |
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Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
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if(MCInst_getOpcode(Inst) == Mips_SC){ |
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MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
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} |
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MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
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MCInst_addOperand(Inst, MCOperand_CreateReg(Base)); |
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MCInst_addOperand(Inst, MCOperand_CreateImm(Offset)); |
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return MCDisassembler_Success; |
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} |
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static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn, |
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uint64_t Address, MCRegisterInfo *Decoder) |
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{ |
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int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10); |
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unsigned Reg = fieldFromInstruction(Insn, 6, 5); |
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unsigned Base = fieldFromInstruction(Insn, 11, 5); |
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Reg = getReg(Decoder, Mips_MSA128BRegClassID, Reg); |
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Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
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MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
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MCInst_addOperand(Inst, MCOperand_CreateReg(Base)); |
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// MCInst_addOperand(Inst, MCOperand_CreateImm(Offset)); |
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// The immediate field of an LD/ST instruction is scaled which means it must |
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// be multiplied (when decoding) by the size (in bytes) of the instructions' |
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// data format. |
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// .b - 1 byte |
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// .h - 2 bytes |
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// .w - 4 bytes |
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// .d - 8 bytes |
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switch(MCInst_getOpcode(Inst)) |
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{ |
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default: |
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//assert (0 && "Unexpected instruction"); |
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return MCDisassembler_Fail; |
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break; |
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case Mips_LD_B: |
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case Mips_ST_B: |
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MCInst_addOperand(Inst, MCOperand_CreateImm(Offset)); |
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break; |
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case Mips_LD_H: |
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case Mips_ST_H: |
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MCInst_addOperand(Inst, MCOperand_CreateImm(Offset << 1)); |
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break; |
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case Mips_LD_W: |
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case Mips_ST_W: |
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MCInst_addOperand(Inst, MCOperand_CreateImm(Offset << 2)); |
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break; |
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case Mips_LD_D: |
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case Mips_ST_D: |
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MCInst_addOperand(Inst, MCOperand_CreateImm(Offset << 3)); |
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break; |
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} |
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return MCDisassembler_Success; |
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} |
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static DecodeStatus DecodeMemMMImm12(MCInst *Inst, |
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unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
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{ |
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int Offset = SignExtend32(Insn & 0x0fff, 12); |
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unsigned Reg = fieldFromInstruction(Insn, 21, 5); |
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unsigned Base = fieldFromInstruction(Insn, 16, 5); |
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Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); |
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Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
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MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
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MCInst_addOperand(Inst, MCOperand_CreateReg(Base)); |
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MCInst_addOperand(Inst, MCOperand_CreateImm(Offset)); |
|
|
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeMemMMImm16(MCInst *Inst, |
|
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
int Offset = SignExtend32(Insn & 0xffff, 16); |
|
unsigned Reg = fieldFromInstruction(Insn, 21, 5); |
|
unsigned Base = fieldFromInstruction(Insn, 16, 5); |
|
|
|
Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg); |
|
Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
|
|
|
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
|
MCInst_addOperand(Inst, MCOperand_CreateReg(Base)); |
|
MCInst_addOperand(Inst, MCOperand_CreateImm(Offset)); |
|
|
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeFMem(MCInst *Inst, |
|
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
int Offset = SignExtend32(Insn & 0xffff, 16); |
|
unsigned Reg = fieldFromInstruction(Insn, 16, 5); |
|
unsigned Base = fieldFromInstruction(Insn, 21, 5); |
|
|
|
Reg = getReg(Decoder, Mips_FGR64RegClassID, Reg); |
|
Base = getReg(Decoder, Mips_GPR32RegClassID, Base); |
|
|
|
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
|
MCInst_addOperand(Inst, MCOperand_CreateReg(Base)); |
|
MCInst_addOperand(Inst, MCOperand_CreateImm(Offset)); |
|
|
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, |
|
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
// Currently only hardware register 29 is supported. |
|
if (RegNo != 29) |
|
return MCDisassembler_Fail; |
|
MCInst_addOperand(Inst, MCOperand_CreateReg(Mips_HWR29)); |
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, |
|
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
if (RegNo > 30 || RegNo %2) |
|
return MCDisassembler_Fail; |
|
|
|
unsigned Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2); |
|
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, |
|
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
if (RegNo >= 4) |
|
return MCDisassembler_Fail; |
|
|
|
unsigned Reg = getReg(Decoder, Mips_ACC64DSPRegClassID, RegNo); |
|
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, |
|
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
if (RegNo >= 4) |
|
return MCDisassembler_Fail; |
|
|
|
unsigned Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo); |
|
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, |
|
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
if (RegNo >= 4) |
|
return MCDisassembler_Fail; |
|
|
|
unsigned Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo); |
|
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, |
|
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
if (RegNo > 31) |
|
return MCDisassembler_Fail; |
|
|
|
unsigned Reg = getReg(Decoder, Mips_MSA128BRegClassID, RegNo); |
|
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
|
|
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, |
|
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
if (RegNo > 31) |
|
return MCDisassembler_Fail; |
|
|
|
unsigned Reg = getReg(Decoder, Mips_MSA128HRegClassID, RegNo); |
|
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
|
|
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, |
|
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
if (RegNo > 31) |
|
return MCDisassembler_Fail; |
|
|
|
unsigned Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo); |
|
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
|
|
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, |
|
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
if (RegNo > 31) |
|
return MCDisassembler_Fail; |
|
|
|
unsigned Reg = getReg(Decoder, Mips_MSA128DRegClassID, RegNo); |
|
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
|
|
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, |
|
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
if (RegNo > 7) |
|
return MCDisassembler_Fail; |
|
|
|
unsigned Reg = getReg(Decoder, Mips_MSACtrlRegClassID, RegNo); |
|
MCInst_addOperand(Inst, MCOperand_CreateReg(Reg)); |
|
|
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeBranchTarget(MCInst *Inst, |
|
unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
unsigned BranchOffset = Offset & 0xffff; |
|
BranchOffset = SignExtend32(BranchOffset << 2, 18) + 4; |
|
MCInst_addOperand(Inst, MCOperand_CreateImm(BranchOffset)); |
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeJumpTarget(MCInst *Inst, |
|
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2; |
|
MCInst_addOperand(Inst, MCOperand_CreateImm(JumpOffset)); |
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, |
|
unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
unsigned BranchOffset = Offset & 0xffff; |
|
BranchOffset = SignExtend32(BranchOffset << 1, 18); |
|
MCInst_addOperand(Inst, MCOperand_CreateImm(BranchOffset)); |
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, |
|
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1; |
|
MCInst_addOperand(Inst, MCOperand_CreateImm(JumpOffset)); |
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeSimm16(MCInst *Inst, |
|
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
MCInst_addOperand(Inst, MCOperand_CreateImm(SignExtend32(Insn, 16))); |
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeLSAImm(MCInst *Inst, |
|
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
// We add one to the immediate field as it was encoded as 'imm - 1'. |
|
MCInst_addOperand(Inst, MCOperand_CreateImm(Insn + 1)); |
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeInsSize(MCInst *Inst, |
|
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
// First we need to grab the pos(lsb) from MCInst. |
|
int Pos = MCOperand_getImm(MCInst_getOperand(Inst, 2)); |
|
int Size = (int) Insn - Pos + 1; |
|
MCInst_addOperand(Inst, MCOperand_CreateImm(SignExtend32(Size, 16))); |
|
return MCDisassembler_Success; |
|
} |
|
|
|
static DecodeStatus DecodeExtSize(MCInst *Inst, |
|
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder) |
|
{ |
|
int Size = (int) Insn + 1; |
|
MCInst_addOperand(Inst, MCOperand_CreateImm(SignExtend32(Size, 16))); |
|
return MCDisassembler_Success; |
|
}
|
|
|