Josh
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90eb5ff592
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- Fixed memory leak for cython disasm functions
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10 years ago |
Nguyen Anh Quynh
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f2157deacc
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arm: in Thumb mode, ADC & SBC do not update flags. bug reported by @jabba2989
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10 years ago |
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Nguyen Anh Quynh
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67fe1c2547
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arm: in Thumb mode, ADC & SBC do not update flags. bug reported by @jabba2989
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10 years ago |
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Nguyen Anh Quynh
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42d11f7dd3
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python: fix test_arm.py
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10 years ago |
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Nguyen Anh Quynh
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911990671f
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arm64 & sparc: fix some warnings reported by MSVC
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10 years ago |
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Nguyen Anh Quynh
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ea39692786
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suite: fix an compilation warning reported by MSVC on test_arm_regression.c
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10 years ago |
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Nguyen Anh Quynh
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e95a76611c
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x86: remove some instructions unsupported in 3.x version
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10 years ago |
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Nguyen Anh Quynh
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273c6f4a9e
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arm64 & sparc: fix some warnings reported by MSVC
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10 years ago |
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Nguyen Anh Quynh
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9a1238d353
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suite: fix an compilation warning reported by MSVC on test_arm_regression.c
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10 years ago |
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Nguyen Anh Quynh
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25525fb20c
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x86: remove some instructions irrelevant for LOCK prefix in invalidPrefix()
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10 years ago |
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Nguyen Anh Quynh
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08482e106d
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x86: remove some instructions irrelevant for LOCK prefix in invalidPrefix()
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10 years ago |
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Nguyen Anh Quynh
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7de172d6ec
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x86: properly handle REP, REPNE & REPNZ prefixes
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10 years ago |
Andrew Wesie
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29f41da4c2
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x86: add more valid instructions for LOCK prefix
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10 years ago |
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Nguyen Anh Quynh
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5323128ed2
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x86: check for invalid instructions with LOCK prefix
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10 years ago |
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Nguyen Anh Quynh
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b3e26fdaa6
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x86: add prefix constant REPE
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10 years ago |
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Nguyen Anh Quynh
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a176ba4447
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x86: properly handle REP, REPNE & REPNZ prefixes
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10 years ago |
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Nguyen Anh Quynh
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18dfc1929d
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Merge branch 'v3' of https://github.com/aquynh/capstone into v3
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10 years ago |
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Nguyen Anh Quynh
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0c30daf749
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arm64: BL & BLR do not read SP register
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10 years ago |
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Nguyen Anh Quynh
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c6cf01c256
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arm64: BL & BLR do not read SP register
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10 years ago |
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Nguyen Anh Quynh
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993e031795
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java & ocaml: update these bindings following the addition of lshift field to arm_op_mem of Arm engine
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10 years ago |
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Nguyen Anh Quynh
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6c34c6659b
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tests: update test_arm.c to add a sample reflecting the addition of lshift field on arm_op_mem
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10 years ago |
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Nguyen Anh Quynh
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2951e640a4
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Merge branch 'next' of https://github.com/aquynh/capstone into next
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10 years ago |
|
Nguyen Anh Quynh
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590b1de14b
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python: update Python binding for ARM after the latest change in the core
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10 years ago |
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Nguyen Anh Quynh
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706b808af3
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arm: add lshift field to arm_op_mem to provide left-shift value for index register in some memory op. issue reported by @jabba2989
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10 years ago |
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Nguyen Anh Quynh
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78d640045c
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cython: fix incomplete array of bytes returned by CsInsn.bytes. bug reported by @secretsquirrel
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10 years ago |
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Nguyen Anh Quynh
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4de9de683d
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cython: fix incomplete array of bytes returned by CsInsn.bytes. bug reported by @secretsquirrel
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10 years ago |
|
Nguyen Anh Quynh
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499f0ca7cb
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suite: add some tools to verify X86 machine code
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10 years ago |
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Nguyen Anh Quynh
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0653c4edb1
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Merge pull request #245 from awesie/next
x86: add more valid instructions for LOCK prefix
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10 years ago |
|
Andrew Wesie
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5de09479a6
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x86: add more valid instructions for LOCK prefix
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10 years ago |
|
Nguyen Anh Quynh
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beb3248c26
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x86: check for invalid instructions with LOCK prefix
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10 years ago |
|
Nguyen Anh Quynh
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4539ba3088
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x86: support MOVSXD64rm with missing REX byte. bug reported by Aurélien Wailly
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10 years ago |
|
Nguyen Anh Quynh
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599b559455
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x86: fix some compilation issues about missing instructions on CAPSTONE_X86_REDUCE setup
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10 years ago |
Maciej Szawlowski
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2c24d88f89
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fixed bug that prevented using md.detail = true and md.skipdata = true together
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10 years ago |
|
Nguyen Anh Quynh
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dc101c25b3
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Merge branch 'master' of https://github.com/mszawlow/capstone into next
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10 years ago |
|
Maciej Szawlowski
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9b0221f229
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fixed bug that prevented using md.detail = true and md.skipdata = true together
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10 years ago |
|
Nguyen Anh Quynh
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3c27827a25
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x86: handle 0x82 opcode for CAPSTONE_X86_REDUCE setup
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10 years ago |
|
Nguyen Anh Quynh
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3410b63a4e
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x86: handle 0x82 opcode. bug reported by Anton Kochkov
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10 years ago |
derrek
|
07526e989b
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arm: Thumb BL & BLX read ARM_REG_PC instead of ARM_REG_SP.
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10 years ago |
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Nguyen Anh Quynh
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828667f3b3
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Merge pull request #240 from derrekr/next
arm: Thumb BL & BLX read ARM_REG_PC instead of ARM_REG_SP.
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10 years ago |
|
derrek
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bda2c1c591
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arm: Thumb BL & BLX read ARM_REG_PC instead of ARM_REG_SP.
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10 years ago |
|
Nguyen Anh Quynh
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c51e04fa97
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x86: support CR9-CR15 registers
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10 years ago |
|
Nguyen Anh Quynh
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08390775b5
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x86: support CR9-CR15 registers
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10 years ago |
|
Nguyen Anh Quynh
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db684b2398
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arm: BL & BLX do not read SP, but PC register. issue reported by Der Rek
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10 years ago |
|
Nguyen Anh Quynh
|
0f9ef1559d
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arm: BL & BLX do not read SP, but PC register. issue reported by Der Rek
|
10 years ago |
|
Nguyen Anh Quynh
|
61ab00718a
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x86: remove dead code & dead SSE_CC constants. issue reported by Coverity
|
10 years ago |
|
Nguyen Anh Quynh
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1038fdb038
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x86: add new registers DR8-DR15
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10 years ago |
|
Nguyen Anh Quynh
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59c72afe7a
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x86: add 3 new undocumented instructions fdisi8087_nop, feni8087_nop & ffreep
|
10 years ago |
|
Nguyen Anh Quynh
|
534b948661
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bump version to 4.0
|
10 years ago |
|
Nguyen Anh Quynh
|
7ca66a4982
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bump package version to 3.0.1
|
10 years ago |
|
Nguyen Anh Quynh
|
9f694cc934
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x86: handle undocumented immediates for (v)cmpps/pd/ss/sd instructions
|
10 years ago |
