Guillaume Jeanne
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e2cb91d866
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ocaml: update reg/inst/group const in arm
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10 years ago |
|
Guillaume Jeanne
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d157775c20
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ocaml: update reg/inst/group const in arm64
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10 years ago |
Nguyen Anh Quynh
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7178cd0e6f
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Merge branch 'next' into opsize
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10 years ago |
|
Nguyen Anh Quynh
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078f833da7
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update CREDITS.TXT
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10 years ago |
|
Nguyen Anh Quynh
|
28b1f49b39
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ocaml: update README
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10 years ago |
|
Nguyen Anh Quynh
|
a3676e31b5
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update .gitignore for Ocaml binding
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10 years ago |
|
Guillaume Jeanne
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cece24e426
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working OCaml bindings
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10 years ago |
|
Nguyen Anh Quynh
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1a66fecdbc
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x86: support avx_sae & avx_rm in cs_x86 struct. this also updates Python & Java bindings following the core's change
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10 years ago |
|
Nguyen Anh Quynh
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7de200afee
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python & java: update after the last change in the core on avx_zero_opmask
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10 years ago |
|
Nguyen Anh Quynh
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12e6e31389
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x86: rename zero_opmask of cs_x86_op to avx_zero_opmask
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10 years ago |
|
Nguyen Anh Quynh
|
2b338ce65a
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x86: update some comments on x86.h
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10 years ago |
|
Nguyen Anh Quynh
|
92a3d4c079
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x86: add AVX's zero_opmask to cs_x86_op struct. updated Python & Java bindings for this change
|
10 years ago |
|
Nguyen Anh Quynh
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f1ec52628e
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x86: provide size for X86_OP_IMM operand. thank Gabriel Quadros for some suggestions
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10 years ago |
|
Nguyen Anh Quynh
|
e1aba1703f
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x86: fix all {cc} instructions to have correct instruction ID
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10 years ago |
|
Nguyen Anh Quynh
|
4c5eabc32b
|
x86: support SSE_CC & AVX_CC in cs_x86 struct. this also updates Python & Java bindings
|
10 years ago |
|
Nguyen Anh Quynh
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0de6783d49
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python: print instruction's basic info from print_detail() of test_detail.py
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10 years ago |
|
Nguyen Anh Quynh
|
0d716450fc
|
x86: add avx_bcast to cs_x86_op to support AVX512 instructions. this also updates Python & Java binding
|
10 years ago |
|
Nguyen Anh Quynh
|
eeb06902ed
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java: update X86 after the last change in the core
|
10 years ago |
|
Nguyen Anh Quynh
|
bb6440c5ef
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x86: extend cs_x86.opcode to 4 bytes to contain EVEX opcode. this also updates Python binding following this interface change
|
10 years ago |
|
Nguyen Anh Quynh
|
15b746fe4f
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x86: op_addReg() & op_addImm() only work when detail mode is ON
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10 years ago |
|
Nguyen Anh Quynh
|
c74ec28691
|
x86: LEA for 16bit register should have pointer size of word, not dword. bug reported by Gabriel Quadros
|
10 years ago |
|
Nguyen Anh Quynh
|
d29aa6235a
|
x86: correct comments on x86_op_mem.scale
|
10 years ago |
|
Nguyen Anh Quynh
|
0467842205
|
java: update X86 binding after the last update in the core
|
10 years ago |
|
Nguyen Anh Quynh
|
14ba46bfab
|
x86: add segment to x86_op_mem struct. this fixes a bug in generating detail for instructions with segment override. bug reported by Sean Heelan.
|
10 years ago |
|
Nguyen Anh Quynh
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d948dd42b8
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tests/test_x86: prefix[] size is now 4, not 5
|
10 years ago |
|
Nguyen Anh Quynh
|
f3a9659cd5
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python & java: update x86 following the last update in core
|
10 years ago |
|
Nguyen Anh Quynh
|
fb15221666
|
x86: cs_x86.prefix[] should have size 4, not 5
|
10 years ago |
|
Nguyen Anh Quynh
|
eb2f3fb85a
|
x86: properly reset prefixPresent for prefix0/1 group
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10 years ago |
|
Nguyen Anh Quynh
|
5a7f409dec
|
set @insn to NULL on error in cs_disasm_ex()
|
10 years ago |
|
Nguyen Anh Quynh
|
dab17fd0b1
|
set @insn to NULL on error in cs_disasm_ex()
|
10 years ago |
|
Nguyen Anh Quynh
|
11bb56f04d
|
Merge branch 'opsize' of https://github.com/aquynh/capstone into opsize
|
10 years ago |
|
Nguyen Anh Quynh
|
369ecf66f6
|
Merge branch 'next' into opsize
|
10 years ago |
|
Nguyen Anh Quynh
|
6c182aedcf
|
fix a memleaking issue in cs_disasm_ex() where memory was not freed when input code is illegit
|
10 years ago |
|
Nguyen Anh Quynh
|
09132bf5d6
|
Merge branch 'next' into opsize
|
10 years ago |
|
Nguyen Anh Quynh
|
cb6fc59da1
|
remove redundant return in MCInst_Init()
|
10 years ago |
|
Nguyen Anh Quynh
|
1e688d4ff9
|
x86: do not use markup in AT&T syntax
|
10 years ago |
|
Nguyen Anh Quynh
|
46291c139f
|
Merge branch 'next' into opsize
|
10 years ago |
|
Nguyen Anh Quynh
|
83800cdc31
|
python & java: add comments on operand's size
|
10 years ago |
|
Nguyen Anh Quynh
|
44db3c37fa
|
x86: support CS_OPT_MODE for dynamically changing mode at run-time
|
10 years ago |
|
Nguyen Anh Quynh
|
cff03629ac
|
arm64: assign NULL to char pointer, not zero. bug reported by Coverity
|
10 years ago |
|
Nguyen Anh Quynh
|
e68ce0ecc8
|
java: update after the last change in x86 core
|
10 years ago |
|
Nguyen Anh Quynh
|
e792451cce
|
python: update after the last change in x86 core
|
10 years ago |
|
Nguyen Anh Quynh
|
1085073f8f
|
x86: remove disp_size, imm_size, op_size. add size to each operand. thanks Gabriel Quadros for some nice ideas
|
10 years ago |
|
Nguyen Anh Quynh
|
7ae389ede8
|
suite: support XCore in fuzz.py
|
10 years ago |
|
Nguyen Anh Quynh
|
6a5cc570cc
|
suite: support XCore in benchmark.py
|
10 years ago |
|
Nguyen Anh Quynh
|
73eb5d5486
|
arm: op_addImm() is called only when detail mode is ON
|
10 years ago |
|
Nguyen Anh Quynh
|
b287301ef4
|
bump number of operands supported by MCInst to 48. this fixes a segfault in ARM
|
10 years ago |
|
Nguyen Anh Quynh
|
476d5ad7a5
|
msvc: disable warning on strcpy()
|
10 years ago |
|
Nguyen Anh Quynh
|
cae09bf543
|
replace offset_of with offsetof from stddef.h
|
10 years ago |
|
Nguyen Anh Quynh
|
4fe59955d6
|
python: test_detail.py print groups with space delimiter
|
10 years ago |
