Nguyen Anh Quynh
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f721e3124d
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Disassembler -> Disassembly
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11 years ago |
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Nguyen Anh Quynh
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8f50ba894c
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Merge branch 'next' into xcore
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11 years ago |
|
Nguyen Anh Quynh
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04f2ec6d0f
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cleanup redundant headers included
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11 years ago |
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Nguyen Anh Quynh
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2cf9c524da
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x86: MOV64rr belongs to GRP_MODE64 group. bug reported by Jason Oster
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11 years ago |
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Nguyen Anh Quynh
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d0f3e15d90
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python: fix Xcore bug
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11 years ago |
|
Nguyen Anh Quynh
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553bb488d7
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python: support XCore
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11 years ago |
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Nguyen Anh Quynh
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52a8d2afa2
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enable disabled archs
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11 years ago |
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Nguyen Anh Quynh
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c80d840ffc
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add XCore architecture
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11 years ago |
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Nguyen Anh Quynh
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3dc080c2b6
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systemz: cleanup SystemZGenDisassemblerTables.inc
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11 years ago |
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Nguyen Anh Quynh
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5a5d8a71cd
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python & java: fix Sparc's CC constants after the last change in the core
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11 years ago |
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Nguyen Anh Quynh
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5d6383e335
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sparc: SPARC_CC_ICC_N should not have the same value as SPARC_CC_INVALID. bug reported by Jason Oster
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11 years ago |
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Nguyen Anh Quynh
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708d151fb6
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Merge pull request #127 from parasyte/bug/SystemZ/r0l-reg
Add `r0l` register to SystemZMapping.c
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11 years ago |
Jason Oster
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6380446222
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Add `r0l` register to SystemZMapping.c
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11 years ago |
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Nguyen Anh Quynh
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0ebbf1e49c
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python: ArmOpValue.imm uses int32 type after the last change in the core
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11 years ago |
|
Nguyen Anh Quynh
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eddf47c712
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Merge pull request #125 from parasyte/ticket-124
ARM: Make `imm` detail field signed.
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11 years ago |
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Jason Oster
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aa60b8cd1b
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[#124] ARM: Make `imm` detail field signed.
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11 years ago |
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Nguyen Anh Quynh
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e96e34df9a
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python: test_x86.py print prefixes with a space between consecutive bytes
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11 years ago |
|
Nguyen Anh Quynh
|
4ebd062ee3
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x86: cleanup unused code
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11 years ago |
|
Nguyen Anh Quynh
|
fed098f9a7
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x86: eliminate irrelevant prefixes in x86.prefix[] - such as f2/f3 prefixed irrelevant instructions
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11 years ago |
|
Nguyen Anh Quynh
|
1e93adf5c3
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x86: add CL operand into details for 'SHL *, CL' instruction
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11 years ago |
|
Nguyen Anh Quynh
|
7a65ad7e4b
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x86: detail operands for 'fstpnce st(0), st(0)' & 'fstpst(7), st(0)'
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11 years ago |
|
Nguyen Anh Quynh
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b6e3f01bb8
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x86: handle REP MOVSD/CMPSD/SCASD/LODSD/STOSD properly (due to confused 128bit media instructions having the same mnemonics)
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11 years ago |
|
Nguyen Anh Quynh
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3a86d92e7c
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x86: correct instructions related to REP prefix
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11 years ago |
|
Nguyen Anh Quynh
|
1d6f7ee50e
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x86: prefix REP/REPNE are only relevant for MOVS/CMPS/SCAS/LDOS/STOS/INS/OUTS instructions
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11 years ago |
|
Nguyen Anh Quynh
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7a75baa679
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Merge pull request #122 from parasyte/next
MIPS: Add HI, LO, and PC registers to MipsMapping.c
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11 years ago |
|
Jason Oster
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984ed7e9e8
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MIPS: Add HI, LO, and PC registers to MipsMapping.c
- Using MIPS_REG_HI, MIPS_REG_LO, and MIPS_REG_PC with cs_reg_name() caused out-of-bounds reads
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11 years ago |
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Nguyen Anh Quynh
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2c61656d99
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tests: correct the prototype of mycallback() in test_skipdata
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11 years ago |
danghvu
|
50fdc6c463
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Merge with upstream
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11 years ago |
|
danghvu
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69a7c2d580
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Make test_skipdata performs tests by default
|
11 years ago |
|
Nguyen Anh Quynh
|
7b91574257
|
TODO: remove Python3 & MSVC from wanted features
|
11 years ago |
|
Nguyen Anh Quynh
|
6f9b113009
|
update COMPILE_MSVC.TXT
|
11 years ago |
|
Nguyen Anh Quynh
|
6456481508
|
x86: add immediate operand (1) for SHL/SHR/ROR/ROL/SAR/SAL in detail mode & Intel syntax
|
11 years ago |
|
Nguyen Anh Quynh
|
f338657f17
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x86: set syntax variable when changing syntax with cs_option()
|
11 years ago |
|
Nguyen Anh Quynh
|
f260c2023e
|
fix some conflicts when merging msvc2 into next
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11 years ago |
|
Nguyen Anh Quynh
|
1922b2f74b
|
arm64: clean reg_name_maps[]
|
11 years ago |
|
Nguyen Anh Quynh
|
61882e56d5
|
msvc: update documentation for VS2010
|
11 years ago |
|
Nguyen Anh Quynh
|
96934501fd
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arm64: do not consider WZR & XZR alias registers
|
11 years ago |
|
Nguyen Anh Quynh
|
cb2c4f90bf
|
test_x86: output sib_base, sib_index, sib_scale separately
|
11 years ago |
|
Nguyen Anh Quynh
|
688efe3018
|
python: properly handle SIB's registers on irrelevant cases (zero value) of test_x86.py
|
11 years ago |
|
Nguyen Anh Quynh
|
1aa60d0921
|
python: handle invalid argument (zero) for reg_name() & insn_name() of class CsInsn
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11 years ago |
|
Nguyen Anh Quynh
|
1098329f40
|
python: refactor tests, so it is possible to reuse print_insn_detail() of all archs
|
11 years ago |
|
Nguyen Anh Quynh
|
fc3636a0b8
|
python: update test_all.py
|
11 years ago |
|
Nguyen Anh Quynh
|
7dcb1dd177
|
Merge branch 'test' into msvc2
|
11 years ago |
|
Nguyen Anh Quynh
|
015849db81
|
update .gitignore for VS2010
|
11 years ago |
|
Nguyen Anh Quynh
|
c3d0d22709
|
msvc: fix for VS2010
|
11 years ago |
|
Nguyen Anh Quynh
|
0273468003
|
msvc: support VS2010
|
11 years ago |
|
Nguyen Anh Quynh
|
bf7df4b91e
|
update CREDITS.TXT
|
11 years ago |
|
Nguyen Anh Quynh
|
cb5910627a
|
remove some more forgotten stdbool.h
|
11 years ago |
|
Nguyen Anh Quynh
|
c5cad6cab3
|
avoid using stdbool.h to support compilers without C99 support
|
11 years ago |
|
Nguyen Anh Quynh
|
e2d941672b
|
msvc: add inttypes.h for pre-VS2012 compiler (without C99 support)
|
11 years ago |
