5426fe0cec
arm64: change headerguard for AArch64AddressingModes.h
10 years ago
c44acedc79
x86: properly zero-out x86.operands[]
10 years ago
9be1f93f88
fixed warnings in MSVC x64 compilation
10 years ago
0693809980
fixed compile errors on visual studio (variable declarations in C have to be in the top of the function)
10 years ago
5df81b4ab9
fix a c99 warning
10 years ago
4b6b15fcb1
fix more MSVC warnings
10 years ago
07c92ec20a
fix warnings reported by MSVC
10 years ago
ed1234a892
xcore: update core
10 years ago
a7792ae488
systemz: update core. also update Python & Java bindings
10 years ago
14b684e07d
last commit missed a check
10 years ago
b1e87e3e31
arm, mips, ppc, spac, x86: printAliasInstr() should handle \t (besides space) as separate char between mnemonic & operands
10 years ago
8027adad6c
arm64: refine output of some instructions to make them match available test suites
10 years ago
62af137a81
arm64: printAliasInstr() should handle \t (besides space) as separate char between mnemonic & operands
10 years ago
46a74e53b7
arm64: update core. this added a lot more details to cs_arm64_op struct
10 years ago
ffb6b23c7d
x86: add SMAP group for CLAC/STAC instructions
10 years ago
663829431e
x86: return proper error if cs_option() enables AT&T syntax but AT&T support is opt-out at compile time
10 years ago
1ce5dea3e0
ppc: fix an unused variable warning
10 years ago
b7e2ff451f
x86.operands array wasn't fully cleared
10 years ago
86e845056d
renamed CAPSTONE_NO_ATT to CAPSTONE_X86_ATT_DISABLE, added options to makefile, cmake, compile.txt
10 years ago
4f412c4483
Selectively disable AT&T syntax in non-diet mode to reduce library size
10 years ago
a726402513
sparc: update core. this added/removed some instructions & groups. updated Python & Java bindings accordingly
10 years ago
2124b8a9c9
mips: indentations
10 years ago
159ddbd99f
ppc: add new groups to group_name_maps[]
10 years ago
64f36d9759
change '2013>' to 2013-2014
10 years ago
91a64776a8
ppc: fix a mistake on interpreting CR registers by deleting CR8 -> CR31
10 years ago
dd3deec1e9
ppc: update core. this added new instructions, groups & registers. updated Python & Java bindings accordingly
10 years ago
0f0eb9851a
mips: update core. this added bunch of new instructions & groups. updated Python & Java bindings accordingly
10 years ago
7c089fd6c6
arm: add new mode CS_MODE_MCLASS for Cortex-M series. updated Python & Java bindings accordingly
10 years ago
b52f11f636
arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly
10 years ago
0b690387b3
x86: update core with upstream. this added bunch of new instructions & groups. also updated Python & Java bindings after the core change
10 years ago
4db4d9bdd7
xcore: fix an warning of unused array when DIET mode is enable
10 years ago
590f23af54
arm: do not need to initialize local variable opcode in DecodeRegListOperand()
10 years ago
0c235e15ab
arm: some simple improvements & cleanups
10 years ago
26dfbc6677
fix indentation introduced by the latest merge. also move test_arm_regression.c into suite/arm/ and add Makefile for it
10 years ago
48eb7a6614
x86: INTO is invalid in 64bit mode. bug reported by Pancake & Ange Albertini
10 years ago
298d413bbc
* added a test file to suite for testing invalid and valid instruction sequences
...
* fixed and added a test for a thumb-2 invalid sequence that was incorrectly allowed before these changes (pop.w with sp argument included)
* fixed and added a test for a blx from thumb to ARM that had its immediate argument incorrect (misaligned)
* eliminated some warnings by explicitly casting so I could turn on
treat warnings as errors locally
General notes:
* probably worth turning on treat all warnings as errors in the msvc project files, had a subtle bug that resulted from a missing declaration causing differences in dll and static compilation modes
( code was working incorrectly in dll form because of missing declaration in arch/ARM/ARMMapping.h for new function ARM_blx_to_arm_mode. Something about the linking was confusing ld when making the dll, and the resulting offsets were wonky (e.g. the added ble test would show up as #0x1fc instead of #0x1fe like it should have )
* the invalid pop was being treated as a soft fail which then gets coerced
to a success because it is != MCDisassembler_Fail in Thumb_getInstruction
what are the semantics of a soft fail? Maybe we should be able to set up
whether or not we want a soft fail to be a real fail in the csh struct?
10 years ago
55cd996add
sparc: initialize detail->sparc in Sparc_getInstruction. bug reported by Ben Nagy
11 years ago
e1fc8a83ba
sparc: initialize detail->sparc in Sparc_getInstruction. bug reported by Ben Nagy
11 years ago
4d2eba7f43
systemz: initialize detail->sysz in SystemZ_getInstruction. bug reported by Ben Nagy
11 years ago
39d6b2f066
systemz: initialize detail->sysz in SystemZ_getInstruction. bug reported by Ben Nagy
11 years ago
650f96ce43
add new API cs_group_name() to return group name in string, given the group id
11 years ago
bb8bbaa930
x86: test reg, [mem] -> test [mem], reg. bug reported by Gabriel Quadros
11 years ago
dbdb61a9cf
x86: regs_write[] of RDTSC & RDTSCP depend on @mode
11 years ago
9f6ed7155a
x86: add @rex to cs_x86 struct. updated python & java binding for this change
11 years ago
32e2c6c9c7
x86: address-size prefix should override RIP relative address in x64 mode. bug reported by @hlide
11 years ago
ed6b8c5a96
x86: address-size prefix should override RIP relative address in x64 mode. bug reported by @hlide
11 years ago
656ebc9625
x86: handle RIP relative addressing in 64bit mode properly. bug reported by @hlide
11 years ago
af6db2afe8
x86: handle RIP relative addressing in 64bit mode properly. bug reported by @hlide
11 years ago
7ef3700550
x86: SHL reg, 1 has one too many operands. bug reported by Sean Heelan
11 years ago
1a66fecdbc
x86: support avx_sae & avx_rm in cs_x86 struct. this also updates Python & Java bindings following the core's change
11 years ago
Nguyen Anh Quynh
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