Nguyen Anh Quynh
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10434df006
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arm: some instructions update status flags in insns_ops[]
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10 years ago |
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Nguyen Anh Quynh
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760c5486d2
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arm: fix some more Thumb & vectored instructions in insn_ops[]
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10 years ago |
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Nguyen Anh Quynh
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cea230f867
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arm: fix some Thumb instructions in insn_ops[]
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10 years ago |
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Nguyen Anh Quynh
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d0f96df26d
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arm: add insn_ops[] (temporarily disable)
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10 years ago |
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Nguyen Anh Quynh
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e8eb536346
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arm64: add place holder for insn_ops[]
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10 years ago |
pzread
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ced9a6ed92
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Correct printAM3PreOrOffsetIndexOp disp value
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10 years ago |
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pzread
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ec95020fa0
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Remove incorrect ITBlock.size = 0
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10 years ago |
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Nguyen Anh Quynh
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e3bcbdb2fa
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x86: REPNE can go with STOS/MOVS. bug reported by Gabriel Quadros
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10 years ago |
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Nguyen Anh Quynh
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dfa396e6ff
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x86: add the missing X86 instructions in X86_REDUCE mode in X86DisassemblerDecoder.c. bug reported by Julian Stecklina
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10 years ago |
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Nguyen Anh Quynh
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4363911eb4
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x86: fix operand size for 'CALL PTR [REG]'. bug reported by Gabriel Quadros
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10 years ago |
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Nguyen Anh Quynh
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7ea921e539
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x86: add work-in-progress mapping table on explicit operands access. this reused some code contributed by Vincent Bénony
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10 years ago |
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Nguyen Anh Quynh
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9426ad572f
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arm: add few more post-indexed instructions doing writeback
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10 years ago |
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Nguyen Anh Quynh
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7bbb4336a8
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arm: fix a bug in the last commit
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10 years ago |
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Nguyen Anh Quynh
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e19490e8f7
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arm: some load/store instructions writeback without bang letter. bug reported by @jabba2989
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10 years ago |
|
Nguyen Anh Quynh
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58fbf2f627
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arm: add few more post-indexed instructions doing writeback
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10 years ago |
|
Nguyen Anh Quynh
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5719eb5a9d
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arm: fix a bug in the last commit
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10 years ago |
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Nguyen Anh Quynh
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03e5e106b0
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arm: some load/store instructions writeback without bang letter. bug reported by @jabba2989
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10 years ago |
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Nguyen Anh Quynh
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f2157deacc
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arm: in Thumb mode, ADC & SBC do not update flags. bug reported by @jabba2989
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10 years ago |
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Nguyen Anh Quynh
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67fe1c2547
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arm: in Thumb mode, ADC & SBC do not update flags. bug reported by @jabba2989
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10 years ago |
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Nguyen Anh Quynh
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911990671f
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arm64 & sparc: fix some warnings reported by MSVC
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10 years ago |
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Nguyen Anh Quynh
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e95a76611c
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x86: remove some instructions unsupported in 3.x version
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10 years ago |
|
Nguyen Anh Quynh
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273c6f4a9e
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arm64 & sparc: fix some warnings reported by MSVC
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10 years ago |
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Nguyen Anh Quynh
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25525fb20c
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x86: remove some instructions irrelevant for LOCK prefix in invalidPrefix()
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10 years ago |
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Nguyen Anh Quynh
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08482e106d
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x86: remove some instructions irrelevant for LOCK prefix in invalidPrefix()
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10 years ago |
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Nguyen Anh Quynh
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7de172d6ec
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x86: properly handle REP, REPNE & REPNZ prefixes
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10 years ago |
Andrew Wesie
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29f41da4c2
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x86: add more valid instructions for LOCK prefix
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10 years ago |
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Nguyen Anh Quynh
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5323128ed2
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x86: check for invalid instructions with LOCK prefix
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10 years ago |
|
Nguyen Anh Quynh
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a176ba4447
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x86: properly handle REP, REPNE & REPNZ prefixes
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10 years ago |
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Nguyen Anh Quynh
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0c30daf749
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arm64: BL & BLR do not read SP register
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10 years ago |
|
Nguyen Anh Quynh
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c6cf01c256
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arm64: BL & BLR do not read SP register
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10 years ago |
|
Nguyen Anh Quynh
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706b808af3
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arm: add lshift field to arm_op_mem to provide left-shift value for index register in some memory op. issue reported by @jabba2989
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10 years ago |
|
Andrew Wesie
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5de09479a6
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x86: add more valid instructions for LOCK prefix
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10 years ago |
|
Nguyen Anh Quynh
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beb3248c26
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x86: check for invalid instructions with LOCK prefix
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10 years ago |
|
Nguyen Anh Quynh
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4539ba3088
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x86: support MOVSXD64rm with missing REX byte. bug reported by Aurélien Wailly
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10 years ago |
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Nguyen Anh Quynh
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599b559455
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x86: fix some compilation issues about missing instructions on CAPSTONE_X86_REDUCE setup
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10 years ago |
|
Nguyen Anh Quynh
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3c27827a25
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x86: handle 0x82 opcode for CAPSTONE_X86_REDUCE setup
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10 years ago |
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Nguyen Anh Quynh
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3410b63a4e
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x86: handle 0x82 opcode. bug reported by Anton Kochkov
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10 years ago |
derrek
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07526e989b
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arm: Thumb BL & BLX read ARM_REG_PC instead of ARM_REG_SP.
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10 years ago |
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derrek
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bda2c1c591
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arm: Thumb BL & BLX read ARM_REG_PC instead of ARM_REG_SP.
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10 years ago |
|
Nguyen Anh Quynh
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c51e04fa97
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x86: support CR9-CR15 registers
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10 years ago |
|
Nguyen Anh Quynh
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08390775b5
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x86: support CR9-CR15 registers
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10 years ago |
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Nguyen Anh Quynh
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db684b2398
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arm: BL & BLX do not read SP, but PC register. issue reported by Der Rek
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10 years ago |
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Nguyen Anh Quynh
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0f9ef1559d
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arm: BL & BLX do not read SP, but PC register. issue reported by Der Rek
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10 years ago |
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Nguyen Anh Quynh
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61ab00718a
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x86: remove dead code & dead SSE_CC constants. issue reported by Coverity
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10 years ago |
|
Nguyen Anh Quynh
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1038fdb038
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x86: add new registers DR8-DR15
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10 years ago |
|
Nguyen Anh Quynh
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59c72afe7a
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x86: add 3 new undocumented instructions fdisi8087_nop, feni8087_nop & ffreep
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10 years ago |
|
Nguyen Anh Quynh
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9f694cc934
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x86: handle undocumented immediates for (v)cmpps/pd/ss/sd instructions
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10 years ago |
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Nguyen Anh Quynh
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d319c114db
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x86: more encodings for FXCH & FCOMP. also print LJUMP without * as prefix for Intel syntax. handle BOUND & FARCALL better
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10 years ago |
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Nguyen Anh Quynh
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5f8c4239c2
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x86: add missing CR8-CR15 registers to arch/X86/X86DisassemblerDecoder.h
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10 years ago |
|
Nguyen Anh Quynh
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2ac7941227
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x86: handle REX properly for segment related instructions by ignoring REX.r entirely
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10 years ago |
