Merge remote-tracking branch 'upstream/next' into next

arch/M68K/M68KDisassembler.c

@@ -983,19 +983,21 @@ static void build_cas2(m68k_info *info, int size)
 
 	op0->address_mode = M68K_AM_NONE;
 	op0->type = M68K_OP_REG_PAIR;
-	op0->register_bits = (((extension >> 16) & 7) << 4) | (extension & 7);
+	op0->reg_pair.reg_0 = (extension >> 16) & 7;
+	op0->reg_pair.reg_1 = extension & 7;
 
 	op1->address_mode = M68K_AM_NONE;
 	op1->type = M68K_OP_REG_PAIR;
-	op1->register_bits = (((extension >> 22) & 7) << 4) | ((extension >> 6) & 7);
+	op1->reg_pair.reg_0 = (extension >> 22) & 7;
+	op1->reg_pair.reg_1 = (extension >> 6) & 7;
 
 	reg_0 = (extension >> 28) & 7;
 	reg_1 = (extension >> 12) & 7;
 
 	op2->address_mode = M68K_AM_NONE;
 	op2->type = M68K_OP_REG_PAIR;
-	op2->register_bits = ((reg_0 + (BIT_1F(extension) ? 8 : 0)) << 4) |
-		(reg_1 + (BIT_F(extension) ? 8 : 0));
+	op2->reg_pair.reg_0 = reg_0 + (BIT_1F(extension) ? 8 : 0);
+	op2->reg_pair.reg_1 = reg_1 + (BIT_F(extension) ? 8 : 0);
 }
 
 static void build_chk2_cmp2(m68k_info *info, int size)
@@ -2081,12 +2083,14 @@ static void d68020_cpgen(m68k_info *info)
 				ext->op_size.type = M68K_SIZE_TYPE_FPU;
 				ext->op_size.fpu_size = M68K_FPU_SIZE_SINGLE;
 				get_ea_mode_op(info, op0, info->ir, 4);
+				op0->type = M68K_OP_FP_SINGLE;
 				break;
 
 			case 0x05:
 				ext->op_size.type = M68K_SIZE_TYPE_FPU;
 				ext->op_size.fpu_size = M68K_FPU_SIZE_DOUBLE;
 				get_ea_mode_op(info, op0, info->ir, 8);
+				op0->type = M68K_OP_FP_DOUBLE;
 				break;
 
 			default :
@@ -2248,7 +2252,8 @@ static void d68020_divl(m68k_info *info)
 
 	op1->address_mode = M68K_AM_NONE;
 	op1->type = M68K_OP_REG_PAIR;
-	op1->register_bits = (reg_0 << 4) | reg_1;
+	op1->reg_pair.reg_0 = reg_0;
+	op1->reg_pair.reg_1 = reg_1;
 
 	if ((reg_0 == reg_1) || !BIT_A(extension)) {
 		op1->type = M68K_OP_REG;
@@ -2793,7 +2798,8 @@ static void d68020_mull(m68k_info *info)
 
 	op1->address_mode = M68K_AM_NONE;
 	op1->type = M68K_OP_REG_PAIR;
-	op1->register_bits = (reg_0 << 4) | reg_1;
+	op1->reg_pair.reg_0 = reg_0;
+	op1->reg_pair.reg_1 = reg_1;
 
 	if (!BIT_A(extension)) {
 		op1->type = M68K_OP_REG;

arch/M68K/M68KInstPrinter.c

@@ -113,8 +113,8 @@ static void registerBits(SStream* O, const cs_m68k_op* op)
 
 static void registerPair(SStream* O, const cs_m68k_op* op)
 {
-	SStream_concat(O, "%s:%s", s_reg_names[M68K_REG_D0 + (op->register_bits >> 4)],
-			s_reg_names[M68K_REG_D0 + (op->register_bits & 0xf)]);
+	SStream_concat(O, "%s:%s", s_reg_names[M68K_REG_D0 + op->reg_pair.reg_0],
+			s_reg_names[M68K_REG_D0 + op->reg_pair.reg_1]);
 }
 
 void printAddressingMode(SStream* O, const cs_m68k* inst, const cs_m68k_op* op)

bindings/java/capstone/M68k_const.java

@@ -83,9 +83,10 @@ public class M68k_const {
 	public static final int M68K_OP_REG = 1;
 	public static final int M68K_OP_IMM = 2;
 	public static final int M68K_OP_MEM = 3;
-	public static final int M68K_OP_FP = 4;
-	public static final int M68K_OP_REG_BITS = 5;
-	public static final int M68K_OP_REG_PAIR = 6;
+	public static final int M68K_OP_FP_SINGLE = 4;
+	public static final int M68K_OP_FP_DOUBLE = 5;
+	public static final int M68K_OP_REG_BITS = 6;
+	public static final int M68K_OP_REG_PAIR = 7;
 
 	public static final int M68K_CPU_SIZE_NONE = 0;
 	public static final int M68K_CPU_SIZE_BYTE = 1;

bindings/ocaml/m68k_const.ml

@@ -80,9 +80,10 @@ let _M68K_OP_INVALID = 0;;
 let _M68K_OP_REG = 1;;
 let _M68K_OP_IMM = 2;;
 let _M68K_OP_MEM = 3;;
-let _M68K_OP_FP = 4;;
-let _M68K_OP_REG_BITS = 5;;
-let _M68K_OP_REG_PAIR = 6;;
+let _M68K_OP_FP_SINGLE = 4;;
+let _M68K_OP_FP_DOUBLE = 5;;
+let _M68K_OP_REG_BITS = 6;;
+let _M68K_OP_REG_PAIR = 7;;
 
 let _M68K_CPU_SIZE_NONE = 0;;
 let _M68K_CPU_SIZE_BYTE = 1;;

bindings/python/capstone/m68k.py

@@ -19,12 +19,19 @@ class M68KOpMem(ctypes.Structure):
         ('index_size', ctypes.c_ubyte),
     )
 
+class M68KOpRegPair(ctypes.Structure):
+    _fields_ = (
+        ('reg_0', ctypes.c_uint),
+        ('reg_1', ctypes.c_uint),
+    )
+
 class M68KOpValue(ctypes.Union):
     _fields_ = (
         ('imm', ctypes.c_int64),
         ('dimm', ctypes.c_double),
         ('simm', ctypes.c_float),
         ('reg', ctypes.c_uint),
+        ('reg_pair', M68KOpRegPair),
         ('mem', M68KOpMem),
         ('register_bits', ctypes.c_uint),
     )

bindings/python/capstone/m68k_const.py

@@ -80,9 +80,10 @@ M68K_OP_INVALID = 0
 M68K_OP_REG = 1
 M68K_OP_IMM = 2
 M68K_OP_MEM = 3
-M68K_OP_FP = 4
-M68K_OP_REG_BITS = 5
-M68K_OP_REG_PAIR = 6
+M68K_OP_FP_SINGLE = 4
+M68K_OP_FP_DOUBLE = 5
+M68K_OP_REG_BITS = 6
+M68K_OP_REG_PAIR = 7
 
 M68K_CPU_SIZE_NONE = 0
 M68K_CPU_SIZE_BYTE = 1

include/capstone/m68k.h

@@ -112,7 +112,8 @@ typedef enum m68k_op_type {
 	M68K_OP_REG,         // = CS_OP_REG (Register operand).
 	M68K_OP_IMM,         // = CS_OP_IMM (Immediate operand).
 	M68K_OP_MEM,         // = CS_OP_MEM (Memory operand).
-	M68K_OP_FP,          // = CS_OP_FP  (Floating-Point operand)
+	M68K_OP_FP_SINGLE,   // single precision Floating-Point operand
+	M68K_OP_FP_DOUBLE,   // double precision Floating-Point operand
 	M68K_OP_REG_BITS,    // Register bits move
 	M68K_OP_REG_PAIR,    // Register pair in the same op (upper 4 bits for first reg, lower for second) 
 } m68k_op_type;
@@ -140,8 +141,12 @@ typedef struct cs_m68k_op {
 		double dimm; 		    // double imm
 		float simm; 		    // float imm
 		m68k_reg reg;		    // register value for REG operand
+		struct {		    // register pair in one operand
+			m68k_reg reg_0;
+			m68k_reg reg_1;
+		} reg_pair;
 		m68k_op_mem mem; 	    // data when operand is targeting memory
-		uint32_t register_bits; // register bits for movem/cas2/etc (always in d0-d7, a0-a7, fp0 - fp7 order)
+		uint32_t register_bits; // register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order)
 	};
 	m68k_op_type type;
 	m68k_address_mode address_mode;	// M68K addressing mode for this op

tests/test_arm.c

@@ -62,10 +62,10 @@ static void print_insn_detail(csh cs_handle, cs_insn *ins)
 				break;
 			case ARM_OP_MEM:
 				printf("\t\toperands[%u].type: MEM\n", i);
-				if (op->mem.base != X86_REG_INVALID)
+				if (op->mem.base != ARM_REG_INVALID)
 					printf("\t\t\toperands[%u].mem.base: REG = %s\n",
 							i, cs_reg_name(cs_handle, op->mem.base));
-				if (op->mem.index != X86_REG_INVALID)
+				if (op->mem.index != ARM_REG_INVALID)
 					printf("\t\t\toperands[%u].mem.index: REG = %s\n",
 							i, cs_reg_name(cs_handle, op->mem.index));
 				if (op->mem.scale != 1)

tests/test_mips.c

@@ -55,7 +55,7 @@ static void print_insn_detail(cs_insn *ins)
 				break;
 			case MIPS_OP_MEM:
 				printf("\t\toperands[%u].type: MEM\n", i);
-				if (op->mem.base != X86_REG_INVALID)
+				if (op->mem.base != MIPS_REG_INVALID)
 					printf("\t\t\toperands[%u].mem.base: REG = %s\n",
 							i, cs_reg_name(handle, op->mem.base));
 				if (op->mem.disp != 0)

tests/test_ppc.c

@@ -83,7 +83,7 @@ static void print_insn_detail(cs_insn *ins)
 				break;
 			case PPC_OP_MEM:
 				printf("\t\toperands[%u].type: MEM\n", i);
-				if (op->mem.base != X86_REG_INVALID)
+				if (op->mem.base != PPC_REG_INVALID)
 					printf("\t\t\toperands[%u].mem.base: REG = %s\n",
 							i, cs_reg_name(handle, op->mem.base));
 				if (op->mem.disp != 0)