From e3ecb0a82f8c8db1e7748be626428817317a4ec9 Mon Sep 17 00:00:00 2001 From: Nguyen Anh Quynh Date: Sat, 29 Mar 2014 17:26:51 +0800 Subject: [PATCH] x86: do not print memory offset in negative form. bug reported by Le Dinh Long --- arch/X86/X86ATTInstPrinter.c | 11 ++++------- arch/X86/X86IntelInstPrinter.c | 11 ++++------- arch/X86/X86Mapping.c | 10 ++++++++++ arch/X86/X86Mapping.h | 2 ++ 4 files changed, 20 insertions(+), 14 deletions(-) diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c index dc7c8532..c1eb5bc0 100644 --- a/arch/X86/X86ATTInstPrinter.c +++ b/arch/X86/X86ATTInstPrinter.c @@ -210,10 +210,7 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O) if (MI->csh->detail) MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = imm; if (imm < 0) { - if (imm < -HEX_THRESHOLD) - SStream_concat(O, "-0x%"PRIx64, -imm); - else - SStream_concat(O, "-%"PRIu64, -imm); + SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & imm); } else { if (imm > HEX_THRESHOLD) SStream_concat(O, "0x%"PRIx64, imm); @@ -373,7 +370,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) else SStream_concat(O, "%s$%"PRIu64"%s", markup("")); } else { - SStream_concat(O, "%s$0x%"PRIx64"%s", markup("x86_imm_size) - 1) & imm, markup(">")); + SStream_concat(O, "%s$0x%"PRIx64"%s", markup("x86_imm_size] & imm, markup(">")); } if (MI->csh->detail) { MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_IMM; @@ -393,7 +390,7 @@ static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O) // Print X86 immediates as signed values. int64_t imm = MCOperand_getImm(Op); if (imm < 0) { - SStream_concat(O, "%s$0x%"PRIx64"%s", markup("x86_imm_size) - 1) & imm, markup(">")); + SStream_concat(O, "%s$0x%"PRIx64"%s", markup("x86_imm_size] & imm, markup(">")); } else { if (imm > HEX_THRESHOLD) SStream_concat(O, "%s$0x%"PRIx64"%s", markup("")); @@ -432,7 +429,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O) MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = DispVal; if (DispVal || (!MCOperand_getReg(IndexReg) && !MCOperand_getReg(BaseReg))) { if (DispVal < 0) { - SStream_concat(O, "0x%"PRIx64, ((1L << (8*MI->csh->mode)) - 1) & DispVal); + SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal); } else { if (DispVal > HEX_THRESHOLD) SStream_concat(O, "0x%"PRIx64, DispVal); diff --git a/arch/X86/X86IntelInstPrinter.c b/arch/X86/X86IntelInstPrinter.c index 92a8950a..88b54db4 100644 --- a/arch/X86/X86IntelInstPrinter.c +++ b/arch/X86/X86IntelInstPrinter.c @@ -214,10 +214,7 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O) if (MI->csh->detail) MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = imm; if (imm < 0) { - if (imm < -HEX_THRESHOLD) - SStream_concat(O, "-0x%"PRIx64, -imm); - else - SStream_concat(O, "-%"PRIu64, -imm); + SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & imm); } else { if (imm > HEX_THRESHOLD) SStream_concat(O, "0x%"PRIx64, imm); @@ -416,7 +413,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) else SStream_concat(O, "%"PRIu64, imm); } else { - SStream_concat(O, "0x%"PRIx64, ((1 << 8*MI->x86_imm_size) - 1) & imm); + SStream_concat(O, "0x%"PRIx64, arch_masks[MI->x86_imm_size] & imm); } if (MI->csh->detail) { @@ -436,7 +433,7 @@ static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O) } else if (MCOperand_isImm(Op)) { int64_t imm = MCOperand_getImm(Op); if (imm < 0) { - SStream_concat(O, "0x%"PRIx64, ((1 << 8*MI->x86_imm_size) - 1) & imm); + SStream_concat(O, "0x%"PRIx64, arch_masks[MI->x86_imm_size] & imm); } else { if (imm > HEX_THRESHOLD) SStream_concat(O, "0x%"PRIx64, imm); @@ -497,7 +494,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O) } if (DispVal < 0) { - SStream_concat(O, "0x%"PRIx64, ((1L << (8*MI->csh->mode)) - 1) & DispVal); + SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal); } else { if (DispVal > HEX_THRESHOLD) SStream_concat(O, "0x%"PRIx64, DispVal); diff --git a/arch/X86/X86Mapping.c b/arch/X86/X86Mapping.c index 68bf0b64..470a738f 100644 --- a/arch/X86/X86Mapping.c +++ b/arch/X86/X86Mapping.c @@ -9,6 +9,16 @@ #include "../../utils.h" #include "../../include/x86.h" + +uint64_t arch_masks[9] = { + 0, 0xff, + 0xffff, + 0, + 0xffffffff, + 0, 0, 0, + 0xffffffffffffffff +}; + static x86_reg sib_base_map[] = { X86_REG_INVALID, #define ENTRY(x) X86_REG_##x, diff --git a/arch/X86/X86Mapping.h b/arch/X86/X86Mapping.h index 7dcae0fa..b35a23f7 100644 --- a/arch/X86/X86Mapping.h +++ b/arch/X86/X86Mapping.h @@ -44,4 +44,6 @@ void X86_insn_combine(cs_struct *h, cs_insn *insn, cs_insn *prev); // this is to handle instructions embedding accumulate registers into AsmStrs[] x86_reg X86_insn_reg(unsigned int id); +extern uint64_t arch_masks[9]; + #endif