From e06b2d0868eceb2b6485441ea05d1d88dee119d7 Mon Sep 17 00:00:00 2001 From: Nguyen Anh Quynh Date: Wed, 1 Jan 2014 22:30:53 +0800 Subject: [PATCH] python: simplify access to operand's information thanks to some getters for Ops classes --- bindings/python/capstone/arm.py | 17 +++++++++++++++++ bindings/python/capstone/arm64.py | 17 +++++++++++++++++ bindings/python/capstone/mips.py | 13 +++++++++++++ bindings/python/capstone/x86.py | 17 +++++++++++++++++ bindings/python/test_arm.py | 26 +++++++++++++------------- bindings/python/test_arm64.py | 20 ++++++++++---------- bindings/python/test_mips.py | 12 ++++++------ bindings/python/test_x86.py | 24 ++++++++++++------------ 8 files changed, 105 insertions(+), 41 deletions(-) diff --git a/bindings/python/capstone/arm.py b/bindings/python/capstone/arm.py index 42d74447..fa80e401 100644 --- a/bindings/python/capstone/arm.py +++ b/bindings/python/capstone/arm.py @@ -33,6 +33,23 @@ class ArmOp(ctypes.Structure): ('value', ArmOpValue), ) + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def fp(self): + return self.value.fp + + @property + def mem(self): + return self.value.mem + + class CsArm(ctypes.Structure): _fields_ = ( ('cc', ctypes.c_uint), diff --git a/bindings/python/capstone/arm64.py b/bindings/python/capstone/arm64.py index 348c28ad..ebb71e1e 100644 --- a/bindings/python/capstone/arm64.py +++ b/bindings/python/capstone/arm64.py @@ -33,6 +33,23 @@ class Arm64Op(ctypes.Structure): ('value', Arm64OpValue), ) + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def fp(self): + return self.value.fp + + @property + def mem(self): + return self.value.mem + + class CsArm64(ctypes.Structure): _fields_ = ( ('cc', ctypes.c_uint), diff --git a/bindings/python/capstone/mips.py b/bindings/python/capstone/mips.py index 32bf9cb2..a367150b 100644 --- a/bindings/python/capstone/mips.py +++ b/bindings/python/capstone/mips.py @@ -23,6 +23,19 @@ class MipsOp(ctypes.Structure): ('value', MipsOpValue), ) + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def mem(self): + return self.value.mem + + class CsMips(ctypes.Structure): _fields_ = ( ('op_count', ctypes.c_uint8), diff --git a/bindings/python/capstone/x86.py b/bindings/python/capstone/x86.py index b6f8898d..a88dbdf5 100644 --- a/bindings/python/capstone/x86.py +++ b/bindings/python/capstone/x86.py @@ -26,6 +26,23 @@ class X86Op(ctypes.Structure): ('value', X86OpValue), ) + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def fp(self): + return self.value.fp + + @property + def mem(self): + return self.value.mem + + class CsX86(ctypes.Structure): _fields_ = ( ('prefix', ctypes.c_uint8 * 5), diff --git a/bindings/python/test_arm.py b/bindings/python/test_arm.py index cc6bcf6e..a2d6a76e 100755 --- a/bindings/python/test_arm.py +++ b/bindings/python/test_arm.py @@ -45,29 +45,29 @@ def test_class(): c = 0 for i in insn.operands: if i.type == ARM_OP_REG: - print("\t\toperands[%u].type: REG = %s" %(c, insn.reg_name(i.value.reg))) + print("\t\toperands[%u].type: REG = %s" %(c, insn.reg_name(i.reg))) if i.type == ARM_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" %(c, to_x_32(i.value.imm))) + print("\t\toperands[%u].type: IMM = 0x%s" %(c, to_x_32(i.imm))) if i.type == ARM_OP_PIMM: - print("\t\toperands[%u].type: P-IMM = %u" %(c, i.value.imm)) + print("\t\toperands[%u].type: P-IMM = %u" %(c, i.imm)) if i.type == ARM_OP_CIMM: - print("\t\toperands[%u].type: C-IMM = %u" %(c, i.value.imm)) + print("\t\toperands[%u].type: C-IMM = %u" %(c, i.imm)) if i.type == ARM_OP_FP: - print("\t\toperands[%u].type: FP = %f" %(c, i.value.fp)) + print("\t\toperands[%u].type: FP = %f" %(c, i.fp)) if i.type == ARM_OP_MEM: print("\t\toperands[%u].type: MEM" %c) - if i.value.mem.base != 0: + if i.mem.base != 0: print("\t\t\toperands[%u].mem.base: REG = %s" \ - %(c, insn.reg_name(i.value.mem.base))) - if i.value.mem.index != 0: + %(c, insn.reg_name(i.mem.base))) + if i.mem.index != 0: print("\t\t\toperands[%u].mem.index: REG = %s" \ - %(c, insn.reg_name(i.value.mem.index))) - if i.value.mem.scale != 1: + %(c, insn.reg_name(i.mem.index))) + if i.mem.scale != 1: print("\t\t\toperands[%u].mem.scale: %u" \ - %(c, i.value.mem.scale)) - if i.value.mem.disp != 0: + %(c, i.mem.scale)) + if i.mem.disp != 0: print("\t\t\toperands[%u].mem.disp: 0x%s" \ - %(c, to_x_32(i.value.mem.disp))) + %(c, to_x_32(i.mem.disp))) if i.shift.type != ARM_SFT_INVALID and i.shift.value: print("\t\t\tShift: type = %u, value = %u\n" \ diff --git a/bindings/python/test_arm64.py b/bindings/python/test_arm64.py index 0df12236..4d0e356e 100755 --- a/bindings/python/test_arm64.py +++ b/bindings/python/test_arm64.py @@ -33,24 +33,24 @@ def test_class(): for i in insn.operands: c += 1 if i.type == ARM64_OP_REG: - print("\t\toperands[%u].type: REG = %s" %(c, insn.reg_name(i.value.reg))) + print("\t\toperands[%u].type: REG = %s" %(c, insn.reg_name(i.reg))) if i.type == ARM64_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" %(c, to_x(i.value.imm))) + print("\t\toperands[%u].type: IMM = 0x%s" %(c, to_x(i.imm))) if i.type == ARM64_OP_CIMM: - print("\t\toperands[%u].type: C-IMM = %u" %(c, i.value.imm)) + print("\t\toperands[%u].type: C-IMM = %u" %(c, i.imm)) if i.type == ARM64_OP_FP: - print("\t\toperands[%u].type: FP = %f" %(c, i.value.fp)) + print("\t\toperands[%u].type: FP = %f" %(c, i.fp)) if i.type == ARM64_OP_MEM: print("\t\toperands[%u].type: MEM" %c) - if i.value.mem.base != 0: + if i.mem.base != 0: print("\t\t\toperands[%u].mem.base: REG = %s" \ - %(c, insn.reg_name(i.value.mem.base))) - if i.value.mem.index != 0: + %(c, insn.reg_name(i.mem.base))) + if i.mem.index != 0: print("\t\t\toperands[%u].mem.index: REG = %s" \ - %(c, insn.reg_name(i.value.mem.index))) - if i.value.mem.disp != 0: + %(c, insn.reg_name(i.mem.index))) + if i.mem.disp != 0: print("\t\t\toperands[%u].mem.disp: 0x%s" \ - %(c, to_x(i.value.mem.disp))) + %(c, to_x(i.mem.disp))) if i.shift.type != ARM64_SFT_INVALID and i.shift.value: print("\t\t\tShift: type = %u, value = %u" \ diff --git a/bindings/python/test_mips.py b/bindings/python/test_mips.py index 72fcbac2..8d49d994 100755 --- a/bindings/python/test_mips.py +++ b/bindings/python/test_mips.py @@ -35,17 +35,17 @@ def test_class(): for i in insn.operands: c += 1 if i.type == MIPS_OP_REG: - print("\t\toperands[%u].type: REG = %s" %(c, insn.reg_name(i.value.reg))) + print("\t\toperands[%u].type: REG = %s" %(c, insn.reg_name(i.reg))) if i.type == MIPS_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" %(c, to_x(i.value.imm))) + print("\t\toperands[%u].type: IMM = 0x%s" %(c, to_x(i.imm))) if i.type == MIPS_OP_MEM: print("\t\toperands[%u].type: MEM" %c) - if i.value.mem.base != 0: + if i.mem.base != 0: print("\t\t\toperands[%u].mem.base: REG = %s" \ - %(c, insn.reg_name(i.value.mem.base))) - if i.value.mem.disp != 0: + %(c, insn.reg_name(i.mem.base))) + if i.mem.disp != 0: print("\t\t\toperands[%u].mem.disp: 0x%s" \ - %(c, to_x(i.value.mem.disp))) + %(c, to_x(i.mem.disp))) for (arch, mode, code, comment) in all_tests: diff --git a/bindings/python/test_x86.py b/bindings/python/test_x86.py index a408d975..d678eeeb 100755 --- a/bindings/python/test_x86.py +++ b/bindings/python/test_x86.py @@ -77,7 +77,7 @@ def test_class(): print("\timm_count: %u" %count) for i in xrange(count): op = insn.op_find(X86_OP_IMM, i + 1) - print("\t\timms[%u]: 0x%s" %(i+1, to_x(op.value.imm))) + print("\t\timms[%u]: 0x%s" %(i+1, to_x(op.imm))) if len(insn.operands) > 0: print("\top_count: %u" %len(insn.operands)) @@ -85,21 +85,21 @@ def test_class(): for i in insn.operands: c += 1 if i.type == X86_OP_REG: - print("\t\toperands[%u].type: REG = %s" %(c, insn.reg_name(i.value.reg))) + print("\t\toperands[%u].type: REG = %s" %(c, insn.reg_name(i.reg))) if i.type == X86_OP_IMM: - print("\t\toperands[%u].type: IMM = 0x%s" %(c, to_x(i.value.imm))) + print("\t\toperands[%u].type: IMM = 0x%s" %(c, to_x(i.imm))) if i.type == X86_OP_FP: - print("\t\toperands[%u].type: FP = %f" %(c, i.value.fp)) + print("\t\toperands[%u].type: FP = %f" %(c, i.fp)) if i.type == X86_OP_MEM: print("\t\toperands[%u].type: MEM" %c) - if i.value.mem.base != 0: - print("\t\t\toperands[%u].mem.base: REG = %s" %(c, insn.reg_name(i.value.mem.base))) - if i.value.mem.index != 0: - print("\t\t\toperands[%u].mem.index: REG = %s" %(c, insn.reg_name(i.value.mem.index))) - if i.value.mem.scale != 1: - print("\t\t\toperands[%u].mem.scale: %u" %(c, i.value.mem.scale)) - if i.value.mem.disp != 0: - print("\t\t\toperands[%u].mem.disp: 0x%s" %(c, to_x(i.value.mem.disp))) + if i.mem.base != 0: + print("\t\t\toperands[%u].mem.base: REG = %s" %(c, insn.reg_name(i.mem.base))) + if i.mem.index != 0: + print("\t\t\toperands[%u].mem.index: REG = %s" %(c, insn.reg_name(i.mem.index))) + if i.mem.scale != 1: + print("\t\t\toperands[%u].mem.scale: %u" %(c, i.mem.scale)) + if i.mem.disp != 0: + print("\t\t\toperands[%u].mem.disp: 0x%s" %(c, to_x(i.mem.disp))) for (arch, mode, code, comment, syntax) in all_tests: