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mips: fix bugs in the last update

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test2
Nguyen Anh Quynh 10 years ago
parent bf88118974
commit c87ccd1b89
17 changed files with 481 additions and 187 deletions
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  1. 19
      MCRegisterInfo.h
  2. 5
      arch/AArch64/AArch64Module.c
  3. 5
      arch/ARM/ARMModule.c
  4. 34
      arch/Mips/MipsDisassembler.c
  5. 5
      arch/Mips/MipsGenAsmWriter.inc
  6. 14
      arch/Mips/MipsGenDisassemblerTables.inc
  7. 51
      arch/Mips/MipsGenRegisterInfo.inc
  8. 2
      arch/Mips/MipsInstPrinter.c
  9. 448
      arch/Mips/MipsMapping.c
  10. 15
      arch/Mips/MipsModule.c
  11. 5
      arch/PowerPC/PPCModule.c
  12. 5
      arch/Sparc/SparcModule.c
  13. 5
      arch/SystemZ/SystemZModule.c
  14. 5
      arch/X86/X86Module.c
  15. 5
      arch/XCore/XCoreModule.c
  16. 3
      cs_priv.h
  17. 42
      include/capstone/mips.h

19
MCRegisterInfo.h
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@ -28,18 +28,6 @@ typedef uint16_t MCPhysReg;
typedef MCPhysReg* iterator;
typedef struct MCRegisterClass {
char *Name;
iterator RegsBegin;
uint8_t *RegSet;
uint16_t RegsSize;
uint16_t RegSetSize;
uint16_t ID;
uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
int8_t CopyCost;
bool Allocatable;
} MCRegisterClass;
typedef struct MCRegisterClass2 {
iterator RegsBegin;
uint8_t *RegSet;
uint32_t NameIdx;
@ -49,7 +37,7 @@ typedef struct MCRegisterClass2 {
uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
int8_t CopyCost;
bool Allocatable;
} MCRegisterClass2;
} MCRegisterClass;
/// MCRegisterDesc - This record contains information about a particular
/// register. The SubRegs field is a zero terminated array of registers that
@ -70,6 +58,10 @@ typedef struct MCRegisterDesc {
// RegUnits - Points to the list of register units. The low 4 bits holds the
// Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
uint32_t RegUnits;
/// Index into list with lane mask sequences. The sequence contains a lanemask
/// for every register unit.
uint16_t RegUnitLaneMasks;
} MCRegisterDesc;
/// MCRegisterInfo base class - We assume that the target defines a static
@ -114,7 +106,6 @@ void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
unsigned NumIndices,
uint16_t *RET);
unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC);
unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx);

5
arch/AArch64/AArch64Module.c
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@ -38,15 +38,10 @@ static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
return CS_ERR_OK;
}
static void destroy(cs_struct *handle)
{
}
void AArch64_enable(void)
{
arch_init[CS_ARCH_ARM64] = init;
arch_option[CS_ARCH_ARM64] = option;
arch_destroy[CS_ARCH_ARM64] = destroy;
// support this arch
all_arch |= (1 << CS_ARCH_ARM64);

5
arch/ARM/ARMModule.c
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@ -61,15 +61,10 @@ static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
return CS_ERR_OK;
}
static void destroy(cs_struct *handle)
{
}
void ARM_enable(void)
{
arch_init[CS_ARCH_ARM] = init;
arch_option[CS_ARCH_ARM] = option;
arch_destroy[CS_ARCH_ARM] = destroy;
// support this arch
all_arch |= (1 << CS_ARCH_ARM);

34
arch/Mips/MipsDisassembler.c
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@ -366,10 +366,10 @@ void Mips_init(MCRegisterInfo *MRI)
/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
/// according to the given endianess.
static void readInstruction16(unsigned char *code, uint32_t *insn,
bool IsBigEndian)
bool isBigEndian)
{
// We want to read exactly 2 Bytes of data.
if (IsBigEndian)
if (isBigEndian)
*insn = (code[0] << 8) | code[1];
else
*insn = (code[1] << 8) | code[0];
@ -388,12 +388,12 @@ static void readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEnd
// Little-endian: 1 | 0 | 3 | 2
// We want to read exactly 4 Bytes of data.
if (IsBigEndian) {
if (isBigEndian) {
// Encoded as a big-endian 32-bit word in the stream.
*insn =
(code[3] << 0) | (code[2] << 8) | (code[1] << 16) | (code[0] << 24);
} else {
if (IsMicroMips) {
if (isMicroMips) {
*insn = (code[2] << 0) | (code[3] << 8) | (code[0] << 16) |
(code[1] << 24);
} else {
@ -420,7 +420,7 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
// not enough data
return MCDisassembler_Fail;
readInstruction16((unsigned char*)code, &Insn, IsBigEndian);
readInstruction16((unsigned char*)code, &Insn, isBigEndian);
// Calling the auto-generated decoder function.
Result = decodeInstruction(DecoderTableMicroMips16, instr, Insn, Address, MRI, mode);
@ -433,7 +433,7 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
// not enough data
return MCDisassembler_Fail;
readInstruction32((unsigned char*)code, &Insn, IsBigEndian, true);
readInstruction32((unsigned char*)code, &Insn, isBigEndian, true);
//DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
// Calling the auto-generated decoder function.
@ -449,9 +449,9 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
// not enough data
return MCDisassembler_Fail;
readInstruction32((unsigned char*)code, &Insn, IsBigEndian, false);
readInstruction32((unsigned char*)code, &Insn, isBigEndian, false);
if (hasCOP3()) {
if (((mode & CS_MODE_MIPS32) == 0) && ((mode & CS_MODE_MIPS3) == 0)) {
// DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode);
if (Result != MCDisassembler_Fail) {
@ -483,11 +483,11 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
if (mode & CS_MODE_MIPSGP64) {
// DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
Result = decodeInstruction(DecoderTableMips6432, instr, Insn,
Address, MRI, mode)
if (Result != MCDisassembler_Fail) {
*Size = 4;
return Result;
}
Address, MRI, mode);
if (Result != MCDisassembler_Fail) {
*Size = 4;
return Result;
}
}
// DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
@ -1212,7 +1212,7 @@ static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
switch (Inst.getOpcode()) {
switch (MCInst_getOpcode(Inst)) {
case Mips_SWM32_MM:
case Mips_LWM32_MM:
if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
@ -1226,7 +1226,7 @@ static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
// fallthrough
default:
MCOperand_CreateReg0(Inst, Reg);
if (Inst.getOpcode() == Mips_LWP_MM || Inst.getOpcode() == Mips_SWP_MM)
if (MCInst_getOpcode(Inst) == Mips_LWP_MM || MCInst_getOpcode(Inst) == Mips_SWP_MM)
MCOperand_CreateReg0(Inst, Reg + 1);
MCOperand_CreateReg0(Inst, Base);
@ -1590,7 +1590,7 @@ static DecodeStatus DecodeLiSimm7(MCInst *Inst,
unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
{
if (Value == 0x7F)
MCOperand_CreateImm0(Inst, -1)
MCOperand_CreateImm0(Inst, -1);
else
MCOperand_CreateImm0(Inst, Value);
@ -1660,7 +1660,7 @@ static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
}
static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn,
uint64_t Address, const void *Decoder)
uint64_t Address, MCRegisterInfo *Decoder)
{
int32_t DecodedValue;

5
arch/Mips/MipsGenAsmWriter.inc
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@ -5267,10 +5267,11 @@ static char *getRegisterName(unsigned RegNo)
144,
};
//printf("==== RegNo = %u, id = %s\n", RegNo, AsmStrs+RegAsmOffset[RegNo-1]);
//int i;
//for (i = 0; i < sizeof(RegAsmOffset)/4; i++)
//for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
// printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
//printf("*************************\n");
//printf("-------------------------\n");
return AsmStrs+RegAsmOffset[RegNo-1];
#else
return NULL;

14
arch/Mips/MipsGenDisassemblerTables.inc
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@ -6203,7 +6203,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
MCOperand_CreateImm0(MI, tmp); \
return S; \
case 178: \
if (DecodeINSVE_DF(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
if (DecodeINSVE_DF_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
return S; \
case 179: \
tmp = fieldname(insn, 6, 5); \
@ -6531,13 +6531,13 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
if (DecodeSimm16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
return S; \
case 226: \
if (DecodeBlezGroupBranch(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
if (DecodeBlezGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
return S; \
case 227: \
if (DecodeBgtzGroupBranch(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
if (DecodeBgtzGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
return S; \
case 228: \
if (DecodeAddiGroupBranch(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
if (DecodeAddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
return S; \
case 229: \
tmp = fieldname(insn, 16, 5); \
@ -6619,13 +6619,13 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
if (DecodeFMemCop2R6(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
return S; \
case 239: \
if (DecodeBlezlGroupBranch(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
if (DecodeBlezlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
return S; \
case 240: \
if (DecodeBgtzlGroupBranch(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
if (DecodeBgtzlGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
return S; \
case 241: \
if (DecodeDaddiGroupBranch(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
if (DecodeDaddiGroupBranch_4(MI, insn, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
return S; \
case 242: \
tmp = fieldname(insn, 21, 5); \

51
arch/Mips/MipsGenRegisterInfo.inc
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@ -1628,56 +1628,7 @@ static MCRegisterDesc MipsRegDesc[] = { // Descriptors
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
};
}
extern const char MipsRegClassStrings[] = {
/* 0 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'F', 'G', 'R', 'H', '3', '2', 0,
/* 40 */ 'H', 'I', '3', '2', 0,
/* 45 */ 'L', 'O', '3', '2', 0,
/* 50 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'F', 'G', 'R', '3', '2', 0,
/* 89 */ 'G', 'P', 'R', '3', '2', 0,
/* 95 */ 'C', 'O', 'P', '2', 0,
/* 100 */ 'C', 'O', 'P', '3', 0,
/* 105 */ 'A', 'C', 'C', '6', '4', 0,
/* 111 */ 'H', 'I', '6', '4', 0,
/* 116 */ 'L', 'O', '6', '4', 0,
/* 121 */ 'A', 'F', 'G', 'R', '6', '4', 0,
/* 128 */ 'G', 'P', 'R', '6', '4', 0,
/* 134 */ 'G', 'P', 'R', 'M', 'M', '1', '6', 0,
/* 142 */ 'A', 'C', 'C', '1', '2', '8', 0,
/* 149 */ 'M', 'S', 'A', '1', '2', '8', 'B', 0,
/* 157 */ 'F', 'C', 'C', 0,
/* 161 */ 'D', 'S', 'P', 'C', 'C', 0,
/* 167 */ 'F', 'G', 'R', 'C', 'C', 0,
/* 173 */ 'M', 'S', 'A', '1', '2', '8', 'D', 0,
/* 181 */ 'M', 'S', 'A', '1', '2', '8', 'H', 0,
/* 189 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'M', 'P', 'L', 0,
/* 200 */ 'H', 'I', '3', '2', 'D', 'S', 'P', 0,
/* 208 */ 'L', 'O', '3', '2', 'D', 'S', 'P', 0,
/* 216 */ 'A', 'C', 'C', '6', '4', 'D', 'S', 'P', 0,
/* 225 */ 'F', 'G', 'R', 'H', '3', '2', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0,
/* 242 */ 'F', 'G', 'R', '3', '2', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0,
/* 258 */ 'A', 'F', 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0,
/* 275 */ 'M', 'S', 'A', '1', '2', '8', 'B', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '6', '4', '_', 'i', 'n', '_', 'O', 'd', 'd', 'S', 'P', 0,
/* 304 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 'P', 'l', 'u', 's', 'S', 'P', 0,
/* 341 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'P', 0,
/* 350 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
/* 398 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
/* 432 */ 'C', 'C', 'R', 0,
/* 436 */ 'D', 'S', 'P', 'R', 0,
/* 441 */ 'M', 'S', 'A', '1', '2', '8', 'W', 0,
/* 449 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', 'R', 'A', 'R', 'e', 'g', 0,
/* 479 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', 'S', 'P', 'R', 'e', 'g', 0,
/* 509 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', 0,
/* 527 */ 'M', 'S', 'A', 'C', 't', 'r', 'l', 0,
/* 535 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
/* 585 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
/* 649 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
/* 696 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
/* 729 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 0,
/* 760 */ 'H', 'W', 'R', 'e', 'g', 's', 0,
/* 767 */ 'M', 'S', 'A', '1', '2', '8', 'W', 'E', 'v', 'e', 'n', 's', 0,
static MCRegisterClass2 MipsMCRegisterClasses[] = {
static MCRegisterClass MipsMCRegisterClasses[] = {
{ OddSP, OddSPBits, 236, 56, sizeof(OddSPBits), Mips_OddSPRegClassID, 4, 4, 1, 0 },
{ CCR, CCRBits, 432, 32, sizeof(CCRBits), Mips_CCRRegClassID, 4, 4, 1, 0 },
{ COP2, COP2Bits, 95, 32, sizeof(COP2Bits), Mips_COP2RegClassID, 4, 4, 1, 0 },

2
arch/Mips/MipsInstPrinter.c
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@ -430,7 +430,7 @@ static char *printAlias(MCInst *MI, SStream *OS)
static void printRegisterList(MCInst *MI, int opNum, SStream *O)
{
int i;
int i, e;
// - 2 because register List is always first operand of instruction and it is
// always followed by memory operand (base + offset).

448
arch/Mips/MipsMapping.c
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File diff suppressed because it is too large Load Diff

15
arch/Mips/MipsModule.c
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@ -36,26 +36,13 @@ static cs_err init(cs_struct *ud)
static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
{
if (type == CS_OPT_MODE) {
if (value & CS_MODE_32)
handle->disasm = Mips_getInstruction;
else
handle->disasm = Mips64_getInstruction;
handle->mode = value;
}
return CS_ERR_OK;
}
static void destroy(cs_struct *handle)
{
return CS_ERR_OPTION;
}
void Mips_enable(void)
{
arch_init[CS_ARCH_MIPS] = init;
arch_option[CS_ARCH_MIPS] = option;
arch_destroy[CS_ARCH_MIPS] = destroy;
// support this arch
all_arch |= (1 << CS_ARCH_MIPS);

5
arch/PowerPC/PPCModule.c
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@ -43,15 +43,10 @@ static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
return CS_ERR_OK;
}
static void destroy(cs_struct *handle)
{
}
void PPC_enable(void)
{
arch_init[CS_ARCH_PPC] = init;
arch_option[CS_ARCH_PPC] = option;
arch_destroy[CS_ARCH_PPC] = destroy;
// support this arch
all_arch |= (1 << CS_ARCH_PPC);

5
arch/Sparc/SparcModule.c
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@ -42,15 +42,10 @@ static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
return CS_ERR_OK;
}
static void destroy(cs_struct *handle)
{
}
void Sparc_enable(void)
{
arch_init[CS_ARCH_SPARC] = init;
arch_option[CS_ARCH_SPARC] = option;
arch_destroy[CS_ARCH_SPARC] = destroy;
// support this arch
all_arch |= (1 << CS_ARCH_SPARC);

5
arch/SystemZ/SystemZModule.c
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@ -38,15 +38,10 @@ static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
return CS_ERR_OK;
}
static void destroy(cs_struct *handle)
{
}
void SystemZ_enable(void)
{
arch_init[CS_ARCH_SYSZ] = init;
arch_option[CS_ARCH_SYSZ] = option;
arch_destroy[CS_ARCH_SYSZ] = destroy;
// support this arch
all_arch |= (1 << CS_ARCH_SYSZ);

5
arch/X86/X86Module.c
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@ -87,15 +87,10 @@ static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
return CS_ERR_OK;
}
static void destroy(cs_struct *handle)
{
}
void X86_enable(void)
{
arch_init[CS_ARCH_X86] = init;
arch_option[CS_ARCH_X86] = option;
arch_destroy[CS_ARCH_X86] = destroy;
// support this arch
all_arch |= (1 << CS_ARCH_X86);

5
arch/XCore/XCoreModule.c
Unescape View File

@ -35,15 +35,10 @@ static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
return CS_ERR_OK;
}
static void destroy(cs_struct *handle)
{
}
void XCore_enable(void)
{
arch_init[CS_ARCH_XCORE] = init;
arch_option[CS_ARCH_XCORE] = option;
arch_destroy[CS_ARCH_XCORE] = destroy;
// support this arch
all_arch |= (1 << CS_ARCH_XCORE);

3
cs_priv.h
Unescape View File

@ -64,9 +64,6 @@ extern cs_err (*arch_init[MAX_ARCH]) (cs_struct *);
// support cs_option() for all archs
extern cs_err (*arch_option[MAX_ARCH]) (cs_struct*, cs_opt_type, size_t value);
// deinitialized functions: to be called when cs_close() is called
extern void (*arch_destroy[MAX_ARCH]) (cs_struct*);
extern unsigned int all_arch;
extern cs_malloc_t cs_mem_malloc;

42
include/capstone/mips.h
Unescape View File

@ -56,6 +56,8 @@ typedef struct cs_mips {
typedef enum mips_reg {
MIPS_REG_INVALID = 0,
//> General purpose registers
MIPS_REG_PC,
MIPS_REG_0,
MIPS_REG_1,
MIPS_REG_2,
@ -260,6 +262,10 @@ typedef enum mips_insn {
MIPS_INS_ABSQ_S,
MIPS_INS_ADD,
MIPS_INS_ADDIUPC,
MIPS_INS_ADDIUR1SP,
MIPS_INS_ADDIUR2,
MIPS_INS_ADDIUS5,
MIPS_INS_ADDIUSP,
MIPS_INS_ADDQH,
MIPS_INS_ADDQH_R,
MIPS_INS_ADDQ,
@ -268,6 +274,7 @@ typedef enum mips_insn {
MIPS_INS_ADDS_A,
MIPS_INS_ADDS_S,
MIPS_INS_ADDS_U,
MIPS_INS_ADDU16,
MIPS_INS_ADDUH,
MIPS_INS_ADDUH_R,
MIPS_INS_ADDU,
@ -281,6 +288,8 @@ typedef enum mips_insn {
MIPS_INS_ALIGN,
MIPS_INS_ALUIPC,
MIPS_INS_AND,
MIPS_INS_AND16,
MIPS_INS_ANDI16,
MIPS_INS_ANDI,
MIPS_INS_APPEND,
MIPS_INS_ASUB_S,
@ -291,10 +300,15 @@ typedef enum mips_insn {
MIPS_INS_AVER_U,
MIPS_INS_AVE_S,
MIPS_INS_AVE_U,
MIPS_INS_B16,
MIPS_INS_BADDU,
MIPS_INS_BAL,
MIPS_INS_BALC,
MIPS_INS_BALIGN,
MIPS_INS_BBIT0,
MIPS_INS_BBIT032,
MIPS_INS_BBIT1,
MIPS_INS_BBIT132,
MIPS_INS_BC,
MIPS_INS_BC0F,
MIPS_INS_BC0FL,
@ -321,6 +335,7 @@ typedef enum mips_insn {
MIPS_INS_BEQ,
MIPS_INS_BEQC,
MIPS_INS_BEQL,
MIPS_INS_BEQZ16,
MIPS_INS_BEQZALC,
MIPS_INS_BEQZC,
MIPS_INS_BGEC,
@ -364,6 +379,7 @@ typedef enum mips_insn {
MIPS_INS_BNEGI,
MIPS_INS_BNEG,
MIPS_INS_BNEL,
MIPS_INS_BNEZ16,
MIPS_INS_BNEZALC,
MIPS_INS_BNEZC,
MIPS_INS_BNVC,
@ -371,6 +387,7 @@ typedef enum mips_insn {
MIPS_INS_BOVC,
MIPS_INS_BPOSGE32,
MIPS_INS_BREAK,
MIPS_INS_BREAK16,
MIPS_INS_BSELI,
MIPS_INS_BSEL,
MIPS_INS_BSETI,
@ -580,16 +597,19 @@ typedef enum mips_insn {
MIPS_INS_J,
MIPS_INS_JAL,
MIPS_INS_JALR,
MIPS_INS_JALRS16,
MIPS_INS_JALRS,
MIPS_INS_JALS,
MIPS_INS_JALX,
MIPS_INS_JIALC,
MIPS_INS_JIC,
MIPS_INS_JR,
MIPS_INS_JR16,
MIPS_INS_JRADDIUSP,
MIPS_INS_JRC,
MIPS_INS_JALRC,
MIPS_INS_LB,
MIPS_INS_LBU16,
MIPS_INS_LBUX,
MIPS_INS_LBU,
MIPS_INS_LD,
@ -602,24 +622,31 @@ typedef enum mips_insn {
MIPS_INS_LDR,
MIPS_INS_LDXC1,
MIPS_INS_LH,
MIPS_INS_LHU16,
MIPS_INS_LHX,
MIPS_INS_LHU,
MIPS_INS_LI16,
MIPS_INS_LL,
MIPS_INS_LLD,
MIPS_INS_LSA,
MIPS_INS_LUXC1,
MIPS_INS_LUI,
MIPS_INS_LW,
MIPS_INS_LW16,
MIPS_INS_LWC1,
MIPS_INS_LWC2,
MIPS_INS_LWC3,
MIPS_INS_LWL,
MIPS_INS_LWM16,
MIPS_INS_LWM32,
MIPS_INS_LWPC,
MIPS_INS_LWP,
MIPS_INS_LWR,
MIPS_INS_LWUPC,
MIPS_INS_LWU,
MIPS_INS_LWX,
MIPS_INS_LWXC1,
MIPS_INS_LWXS,
MIPS_INS_LI,
MIPS_INS_MADD,
MIPS_INS_MADDF,
@ -655,6 +682,7 @@ typedef enum mips_insn {
MIPS_INS_MOD_S,
MIPS_INS_MOD_U,
MIPS_INS_MOVE,
MIPS_INS_MOVEP,
MIPS_INS_MOVF,
MIPS_INS_MOVN,
MIPS_INS_MOVT,
@ -699,8 +727,10 @@ typedef enum mips_insn {
MIPS_INS_NMSUB,
MIPS_INS_NOR,
MIPS_INS_NORI,
MIPS_INS_NOT16,
MIPS_INS_NOT,
MIPS_INS_OR,
MIPS_INS_OR16,
MIPS_INS_ORI,
MIPS_INS_PACKRL,
MIPS_INS_PAUSE,
@ -732,10 +762,12 @@ typedef enum mips_insn {
MIPS_INS_SAT_S,
MIPS_INS_SAT_U,
MIPS_INS_SB,
MIPS_INS_SB16,
MIPS_INS_SC,
MIPS_INS_SCD,
MIPS_INS_SD,
MIPS_INS_SDBBP,
MIPS_INS_SDBBP16,
MIPS_INS_SDC1,
MIPS_INS_SDC2,
MIPS_INS_SDC3,
@ -750,6 +782,7 @@ typedef enum mips_insn {
MIPS_INS_SEQ,
MIPS_INS_SEQI,
MIPS_INS_SH,
MIPS_INS_SH16,
MIPS_INS_SHF,
MIPS_INS_SHILO,
MIPS_INS_SHILOV,
@ -766,6 +799,7 @@ typedef enum mips_insn {
MIPS_INS_SLDI,
MIPS_INS_SLD,
MIPS_INS_SLL,
MIPS_INS_SLL16,
MIPS_INS_SLLI,
MIPS_INS_SLLV,
MIPS_INS_SLT,
@ -782,6 +816,7 @@ typedef enum mips_insn {
MIPS_INS_SRAR,
MIPS_INS_SRAV,
MIPS_INS_SRL,
MIPS_INS_SRL16,
MIPS_INS_SRLI,
MIPS_INS_SRLRI,
MIPS_INS_SRLR,
@ -796,6 +831,7 @@ typedef enum mips_insn {
MIPS_INS_SUBSUU_S,
MIPS_INS_SUBS_S,
MIPS_INS_SUBS_U,
MIPS_INS_SUBU16,
MIPS_INS_SUBUH,
MIPS_INS_SUBUH_R,
MIPS_INS_SUBU,
@ -804,13 +840,18 @@ typedef enum mips_insn {
MIPS_INS_SUBV,
MIPS_INS_SUXC1,
MIPS_INS_SW,
MIPS_INS_SW16,
MIPS_INS_SWC1,
MIPS_INS_SWC2,
MIPS_INS_SWC3,
MIPS_INS_SWL,
MIPS_INS_SWM16,
MIPS_INS_SWM32,
MIPS_INS_SWP,
MIPS_INS_SWR,
MIPS_INS_SWXC1,
MIPS_INS_SYNC,
MIPS_INS_SYNCI,
MIPS_INS_SYSCALL,
MIPS_INS_TEQ,
MIPS_INS_TEQI,
@ -837,6 +878,7 @@ typedef enum mips_insn {
MIPS_INS_WRDSP,
MIPS_INS_WSBH,
MIPS_INS_XOR,
MIPS_INS_XOR16,
MIPS_INS_XORI,
//> some alias instructions

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