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@ -177,8 +177,12 @@ static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc, |
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//assert (!(ShOpc == ARM_AM_ror && !ShImm) && "Cannot have ror #0");
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SStream_concat(O, ARM_AM_getShiftOpcStr(ShOpc)); |
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if (MI->csh->detail) |
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if (MI->csh->detail) { |
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if (MI->csh->doing_mem) |
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MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.type = (arm_shifter)ShOpc; |
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else |
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MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type = (arm_shifter)ShOpc; |
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} |
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if (ShOpc != ARM_AM_rrx) { |
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SStream_concat(O, " "); |
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@ -187,9 +191,13 @@ static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc, |
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SStream_concat(O, "#%u", translateShiftImm(ShImm)); |
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if (_UseMarkup) |
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SStream_concat(O, ">"); |
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if (MI->csh->detail) |
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if (MI->csh->detail) { |
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if (MI->csh->doing_mem) |
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MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.value = translateShiftImm(ShImm); |
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else |
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MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = translateShiftImm(ShImm); |
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} |
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} |
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} |
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static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo) |
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