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Merge branch 'next' of https://github.com/aquynh/capstone into next

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test2
Vincent Bénony 10 years ago
parent d2f47d065f de693e48e1
commit b5e0f13cb0
5 changed files with 129 additions and 58 deletions
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  1. 4
      CMakeLists.txt
  2. 75
      arch/Sparc/SparcInstPrinter.c
  3. 3
      arch/X86/X86ATTInstPrinter.c
  4. 3
      arch/X86/X86IntelInstPrinter.c
  5. 102
      include/capstone/x86.h

4
CMakeLists.txt
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@ -192,6 +192,10 @@ if (CAPSTONE_BUILD_SHARED)
set_property(TARGET capstone-shared PROPERTY OUTPUT_NAME capstone)
set_property(TARGET capstone-shared PROPERTY COMPILE_FLAGS -DCAPSTONE_SHARED)
if (MSVC)
set_target_properties(capstone-shared PROPERTIES IMPORT_SUFFIX _dll.lib)
endif ()
if(NOT DEFINED default-target) # honor `capstone-static` for tests first.
set(default-target capstone-shared)
add_definitions(-DCAPSTONE_SHARED)

75
arch/Sparc/SparcInstPrinter.c
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@ -188,12 +188,75 @@ static void printOperand(MCInst *MI, int opNum, SStream *O)
if (MCOperand_isImm(MO)) {
Imm = (int)MCOperand_getImm(MO);
// get absolute address for CALL/Bxx
if (MI->Opcode == SP_CALL)
Imm += (uint32_t)MI->address;
else if (MI->flat_insn->id == SPARC_INS_B)
// pc + (disp30 * 4)
Imm = (uint32_t)MI->address + Imm * 4;
// Conditional branches displacements needs to be signextended to be
// able to jump backwards.
//
// Displacements are measured as the number of instructions forward or
// backward, so they need to be multiplied by 4
switch (MI->Opcode) {
case SP_CALL:
Imm = SignExtend32(Imm, 30);
Imm += (uint32_t)MI->address;
break;
// Branch on integer condition with prediction (BPcc)
// Branch on floating point condition with prediction (FBPfcc)
case SP_BPICC:
case SP_BPICCA:
case SP_BPICCANT:
case SP_BPICCNT:
case SP_BPXCC:
case SP_BPXCCA:
case SP_BPXCCANT:
case SP_BPXCCNT:
case SP_BPFCC:
case SP_BPFCCA:
case SP_BPFCCANT:
case SP_BPFCCNT:
Imm = SignExtend32(Imm, 19);
Imm = (uint32_t)MI->address + Imm * 4;
break;
// Branch on integer condition (Bicc)
// Branch on floating point condition (FBfcc)
case SP_BA:
case SP_BCOND:
case SP_BCONDA:
case SP_FBCOND:
case SP_FBCONDA:
Imm = SignExtend32(Imm, 22);
Imm = (uint32_t)MI->address + Imm * 4;
break;
// Branch on integer register with prediction (BPr)
case SP_BPGEZapn:
case SP_BPGEZapt:
case SP_BPGEZnapn:
case SP_BPGEZnapt:
case SP_BPGZapn:
case SP_BPGZapt:
case SP_BPGZnapn:
case SP_BPGZnapt:
case SP_BPLEZapn:
case SP_BPLEZapt:
case SP_BPLEZnapn:
case SP_BPLEZnapt:
case SP_BPLZapn:
case SP_BPLZapt:
case SP_BPLZnapn:
case SP_BPLZnapt:
case SP_BPNZapn:
case SP_BPNZapt:
case SP_BPNZnapn:
case SP_BPNZnapt:
case SP_BPZapn:
case SP_BPZapt:
case SP_BPZnapn:
case SP_BPZnapt:
Imm = SignExtend32(Imm, 16);
Imm = (uint32_t)MI->address + Imm * 4;
break;
}
if (Imm >= 0) {
if (Imm > HEX_THRESHOLD)

3
arch/X86/X86ATTInstPrinter.c
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@ -649,6 +649,9 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
case X86_TEST8mi_alt:
case X86_XOR8mi:
case X86_XOR8mi8:
case X86_PUSH64i8:
case X86_CMP32ri8:
case X86_CMP64ri8:
imm = imm & 0xff;
opsize = 1; // immediate of 1 byte

3
arch/X86/X86IntelInstPrinter.c
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@ -776,6 +776,9 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
case X86_TEST8mi_alt:
case X86_XOR8mi:
case X86_XOR8mi8:
case X86_PUSH64i8:
case X86_CMP32ri8:
case X86_CMP64ri8:
imm = imm & 0xff;
opsize = 1; // immediate of 1 byte

102
include/capstone/x86.h
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@ -70,54 +70,52 @@ typedef enum x86_reg {
} x86_reg;
//> Sub-flags of EFLAGS
typedef enum x86_eflags_type {
X86_EFLAGS_MODIFY_AF = (uint64_t)1 << 0,
X86_EFLAGS_MODIFY_CF = (uint64_t)1 << 1,
X86_EFLAGS_MODIFY_SF = (uint64_t)1 << 2,
X86_EFLAGS_MODIFY_ZF = (uint64_t)1 << 3,
X86_EFLAGS_MODIFY_PF = (uint64_t)1 << 4,
X86_EFLAGS_MODIFY_OF = (uint64_t)1 << 5,
X86_EFLAGS_MODIFY_TF = (uint64_t)1 << 6,
X86_EFLAGS_MODIFY_IF = (uint64_t)1 << 7,
X86_EFLAGS_MODIFY_DF = (uint64_t)1 << 8,
X86_EFLAGS_MODIFY_NT = (uint64_t)1 << 9,
X86_EFLAGS_MODIFY_RF = (uint64_t)1 << 10,
X86_EFLAGS_PRIOR_OF = (uint64_t)1 << 11,
X86_EFLAGS_PRIOR_SF = (uint64_t)1 << 12,
X86_EFLAGS_PRIOR_ZF = (uint64_t)1 << 13,
X86_EFLAGS_PRIOR_AF = (uint64_t)1 << 14,
X86_EFLAGS_PRIOR_PF = (uint64_t)1 << 15,
X86_EFLAGS_PRIOR_CF = (uint64_t)1 << 16,
X86_EFLAGS_PRIOR_TF = (uint64_t)1 << 17,
X86_EFLAGS_PRIOR_IF = (uint64_t)1 << 18,
X86_EFLAGS_PRIOR_DF = (uint64_t)1 << 19,
X86_EFLAGS_PRIOR_NT = (uint64_t)1 << 20,
X86_EFLAGS_RESET_OF = (uint64_t)1 << 21,
X86_EFLAGS_RESET_CF = (uint64_t)1 << 22,
X86_EFLAGS_RESET_DF = (uint64_t)1 << 23,
X86_EFLAGS_RESET_IF = (uint64_t)1 << 24,
X86_EFLAGS_RESET_SF = (uint64_t)1 << 25,
X86_EFLAGS_RESET_AF = (uint64_t)1 << 26,
X86_EFLAGS_RESET_TF = (uint64_t)1 << 27,
X86_EFLAGS_RESET_NT = (uint64_t)1 << 28,
X86_EFLAGS_RESET_PF = (uint64_t)1 << 29,
X86_EFLAGS_SET_CF = (uint64_t)1 << 30,
X86_EFLAGS_SET_DF = (uint64_t)1 << 31,
X86_EFLAGS_SET_IF = (uint64_t)1 << 32,
X86_EFLAGS_TEST_OF = (uint64_t)1 << 33,
X86_EFLAGS_TEST_SF = (uint64_t)1 << 34,
X86_EFLAGS_TEST_ZF = (uint64_t)1 << 35,
X86_EFLAGS_TEST_PF = (uint64_t)1 << 36,
X86_EFLAGS_TEST_CF = (uint64_t)1 << 37,
X86_EFLAGS_TEST_NT = (uint64_t)1 << 38,
X86_EFLAGS_TEST_DF = (uint64_t)1 << 39,
X86_EFLAGS_UNDEFINED_OF = (uint64_t)1 << 40,
X86_EFLAGS_UNDEFINED_SF = (uint64_t)1 << 41,
X86_EFLAGS_UNDEFINED_ZF = (uint64_t)1 << 42,
X86_EFLAGS_UNDEFINED_PF = (uint64_t)1 << 43,
X86_EFLAGS_UNDEFINED_AF = (uint64_t)1 << 44,
X86_EFLAGS_UNDEFINED_CF = (uint64_t)1 << 45,
} x86_eflags_type;
#define X86_EFLAGS_MODIFY_AF (1ULL << 0)
#define X86_EFLAGS_MODIFY_CF (1ULL << 1)
#define X86_EFLAGS_MODIFY_SF (1ULL << 2)
#define X86_EFLAGS_MODIFY_ZF (1ULL << 3)
#define X86_EFLAGS_MODIFY_PF (1ULL << 4)
#define X86_EFLAGS_MODIFY_OF (1ULL << 5)
#define X86_EFLAGS_MODIFY_TF (1ULL << 6)
#define X86_EFLAGS_MODIFY_IF (1ULL << 7)
#define X86_EFLAGS_MODIFY_DF (1ULL << 8)
#define X86_EFLAGS_MODIFY_NT (1ULL << 9)
#define X86_EFLAGS_MODIFY_RF (1ULL << 10)
#define X86_EFLAGS_PRIOR_OF (1ULL << 11)
#define X86_EFLAGS_PRIOR_SF (1ULL << 12)
#define X86_EFLAGS_PRIOR_ZF (1ULL << 13)
#define X86_EFLAGS_PRIOR_AF (1ULL << 14)
#define X86_EFLAGS_PRIOR_PF (1ULL << 15)
#define X86_EFLAGS_PRIOR_CF (1ULL << 16)
#define X86_EFLAGS_PRIOR_TF (1ULL << 17)
#define X86_EFLAGS_PRIOR_IF (1ULL << 18)
#define X86_EFLAGS_PRIOR_DF (1ULL << 19)
#define X86_EFLAGS_PRIOR_NT (1ULL << 20)
#define X86_EFLAGS_RESET_OF (1ULL << 21)
#define X86_EFLAGS_RESET_CF (1ULL << 22)
#define X86_EFLAGS_RESET_DF (1ULL << 23)
#define X86_EFLAGS_RESET_IF (1ULL << 24)
#define X86_EFLAGS_RESET_SF (1ULL << 25)
#define X86_EFLAGS_RESET_AF (1ULL << 26)
#define X86_EFLAGS_RESET_TF (1ULL << 27)
#define X86_EFLAGS_RESET_NT (1ULL << 28)
#define X86_EFLAGS_RESET_PF (1ULL << 29)
#define X86_EFLAGS_SET_CF (1ULL << 30)
#define X86_EFLAGS_SET_DF (1ULL << 31)
#define X86_EFLAGS_SET_IF (1ULL << 32)
#define X86_EFLAGS_TEST_OF (1ULL << 33)
#define X86_EFLAGS_TEST_SF (1ULL << 34)
#define X86_EFLAGS_TEST_ZF (1ULL << 35)
#define X86_EFLAGS_TEST_PF (1ULL << 36)
#define X86_EFLAGS_TEST_CF (1ULL << 37)
#define X86_EFLAGS_TEST_NT (1ULL << 38)
#define X86_EFLAGS_TEST_DF (1ULL << 39)
#define X86_EFLAGS_UNDEFINED_OF (1ULL << 40)
#define X86_EFLAGS_UNDEFINED_SF (1ULL << 41)
#define X86_EFLAGS_UNDEFINED_ZF (1ULL << 42)
#define X86_EFLAGS_UNDEFINED_PF (1ULL << 43)
#define X86_EFLAGS_UNDEFINED_AF (1ULL << 44)
#define X86_EFLAGS_UNDEFINED_CF (1ULL << 45)
//> Operand type for instruction's operands
typedef enum x86_op_type {
@ -230,9 +228,9 @@ typedef enum x86_prefix {
// Instruction's operand referring to memory
// This is associated with X86_OP_MEM operand type above
typedef struct x86_op_mem {
unsigned int segment; // segment register (or X86_REG_INVALID if irrelevant)
unsigned int base; // base register (or X86_REG_INVALID if irrelevant)
unsigned int index; // index register (or X86_REG_INVALID if irrelevant)
x86_reg segment; // segment register (or X86_REG_INVALID if irrelevant)
x86_reg base; // base register (or X86_REG_INVALID if irrelevant)
x86_reg index; // index register (or X86_REG_INVALID if irrelevant)
int scale; // scale for index register
int64_t disp; // displacement value
} x86_op_mem;
@ -241,7 +239,7 @@ typedef struct x86_op_mem {
typedef struct cs_x86_op {
x86_op_type type; // operand type
union {
unsigned int reg; // register value for REG operand
x86_reg reg; // register value for REG operand
int64_t imm; // immediate value for IMM operand
double fp; // floating point value for FP operand
x86_op_mem mem; // base/index/scale/disp value for MEM operand

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