x86: add missing CL register operand for shift rotate instructions involving CL (AT&T syntax)

arch/X86/X86ATTInstPrinter.c

@@ -771,12 +771,15 @@ void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info)
 	}
 
 	if (MI->csh->detail) {
+		uint8_t access[6];
 		// special instruction needs to supply register op
 		// first op can be embedded in the asm by llvm.
 		// so we have to add the missing register as the first operand
+
+		//printf(">>> opcode = %u\n", MCInst_getOpcode(MI));
+
 		reg = X86_insn_reg_att(MCInst_getOpcode(MI));
 		if (reg) {
-			uint8_t access[6];
 			// shift all the ops right to leave 1st slot for this new register op
 			memmove(&(MI->flat_insn->detail->x86.operands[1]), &(MI->flat_insn->detail->x86.operands[0]),
 					sizeof(MI->flat_insn->detail->x86.operands[0]) * (ARR_SIZE(MI->flat_insn->detail->x86.operands) - 1));
@@ -784,26 +787,25 @@ void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info)
 			MI->flat_insn->detail->x86.operands[0].reg = reg;
 			MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg];
 
-			get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
-			MI->flat_insn->detail->x86.operands[0].access = access[0];
 			MI->flat_insn->detail->x86.op_count++;
 		} else {
 			if (X86_insn_reg_att2(MCInst_getOpcode(MI), &reg, &reg2)) {
-				uint8_t access[6];
-
-				get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
 
 				MI->flat_insn->detail->x86.operands[0].type = X86_OP_REG;
 				MI->flat_insn->detail->x86.operands[0].reg = reg;
 				MI->flat_insn->detail->x86.operands[0].size = MI->csh->regsize_map[reg];
-				MI->flat_insn->detail->x86.operands[0].access = access[0];
 				MI->flat_insn->detail->x86.operands[1].type = X86_OP_REG;
 				MI->flat_insn->detail->x86.operands[1].reg = reg2;
 				MI->flat_insn->detail->x86.operands[1].size = MI->csh->regsize_map[reg2];
-				MI->flat_insn->detail->x86.operands[1].access = access[1];
 				MI->flat_insn->detail->x86.op_count = 2;
 			}
 		}
+
+#ifndef CAPSTONE_DIET
+		get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
+		MI->flat_insn->detail->x86.operands[0].access = access[0];
+		MI->flat_insn->detail->x86.operands[1].access = access[1];
+#endif
 	}
 }
 

arch/X86/X86Mapping.c

@@ -2551,6 +2551,52 @@ static struct insn_reg insn_regs_att[] = {
 	{ X86_POPGS16, X86_REG_GS },
 	{ X86_POPSS16, X86_REG_SS },
 
+	{ X86_RCL32rCL, X86_REG_CL },
+	{ X86_SHL8rCL, X86_REG_CL },
+	{ X86_SHL16rCL, X86_REG_CL },
+	{ X86_SHL32rCL, X86_REG_CL },
+	{ X86_SHL64rCL, X86_REG_CL },
+	{ X86_SAL8rCL, X86_REG_CL },
+	{ X86_SAL16rCL, X86_REG_CL },
+	{ X86_SAL32rCL, X86_REG_CL },
+	{ X86_SAL64rCL, X86_REG_CL },
+	{ X86_SHR8rCL, X86_REG_CL },
+	{ X86_SHR16rCL, X86_REG_CL },
+	{ X86_SHR32rCL, X86_REG_CL },
+	{ X86_SHR64rCL, X86_REG_CL },
+	{ X86_SAR8rCL, X86_REG_CL },
+	{ X86_SAR16rCL, X86_REG_CL },
+	{ X86_SAR32rCL, X86_REG_CL },
+	{ X86_SAR64rCL, X86_REG_CL },
+	{ X86_RCL8rCL, X86_REG_CL },
+	{ X86_RCL16rCL, X86_REG_CL },
+	{ X86_RCL32rCL, X86_REG_CL },
+	{ X86_RCL64rCL, X86_REG_CL },
+	{ X86_RCR8rCL, X86_REG_CL },
+	{ X86_RCR16rCL, X86_REG_CL },
+	{ X86_RCR32rCL, X86_REG_CL },
+	{ X86_RCR64rCL, X86_REG_CL },
+	{ X86_ROL8rCL, X86_REG_CL },
+	{ X86_ROL16rCL, X86_REG_CL },
+	{ X86_ROL32rCL, X86_REG_CL },
+	{ X86_ROL64rCL, X86_REG_CL },
+	{ X86_ROR8rCL, X86_REG_CL },
+	{ X86_ROR16rCL, X86_REG_CL },
+	{ X86_ROR32rCL, X86_REG_CL },
+	{ X86_ROR64rCL, X86_REG_CL },
+	{ X86_SHLD16rrCL, X86_REG_CL },
+	{ X86_SHRD16rrCL, X86_REG_CL },
+	{ X86_SHLD32rrCL, X86_REG_CL },
+	{ X86_SHRD32rrCL, X86_REG_CL },
+	{ X86_SHLD64rrCL, X86_REG_CL },
+	{ X86_SHRD64rrCL, X86_REG_CL },
+	{ X86_SHLD16mrCL, X86_REG_CL },
+	{ X86_SHRD16mrCL, X86_REG_CL },
+	{ X86_SHLD32mrCL, X86_REG_CL },
+	{ X86_SHRD32mrCL, X86_REG_CL },
+	{ X86_SHLD64mrCL, X86_REG_CL },
+	{ X86_SHRD64mrCL, X86_REG_CL },
+
 #ifndef CAPSTONE_X86_REDUCE
 	{ X86_SKINIT, X86_REG_EAX },
 	{ X86_INVLPGA32, X86_REG_EAX },