diff --git a/arch/AArch64/AArch64Module.c b/arch/AArch64/AArch64Module.c index 83b4f4b3..2e745b8c 100644 --- a/arch/AArch64/AArch64Module.c +++ b/arch/AArch64/AArch64Module.c @@ -11,7 +11,7 @@ void enable_arm64() {} static cs_err init(cs_struct *ud) { - MCRegisterInfo *mri; + MCRegisterInfo *mri; // verify if requested mode is valid if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_BIG_ENDIAN)) diff --git a/arch/ARM/ARMDisassembler.c b/arch/ARM/ARMDisassembler.c index 31fb5dda..8de834c3 100644 --- a/arch/ARM/ARMDisassembler.c +++ b/arch/ARM/ARMDisassembler.c @@ -379,16 +379,16 @@ static uint64_t getFeatureBits(int mode) // some features are mutually exclusive if (mode & CS_MODE_THUMB) { - //Bits &= ~ARM_HasV6Ops; - //Bits &= ~ARM_FeatureCRC; - //Bits &= ~ARM_HasV5TEOps; - //Bits &= ~ARM_HasV4TOps; - //Bits &= ~ARM_HasV6T2Ops; - //Bits &= ~ARM_FeatureDB; - //Bits &= ~ARM_FeatureHWDivARM; - //Bits &= ~ARM_FeatureNaClTrap; - //Bits &= ~ARM_FeatureMClass; - // ArmV8 + //Bits &= ~ARM_HasV6Ops; + //Bits &= ~ARM_FeatureCRC; + //Bits &= ~ARM_HasV5TEOps; + //Bits &= ~ARM_HasV4TOps; + //Bits &= ~ARM_HasV6T2Ops; + //Bits &= ~ARM_FeatureDB; + //Bits &= ~ARM_FeatureHWDivARM; + //Bits &= ~ARM_FeatureNaClTrap; + //Bits &= ~ARM_FeatureMClass; + // ArmV8 } else { // ARM mode Bits &= ~ARM_ModeThumb; Bits &= ~ARM_FeatureThumb2; @@ -425,7 +425,7 @@ void ARM_init(MCRegisterInfo *MRI) ARMRegUnitRoots, 77, ARMRegDiffLists, ARMRegStrings, ARMSubRegIdxLists, 57, ARMSubRegIdxRanges, ARMRegEncodingTable); - */ + */ MCRegisterInfo_InitMCRegisterInfo(MRI, ARMRegDesc, 289, 0, 0, @@ -564,9 +564,9 @@ static void AddThumb1SBit(MCInst *MI, bool InITBlock) static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI) { DecodeStatus S = MCDisassembler_Success; - MCOperandInfo *OpInfo; - unsigned short NumOps; - unsigned int i; + MCOperandInfo *OpInfo; + unsigned short NumOps; + unsigned int i; // A few instructions actually have predicates encoded in them. Don't // try to overwrite it if we're seeing one of those. @@ -643,9 +643,9 @@ static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI) static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI) { unsigned CC; - unsigned short NumOps; - MCOperandInfo *OpInfo; - unsigned i; + unsigned short NumOps; + MCOperandInfo *OpInfo; + unsigned i; CC = ITStatus_getITCC(&(ud->ITBlock)); if (ITStatus_instrInITBlock(&(ud->ITBlock))) @@ -1132,7 +1132,7 @@ static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; - ARM_AM_ShiftOpc Shift; + ARM_AM_ShiftOpc Shift; unsigned Rm = fieldFromInstruction_4(Val, 0, 4); unsigned type = fieldFromInstruction_4(Val, 5, 2); @@ -1171,7 +1171,7 @@ static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; - ARM_AM_ShiftOpc Shift; + ARM_AM_ShiftOpc Shift; unsigned Rm = fieldFromInstruction_4(Val, 0, 4); unsigned type = fieldFromInstruction_4(Val, 5, 2); @@ -1306,7 +1306,7 @@ static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val, // create the final mask. unsigned msb = fieldFromInstruction_4(Val, 5, 5); unsigned lsb = fieldFromInstruction_4(Val, 0, 5); - uint32_t lsb_mask; + uint32_t lsb_mask; DecodeStatus S = MCDisassembler_Success; if (lsb > msb) { @@ -1474,8 +1474,8 @@ static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; - ARM_AM_AddrOpc Op; - ARM_AM_ShiftOpc Opc; + ARM_AM_AddrOpc Op; + ARM_AM_ShiftOpc Opc; unsigned Rn = fieldFromInstruction_4(Insn, 16, 4); unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); @@ -1582,7 +1582,7 @@ static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler_Success; - ARM_AM_ShiftOpc ShOp; + ARM_AM_ShiftOpc ShOp; unsigned Rn = fieldFromInstruction_4(Val, 13, 4); unsigned Rm = fieldFromInstruction_4(Val, 0, 4); @@ -4904,7 +4904,7 @@ static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val, static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { - DecodeStatus S; + DecodeStatus S; unsigned Rt = fieldFromInstruction_4(Insn, 12, 4); unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4); diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c index 8093c07b..bfcce01e 100644 --- a/arch/ARM/ARMInstPrinter.c +++ b/arch/ARM/ARMInstPrinter.c @@ -505,30 +505,30 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info) case ARM_STREXD: case ARM_LDAEXD: case ARM_STLEXD: { - MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID); - bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD; - - unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0)); - if (MCRegisterClass_contains(MRC, Reg)) { - MCInst NewMI; - MCOperand *NewReg; - MCInst_setOpcode(&NewMI, Opcode); - - if (isStore) - MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0)); - NewReg = MCOperand_CreateReg(MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0, - MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID))); - MCInst_addOperand2(&NewMI, NewReg); - cs_mem_free(NewReg); - - // Copy the rest operands into NewMI. - unsigned i; - for(i= isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i) - MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i)); - printInstruction(&NewMI, O, MRI); - return; + MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID); + bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD; + + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0)); + if (MCRegisterClass_contains(MRC, Reg)) { + MCInst NewMI; + MCOperand *NewReg; + MCInst_setOpcode(&NewMI, Opcode); + + if (isStore) + MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0)); + NewReg = MCOperand_CreateReg(MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0, + MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID))); + MCInst_addOperand2(&NewMI, NewReg); + cs_mem_free(NewReg); + + // Copy the rest operands into NewMI. + unsigned i; + for(i= isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i) + MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i)); + printInstruction(&NewMI, O, MRI); + return; + } } - } } //if (printAliasInstr(MI, O, MRI)) @@ -854,7 +854,7 @@ static void printAM3PostIndexOp(MCInst *MI, unsigned Op, SStream *O) if (op) MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = ImmOffs; else - MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = -(int)ImmOffs; + MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = -(int)ImmOffs; MI->flat_insn.arm.op_count++; } @@ -1277,7 +1277,7 @@ static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O) // FIXME: FeatureMClass becomes mode?? //if (ARM_getFeatureBits(MI->csh->mode) & ARM_FeatureMClass) { //if (true) - { + { unsigned SYSm = (unsigned int)MCOperand_getImm(Op); unsigned Opcode = MCInst_getOpcode(MI); // For reads of the special registers ignore the "mask encoding" bits @@ -1422,7 +1422,7 @@ static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O) SStream_concat(O, "c%u", MCOperand_getImm(MCInst_getOperand(MI, OpNum))); if (MI->csh->detail) { MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_CIMM; - MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); MI->flat_insn.arm.op_count++; } } @@ -1481,11 +1481,11 @@ static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O) SStream_concat(O, "%s#0x%x", markup("csh->detail) { - MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM; - MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = tmp; - MI->flat_insn.arm.op_count++; - } + if (MI->csh->detail) { + MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM; + MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = tmp; + MI->flat_insn.arm.op_count++; + } SStream_concat(O, markup(">")); } @@ -1636,8 +1636,8 @@ static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); - int32_t OffImm; - bool isSub; + int32_t OffImm; + bool isSub; if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right. printOperand(MI, OpNum, O); @@ -1676,8 +1676,8 @@ static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, { MCOperand *MO1 = MCInst_getOperand(MI, OpNum); MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1); - int32_t OffImm; - bool isSub; + int32_t OffImm; + bool isSub; SStream_concat(O, "%s[", markup("