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address warnings with capstone_static_winkernel

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v3
tandasat 9 years ago
parent 2c44f91cb3
commit a6609fede8
9 changed files with 19 additions and 19 deletions
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  1. 6
      arch/AArch64/AArch64Disassembler.c
  2. 2
      arch/AArch64/AArch64InstPrinter.c
  3. 2
      arch/Sparc/SparcDisassembler.c
  4. 6
      arch/Sparc/SparcInstPrinter.c
  5. 2
      arch/X86/X86ATTInstPrinter.c
  6. 2
      arch/X86/X86DisassemblerDecoder.c
  7. 2
      arch/X86/X86IntelInstPrinter.c
  8. 14
      arch/XCore/XCoreInstPrinter.c
  9. 2
      cs.c

6
arch/AArch64/AArch64Disassembler.c
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@ -1175,9 +1175,9 @@ static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst,
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
MCOperand_CreateImm0(Inst, offset);
IsLoad = fieldFromInstruction(insn, 22, 1);
IsLoad = fieldFromInstruction(insn, 22, 1) != 0;
IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
IsFP = fieldFromInstruction(insn, 26, 1);
IsFP = fieldFromInstruction(insn, 26, 1) != 0;
// Cannot write back to a transfer register (but xzr != sp).
if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
@ -1270,7 +1270,7 @@ static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn,
unsigned Rn = fieldFromInstruction(insn, 5, 5);
unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
int32_t offset = fieldFromInstruction(insn, 15, 7);
bool IsLoad = fieldFromInstruction(insn, 22, 1);
bool IsLoad = fieldFromInstruction(insn, 22, 1) != 0;
unsigned Opcode = MCInst_getOpcode(Inst);
bool NeedsDisjointWritebackTransfer = false;

2
arch/AArch64/AArch64InstPrinter.c
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@ -1365,7 +1365,7 @@ static void printSystemPStateField(MCInst *MI, unsigned OpNo, SStream *O)
static void printSIMDType10Operand(MCInst *MI, unsigned OpNo, SStream *O)
{
unsigned RawVal = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
uint8_t RawVal = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
uint64_t Val = AArch64_AM_decodeAdvSIMDModImmType10(RawVal);
SStream_concat(O, "#%#016llx", Val);
if (MI->csh->detail) {

2
arch/Sparc/SparcDisassembler.c
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@ -255,7 +255,7 @@ static DecodeStatus DecodeMem(MCInst *MI, unsigned insn, uint64_t Address,
DecodeStatus status;
unsigned rd = fieldFromInstruction_4(insn, 25, 5);
unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
bool isImm = fieldFromInstruction_4(insn, 13, 1);
bool isImm = fieldFromInstruction_4(insn, 13, 1) != 0;
unsigned rs2 = 0;
unsigned simm13 = 0;

6
arch/Sparc/SparcInstPrinter.c
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@ -81,7 +81,7 @@ void Sparc_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
if (insn->id == SPARC_INS_CASX) {
// first op is actually a memop, not regop
insn->detail->sparc.operands[0].type = SPARC_OP_MEM;
insn->detail->sparc.operands[0].mem.base = insn->detail->sparc.operands[0].reg;
insn->detail->sparc.operands[0].mem.base = (uint8_t)insn->detail->sparc.operands[0].reg;
insn->detail->sparc.operands[0].mem.disp = 0;
}
}
@ -172,9 +172,9 @@ static void printOperand(MCInst *MI, int opNum, SStream *O)
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
if (MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base)
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = reg;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = (uint8_t)reg;
else
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = reg;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = (uint8_t)reg;
} else {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;

2
arch/X86/X86ATTInstPrinter.c
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@ -493,7 +493,7 @@ static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O)
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
int opsize = 0;
uint8_t opsize = 0;
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {

2
arch/X86/X86DisassemblerDecoder.c
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@ -1095,7 +1095,7 @@ static int getIDWithAttrMask(uint16_t *instructionID,
hasModRMExtension = modRMRequired(insn->opcodeType,
instructionClass,
insn->opcode);
insn->opcode) != 0;
if (hasModRMExtension) {
if (readModRM(insn))

2
arch/X86/X86IntelInstPrinter.c
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@ -582,7 +582,7 @@ static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O)
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
int opsize = 0;
uint8_t opsize = 0;
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {

14
arch/XCore/XCoreInstPrinter.c
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@ -91,7 +91,7 @@ void XCore_insn_extract(MCInst *MI, const char *code)
// base register
if (MI->csh->detail) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = id;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)id;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1;
@ -109,7 +109,7 @@ void XCore_insn_extract(MCInst *MI, const char *code)
if (id) {
// index register
if (MI->csh->detail) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = id;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)id;
}
} else {
// a number means disp
@ -160,7 +160,7 @@ static void set_mem_access(MCInst *MI, bool status, int reg)
if (reg != 0xffff && reg != -0xffff) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
if (reg) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = reg;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)reg;
} else {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = XCORE_REG_INVALID;
}
@ -171,7 +171,7 @@ static void set_mem_access(MCInst *MI, bool status, int reg)
// the last op should be the memory base
MI->flat_insn->detail->xcore.op_count--;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0;
if (reg > 0)
@ -181,7 +181,7 @@ static void set_mem_access(MCInst *MI, bool status, int reg)
}
} else {
if (reg) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = reg;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)reg;
// done, create the next operand slot
MI->flat_insn->detail->xcore.op_count++;
}
@ -199,9 +199,9 @@ static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O)
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
if (MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base == ARM_REG_INVALID)
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = reg;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)reg;
else
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = reg;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)reg;
} else {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = reg;

2
cs.c
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@ -289,7 +289,7 @@ static void fill_insn(struct cs_struct *handle, cs_insn *insn, char *buffer, MCI
#ifndef CAPSTONE_DIET
char *sp, *mnem;
#endif
unsigned int copy_size = MIN(sizeof(insn->bytes), insn->size);
uint16_t copy_size = MIN(sizeof(insn->bytes), insn->size);
// fill the instruction bytes.
// we might skip some redundant bytes in front in the case of X86

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