x86: add new instructions: FSETPM, SALC, GETSEC & INT1. bug reported by Pancake

Makefile

@@ -47,6 +47,14 @@ LIBNAME = capstone
 LIBOBJ =
 LIBOBJ += cs.o utils.o SStream.o MCInstrDesc.o MCRegisterInfo.o
 
+ifneq (,$(findstring x86,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_X86
+	LIBOBJ += arch/X86/X86DisassemblerDecoder.o
+	LIBOBJ += arch/X86/X86Disassembler.o
+	LIBOBJ += arch/X86/X86IntelInstPrinter.o
+	LIBOBJ += arch/X86/X86ATTInstPrinter.o
+	LIBOBJ += arch/X86/mapping.o arch/X86/module.o
+endif
 ifneq (,$(findstring arm,$(CAPSTONE_ARCHS)))
 	CFLAGS += -DCAPSTONE_HAS_ARM
 	LIBOBJ += arch/ARM/ARMDisassembler.o
@@ -68,14 +76,6 @@ ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS)))
 	LIBOBJ += arch/PowerPC/mapping.o
 	LIBOBJ += arch/PowerPC/module.o
 endif
-ifneq (,$(findstring x86,$(CAPSTONE_ARCHS)))
-	CFLAGS += -DCAPSTONE_HAS_X86
-	LIBOBJ += arch/X86/X86DisassemblerDecoder.o
-	LIBOBJ += arch/X86/X86Disassembler.o
-	LIBOBJ += arch/X86/X86IntelInstPrinter.o
-	LIBOBJ += arch/X86/X86ATTInstPrinter.o
-	LIBOBJ += arch/X86/mapping.o arch/X86/module.o
-endif
 ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS)))
 	CFLAGS += -DCAPSTONE_HAS_ARM64
 	LIBOBJ += arch/AArch64/AArch64BaseInfo.o

arch/X86/X86ATTInstPrinter.c

@@ -446,7 +446,7 @@ void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info)
 	//  OS << "\tlock\n";
 
 	// Try to print any aliases first.
-	if (printAliasInstr(MI, OS)) {
+	if (printAliasInstr(MI, OS, NULL)) {
 		char *mnem = cs_strdup(OS->buffer);
 		char *tab = strchr(mnem, '\t');
 		if (tab)

arch/X86/X86GenRegisterInfo.inc

@@ -6,9 +6,10 @@
 |*                                                                            *|
 \*===----------------------------------------------------------------------===*/
 
-/* Capstone Disassembler Engine */
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
 
+
 #ifdef GET_REGINFO_ENUM
 #undef GET_REGINFO_ENUM
 
@@ -249,6 +250,7 @@ enum {
   X86_NUM_TARGET_REGS 	// 233
 };
 
+// Register classes
 enum {
   X86_GR8RegClassID = 0,
   X86_GR8_NOREXRegClassID = 1,
@@ -322,3 +324,4 @@ enum {
 };
 
 #endif // GET_REGINFO_ENUM
+

arch/X86/X86IntelInstPrinter.c

@@ -216,14 +216,14 @@ static bool get_first_op(char *buffer, char *firstop)
 		return false;
 }
 
-static bool printAliasInstr(MCInst *MI, SStream *OS);
+static bool printAliasInstr(MCInst *MI, SStream *OS, void *info);
 static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
 void X86_Intel_printInst(MCInst *MI, SStream *O, void *Info)
 {
 	//if (TSFlags & X86II::LOCK)
 	//  O << "\tlock\n";
 
-	if (printAliasInstr(MI, O)) {
+	if (printAliasInstr(MI, O, NULL)) {
 		char *mnem = cs_strdup(O->buffer);
 		char *tab = strchr(mnem, '\t');
 		if (tab)
@@ -352,7 +352,7 @@ static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O)
 	}
 }
 
-static const char *getRegisterName(unsigned RegNo);
+static char *getRegisterName(unsigned RegNo);
 static void printRegName(SStream *OS, unsigned RegNo)
 {
 	SStream_concat(OS, getRegisterName(RegNo));

arch/X86/mapping.c

@@ -518,6 +518,7 @@ static name_map insn_name_maps[] = {
 	{ X86_INS_FRSTOR, "frstor" },
 	{ X86_INS_FNSAVE, "fnsave" },
 	{ X86_INS_FSCALE, "fscale" },
+	{ X86_INS_FSETPM, "fsetpm" },
 	{ X86_INS_FSINCOS, "fsincos" },
 	{ X86_INS_FNSTENV, "fnstenv" },
 	{ X86_INS_FS, "fs" },
@@ -537,6 +538,7 @@ static name_map insn_name_maps[] = {
 	{ X86_INS_VMOVAPS, "vmovaps" },
 	{ X86_INS_XORPD, "xorpd" },
 	{ X86_INS_XORPS, "xorps" },
+	{ X86_INS_GETSEC, "getsec" },
 	{ X86_INS_GS, "gs" },
 	{ X86_INS_HADDPD, "haddpd" },
 	{ X86_INS_HADDPS, "haddps" },
@@ -552,6 +554,7 @@ static name_map insn_name_maps[] = {
 	{ X86_INS_INSERTPS, "insertps" },
 	{ X86_INS_INSERTQ, "insertq" },
 	{ X86_INS_INT, "int" },
+	{ X86_INS_INT1, "int1" },
 	{ X86_INS_INT3, "int3" },
 	{ X86_INS_INTO, "into" },
 	{ X86_INS_INVD, "invd" },
@@ -921,6 +924,7 @@ static name_map insn_name_maps[] = {
 	{ X86_INS_RSQRTPS, "rsqrtps" },
 	{ X86_INS_RSQRTSS, "rsqrtss" },
 	{ X86_INS_SAHF, "sahf" },
+	{ X86_INS_SALC, "salc" },
 	{ X86_INS_SAR, "sar" },
 	{ X86_INS_SARX, "sarx" },
 	{ X86_INS_SBB, "sbb" },
@@ -2258,6 +2262,7 @@ static insn_map insns[] = {
 	{ X86_FRSTORm, X86_INS_FRSTOR, { 0 }, { 0 }, { 0 }, 0, 0 },
 	{ X86_FSAVEm, X86_INS_FNSAVE, { 0 }, { 0 }, { 0 }, 0, 0 },
 	{ X86_FSCALE, X86_INS_FSCALE, { 0 }, { 0 }, { 0 }, 0, 0 },
+	{ X86_FSETPM, X86_INS_FSETPM, { 0 }, { 0 }, { 0 }, 0, 0 },
 	{ X86_FSINCOS, X86_INS_FSINCOS, { 0 }, { 0 }, { 0 }, 0, 0 },
 	{ X86_FSTENVm, X86_INS_FNSTENV, { 0 }, { 0 }, { 0 }, 0, 0 },
 	{ X86_FS_PREFIX, X86_INS_FS, { 0 }, { 0 }, { 0 }, 0, 0 },
@@ -2289,6 +2294,7 @@ static insn_map insns[] = {
 	{ X86_FsXORPDrr, X86_INS_XORPD, { 0 }, { 0 }, { X86_GRP_SSE2, 0 }, 0, 0 },
 	{ X86_FsXORPSrm, X86_INS_XORPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
 	{ X86_FsXORPSrr, X86_INS_XORPS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
+	{ X86_GETSEC, X86_INS_GETSEC, { X86_REG_EAX, 0 }, { 0 }, { 0 }, 0, 0 },
 	{ X86_GS_PREFIX, X86_INS_GS, { 0 }, { 0 }, { 0 }, 0, 0 },
 	{ X86_HADDPDrm, X86_INS_HADDPD, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
 	{ X86_HADDPDrr, X86_INS_HADDPD, { 0 }, { 0 }, { X86_GRP_SSE3, 0 }, 0, 0 },
@@ -2364,6 +2370,7 @@ static insn_map insns[] = {
 	{ X86_INSERTQ, X86_INS_INSERTQ, { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 },
 	{ X86_INSERTQI, X86_INS_INSERTQ, { 0 }, { 0 }, { X86_GRP_SSE4A, 0 }, 0, 0 },
 	{ X86_INT, X86_INS_INT, { 0 }, { 0 }, { 0 }, 0, 0 },
+	{ X86_INT1, X86_INS_INT1, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
 	{ X86_INT3, X86_INS_INT3, { 0 }, { 0 }, { 0 }, 0, 0 },
 	{ X86_INTO, X86_INS_INTO, { X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 0, 0 },
 	{ X86_INVD, X86_INS_INVD, { 0 }, { 0 }, { 0 }, 0, 0 },
@@ -3735,6 +3742,7 @@ static insn_map insns[] = {
 	{ X86_RSQRTSSr, X86_INS_RSQRTSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
 	{ X86_RSQRTSSr_Int, X86_INS_RSQRTSS, { 0 }, { 0 }, { X86_GRP_SSE1, 0 }, 0, 0 },
 	{ X86_SAHF, X86_INS_SAHF, { X86_REG_AH, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
+	{ X86_SALC, X86_INS_SALC, { X86_REG_EFLAGS, 0 }, { X86_REG_AL, 0 }, { 0 }, 0, 0 },
 	{ X86_SAR16m1, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
 	{ X86_SAR16mCL, X86_INS_SAR, { X86_REG_CL, 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },
 	{ X86_SAR16mi, X86_INS_SAR, { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 },

include/x86.h

@@ -339,6 +339,7 @@ typedef enum  x86_insn {
 	X86_INS_FRSTOR,
 	X86_INS_FNSAVE,
 	X86_INS_FSCALE,
+	X86_INS_FSETPM,
 	X86_INS_FSINCOS,
 	X86_INS_FNSTENV,
 	X86_INS_FS,
@@ -358,6 +359,7 @@ typedef enum  x86_insn {
 	X86_INS_VMOVAPS,
 	X86_INS_XORPD,
 	X86_INS_XORPS,
+	X86_INS_GETSEC,
 	X86_INS_GS,
 	X86_INS_HADDPD,
 	X86_INS_HADDPS,
@@ -373,6 +375,7 @@ typedef enum  x86_insn {
 	X86_INS_INSERTPS,
 	X86_INS_INSERTQ,
 	X86_INS_INT,
+	X86_INS_INT1,
 	X86_INS_INT3,
 	X86_INS_INTO,
 	X86_INS_INVD,
@@ -742,6 +745,7 @@ typedef enum  x86_insn {
 	X86_INS_RSQRTPS,
 	X86_INS_RSQRTSS,
 	X86_INS_SAHF,
+	X86_INS_SALC,
 	X86_INS_SAR,
 	X86_INS_SARX,
 	X86_INS_SBB,