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Merge branch 'improvement/remove_mips_n64' of https://github.com/parasyte/capstone into mips

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test2
Nguyen Anh Quynh 10 years ago
parent a91c1994ea 79e253c516
commit 8c5c292752
8 changed files with 27 additions and 40 deletions
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  1. 2
      arch/Mips/MipsDisassembler.c
  2. 2
      arch/Mips/MipsModule.c
  3. 8
      bindings/java/capstone/Capstone.java
  4. 2
      bindings/ocaml/capstone.ml
  5. 22
      bindings/ocaml/ocaml.c
  6. 8
      bindings/python/capstone/__init__.py
  7. 7
      include/capstone.h
  8. 2
      suite/MC/Mips/nabi-regs.s.cs

2
arch/Mips/MipsDisassembler.c
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@ -767,7 +767,7 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
if (Inst->csh->mode & CS_MODE_N64)
if (Inst->csh->mode & CS_MODE_64)
return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);

2
arch/Mips/MipsModule.c
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@ -15,7 +15,7 @@ static cs_err init(cs_struct *ud)
// verify if requested mode is valid
if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 |
CS_MODE_MICRO | CS_MODE_N64 | CS_MODE_BIG_ENDIAN))
CS_MODE_MICRO | CS_MODE_BIG_ENDIAN))
return CS_ERR_MODE;
mri = cs_mem_malloc(sizeof(*mri));

8
bindings/java/capstone/Capstone.java
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@ -297,10 +297,9 @@ public class Capstone {
public static final int CS_MODE_THUMB = 1 << 4; // ARM's Thumb mode, including Thumb-2
public static final int CS_MODE_MCLASS = 1 << 5; // ARM's Cortex-M series
public static final int CS_MODE_MICRO = 1 << 4; // MicroMips mode (Mips arch)
public static final int CS_MODE_N64 = 1 << 5; // Nintendo-64 mode (Mips arch)
public static final int CS_MODE_MIPS3 = 1 << 6; // Mips III ISA
public static final int CS_MODE_MIPS32R6 = 1 << 7; // Mips32r6 ISA
public static final int CS_MODE_MIPSGP64 = 1 << 8; // General Purpose Registers are 64-bit wide (MIPS arch)
public static final int CS_MODE_MIPS3 = 1 << 5; // Mips III ISA
public static final int CS_MODE_MIPS32R6 = 1 << 6; // Mips32r6 ISA
public static final int CS_MODE_MIPSGP64 = 1 << 7; // General Purpose Registers are 64-bit wide (MIPS arch)
public static final int CS_MODE_BIG_ENDIAN = 1 << 31;
public static final int CS_MODE_V9 = 1 << 4; // SparcV9 mode (Sparc arch)
@ -427,4 +426,3 @@ public class Capstone {
return allInsn;
}
}

2
bindings/ocaml/capstone.ml
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@ -30,7 +30,6 @@ type mode =
| CS_MODE_THUMB (* ARM's Thumb mode, including Thumb-2 *)
| CS_MODE_MCLASS (* ARM's MClass mode *)
| CS_MODE_MICRO (* MicroMips mode (MIPS architecture) *)
| CS_MODE_N64 (* Nintendo-64 mode (MIPS architecture) *)
| CS_MODE_MIPS3 (* Mips3 mode (MIPS architecture) *)
| CS_MODE_MIPS32R6 (* Mips32-R6 mode (MIPS architecture) *)
| CS_MODE_MIPSGP64 (* MipsGP64 mode (MIPS architecture) *)
@ -168,4 +167,3 @@ class cs a m =
List.map (fun x -> new cs_insn handle x) insns;
end;;

22
bindings/ocaml/ocaml.c
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@ -680,21 +680,18 @@ CAMLprim value ocaml_cs_disasm(value _arch, value _mode, value _code, value _add
mode |= CS_MODE_MICRO;
break;
case 8:
mode |= CS_MODE_N64;
break;
case 9:
mode |= CS_MODE_MIPS3;
break;
case 10:
case 9:
mode |= CS_MODE_MIPS32R6;
break;
case 11:
case 10:
mode |= CS_MODE_MIPSGP64;
break;
case 12:
case 11:
mode |= CS_MODE_V9;
break;
case 13:
case 12:
mode |= CS_MODE_BIG_ENDIAN;
break;
default:
@ -805,21 +802,18 @@ CAMLprim value ocaml_open(value _arch, value _mode)
mode |= CS_MODE_MICRO;
break;
case 8:
mode |= CS_MODE_N64;
break;
case 9:
mode |= CS_MODE_MIPS3;
break;
case 10:
case 9:
mode |= CS_MODE_MIPS32R6;
break;
case 11:
case 10:
mode |= CS_MODE_MIPSGP64;
break;
case 12:
case 11:
mode |= CS_MODE_V9;
break;
case 13:
case 12:
mode |= CS_MODE_BIG_ENDIAN;
break;
default:

8
bindings/python/capstone/__init__.py
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@ -38,7 +38,6 @@ __all__ = [
'CS_MODE_THUMB',
'CS_MODE_MCLASS',
'CS_MODE_MICRO',
'CS_MODE_N64',
'CS_MODE_MIPS3',
'CS_MODE_MIPS32R6',
'CS_MODE_MIPSGP64',
@ -104,10 +103,9 @@ CS_MODE_64 = (1 << 3) # 64-bit mode (for X86, Mips)
CS_MODE_THUMB = (1 << 4) # ARM's Thumb mode, including Thumb-2
CS_MODE_MCLASS = (1 << 5) # ARM's Cortex-M series
CS_MODE_MICRO = (1 << 4) # MicroMips mode (MIPS architecture)
CS_MODE_N64 = (1 << 5) # Nintendo-64 mode (MIPS architecture)
CS_MODE_MIPS3 = 1 << 6 # Mips III ISA
CS_MODE_MIPS32R6 = 1 << 7 # Mips32r6 ISA
CS_MODE_MIPSGP64 = 1 << 8 # General Purpose Registers are 64-bit wide (MIPS arch)
CS_MODE_MIPS3 = (1 << 5) # Mips III ISA
CS_MODE_MIPS32R6 = (1 << 6) # Mips32r6 ISA
CS_MODE_MIPSGP64 = (1 << 7) # General Purpose Registers are 64-bit wide (MIPS arch)
CS_MODE_V9 = (1 << 4) # Nintendo-64 mode (MIPS architecture)
CS_MODE_BIG_ENDIAN = (1 << 31) # big-endian mode

7
include/capstone.h
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@ -81,10 +81,9 @@ typedef enum cs_mode {
CS_MODE_THUMB = 1 << 4, // ARM's Thumb mode, including Thumb-2
CS_MODE_MCLASS = 1 << 5, // ARM's Cortex-M series
CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS architecture)
CS_MODE_N64 = 1 << 5, // Nintendo-64 mode (MIPS architecture)
CS_MODE_MIPS3 = 1 << 6, // Mips III ISA
CS_MODE_MIPS32R6 = 1 << 7, // Mips32r6 ISA
CS_MODE_MIPSGP64 = 1 << 8, // General Purpose Registers are 64-bit wide (MIPS arch)
CS_MODE_MIPS3 = 1 << 5, // Mips III ISA
CS_MODE_MIPS32R6 = 1 << 6, // Mips32r6 ISA
CS_MODE_MIPSGP64 = 1 << 7, // General Purpose Registers are 64-bit wide (MIPS arch)
CS_MODE_V9 = 1 << 4, // SparcV9 mode (Sparc architecture)
CS_MODE_BIG_ENDIAN = 1 << 31 // big endian mode
} cs_mode;

2
suite/MC/Mips/nabi-regs.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_64+CS_MODE_BIG_ENDIAN+CS_MODE_N64, None
# CS_ARCH_MIPS, CS_MODE_64+CS_MODE_BIG_ENDIAN, None
0x02,0x04,0x80,0x20 = add $16, $16, $4
0x02,0x06,0x80,0x20 = add $16, $16, $6
0x02,0x07,0x80,0x20 = add $16, $16, $7

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