diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c
index 8814ee36..c5fb19e9 100644
--- a/arch/Mips/MipsDisassembler.c
+++ b/arch/Mips/MipsDisassembler.c
@@ -265,11 +265,11 @@ void Mips_init(MCRegisterInfo *MRI)
 	// 		MipsRegEncodingTable);
 
 	MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 394,
-			0, 0, 
+			0, 0,
 			MipsMCRegisterClasses, 48,
-			0, 0, 
+			0, 0,
 			MipsRegDiffLists,
-			0, 
+			0,
 			MipsSubRegIdxLists, 12,
 			0);
 }
@@ -767,7 +767,7 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
 static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
 		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
 {
-	if (Inst->csh->mode & CS_MODE_N64)
+	if (Inst->csh->mode & CS_MODE_64)
 		return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 
 	return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
diff --git a/arch/Mips/MipsModule.c b/arch/Mips/MipsModule.c
index 46867993..0fe1eab3 100644
--- a/arch/Mips/MipsModule.c
+++ b/arch/Mips/MipsModule.c
@@ -15,7 +15,7 @@ static cs_err init(cs_struct *ud)
 
 	// verify if requested mode is valid
 	if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 |
-				CS_MODE_MICRO | CS_MODE_N64 | CS_MODE_BIG_ENDIAN))
+				CS_MODE_MICRO | CS_MODE_BIG_ENDIAN))
 		return CS_ERR_MODE;
 
 	mri = cs_mem_malloc(sizeof(*mri));
diff --git a/bindings/java/capstone/Capstone.java b/bindings/java/capstone/Capstone.java
index aeb3d436..e1c4bdf1 100644
--- a/bindings/java/capstone/Capstone.java
+++ b/bindings/java/capstone/Capstone.java
@@ -297,10 +297,9 @@ public class Capstone {
   public static final int CS_MODE_THUMB = 1 << 4;	  // ARM's Thumb mode, including Thumb-2
   public static final int CS_MODE_MCLASS = 1 << 5;	  // ARM's Cortex-M series
   public static final int CS_MODE_MICRO = 1 << 4;	  // MicroMips mode (Mips arch)
-  public static final int CS_MODE_N64 = 1 << 5;	      // Nintendo-64 mode (Mips arch)
-  public static final int CS_MODE_MIPS3 = 1 << 6;     // Mips III ISA
-  public static final int CS_MODE_MIPS32R6 = 1 << 7;  // Mips32r6 ISA
-  public static final int CS_MODE_MIPSGP64 = 1 << 8;  // General Purpose Registers are 64-bit wide (MIPS arch)
+  public static final int CS_MODE_MIPS3 = 1 << 5;     // Mips III ISA
+  public static final int CS_MODE_MIPS32R6 = 1 << 6;  // Mips32r6 ISA
+  public static final int CS_MODE_MIPSGP64 = 1 << 7;  // General Purpose Registers are 64-bit wide (MIPS arch)
   public static final int CS_MODE_BIG_ENDIAN = 1 << 31;
   public static final int CS_MODE_V9 = 1 << 4;	      // SparcV9 mode (Sparc arch)
 
@@ -427,4 +426,3 @@ public class Capstone {
     return allInsn;
   }
 }
-
diff --git a/bindings/ocaml/capstone.ml b/bindings/ocaml/capstone.ml
index 79e14606..d3127bca 100644
--- a/bindings/ocaml/capstone.ml
+++ b/bindings/ocaml/capstone.ml
@@ -30,7 +30,6 @@ type mode =
   |	CS_MODE_THUMB		(* ARM's Thumb mode, including Thumb-2 *)
   |	CS_MODE_MCLASS		(* ARM's MClass mode *)
   |	CS_MODE_MICRO		(* MicroMips mode (MIPS architecture) *)
-  |	CS_MODE_N64			(* Nintendo-64 mode (MIPS architecture) *)
   |	CS_MODE_MIPS3		(* Mips3 mode (MIPS architecture) *)
   |	CS_MODE_MIPS32R6	(* Mips32-R6 mode (MIPS architecture) *)
   |	CS_MODE_MIPSGP64	(* MipsGP64 mode (MIPS architecture) *)
@@ -55,7 +54,7 @@ let _CS_OPT_SYNTAX_ATT = 2L;; (* X86 ATT asm syntax (CS_OPT_SYNTAX). *)
 let _CS_OPT_SYNTAX_NOREGNAME = 3L;; (* Prints register name with only number (CS_OPT_SYNTAX) *)
 
 
-type cs_arch = 
+type cs_arch =
 	| CS_INFO_ARM of cs_arm
 	| CS_INFO_ARM64 of cs_arm64
 	| CS_INFO_MIPS of cs_mips
@@ -168,4 +167,3 @@ class cs a m =
 			List.map (fun x -> new cs_insn handle x) insns;
 
 	end;;
-
diff --git a/bindings/ocaml/ocaml.c b/bindings/ocaml/ocaml.c
index 0458a17b..51f7d150 100644
--- a/bindings/ocaml/ocaml.c
+++ b/bindings/ocaml/ocaml.c
@@ -47,7 +47,7 @@ CAMLprim value _cs_disasm(cs_arch arch, csh handle, const uint8_t * code, size_t
 			Store_field(rec_insn, 0, Val_int(insn[j-1].id));
 			Store_field(rec_insn, 1, Val_int(insn[j-1].address));
 			Store_field(rec_insn, 2, Val_int(insn[j-1].size));
-			
+
 			// copy raw bytes of instruction
 			lcount = insn[j-1].size;
 			if (lcount) {
@@ -680,21 +680,18 @@ CAMLprim value ocaml_cs_disasm(value _arch, value _mode, value _code, value _add
 				mode |= CS_MODE_MICRO;
 				break;
 			case 8:
-				mode |= CS_MODE_N64;
-				break;
-			case 9:
 				mode |= CS_MODE_MIPS3;
 				break;
-			case 10:
+			case 9:
 				mode |= CS_MODE_MIPS32R6;
 				break;
-			case 11:
+			case 10:
 				mode |= CS_MODE_MIPSGP64;
 				break;
-			case 12:
+			case 11:
 				mode |= CS_MODE_V9;
 				break;
-			case 13:
+			case 12:
 				mode |= CS_MODE_BIG_ENDIAN;
 				break;
 			default:
@@ -726,7 +723,7 @@ CAMLprim value ocaml_cs_disasm_internal(value _arch, value _handle, value _code,
 	uint64_t addr, count, code_len;
 
 	handle = Int64_val(_handle);
-	
+
 	arch = Int_val(_arch);
 	code = (uint8_t *)String_val(_code);
 	code_len = caml_string_length(_code);
@@ -805,21 +802,18 @@ CAMLprim value ocaml_open(value _arch, value _mode)
 				mode |= CS_MODE_MICRO;
 				break;
 			case 8:
-				mode |= CS_MODE_N64;
-				break;
-			case 9:
 				mode |= CS_MODE_MIPS3;
 				break;
-			case 10:
+			case 9:
 				mode |= CS_MODE_MIPS32R6;
 				break;
-			case 11:
+			case 10:
 				mode |= CS_MODE_MIPSGP64;
 				break;
-			case 12:
+			case 11:
 				mode |= CS_MODE_V9;
 				break;
-			case 13:
+			case 12:
 				mode |= CS_MODE_BIG_ENDIAN;
 				break;
 			default:
@@ -829,7 +823,7 @@ CAMLprim value ocaml_open(value _arch, value _mode)
 		_mode = Field(_mode, 1);  /* point to the tail for next loop */
 	}
 
-	if (cs_open(arch, mode, &handle) != 0) 
+	if (cs_open(arch, mode, &handle) != 0)
 		CAMLreturn(Val_int(0));
 
 	CAMLlocal1(result);
diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py
index 9b0f91a7..8c0bc4f8 100644
--- a/bindings/python/capstone/__init__.py
+++ b/bindings/python/capstone/__init__.py
@@ -38,7 +38,6 @@ __all__ = [
     'CS_MODE_THUMB',
     'CS_MODE_MCLASS',
     'CS_MODE_MICRO',
-    'CS_MODE_N64',
     'CS_MODE_MIPS3',
     'CS_MODE_MIPS32R6',
     'CS_MODE_MIPSGP64',
@@ -104,10 +103,9 @@ CS_MODE_64 = (1 << 3)          # 64-bit mode (for X86, Mips)
 CS_MODE_THUMB = (1 << 4)       # ARM's Thumb mode, including Thumb-2
 CS_MODE_MCLASS = (1 << 5)      # ARM's Cortex-M series
 CS_MODE_MICRO = (1 << 4)       # MicroMips mode (MIPS architecture)
-CS_MODE_N64 = (1 << 5)         # Nintendo-64 mode (MIPS architecture)
-CS_MODE_MIPS3 = 1 << 6         # Mips III ISA
-CS_MODE_MIPS32R6 = 1 << 7      # Mips32r6 ISA
-CS_MODE_MIPSGP64 = 1 << 8      # General Purpose Registers are 64-bit wide (MIPS arch)
+CS_MODE_MIPS3 = (1 << 5)       # Mips III ISA
+CS_MODE_MIPS32R6 = (1 << 6)    # Mips32r6 ISA
+CS_MODE_MIPSGP64 = (1 << 7)    # General Purpose Registers are 64-bit wide (MIPS arch)
 CS_MODE_V9 = (1 << 4)          # Nintendo-64 mode (MIPS architecture)
 CS_MODE_BIG_ENDIAN = (1 << 31) # big-endian mode
 
diff --git a/include/capstone.h b/include/capstone.h
index fa4144a7..81863e5d 100644
--- a/include/capstone.h
+++ b/include/capstone.h
@@ -81,10 +81,9 @@ typedef enum cs_mode {
 	CS_MODE_THUMB = 1 << 4,	// ARM's Thumb mode, including Thumb-2
 	CS_MODE_MCLASS = 1 << 5,	// ARM's Cortex-M series
 	CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS architecture)
-	CS_MODE_N64 = 1 << 5, // Nintendo-64 mode (MIPS architecture)
-	CS_MODE_MIPS3 = 1 << 6, // Mips III ISA
-	CS_MODE_MIPS32R6 = 1 << 7, // Mips32r6 ISA
-	CS_MODE_MIPSGP64 = 1 << 8, // General Purpose Registers are 64-bit wide (MIPS arch)
+	CS_MODE_MIPS3 = 1 << 5, // Mips III ISA
+	CS_MODE_MIPS32R6 = 1 << 6, // Mips32r6 ISA
+	CS_MODE_MIPSGP64 = 1 << 7, // General Purpose Registers are 64-bit wide (MIPS arch)
 	CS_MODE_V9 = 1 << 4, // SparcV9 mode (Sparc architecture)
 	CS_MODE_BIG_ENDIAN = 1 << 31	// big endian mode
 } cs_mode;
diff --git a/suite/MC/Mips/nabi-regs.s.cs b/suite/MC/Mips/nabi-regs.s.cs
index 1145d9e9..0cb3dc8a 100644
--- a/suite/MC/Mips/nabi-regs.s.cs
+++ b/suite/MC/Mips/nabi-regs.s.cs
@@ -1,4 +1,4 @@
-# CS_ARCH_MIPS, CS_MODE_64+CS_MODE_BIG_ENDIAN+CS_MODE_N64, None
+# CS_ARCH_MIPS, CS_MODE_64+CS_MODE_BIG_ENDIAN, None
 0x02,0x04,0x80,0x20 = add $16, $16, $4
 0x02,0x06,0x80,0x20 = add $16, $16, $6
 0x02,0x07,0x80,0x20 = add $16, $16, $7