ppc: handle branch condition for alias instructions. this also updates Python & Java bindings

test2
Nguyen Anh Quynh 11 years ago
parent 9d6383973f
commit 7e57e79800
  1. 53
      arch/PowerPC/PPCInstPrinter.c
  2. 179
      arch/PowerPC/PPCMapping.c
  3. 9
      arch/PowerPC/PPCMapping.h
  4. 29
      bindings/java/capstone/Ppc_const.java
  5. 29
      bindings/python/capstone/ppc_const.py
  6. 33
      include/ppc.h
  7. 2
      tests/test_detail.c
  8. 2
      tests/test_ppc.c

@ -146,23 +146,72 @@ void PPC_printInst(MCInst *MI, SStream *O, void *Info)
mnem = printAliasInstr(MI, O, Info);
if (mnem) {
struct ppc_alias alias;
// check to remove the last letter of ('.', '-', '+')
if (mnem[strlen(mnem) - 1] == '-' || mnem[strlen(mnem) - 1] == '+' || mnem[strlen(mnem) - 1] == '.')
mnem[strlen(mnem) - 1] = '\0';
MCInst_setOpcodePub(MI, PPC_map_insn(mnem));
if (PPC_alias_insn(mnem, &alias)) {
MCInst_setOpcodePub(MI, alias.id);
if (MI->csh->detail) {
MI->flat_insn->detail->ppc.bc = (ppc_bc)alias.cc;
}
}
cs_mem_free(mnem);
} else
printInstruction(MI, O, NULL);
}
enum ppc_bc_hint {
PPC_BC_LT_MINUS = (0 << 5) | 14,
PPC_BC_LE_MINUS = (1 << 5) | 6,
PPC_BC_EQ_MINUS = (2 << 5) | 14,
PPC_BC_GE_MINUS = (0 << 5) | 6,
PPC_BC_GT_MINUS = (1 << 5) | 14,
PPC_BC_NE_MINUS = (2 << 5) | 6,
PPC_BC_UN_MINUS = (3 << 5) | 14,
PPC_BC_NU_MINUS = (3 << 5) | 6,
PPC_BC_LT_PLUS = (0 << 5) | 15,
PPC_BC_LE_PLUS = (1 << 5) | 7,
PPC_BC_EQ_PLUS = (2 << 5) | 15,
PPC_BC_GE_PLUS = (0 << 5) | 7,
PPC_BC_GT_PLUS = (1 << 5) | 15,
PPC_BC_NE_PLUS = (2 << 5) | 7,
PPC_BC_UN_PLUS = (3 << 5) | 15,
PPC_BC_NU_PLUS = (3 << 5) | 7,
};
// normalize CC to remove _MINUS & _PLUS
static int cc_normalize(int cc)
{
switch(cc) {
default: return cc;
case PPC_BC_LT_MINUS: return PPC_BC_LT;
case PPC_BC_LE_MINUS: return PPC_BC_LE;
case PPC_BC_EQ_MINUS: return PPC_BC_EQ;
case PPC_BC_GE_MINUS: return PPC_BC_GE;
case PPC_BC_GT_MINUS: return PPC_BC_GT;
case PPC_BC_NE_MINUS: return PPC_BC_NE;
case PPC_BC_UN_MINUS: return PPC_BC_UN;
case PPC_BC_NU_MINUS: return PPC_BC_NU;
case PPC_BC_LT_PLUS : return PPC_BC_LT;
case PPC_BC_LE_PLUS : return PPC_BC_LE;
case PPC_BC_EQ_PLUS : return PPC_BC_EQ;
case PPC_BC_GE_PLUS : return PPC_BC_GE;
case PPC_BC_GT_PLUS : return PPC_BC_GT;
case PPC_BC_NE_PLUS : return PPC_BC_NE;
case PPC_BC_UN_PLUS : return PPC_BC_UN;
case PPC_BC_NU_PLUS : return PPC_BC_NU;
}
}
static void printPredicateOperand(MCInst *MI, unsigned OpNo,
SStream *O, const char *Modifier)
{
unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
MI->flat_insn->detail->ppc.bc = (ppc_bc)Code;
MI->flat_insn->detail->ppc.bc = (ppc_bc)cc_normalize(Code);
if (!strcmp(Modifier, "cc")) {
switch ((ppc_predicate)Code) {

@ -491,61 +491,61 @@ static insn_map insns[] = {
#endif
},
{
PPC_BCC, PPC_INS_B_CC,
PPC_BCC, PPC_INS_B,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 1, 0
#endif
},
{
PPC_BCCA, PPC_INS_BA_CC,
PPC_BCCA, PPC_INS_BA,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 1, 0
#endif
},
{
PPC_BCCCTR, PPC_INS_BCTR_CC,
PPC_BCCCTR, PPC_INS_BCTR,
#ifndef CAPSTONE_DIET
{ PPC_REG_CTR, 0 }, { 0 }, { 0 }, 1, 1
#endif
},
{
PPC_BCCCTR8, PPC_INS_BCTR_CC,
PPC_BCCCTR8, PPC_INS_BCTR,
#ifndef CAPSTONE_DIET
{ PPC_REG_CTR8, 0 }, { 0 }, { PPC_GRP_MODE64, 0 }, 1, 1
#endif
},
{
PPC_BCCCTRL, PPC_INS_BCTRL_CC,
PPC_BCCCTRL, PPC_INS_BCTRL,
#ifndef CAPSTONE_DIET
{ PPC_REG_CTR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0
#endif
},
{
PPC_BCCCTRL8, PPC_INS_BCTRL_CC,
PPC_BCCCTRL8, PPC_INS_BCTRL,
#ifndef CAPSTONE_DIET
{ PPC_REG_CTR8, PPC_REG_RM, 0 }, { PPC_REG_LR8, 0 }, { PPC_GRP_MODE64, 0 }, 0, 0
#endif
},
{
PPC_BCCL, PPC_INS_BL_CC,
PPC_BCCL, PPC_INS_BL,
#ifndef CAPSTONE_DIET
{ PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0
#endif
},
{
PPC_BCCLA, PPC_INS_BLA_CC,
PPC_BCCLA, PPC_INS_BLA,
#ifndef CAPSTONE_DIET
{ PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0
#endif
},
{
PPC_BCCLR, PPC_INS_BLR_CC,
PPC_BCCLR, PPC_INS_BLR,
#ifndef CAPSTONE_DIET
{ PPC_REG_LR, PPC_REG_RM, 0 }, { 0 }, { 0 }, 1, 0
#endif
},
{
PPC_BCCLRL, PPC_INS_BLRL_CC,
PPC_BCCLRL, PPC_INS_BLRL,
#ifndef CAPSTONE_DIET
{ PPC_REG_LR, PPC_REG_RM, 0 }, { PPC_REG_LR, 0 }, { 0 }, 0, 0
#endif
@ -7862,19 +7862,6 @@ static name_map insn_name_maps[] = {
{ PPC_INS_BDNZFLRL, "bdnzflrl" },
{ PPC_INS_BDZTLRL, "bdztlrl" },
{ PPC_INS_BDZFLRL, "bdzflrl" },
// BccX
{ PPC_INS_B_CC, "b_cc" },
{ PPC_INS_BL_CC, "bl_cc" },
{ PPC_INS_BLA_CC, "bla_cc" },
{ PPC_INS_BLR_CC, "blr_cc" },
{ PPC_INS_BLRL_CC, "blrl_cc" },
{ PPC_INS_BA_CC, "ba_cc" },
{ PPC_INS_BCTR_CC, "bctr_cc" },
{ PPC_INS_BCTRL_CC, "bctrl_cc" },
// alias instructions
{ PPC_INS_BNE, "bne" },
};
// special alias insn
@ -8001,58 +7988,120 @@ ppc_reg PPC_map_register(unsigned int r)
return 0;
}
static name_map alias_insn_name_maps[] = {
{ PPC_INS_BTA, "bta" },
{ PPC_INS_B, "blt" },
{ PPC_INS_B, "bgt" },
{ PPC_INS_B, "beq" },
{ PPC_INS_B, "bne" },
static struct ppc_alias alias_insn_name_maps[] = {
//{ PPC_INS_BTA, "bta" },
{ PPC_INS_B, PPC_BC_LT, "blt" },
{ PPC_INS_B, PPC_BC_LE, "ble" },
{ PPC_INS_B, PPC_BC_EQ, "beq" },
{ PPC_INS_B, PPC_BC_GE, "bge" },
{ PPC_INS_B, PPC_BC_GT, "bgt" },
{ PPC_INS_B, PPC_BC_NE, "bne" },
{ PPC_INS_B, PPC_BC_UN, "bun" },
{ PPC_INS_B, PPC_BC_NU, "bnu" },
{ PPC_INS_B, PPC_BC_SO, "bso" },
{ PPC_INS_B, PPC_BC_NS, "bns" },
{ PPC_INS_BA_CC, "blta" },
{ PPC_INS_BA_CC, "bgta" },
{ PPC_INS_BA_CC, "beqa" },
{ PPC_INS_BA_CC, "bnea" },
{ PPC_INS_BA, PPC_BC_LT, "blta" },
{ PPC_INS_BA, PPC_BC_LE, "blea" },
{ PPC_INS_BA, PPC_BC_EQ, "beqa" },
{ PPC_INS_BA, PPC_BC_GE, "bgea" },
{ PPC_INS_BA, PPC_BC_GT, "bgta" },
{ PPC_INS_BA, PPC_BC_NE, "bnea" },
{ PPC_INS_BA, PPC_BC_UN, "buna" },
{ PPC_INS_BA, PPC_BC_NU, "bnua" },
{ PPC_INS_BA, PPC_BC_SO, "bsoa" },
{ PPC_INS_BA, PPC_BC_NS, "bnsa" },
{ PPC_INS_BCTR_CC, "bltctr" },
{ PPC_INS_BCTR_CC, "bgtctr" },
{ PPC_INS_BCTR_CC, "beqctr" },
{ PPC_INS_BCTR_CC, "bnectr" },
{ PPC_INS_BCTR, PPC_BC_LT, "bltctr" },
{ PPC_INS_BCTR, PPC_BC_LE, "blectr" },
{ PPC_INS_BCTR, PPC_BC_EQ, "beqctr" },
{ PPC_INS_BCTR, PPC_BC_GE, "bgectr" },
{ PPC_INS_BCTR, PPC_BC_GT, "bgtctr" },
{ PPC_INS_BCTR, PPC_BC_NE, "bnectr" },
{ PPC_INS_BCTR, PPC_BC_UN, "bunctr" },
{ PPC_INS_BCTR, PPC_BC_NU, "bnuctr" },
{ PPC_INS_BCTR, PPC_BC_SO, "bsoctr" },
{ PPC_INS_BCTR, PPC_BC_NS, "bnsctr" },
{ PPC_INS_BCTRL_CC, "bltctrl" },
{ PPC_INS_BCTRL_CC, "bgtctrl" },
{ PPC_INS_BCTRL_CC, "beqctrl" },
{ PPC_INS_BCTRL_CC, "bnectrl" },
{ PPC_INS_BCTRL, PPC_BC_LT, "bltctrl" },
{ PPC_INS_BCTRL, PPC_BC_LE, "blectrl" },
{ PPC_INS_BCTRL, PPC_BC_EQ, "beqctrl" },
{ PPC_INS_BCTRL, PPC_BC_GE, "bgectrl" },
{ PPC_INS_BCTRL, PPC_BC_GT, "bgtctrl" },
{ PPC_INS_BCTRL, PPC_BC_NE, "bnectrl" },
{ PPC_INS_BCTRL, PPC_BC_UN, "bunctrl" },
{ PPC_INS_BCTRL, PPC_BC_NU, "bnuctrl" },
{ PPC_INS_BCTRL, PPC_BC_SO, "bsoctrl" },
{ PPC_INS_BCTRL, PPC_BC_NS, "bnsctrl" },
{ PPC_INS_BL_CC, "bltl" },
{ PPC_INS_BL_CC, "bgtl" },
{ PPC_INS_BL_CC, "beql" },
{ PPC_INS_BL_CC, "bnel" },
{ PPC_INS_BL, PPC_BC_LT, "bltl" },
{ PPC_INS_BL, PPC_BC_LE, "blel" },
{ PPC_INS_BL, PPC_BC_EQ, "beql" },
{ PPC_INS_BL, PPC_BC_GE, "bgel" },
{ PPC_INS_BL, PPC_BC_GT, "bgtl" },
{ PPC_INS_BL, PPC_BC_NE, "bnel" },
{ PPC_INS_BL, PPC_BC_UN, "bunl" },
{ PPC_INS_BL, PPC_BC_NU, "bnul" },
{ PPC_INS_BL, PPC_BC_SO, "bsol" },
{ PPC_INS_BL, PPC_BC_NS, "bnsl" },
{ PPC_INS_BLA_CC, "bltla" },
{ PPC_INS_BLA_CC, "bgtla" },
{ PPC_INS_BLA_CC, "beqla" },
{ PPC_INS_BLA_CC, "bnela" },
{ PPC_INS_BLA, PPC_BC_LT, "bltla" },
{ PPC_INS_BLA, PPC_BC_LE, "blela" },
{ PPC_INS_BLA, PPC_BC_EQ, "beqla" },
{ PPC_INS_BLA, PPC_BC_GE, "bgela" },
{ PPC_INS_BLA, PPC_BC_GT, "bgtla" },
{ PPC_INS_BLA, PPC_BC_NE, "bnela" },
{ PPC_INS_BLA, PPC_BC_UN, "bunla" },
{ PPC_INS_BLA, PPC_BC_NU, "bnula" },
{ PPC_INS_BLA, PPC_BC_SO, "bsola" },
{ PPC_INS_BLA, PPC_BC_NS, "bnsla" },
{ PPC_INS_BLR_CC, "bltlr" },
{ PPC_INS_BLR_CC, "bgtlr" },
{ PPC_INS_BLR_CC, "beqlr" },
{ PPC_INS_BLR_CC, "bnelr" },
{ PPC_INS_BLR, PPC_BC_LT, "bltlr" },
{ PPC_INS_BLR, PPC_BC_LE, "blelr" },
{ PPC_INS_BLR, PPC_BC_EQ, "beqlr" },
{ PPC_INS_BLR, PPC_BC_GE, "bgelr" },
{ PPC_INS_BLR, PPC_BC_GT, "bgtlr" },
{ PPC_INS_BLR, PPC_BC_NE, "bnelr" },
{ PPC_INS_BLR, PPC_BC_UN, "bunlr" },
{ PPC_INS_BLR, PPC_BC_NU, "bnulr" },
{ PPC_INS_BLR, PPC_BC_SO, "bsolr" },
{ PPC_INS_BLR, PPC_BC_NS, "bnslr" },
{ PPC_INS_BLRL_CC, "bltlrl" },
{ PPC_INS_BLRL_CC, "bgtlrl" },
{ PPC_INS_BLRL_CC, "beqlrl" },
{ PPC_INS_BLRL_CC, "bnelrl" },
{ PPC_INS_BLRL, PPC_BC_LT, "bltlrl" },
{ PPC_INS_BLRL, PPC_BC_LE, "blelrl" },
{ PPC_INS_BLRL, PPC_BC_EQ, "beqlrl" },
{ PPC_INS_BLRL, PPC_BC_GE, "bgelrl" },
{ PPC_INS_BLRL, PPC_BC_GT, "bgtlrl" },
{ PPC_INS_BLRL, PPC_BC_NE, "bnelrl" },
{ PPC_INS_BLRL, PPC_BC_UN, "bunlrl" },
{ PPC_INS_BLRL, PPC_BC_NU, "bnulrl" },
{ PPC_INS_BLRL, PPC_BC_SO, "bsolrl" },
{ PPC_INS_BLRL, PPC_BC_NS, "bnslrl" },
};
// map instruction name to public instruction ID
ppc_reg PPC_map_insn(const char *name)
// given alias mnemonic, return instruction ID & CC
bool PPC_alias_insn(const char *name, struct ppc_alias *alias)
{
// NOTE: skip first NULL name in insn_name_maps
int i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name);
int i;
if (i == -1)
// try again with 'special' insn that is not available in insn_name_maps
i = name2id(alias_insn_name_maps, ARR_SIZE(alias_insn_name_maps), name);
for(i = 0; i < ARR_SIZE(alias_insn_name_maps); i++) {
if (!strcmp(name, alias_insn_name_maps[i].mnem)) {
alias->id = alias_insn_name_maps[i].id;
alias->cc = alias_insn_name_maps[i].cc;
return true;
}
}
return (i != -1)? i : PPC_REG_INVALID;
// not really an alias insn
i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name);
if (i) {
alias->id = insn_name_maps[i].id;
alias->cc = PPC_BC_INVALID;
return true;
}
// not found
return false;
}
#endif

@ -18,7 +18,14 @@ const char *PPC_group_name(csh handle, unsigned int id);
// map internal raw register to 'public' register
ppc_reg PPC_map_register(unsigned int r);
ppc_reg PPC_map_insn(const char *name);
struct ppc_alias {
unsigned int id; // instruction id
int cc; // code condition
const char *mnem;
};
// given alias mnemonic, return instruction ID & CC
bool PPC_alias_insn(const char *name, struct ppc_alias *alias);
#endif

@ -14,22 +14,8 @@ public class Ppc_const {
public static final int PPC_BC_NE = (2<<5)|4;
public static final int PPC_BC_UN = (3<<5)|12;
public static final int PPC_BC_NU = (3<<5)|4;
public static final int PPC_BC_LT_MINUS = (0<<5)|14;
public static final int PPC_BC_LE_MINUS = (1<<5)|6;
public static final int PPC_BC_EQ_MINUS = (2<<5)|14;
public static final int PPC_BC_GE_MINUS = (0<<5)|6;
public static final int PPC_BC_GT_MINUS = (1<<5)|14;
public static final int PPC_BC_NE_MINUS = (2<<5)|6;
public static final int PPC_BC_UN_MINUS = (3<<5)|14;
public static final int PPC_BC_NU_MINUS = (3<<5)|6;
public static final int PPC_BC_LT_PLUS = (0<<5)|15;
public static final int PPC_BC_LE_PLUS = (1<<5)|7;
public static final int PPC_BC_EQ_PLUS = (2<<5)|15;
public static final int PPC_BC_GE_PLUS = (0<<5)|7;
public static final int PPC_BC_GT_PLUS = (1<<5)|15;
public static final int PPC_BC_NE_PLUS = (2<<5)|7;
public static final int PPC_BC_UN_PLUS = (3<<5)|15;
public static final int PPC_BC_NU_PLUS = (3<<5)|7;
public static final int PPC_BC_SO = 4<<5;
public static final int PPC_BC_NS = 4<<5;
// PPC branch hint for some branch instructions
@ -1162,16 +1148,7 @@ public class Ppc_const {
public static final int PPC_INS_BDNZFLRL = 931;
public static final int PPC_INS_BDZTLRL = 932;
public static final int PPC_INS_BDZFLRL = 933;
public static final int PPC_INS_B_CC = 934;
public static final int PPC_INS_BL_CC = 935;
public static final int PPC_INS_BLA_CC = 936;
public static final int PPC_INS_BLR_CC = 937;
public static final int PPC_INS_BLRL_CC = 938;
public static final int PPC_INS_BA_CC = 939;
public static final int PPC_INS_BCTR_CC = 940;
public static final int PPC_INS_BCTRL_CC = 941;
public static final int PPC_INS_BNE = 942;
public static final int PPC_INS_MAX = 943;
public static final int PPC_INS_MAX = 934;
// Group of PPC instructions

@ -11,22 +11,8 @@ PPC_BC_GT = (1<<5)|12
PPC_BC_NE = (2<<5)|4
PPC_BC_UN = (3<<5)|12
PPC_BC_NU = (3<<5)|4
PPC_BC_LT_MINUS = (0<<5)|14
PPC_BC_LE_MINUS = (1<<5)|6
PPC_BC_EQ_MINUS = (2<<5)|14
PPC_BC_GE_MINUS = (0<<5)|6
PPC_BC_GT_MINUS = (1<<5)|14
PPC_BC_NE_MINUS = (2<<5)|6
PPC_BC_UN_MINUS = (3<<5)|14
PPC_BC_NU_MINUS = (3<<5)|6
PPC_BC_LT_PLUS = (0<<5)|15
PPC_BC_LE_PLUS = (1<<5)|7
PPC_BC_EQ_PLUS = (2<<5)|15
PPC_BC_GE_PLUS = (0<<5)|7
PPC_BC_GT_PLUS = (1<<5)|15
PPC_BC_NE_PLUS = (2<<5)|7
PPC_BC_UN_PLUS = (3<<5)|15
PPC_BC_NU_PLUS = (3<<5)|7
PPC_BC_SO = 4<<5
PPC_BC_NS = 4<<5
# PPC branch hint for some branch instructions
@ -1159,16 +1145,7 @@ PPC_INS_BDNZTLRL = 930
PPC_INS_BDNZFLRL = 931
PPC_INS_BDZTLRL = 932
PPC_INS_BDZFLRL = 933
PPC_INS_B_CC = 934
PPC_INS_BL_CC = 935
PPC_INS_BLA_CC = 936
PPC_INS_BLR_CC = 937
PPC_INS_BLRL_CC = 938
PPC_INS_BA_CC = 939
PPC_INS_BCTR_CC = 940
PPC_INS_BCTRL_CC = 941
PPC_INS_BNE = 942
PPC_INS_MAX = 943
PPC_INS_MAX = 934
# Group of PPC instructions

@ -26,22 +26,10 @@ typedef enum ppc_bc {
PPC_BC_NE = (2 << 5) | 4,
PPC_BC_UN = (3 << 5) | 12,
PPC_BC_NU = (3 << 5) | 4,
PPC_BC_LT_MINUS = (0 << 5) | 14,
PPC_BC_LE_MINUS = (1 << 5) | 6,
PPC_BC_EQ_MINUS = (2 << 5) | 14,
PPC_BC_GE_MINUS = (0 << 5) | 6,
PPC_BC_GT_MINUS = (1 << 5) | 14,
PPC_BC_NE_MINUS = (2 << 5) | 6,
PPC_BC_UN_MINUS = (3 << 5) | 14,
PPC_BC_NU_MINUS = (3 << 5) | 6,
PPC_BC_LT_PLUS = (0 << 5) | 15,
PPC_BC_LE_PLUS = (1 << 5) | 7,
PPC_BC_EQ_PLUS = (2 << 5) | 15,
PPC_BC_GE_PLUS = (0 << 5) | 7,
PPC_BC_GT_PLUS = (1 << 5) | 15,
PPC_BC_NE_PLUS = (2 << 5) | 7,
PPC_BC_UN_PLUS = (3 << 5) | 15,
PPC_BC_NU_PLUS = (3 << 5) | 7
// extra conditions
PPC_BC_SO = 4 << 5, // summary overflow
PPC_BC_NS = 4 << 5, // not summary overflow
} ppc_bc;
//> PPC branch hint for some branch instructions
@ -1221,19 +1209,6 @@ typedef enum ppc_insn {
PPC_INS_BDZTLRL,
PPC_INS_BDZFLRL,
// branch CC instruction
PPC_INS_B_CC, // Bcc
PPC_INS_BL_CC, // BccL
PPC_INS_BLA_CC, // BccLA
PPC_INS_BLR_CC, // BccLR
PPC_INS_BLRL_CC, // BccLRL
PPC_INS_BA_CC, // BccA
PPC_INS_BCTR_CC, // BccCTR
PPC_INS_BCTRL_CC, // BccCTRL
// alias instructions
PPC_INS_BNE,
PPC_INS_MAX, // <-- mark the end of the list of instructions
} ppc_insn;

@ -54,7 +54,7 @@ static void test()
#define ARM64_CODE "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
//#define THUMB_CODE "\x0a\xbf" // itet eq
//#define X86_CODE32 "\x77\x04" // ja +6
#define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
#define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
#define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"

@ -78,7 +78,7 @@ static void print_insn_detail(cs_insn *ins)
static void test()
{
#define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
#define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
struct platform platforms[] = {
{

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