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Merge branch 'next' of https://github.com/aquynh/capstone into next

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test2
Vincent Bénony 10 years ago
parent e3b572364d 7289f15a5d
commit 66cff88870
27 changed files with 864 additions and 2509 deletions
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  1. 4
      .gitignore
  2. 1
      MCInst.c
  3. 2
      MCInst.h
  4. 1
      Makefile
  5. 4
      README
  6. 8
      arch/ARM/ARMDisassembler.c
  7. 359
      arch/ARM/ARMInstPrinter.c
  8. 69
      arch/ARM/ARMMapping.c
  9. 6
      arch/ARM/ARMMapping.h
  10. 2548
      arch/ARM/ARMMappingInsnOp.inc
  11. 3
      arch/ARM/ARMModule.c
  12. 30
      arch/X86/X86ATTInstPrinter.c
  13. 30
      arch/X86/X86DisassemblerDecoder.c
  14. 22
      arch/X86/X86IntelInstPrinter.c
  15. 105
      arch/X86/X86Mapping.c
  16. 44
      arch/X86/X86MappingInsnOp.inc
  17. 8
      bindings/README
  18. 6
      bindings/java/capstone/Arm.java
  19. 2
      bindings/ocaml/arm.ml
  20. 4
      bindings/ocaml/ocaml.c
  21. 12
      bindings/python/Makefile
  22. 2
      bindings/python/capstone/arm.py
  23. 5
      bindings/python/setup.py
  24. 26
      bindings/python/test_arm.py
  25. 12
      include/capstone/arm.h
  26. 56
      tests/test_arm.c
  27. 4
      xcode/Capstone.xcodeproj/project.pbxproj

4
.gitignore vendored
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@ -81,8 +81,8 @@ ipch/
*.user
# Xcode
xcode/Capstone.xcodeproj/xcuserdata/
xcode/Capstone.xcodeproj/project.xcworkspace/
xcode/Capstone.xcodeproj/xcuserdata
xcode/Capstone.xcodeproj/project.xcworkspace/xcuserdata
# suite/
test_arm_regression

1
MCInst.c
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@ -17,6 +17,7 @@ void MCInst_Init(MCInst *inst)
inst->has_imm = false;
inst->op1_size = 0;
inst->writeback = false;
inst->ac_idx = 0;
}
void MCInst_clear(MCInst *inst)

2
MCInst.h
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@ -107,6 +107,8 @@ struct MCInst {
uint8_t x86_prefix[4];
uint8_t imm_size; // immediate size for X86_OP_IMM operand
bool writeback; // writeback for ARM
// operand access index for list of registers sharing the same access right (for ARM)
uint8_t ac_idx;
};
void MCInst_Init(MCInst *inst);

1
Makefile
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@ -87,6 +87,7 @@ DEP_ARM += arch/ARM/ARMGenInstrInfo.inc
DEP_ARM += arch/ARM/ARMGenRegisterInfo.inc
DEP_ARM += arch/ARM/ARMGenSubtargetInfo.inc
DEP_ARM += arch/ARM/ARMMappingInsn.inc
DEP_ARM += arch/ARM/ARMMappingInsnOp.inc
LIBOBJ_ARM =
ifneq (,$(findstring arm,$(CAPSTONE_ARCHS)))

4
README
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@ -15,8 +15,8 @@ Capstone offers some unparalleled features:
registers read & written.
- Implemented in pure C language, with lightweight wrappers for C++, C#, Go,
Java, Lua, NodeJS, Ocaml, Python, Ruby & Vala ready (available in main code,
or provided externally by the community).
Java, Lua, NodeJS, Ocaml, Python, Ruby, Rust & Vala ready (available in main
code, or provided externally by the community).
- Native support for all popular platforms: Windows, Mac OSX, iOS, Android,
Linux, *BSD, Solaris, etc.

8
arch/ARM/ARMDisassembler.c
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@ -472,8 +472,10 @@ static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t
if (MI->flat_insn->detail) {
memset(&MI->flat_insn->detail->arm, 0, sizeof(cs_arm));
for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++)
for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) {
MI->flat_insn->detail->arm.operands[i].vector_index = -1;
MI->flat_insn->detail->arm.operands[i].neon_lane = -1;
}
}
if (ud->big_endian)
@ -713,8 +715,10 @@ static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8
if (MI->flat_insn->detail) {
memset(&MI->flat_insn->detail->arm, 0, sizeof(cs_arm));
for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++)
for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) {
MI->flat_insn->detail->arm.operands[i].vector_index = -1;
MI->flat_insn->detail->arm.operands[i].neon_lane = -1;
}
}
if (ud->big_endian)

359
arch/ARM/ARMInstPrinter.c
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@ -121,6 +121,21 @@ static void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O);
// copy & normalize access info
static uint8_t get_op_access(cs_struct *h, unsigned int id, unsigned int index)
{
#ifndef CAPSTONE_DIET
uint8_t *arr = ARM_get_op_access(h, id);
if (arr[index] == CS_AC_IGNORE)
return 0;
return arr[index];
#else
return 0;
#endif
}
static void set_mem_access(MCInst *MI, bool status)
{
if (MI->csh->detail != CS_OPT_ON)
@ -128,11 +143,21 @@ static void set_mem_access(MCInst *MI, bool status)
MI->csh->doing_mem = status;
if (status) {
#ifndef CAPSTONE_DIET
uint8_t access;
#endif
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_INVALID;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
#ifndef CAPSTONE_DIET
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
MI->ac_idx++;
#endif
} else {
// done, create the next operand slot
MI->flat_insn->detail->arm.op_count++;
@ -391,8 +416,10 @@ void ARM_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
case ARM_MOVPCLR:
insn->detail->arm.operands[0].type = ARM_OP_REG;
insn->detail->arm.operands[0].reg = ARM_REG_PC;
insn->detail->arm.operands[0].access = CS_AC_READ;
insn->detail->arm.operands[1].type = ARM_OP_REG;
insn->detail->arm.operands[1].reg = ARM_REG_LR;
insn->detail->arm.operands[1].access = CS_AC_WRITE;
insn->detail->arm.op_count = 2;
break;
}
@ -401,9 +428,9 @@ void ARM_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
void ARM_printInst(MCInst *MI, SStream *O, void *Info)
{
MCRegisterInfo *MRI = (MCRegisterInfo *)Info;
unsigned Opcode = MCInst_getOpcode(MI), tmp, i, pubOpcode;
switch(Opcode) {
// Check for HINT instructions w/ canonical names.
case ARM_HINT:
@ -452,6 +479,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst);
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE;
MI->flat_insn->detail->arm.op_count++;
}
@ -461,6 +489,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
MI->flat_insn->detail->arm.op_count++;
}
@ -469,6 +498,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2);
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
MI->flat_insn->detail->arm.op_count++;
}
//assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0);
@ -490,6 +520,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst);
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE;
MI->flat_insn->detail->arm.op_count++;
}
@ -498,6 +529,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
MI->flat_insn->detail->arm.op_count++;
}
@ -546,8 +578,16 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
SStream_concat0(O, "\t{");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 1)));
if (MI->csh->detail) {
#ifndef CAPSTONE_DIET
uint8_t access;
#endif
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1));
#ifndef CAPSTONE_DIET
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
MI->ac_idx++;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "}");
@ -567,6 +607,13 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
if (Opcode == ARM_t2LDMIA_UPD)
SStream_concat0(O, ".w");
SStream_concat0(O, "\t");
if (MI->csh->detail) {
MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP;
MI->flat_insn->detail->regs_read_count++;
MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP;
MI->flat_insn->detail->regs_write_count++;
}
printRegisterList(MI, 4, O);
return;
}
@ -586,6 +633,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "}");
@ -638,6 +686,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = BaseReg;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
MI->flat_insn->detail->arm.op_count++;
}
if (Writeback) {
@ -721,8 +770,17 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
else
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = Reg;
} else {
#ifndef CAPSTONE_DIET
uint8_t access;
#endif
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg;
#ifndef CAPSTONE_DIET
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
MI->ac_idx++;
#endif
MI->flat_insn->detail->arm.op_count++;
}
}
@ -829,6 +887,7 @@ static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O)
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
MI->flat_insn->detail->arm.op_count++;
}
}
@ -850,6 +909,7 @@ static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (MCOperand_getImm(MO3) & 7) + ARM_SFT_ASR_REG - 1;
MI->flat_insn->detail->arm.op_count++;
@ -878,6 +938,7 @@ static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = MCOperand_getImm(MO2) & 7;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = (unsigned int)MCOperand_getImm(MO2) >> 3;
MI->flat_insn->detail->arm.op_count++;
@ -1019,6 +1080,7 @@ static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
MI->flat_insn->detail->arm.op_count++;
}
@ -1109,6 +1171,7 @@ static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
MI->flat_insn->detail->arm.op_count++;
}
@ -1158,6 +1221,7 @@ static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
MI->flat_insn->detail->arm.op_count++;
}
}
@ -1194,6 +1258,7 @@ static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O,
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
}
ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2));
@ -1268,6 +1333,7 @@ static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO);
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
MI->flat_insn->detail->arm.op_count++;
}
}
@ -1382,17 +1448,37 @@ static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O)
static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned i, e;
#ifndef CAPSTONE_DIET
uint8_t access;
#endif
SStream_concat0(O, "{");
#ifndef CAPSTONE_DIET
if (MI->csh->detail) {
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
}
#endif
for (i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) {
if (i != OpNum) SStream_concat0(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, i)));
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, i));
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
}
SStream_concat0(O, "}");
#ifndef CAPSTONE_DIET
if (MI->csh->detail) {
MI->ac_idx++;
}
#endif
}
static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O,
@ -1688,7 +1774,9 @@ static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat(O, "%u", tmp);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
MI->flat_insn->detail->arm.op_count--;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].neon_lane = tmp;
MI->ac_idx--; // consecutive operands share the same access right
} else {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
@ -1906,6 +1994,7 @@ static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
MI->flat_insn->detail->arm.op_count++;
}
@ -2320,9 +2409,9 @@ static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "[0x%x]",tmp);
SStream_concat(O, "[0x%x]", tmp);
else
SStream_concat(O, "[%u]",tmp);
SStream_concat(O, "[%u]", tmp);
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].vector_index = tmp;
}
@ -2333,9 +2422,22 @@ static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat0(O, "{");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
#endif
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
#ifndef CAPSTONE_DIET
MI->ac_idx++;
#endif
}
SStream_concat0(O, "}");
}
@ -2343,14 +2445,25 @@ static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O)
static void printVectorListTwo(MCInst *MI, unsigned OpNum,
SStream *O, MCRegisterInfo *MRI)
{
#ifndef CAPSTONE_DIET
uint8_t access;
#endif
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1);
#ifndef CAPSTONE_DIET
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
#endif
SStream_concat0(O, "{");
printRegName(MI->csh, O, Reg0);
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, ", ");
@ -2358,22 +2471,40 @@ static void printVectorListTwo(MCInst *MI, unsigned OpNum,
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "}");
#ifndef CAPSTONE_DIET
MI->ac_idx++;
#endif
}
static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum,
SStream *O, MCRegisterInfo *MRI)
{
#ifndef CAPSTONE_DIET
uint8_t access;
#endif
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2);
#ifndef CAPSTONE_DIET
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
#endif
SStream_concat0(O, "{");
printRegName(MI->csh, O, Reg0);
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, ", ");
@ -2381,13 +2512,26 @@ static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum,
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "}");
#ifndef CAPSTONE_DIET
MI->ac_idx++;
#endif
}
static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O)
{
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
#endif
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
@ -2396,6 +2540,9 @@ static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, ", ");
@ -2403,6 +2550,9 @@ static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, ", ");
@ -2410,13 +2560,26 @@ static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "}");
#ifndef CAPSTONE_DIET
MI->ac_idx++;
#endif
}
static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O)
{
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
#endif
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
@ -2425,6 +2588,9 @@ static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, ", ");
@ -2432,6 +2598,9 @@ static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, ", ");
@ -2439,6 +2608,9 @@ static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, ", ");
@ -2446,34 +2618,65 @@ static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "}");
#ifndef CAPSTONE_DIET
MI->ac_idx++;
#endif
}
static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
{
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
#endif
SStream_concat0(O, "{");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[]}");
#ifndef CAPSTONE_DIET
MI->ac_idx++;
#endif
}
static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum,
SStream *O, MCRegisterInfo *MRI)
{
#ifndef CAPSTONE_DIET
uint8_t access;
#endif
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1);
#ifndef CAPSTONE_DIET
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
#endif
SStream_concat0(O, "{");
printRegName(MI->csh, O, Reg0);
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[], ");
@ -2481,13 +2684,26 @@ static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum,
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[]}");
#ifndef CAPSTONE_DIET
MI->ac_idx++;
#endif
}
static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
{
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
#endif
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
@ -2496,6 +2712,9 @@ static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[], ");
@ -2503,6 +2722,9 @@ static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[], ");
@ -2510,13 +2732,26 @@ static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[]}");
#ifndef CAPSTONE_DIET
MI->ac_idx++;
#endif
}
static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
{
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
#endif
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
@ -2525,6 +2760,9 @@ static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[], ");
@ -2532,6 +2770,9 @@ static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[], ");
@ -2539,6 +2780,9 @@ static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[], ");
@ -2546,22 +2790,40 @@ static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[]}");
#ifndef CAPSTONE_DIET
MI->ac_idx++;
#endif
}
static void printVectorListTwoSpacedAllLanes(MCInst *MI,
unsigned OpNum, SStream *O, MCRegisterInfo *MRI)
{
#ifndef CAPSTONE_DIET
uint8_t access;
#endif
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2);
#ifndef CAPSTONE_DIET
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
#endif
SStream_concat0(O, "{");
printRegName(MI->csh, O, Reg0);
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[], ");
@ -2569,14 +2831,27 @@ static void printVectorListTwoSpacedAllLanes(MCInst *MI,
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[]}");
#ifndef CAPSTONE_DIET
MI->ac_idx++;
#endif
}
static void printVectorListThreeSpacedAllLanes(MCInst *MI,
unsigned OpNum, SStream *O)
{
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
#endif
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
@ -2585,6 +2860,9 @@ static void printVectorListThreeSpacedAllLanes(MCInst *MI,
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[], ");
@ -2592,6 +2870,9 @@ static void printVectorListThreeSpacedAllLanes(MCInst *MI,
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[], ");
@ -2599,14 +2880,27 @@ static void printVectorListThreeSpacedAllLanes(MCInst *MI,
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[]}");
#ifndef CAPSTONE_DIET
MI->ac_idx++;
#endif
}
static void printVectorListFourSpacedAllLanes(MCInst *MI,
unsigned OpNum, SStream *O)
{
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
#endif
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
@ -2615,6 +2909,9 @@ static void printVectorListFourSpacedAllLanes(MCInst *MI,
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[], ");
@ -2622,6 +2919,9 @@ static void printVectorListFourSpacedAllLanes(MCInst *MI,
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[], ");
@ -2629,6 +2929,9 @@ static void printVectorListFourSpacedAllLanes(MCInst *MI,
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[], ");
@ -2636,13 +2939,26 @@ static void printVectorListFourSpacedAllLanes(MCInst *MI,
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "[]}");
#ifndef CAPSTONE_DIET
MI->ac_idx++;
#endif
}
static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O)
{
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
#endif
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
@ -2651,6 +2967,9 @@ static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, ", ");
@ -2658,6 +2977,9 @@ static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, ", ");
@ -2665,13 +2987,26 @@ static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "}");
#ifndef CAPSTONE_DIET
MI->ac_idx++;
#endif
}
static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O)
{
#ifndef CAPSTONE_DIET
uint8_t access;
access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
#endif
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
@ -2680,6 +3015,9 @@ static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, ", ");
@ -2687,6 +3025,9 @@ static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, ", ");
@ -2694,6 +3035,9 @@ static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, ", ");
@ -2701,9 +3045,16 @@ static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
#ifndef CAPSTONE_DIET
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
#endif
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "}");
#ifndef CAPSTONE_DIET
MI->ac_idx++;
#endif
}
void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd)

69
arch/ARM/ARMMapping.c
Unescape View File

@ -877,24 +877,83 @@ bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int id) {
}
#if 0
#ifndef CAPSTONE_DIET
// map instruction to its characteristics
typedef struct insn_op {
unsigned int eflags_update; // how this instruction update status flags
cs_ac_type operands[4];
uint8_t access[7];
} insn_op;
static insn_op insn_ops[] = {
{
// NULL item
0,
{ 0 }
},
#include "ARMMappingInsnOp.inc"
};
// given internal insn id, return operand access info
uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id)
{
int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
if (i != 0) {
return insn_ops[i].access;
}
return NULL;
}
void ARM_reg_access(const cs_insn *insn,
cs_regs regs_read, uint8_t *regs_read_count,
cs_regs regs_write, uint8_t *regs_write_count)
{
uint8_t i;
uint8_t read_count, write_count;
cs_arm *arm = &(insn->detail->arm);
read_count = insn->detail->regs_read_count;
write_count = insn->detail->regs_write_count;
// implicit registers
memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0]));
memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0]));
// explicit registers
for (i = 0; i < arm->op_count; i++) {
cs_arm_op *op = &(arm->operands[i]);
switch((int)op->type) {
case ARM_OP_REG:
if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) {
regs_read[read_count] = op->reg;
read_count++;
}
if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) {
regs_write[write_count] = op->reg;
write_count++;
}
break;
case ARM_OP_MEM:
// registers appeared in memory references always being read
if ((op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) {
regs_read[read_count] = op->mem.base;
read_count++;
}
if ((op->mem.index != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) {
regs_read[read_count] = op->mem.index;
read_count++;
}
if ((arm->writeback) && (op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) {
regs_write[write_count] = op->mem.base;
write_count++;
}
default:
break;
}
}
*regs_read_count = read_count;
*regs_write_count = write_count;
}
#endif
#endif

6
arch/ARM/ARMMapping.h
Unescape View File

@ -23,4 +23,10 @@ bool ARM_rel_branch(cs_struct *h, unsigned int insn_id);
bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id);
uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id);
void ARM_reg_access(const cs_insn *insn,
cs_regs regs_read, uint8_t *regs_read_count,
cs_regs regs_write, uint8_t *regs_write_count);
#endif

2548
arch/ARM/ARMMappingInsnOp.inc
View File

File diff suppressed because it is too large Load Diff

3
arch/ARM/ARMModule.c
Unescape View File

@ -30,6 +30,9 @@ static cs_err init(cs_struct *ud)
ud->insn_name = ARM_insn_name;
ud->group_name = ARM_group_name;
ud->post_printer = ARM_post_printer;
#ifndef CAPSTONE_DIET
ud->reg_access = ARM_reg_access;
#endif
if (ud->mode & CS_MODE_THUMB)
ud->disasm = Thumb_getInstruction;

30
arch/X86/X86ATTInstPrinter.c
Unescape View File

@ -562,6 +562,24 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
// Print X86 immediates as signed values.
int64_t imm = MCOperand_getImm(Op);
switch(MCInst_getOpcode(MI)) {
default:
break;
case X86_AAD8i8:
case X86_AAM8i8:
case X86_ADC8i8:
case X86_ADD8i8:
case X86_AND8i8:
case X86_CMP8i8:
case X86_OR8i8:
case X86_SBB8i8:
case X86_SUB8i8:
case X86_TEST8i8:
case X86_XOR8i8:
imm = imm & 0xff;
break;
}
switch(MI->flat_insn->id) {
default:
if (imm >= 0) {
@ -576,6 +594,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
SStream_concat(O, "$-%"PRIu64, -imm);
}
break;
case X86_INS_INT:
// do not print number in negative form
if (imm >= 0 && imm <= HEX_THRESHOLD)
@ -583,6 +602,17 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
else
SStream_concat(O, "$0x%x", imm & 0xff);
break;
case X86_INS_AND:
case X86_INS_OR:
case X86_INS_XOR:
// do not print number in negative form
if (imm >= 0 && imm <= HEX_THRESHOLD)
SStream_concat(O, "$%u", imm);
else
SStream_concat(O, "$0x%"PRIx64, arch_masks[MI->op1_size? MI->op1_size : MI->imm_size] & imm);
break;
case X86_INS_RET:
// RET imm16
if (imm >= 0 && imm <= HEX_THRESHOLD)

30
arch/X86/X86DisassemblerDecoder.c
Unescape View File

@ -400,7 +400,8 @@ static int readPrefixes(struct InternalInstruction *insn)
return -1;
if ((byte & 0xf0) == 0x40) {
// another REX prefix, but we only remember the last one
consumeByte(insn, &byte);
if (consumeByte(insn, &byte))
return -1;
} else
break;
}
@ -435,8 +436,11 @@ static int readPrefixes(struct InternalInstruction *insn)
break;
if (insn->readerCursor - 1 == insn->startLocation
&& (byte == 0xf2 || byte == 0xf3)
&& !lookAtByte(insn, &nextByte)) {
&& (byte == 0xf2 || byte == 0xf3)) {
if (lookAtByte(insn, &nextByte))
return -1;
/*
* If the byte is 0xf2 or 0xf3, and any of the following conditions are
* met:
@ -652,8 +656,10 @@ static int readPrefixes(struct InternalInstruction *insn)
if (insn->vectorExtensionType == TYPE_VEX_3B) {
insn->vectorExtensionPrefix[0] = byte;
consumeByte(insn, &insn->vectorExtensionPrefix[1]);
consumeByte(insn, &insn->vectorExtensionPrefix[2]);
if (consumeByte(insn, &insn->vectorExtensionPrefix[1]))
return -1;
if (consumeByte(insn, &insn->vectorExtensionPrefix[2]))
return -1;
/* We simulate the REX prefix for simplicity's sake */
if (insn->mode == MODE_64BIT) {
@ -681,7 +687,8 @@ static int readPrefixes(struct InternalInstruction *insn)
if (insn->vectorExtensionType == TYPE_VEX_2B) {
insn->vectorExtensionPrefix[0] = byte;
consumeByte(insn, &insn->vectorExtensionPrefix[1]);
if (consumeByte(insn, &insn->vectorExtensionPrefix[1]))
return -1;
if (insn->mode == MODE_64BIT) {
insn->rexPrefix = 0x40
@ -714,8 +721,10 @@ static int readPrefixes(struct InternalInstruction *insn)
if (insn->vectorExtensionType == TYPE_XOP) {
insn->vectorExtensionPrefix[0] = byte;
consumeByte(insn, &insn->vectorExtensionPrefix[1]);
consumeByte(insn, &insn->vectorExtensionPrefix[2]);
if (consumeByte(insn, &insn->vectorExtensionPrefix[1]))
return -1;
if (consumeByte(insn, &insn->vectorExtensionPrefix[2]))
return -1;
/* We simulate the REX prefix for simplicity's sake */
if (insn->mode == MODE_64BIT) {
@ -744,7 +753,8 @@ static int readPrefixes(struct InternalInstruction *insn)
return -1;
if ((opcodeByte & 0xf0) == 0x40) {
// another REX prefix, but we only remember the last one
consumeByte(insn, &byte);
if (consumeByte(insn, &byte))
return -1;
} else
break;
}
@ -813,7 +823,7 @@ static int readOpcode(struct InternalInstruction *insn)
/* Determine the length of the primary opcode */
uint8_t current;
// printf(">>> readOpcode()\n");
// printf(">>> readOpcode() = %x\n", insn->readerCursor);
insn->opcodeType = ONEBYTE;

22
arch/X86/X86IntelInstPrinter.c
Unescape View File

@ -285,7 +285,7 @@ static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O)
}
#ifndef CAPSTONE_DIET
// convert Intel access info to AT&T access info
// copy & normalize access info
static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64_t *eflags)
{
#ifndef CAPSTONE_DIET
@ -689,6 +689,24 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
} else if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op);
switch(MCInst_getOpcode(MI)) {
default:
break;
case X86_AAD8i8:
case X86_AAM8i8:
case X86_ADC8i8:
case X86_ADD8i8:
case X86_AND8i8:
case X86_CMP8i8:
case X86_OR8i8:
case X86_SBB8i8:
case X86_SUB8i8:
case X86_TEST8i8:
case X86_XOR8i8:
imm = imm & 0xff;
break;
}
switch(MI->flat_insn->id) {
default:
if (imm >= 0) {
@ -712,6 +730,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
else
SStream_concat(O, "0x%x", imm & 0xff);
break;
case X86_INS_AND:
case X86_INS_OR:
case X86_INS_XOR:
@ -721,6 +740,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
else
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->op1_size? MI->op1_size : MI->imm_size] & imm);
break;
case X86_INS_RET:
// RET imm16
if (imm >= 0 && imm <= HEX_THRESHOLD)

105
arch/X86/X86Mapping.c
Unescape View File

@ -2463,61 +2463,14 @@ struct insn_reg2 {
};
static struct insn_reg insn_regs_att[] = {
{ X86_LODSQ, X86_REG_RAX },
{ X86_OR32i32, X86_REG_EAX },
{ X86_SUB32i32, X86_REG_EAX },
{ X86_TEST32i32, X86_REG_EAX },
{ X86_XCHG64ar, X86_REG_RAX },
{ X86_LODSB, X86_REG_AL },
{ X86_AND32i32, X86_REG_EAX },
{ X86_IN16ri, X86_REG_AX },
{ X86_CMP64i32, X86_REG_RAX },
{ X86_XOR32i32, X86_REG_EAX },
{ X86_XCHG16ar, X86_REG_AX },
{ X86_LODSW, X86_REG_AX },
{ X86_AND16i16, X86_REG_AX },
{ X86_INSB, X86_REG_DX },
{ X86_INSW, X86_REG_DX },
{ X86_INSL, X86_REG_DX },
{ X86_MOV64o64a, X86_REG_RAX },
{ X86_ADC16i16, X86_REG_AX },
{ X86_XCHG32ar64, X86_REG_EAX },
{ X86_ADC8i8, X86_REG_AL },
{ X86_CMP32i32, X86_REG_EAX },
{ X86_AND8i8, X86_REG_AL },
{ X86_SCASW, X86_REG_AX },
{ X86_XOR8i8, X86_REG_AL },
{ X86_SUB16i16, X86_REG_AX },
{ X86_MOV32ao32, X86_REG_EAX },
{ X86_OR16i16, X86_REG_AX },
{ X86_XCHG32ar, X86_REG_EAX },
{ X86_SBB8i8, X86_REG_AL },
{ X86_SCASQ, X86_REG_RAX },
{ X86_SBB32i32, X86_REG_EAX },
{ X86_XOR64i32, X86_REG_RAX },
{ X86_SUB64i32, X86_REG_RAX },
{ X86_ADD64i32, X86_REG_RAX },
{ X86_OR8i8, X86_REG_AL },
{ X86_TEST64i32, X86_REG_RAX },
{ X86_SBB16i16, X86_REG_AX },
{ X86_TEST8i8, X86_REG_AL },
{ X86_IN8ri, X86_REG_AL },
{ X86_TEST16i16, X86_REG_AX },
{ X86_SCASL, X86_REG_EAX },
{ X86_MOV32o32a, X86_REG_EAX },
{ X86_SUB8i8, X86_REG_AL },
{ X86_ADD8i8, X86_REG_AL },
{ X86_OR64i32, X86_REG_RAX },
{ X86_SCASB, X86_REG_AL },
{ X86_SBB64i32, X86_REG_RAX },
{ X86_ADD16i16, X86_REG_AX },
{ X86_XOR16i16, X86_REG_AX },
{ X86_MOV64o32a, X86_REG_EAX },
{ X86_AND64i32, X86_REG_RAX },
{ X86_MOV16o16a, X86_REG_AX },
{ X86_LODSL, X86_REG_EAX },
{ X86_CMP8i8, X86_REG_AL },
{ X86_ADC64i32, X86_REG_RAX },
{ X86_CMP16i16, X86_REG_AX },
{ X86_ADC32i32, X86_REG_EAX },
{ X86_IN32ri, X86_REG_EAX },
{ X86_PUSHCS32, X86_REG_CS },
{ X86_PUSHDS32, X86_REG_DS },
@ -2599,19 +2552,30 @@ static struct insn_reg insn_regs_att[] = {
#ifndef CAPSTONE_X86_REDUCE
{ X86_SKINIT, X86_REG_EAX },
{ X86_INVLPGA32, X86_REG_EAX },
{ X86_VMRUN32, X86_REG_EAX },
{ X86_VMRUN64, X86_REG_RAX },
{ X86_VMLOAD32, X86_REG_EAX },
{ X86_FNSTSW16r, X86_REG_AX },
{ X86_INVLPGA64, X86_REG_RAX },
{ X86_VMLOAD64, X86_REG_RAX },
{ X86_VMSAVE32, X86_REG_EAX },
{ X86_VMSAVE64, X86_REG_RAX },
{ X86_VMLOAD64, X86_REG_RAX },
{ X86_FNSTSW16r, X86_REG_AX },
{ X86_ADD_FrST0, X86_REG_ST0 },
{ X86_SUB_FrST0, X86_REG_ST0 },
{ X86_SUBR_FrST0, X86_REG_ST0 },
{ X86_MUL_FrST0, X86_REG_ST0 },
{ X86_DIV_FrST0, X86_REG_ST0 },
{ X86_DIVR_FrST0, X86_REG_ST0 },
#endif
};
static struct insn_reg insn_regs_intel[] = {
{ X86_OUTSB, X86_REG_DX },
{ X86_OUTSW, X86_REG_DX },
{ X86_OUTSL, X86_REG_DX },
{ X86_MOV32ao32, X86_REG_EAX },
{ X86_LODSQ, X86_REG_RAX },
{ X86_OR32i32, X86_REG_EAX },
{ X86_SUB32i32, X86_REG_EAX },
@ -2626,7 +2590,6 @@ static struct insn_reg insn_regs_intel[] = {
{ X86_XCHG16ar, X86_REG_AX },
{ X86_LODSW, X86_REG_AX },
{ X86_AND16i16, X86_REG_AX },
{ X86_MOV64o64a, X86_REG_RAX },
{ X86_ADC16i16, X86_REG_AX },
{ X86_XCHG32ar64, X86_REG_EAX },
{ X86_ADC8i8, X86_REG_AL },
@ -2650,7 +2613,6 @@ static struct insn_reg insn_regs_intel[] = {
{ X86_IN8ri, X86_REG_AL },
{ X86_TEST16i16, X86_REG_AX },
{ X86_SCASL, X86_REG_EAX },
{ X86_MOV32o32a, X86_REG_EAX },
{ X86_SUB8i8, X86_REG_AL },
{ X86_ADD8i8, X86_REG_AL },
{ X86_OR64i32, X86_REG_RAX },
@ -2658,9 +2620,7 @@ static struct insn_reg insn_regs_intel[] = {
{ X86_SBB64i32, X86_REG_RAX },
{ X86_ADD16i16, X86_REG_AX },
{ X86_XOR16i16, X86_REG_AX },
{ X86_MOV64o32a, X86_REG_EAX },
{ X86_AND64i32, X86_REG_RAX },
{ X86_MOV16o16a, X86_REG_AX },
{ X86_LODSL, X86_REG_EAX },
{ X86_CMP8i8, X86_REG_AL },
{ X86_ADC64i32, X86_REG_RAX },
@ -2702,15 +2662,31 @@ static struct insn_reg insn_regs_intel[] = {
#ifndef CAPSTONE_X86_REDUCE
{ X86_SKINIT, X86_REG_EAX },
{ X86_INVLPGA32, X86_REG_EAX },
{ X86_VMRUN32, X86_REG_EAX },
{ X86_VMRUN64, X86_REG_RAX },
{ X86_VMLOAD32, X86_REG_EAX },
{ X86_FNSTSW16r, X86_REG_AX },
{ X86_INVLPGA64, X86_REG_RAX },
{ X86_VMLOAD64, X86_REG_RAX },
{ X86_VMSAVE32, X86_REG_EAX },
{ X86_VMSAVE64, X86_REG_RAX },
{ X86_VMLOAD64, X86_REG_RAX },
{ X86_FNSTSW16r, X86_REG_AX },
{ X86_CMOVB_F, X86_REG_ST0 },
{ X86_CMOVBE_F, X86_REG_ST0 },
{ X86_CMOVE_F, X86_REG_ST0 },
{ X86_CMOVP_F, X86_REG_ST0 },
{ X86_CMOVNB_F, X86_REG_ST0 },
{ X86_CMOVNBE_F, X86_REG_ST0 },
{ X86_CMOVNE_F, X86_REG_ST0 },
{ X86_CMOVNP_F, X86_REG_ST0 },
{ X86_ST_FXCHST0r, X86_REG_ST0 },
{ X86_ST_FXCHST0r_alt, X86_REG_ST0 },
{ X86_ST_FCOMST0r, X86_REG_ST0 },
{ X86_ST_FCOMPST0r, X86_REG_ST0 },
{ X86_ST_FCOMPST0r_alt, X86_REG_ST0 },
{ X86_ST_FPST0r, X86_REG_ST0 },
{ X86_ST_FPST0r_alt, X86_REG_ST0 },
{ X86_ST_FPNCEST0r, X86_REG_ST0 },
#endif
};
@ -2722,6 +2698,9 @@ static struct insn_reg2 insn_regs_intel2[] = {
{ X86_OUT8rr, X86_REG_DX, X86_REG_AL },
{ X86_OUT16rr, X86_REG_DX, X86_REG_AX },
{ X86_OUT32rr, X86_REG_DX, X86_REG_EAX },
{ X86_INVLPGA32, X86_REG_EAX, X86_REG_ECX },
{ X86_INVLPGA64, X86_REG_RAX, X86_REG_ECX },
};
// return register of given instruction id

44
arch/X86/X86MappingInsnOp.inc
Unescape View File

@ -415,7 +415,7 @@
},
{ /* X86_ADD_FrST0, X86_INS_FADD: fadd $op, st(0) */
0,
{ CS_AC_READ, CS_AC_IGNORE, 0 }
{ CS_AC_READ, CS_AC_READ, 0 }
},
{ /* X86_ADOX32rm, X86_INS_ADOX: adox{l} $dst, $src */
0,
@ -1367,11 +1367,11 @@
},
{ /* X86_CMOVBE_F, X86_INS_FCMOVBE: fcmovbe st(0), $op */
X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF,
{ CS_AC_IGNORE, CS_AC_WRITE, 0 }
{ CS_AC_READ, CS_AC_WRITE, 0 }
},
{ /* X86_CMOVB_F, X86_INS_FCMOVB: fcmovb st(0), $op */
X86_EFLAGS_TEST_CF,
{ CS_AC_IGNORE, CS_AC_WRITE, 0 }
{ CS_AC_READ, CS_AC_WRITE, 0 }
},
{ /* X86_CMOVE16rm, X86_INS_CMOVE: cmove{w} $dst, $src2 */
X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF,
@ -1399,7 +1399,7 @@
},
{ /* X86_CMOVE_F, X86_INS_FCMOVE: fcmove st(0), $op */
X86_EFLAGS_TEST_ZF,
{ CS_AC_IGNORE, CS_AC_WRITE, 0 }
{ CS_AC_READ, CS_AC_WRITE, 0 }
},
{ /* X86_CMOVG16rm, X86_INS_CMOVG: cmovg{w} $dst, $src2 */
X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF,
@ -1499,11 +1499,11 @@
},
{ /* X86_CMOVNBE_F, X86_INS_FCMOVNBE: fcmovnbe st(0), $op */
X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_CF,
{ CS_AC_IGNORE, CS_AC_WRITE, 0 }
{ CS_AC_READ, CS_AC_WRITE, 0 }
},
{ /* X86_CMOVNB_F, X86_INS_FCMOVNB: fcmovnb st(0), $op */
X86_EFLAGS_TEST_CF,
{ CS_AC_IGNORE, CS_AC_WRITE, 0 }
{ CS_AC_READ, CS_AC_WRITE, 0 }
},
{ /* X86_CMOVNE16rm, X86_INS_CMOVNE: cmovne{w} $dst, $src2 */
X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF,
@ -1531,7 +1531,7 @@
},
{ /* X86_CMOVNE_F, X86_INS_FCMOVNE: fcmovne st(0), $op */
X86_EFLAGS_TEST_ZF,
{ CS_AC_IGNORE, CS_AC_WRITE, 0 }
{ CS_AC_READ, CS_AC_WRITE, 0 }
},
{ /* X86_CMOVNO16rm, X86_INS_CMOVNO: cmovno{w} $dst, $src2 */
X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF,
@ -1583,7 +1583,7 @@
},
{ /* X86_CMOVNP_F, X86_INS_FCMOVNU: fcmovnu st(0), $op */
X86_EFLAGS_TEST_PF,
{ CS_AC_IGNORE, CS_AC_WRITE, 0 }
{ CS_AC_READ, CS_AC_WRITE, 0 }
},
{ /* X86_CMOVNS16rm, X86_INS_CMOVNS: cmovns{w} $dst, $src2 */
X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF,
@ -1659,7 +1659,7 @@
},
{ /* X86_CMOVP_F, X86_INS_FCMOVU: fcmovu st(0), $op */
X86_EFLAGS_TEST_PF,
{ CS_AC_IGNORE, CS_AC_WRITE, 0 }
{ CS_AC_READ, CS_AC_WRITE, 0 }
},
{ /* X86_CMOVS16rm, X86_INS_CMOVS: cmovs{w} $dst, $src2 */
X86_EFLAGS_TEST_OF | X86_EFLAGS_TEST_SF | X86_EFLAGS_TEST_ZF | X86_EFLAGS_TEST_PF | X86_EFLAGS_TEST_CF,
@ -2343,7 +2343,7 @@
},
{ /* X86_DIVR_FrST0, X86_INS_FDIVR: fdiv{|r} {%st(0), $op|$op, st(0)} */
0,
{ CS_AC_READ, 0 }
{ CS_AC_READ, CS_AC_READ, 0 }
},
{ /* X86_DIVSDrm, X86_INS_DIVSD: divsd $dst, $src2 */
0,
@ -2403,7 +2403,7 @@
},
{ /* X86_DIV_FrST0, X86_INS_FDIV: fdiv{r} $op, st(0) */
0,
{ CS_AC_READ, CS_AC_IGNORE, 0 }
{ CS_AC_READ, CS_AC_READ, 0 }
},
{ /* X86_DPPDrmi, X86_INS_DPPD: dppd $dst, $src2, $src3 */
0,
@ -6503,7 +6503,7 @@
},
{ /* X86_MUL_FrST0, X86_INS_FMUL: fmul $op, st(0) */
0,
{ CS_AC_READ, CS_AC_IGNORE, 0 }
{ CS_AC_READ, CS_AC_READ, 0 }
},
{ /* X86_MWAITrr, X86_INS_MWAIT: mwait */
0,
@ -10091,15 +10091,15 @@
},
{ /* X86_ST_FCOMPST0r, X86_INS_FCOMP: fcomp st(0), $op */
0,
{ CS_AC_IGNORE, CS_AC_READ, 0 }
{ CS_AC_READ, CS_AC_READ, 0 }
},
{ /* X86_ST_FCOMPST0r_alt, X86_INS_FCOMP: fcomp st(0), $op */
0,
{ CS_AC_IGNORE, CS_AC_READ, 0 }
{ CS_AC_READ, CS_AC_READ, 0 }
},
{ /* X86_ST_FCOMST0r, X86_INS_FCOM: fcom st(0), $op */
0,
{ CS_AC_IGNORE, CS_AC_READ, 0 }
{ CS_AC_READ, CS_AC_READ, 0 }
},
{ /* X86_ST_FP32m, X86_INS_FSTP: fstp{s} $dst */
0,
@ -10115,15 +10115,15 @@
},
{ /* X86_ST_FPNCEST0r, X86_INS_FSTPNCE: fstpnce $op, st(0) */
0,
{ CS_AC_WRITE, CS_AC_IGNORE, 0 }
{ CS_AC_WRITE, CS_AC_READ, 0 }
},
{ /* X86_ST_FPST0r, X86_INS_FSTP: fstp $op, st(0) */
0,
{ CS_AC_WRITE, CS_AC_IGNORE, 0 }
{ CS_AC_WRITE, CS_AC_READ, 0 }
},
{ /* X86_ST_FPST0r_alt, X86_INS_FSTP: fstp $op, st(0) */
0,
{ CS_AC_WRITE, CS_AC_IGNORE, 0 }
{ CS_AC_WRITE, CS_AC_READ, 0 }
},
{ /* X86_ST_FPrr, X86_INS_FSTP: fstp $op */
0,
@ -10131,11 +10131,11 @@
},
{ /* X86_ST_FXCHST0r, X86_INS_FXCH: fxch st(0), $op */
0,
{ CS_AC_IGNORE, CS_AC_READ, 0 }
{ CS_AC_READ, CS_AC_READ, 0 }
},
{ /* X86_ST_FXCHST0r_alt, X86_INS_FXCH: fxch st(0), $op */
0,
{ CS_AC_IGNORE, CS_AC_READ, 0 }
{ CS_AC_READ, CS_AC_READ, 0 }
},
{ /* X86_ST_Frr, X86_INS_FST: fst $op */
0,
@ -10327,7 +10327,7 @@
},
{ /* X86_SUBR_FrST0, X86_INS_FSUBR: fsub{|r} {%st(0), $op|$op, st(0)} */
0,
{ CS_AC_READ, 0 }
{ CS_AC_READ, CS_AC_READ, 0 }
},
{ /* X86_SUBSDrm, X86_INS_SUBSD: subsd $dst, $src2 */
0,
@ -10387,7 +10387,7 @@
},
{ /* X86_SUB_FrST0, X86_INS_FSUB: fsub{r} $op, st(0) */
0,
{ CS_AC_READ, CS_AC_IGNORE, 0 }
{ CS_AC_READ, CS_AC_READ, 0 }
},
{ /* X86_SWAPGS, X86_INS_SWAPGS: swapgs */
0,

8
bindings/README
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@ -26,3 +26,11 @@ More bindings created & maintained by the community are available as followings.
- C++ binding (by Peter Hlavaty)
https://github.com/zer0mem/cccapstone
- Lua binding (by Antonio Davide)
https://github.com/Dax89/LuaCapstone
- Rust binding (by Richo Healey)
https://github.com/richo/capstone-rs

6
bindings/java/capstone/Arm.java
Unescape View File

@ -55,6 +55,8 @@ public class Arm {
public int type;
public OpValue value;
public boolean subtracted;
public int access;
public int neon_lane;
public void read() {
readField("vector_index");
@ -72,11 +74,13 @@ public class Arm {
readField("value");
readField("shift");
readField("subtracted");
readField("access");
readField("neon_lane");
}
@Override
public List getFieldOrder() {
return Arrays.asList("vector_index", "shift", "type", "value", "subtracted");
return Arrays.asList("vector_index", "shift", "type", "value", "subtracted", "access", "neon_lane");
}
}

2
bindings/ocaml/arm.ml
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@ -37,6 +37,8 @@ type arm_op = {
shift: arm_op_shift;
value: arm_op_value;
subtracted: bool;
access: int;
neon_lane: int;
}
type cs_arm = {

4
bindings/ocaml/ocaml.c
Unescape View File

@ -122,7 +122,7 @@ CAMLprim value _cs_disasm(cs_arch arch, csh handle, const uint8_t * code, size_t
if (lcount > 0) {
array = caml_alloc(lcount, 0);
for (i = 0; i < lcount; i++) {
tmp2 = caml_alloc(4, 0);
tmp2 = caml_alloc(6, 0);
switch(insn[j-1].detail->arm.operands[i].type) {
case ARM_OP_REG:
case ARM_OP_SYSREG:
@ -168,6 +168,8 @@ CAMLprim value _cs_disasm(cs_arch arch, csh handle, const uint8_t * code, size_t
Store_field(tmp2, 1, tmp3);
Store_field(tmp2, 2, tmp);
Store_field(tmp2, 3, Val_bool(insn[j-1].detail->arm.operands[i].subtracted));
Store_field(tmp2, 4, Val_int(insn[j-1].detail->arm.operands[i].access));
Store_field(tmp2, 5, Val_int(insn[j-1].detail->arm.operands[i].neon_lane));
Store_field(array, i, tmp2);
}
} else // empty list

12
bindings/python/Makefile
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@ -13,13 +13,21 @@ install:
rm -rf $(OBJDIR) src/
rm -rf prebuilt/win64/capstone.dll
rm -rf prebuilt/win32/capstone.dll
python setup.py build -b $(OBJDIR) install
if test -n "${DESTDIR}"; then \
python setup.py build -b $(OBJDIR) install --root="${DESTDIR}"; \
else \
python setup.py build -b $(OBJDIR) install; \
fi
install3:
rm -rf $(OBJDIR) src/
rm -rf prebuilt/win64/capstone.dll
rm -rf prebuilt/win32/capstone.dll
python3 setup.py build -b $(OBJDIR) install
if test -n "${DESTDIR}"; then \
python3 setup.py build -b $(OBJDIR) install --root="${DESTDIR}"; \
else \
python3 setup.py build -b $(OBJDIR) install; \
fi
# NOTE: Newer cython can be installed by: sudo pip install --upgrade cython
install_cython:

2
bindings/python/capstone/arm.py
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@ -35,6 +35,8 @@ class ArmOp(ctypes.Structure):
('type', ctypes.c_uint),
('value', ArmOpValue),
('subtracted', ctypes.c_bool),
('access', ctypes.c_uint8),
('neon_lane', ctypes.c_int8),
)
@property

5
bindings/python/setup.py
Unescape View File

@ -10,10 +10,7 @@ from distutils import log
from distutils import dir_util
from distutils.command.build_clib import build_clib
from distutils.command.sdist import sdist
try:
from setuptools import setup
except ImportError:
from distutils import setup
from distutils.core import setup
from distutils.sysconfig import get_python_lib
# prebuilt libraries for Windows - for sdist

26
bindings/python/test_arm.py
Unescape View File

@ -8,7 +8,7 @@ from capstone.arm import *
from xprint import to_hex, to_x, to_x_32
ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00"
ARM_CODE = b"\x86\x48\x60\xf4\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00"
ARM_CODE2 = b"\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c"
THUMB_CODE = b"\x70\x47\xeb\x46\x83\xb0\xc9\x68\x1f\xb1\x30\xbf\xaf\xf3\x20\x84\x52\xf8\x23\xf0"
THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0\x18\xbf\xad\xbf\xf3\xff\x0b\x0c\x86\xf3\x00\x89\x80\xf3\x00\x8c\x4f\xfa\x99\xf6\xd0\xff\xa2\x01"
@ -72,6 +72,16 @@ def print_insn_detail(insn):
print("\t\t\toperands[%u].mem.lshift: 0x%s" \
% (c, to_x_32(i.mem.lshift)))
if i.neon_lane != -1:
print("\t\toperands[%u].neon_lane = %u" % (c, i.neon_lane))
if i.access == CS_AC_READ:
print("\t\toperands[%u].access: READ\n" % (c))
elif i.access == CS_AC_WRITE:
print("\t\toperands[%u].access: WRITE\n" % (c))
elif i.access == CS_AC_READ | CS_AC_WRITE:
print("\t\toperands[%u].access: READ | WRITE\n" % (c))
if i.shift.type != ARM_SFT_INVALID and i.shift.value:
print("\t\t\tShift: %u = %u" \
% (i.shift.type, i.shift.value))
@ -101,6 +111,20 @@ def print_insn_detail(insn):
if insn.mem_barrier:
print("\tMemory-barrier: %u" %(insn.mem_barrier))
(regs_read, regs_write) = insn.regs_access()
if len(regs_read) > 0:
print("\tRegisters read:", end="")
for r in regs_read:
print(" %s" %(insn.reg_name(r)), end="")
print("")
if len(regs_write) > 0:
print("\tRegisters modified:", end="")
for r in regs_write:
print(" %s" %(insn.reg_name(r)), end="")
print("")
# ## Test class Cs
def test_class():

12
include/capstone/arm.h
Unescape View File

@ -262,11 +262,14 @@ typedef struct arm_op_mem {
// Instruction operand
typedef struct cs_arm_op {
int vector_index; // Vector Index for some vector operands (or -1 if irrelevant)
struct {
arm_shifter type;
unsigned int value;
} shift;
arm_op_type type; // operand type
union {
unsigned int reg; // register value for REG/SYSREG operand
int32_t imm; // immediate value for C-IMM, P-IMM or IMM operand
@ -274,9 +277,18 @@ typedef struct cs_arm_op {
arm_op_mem mem; // base/index/scale/disp value for MEM operand
arm_setend_type setend; // SETEND instruction's operand type
};
// in some instructions, an operand can be subtracted or added to
// the base register,
bool subtracted; // if TRUE, this operand is subtracted. otherwise, it is added.
// How is this operand accessed? (READ, WRITE or READ|WRITE)
// This field is combined of cs_ac_type.
// NOTE: this field is irrelevant if engine is compiled in DIET mode.
uint8_t access;
// Neon lane index for NEON instructions (or -1 if irrelevant)
int8_t neon_lane;
} cs_arm_op;
// Instruction structure

56
tests/test_arm.c
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@ -30,10 +30,12 @@ static void print_string_hex(char *comment, unsigned char *str, size_t len)
printf("\n");
}
static void print_insn_detail(cs_insn *ins)
static void print_insn_detail(csh handle, cs_insn *ins)
{
cs_arm *arm;
int i;
cs_regs regs_read, regs_write;
uint8_t regs_read_count, regs_write_count;
// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
if (ins->detail == NULL)
@ -88,6 +90,24 @@ static void print_insn_detail(cs_insn *ins)
break;
}
if (op->neon_lane != -1) {
printf("\t\toperands[%u].neon_lane = %u\n", i, op->neon_lane);
}
switch(op->access) {
default:
break;
case CS_AC_READ:
printf("\t\toperands[%u].access: READ\n", i);
break;
case CS_AC_WRITE:
printf("\t\toperands[%u].access: WRITE\n", i);
break;
case CS_AC_READ | CS_AC_WRITE:
printf("\t\toperands[%u].access: READ | WRITE\n", i);
break;
}
if (op->shift.type != ARM_SFT_INVALID && op->shift.value) {
if (op->shift.type < ARM_SFT_ASR_REG)
// shift with constant value
@ -133,6 +153,27 @@ static void print_insn_detail(cs_insn *ins)
if (arm->mem_barrier)
printf("\tMemory-barrier: %u\n", arm->mem_barrier);
// Print out all registers accessed by this instruction (either implicit or explicit)
if (!cs_regs_access(handle, ins,
regs_read, &regs_read_count,
regs_write, &regs_write_count)) {
if (regs_read_count) {
printf("\tRegisters read:");
for(i = 0; i < regs_read_count; i++) {
printf(" %s", cs_reg_name(handle, regs_read[i]));
}
printf("\n");
}
if (regs_write_count) {
printf("\tRegisters modified:");
for(i = 0; i < regs_write_count; i++) {
printf(" %s", cs_reg_name(handle, regs_write[i]));
}
printf("\n");
}
}
printf("\n");
}
@ -184,7 +225,11 @@ static void test()
//#define ARM_CODE "\x90\x04\x0E\x00" // muleq lr, r0, r4
//#define ARM_CODE "\x90\x24\x0E\x00" // muleq lr, r0, r4
//#define ARM_CODE "\xb6\x10\x5f\xe1" // ldrh r1, [pc, #-6]
#define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00"
#define ARM_CODE "\x86\x48\x60\xf4\x4d\x0f\xe2\xf4\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00"
//#define ARM_CODE "\x86\x48\x60\xf4"
//#define ARM_CODE2 "\xf0\x24"
//#define ARM_CODE2 "\x83\xb0"
#define ARM_CODE2 "\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c"
@ -194,7 +239,10 @@ static void test()
//#define THUMB_CODE "\x01\x47" // bx r0
//#define THUMB_CODE "\x02\x47" // bx r0
//#define THUMB_CODE "\x0a\xbf" // itet eq
#define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68\x1f\xb1\x30\xbf\xaf\xf3\x20\x84\x52\xf8\x23\xf0"
#define THUMB_CODE "\x60\xf9\x1f\x04\xe0\xf9\x4f\x07\x70\x47\xeb\x46\x83\xb0\xc9\x68\x1f\xb1\x30\xbf\xaf\xf3\x20\x84\x52\xf8\x23\xf0"
//#define THUMB_CODE "\xe0\xf9\x4f\x07"
#define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0\x18\xbf\xad\xbf\xf3\xff\x0b\x0c\x86\xf3\x00\x89\x80\xf3\x00\x8c\x4f\xfa\x99\xf6\xd0\xff\xa2\x01"
#define THUMB_MCLASS "\xef\xf3\x02\x80"
#define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
@ -272,7 +320,7 @@ static void test()
for (j = 0; j < count; j++) {
printf("0x%"PRIx64":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
print_insn_detail(&insn[j]);
print_insn_detail(handle, &insn[j]);
}
printf("0x%"PRIx64":\n", insn[j-1].address + insn[j-1].size);

4
xcode/Capstone.xcodeproj/project.pbxproj
Unescape View File

@ -308,6 +308,7 @@
DC474F6B19DE6F3B00BCA449 /* Info.plist */ = {isa = PBXFileReference; lastKnownFileType = text.plist.xml; path = Info.plist; sourceTree = "<group>"; };
DC5BFF4019EE544E008CA585 /* test_iter */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.executable"; includeInIndex = 0; path = test_iter; sourceTree = BUILT_PRODUCTS_DIR; };
DC5BFF4819EE54BE008CA585 /* test_iter.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = test_iter.c; path = ../tests/test_iter.c; sourceTree = "<group>"; };
DC696C5E1AD4600200A56306 /* myinttypes.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; name = myinttypes.h; path = ../myinttypes.h; sourceTree = "<group>"; };
DCFE23BD19DDCC2D00EF8EA9 /* libcapstone.a */ = {isa = PBXFileReference; explicitFileType = archive.ar; includeInIndex = 0; path = libcapstone.a; sourceTree = BUILT_PRODUCTS_DIR; };
DCFE23CD19DDCC9500EF8EA9 /* libcapstone.dylib */ = {isa = PBXFileReference; explicitFileType = "compiled.mach-o.dylib"; includeInIndex = 0; path = libcapstone.dylib; sourceTree = BUILT_PRODUCTS_DIR; };
DCFE23DD19DDCD8700EF8EA9 /* AArch64AddressingModes.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = AArch64AddressingModes.h; sourceTree = "<group>"; };
@ -430,7 +431,6 @@
DCFE24A119DDCDEE00EF8EA9 /* SStream.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = SStream.c; path = ../SStream.c; sourceTree = "<group>"; };
DCFE24A219DDCDEE00EF8EA9 /* utils.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = utils.c; path = ../utils.c; sourceTree = "<group>"; };
DCFE24B019DDCE1E00EF8EA9 /* cs_priv.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; name = cs_priv.h; path = ../cs_priv.h; sourceTree = "<group>"; };
DCFE24B119DDCE1E00EF8EA9 /* inttypes.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; name = inttypes.h; path = ../inttypes.h; sourceTree = "<group>"; };
DCFE24B219DDCE1E00EF8EA9 /* LEB128.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; name = LEB128.h; path = ../LEB128.h; sourceTree = "<group>"; };
DCFE24B319DDCE1E00EF8EA9 /* MathExtras.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; name = MathExtras.h; path = ../MathExtras.h; sourceTree = "<group>"; };
DCFE24B419DDCE1E00EF8EA9 /* MCDisassembler.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; name = MCDisassembler.h; path = ../MCDisassembler.h; sourceTree = "<group>"; };
@ -616,7 +616,6 @@
children = (
DCFE249D19DDCDEE00EF8EA9 /* cs.c */,
DCFE24B019DDCE1E00EF8EA9 /* cs_priv.h */,
DCFE24B119DDCE1E00EF8EA9 /* inttypes.h */,
DCFE24B219DDCE1E00EF8EA9 /* LEB128.h */,
DCFE24B319DDCE1E00EF8EA9 /* MathExtras.h */,
DCFE24B419DDCE1E00EF8EA9 /* MCDisassembler.h */,
@ -627,6 +626,7 @@
DCFE24B719DDCE1E00EF8EA9 /* MCInstrDesc.h */,
DCFE24A019DDCDEE00EF8EA9 /* MCRegisterInfo.c */,
DCFE24B819DDCE1E00EF8EA9 /* MCRegisterInfo.h */,
DC696C5E1AD4600200A56306 /* myinttypes.h */,
DCFE24A119DDCDEE00EF8EA9 /* SStream.c */,
DCFE24B919DDCE1E00EF8EA9 /* SStream.h */,
DCFE24A219DDCDEE00EF8EA9 /* utils.c */,

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