mips: add JR.HB & JALR.HB instructions. also update Ocaml/Python/Java bindings

arch/Mips/MipsMapping.c

@@ -4843,7 +4843,7 @@ static insn_map insns[] = {
 #endif
 	},
 	{
-		Mips_JALR_HB, MIPS_INS_JALR,
+		Mips_JALR_HB, MIPS_INS_JALR_HB,
 #ifndef CAPSTONE_DIET
 		{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 1
 #endif
@@ -4903,13 +4903,13 @@ static insn_map insns[] = {
 #endif
 	},
 	{
-		Mips_JR_HB, MIPS_INS_JR,
+		Mips_JR_HB, MIPS_INS_JR_HB,
 #ifndef CAPSTONE_DIET
 		{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 1
 #endif
 	},
 	{
-		Mips_JR_HB_R6, MIPS_INS_JR,
+		Mips_JR_HB_R6, MIPS_INS_JR_HB,
 #ifndef CAPSTONE_DIET
 		{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 1
 #endif
@@ -9867,32 +9867,17 @@ static name_map insn_name_maps[] = {
 	// alias instructions
 	{ MIPS_INS_NOP, "nop" },
 	{ MIPS_INS_NEGU, "negu" },
-};
 
-// special alias insn
-static name_map alias_insn_names[] = {
-	{ MIPS_INS_NOP, "nop" },
-	{ MIPS_INS_BEQZ, "beqz" },
-	{ MIPS_INS_BAL, "bal" },
-	{ MIPS_INS_BC1T, "bc1t" },
-	{ MIPS_INS_BC1F, "bc1f" },
-	{ MIPS_INS_NEGU, "negu" },
+	{ MIPS_INS_JALR_HB, "jalr.hb" },
+	{ MIPS_INS_JR_HB, "jr.hb" },
 };
 
 const char *Mips_insn_name(csh handle, unsigned int id)
 {
 #ifndef CAPSTONE_DIET
-	unsigned int i;
-
 	if (id >= MIPS_INS_MAXIMUM)
 		return NULL;
 
-	// handle special alias first
-	for (i = 0; i < ARR_SIZE(alias_insn_names); i++) {
-		if (alias_insn_names[i].id == id)
-			return alias_insn_names[i].name;
-	}
-
 	return insn_name_maps[id].name;
 #else
 	return NULL;
@@ -9963,11 +9948,6 @@ mips_reg Mips_map_insn(const char *name)
 	// handle special alias first
 	unsigned int i;
 
-	for (i = 0; i < ARR_SIZE(alias_insn_names); i++) {
-		if (!strcmp(alias_insn_names[i].name, name))
-			return alias_insn_names[i].id;
-	}
-
 	// NOTE: skip first NULL name in insn_name_maps
 	i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name);
 

bindings/java/capstone/Mips_const.java

@@ -792,7 +792,11 @@ public class Mips_const {
 	// some alias instructions
 	public static final int MIPS_INS_NOP = 582;
 	public static final int MIPS_INS_NEGU = 583;
-	public static final int MIPS_INS_MAXIMUM = 584;
+
+	// special instructions
+	public static final int MIPS_INS_JALR_HB = 584;
+	public static final int MIPS_INS_JR_HB = 585;
+	public static final int MIPS_INS_MAXIMUM = 586;
 
 	// Group of MIPS instructions
 

bindings/ocaml/mips_const.ml

@@ -789,7 +789,11 @@ let _MIPS_INS_XORI = 581;;
 (* some alias instructions *)
 let _MIPS_INS_NOP = 582;;
 let _MIPS_INS_NEGU = 583;;
-let _MIPS_INS_MAXIMUM = 584;;
+
+(* special instructions *)
+let _MIPS_INS_JALR_HB = 584;;
+let _MIPS_INS_JR_HB = 585;;
+let _MIPS_INS_MAXIMUM = 586;;
 
 (* Group of MIPS instructions *)
 

bindings/python/capstone/mips_const.py

@@ -789,7 +789,11 @@ MIPS_INS_XORI = 581
 # some alias instructions
 MIPS_INS_NOP = 582
 MIPS_INS_NEGU = 583
-MIPS_INS_MAXIMUM = 584
+
+# special instructions
+MIPS_INS_JALR_HB = 584
+MIPS_INS_JR_HB = 585
+MIPS_INS_MAXIMUM = 586
 
 # Group of MIPS instructions
 

include/mips.h

@@ -844,6 +844,10 @@ typedef enum mips_insn {
 	MIPS_INS_NOP,
 	MIPS_INS_NEGU,
 
+	//> special instructions
+	MIPS_INS_JALR_HB,	// jump and link with Hazard Barrier
+	MIPS_INS_JR_HB,		// jump register with Hazard Barrier
+
 	MIPS_INS_MAXIMUM,
 } mips_insn;
 

tests/test_detail.c

@@ -39,7 +39,7 @@ static void test()
 #define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
 #define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
 #define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
-#define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
+#define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56\x00\x80\x04\x08"
 //#define MIPS_CODE "\x21\x38\x00\x01"
 //#define MIPS_CODE "\x21\x30\xe6\x70"
 //#define MIPS_CODE "\x1c\x00\x40\x14"