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@ -2289,6 +2289,7 @@ static insn_map insns[] = { // reduce x86 instructions |
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}; |
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}; |
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#endif |
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#endif |
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#ifndef CAPSTONE_DIET |
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// replace r1 = r2
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// replace r1 = r2
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static void arr_replace(uint16_t *arr, uint8_t max, x86_reg r1, x86_reg r2) |
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static void arr_replace(uint16_t *arr, uint8_t max, x86_reg r1, x86_reg r2) |
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{ |
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{ |
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@ -2301,6 +2302,7 @@ static void arr_replace(uint16_t *arr, uint8_t max, x86_reg r1, x86_reg r2) |
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} |
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} |
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} |
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} |
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} |
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} |
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#endif |
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// given internal insn id, return public instruction info
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// given internal insn id, return public instruction info
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void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) |
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void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) |
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@ -2922,6 +2924,7 @@ static bool valid_repe(cs_struct *h, unsigned int opcode) |
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return false; |
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return false; |
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} |
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} |
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#ifndef CAPSTONE_DIET |
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// add *CX register to regs_read[] & regs_write[]
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// add *CX register to regs_read[] & regs_write[]
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static void add_cx(MCInst *MI) |
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static void add_cx(MCInst *MI) |
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{ |
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{ |
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@ -2942,6 +2945,7 @@ static void add_cx(MCInst *MI) |
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MI->flat_insn->detail->regs_write_count++; |
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MI->flat_insn->detail->regs_write_count++; |
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} |
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} |
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} |
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} |
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#endif |
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// return true if we patch the mnemonic
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// return true if we patch the mnemonic
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bool X86_lockrep(MCInst *MI, SStream *O) |
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bool X86_lockrep(MCInst *MI, SStream *O) |
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