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@ -14299,7 +14299,7 @@ static insn_op insn_ops[] = { |
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{ 0 } |
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}, |
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{ /* ARM_CLREX, ARM_INS_CLREX: clrex */ |
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ARM_REG_CPSR, |
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0, |
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{ 0 } |
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}, |
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{ /* ARM_CLZ, ARM_INS_CLZ: clz${p} $rd, $rm */ |
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@ -15619,11 +15619,11 @@ static insn_op insn_ops[] = { |
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{ CS_OP_READ, 0 } |
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}, |
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{ /* ARM_TRAP, ARM_INS_TRAP: trap */ |
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ARM_REG_CPSR, |
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0, |
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{ 0 } |
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}, |
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{ /* ARM_TRAPNaCl, ARM_INS_TRAP: trap */ |
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ARM_REG_CPSR, |
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0, |
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{ 0 } |
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}, |
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{ /* ARM_TSTri, ARM_INS_TST: tst${p} $rn, $imm */ |
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@ -21331,7 +21331,7 @@ static insn_op insn_ops[] = { |
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{ 0 } |
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}, |
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{ /* ARM_t2CLREX, ARM_INS_CLREX: clrex${p} */ |
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ARM_REG_CPSR, |
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0, |
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{ 0 } |
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}, |
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{ /* ARM_t2CLZ, ARM_INS_CLZ: clz${p} $rd, $rm */ |
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@ -21403,15 +21403,15 @@ static insn_op insn_ops[] = { |
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{ 0 } |
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}, |
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{ /* ARM_t2DCPS1, ARM_INS_DCPS1: dcps1${p} */ |
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ARM_REG_CPSR, |
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0, |
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{ 0 } |
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}, |
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{ /* ARM_t2DCPS2, ARM_INS_DCPS2: dcps2${p} */ |
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ARM_REG_CPSR, |
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0, |
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{ 0 } |
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}, |
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{ /* ARM_t2DCPS3, ARM_INS_DCPS3: dcps3${p} */ |
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ARM_REG_CPSR, |
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0, |
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{ 0 } |
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}, |
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{ /* ARM_t2DMB, ARM_INS_DMB: dmb${p} $opt */ |
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@ -22979,7 +22979,7 @@ static insn_op insn_ops[] = { |
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{ CS_OP_WRITE, CS_OP_READ, 0 } |
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}, |
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{ /* ARM_tTRAP, ARM_INS_TRAP: trap */ |
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ARM_REG_CPSR, |
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0, |
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{ 0 } |
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}, |
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{ /* ARM_tTST, ARM_INS_TST: tst${p} $rn, $rm */ |
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