From 63547c70d4d23e0c8b48eb0e00b81100bd9aba20 Mon Sep 17 00:00:00 2001 From: David Callahan Date: Sun, 10 May 2015 16:39:15 -0700 Subject: [PATCH 1/4] fix setting writeback for post index memory accesses --- arch/AArch64/AArch64InstPrinter.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c index 113ae0ed..09948c8b 100644 --- a/arch/AArch64/AArch64InstPrinter.c +++ b/arch/AArch64/AArch64InstPrinter.c @@ -1379,8 +1379,15 @@ void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst return; // check if this insn requests write-back - if (strrchr(insn_asm, '!') != NULL) + if (strrchr(insn_asm, '!') != NULL) { flat_insn->detail->arm64.writeback = true; + } else { + // check for post-index ... [reg], #offset + const char * lb = strrchr(insn_asm, ']'); + if (lb != NULL && lb[1] == ',') { + flat_insn->detail->arm64.writeback = true; + } + } } #endif From 9c95bdef67f6fe3cf79e5c2646bf8f114c7bcab9 Mon Sep 17 00:00:00 2001 From: David Callahan Date: Sun, 10 May 2015 16:39:15 -0700 Subject: [PATCH 2/4] fix setting writeback for post index memory accesses --- arch/AArch64/AArch64InstPrinter.c | 251 +++++++++++++++++++++++++++++- 1 file changed, 247 insertions(+), 4 deletions(-) diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c index 113ae0ed..6d2f93a5 100644 --- a/arch/AArch64/AArch64InstPrinter.c +++ b/arch/AArch64/AArch64InstPrinter.c @@ -1377,10 +1377,253 @@ void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst { if (((cs_struct *)handle)->detail != CS_OPT_ON) return; - - // check if this insn requests write-back - if (strrchr(insn_asm, '!') != NULL) - flat_insn->detail->arm64.writeback = true; + + unsigned opcode = MCInst_getOpcode(mci); + switch (opcode) { + default: + break; + case AArch64_LD1Fourv16b_POST: + case AArch64_LD1Fourv1d_POST: + case AArch64_LD1Fourv2d_POST: + case AArch64_LD1Fourv2s_POST: + case AArch64_LD1Fourv4h_POST: + case AArch64_LD1Fourv4s_POST: + case AArch64_LD1Fourv8b_POST: + case AArch64_LD1Fourv8h_POST: + case AArch64_LD1Onev16b_POST: + case AArch64_LD1Onev1d_POST: + case AArch64_LD1Onev2d_POST: + case AArch64_LD1Onev2s_POST: + case AArch64_LD1Onev4h_POST: + case AArch64_LD1Onev4s_POST: + case AArch64_LD1Onev8b_POST: + case AArch64_LD1Onev8h_POST: + case AArch64_LD1Rv16b_POST: + case AArch64_LD1Rv1d_POST: + case AArch64_LD1Rv2d_POST: + case AArch64_LD1Rv2s_POST: + case AArch64_LD1Rv4h_POST: + case AArch64_LD1Rv4s_POST: + case AArch64_LD1Rv8b_POST: + case AArch64_LD1Rv8h_POST: + case AArch64_LD1Threev16b_POST: + case AArch64_LD1Threev1d_POST: + case AArch64_LD1Threev2d_POST: + case AArch64_LD1Threev2s_POST: + case AArch64_LD1Threev4h_POST: + case AArch64_LD1Threev4s_POST: + case AArch64_LD1Threev8b_POST: + case AArch64_LD1Threev8h_POST: + case AArch64_LD1Twov16b_POST: + case AArch64_LD1Twov1d_POST: + case AArch64_LD1Twov2d_POST: + case AArch64_LD1Twov2s_POST: + case AArch64_LD1Twov4h_POST: + case AArch64_LD1Twov4s_POST: + case AArch64_LD1Twov8b_POST: + case AArch64_LD1Twov8h_POST: + case AArch64_LD1i16_POST: + case AArch64_LD1i32_POST: + case AArch64_LD1i64_POST: + case AArch64_LD1i8_POST: + case AArch64_LD2Rv16b_POST: + case AArch64_LD2Rv1d_POST: + case AArch64_LD2Rv2d_POST: + case AArch64_LD2Rv2s_POST: + case AArch64_LD2Rv4h_POST: + case AArch64_LD2Rv4s_POST: + case AArch64_LD2Rv8b_POST: + case AArch64_LD2Rv8h_POST: + case AArch64_LD2Twov16b_POST: + case AArch64_LD2Twov2d_POST: + case AArch64_LD2Twov2s_POST: + case AArch64_LD2Twov4h_POST: + case AArch64_LD2Twov4s_POST: + case AArch64_LD2Twov8b_POST: + case AArch64_LD2Twov8h_POST: + case AArch64_LD2i16_POST: + case AArch64_LD2i32_POST: + case AArch64_LD2i64_POST: + case AArch64_LD2i8_POST: + case AArch64_LD3Rv16b_POST: + case AArch64_LD3Rv1d_POST: + case AArch64_LD3Rv2d_POST: + case AArch64_LD3Rv2s_POST: + case AArch64_LD3Rv4h_POST: + case AArch64_LD3Rv4s_POST: + case AArch64_LD3Rv8b_POST: + case AArch64_LD3Rv8h_POST: + case AArch64_LD3Threev16b_POST: + case AArch64_LD3Threev2d_POST: + case AArch64_LD3Threev2s_POST: + case AArch64_LD3Threev4h_POST: + case AArch64_LD3Threev4s_POST: + case AArch64_LD3Threev8b_POST: + case AArch64_LD3Threev8h_POST: + case AArch64_LD3i16_POST: + case AArch64_LD3i32_POST: + case AArch64_LD3i64_POST: + case AArch64_LD3i8_POST: + case AArch64_LD4Fourv16b_POST: + case AArch64_LD4Fourv2d_POST: + case AArch64_LD4Fourv2s_POST: + case AArch64_LD4Fourv4h_POST: + case AArch64_LD4Fourv4s_POST: + case AArch64_LD4Fourv8b_POST: + case AArch64_LD4Fourv8h_POST: + case AArch64_LD4Rv16b_POST: + case AArch64_LD4Rv1d_POST: + case AArch64_LD4Rv2d_POST: + case AArch64_LD4Rv2s_POST: + case AArch64_LD4Rv4h_POST: + case AArch64_LD4Rv4s_POST: + case AArch64_LD4Rv8b_POST: + case AArch64_LD4Rv8h_POST: + case AArch64_LD4i16_POST: + case AArch64_LD4i32_POST: + case AArch64_LD4i64_POST: + case AArch64_LD4i8_POST: + case AArch64_LDPDpost: + case AArch64_LDPDpre: + case AArch64_LDPQpost: + case AArch64_LDPQpre: + case AArch64_LDPSWpost: + case AArch64_LDPSWpre: + case AArch64_LDPSpost: + case AArch64_LDPSpre: + case AArch64_LDPWpost: + case AArch64_LDPWpre: + case AArch64_LDPXpost: + case AArch64_LDPXpre: + case AArch64_LDRBBpost: + case AArch64_LDRBBpre: + case AArch64_LDRBpost: + case AArch64_LDRBpre: + case AArch64_LDRDpost: + case AArch64_LDRDpre: + case AArch64_LDRHHpost: + case AArch64_LDRHHpre: + case AArch64_LDRHpost: + case AArch64_LDRHpre: + case AArch64_LDRQpost: + case AArch64_LDRQpre: + case AArch64_LDRSBWpost: + case AArch64_LDRSBWpre: + case AArch64_LDRSBXpost: + case AArch64_LDRSBXpre: + case AArch64_LDRSHWpost: + case AArch64_LDRSHWpre: + case AArch64_LDRSHXpost: + case AArch64_LDRSHXpre: + case AArch64_LDRSWpost: + case AArch64_LDRSWpre: + case AArch64_LDRSpost: + case AArch64_LDRSpre: + case AArch64_LDRWpost: + case AArch64_LDRWpre: + case AArch64_LDRXpost: + case AArch64_LDRXpre: + case AArch64_ST1Fourv16b_POST: + case AArch64_ST1Fourv1d_POST: + case AArch64_ST1Fourv2d_POST: + case AArch64_ST1Fourv2s_POST: + case AArch64_ST1Fourv4h_POST: + case AArch64_ST1Fourv4s_POST: + case AArch64_ST1Fourv8b_POST: + case AArch64_ST1Fourv8h_POST: + case AArch64_ST1Onev16b_POST: + case AArch64_ST1Onev1d_POST: + case AArch64_ST1Onev2d_POST: + case AArch64_ST1Onev2s_POST: + case AArch64_ST1Onev4h_POST: + case AArch64_ST1Onev4s_POST: + case AArch64_ST1Onev8b_POST: + case AArch64_ST1Onev8h_POST: + case AArch64_ST1Threev16b_POST: + case AArch64_ST1Threev1d_POST: + case AArch64_ST1Threev2d_POST: + case AArch64_ST1Threev2s_POST: + case AArch64_ST1Threev4h_POST: + case AArch64_ST1Threev4s_POST: + case AArch64_ST1Threev8b_POST: + case AArch64_ST1Threev8h_POST: + case AArch64_ST1Twov16b_POST: + case AArch64_ST1Twov1d_POST: + case AArch64_ST1Twov2d_POST: + case AArch64_ST1Twov2s_POST: + case AArch64_ST1Twov4h_POST: + case AArch64_ST1Twov4s_POST: + case AArch64_ST1Twov8b_POST: + case AArch64_ST1Twov8h_POST: + case AArch64_ST1i16_POST: + case AArch64_ST1i32_POST: + case AArch64_ST1i64_POST: + case AArch64_ST1i8_POST: + case AArch64_ST2Twov16b_POST: + case AArch64_ST2Twov2d_POST: + case AArch64_ST2Twov2s_POST: + case AArch64_ST2Twov4h_POST: + case AArch64_ST2Twov4s_POST: + case AArch64_ST2Twov8b_POST: + case AArch64_ST2Twov8h_POST: + case AArch64_ST2i16_POST: + case AArch64_ST2i32_POST: + case AArch64_ST2i64_POST: + case AArch64_ST2i8_POST: + case AArch64_ST3Threev16b_POST: + case AArch64_ST3Threev2d_POST: + case AArch64_ST3Threev2s_POST: + case AArch64_ST3Threev4h_POST: + case AArch64_ST3Threev4s_POST: + case AArch64_ST3Threev8b_POST: + case AArch64_ST3Threev8h_POST: + case AArch64_ST3i16_POST: + case AArch64_ST3i32_POST: + case AArch64_ST3i64_POST: + case AArch64_ST3i8_POST: + case AArch64_ST4Fourv16b_POST: + case AArch64_ST4Fourv2d_POST: + case AArch64_ST4Fourv2s_POST: + case AArch64_ST4Fourv4h_POST: + case AArch64_ST4Fourv4s_POST: + case AArch64_ST4Fourv8b_POST: + case AArch64_ST4Fourv8h_POST: + case AArch64_ST4i16_POST: + case AArch64_ST4i32_POST: + case AArch64_ST4i64_POST: + case AArch64_ST4i8_POST: + case AArch64_STPDpost: + case AArch64_STPDpre: + case AArch64_STPQpost: + case AArch64_STPQpre: + case AArch64_STPSpost: + case AArch64_STPSpre: + case AArch64_STPWpost: + case AArch64_STPWpre: + case AArch64_STPXpost: + case AArch64_STPXpre: + case AArch64_STRBBpost: + case AArch64_STRBBpre: + case AArch64_STRBpost: + case AArch64_STRBpre: + case AArch64_STRDpost: + case AArch64_STRDpre: + case AArch64_STRHHpost: + case AArch64_STRHHpre: + case AArch64_STRHpost: + case AArch64_STRHpre: + case AArch64_STRQpost: + case AArch64_STRQpre: + case AArch64_STRSpost: + case AArch64_STRSpre: + case AArch64_STRWpost: + case AArch64_STRWpre: + case AArch64_STRXpost: + case AArch64_STRXpre: + flat_insn->detail->arm64.writeback = true; + break; + } + return ; } #endif From 4cd188502fb4a82394984c8c2426b3ac489865fa Mon Sep 17 00:00:00 2001 From: David Callahan Date: Sat, 16 May 2015 09:52:12 -0700 Subject: [PATCH 3/4] reformat --- arch/AArch64/AArch64InstPrinter.c | 495 +++++++++++++++--------------- 1 file changed, 248 insertions(+), 247 deletions(-) diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c index ef5ffff2..8e0f20fe 100644 --- a/arch/AArch64/AArch64InstPrinter.c +++ b/arch/AArch64/AArch64InstPrinter.c @@ -1,4 +1,4 @@ -//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==// +s//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==// // // The LLVM Compiler Infrastructure // @@ -1377,252 +1377,253 @@ void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst { if (((cs_struct *)handle)->detail != CS_OPT_ON) return; - unsigned opcode = MCInst_getOpcode(mci); - switch (opcode) { - default: - break; - case AArch64_LD1Fourv16b_POST: - case AArch64_LD1Fourv1d_POST: - case AArch64_LD1Fourv2d_POST: - case AArch64_LD1Fourv2s_POST: - case AArch64_LD1Fourv4h_POST: - case AArch64_LD1Fourv4s_POST: - case AArch64_LD1Fourv8b_POST: - case AArch64_LD1Fourv8h_POST: - case AArch64_LD1Onev16b_POST: - case AArch64_LD1Onev1d_POST: - case AArch64_LD1Onev2d_POST: - case AArch64_LD1Onev2s_POST: - case AArch64_LD1Onev4h_POST: - case AArch64_LD1Onev4s_POST: - case AArch64_LD1Onev8b_POST: - case AArch64_LD1Onev8h_POST: - case AArch64_LD1Rv16b_POST: - case AArch64_LD1Rv1d_POST: - case AArch64_LD1Rv2d_POST: - case AArch64_LD1Rv2s_POST: - case AArch64_LD1Rv4h_POST: - case AArch64_LD1Rv4s_POST: - case AArch64_LD1Rv8b_POST: - case AArch64_LD1Rv8h_POST: - case AArch64_LD1Threev16b_POST: - case AArch64_LD1Threev1d_POST: - case AArch64_LD1Threev2d_POST: - case AArch64_LD1Threev2s_POST: - case AArch64_LD1Threev4h_POST: - case AArch64_LD1Threev4s_POST: - case AArch64_LD1Threev8b_POST: - case AArch64_LD1Threev8h_POST: - case AArch64_LD1Twov16b_POST: - case AArch64_LD1Twov1d_POST: - case AArch64_LD1Twov2d_POST: - case AArch64_LD1Twov2s_POST: - case AArch64_LD1Twov4h_POST: - case AArch64_LD1Twov4s_POST: - case AArch64_LD1Twov8b_POST: - case AArch64_LD1Twov8h_POST: - case AArch64_LD1i16_POST: - case AArch64_LD1i32_POST: - case AArch64_LD1i64_POST: - case AArch64_LD1i8_POST: - case AArch64_LD2Rv16b_POST: - case AArch64_LD2Rv1d_POST: - case AArch64_LD2Rv2d_POST: - case AArch64_LD2Rv2s_POST: - case AArch64_LD2Rv4h_POST: - case AArch64_LD2Rv4s_POST: - case AArch64_LD2Rv8b_POST: - case AArch64_LD2Rv8h_POST: - case AArch64_LD2Twov16b_POST: - case AArch64_LD2Twov2d_POST: - case AArch64_LD2Twov2s_POST: - case AArch64_LD2Twov4h_POST: - case AArch64_LD2Twov4s_POST: - case AArch64_LD2Twov8b_POST: - case AArch64_LD2Twov8h_POST: - case AArch64_LD2i16_POST: - case AArch64_LD2i32_POST: - case AArch64_LD2i64_POST: - case AArch64_LD2i8_POST: - case AArch64_LD3Rv16b_POST: - case AArch64_LD3Rv1d_POST: - case AArch64_LD3Rv2d_POST: - case AArch64_LD3Rv2s_POST: - case AArch64_LD3Rv4h_POST: - case AArch64_LD3Rv4s_POST: - case AArch64_LD3Rv8b_POST: - case AArch64_LD3Rv8h_POST: - case AArch64_LD3Threev16b_POST: - case AArch64_LD3Threev2d_POST: - case AArch64_LD3Threev2s_POST: - case AArch64_LD3Threev4h_POST: - case AArch64_LD3Threev4s_POST: - case AArch64_LD3Threev8b_POST: - case AArch64_LD3Threev8h_POST: - case AArch64_LD3i16_POST: - case AArch64_LD3i32_POST: - case AArch64_LD3i64_POST: - case AArch64_LD3i8_POST: - case AArch64_LD4Fourv16b_POST: - case AArch64_LD4Fourv2d_POST: - case AArch64_LD4Fourv2s_POST: - case AArch64_LD4Fourv4h_POST: - case AArch64_LD4Fourv4s_POST: - case AArch64_LD4Fourv8b_POST: - case AArch64_LD4Fourv8h_POST: - case AArch64_LD4Rv16b_POST: - case AArch64_LD4Rv1d_POST: - case AArch64_LD4Rv2d_POST: - case AArch64_LD4Rv2s_POST: - case AArch64_LD4Rv4h_POST: - case AArch64_LD4Rv4s_POST: - case AArch64_LD4Rv8b_POST: - case AArch64_LD4Rv8h_POST: - case AArch64_LD4i16_POST: - case AArch64_LD4i32_POST: - case AArch64_LD4i64_POST: - case AArch64_LD4i8_POST: - case AArch64_LDPDpost: - case AArch64_LDPDpre: - case AArch64_LDPQpost: - case AArch64_LDPQpre: - case AArch64_LDPSWpost: - case AArch64_LDPSWpre: - case AArch64_LDPSpost: - case AArch64_LDPSpre: - case AArch64_LDPWpost: - case AArch64_LDPWpre: - case AArch64_LDPXpost: - case AArch64_LDPXpre: - case AArch64_LDRBBpost: - case AArch64_LDRBBpre: - case AArch64_LDRBpost: - case AArch64_LDRBpre: - case AArch64_LDRDpost: - case AArch64_LDRDpre: - case AArch64_LDRHHpost: - case AArch64_LDRHHpre: - case AArch64_LDRHpost: - case AArch64_LDRHpre: - case AArch64_LDRQpost: - case AArch64_LDRQpre: - case AArch64_LDRSBWpost: - case AArch64_LDRSBWpre: - case AArch64_LDRSBXpost: - case AArch64_LDRSBXpre: - case AArch64_LDRSHWpost: - case AArch64_LDRSHWpre: - case AArch64_LDRSHXpost: - case AArch64_LDRSHXpre: - case AArch64_LDRSWpost: - case AArch64_LDRSWpre: - case AArch64_LDRSpost: - case AArch64_LDRSpre: - case AArch64_LDRWpost: - case AArch64_LDRWpre: - case AArch64_LDRXpost: - case AArch64_LDRXpre: - case AArch64_ST1Fourv16b_POST: - case AArch64_ST1Fourv1d_POST: - case AArch64_ST1Fourv2d_POST: - case AArch64_ST1Fourv2s_POST: - case AArch64_ST1Fourv4h_POST: - case AArch64_ST1Fourv4s_POST: - case AArch64_ST1Fourv8b_POST: - case AArch64_ST1Fourv8h_POST: - case AArch64_ST1Onev16b_POST: - case AArch64_ST1Onev1d_POST: - case AArch64_ST1Onev2d_POST: - case AArch64_ST1Onev2s_POST: - case AArch64_ST1Onev4h_POST: - case AArch64_ST1Onev4s_POST: - case AArch64_ST1Onev8b_POST: - case AArch64_ST1Onev8h_POST: - case AArch64_ST1Threev16b_POST: - case AArch64_ST1Threev1d_POST: - case AArch64_ST1Threev2d_POST: - case AArch64_ST1Threev2s_POST: - case AArch64_ST1Threev4h_POST: - case AArch64_ST1Threev4s_POST: - case AArch64_ST1Threev8b_POST: - case AArch64_ST1Threev8h_POST: - case AArch64_ST1Twov16b_POST: - case AArch64_ST1Twov1d_POST: - case AArch64_ST1Twov2d_POST: - case AArch64_ST1Twov2s_POST: - case AArch64_ST1Twov4h_POST: - case AArch64_ST1Twov4s_POST: - case AArch64_ST1Twov8b_POST: - case AArch64_ST1Twov8h_POST: - case AArch64_ST1i16_POST: - case AArch64_ST1i32_POST: - case AArch64_ST1i64_POST: - case AArch64_ST1i8_POST: - case AArch64_ST2Twov16b_POST: - case AArch64_ST2Twov2d_POST: - case AArch64_ST2Twov2s_POST: - case AArch64_ST2Twov4h_POST: - case AArch64_ST2Twov4s_POST: - case AArch64_ST2Twov8b_POST: - case AArch64_ST2Twov8h_POST: - case AArch64_ST2i16_POST: - case AArch64_ST2i32_POST: - case AArch64_ST2i64_POST: - case AArch64_ST2i8_POST: - case AArch64_ST3Threev16b_POST: - case AArch64_ST3Threev2d_POST: - case AArch64_ST3Threev2s_POST: - case AArch64_ST3Threev4h_POST: - case AArch64_ST3Threev4s_POST: - case AArch64_ST3Threev8b_POST: - case AArch64_ST3Threev8h_POST: - case AArch64_ST3i16_POST: - case AArch64_ST3i32_POST: - case AArch64_ST3i64_POST: - case AArch64_ST3i8_POST: - case AArch64_ST4Fourv16b_POST: - case AArch64_ST4Fourv2d_POST: - case AArch64_ST4Fourv2s_POST: - case AArch64_ST4Fourv4h_POST: - case AArch64_ST4Fourv4s_POST: - case AArch64_ST4Fourv8b_POST: - case AArch64_ST4Fourv8h_POST: - case AArch64_ST4i16_POST: - case AArch64_ST4i32_POST: - case AArch64_ST4i64_POST: - case AArch64_ST4i8_POST: - case AArch64_STPDpost: - case AArch64_STPDpre: - case AArch64_STPQpost: - case AArch64_STPQpre: - case AArch64_STPSpost: - case AArch64_STPSpre: - case AArch64_STPWpost: - case AArch64_STPWpre: - case AArch64_STPXpost: - case AArch64_STPXpre: - case AArch64_STRBBpost: - case AArch64_STRBBpre: - case AArch64_STRBpost: - case AArch64_STRBpre: - case AArch64_STRDpost: - case AArch64_STRDpre: - case AArch64_STRHHpost: - case AArch64_STRHHpre: - case AArch64_STRHpost: - case AArch64_STRHpre: - case AArch64_STRQpost: - case AArch64_STRQpre: - case AArch64_STRSpost: - case AArch64_STRSpre: - case AArch64_STRWpost: - case AArch64_STRWpre: - case AArch64_STRXpost: - case AArch64_STRXpre: - flat_insn->detail->arm64.writeback = true; - break; - } - return ; + + unsigned opcode = MCInst_getOpcode(mci); + switch (opcode) { + default: + break; + case AArch64_LD1Fourv16b_POST: + case AArch64_LD1Fourv1d_POST: + case AArch64_LD1Fourv2d_POST: + case AArch64_LD1Fourv2s_POST: + case AArch64_LD1Fourv4h_POST: + case AArch64_LD1Fourv4s_POST: + case AArch64_LD1Fourv8b_POST: + case AArch64_LD1Fourv8h_POST: + case AArch64_LD1Onev16b_POST: + case AArch64_LD1Onev1d_POST: + case AArch64_LD1Onev2d_POST: + case AArch64_LD1Onev2s_POST: + case AArch64_LD1Onev4h_POST: + case AArch64_LD1Onev4s_POST: + case AArch64_LD1Onev8b_POST: + case AArch64_LD1Onev8h_POST: + case AArch64_LD1Rv16b_POST: + case AArch64_LD1Rv1d_POST: + case AArch64_LD1Rv2d_POST: + case AArch64_LD1Rv2s_POST: + case AArch64_LD1Rv4h_POST: + case AArch64_LD1Rv4s_POST: + case AArch64_LD1Rv8b_POST: + case AArch64_LD1Rv8h_POST: + case AArch64_LD1Threev16b_POST: + case AArch64_LD1Threev1d_POST: + case AArch64_LD1Threev2d_POST: + case AArch64_LD1Threev2s_POST: + case AArch64_LD1Threev4h_POST: + case AArch64_LD1Threev4s_POST: + case AArch64_LD1Threev8b_POST: + case AArch64_LD1Threev8h_POST: + case AArch64_LD1Twov16b_POST: + case AArch64_LD1Twov1d_POST: + case AArch64_LD1Twov2d_POST: + case AArch64_LD1Twov2s_POST: + case AArch64_LD1Twov4h_POST: + case AArch64_LD1Twov4s_POST: + case AArch64_LD1Twov8b_POST: + case AArch64_LD1Twov8h_POST: + case AArch64_LD1i16_POST: + case AArch64_LD1i32_POST: + case AArch64_LD1i64_POST: + case AArch64_LD1i8_POST: + case AArch64_LD2Rv16b_POST: + case AArch64_LD2Rv1d_POST: + case AArch64_LD2Rv2d_POST: + case AArch64_LD2Rv2s_POST: + case AArch64_LD2Rv4h_POST: + case AArch64_LD2Rv4s_POST: + case AArch64_LD2Rv8b_POST: + case AArch64_LD2Rv8h_POST: + case AArch64_LD2Twov16b_POST: + case AArch64_LD2Twov2d_POST: + case AArch64_LD2Twov2s_POST: + case AArch64_LD2Twov4h_POST: + case AArch64_LD2Twov4s_POST: + case AArch64_LD2Twov8b_POST: + case AArch64_LD2Twov8h_POST: + case AArch64_LD2i16_POST: + case AArch64_LD2i32_POST: + case AArch64_LD2i64_POST: + case AArch64_LD2i8_POST: + case AArch64_LD3Rv16b_POST: + case AArch64_LD3Rv1d_POST: + case AArch64_LD3Rv2d_POST: + case AArch64_LD3Rv2s_POST: + case AArch64_LD3Rv4h_POST: + case AArch64_LD3Rv4s_POST: + case AArch64_LD3Rv8b_POST: + case AArch64_LD3Rv8h_POST: + case AArch64_LD3Threev16b_POST: + case AArch64_LD3Threev2d_POST: + case AArch64_LD3Threev2s_POST: + case AArch64_LD3Threev4h_POST: + case AArch64_LD3Threev4s_POST: + case AArch64_LD3Threev8b_POST: + case AArch64_LD3Threev8h_POST: + case AArch64_LD3i16_POST: + case AArch64_LD3i32_POST: + case AArch64_LD3i64_POST: + case AArch64_LD3i8_POST: + case AArch64_LD4Fourv16b_POST: + case AArch64_LD4Fourv2d_POST: + case AArch64_LD4Fourv2s_POST: + case AArch64_LD4Fourv4h_POST: + case AArch64_LD4Fourv4s_POST: + case AArch64_LD4Fourv8b_POST: + case AArch64_LD4Fourv8h_POST: + case AArch64_LD4Rv16b_POST: + case AArch64_LD4Rv1d_POST: + case AArch64_LD4Rv2d_POST: + case AArch64_LD4Rv2s_POST: + case AArch64_LD4Rv4h_POST: + case AArch64_LD4Rv4s_POST: + case AArch64_LD4Rv8b_POST: + case AArch64_LD4Rv8h_POST: + case AArch64_LD4i16_POST: + case AArch64_LD4i32_POST: + case AArch64_LD4i64_POST: + case AArch64_LD4i8_POST: + case AArch64_LDPDpost: + case AArch64_LDPDpre: + case AArch64_LDPQpost: + case AArch64_LDPQpre: + case AArch64_LDPSWpost: + case AArch64_LDPSWpre: + case AArch64_LDPSpost: + case AArch64_LDPSpre: + case AArch64_LDPWpost: + case AArch64_LDPWpre: + case AArch64_LDPXpost: + case AArch64_LDPXpre: + case AArch64_LDRBBpost: + case AArch64_LDRBBpre: + case AArch64_LDRBpost: + case AArch64_LDRBpre: + case AArch64_LDRDpost: + case AArch64_LDRDpre: + case AArch64_LDRHHpost: + case AArch64_LDRHHpre: + case AArch64_LDRHpost: + case AArch64_LDRHpre: + case AArch64_LDRQpost: + case AArch64_LDRQpre: + case AArch64_LDRSBWpost: + case AArch64_LDRSBWpre: + case AArch64_LDRSBXpost: + case AArch64_LDRSBXpre: + case AArch64_LDRSHWpost: + case AArch64_LDRSHWpre: + case AArch64_LDRSHXpost: + case AArch64_LDRSHXpre: + case AArch64_LDRSWpost: + case AArch64_LDRSWpre: + case AArch64_LDRSpost: + case AArch64_LDRSpre: + case AArch64_LDRWpost: + case AArch64_LDRWpre: + case AArch64_LDRXpost: + case AArch64_LDRXpre: + case AArch64_ST1Fourv16b_POST: + case AArch64_ST1Fourv1d_POST: + case AArch64_ST1Fourv2d_POST: + case AArch64_ST1Fourv2s_POST: + case AArch64_ST1Fourv4h_POST: + case AArch64_ST1Fourv4s_POST: + case AArch64_ST1Fourv8b_POST: + case AArch64_ST1Fourv8h_POST: + case AArch64_ST1Onev16b_POST: + case AArch64_ST1Onev1d_POST: + case AArch64_ST1Onev2d_POST: + case AArch64_ST1Onev2s_POST: + case AArch64_ST1Onev4h_POST: + case AArch64_ST1Onev4s_POST: + case AArch64_ST1Onev8b_POST: + case AArch64_ST1Onev8h_POST: + case AArch64_ST1Threev16b_POST: + case AArch64_ST1Threev1d_POST: + case AArch64_ST1Threev2d_POST: + case AArch64_ST1Threev2s_POST: + case AArch64_ST1Threev4h_POST: + case AArch64_ST1Threev4s_POST: + case AArch64_ST1Threev8b_POST: + case AArch64_ST1Threev8h_POST: + case AArch64_ST1Twov16b_POST: + case AArch64_ST1Twov1d_POST: + case AArch64_ST1Twov2d_POST: + case AArch64_ST1Twov2s_POST: + case AArch64_ST1Twov4h_POST: + case AArch64_ST1Twov4s_POST: + case AArch64_ST1Twov8b_POST: + case AArch64_ST1Twov8h_POST: + case AArch64_ST1i16_POST: + case AArch64_ST1i32_POST: + case AArch64_ST1i64_POST: + case AArch64_ST1i8_POST: + case AArch64_ST2Twov16b_POST: + case AArch64_ST2Twov2d_POST: + case AArch64_ST2Twov2s_POST: + case AArch64_ST2Twov4h_POST: + case AArch64_ST2Twov4s_POST: + case AArch64_ST2Twov8b_POST: + case AArch64_ST2Twov8h_POST: + case AArch64_ST2i16_POST: + case AArch64_ST2i32_POST: + case AArch64_ST2i64_POST: + case AArch64_ST2i8_POST: + case AArch64_ST3Threev16b_POST: + case AArch64_ST3Threev2d_POST: + case AArch64_ST3Threev2s_POST: + case AArch64_ST3Threev4h_POST: + case AArch64_ST3Threev4s_POST: + case AArch64_ST3Threev8b_POST: + case AArch64_ST3Threev8h_POST: + case AArch64_ST3i16_POST: + case AArch64_ST3i32_POST: + case AArch64_ST3i64_POST: + case AArch64_ST3i8_POST: + case AArch64_ST4Fourv16b_POST: + case AArch64_ST4Fourv2d_POST: + case AArch64_ST4Fourv2s_POST: + case AArch64_ST4Fourv4h_POST: + case AArch64_ST4Fourv4s_POST: + case AArch64_ST4Fourv8b_POST: + case AArch64_ST4Fourv8h_POST: + case AArch64_ST4i16_POST: + case AArch64_ST4i32_POST: + case AArch64_ST4i64_POST: + case AArch64_ST4i8_POST: + case AArch64_STPDpost: + case AArch64_STPDpre: + case AArch64_STPQpost: + case AArch64_STPQpre: + case AArch64_STPSpost: + case AArch64_STPSpre: + case AArch64_STPWpost: + case AArch64_STPWpre: + case AArch64_STPXpost: + case AArch64_STPXpre: + case AArch64_STRBBpost: + case AArch64_STRBBpre: + case AArch64_STRBpost: + case AArch64_STRBpre: + case AArch64_STRDpost: + case AArch64_STRDpre: + case AArch64_STRHHpost: + case AArch64_STRHHpre: + case AArch64_STRHpost: + case AArch64_STRHpre: + case AArch64_STRQpost: + case AArch64_STRQpre: + case AArch64_STRSpost: + case AArch64_STRSpre: + case AArch64_STRWpost: + case AArch64_STRWpre: + case AArch64_STRXpost: + case AArch64_STRXpre: + flat_insn->detail->arm64.writeback = true; + break; + } + return; } #endif From 19dc1ce875b56ffdcb56dc8ce091a893444b9406 Mon Sep 17 00:00:00 2001 From: David Callahan Date: Mon, 18 May 2015 11:58:21 -0700 Subject: [PATCH 4/4] fix stray typo --- arch/AArch64/AArch64InstPrinter.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c index 8e0f20fe..216ac52e 100644 --- a/arch/AArch64/AArch64InstPrinter.c +++ b/arch/AArch64/AArch64InstPrinter.c @@ -1,4 +1,4 @@ -s//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==// +//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==// // // The LLVM Compiler Infrastructure //