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fix C coding style

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_v3_old
Nguyen Anh Quynh 11 years ago
parent eaeee31f64
commit 2e79ba8996
4 changed files with 34 additions and 44 deletions
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  1. 2
      MCRegisterInfo.c
  2. 6
      MathExtras.h
  3. 52
      arch/AArch64/AArch64Disassembler.c
  4. 18
      arch/AArch64/AArch64InstPrinter.c

2
MCRegisterInfo.c
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@ -63,7 +63,7 @@ static uint16_t DiffListIterator_getVal(DiffListIterator *d)
static bool DiffListIterator_next(DiffListIterator *d)
{
MCPhysReg D;
MCPhysReg D;
if (d->List == 0)
return false;

6
MathExtras.h
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@ -133,7 +133,7 @@ static inline unsigned CountLeadingZeros_64(uint64_t Value) {
#else
#ifndef _MSC_VER
if (sizeof(long) == sizeof(int64_t))
{
{
if (!Value) return 64;
Count = 0;
// bisection method for count leading zeros
@ -146,9 +146,9 @@ static inline unsigned CountLeadingZeros_64(uint64_t Value) {
}
}
}
else
else
#endif
{
{
// get hi portion
uint32_t Hi = Hi_32(Value);

52
arch/AArch64/AArch64Disassembler.c
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@ -308,7 +308,7 @@ static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
uint16_t Register;
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
@ -318,11 +318,10 @@ static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
return MCDisassembler_Success;
}
static DecodeStatus
DecodeGPR64xspRegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeGPR64xspRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
uint16_t Register;
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
@ -336,7 +335,7 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
void *Decoder)
{
uint16_t Register;
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
@ -346,11 +345,10 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
return MCDisassembler_Success;
}
static DecodeStatus
DecodeGPR32wspRegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeGPR32wspRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
uint16_t Register;
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
@ -360,11 +358,10 @@ DecodeGPR32wspRegisterClass(MCInst *Inst, unsigned RegNo,
return MCDisassembler_Success;
}
static DecodeStatus
DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
uint16_t Register;
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
@ -374,11 +371,10 @@ DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
return MCDisassembler_Success;
}
static DecodeStatus
DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
uint16_t Register;
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
@ -389,11 +385,10 @@ DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
}
static DecodeStatus
DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
uint16_t Register;
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
@ -403,11 +398,10 @@ DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
return MCDisassembler_Success;
}
static DecodeStatus
DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
uint16_t Register;
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
@ -417,8 +411,7 @@ DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
return MCDisassembler_Success;
}
static DecodeStatus
DecodeFPR64LoRegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeFPR64LoRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
if (RegNo > 15)
@ -427,11 +420,10 @@ DecodeFPR64LoRegisterClass(MCInst *Inst, unsigned RegNo,
return DecodeFPR64RegisterClass(Inst, RegNo, Address, Decoder);
}
static DecodeStatus
DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
uint16_t Register;
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
@ -441,8 +433,7 @@ DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
return MCDisassembler_Success;
}
static DecodeStatus
DecodeFPR128LoRegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeFPR128LoRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
if (RegNo > 15)
@ -456,7 +447,7 @@ static DecodeStatus DecodeGPR64noxzrRegisterClass(MCInst *Inst,
uint64_t Address,
void *Decoder)
{
uint16_t Register;
uint16_t Register;
if (RegNo > 30)
return MCDisassembler_Fail;
@ -470,7 +461,7 @@ static DecodeStatus DecodeRegisterClassByID(MCInst *Inst, unsigned RegNo,
unsigned RegID,
void *Decoder)
{
uint16_t Register;
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
@ -1050,8 +1041,7 @@ static DecodeStatus DecodeSingleIndexedInstruction(MCInst *Inst,
return MCDisassembler_Success;
}
static DecodeStatus
DecodeNeonMovImmShiftOperand(MCInst *Inst, unsigned ShiftAmount,
static DecodeStatus DecodeNeonMovImmShiftOperand(MCInst *Inst, unsigned ShiftAmount,
uint64_t Address, void *Decoder, A64SE_ShiftExtSpecifiers Ext, bool IsHalf)
{
bool IsLSL = false;

18
arch/AArch64/AArch64InstPrinter.c
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@ -116,15 +116,15 @@ static void printAddrRegExtendOperand(MCInst *MI, unsigned OpNum,
SStream_concat(O, " #0x%x", ShiftAmt);
else
SStream_concat(O, " #%u", ShiftAmt);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].shift.type = ARM64_SFT_LSL;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].shift.value = ShiftAmt;
} else {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = ShiftAmt;
}
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].shift.type = ARM64_SFT_LSL;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].shift.value = ShiftAmt;
} else {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = ShiftAmt;
}
}
} else if (IsLSL) {
SStream_concat(O, " #0");
}
@ -490,7 +490,7 @@ static void printRegExtendOperand(MCInst *MI, unsigned OpNum, SStream *O,
// easily. We will only accumulate more of these hacks.
unsigned Reg0 = MCOperand_getReg(MCInst_getOperand(MI, 0));
unsigned Reg1 = MCOperand_getReg(MCInst_getOperand(MI, 1));
MCOperand *MO;
MCOperand *MO;
if (isStackReg(Reg0) || isStackReg(Reg1)) {
A64SE_ShiftExtSpecifiers LSLEquiv;

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