Merge branch 'next'

_v3_old
Nguyen Anh Quynh 11 years ago
commit 23118936f1
  1. 2
      CONFIG
  2. 1
      LICENSE.TXT
  3. 1
      MCInst.h
  4. 8
      MCRegisterInfo.c
  5. 34
      Makefile
  6. 11
      MathExtras.h
  7. 10
      RELEASE_NOTES
  8. 2
      SStream.c
  9. 4
      arch/AArch64/AArch64BaseInfo.c
  10. 76
      arch/AArch64/AArch64Disassembler.c
  11. 343
      arch/AArch64/AArch64GenAsmWriter.inc
  12. 17
      arch/AArch64/AArch64GenDisassemblerTables.inc
  13. 96
      arch/AArch64/AArch64InstPrinter.c
  14. 19004
      arch/AArch64/AArch64Mapping.c
  15. 3
      arch/AArch64/AArch64Mapping.h
  16. 4
      arch/AArch64/AArch64Module.c
  17. 4
      arch/ARM/ARMAddressingModes.h
  18. 83
      arch/ARM/ARMDisassembler.c
  19. 592
      arch/ARM/ARMGenAsmWriter.inc
  20. 6827
      arch/ARM/ARMGenDisassemblerTables.inc
  21. 8746
      arch/ARM/ARMGenInstrInfo.inc
  22. 239
      arch/ARM/ARMInstPrinter.c
  23. 15220
      arch/ARM/ARMMapping.c
  24. 6
      arch/ARM/ARMMapping.h
  25. 4
      arch/ARM/ARMModule.c
  26. 15
      arch/Mips/MipsDisassembler.c
  27. 4399
      arch/Mips/MipsGenAsmWriter.inc
  28. 7351
      arch/Mips/MipsGenDisassemblerTables.inc
  29. 2288
      arch/Mips/MipsGenInstrInfo.inc
  30. 96
      arch/Mips/MipsInstPrinter.c
  31. 8991
      arch/Mips/MipsMapping.c
  32. 3
      arch/Mips/MipsMapping.h
  33. 4
      arch/Mips/MipsModule.c
  34. 2
      arch/PowerPC/PPCDisassembler.c
  35. 170
      arch/PowerPC/PPCGenAsmWriter.inc
  36. 623
      arch/PowerPC/PPCGenDisassemblerTables.inc
  37. 815
      arch/PowerPC/PPCGenInstrInfo.inc
  38. 1
      arch/PowerPC/PPCGenRegisterInfo.inc
  39. 30
      arch/PowerPC/PPCInstPrinter.c
  40. 5332
      arch/PowerPC/PPCMapping.c
  41. 7
      arch/PowerPC/PPCMapping.h
  42. 4
      arch/PowerPC/PPCModule.c
  43. 178
      arch/X86/X86ATTInstPrinter.c
  44. 170
      arch/X86/X86Disassembler.c
  45. 592
      arch/X86/X86DisassemblerDecoder.c
  46. 52
      arch/X86/X86DisassemblerDecoder.h
  47. 148
      arch/X86/X86DisassemblerDecoderCommon.h
  48. 17287
      arch/X86/X86GenAsmWriter.inc
  49. 16983
      arch/X86/X86GenAsmWriter1.inc
  50. 2339804
      arch/X86/X86GenDisassemblerTables.inc
  51. 20861
      arch/X86/X86GenInstrInfo.inc
  52. 141
      arch/X86/X86GenRegisterInfo.inc
  53. 190
      arch/X86/X86IntelInstPrinter.c
  54. 35350
      arch/X86/X86Mapping.c
  55. 13
      arch/X86/X86Mapping.h
  56. 18
      bindings/java/capstone/Capstone.java
  57. 700
      bindings/java/capstone/Mips_const.java
  58. 690
      bindings/java/capstone/Ppc_const.java
  59. 2364
      bindings/java/capstone/X86_const.java
  60. 9
      bindings/python/README
  61. 2
      bindings/python/capstone/__init__.py
  62. 150
      bindings/python/capstone/capstone.py
  63. 700
      bindings/python/capstone/mips_const.py
  64. 690
      bindings/python/capstone/ppc_const.py
  65. 2364
      bindings/python/capstone/x86_const.py
  66. 67
      bindings/python/pyx/ccapstone.pyx
  67. 2
      bindings/python/setup.py
  68. 2
      bindings/python/setup_cython.py
  69. 2
      bindings/python/test.py
  70. 78
      bindings/python/test_lite.py
  71. 37
      config.mk
  72. 106
      cs.c
  73. 28
      docs/README
  74. 6
      include/arm.h
  75. 4
      include/arm64.h
  76. 48
      include/capstone.h
  77. 8
      include/mips.h
  78. 7
      include/ppc.h
  79. 39
      include/x86.h
  80. 14
      make.sh
  81. 22
      packages/freebsd/ports/devel/capstone/Makefile
  82. 2
      packages/freebsd/ports/devel/capstone/distinfo
  83. 52
      packages/freebsd/ports/devel/capstone/files/patch-Makefile
  84. 22
      packages/freebsd/ports/devel/capstone/files/patch-tests_Makefile
  85. 16
      packages/freebsd/ports/devel/capstone/pkg-descr
  86. 10
      packages/freebsd/ports/devel/capstone/pkg-plist
  87. 2
      packages/homebrew/README
  88. 14
      packages/homebrew/capstone.rb
  89. 40
      packages/macports/devel/capstone/Portfile
  90. 81
      packages/macports/devel/capstone/files/patch-Makefile.diff
  91. 24
      suite/benchmark.py
  92. 2
      tests/test.c
  93. 2
      tests/test_arm.c
  94. 2
      tests/test_arm64.c
  95. 2
      tests/test_detail.c
  96. 2
      tests/test_mips.c
  97. 2
      tests/test_ppc.c
  98. 2
      tests/test_x86.c
  99. 15
      utils.c
  100. 6
      utils.h

@ -1,6 +1,6 @@
// Package version
#define PKG_MAJOR 2
#define PKG_MINOR 0
#define PKG_MINOR 1

@ -1,5 +1,6 @@
This is the software license for Capstone disassembly framework.
Capstone has been designed & implemented by Nguyen Anh Quynh <aquynh@gmail.com>
See http://www.capstone-engine.org for further information.
Copyright (c) 2013, COSEINC.

@ -140,7 +140,6 @@ struct MCInst {
cs_insn_flat flat_insn; // insn to be exposed to public
unsigned OpcodePub;
int insn_size; // instruction size
int x86_segment; // remove when segment mem ref hack is redundant.
uint64_t address; // address of this insn
cs_struct *csh; // save the main csh
};

@ -63,10 +63,12 @@ static uint16_t DiffListIterator_getVal(DiffListIterator *d)
static bool DiffListIterator_next(DiffListIterator *d)
{
MCPhysReg D;
if (d->List == 0)
return false;
MCPhysReg D = *d->List;
D = *d->List;
d->List++;
d->Val += D;
@ -89,7 +91,7 @@ unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, un
return 0;
}
DiffListIterator_init(&iter, Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs);
DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs);
DiffListIterator_next(&iter);
while(DiffListIterator_isValid(&iter)) {
@ -108,7 +110,7 @@ unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx
DiffListIterator iter;
uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices;
DiffListIterator_init(&iter, Reg, RI->DiffLists + RI->Desc[Reg].SubRegs);
DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs);
DiffListIterator_next(&iter);
while(DiffListIterator_isValid(&iter)) {

@ -89,10 +89,19 @@ endif
LIBOBJ += MCInst.o
UNAME_S := $(shell uname -s)
PKGCFCGDIR = $(LIBDIR)/pkgconfig
# OSX?
ifeq ($(UNAME_S),Darwin)
EXT = dylib
AR_EXT = a
# By default, suppose that Brew is installed & use Brew path for pkgconfig file
PKGCFCGDIR = /usr/local/lib/pkgconfig
# is Macport installed instead?
ifneq (,$(wildcard /opt/local/bin/port))
# then correct the path for pkgconfig file
PKGCFCGDIR = /opt/local/lib/pkgconfig
endif
else
# Cygwin?
IS_CYGWIN := $(shell $(CC) -dumpmachine | grep -i cygwin | wc -l)
@ -126,15 +135,30 @@ PKGCFGF = $(LIBNAME).pc
VERSION=$(shell echo `grep -e PKG_MAJOR -e PKG_MINOR CONFIG | grep -v = | awk '{print $$3}'` | awk '{print $$1"."$$2}')
.PHONY: all clean install uninstall
.PHONY: all clean install uninstall diet dist
all: $(LIBRARY) $(ARCHIVE) $(PKGCFGF)
$(MAKE) -C tests
$(INSTALL_DATA) lib$(LIBNAME).$(EXT) tests
$(LIBRARY): $(LIBOBJ)
$(LIBRARY): diet $(LIBOBJ)
$(CC) $(LDFLAGS) $(LIBOBJ) -o $(LIBRARY)
# generate include/diet.h
diet:
@echo "#ifndef CAPSTONE_DIET_H" > include/diet.h
@echo "#define CAPSTONE_DIET_H" >> include/diet.h
@echo "" >> include/diet.h
@echo "// File auto-generated by Makefile for Capstone framework. DO NOT MODIFY!" >> include/diet.h
@echo "" >> include/diet.h
ifneq (,$(findstring yes,$(CAPSTONE_DIET)))
@echo "#define CAPSTONE_DIET" >> include/diet.h
else
@echo "#undef CAPSTONE_DIET" >> include/diet.h
endif
@echo "" >> include/diet.h
@echo "#endif" >> include/diet.h
$(ARCHIVE): $(LIBOBJ)
rm -f $(ARCHIVE)
$(AR) q $(ARCHIVE) $(LIBOBJ)
@ -156,14 +180,14 @@ install: $(PKGCFGF) $(ARCHIVE) $(LIBRARY)
$(INSTALL_DATA) lib$(LIBNAME).$(AR_EXT) $(LIBDIR)
mkdir -p $(INCDIR)/$(LIBNAME)
$(INSTALL_DATA) include/*.h $(INCDIR)/$(LIBNAME)
mkdir -p $(LIBDIR)/pkgconfig
$(INSTALL_DATA) $(PKGCFGF) $(LIBDIR)/pkgconfig/
mkdir -p $(PKGCFCGDIR)
$(INSTALL_DATA) $(PKGCFGF) $(PKGCFCGDIR)/
uninstall:
rm -rf $(INCDIR)/$(LIBNAME)
rm -f $(LIBDIR)/lib$(LIBNAME).$(EXT)
rm -f $(LIBDIR)/lib$(LIBNAME).$(AR_EXT)
rm -f $(LIBDIR)/pkgconfig/$(LIBNAME).pc
rm -f $(PKGCFCGDIR)/$(LIBNAME).pc
clean:
rm -f $(LIBOBJ) lib$(LIBNAME).*

@ -131,7 +131,9 @@ static inline unsigned CountLeadingZeros_64(uint64_t Value) {
#endif
Count = __builtin_clzll(Value);
#else
if (sizeof(long) == sizeof(int64_t)) {
#ifndef _MSC_VER
if (sizeof(long) == sizeof(int64_t))
{
if (!Value) return 64;
Count = 0;
// bisection method for count leading zeros
@ -143,7 +145,10 @@ static inline unsigned CountLeadingZeros_64(uint64_t Value) {
Count |= Shift;
}
}
} else {
}
else
#endif
{
// get hi portion
uint32_t Hi = Hi_32(Value);
@ -250,7 +255,7 @@ static inline unsigned CountPopulation_64(uint64_t Value) {
uint64_t v = Value - ((Value >> 1) & 0x5555555555555555ULL);
v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL);
v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL;
return unsigned((uint64_t)(v * 0x0101010101010101ULL) >> 56);
return (uint64_t)((v * 0x0101010101010101ULL) >> 56);
#endif
}

@ -1,10 +0,0 @@
Version 2.0 has a known X86 issue: if you disassemble a buffer of instructions
that having the first byte as a prefix (LOCK, REP, REPNE), and you only
get 1 instruction (passing 1 as value for the 'count' argument), then only
the prefix will be returned as instruction.
An work-around is to disassemble the whole buffer & get out the first
instruction, then this instruction would properly include both prefix and
the next instruction.
This issue will be fixed in the next version.

@ -16,12 +16,14 @@ void SStream_Init(SStream *ss)
void SStream_concat(SStream *ss, const char *fmt, ...)
{
#ifndef CAPSTONE_DIET
va_list ap;
va_start(ap, fmt);
int ret = cs_vsnprintf(ss->buffer + ss->index, sizeof(ss->buffer) - (ss->index + 1), fmt, ap);
va_end(ap);
ss->index += ret;
#endif
}
/*

@ -41,7 +41,7 @@ static bool compare_lower_str(char *s1, char *s2)
{
char *lower = cs_strdup(s2), *c;
for (c = lower; *c; c++)
*c = tolower((int) *c);
*c = (char)tolower((int) *c);
bool res = (strcmp(s1, lower) == 0);
cs_mem_free(lower);
@ -60,7 +60,7 @@ uint32_t NamedImmMapper_fromString(NamedImmMapper *N, char *Name, bool *Valid)
}
*Valid = false;
return -1;
return (uint32_t)-1;
}
bool NamedImmMapper_validImm(NamedImmMapper *N, uint32_t Value)

@ -215,7 +215,7 @@ static bool Check(DecodeStatus *Out, DecodeStatus In);
static uint64_t getFeatureBits(int feature)
{
// enable all features
return -1;
return (uint64_t)-1;
}
#include "AArch64GenDisassemblerTables.inc"
@ -308,22 +308,25 @@ static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
uint16_t Register = getReg(Decoder, AArch64_GPR64RegClassID, RegNo);
Register = (uint16_t)getReg(Decoder, AArch64_GPR64RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
static DecodeStatus
DecodeGPR64xspRegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeGPR64xspRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
uint16_t Register = getReg(Decoder, AArch64_GPR64xspRegClassID, RegNo);
Register = (uint16_t)getReg(Decoder, AArch64_GPR64xspRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@ -332,77 +335,83 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
void *Decoder)
{
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
uint16_t Register = getReg(Decoder, AArch64_GPR32RegClassID, RegNo);
Register = (uint16_t)getReg(Decoder, AArch64_GPR32RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
static DecodeStatus
DecodeGPR32wspRegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeGPR32wspRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
uint16_t Register = getReg(Decoder, AArch64_GPR32wspRegClassID, RegNo);
Register = (uint16_t)getReg(Decoder, AArch64_GPR32wspRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
static DecodeStatus
DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
uint16_t Register = getReg(Decoder, AArch64_FPR8RegClassID, RegNo);
Register = (uint16_t)getReg(Decoder, AArch64_FPR8RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
static DecodeStatus
DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
uint16_t Register = getReg(Decoder, AArch64_FPR16RegClassID, RegNo);
Register = (uint16_t)getReg(Decoder, AArch64_FPR16RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
static DecodeStatus
DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
uint16_t Register = getReg(Decoder, AArch64_FPR32RegClassID, RegNo);
Register = (uint16_t)getReg(Decoder, AArch64_FPR32RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
static DecodeStatus
DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
uint16_t Register = getReg(Decoder, AArch64_FPR64RegClassID, RegNo);
Register = (uint16_t)getReg(Decoder, AArch64_FPR64RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
static DecodeStatus
DecodeFPR64LoRegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeFPR64LoRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
if (RegNo > 15)
@ -411,20 +420,20 @@ DecodeFPR64LoRegisterClass(MCInst *Inst, unsigned RegNo,
return DecodeFPR64RegisterClass(Inst, RegNo, Address, Decoder);
}
static DecodeStatus
DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
uint16_t Register = getReg(Decoder, AArch64_FPR128RegClassID, RegNo);
Register = (uint16_t)getReg(Decoder, AArch64_FPR128RegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
static DecodeStatus
DecodeFPR128LoRegisterClass(MCInst *Inst, unsigned RegNo,
static DecodeStatus DecodeFPR128LoRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
if (RegNo > 15)
@ -438,10 +447,12 @@ static DecodeStatus DecodeGPR64noxzrRegisterClass(MCInst *Inst,
uint64_t Address,
void *Decoder)
{
uint16_t Register;
if (RegNo > 30)
return MCDisassembler_Fail;
uint16_t Register = getReg(Decoder, AArch64_GPR64noxzrRegClassID, RegNo);
Register = (uint16_t)getReg(Decoder, AArch64_GPR64noxzrRegClassID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@ -450,10 +461,12 @@ static DecodeStatus DecodeRegisterClassByID(MCInst *Inst, unsigned RegNo,
unsigned RegID,
void *Decoder)
{
uint16_t Register;
if (RegNo > 31)
return MCDisassembler_Fail;
uint16_t Register = getReg(Decoder, RegID, RegNo);
Register = (uint16_t)getReg(Decoder, RegID, RegNo);
MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
return MCDisassembler_Success;
}
@ -1028,8 +1041,7 @@ static DecodeStatus DecodeSingleIndexedInstruction(MCInst *Inst,
return MCDisassembler_Success;
}
static DecodeStatus
DecodeNeonMovImmShiftOperand(MCInst *Inst, unsigned ShiftAmount,
static DecodeStatus DecodeNeonMovImmShiftOperand(MCInst *Inst, unsigned ShiftAmount,
uint64_t Address, void *Decoder, A64SE_ShiftExtSpecifiers Ext, bool IsHalf)
{
bool IsLSL = false;

File diff suppressed because it is too large Load Diff

@ -14051,7 +14051,7 @@ static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
} \
case MCD_OPC_FilterValue: { \
unsigned Len; \
InsnType Val = decodeULEB128(++Ptr, &Len); \
InsnType Val = (InsnType)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
unsigned NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
@ -14063,7 +14063,7 @@ static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
unsigned Start = *++Ptr; \
unsigned Len = *++Ptr; \
InsnType FieldValue = fieldname(insn, Start, Len); \
uint32_t ExpectedValue = decodeULEB128(++Ptr, &Len); \
uint32_t ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
unsigned NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
@ -14073,30 +14073,31 @@ static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
} \
case MCD_OPC_CheckPredicate: { \
unsigned Len; \
unsigned PIdx = decodeULEB128(++Ptr, &Len); \
unsigned PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
unsigned NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
bool Pred; \
if (!(Pred = checkDecoderPredicate(PIdx, Bits))) \
Pred = checkDecoderPredicate(PIdx, Bits); \
if (!Pred) \
Ptr += NumToSkip; \
(void)Pred; \
break; \
} \
case MCD_OPC_Decode: { \
unsigned Len; \
unsigned Opc = decodeULEB128(++Ptr, &Len); \
unsigned Opc = (uint32_t)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \
unsigned DecodeIdx = (uint32_t)decodeULEB128(Ptr, &Len); \
Ptr += Len; \
MCInst_setOpcode(MI, Opc); \
return decoder(S, DecodeIdx, insn, MI, Address, MRI); \
} \
case MCD_OPC_SoftFail: { \
unsigned Len; \
InsnType PositiveMask = decodeULEB128(++Ptr, &Len); \
InsnType PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
InsnType NegativeMask = decodeULEB128(Ptr, &Len); \
InsnType NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
Ptr += Len; \
bool Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
if (Fail) \

@ -61,7 +61,7 @@ static int64_t unpackSignedImm(int BitWidth, uint64_t Value)
static void printOffsetSImm9Operand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MOImm = MCInst_getOperand(MI, OpNum);
int32_t Imm = unpackSignedImm(9, MCOperand_getImm(MOImm));
int32_t Imm = (int32_t)unpackSignedImm(9, MCOperand_getImm(MOImm));
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", Imm);
@ -78,7 +78,7 @@ static void printOffsetSImm9Operand(MCInst *MI, unsigned OpNum, SStream *O)
static void printAddrRegExtendOperand(MCInst *MI, unsigned OpNum,
SStream *O, unsigned MemSize, unsigned RmSize)
{
unsigned ExtImm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned ExtImm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned OptionHi = ExtImm >> 1;
unsigned S = ExtImm & 1;
bool IsLSL = OptionHi == 1 && RmSize == 64;
@ -116,15 +116,15 @@ static void printAddrRegExtendOperand(MCInst *MI, unsigned OpNum,
SStream_concat(O, " #0x%x", ShiftAmt);
else
SStream_concat(O, " #%u", ShiftAmt);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].shift.type = ARM64_SFT_LSL;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].shift.value = ShiftAmt;
} else {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = ShiftAmt;
}
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].shift.type = ARM64_SFT_LSL;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].shift.value = ShiftAmt;
} else {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = ShiftAmt;
}
}
} else if (IsLSL) {
SStream_concat(O, " #0");
}
@ -143,7 +143,7 @@ static void printAddSubImmLSL0Operand(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat(O, "#%u"PRIu64, Imm12);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = Imm12;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)Imm12;
MI->flat_insn.arm64.op_count++;
}
}
@ -170,7 +170,7 @@ static void printBareImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat(O, "%"PRIu64, imm);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = imm;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)imm;
MI->flat_insn.arm64.op_count++;
}
}
@ -179,7 +179,7 @@ static void printBFILSBOperand(MCInst *MI, unsigned OpNum,
SStream *O, unsigned RegWidth)
{
MCOperand *ImmROp = MCInst_getOperand(MI, OpNum);
unsigned LSB = MCOperand_getImm(ImmROp) == 0 ? 0 : RegWidth - MCOperand_getImm(ImmROp);
unsigned LSB = MCOperand_getImm(ImmROp) == 0 ? 0 : RegWidth - (unsigned int)MCOperand_getImm(ImmROp);
if (LSB > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", LSB);
@ -195,7 +195,7 @@ static void printBFILSBOperand(MCInst *MI, unsigned OpNum,
static void printBFIWidthOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *ImmSOp = MCInst_getOperand(MI, OpNum);
unsigned Width = MCOperand_getImm(ImmSOp) + 1;
unsigned Width = (unsigned int)MCOperand_getImm(ImmSOp) + 1;
if (Width > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", Width);
@ -208,8 +208,8 @@ static void printBFXWidthOperand(MCInst *MI, unsigned OpNum, SStream *O)
MCOperand *ImmSOp = MCInst_getOperand(MI, OpNum);
MCOperand *ImmROp = MCInst_getOperand(MI, OpNum - 1);
unsigned ImmR = MCOperand_getImm(ImmROp);
unsigned ImmS = MCOperand_getImm(ImmSOp);
unsigned ImmR = (unsigned int)MCOperand_getImm(ImmROp);
unsigned ImmS = (unsigned int)MCOperand_getImm(ImmSOp);
//assert(ImmS >= ImmR && "Invalid ImmR, ImmS combination for bitfield extract");
@ -232,7 +232,7 @@ static void printCRxOperand(MCInst *MI, unsigned OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_CIMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = MCOperand_getImm(CRx);
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)MCOperand_getImm(CRx);
MI->flat_insn.arm64.op_count++;
}
}
@ -247,7 +247,7 @@ static void printCVTFixedPosOperand(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat(O, "#%u", 64 - MCOperand_getImm(ScaleOp));
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = 64 - MCOperand_getImm(ScaleOp);
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = 64 - (int32_t)MCOperand_getImm(ScaleOp);
MI->flat_insn.arm64.op_count++;
}
}
@ -259,7 +259,7 @@ static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
//assert(MOImm8.isImm()
// && "Immediate operand required for floating-point immediate inst");
uint32_t Imm8 = MCOperand_getImm(MOImm8);
uint32_t Imm8 = (uint32_t)MCOperand_getImm(MOImm8);
uint32_t Fraction = Imm8 & 0xf;
uint32_t Exponent = (Imm8 >> 4) & 0x7;
uint32_t Negative = (Imm8 >> 7) & 0x1;
@ -326,7 +326,7 @@ static void printLabelOperand(MCInst *MI, unsigned OpNum,
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = SImm;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)SImm;
MI->flat_insn.arm64.op_count++;
}
@ -341,14 +341,14 @@ static void printLogicalImmOperand(MCInst *MI, unsigned OpNum,
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
uint64_t Val;
A64Imms_isLogicalImmBits(RegWidth, MCOperand_getImm(MO), &Val);
A64Imms_isLogicalImmBits(RegWidth, (uint32_t)MCOperand_getImm(MO), &Val);
if (Val > HEX_THRESHOLD)
SStream_concat(O, "#0x%"PRIx64, Val);
else
SStream_concat(O, "#%"PRIu64, Val);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = Val;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)Val;
MI->flat_insn.arm64.op_count++;
}
}
@ -359,7 +359,7 @@ static void printOffsetUImm12Operand(MCInst *MI, unsigned OpNum,
MCOperand *MOImm = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MOImm)) {
uint32_t Imm = MCOperand_getImm(MOImm) * MemSize;
uint32_t Imm = (uint32_t)MCOperand_getImm(MOImm) * MemSize;
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", Imm);
@ -395,7 +395,7 @@ static void printShiftOperand(MCInst *MI, unsigned OpNum,
default: break; // llvm_unreachable("Invalid shift specifier in logical instruction");
}
unsigned int imm = MCOperand_getImm(MO);
unsigned int imm = (unsigned int)MCOperand_getImm(MO);
if (imm > HEX_THRESHOLD)
SStream_concat(O, " #0x%x", imm);
else
@ -419,12 +419,12 @@ static void printMoveWideImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat(O, "#%"PRIu64, imm);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = imm;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)imm;
MI->flat_insn.arm64.op_count++;
}
if (MCOperand_getImm(ShiftMO) != 0) {
unsigned int shift = MCOperand_getImm(ShiftMO) * 16;
unsigned int shift = (unsigned int)MCOperand_getImm(ShiftMO) * 16;
if (shift > HEX_THRESHOLD)
SStream_concat(O, ", lsl #0x%x", shift);
else
@ -443,7 +443,7 @@ static void printNamedImmOperand(MCInst *MI, unsigned OpNum, SStream *O, NamedIm
{
bool ValidName;
MCOperand *MO = MCInst_getOperand(MI, OpNum);
char *Name = NamedImmMapper_toString(Mapper, MCOperand_getImm(MO), &ValidName);
char *Name = NamedImmMapper_toString(Mapper, (uint32_t)MCOperand_getImm(MO), &ValidName);
if (ValidName)
SStream_concat(O, Name);
@ -455,7 +455,7 @@ static void printNamedImmOperand(MCInst *MI, unsigned OpNum, SStream *O, NamedIm
SStream_concat(O, "#%"PRIu64, imm);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = imm;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)imm;
MI->flat_insn.arm64.op_count++;
}
}
@ -469,7 +469,7 @@ static void printSysRegOperand(SysRegMapper *Mapper,
MCOperand *MO = MCInst_getOperand(MI, OpNum);
SysRegMapper_toString(Mapper, MCOperand_getImm(MO), &ValidName, Name);
SysRegMapper_toString(Mapper, (uint32_t)MCOperand_getImm(MO), &ValidName, Name);
if (ValidName) {
SStream_concat(O, Name);
}
@ -490,6 +490,7 @@ static void printRegExtendOperand(MCInst *MI, unsigned OpNum, SStream *O,
// easily. We will only accumulate more of these hacks.
unsigned Reg0 = MCOperand_getReg(MCInst_getOperand(MI, 0));
unsigned Reg1 = MCOperand_getReg(MCInst_getOperand(MI, 1));
MCOperand *MO;
if (isStackReg(Reg0) || isStackReg(Reg1)) {
A64SE_ShiftExtSpecifiers LSLEquiv;
@ -500,7 +501,7 @@ static void printRegExtendOperand(MCInst *MI, unsigned OpNum, SStream *O,
LSLEquiv = A64SE_UXTW;
if (Ext == LSLEquiv) {
unsigned int shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned int shift = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (shift > HEX_THRESHOLD)
SStream_concat(O, "lsl #0x%x", shift);
else
@ -528,9 +529,9 @@ static void printRegExtendOperand(MCInst *MI, unsigned OpNum, SStream *O,
if (MI->csh->detail)
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].ext = Ext - 4;
MCOperand *MO = MCInst_getOperand(MI, OpNum);
MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_getImm(MO) != 0) {
unsigned int shift = MCOperand_getImm(MO);
unsigned int shift = (unsigned int)MCOperand_getImm(MO);
if (shift > HEX_THRESHOLD)
SStream_concat(O, " #0x%x", shift);
else
@ -546,7 +547,7 @@ static void printSImm7ScaledOperand(MCInst *MI, unsigned OpNum,
SStream *O, int MemScale)
{
MCOperand *MOImm = MCInst_getOperand(MI, OpNum);
int32_t Imm = unpackSignedImm(7, MCOperand_getImm(MOImm));
int32_t Imm = (int32_t)unpackSignedImm(7, MCOperand_getImm(MOImm));
if (Imm * MemScale > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", Imm * MemScale);
@ -605,10 +606,10 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
SStream_concat(O, "#%"PRIu64, imm);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.disp = imm;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.disp = (int32_t)imm;
} else {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = imm;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)imm;
MI->flat_insn.arm64.op_count++;
}
}
@ -669,7 +670,7 @@ static void printNeonMovImmShiftOperand(MCInst *MI, unsigned OpNum,
else
SStream_concat(O, " #%"PRIu64, Imm);
if (MI->csh->detail)
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = Imm;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count - 1].shift.value = (unsigned int)Imm;
}
static void printNeonUImm0Operand(MCInst *MI, unsigned OpNum, SStream *O)
@ -690,7 +691,7 @@ static void printUImmHexOperand(MCInst *MI, unsigned OpNum, SStream *O)
//assert(MOUImm.isImm() &&
// "Immediate operand required for Neon vector immediate inst.");
unsigned Imm = MCOperand_getImm(MOUImm);
unsigned Imm = (unsigned int)MCOperand_getImm(MOUImm);
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", Imm);
@ -710,7 +711,7 @@ static void printUImmBareOperand(MCInst *MI, unsigned OpNum, SStream *O)
//assert(MOUImm.isImm()
// && "Immediate operand required for Neon vector immediate inst.");
unsigned Imm = MCOperand_getImm(MOUImm);
unsigned Imm = (unsigned int)MCOperand_getImm(MOUImm);
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", Imm);
else
@ -732,7 +733,7 @@ static void printNeonUImm64MaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
//assert(MOUImm8.isImm() &&
// "Immediate operand required for Neon vector immediate bytemask inst.");
uint32_t UImm8 = MCOperand_getImm(MOUImm8);
uint32_t UImm8 = (uint32_t)MCOperand_getImm(MOUImm8);
uint64_t Mask = 0;
// Replicates 0x00 or 0xff byte in a 64-bit vector
@ -748,7 +749,7 @@ static void printNeonUImm64MaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat(O, "#%"PRIu64, Mask);
if (MI->csh->detail) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = Mask;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)Mask;
MI->flat_insn.arm64.op_count++;
}
}
@ -811,16 +812,11 @@ void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm)
void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
{
if (printAliasInstr(MI, O, Info)) {
char *mnem = cs_strdup(O->buffer);
char *tab = strchr(mnem, '\t');
if (tab) {
*tab = '\0';
}
// reflect the new insn name (alias) in the opcode
unsigned int id = AArch64_map_insn(mnem);
MCInst_setOpcode(MI, AArch64_get_insn_id2(id));
MCInst_setOpcodePub(MI, id);
char *mnem;
mnem = printAliasInstr(MI, O, Info);
if (mnem) {
MCInst_setOpcodePub(MI, AArch64_map_insn(mnem));
cs_mem_free(mnem);
} else
printInstruction(MI, O, Info);

File diff suppressed because it is too large Load Diff

@ -13,9 +13,6 @@ const char *AArch64_reg_name(csh handle, unsigned int reg);
// given internal insn id, return public instruction info
void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
// given public insn id, return internal instruction ID
unsigned int AArch64_get_insn_id2(unsigned int id);
const char *AArch64_insn_name(csh handle, unsigned int id);
// map instruction name to public instruction ID

@ -11,11 +11,13 @@ void enable_arm64() {}
static cs_err init(cs_struct *ud)
{
MCRegisterInfo *mri;
// verify if requested mode is valid
if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_BIG_ENDIAN))
return CS_ERR_MODE;
MCRegisterInfo *mri = cs_mem_malloc(sizeof(*mri));
mri = cs_mem_malloc(sizeof(*mri));
AArch64_init(mri);
ud->printer = AArch64_printInst;

@ -56,7 +56,7 @@ static inline const char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op)
static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op)
{
switch (Op) {
default: return -1; //llvm_unreachable("Unknown shift opc!");
default: return (unsigned int)-1; //llvm_unreachable("Unknown shift opc!");
case ARM_AM_asr: return 2;
case ARM_AM_lsl: return 0;
case ARM_AM_lsr: return 1;
@ -391,7 +391,7 @@ static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm)
//assert (isT2SOImmTwoPartVal(Imm) &&
// "Immedate cannot be encoded as two part immediate!");
// Try a shifter operand as one part
unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm;
unsigned V = rotr32 (~(unsigned int)255, getT2SOImmValRotate(Imm)) & Imm;
// If the rest is encodable as an immediate, then return it.
if (getT2SOImmVal(V) != -1) return V;

@ -93,7 +93,7 @@ static void ITStatus_setITState(ARM_ITStatus *it, char Firstcond, char Mask)
//assert(NumTZ <= 3 && "Invalid IT mask!");
// push condition codes onto the stack the correct order for the pops
for (Pos = NumTZ+1; Pos <= 3; ++Pos) {
bool T = ((Mask >> Pos) & 1) == CondBit0;
bool T = ((Mask >> Pos) & 1) == (int)CondBit0;
if (T)
ITStatus_push_back(it, CCBits);
else
@ -364,7 +364,7 @@ static DecodeStatus DecodeMRRC2(MCInst *Inst, unsigned Val,
// Hacky: enable all features for disassembler
static uint64_t getFeatureBits(int mode)
{
uint64_t Bits = -1; // everything by default
uint64_t Bits = (uint64_t)-1; // everything by default
// FIXME: ARM_FeatureVFPOnlySP is conflicting with everything else??
Bits &= (~ARM_FeatureVFPOnlySP);
@ -379,16 +379,16 @@ static uint64_t getFeatureBits(int mode)
// some features are mutually exclusive
if (mode & CS_MODE_THUMB) {
//Bits &= ~ARM_HasV6Ops;
//Bits &= ~ARM_FeatureCRC;
//Bits &= ~ARM_HasV5TEOps;
//Bits &= ~ARM_HasV4TOps;
//Bits &= ~ARM_HasV6T2Ops;
//Bits &= ~ARM_FeatureDB;
//Bits &= ~ARM_FeatureHWDivARM;
//Bits &= ~ARM_FeatureNaClTrap;
//Bits &= ~ARM_FeatureMClass;
// ArmV8
//Bits &= ~ARM_HasV6Ops;
//Bits &= ~ARM_FeatureCRC;
//Bits &= ~ARM_HasV5TEOps;
//Bits &= ~ARM_HasV4TOps;
//Bits &= ~ARM_HasV6T2Ops;
//Bits &= ~ARM_FeatureDB;
//Bits &= ~ARM_FeatureHWDivARM;
//Bits &= ~ARM_FeatureNaClTrap;
//Bits &= ~ARM_FeatureMClass;
// ArmV8
} else { // ARM mode
Bits &= ~ARM_ModeThumb;
Bits &= ~ARM_FeatureThumb2;
@ -425,7 +425,7 @@ void ARM_init(MCRegisterInfo *MRI)
ARMRegUnitRoots, 77, ARMRegDiffLists, ARMRegStrings,
ARMSubRegIdxLists, 57,
ARMSubRegIdxRanges, ARMRegEncodingTable);
*/
*/
MCRegisterInfo_InitMCRegisterInfo(MRI, ARMRegDesc, 289,
0, 0,
@ -564,6 +564,9 @@ static void AddThumb1SBit(MCInst *MI, bool InITBlock)
static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI)
{
DecodeStatus S = MCDisassembler_Success;
MCOperandInfo *OpInfo;
unsigned short NumOps;
unsigned int i;
// A few instructions actually have predicates encoded in them. Don't
// try to overwrite it if we're seeing one of those.
@ -608,9 +611,9 @@ static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI)
if (ITStatus_instrInITBlock(&(ud->ITBlock)))
ITStatus_advanceITState(&(ud->ITBlock));
MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
unsigned i;
OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
for (i = 0; i < NumOps; ++i) {
if (i == MCInst_getNumOperands(MI)) break;
if (MCOperandInfo_isPredicate(&OpInfo[i])) {
@ -640,13 +643,17 @@ static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI)
static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI)
{
unsigned CC;
unsigned short NumOps;
MCOperandInfo *OpInfo;
unsigned i;
CC = ITStatus_getITCC(&(ud->ITBlock));
if (ITStatus_instrInITBlock(&(ud->ITBlock)))
ITStatus_advanceITState(&(ud->ITBlock));
MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
unsigned i;
OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
for (i = 0; i < NumOps; ++i) {
if (MCOperandInfo_isPredicate(&OpInfo[i])) {
MCOperand_setImm(MCInst_getOperand(MI, i), CC);
@ -712,9 +719,9 @@ static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8
// to the subsequent instructions.
if (MCInst_getOpcode(MI) == ARM_t2IT) {
unsigned Firstcond = MCOperand_getImm(MCInst_getOperand(MI, 0));
unsigned Mask = MCOperand_getImm(MCInst_getOperand(MI, 1));
ITStatus_setITState(&(ud->ITBlock), Firstcond, Mask);
unsigned Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 0));
unsigned Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 1));
ITStatus_setITState(&(ud->ITBlock), (char)Firstcond, (char)Mask);
}
return result;
@ -1125,6 +1132,7 @@ static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val,
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
ARM_AM_ShiftOpc Shift;
unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
unsigned type = fieldFromInstruction_4(Val, 5, 2);
@ -1134,7 +1142,7 @@ static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val,
if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler_Fail;
ARM_AM_ShiftOpc Shift = ARM_AM_lsl;
Shift = ARM_AM_lsl;
switch (type) {
case 0:
Shift = ARM_AM_lsl;
@ -1163,6 +1171,7 @@ static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val,
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
ARM_AM_ShiftOpc Shift;
unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
unsigned type = fieldFromInstruction_4(Val, 5, 2);
@ -1174,7 +1183,7 @@ static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val,
if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
return MCDisassembler_Fail;
ARM_AM_ShiftOpc Shift = ARM_AM_lsl;
Shift = ARM_AM_lsl;
switch (type) {
case 0:
Shift = ARM_AM_lsl;
@ -1297,6 +1306,7 @@ static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val,
// create the final mask.
unsigned msb = fieldFromInstruction_4(Val, 5, 5);
unsigned lsb = fieldFromInstruction_4(Val, 0, 5);
uint32_t lsb_mask;
DecodeStatus S = MCDisassembler_Success;
if (lsb > msb) {
@ -1309,7 +1319,7 @@ static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val,
uint32_t msb_mask = 0xFFFFFFFF;
if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
uint32_t lsb_mask = (1U << lsb) - 1;
lsb_mask = (1U << lsb) - 1;
MCInst_addOperand(Inst, MCOperand_CreateImm(~(msb_mask ^ lsb_mask)));
return S;
@ -1405,7 +1415,7 @@ static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn,
case ARM_STCL_OFFSET:
case ARM_STC_PRE:
case ARM_STCL_PRE:
imm = ARM_AM_getAM5Opc(U ? ARM_AM_add : ARM_AM_sub, imm);
imm = ARM_AM_getAM5Opc(U ? ARM_AM_add : ARM_AM_sub, (unsigned char)imm);
MCInst_addOperand(Inst, MCOperand_CreateImm(imm));
break;
case ARM_t2LDC2_POST:
@ -1464,6 +1474,8 @@ static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
ARM_AM_AddrOpc Op;
ARM_AM_ShiftOpc Opc;
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
@ -1514,7 +1526,7 @@ static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn,
if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler_Fail;
ARM_AM_AddrOpc Op = ARM_AM_add;
Op = ARM_AM_add;
if (!fieldFromInstruction_4(Insn, 23, 1))
Op = ARM_AM_sub;
@ -1531,7 +1543,7 @@ static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn,
if (reg) {
if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler_Fail;
ARM_AM_ShiftOpc Opc = ARM_AM_lsl;
Opc = ARM_AM_lsl;
switch( fieldFromInstruction_4(Insn, 5, 2)) {
case 0:
Opc = ARM_AM_lsl;
@ -1570,6 +1582,7 @@ static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val,
uint64_t Address, const void *Decoder)
{
DecodeStatus S = MCDisassembler_Success;
ARM_AM_ShiftOpc ShOp;
unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
@ -1577,7 +1590,7 @@ static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val,
unsigned imm = fieldFromInstruction_4(Val, 7, 5);
unsigned U = fieldFromInstruction_4(Val, 12, 1);
ARM_AM_ShiftOpc ShOp = ARM_AM_lsl;
ShOp = ARM_AM_lsl;
switch (type) {
case 0:
ShOp = ARM_AM_lsl;
@ -2130,8 +2143,8 @@ static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val,
if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler_Fail;
if (!add) imm *= -1;
if (imm == 0 && !add) imm = INT32_MIN;
if (!add) imm *= (unsigned int)-1;
if (imm == 0 && !add) imm = (unsigned int)INT32_MIN;
MCInst_addOperand(Inst, MCOperand_CreateImm(imm));
//if (Rn == 15)
// tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
@ -2152,9 +2165,9 @@ static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val,
return MCDisassembler_Fail;
if (U)
MCInst_addOperand(Inst, MCOperand_CreateImm(ARM_AM_getAM5Opc(ARM_AM_add, imm)));
MCInst_addOperand(Inst, MCOperand_CreateImm(ARM_AM_getAM5Opc(ARM_AM_add, (unsigned char)imm)));
else
MCInst_addOperand(Inst, MCOperand_CreateImm(ARM_AM_getAM5Opc(ARM_AM_sub, imm)));
MCInst_addOperand(Inst, MCOperand_CreateImm(ARM_AM_getAM5Opc(ARM_AM_sub, (unsigned char)imm)));
return S;
}
@ -4891,6 +4904,8 @@ static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val,
static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn,
uint64_t Address, const void *Decoder)
{
DecodeStatus S;
unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4);
unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
@ -4899,7 +4914,7 @@ static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn,
if (pred == 0xF)
return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
DecodeStatus S = MCDisassembler_Success;
S = MCDisassembler_Success;
if (Rt == Rn || Rn == Rt2)
S = MCDisassembler_SoftFail;

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

@ -301,7 +301,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
MCOperand *MO2 = MCInst_getOperand(MI, 2);
MCOperand *MO3 = MCInst_getOperand(MI, 3);
SStream_concat(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp(MCOperand_getImm(MO3))));
SStream_concat(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3))));
printSBitModifierOperand(MI, 6, O);
printPredicateOperand(MI, 4, O);
@ -339,7 +339,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
MCOperand *MO1 = MCInst_getOperand(MI, 1);
MCOperand *MO2 = MCInst_getOperand(MI, 2);
SStream_concat(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp(MCOperand_getImm(MO2))));
SStream_concat(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2))));
printSBitModifierOperand(MI, 5, O);
printPredicateOperand(MI, 3, O);
@ -359,13 +359,13 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
MI->flat_insn.arm.op_count++;
}
if (ARM_AM_getSORegShOp(MCOperand_getImm(MO2)) == ARM_AM_rrx) {
if (ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)) == ARM_AM_rrx) {
//printAnnotation(O, Annot);
return;
}
SStream_concat(O, ", %s", markup("<imm:"));
unsigned tmp = translateShiftImm(getSORegOffset(MCOperand_getImm(MO2)));
unsigned tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
@ -373,7 +373,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
SStream_concat(O, markup(">"));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.type =
(arm_shifter)ARM_AM_getSORegShOp(MCOperand_getImm(MO2));
(arm_shifter)ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2));
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = tmp;
}
return;
@ -505,30 +505,30 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
case ARM_STREXD:
case ARM_LDAEXD:
case ARM_STLEXD: {
MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID);
bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD;
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0));
if (MCRegisterClass_contains(MRC, Reg)) {
MCInst NewMI;
MCOperand *NewReg;
MCInst_setOpcode(&NewMI, Opcode);
if (isStore)
MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0));
NewReg = MCOperand_CreateReg(MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0,
MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID)));
MCInst_addOperand2(&NewMI, NewReg);
cs_mem_free(NewReg);
// Copy the rest operands into NewMI.
unsigned i;
for(i= isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i)
MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
printInstruction(&NewMI, O, MRI);
return;
MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID);
bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD;
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0));
if (MCRegisterClass_contains(MRC, Reg)) {
MCInst NewMI;
MCOperand *NewReg;
MCInst_setOpcode(&NewMI, Opcode);
if (isStore)
MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0));
NewReg = MCOperand_CreateReg(MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0,
MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID)));
MCInst_addOperand2(&NewMI, NewReg);
cs_mem_free(NewReg);
// Copy the rest operands into NewMI.
unsigned i;
for(i= isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i)
MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
printInstruction(&NewMI, O, MRI);
return;
}
}
}
}
//if (printAliasInstr(MI, O, MRI))
@ -556,8 +556,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
}
} else if (MCOperand_isImm(Op)) {
SStream_concat(O, markup("<imm:"));
//O << "#" << formatImm(Op.getImm());
int32_t imm = MCOperand_getImm(Op);
int32_t imm = (int32_t)MCOperand_getImm(Op);
// relative branch only has relative offset, so we have to update it
// to reflect absolute address.
@ -566,9 +565,9 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
if (ARM_rel_branch(MI->csh, MCInst_getOpcode(MI))) {
// only do this for relative branch
if (MI->csh->mode & CS_MODE_THUMB)
imm += MI->address + 4;
imm += (int32_t)MI->address + 4;
else
imm += MI->address + 8;
imm += (int32_t)MI->address + 8;
if (imm > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", imm);
@ -641,7 +640,7 @@ static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
}
// Print the shift opc.
ARM_AM_ShiftOpc ShOpc = ARM_AM_getSORegShOp(MCOperand_getImm(MO3));
ARM_AM_ShiftOpc ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3));
SStream_concat(O, ", ");
SStream_concat(O, ARM_AM_getShiftOpcStr(ShOpc));
if (ShOpc == ARM_AM_rrx)
@ -664,13 +663,13 @@ static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.type = MCOperand_getImm(MO2) & 7;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.value = MCOperand_getImm(MO2) >> 3;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.value = (unsigned int)MCOperand_getImm(MO2) >> 3;
MI->flat_insn.arm.op_count++;
}
// Print the shift opc.
printRegImmShift(MI, O, ARM_AM_getSORegShOp(MCOperand_getImm(MO2)),
getSORegOffset(MCOperand_getImm(MO2)), UseMarkup);
printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)),
getSORegOffset((unsigned int)MCOperand_getImm(MO2)), UseMarkup);
}
//===--------------------------------------------------------------------===//
@ -692,15 +691,15 @@ static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O)
}
if (!MCOperand_getReg(MO2)) {
unsigned tmp = getAM2Offset(MCOperand_getImm(MO3));
unsigned tmp = getAM2Offset((unsigned int)MCOperand_getImm(MO3));
if (tmp) { // Don't print +0.
SStream_concat(O, ", %s", markup("<imm:"));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO3))), tmp);
SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO3))), tmp);
else
SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO3))), tmp);
SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO3))), tmp);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.type = (arm_shifter)getAM2Op(MCOperand_getImm(MO3));
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.type = (arm_shifter)getAM2Op((unsigned int)MCOperand_getImm(MO3));
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].shift.value = tmp;
}
SStream_concat(O, markup(">"));
@ -711,14 +710,14 @@ static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O)
}
SStream_concat(O, ", ");
SStream_concat(O, ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO3))));
SStream_concat(O, ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO3))));
printRegName(O, MCOperand_getReg(MO2));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
}
printRegImmShift(MI, O, getAM2ShiftOpc(MCOperand_getImm(MO3)),
getAM2Offset(MCOperand_getImm(MO3)), UseMarkup);
printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO3)),
getAM2Offset((unsigned int)MCOperand_getImm(MO3)), UseMarkup);
SStream_concat(O, "]%s", markup(">"));
set_mem_access(MI, false);
}
@ -779,14 +778,14 @@ static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
if (!MCOperand_getReg(MO1)) {
unsigned ImmOffs = getAM2Offset(MCOperand_getImm(MO2));
unsigned ImmOffs = getAM2Offset((unsigned int)MCOperand_getImm(MO2));
if (ImmOffs > HEX_THRESHOLD)
SStream_concat(O, "%s#%s0x%x%s", markup("<imm:"),
ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO2))), ImmOffs,
ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO2))), ImmOffs,
markup(">"));
else
SStream_concat(O, "%s#%s%u%s", markup("<imm:"),
ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO2))), ImmOffs,
ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO2))), ImmOffs,
markup(">"));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
@ -796,7 +795,7 @@ static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
return;
}
SStream_concat(O, ARM_AM_getAddrOpcStr(getAM2Op(MCOperand_getImm(MO2))));
SStream_concat(O, ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO2))));
printRegName(O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
@ -804,8 +803,8 @@ static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
MI->flat_insn.arm.op_count++;
}
printRegImmShift(MI, O, getAM2ShiftOpc(MCOperand_getImm(MO2)),
getAM2Offset(MCOperand_getImm(MO2)), UseMarkup);
printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO2)),
getAM2Offset((unsigned int)MCOperand_getImm(MO2)), UseMarkup);
}
//===--------------------------------------------------------------------===//
@ -817,7 +816,7 @@ static void printAM3PostIndexOp(MCInst *MI, unsigned Op, SStream *O)
MCOperand *MO1 = MCInst_getOperand(MI, Op);
MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
ARM_AM_AddrOpc op = getAM3Op(MCOperand_getImm(MO3));
ARM_AM_AddrOpc op = getAM3Op((unsigned int)MCOperand_getImm(MO3));
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
@ -838,7 +837,7 @@ static void printAM3PostIndexOp(MCInst *MI, unsigned Op, SStream *O)
return;
}
unsigned ImmOffs = getAM3Offset(MCOperand_getImm(MO3));
unsigned ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3));
if (ImmOffs > HEX_THRESHOLD)
SStream_concat(O, "%s#%s0x%x%s", markup("<imm:"),
ARM_AM_getAddrOpcStr(op), ImmOffs,
@ -854,7 +853,7 @@ static void printAM3PostIndexOp(MCInst *MI, unsigned Op, SStream *O)
if (op)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = ImmOffs;
else
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = -ImmOffs;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = -(int)ImmOffs;
MI->flat_insn.arm.op_count++;
}
@ -866,7 +865,7 @@ static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O,
MCOperand *MO1 = MCInst_getOperand(MI, Op);
MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
ARM_AM_AddrOpc op = getAM3Op(MCOperand_getImm(MO3));
ARM_AM_AddrOpc op = getAM3Op((unsigned int)MCOperand_getImm(MO3));
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
@ -888,7 +887,7 @@ static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O,
}
//If the op is sub we have to print the immediate even if it is 0
unsigned ImmOffs = getAM3Offset(MCOperand_getImm(MO3));
unsigned ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3));
if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM_sub)) {
if (ImmOffs > HEX_THRESHOLD)
@ -901,9 +900,9 @@ static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O,
if (MI->csh->detail) {
if (op)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = MCOperand_getImm(MO3);
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = (int)MCOperand_getImm(MO3);
else
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = -MCOperand_getImm(MO3);
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.disp = (int)-MCOperand_getImm(MO3);
}
SStream_concat(O, "]%s", markup(">"));
@ -920,7 +919,7 @@ static void printAddrMode3Operand(MCInst *MI, unsigned Op, SStream *O,
}
MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
unsigned IdxMode = getAM3IdxMode(MCOperand_getImm(MO3));
unsigned IdxMode = getAM3IdxMode((unsigned int)MCOperand_getImm(MO3));
if (IdxMode == ARMII_IndexModePost) {
printAM3PostIndexOp(MI, Op, O);
@ -934,7 +933,7 @@ static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
ARM_AM_AddrOpc op = getAM3Op(MCOperand_getImm(MO2));
ARM_AM_AddrOpc op = getAM3Op((unsigned int)MCOperand_getImm(MO2));
if (MCOperand_getReg(MO1)) {
SStream_concat(O, ARM_AM_getAddrOpcStr(op));
@ -947,7 +946,7 @@ static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
return;
}
unsigned ImmOffs = getAM3Offset(MCOperand_getImm(MO2));
unsigned ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO2));
if (ImmOffs > HEX_THRESHOLD)
SStream_concat(O, "%s#%s0x%x%s", markup("<imm:"),
ARM_AM_getAddrOpcStr(op), ImmOffs,
@ -962,7 +961,7 @@ static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
if (op)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = ImmOffs;
else
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = -ImmOffs;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = -(int)ImmOffs;
MI->flat_insn.arm.op_count++;
}
@ -971,7 +970,7 @@ static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
unsigned Imm = MCOperand_getImm(MO);
unsigned Imm = (unsigned int)MCOperand_getImm(MO);
if ((Imm & 0xff) > HEX_THRESHOLD)
SStream_concat(O, "%s#%s0x%x%s", markup("<imm:"), ((Imm & 256) ? "" : "-"),
(Imm & 0xff), markup(">"));
@ -1002,7 +1001,7 @@ static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
unsigned Imm = MCOperand_getImm(MO);
unsigned Imm = (unsigned int)MCOperand_getImm(MO);
if (((Imm & 0xff) << 2) > HEX_THRESHOLD)
SStream_concat(O, "%s#%s0x%x%s", markup("<imm:"), ((Imm & 256) ? "" : "-"),
((Imm & 0xff) << 2), markup(">"));
@ -1025,16 +1024,16 @@ static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O,
SStream_concat(O, "%s[", markup("<mem:"));
printRegName(O, MCOperand_getReg(MO1));
unsigned ImmOffs = ARM_AM_getAM5Offset(MCOperand_getImm(MO2));
unsigned Op = ARM_AM_getAM5Op(MCOperand_getImm(MO2));
unsigned ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2));
unsigned Op = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2));
if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM_sub) {
if (ImmOffs * 4 > HEX_THRESHOLD)
SStream_concat(O, ", %s#%s0x%x%s", markup("<imm:"),
ARM_AM_getAddrOpcStr(ARM_AM_getAM5Op(MCOperand_getImm(MO2))),
ARM_AM_getAddrOpcStr(ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2))),
ImmOffs * 4, markup(">"));
else
SStream_concat(O, ", %s#%s%u%s", markup("<imm:"),
ARM_AM_getAddrOpcStr(ARM_AM_getAM5Op(MCOperand_getImm(MO2))),
ARM_AM_getAddrOpcStr(ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2))),
ImmOffs * 4, markup(">"));
}
SStream_concat(O, "]%s", markup(">"));
@ -1050,7 +1049,7 @@ static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O)
printRegName(O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
unsigned tmp = MCOperand_getImm(MO2);
unsigned tmp = (unsigned int)MCOperand_getImm(MO2);
if (tmp) {
if (tmp << 3 > HEX_THRESHOLD)
SStream_concat(O, ":0x%x", (tmp << 3));
@ -1094,7 +1093,7 @@ static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
uint32_t v = ~MCOperand_getImm(MO);
uint32_t v = ~(uint32_t)MCOperand_getImm(MO);
int32_t lsb = CountTrailingZeros_32(v);
int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
@ -1121,7 +1120,7 @@ static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *
static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
// FIXME: HasV80Ops becomes a mode
// SStream_concat(O, ARM_MB_MemBOptToString(val,
// ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops));
@ -1130,13 +1129,13 @@ static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O)
void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
SStream_concat(O, "%s", ARM_ISB_InstSyncBOptToString(val));
}
static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned ShiftOp = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
bool isASR = (ShiftOp & (1 << 5)) != 0;
unsigned Amt = ShiftOp & 0x1f;
if (isASR) {
@ -1163,7 +1162,7 @@ static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (Imm == 0)
return;
//assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
@ -1179,7 +1178,7 @@ static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O)
static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
// A shift amount of 32 is encoded as 0.
if (Imm == 0)
Imm = 32;
@ -1243,13 +1242,13 @@ static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O)
static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNum);
SStream_concat(O, "%s", ARM_PROC_IModToString(MCOperand_getImm(Op)));
SStream_concat(O, "%s", ARM_PROC_IModToString((unsigned int)MCOperand_getImm(Op)));
}
static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNum);
unsigned IFlags = MCOperand_getImm(Op);
unsigned IFlags = (unsigned int)MCOperand_getImm(Op);
int i;
for (i=2; i >= 0; --i)
if (IFlags & (1 << i))
@ -1269,13 +1268,16 @@ static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O)
static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNum);
unsigned SpecRegRBit = MCOperand_getImm(Op) >> 4;
unsigned Mask = MCOperand_getImm(Op) & 0xf;
#if 0 // TODO once below is fixed
unsigned SpecRegRBit = (unsigned int)MCOperand_getImm(Op) >> 4;
unsigned Mask = (unsigned int)MCOperand_getImm(Op) & 0xf;
#endif
// FIXME: FeatureMClass becomes mode??
//if (ARM_getFeatureBits(MI->csh->mode) & ARM_FeatureMClass) {
if (true) {
unsigned SYSm = MCOperand_getImm(Op);
//if (true)
{
unsigned SYSm = (unsigned int)MCOperand_getImm(Op);
unsigned Opcode = MCInst_getOpcode(MI);
// For reads of the special registers ignore the "mask encoding" bits
// which are only for writes.
@ -1321,7 +1323,7 @@ static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
case 0x814: SStream_concat(O, "control"); return;
}
}
#if 0 // TODO once above is fixed
// As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
// APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
@ -1346,6 +1348,7 @@ static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
if (Mask & 2) SStream_concat(O, "x");
if (Mask & 1) SStream_concat(O, "c");
}
#endif
}
static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
@ -1387,7 +1390,7 @@ static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O)
static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned tmp = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "0x%x", tmp);
else
@ -1408,7 +1411,7 @@ static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat(O, "p%u", MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_PIMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
}
@ -1418,14 +1421,14 @@ static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat(O, "c%u", MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_CIMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
}
static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned tmp = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "{0x%x}", tmp);
else
@ -1471,24 +1474,22 @@ static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigne
static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
//<< "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
unsigned tmp = MCOperand_getImm(MCInst_getOperand(MI, OpNum)) * 4;
unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)) * 4;
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "%s#0x%x", markup("<imm:"), tmp);
else
SStream_concat(O, "%s#%u", markup("<imm:"), tmp);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = tmp;
MI->flat_insn.arm.op_count++;
}
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = tmp;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, markup(">"));
}
static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
// << "#" << formatImm((Imm == 0 ? 32 : Imm))
unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned tmp = Imm == 0 ? 32 : Imm;
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "%s#0x%x", markup("<imm:"), tmp);
@ -1507,8 +1508,8 @@ static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O)
static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O)
{
// (3 - the number of trailing zeros) is the number of then / else.
unsigned Mask = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned Firstcond = MCOperand_getImm(MCInst_getOperand(MI, OpNum-1));
unsigned Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum-1));
unsigned CondBit0 = Firstcond & 1;
unsigned NumTZ = CountTrailingZeros_32(Mask);
//assert(NumTZ <= 3 && "Invalid IT mask!");
@ -1567,7 +1568,7 @@ static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned Op, SStream *O,
printRegName(O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
unsigned ImmOffs = MCOperand_getImm(MO2);
unsigned ImmOffs = (unsigned int)MCOperand_getImm(MO2);
if (ImmOffs) {
unsigned tmp = ImmOffs * Scale;
SStream_concat(O, ", %s", markup("<imm:"));
@ -1623,8 +1624,8 @@ static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O)
// Print the shift opc.
//assert(MO2.isImm() && "Not a valid t2_so_reg value!");
printRegImmShift(MI, O, ARM_AM_getSORegShOp(MCOperand_getImm(MO2)),
getSORegOffset(MCOperand_getImm(MO2)), UseMarkup);
printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)),
getSORegOffset((unsigned int)MCOperand_getImm(MO2)), UseMarkup);
}
static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum,
@ -1632,6 +1633,8 @@ static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum,
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
int32_t OffImm;
bool isSub;
if (!MCOperand_isReg(MO1)) { // FIXME: This is for CP entries, but isn't right.
printOperand(MI, OpNum, O);
@ -1646,8 +1649,8 @@ static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum,
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
int32_t OffImm = (int32_t)MCOperand_getImm(MO2);
bool isSub = OffImm < 0;
OffImm = (int32_t)MCOperand_getImm(MO2);
isSub = OffImm < 0;
// Special value for #-0. All others are normal.
if (OffImm == INT32_MIN)
OffImm = 0;
@ -1670,6 +1673,8 @@ static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O,
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
int32_t OffImm;
bool isSub;
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
@ -1678,8 +1683,8 @@ static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O,
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
int32_t OffImm = (int32_t)MCOperand_getImm(MO2);
bool isSub = OffImm < 0;
OffImm = (int32_t)MCOperand_getImm(MO2);
isSub = OffImm < 0;
// Don't print +0.
if (OffImm == INT32_MIN)
OffImm = 0;
@ -1704,6 +1709,8 @@ static void printT2AddrModeImm8s4Operand(MCInst *MI,
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
int32_t OffImm;
bool isSub;
if (!MCOperand_isReg(MO1)) { // For label symbolic references.
printOperand(MI, OpNum, O);
@ -1717,8 +1724,8 @@ static void printT2AddrModeImm8s4Operand(MCInst *MI,
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
int32_t OffImm = (int32_t)MCOperand_getImm(MO2);
bool isSub = OffImm < 0;
OffImm = (int32_t)MCOperand_getImm(MO2);
isSub = OffImm < 0;
//assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
@ -1754,9 +1761,7 @@ static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStrea
if (MCOperand_getImm(MO2)) {
SStream_concat(O, ", ");
SStream_concat(O, markup("<imm:"));
//<< "#" <<
// formatImm(MCOperand_getImm(MO2.getImm() * 4)
unsigned tmp = MCOperand_getImm(MO2) * 4;
unsigned tmp = (unsigned int)MCOperand_getImm(MO2) * 4;
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
@ -1851,7 +1856,7 @@ static void printT2AddrModeSoRegOperand(MCInst *MI,
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
unsigned ShAmt = MCOperand_getImm(MO3);
unsigned ShAmt = (unsigned int)MCOperand_getImm(MO3);
if (ShAmt) {
//assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
SStream_concat(O, ", lsl ");
@ -1871,17 +1876,17 @@ static void printT2AddrModeSoRegOperand(MCInst *MI,
static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
SStream_concat(O, "%s#%f%s", markup("<imm:"), getFPImmFloat(MCOperand_getImm(MO)), markup(">"));
SStream_concat(O, "%s#%f%s", markup("<imm:"), getFPImmFloat((unsigned int)MCOperand_getImm(MO)), markup(">"));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_FP;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].fp = getFPImmFloat(MCOperand_getImm(MO));
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO));
MI->flat_insn.arm.op_count++;
}
}
static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned EncodedImm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned EncodedImm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned EltBits;
uint64_t Val = ARM_AM_decodeNEONModImm(EncodedImm, &EltBits);
if (Val > HEX_THRESHOLD)
@ -1890,14 +1895,14 @@ static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat(O, "%s#%"PRIu64"%s", markup("<imm:"), Val, markup(">"));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_IMM;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = Val;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = (unsigned int)Val;
MI->flat_insn.arm.op_count++;
}
}
static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (Imm + 1 > HEX_THRESHOLD)
SStream_concat(O, "%s#0x%x%s", markup("<imm:"), Imm + 1, markup(">"));
else
@ -1911,7 +1916,7 @@ static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O)
static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (Imm == 0)
return;
SStream_concat(O, ", ror %s#", markup("<imm:"));
@ -1931,7 +1936,7 @@ static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O)
{
SStream_concat(O, markup("<imm:"));
unsigned tmp = 16 - MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
@ -1947,7 +1952,7 @@ static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O)
static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O)
{
SStream_concat(O, markup("<imm:"));
unsigned tmp = 32 - MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
@ -1962,7 +1967,7 @@ static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O)
static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned tmp = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "[0x%x]",tmp);
else

File diff suppressed because it is too large Load Diff

@ -14,14 +14,8 @@ const char *ARM_reg_name(csh handle, unsigned int reg);
// given internal insn id, return public instruction ID
void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
// given public insn id, return internal instruction info
unsigned int ARM_get_insn_id2(unsigned int id);
const char *ARM_insn_name(csh handle, unsigned int id);
// map instruction name to instruction ID
arm_reg ARM_map_insn(const char *name);
// check if this insn is relative branch
bool ARM_rel_branch(cs_struct *h, unsigned int insn_id);

@ -9,12 +9,14 @@
static cs_err init(cs_struct *ud)
{
MCRegisterInfo *mri;
// verify if requested mode is valid
if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM |
CS_MODE_THUMB | CS_MODE_BIG_ENDIAN))
return CS_ERR_MODE;
MCRegisterInfo *mri = cs_mem_malloc(sizeof(*mri));
mri = cs_mem_malloc(sizeof(*mri));
ARM_init(mri);

@ -152,7 +152,7 @@ static DecodeStatus DecodeExtSize(MCInst *Inst,
// Hacky: enable all features for disassembler
static uint64_t getFeatureBits(int mode)
{
uint64_t Bits = -1; // include every features by default
uint64_t Bits = (uint64_t)-1; // include every features by default
// ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate()
// some features are mutually execlusive
@ -193,7 +193,7 @@ static uint64_t getFeatureBits(int mode)
void Mips_init(MCRegisterInfo *MRI)
{
// InitMCRegisterInfo(MipsRegDesc, 317,
// InitMCRegisterInfo(MipsRegDesc, 317,
// RA, PC,
// MipsMCRegisterClasses, 34,
// MipsRegUnitRoots, 196,
@ -249,12 +249,13 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI)
{
uint32_t Insn;
DecodeStatus Result;
if (code_len < 4)
// not enough data
return MCDisassembler_Fail;
DecodeStatus Result = readInstruction32((unsigned char*)code, &Insn, isBigEndian,
Result = readInstruction32((unsigned char*)code, &Insn, isBigEndian,
mode & CS_MODE_MICRO);
if (Result == MCDisassembler_Fail)
return MCDisassembler_Fail;
@ -715,16 +716,16 @@ static DecodeStatus DecodeSimm16(MCInst *Inst,
static DecodeStatus DecodeLSAImm(MCInst *Inst,
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
{
// We add one to the immediate field as it was encoded as 'imm - 1'.
MCInst_addOperand(Inst, MCOperand_CreateImm(Insn + 1));
return MCDisassembler_Success;
// We add one to the immediate field as it was encoded as 'imm - 1'.
MCInst_addOperand(Inst, MCOperand_CreateImm(Insn + 1));
return MCDisassembler_Success;
}
static DecodeStatus DecodeInsSize(MCInst *Inst,
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
{
// First we need to grab the pos(lsb) from MCInst.
int Pos = MCOperand_getImm(MCInst_getOperand(Inst, 2));
int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2));
int Size = (int) Insn - Pos + 1;
MCInst_addOperand(Inst, MCOperand_CreateImm(SignExtend32(Size, 16)));
return MCDisassembler_Success;

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

@ -29,8 +29,8 @@
#include "MipsInstPrinter.h"
static void printUnsignedImm(MCInst *MI, int opNum, SStream *O);
static bool printAliasInstr(MCInst *MI, SStream *O, void *info);
static bool printAlias(MCInst *MI, SStream *OS);
static char *printAliasInstr(MCInst *MI, SStream *O, void *info);
static char *printAlias(MCInst *MI, SStream *OS);
// These enumeration declarations were originally in MipsInstrInfo.h but
// had to be moved here to avoid circular dependencies between
@ -165,6 +165,8 @@ static void printSaveRestore(MCInst *MI, SStream *O)
void Mips_printInst(MCInst *MI, SStream *O, void *info)
{
char *mnem;
switch (MCInst_getOpcode(MI)) {
default: break;
case Mips_RDHWR:
@ -195,19 +197,16 @@ void Mips_printInst(MCInst *MI, SStream *O, void *info)
}
// Try to print any aliases first.
if (!printAliasInstr(MI, O, info) && !printAlias(MI, O))
printInstruction(MI, O, NULL);
else {
mnem = printAliasInstr(MI, O, info);
if (!mnem) {
mnem = printAlias(MI, O);
if (!mnem)
printInstruction(MI, O, NULL);
}
if (mnem) {
// fixup instruction id due to the change in alias instruction
char *mnem = cs_strdup(O->buffer);
char *tab = strchr(mnem, '\t');
if (tab)
*tab = '\0';
// reflect the new insn name (alias) in the opcode
unsigned id = Mips_map_insn(mnem);
MCInst_setOpcode(MI, Mips_get_insn_id2(id));
MCInst_setOpcodePub(MI, id);
MCInst_setOpcodePub(MI, Mips_map_insn(mnem));
cs_mem_free(mnem);
}
@ -351,69 +350,96 @@ static void printFCCOperand(MCInst *MI, int opNum, SStream *O)
SStream_concat(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO)));
}
static bool printAlias1(char *Str, MCInst *MI, unsigned OpNo, SStream *OS)
static char *printAlias1(char *Str, MCInst *MI, unsigned OpNo, SStream *OS)
{
SStream_concat(OS, "%s\t", Str);
printOperand(MI, OpNo, OS);
return true;
return cs_strdup(Str);
}
static bool printAlias2(char *Str, MCInst *MI,
static char *printAlias2(char *Str, MCInst *MI,
unsigned OpNo0, unsigned OpNo1, SStream *OS)
{
printAlias1(Str, MI, OpNo0, OS);
char *tmp;
tmp = printAlias1(Str, MI, OpNo0, OS);
SStream_concat(OS, ", ");
printOperand(MI, OpNo1, OS);
return true;
return tmp;
}
#define GET_REGINFO_ENUM
#include "MipsGenRegisterInfo.inc"
static bool printAlias(MCInst *MI, SStream *OS)
static char *printAlias(MCInst *MI, SStream *OS)
{
switch (MCInst_getOpcode(MI)) {
case Mips_BEQ:
// beq $zero, $zero, $L2 => b $L2
// beq $r0, $zero, $L2 => beqz $r0, $L2
return (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO) &&
printAlias1("b", MI, 2, OS)) ||
(isReg(MI, 1, Mips_ZERO) && printAlias2("beqz", MI, 0, 2, OS));
if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO))
return printAlias1("b", MI, 2, OS);
if (isReg(MI, 1, Mips_ZERO))
return printAlias2("beqz", MI, 0, 2, OS);
return NULL;
case Mips_BEQ64:
// beq $r0, $zero, $L2 => beqz $r0, $L2
return isReg(MI, 1, Mips_ZERO_64) && printAlias2("beqz", MI, 0, 2, OS);
if (isReg(MI, 1, Mips_ZERO_64))
return printAlias2("beqz", MI, 0, 2, OS);
return NULL;
case Mips_BNE:
// bne $r0, $zero, $L2 => bnez $r0, $L2
return isReg(MI, 1, Mips_ZERO) && printAlias2("bnez", MI, 0, 2, OS);
if (isReg(MI, 1, Mips_ZERO))
return printAlias2("bnez", MI, 0, 2, OS);
return NULL;
case Mips_BNE64:
// bne $r0, $zero, $L2 => bnez $r0, $L2
return isReg(MI, 1, Mips_ZERO_64) && printAlias2("bnez", MI, 0, 2, OS);
if (isReg(MI, 1, Mips_ZERO_64))
return printAlias2("bnez", MI, 0, 2, OS);
return NULL;
case Mips_BGEZAL:
// bgezal $zero, $L1 => bal $L1
return isReg(MI, 0, Mips_ZERO) && printAlias1("bal", MI, 1, OS);
if (isReg(MI, 0, Mips_ZERO))
return printAlias1("bal", MI, 1, OS);
return NULL;
case Mips_BC1T:
// bc1t $fcc0, $L1 => bc1t $L1
return isReg(MI, 0, Mips_FCC0) && printAlias1("bc1t", MI, 1, OS);
if (isReg(MI, 0, Mips_FCC0))
return printAlias1("bc1t", MI, 1, OS);
return NULL;
case Mips_BC1F:
// bc1f $fcc0, $L1 => bc1f $L1
return isReg(MI, 0, Mips_FCC0) && printAlias1("bc1f", MI, 1, OS);
if (isReg(MI, 0, Mips_FCC0))
return printAlias1("bc1f", MI, 1, OS);
return NULL;
case Mips_JALR:
// jalr $ra, $r1 => jalr $r1
return isReg(MI, 0, Mips_RA) && printAlias1("jalr", MI, 1, OS);
if (isReg(MI, 0, Mips_RA))
return printAlias1("jalr", MI, 1, OS);
return NULL;
case Mips_JALR64:
// jalr $ra, $r1 => jalr $r1
return isReg(MI, 0, Mips_RA_64) && printAlias1("jalr", MI, 1, OS);
if (isReg(MI, 0, Mips_RA_64))
return printAlias1("jalr", MI, 1, OS);
return NULL;
case Mips_NOR:
case Mips_NOR_MM:
// nor $r0, $r1, $zero => not $r0, $r1
return isReg(MI, 2, Mips_ZERO) && printAlias2("not", MI, 0, 1, OS);
if (isReg(MI, 2, Mips_ZERO))
return printAlias2("not", MI, 0, 1, OS);
return NULL;
case Mips_NOR64:
// nor $r0, $r1, $zero => not $r0, $r1
return isReg(MI, 2, Mips_ZERO_64) && printAlias2("not", MI, 0, 1, OS);
if (isReg(MI, 2, Mips_ZERO_64))
return printAlias2("not", MI, 0, 1, OS);
return NULL;
case Mips_OR:
// or $r0, $r1, $zero => move $r0, $r1
return isReg(MI, 2, Mips_ZERO) && printAlias2("move", MI, 0, 1, OS);
default: return false;
if (isReg(MI, 2, Mips_ZERO))
return printAlias2("move", MI, 0, 1, OS);
return NULL;
default: return NULL;
}
}

File diff suppressed because it is too large Load Diff

@ -13,9 +13,6 @@ const char *Mips_reg_name(csh handle, unsigned int reg);
// given internal insn id, return public instruction info
void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
// given public insn id, return internal insn id
unsigned int Mips_get_insn_id2(unsigned int id);
// given public insn id, return internal insn id
const char *Mips_insn_name(csh handle, unsigned int id);

@ -11,12 +11,14 @@ void enable_mips() {};
static cs_err init(cs_struct *ud)
{
MCRegisterInfo *mri;
// verify if requested mode is valid
if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 |
CS_MODE_MICRO | CS_MODE_N64 | CS_MODE_BIG_ENDIAN))
return CS_ERR_MODE;
MCRegisterInfo *mri = cs_mem_malloc(sizeof(*mri));
mri = cs_mem_malloc(sizeof(*mri));
Mips_init(mri);
ud->printer = Mips_printInst;

@ -104,7 +104,7 @@ static const unsigned G8Regs[] = {
static uint64_t getFeatureBits(int feature)
{
// enable all features
return -1;
return (uint64_t)-1;
}
static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo,

@ -134,10 +134,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
1226217U, // BCLR
1357289U, // BCLRL
155725U, // BCLalways
5697U, // BCTR
5697U, // BCTR8
5659U, // BCTRL
5659U, // BCTRL8
5703U, // BCTR
5703U, // BCTR8
5665U, // BCTRL
5665U, // BCTRL8
159972U, // BDNZ
159972U, // BDNZ8
165245U, // BDNZA
@ -147,9 +147,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
165226U, // BDNZLA
163950U, // BDNZLAm
163865U, // BDNZLAp
5690U, // BDNZLR
5690U, // BDNZLR8
5651U, // BDNZLRL
5696U, // BDNZLR
5696U, // BDNZLR8
5657U, // BDNZLRL
4422U, // BDNZLRLm
4390U, // BDNZLRLp
4438U, // BDNZLRm
@ -167,9 +167,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
165219U, // BDZLA
163942U, // BDZLAm
163857U, // BDZLAp
5684U, // BDZLR
5684U, // BDZLR8
5644U, // BDZLRL
5690U, // BDZLR
5690U, // BDZLR8
5650U, // BDZLRL
4414U, // BDZLRLm
4382U, // BDZLRLp
4431U, // BDZLRm
@ -187,8 +187,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
165208U, // BLA
165208U, // BLA8
1475928U, // BLA8_NOP
5680U, // BLR
5639U, // BLRL
5686U, // BLR
5645U, // BLRL
1610623186U, // CLRLSLDI
1610621433U, // CLRLSLDIo
2147494212U, // CLRLSLWI
@ -238,7 +238,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
9196U, // DIVWUo
9301U, // DIVWo
68870U, // DSS
5632U, // DSSALL
5638U, // DSSALL
77242U, // DST
77242U, // DST64
77255U, // DSTST
@ -254,7 +254,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
4647U, // EH_SjLj_SetJmp32
4827U, // EH_SjLj_SetJmp64
155649U, // EH_SjLj_Setup
5665U, // EIEIO
5671U, // EIEIO
11872U, // EQV
11872U, // EQV8
9211U, // EQV8o
@ -419,7 +419,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
5482U, // LDgotTprelL
4613U, // LDgotTprelL32
1585417U, // LDinto_toc
5625U, // LDtoc
5631U, // LDtoc
5578U, // LDtocCPT
5430U, // LDtocJTI
5440U, // LDtocL
@ -495,6 +495,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
1846199U, // MFVRSAVE
1846199U, // MFVRSAVEv
142187U, // MFVSCR
5625U, // MSYNC
67119052U, // MTCRF
67119052U, // MTCRF8
142311U, // MTCTR
@ -538,7 +539,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
67119067U, // NEG8
67117506U, // NEG8o
67117506U, // NEGo
5676U, // NOP
5682U, // NOP
4446U, // NOP_GT_PWR6
4458U, // NOP_GT_PWR7
11156U, // NOR
@ -702,8 +703,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
157064U, // TAILB8
165194U, // TAILBA
165194U, // TAILBA8
5697U, // TAILBCTR
5697U, // TAILBCTR8
5703U, // TAILBCTR
5703U, // TAILBCTR8
67405115U, // TCRETURNai
67405022U, // TCRETURNai8
67397304U, // TCRETURNdi
@ -715,7 +716,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
2066287U, // TLBIE
141730U, // TLBIEL
5611U, // TLBSYNC
5671U, // TRAP
5677U, // TRAP
85746U, // TW
536955269U, // TWI
67118344U, // UPDATE_VRSAVE
@ -1383,6 +1384,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
0U, // MFVRSAVE
0U, // MFVRSAVEv
0U, // MFVSCR
0U, // MSYNC
0U, // MTCRF
0U, // MTCRF8
0U, // MTCTR
@ -1792,7 +1794,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
0U
};
const char AsmStrs[] = {
#ifndef CAPSTONE_DIET
static char AsmStrs[] = {
/* 0 */ '#', 'E', 'H', '_', 'S', 'j', 'L', 'j', '_', 'S', 'e', 't', 'u', 'p', 9, 0,
/* 16 */ 'b', 'd', 'z', 'l', 'a', '+', 32, 0,
/* 24 */ 'b', 'd', 'n', 'z', 'l', 'a', '+', 32, 0,
@ -2437,27 +2440,31 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
/* 5608 */ 'b', 0,
/* 5610 */ 't', 'l', 'b', 's', 'y', 'n', 'c', 0,
/* 5618 */ 'i', 's', 'y', 'n', 'c', 0,
/* 5624 */ '#', 'L', 'D', 't', 'o', 'c', 0,
/* 5631 */ 'd', 's', 's', 'a', 'l', 'l', 0,
/* 5638 */ 'b', 'l', 'r', 'l', 0,
/* 5643 */ 'b', 'd', 'z', 'l', 'r', 'l', 0,
/* 5650 */ 'b', 'd', 'n', 'z', 'l', 'r', 'l', 0,
/* 5658 */ 'b', 'c', 't', 'r', 'l', 0,
/* 5664 */ 'e', 'i', 'e', 'i', 'o', 0,
/* 5670 */ 't', 'r', 'a', 'p', 0,
/* 5675 */ 'n', 'o', 'p', 0,
/* 5679 */ 'b', 'l', 'r', 0,
/* 5683 */ 'b', 'd', 'z', 'l', 'r', 0,
/* 5689 */ 'b', 'd', 'n', 'z', 'l', 'r', 0,
/* 5696 */ 'b', 'c', 't', 'r', 0,
/* 5624 */ 'm', 's', 'y', 'n', 'c', 0,
/* 5630 */ '#', 'L', 'D', 't', 'o', 'c', 0,
/* 5637 */ 'd', 's', 's', 'a', 'l', 'l', 0,
/* 5644 */ 'b', 'l', 'r', 'l', 0,
/* 5649 */ 'b', 'd', 'z', 'l', 'r', 'l', 0,
/* 5656 */ 'b', 'd', 'n', 'z', 'l', 'r', 'l', 0,
/* 5664 */ 'b', 'c', 't', 'r', 'l', 0,
/* 5670 */ 'e', 'i', 'e', 'i', 'o', 0,
/* 5676 */ 't', 'r', 'a', 'p', 0,
/* 5681 */ 'n', 'o', 'p', 0,
/* 5685 */ 'b', 'l', 'r', 0,
/* 5689 */ 'b', 'd', 'z', 'l', 'r', 0,
/* 5695 */ 'b', 'd', 'n', 'z', 'l', 'r', 0,
/* 5702 */ 'b', 'c', 't', 'r', 0,
};
#endif
// Emit the opcode for the instruction.
uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)];
uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];
uint64_t Bits = (Bits2 << 32) | Bits1;
//assert(Bits != 0 && "Cannot print this instruction.");
// assert(Bits != 0 && "Cannot print this instruction.");
#ifndef CAPSTONE_DIET
SStream_concat(O, "%s", AsmStrs+(Bits & 8191)-1);
#endif
// Fragment 0 encoded into 4 bits for 13 unique commands.
@ -2505,9 +2512,9 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
case 9:
// DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64
printOperand(MI, 2, O);
SStream_concat(O, ", ");
SStream_concat(O, "%s", ", ");
printOperand(MI, 3, O);
SStream_concat(O, ", ");
SStream_concat(O, "%s", ", ");
printU5ImmOperand(MI, 1, O);
return;
break;
@ -2518,7 +2525,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
case 11:
// MTOCRF, MTOCRF8
printcrbitm(MI, 0, O);
SStream_concat(O, ", ");
SStream_concat(O, "%s", ", ");
printOperand(MI, 1, O);
return;
break;
@ -2535,7 +2542,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
default: // unreachable.
case 0:
// ADD4, ADD4TLS, ADD4o, ADD8, ADD8TLS, ADD8TLS_, ADD8o, ADDC, ADDC8, ADD...
SStream_concat(O, ", ");
SStream_concat(O, "%s", ", ");
break;
case 1:
// ADJCALLSTACKDOWN, B, BA, BCLalways, BDNZ, BDNZ8, BDNZA, BDNZAm, BDNZAp...
@ -2543,108 +2550,109 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
break;
case 2:
// ADJCALLSTACKUP, ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, TCRETURNai, ...
SStream_concat(O, " ");
SStream_concat(O, "%s", " ");
break;
case 3:
// BCC
printPredicateOperand(MI, 0, O, "pm");
SStream_concat(O, " ");
SStream_concat(O, "%s", " ");
printPredicateOperand(MI, 0, O, "reg");
SStream_concat(O, ", ");
SStream_concat(O, "%s", ", ");
printBranchOperand(MI, 2, O);
return;
break;
case 4:
// BCCA
SStream_concat(O, "a");
SStream_concat(O, "%s", "a");
printPredicateOperand(MI, 0, O, "pm");
SStream_concat(O, " ");
SStream_concat(O, "%s", " ");
printPredicateOperand(MI, 0, O, "reg");
SStream_concat(O, ", ");
SStream_concat(O, "%s", ", ");
printAbsBranchOperand(MI, 2, O);
return;
break;
case 5:
// BCCL
SStream_concat(O, "l");
SStream_concat(O, "%s", "l");
printPredicateOperand(MI, 0, O, "pm");
SStream_concat(O, " ");
SStream_concat(O, "%s", " ");
printPredicateOperand(MI, 0, O, "reg");
SStream_concat(O, ", ");
SStream_concat(O, "%s", ", ");
printBranchOperand(MI, 2, O);
return;
break;
case 6:
// BCCLA
SStream_concat(O, "la");
SStream_concat(O, "%s", "la");
printPredicateOperand(MI, 0, O, "pm");
SStream_concat(O, " ");
SStream_concat(O, "%s", " ");
printPredicateOperand(MI, 0, O, "reg");
SStream_concat(O, ", ");
SStream_concat(O, "%s", ", ");
printAbsBranchOperand(MI, 2, O);
return;
break;
case 7:
// BCCTR, BCCTR8
SStream_concat(O, "ctr");
SStream_concat(O, "%s", "ctr");
printPredicateOperand(MI, 0, O, "pm");
SStream_concat(O, " ");
SStream_concat(O, "%s", " ");
printPredicateOperand(MI, 0, O, "reg");
return;
break;
case 8:
// BCCTRL, BCCTRL8
SStream_concat(O, "ctrl");
SStream_concat(O, "%s", "ctrl");
printPredicateOperand(MI, 0, O, "pm");
SStream_concat(O, " ");
SStream_concat(O, "%s", " ");
printPredicateOperand(MI, 0, O, "reg");
return;
break;
case 9:
// BCLR
SStream_concat(O, "lr");
SStream_concat(O, "%s", "lr");
printPredicateOperand(MI, 0, O, "pm");
SStream_concat(O, " ");
SStream_concat(O, "%s", " ");
printPredicateOperand(MI, 0, O, "reg");
return;
break;
case 10:
// BCLRL
SStream_concat(O, "lrl");
SStream_concat(O, "%s", "lrl");
printPredicateOperand(MI, 0, O, "pm");
SStream_concat(O, " ");
SStream_concat(O, "%s", " ");
printPredicateOperand(MI, 0, O, "reg");
return;
break;
case 11:
// BL8_NOP, BL8_NOP_TLS, BLA8_NOP
SStream_concat(O, "\n\tnop");
SStream_concat(O, "%s", "\n\tnop");
return;
break;
case 12:
// LDinto_toc
SStream_concat(O, ")");
SStream_concat(O, "%s", ")");
set_mem_access(MI, false);
return;
break;
case 13:
// MFTB8
SStream_concat(O, ", 268");
SStream_concat(O, "%s", ", 268");
return;
break;
case 14:
// MFVRSAVE, MFVRSAVEv
SStream_concat(O, ", 256");
SStream_concat(O, "%s", ", 256");
return;
break;
case 15:
// TLBIE
SStream_concat(O, ",");
SStream_concat(O, "%s", ",");
printOperand(MI, 0, O);
return;
break;
case 16:
// V_SETALLONES, V_SETALLONESB, V_SETALLONESH
SStream_concat(O, ", -1");
SStream_concat(O, "%s", ", -1");
return;
break;
}
@ -2670,18 +2678,18 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
case 3:
// CRSET, CRUNSET, V_SET0, V_SET0B, V_SET0H
printOperand(MI, 0, O);
SStream_concat(O, ", ");
SStream_concat(O, "%s", ", ");
printOperand(MI, 0, O);
return;
break;
case 4:
// LA
printS16ImmOperand(MI, 2, O);
set_mem_access(MI, true);
SStream_concat(O, "(");
SStream_concat(O, "%s", "(");
set_mem_access(MI, true);
printOperand(MI, 1, O);
SStream_concat(O, ")");
set_mem_access(MI, false);
SStream_concat(O, "%s", ")");
set_mem_access(MI, false);
return;
break;
case 5:
@ -2712,7 +2720,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
case 10:
// RLDIMI, RLDIMIo, RLWIMI, RLWIMIo, VCFSX, VCFUX, VCTSXS, VCTUXS, VSPLTB...
printOperand(MI, 2, O);
SStream_concat(O, ", ");
SStream_concat(O, "%s", ", ");
break;
case 11:
// VSPLTISB, VSPLTISH, VSPLTISW
@ -2728,7 +2736,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
default: // unreachable.
case 0:
// ADD4, ADD4TLS, ADD4o, ADD8, ADD8TLS, ADD8TLS_, ADD8o, ADDC, ADDC8, ADD...
SStream_concat(O, ", ");
SStream_concat(O, "%s", ", ");
break;
case 1:
// ADDME, ADDME8, ADDME8o, ADDMEo, ADDZE, ADDZE8, ADDZE8o, ADDZEo, CNTLZD...
@ -2736,25 +2744,25 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
break;
case 2:
// ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32
SStream_concat(O, " ");
SStream_concat(O, "%s", " ");
printOperand(MI, 3, O);
SStream_concat(O, " ");
SStream_concat(O, "%s", " ");
printOperand(MI, 4, O);
return;
break;
case 3:
// RLDIMI, RLDIMIo
printU6ImmOperand(MI, 3, O);
SStream_concat(O, ", ");
SStream_concat(O, "%s", ", ");
printU6ImmOperand(MI, 4, O);
return;
break;
case 4:
// RLWIMI, RLWIMIo
printU5ImmOperand(MI, 3, O);
SStream_concat(O, ", ");
SStream_concat(O, "%s", ", ");
printU5ImmOperand(MI, 4, O);
SStream_concat(O, ", ");
SStream_concat(O, "%s", ", ");
printU5ImmOperand(MI, 5, O);
return;
break;
@ -2765,7 +2773,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
break;
case 6:
// VCFSX_0, VCFUX_0, VCTSXS_0, VCTUXS_0
SStream_concat(O, ", 0");
SStream_concat(O, "%s", ", 0");
return;
break;
}
@ -2814,7 +2822,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
//printf("Frag-5: %"PRIu64"\n", (Bits >> 32) & 1);
if ((Bits >> 32) & 1) {
// CLRLSLDI, CLRLSLDIo, CLRLSLWI, CLRLSLWIo, EXTLDI, EXTLDIo, EXTLWI, EXT...
SStream_concat(O, ", ");
SStream_concat(O, "%s", ", ");
} else {
// ADD4, ADD4TLS, ADD4o, ADD8, ADD8TLS, ADD8TLS_, ADD8o, ADDC, ADDC8, ADD...
return;
@ -2846,7 +2854,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
//printf("Frag-7: %"PRIu64"\n", (Bits >> 35) & 1);
if ((Bits >> 35) & 1) {
// RLWINM, RLWINM8, RLWINM8o, RLWINMo, RLWNM, RLWNMo
SStream_concat(O, ", ");
SStream_concat(O, "%s", ", ");
printU5ImmOperand(MI, 4, O);
return;
} else {
@ -2864,6 +2872,7 @@ static const char *getRegisterName(unsigned RegNo)
{
//assert(RegNo && RegNo < 182 && "Invalid register number!");
#ifndef CAPSTONE_DIET
static const char AsmStrs[] = {
/* 0 */ '*', '*', 'R', 'O', 'U', 'N', 'D', 'I', 'N', 'G', 32, 'M', 'O', 'D', 'E', '*', '*', 0,
/* 18 */ '*', '*', 'F', 'R', 'A', 'M', 'E', 32, 'P', 'O', 'I', 'N', 'T', 'E', 'R', '*', '*', 0,
@ -2993,6 +3002,9 @@ static const char *getRegisterName(unsigned RegNo)
// printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
//printf("*************************\n");
return AsmStrs+RegAsmOffset[RegNo-1];
#else
return NULL;
#endif
}
#ifdef PRINT_ALIAS_INSTR

File diff suppressed because it is too large Load Diff

@ -492,413 +492,414 @@ enum {
PPC_MFVRSAVE = 475,
PPC_MFVRSAVEv = 476,
PPC_MFVSCR = 477,
PPC_MTCRF = 478,
PPC_MTCRF8 = 479,
PPC_MTCTR = 480,
PPC_MTCTR8 = 481,
PPC_MTCTR8loop = 482,
PPC_MTCTRloop = 483,
PPC_MTFSB0 = 484,
PPC_MTFSB1 = 485,
PPC_MTFSF = 486,
PPC_MTLR = 487,
PPC_MTLR8 = 488,
PPC_MTMSR = 489,
PPC_MTMSRD = 490,
PPC_MTOCRF = 491,
PPC_MTOCRF8 = 492,
PPC_MTSPR = 493,
PPC_MTVRSAVE = 494,
PPC_MTVRSAVEv = 495,
PPC_MTVSCR = 496,
PPC_MULHD = 497,
PPC_MULHDU = 498,
PPC_MULHDUo = 499,
PPC_MULHDo = 500,
PPC_MULHW = 501,
PPC_MULHWU = 502,
PPC_MULHWUo = 503,
PPC_MULHWo = 504,
PPC_MULLD = 505,
PPC_MULLDo = 506,
PPC_MULLI = 507,
PPC_MULLI8 = 508,
PPC_MULLW = 509,
PPC_MULLWo = 510,
PPC_MovePCtoLR = 511,
PPC_MovePCtoLR8 = 512,
PPC_NAND = 513,
PPC_NAND8 = 514,
PPC_NAND8o = 515,
PPC_NANDo = 516,
PPC_NEG = 517,
PPC_NEG8 = 518,
PPC_NEG8o = 519,
PPC_NEGo = 520,
PPC_NOP = 521,
PPC_NOP_GT_PWR6 = 522,
PPC_NOP_GT_PWR7 = 523,
PPC_NOR = 524,
PPC_NOR8 = 525,
PPC_NOR8o = 526,
PPC_NORo = 527,
PPC_OR = 528,
PPC_OR8 = 529,
PPC_OR8o = 530,
PPC_ORC = 531,
PPC_ORC8 = 532,
PPC_ORC8o = 533,
PPC_ORCo = 534,
PPC_ORI = 535,
PPC_ORI8 = 536,
PPC_ORIS = 537,
PPC_ORIS8 = 538,
PPC_ORo = 539,
PPC_POPCNTD = 540,
PPC_POPCNTW = 541,
PPC_PPC32GOT = 542,
PPC_RESTORE_CR = 543,
PPC_RESTORE_VRSAVE = 544,
PPC_RLDCL = 545,
PPC_RLDCLo = 546,
PPC_RLDCR = 547,
PPC_RLDCRo = 548,
PPC_RLDIC = 549,
PPC_RLDICL = 550,
PPC_RLDICL_32_64 = 551,
PPC_RLDICLo = 552,
PPC_RLDICR = 553,
PPC_RLDICRo = 554,
PPC_RLDICo = 555,
PPC_RLDIMI = 556,
PPC_RLDIMIo = 557,
PPC_RLWIMI = 558,
PPC_RLWIMIo = 559,
PPC_RLWINM = 560,
PPC_RLWINM8 = 561,
PPC_RLWINM8o = 562,
PPC_RLWINMo = 563,
PPC_RLWNM = 564,
PPC_RLWNMo = 565,
PPC_ROTRDI = 566,
PPC_ROTRDIo = 567,
PPC_ROTRWI = 568,
PPC_ROTRWIo = 569,
PPC_SC = 570,
PPC_SELECT_CC_F4 = 571,
PPC_SELECT_CC_F8 = 572,
PPC_SELECT_CC_I4 = 573,
PPC_SELECT_CC_I8 = 574,
PPC_SELECT_CC_VRRC = 575,
PPC_SLBIA = 576,
PPC_SLBIE = 577,
PPC_SLBMFEE = 578,
PPC_SLBMTE = 579,
PPC_SLD = 580,
PPC_SLDI = 581,
PPC_SLDIo = 582,
PPC_SLDo = 583,
PPC_SLW = 584,
PPC_SLWI = 585,
PPC_SLWIo = 586,
PPC_SLWo = 587,
PPC_SPILL_CR = 588,
PPC_SPILL_VRSAVE = 589,
PPC_SRAD = 590,
PPC_SRADI = 591,
PPC_SRADIo = 592,
PPC_SRADo = 593,
PPC_SRAW = 594,
PPC_SRAWI = 595,
PPC_SRAWIo = 596,
PPC_SRAWo = 597,
PPC_SRD = 598,
PPC_SRDI = 599,
PPC_SRDIo = 600,
PPC_SRDo = 601,
PPC_SRW = 602,
PPC_SRWI = 603,
PPC_SRWIo = 604,
PPC_SRWo = 605,
PPC_STB = 606,
PPC_STB8 = 607,
PPC_STBU = 608,
PPC_STBU8 = 609,
PPC_STBUX = 610,
PPC_STBUX8 = 611,
PPC_STBX = 612,
PPC_STBX8 = 613,
PPC_STD = 614,
PPC_STDBRX = 615,
PPC_STDCX = 616,
PPC_STDU = 617,
PPC_STDUX = 618,
PPC_STDX = 619,
PPC_STFD = 620,
PPC_STFDU = 621,
PPC_STFDUX = 622,
PPC_STFDX = 623,
PPC_STFIWX = 624,
PPC_STFS = 625,
PPC_STFSU = 626,
PPC_STFSUX = 627,
PPC_STFSX = 628,
PPC_STH = 629,
PPC_STH8 = 630,
PPC_STHBRX = 631,
PPC_STHU = 632,
PPC_STHU8 = 633,
PPC_STHUX = 634,
PPC_STHUX8 = 635,
PPC_STHX = 636,
PPC_STHX8 = 637,
PPC_STMW = 638,
PPC_STVEBX = 639,
PPC_STVEHX = 640,
PPC_STVEWX = 641,
PPC_STVX = 642,
PPC_STVXL = 643,
PPC_STW = 644,
PPC_STW8 = 645,
PPC_STWBRX = 646,
PPC_STWCX = 647,
PPC_STWU = 648,
PPC_STWU8 = 649,
PPC_STWUX = 650,
PPC_STWUX8 = 651,
PPC_STWX = 652,
PPC_STWX8 = 653,
PPC_SUBF = 654,
PPC_SUBF8 = 655,
PPC_SUBF8o = 656,
PPC_SUBFC = 657,
PPC_SUBFC8 = 658,
PPC_SUBFC8o = 659,
PPC_SUBFCo = 660,
PPC_SUBFE = 661,
PPC_SUBFE8 = 662,
PPC_SUBFE8o = 663,
PPC_SUBFEo = 664,
PPC_SUBFIC = 665,
PPC_SUBFIC8 = 666,
PPC_SUBFME = 667,
PPC_SUBFME8 = 668,
PPC_SUBFME8o = 669,
PPC_SUBFMEo = 670,
PPC_SUBFZE = 671,
PPC_SUBFZE8 = 672,
PPC_SUBFZE8o = 673,
PPC_SUBFZEo = 674,
PPC_SUBFo = 675,
PPC_SUBI = 676,
PPC_SUBIC = 677,
PPC_SUBICo = 678,
PPC_SUBIS = 679,
PPC_SYNC = 680,
PPC_TAILB = 681,
PPC_TAILB8 = 682,
PPC_TAILBA = 683,
PPC_TAILBA8 = 684,
PPC_TAILBCTR = 685,
PPC_TAILBCTR8 = 686,
PPC_TCRETURNai = 687,
PPC_TCRETURNai8 = 688,
PPC_TCRETURNdi = 689,
PPC_TCRETURNdi8 = 690,
PPC_TCRETURNri = 691,
PPC_TCRETURNri8 = 692,
PPC_TD = 693,
PPC_TDI = 694,
PPC_TLBIE = 695,
PPC_TLBIEL = 696,
PPC_TLBSYNC = 697,
PPC_TRAP = 698,
PPC_TW = 699,
PPC_TWI = 700,
PPC_UPDATE_VRSAVE = 701,
PPC_VADDCUW = 702,
PPC_VADDFP = 703,
PPC_VADDSBS = 704,
PPC_VADDSHS = 705,
PPC_VADDSWS = 706,
PPC_VADDUBM = 707,
PPC_VADDUBS = 708,
PPC_VADDUHM = 709,
PPC_VADDUHS = 710,
PPC_VADDUWM = 711,
PPC_VADDUWS = 712,
PPC_VAND = 713,
PPC_VANDC = 714,
PPC_VAVGSB = 715,
PPC_VAVGSH = 716,
PPC_VAVGSW = 717,
PPC_VAVGUB = 718,
PPC_VAVGUH = 719,
PPC_VAVGUW = 720,
PPC_VCFSX = 721,
PPC_VCFSX_0 = 722,
PPC_VCFUX = 723,
PPC_VCFUX_0 = 724,
PPC_VCMPBFP = 725,
PPC_VCMPBFPo = 726,
PPC_VCMPEQFP = 727,
PPC_VCMPEQFPo = 728,
PPC_VCMPEQUB = 729,
PPC_VCMPEQUBo = 730,
PPC_VCMPEQUH = 731,
PPC_VCMPEQUHo = 732,
PPC_VCMPEQUW = 733,
PPC_VCMPEQUWo = 734,
PPC_VCMPGEFP = 735,
PPC_VCMPGEFPo = 736,
PPC_VCMPGTFP = 737,
PPC_VCMPGTFPo = 738,
PPC_VCMPGTSB = 739,
PPC_VCMPGTSBo = 740,
PPC_VCMPGTSH = 741,
PPC_VCMPGTSHo = 742,
PPC_VCMPGTSW = 743,
PPC_VCMPGTSWo = 744,
PPC_VCMPGTUB = 745,
PPC_VCMPGTUBo = 746,
PPC_VCMPGTUH = 747,
PPC_VCMPGTUHo = 748,
PPC_VCMPGTUW = 749,
PPC_VCMPGTUWo = 750,
PPC_VCTSXS = 751,
PPC_VCTSXS_0 = 752,
PPC_VCTUXS = 753,
PPC_VCTUXS_0 = 754,
PPC_VEXPTEFP = 755,
PPC_VLOGEFP = 756,
PPC_VMADDFP = 757,
PPC_VMAXFP = 758,
PPC_VMAXSB = 759,
PPC_VMAXSH = 760,
PPC_VMAXSW = 761,
PPC_VMAXUB = 762,
PPC_VMAXUH = 763,
PPC_VMAXUW = 764,
PPC_VMHADDSHS = 765,
PPC_VMHRADDSHS = 766,
PPC_VMINFP = 767,
PPC_VMINSB = 768,
PPC_VMINSH = 769,
PPC_VMINSW = 770,
PPC_VMINUB = 771,
PPC_VMINUH = 772,
PPC_VMINUW = 773,
PPC_VMLADDUHM = 774,
PPC_VMRGHB = 775,
PPC_VMRGHH = 776,
PPC_VMRGHW = 777,
PPC_VMRGLB = 778,
PPC_VMRGLH = 779,
PPC_VMRGLW = 780,
PPC_VMSUMMBM = 781,
PPC_VMSUMSHM = 782,
PPC_VMSUMSHS = 783,
PPC_VMSUMUBM = 784,
PPC_VMSUMUHM = 785,
PPC_VMSUMUHS = 786,
PPC_VMULESB = 787,
PPC_VMULESH = 788,
PPC_VMULEUB = 789,
PPC_VMULEUH = 790,
PPC_VMULOSB = 791,
PPC_VMULOSH = 792,
PPC_VMULOUB = 793,
PPC_VMULOUH = 794,
PPC_VNMSUBFP = 795,
PPC_VNOR = 796,
PPC_VOR = 797,
PPC_VPERM = 798,
PPC_VPKPX = 799,
PPC_VPKSHSS = 800,
PPC_VPKSHUS = 801,
PPC_VPKSWSS = 802,
PPC_VPKSWUS = 803,
PPC_VPKUHUM = 804,
PPC_VPKUHUS = 805,
PPC_VPKUWUM = 806,
PPC_VPKUWUS = 807,
PPC_VREFP = 808,
PPC_VRFIM = 809,
PPC_VRFIN = 810,
PPC_VRFIP = 811,
PPC_VRFIZ = 812,
PPC_VRLB = 813,
PPC_VRLH = 814,
PPC_VRLW = 815,
PPC_VRSQRTEFP = 816,
PPC_VSEL = 817,
PPC_VSL = 818,
PPC_VSLB = 819,
PPC_VSLDOI = 820,
PPC_VSLH = 821,
PPC_VSLO = 822,
PPC_VSLW = 823,
PPC_VSPLTB = 824,
PPC_VSPLTH = 825,
PPC_VSPLTISB = 826,
PPC_VSPLTISH = 827,
PPC_VSPLTISW = 828,
PPC_VSPLTW = 829,
PPC_VSR = 830,
PPC_VSRAB = 831,
PPC_VSRAH = 832,
PPC_VSRAW = 833,
PPC_VSRB = 834,
PPC_VSRH = 835,
PPC_VSRO = 836,
PPC_VSRW = 837,
PPC_VSUBCUW = 838,
PPC_VSUBFP = 839,
PPC_VSUBSBS = 840,
PPC_VSUBSHS = 841,
PPC_VSUBSWS = 842,
PPC_VSUBUBM = 843,
PPC_VSUBUBS = 844,
PPC_VSUBUHM = 845,
PPC_VSUBUHS = 846,
PPC_VSUBUWM = 847,
PPC_VSUBUWS = 848,
PPC_VSUM2SWS = 849,
PPC_VSUM4SBS = 850,
PPC_VSUM4SHS = 851,
PPC_VSUM4UBS = 852,
PPC_VSUMSWS = 853,
PPC_VUPKHPX = 854,
PPC_VUPKHSB = 855,
PPC_VUPKHSH = 856,
PPC_VUPKLPX = 857,
PPC_VUPKLSB = 858,
PPC_VUPKLSH = 859,
PPC_VXOR = 860,
PPC_V_SET0 = 861,
PPC_V_SET0B = 862,
PPC_V_SET0H = 863,
PPC_V_SETALLONES = 864,
PPC_V_SETALLONESB = 865,
PPC_V_SETALLONESH = 866,
PPC_WAIT = 867,
PPC_XOR = 868,
PPC_XOR8 = 869,
PPC_XOR8o = 870,
PPC_XORI = 871,
PPC_XORI8 = 872,
PPC_XORIS = 873,
PPC_XORIS8 = 874,
PPC_XORo = 875,
PPC_gBC = 876,
PPC_gBCA = 877,
PPC_gBCCTR = 878,
PPC_gBCCTRL = 879,
PPC_gBCL = 880,
PPC_gBCLA = 881,
PPC_gBCLR = 882,
PPC_gBCLRL = 883,
PPC_INSTRUCTION_LIST_END = 884
PPC_MSYNC = 478,
PPC_MTCRF = 479,
PPC_MTCRF8 = 480,
PPC_MTCTR = 481,
PPC_MTCTR8 = 482,
PPC_MTCTR8loop = 483,
PPC_MTCTRloop = 484,
PPC_MTFSB0 = 485,
PPC_MTFSB1 = 486,
PPC_MTFSF = 487,
PPC_MTLR = 488,
PPC_MTLR8 = 489,
PPC_MTMSR = 490,
PPC_MTMSRD = 491,
PPC_MTOCRF = 492,
PPC_MTOCRF8 = 493,
PPC_MTSPR = 494,
PPC_MTVRSAVE = 495,
PPC_MTVRSAVEv = 496,
PPC_MTVSCR = 497,
PPC_MULHD = 498,
PPC_MULHDU = 499,
PPC_MULHDUo = 500,
PPC_MULHDo = 501,
PPC_MULHW = 502,
PPC_MULHWU = 503,
PPC_MULHWUo = 504,
PPC_MULHWo = 505,
PPC_MULLD = 506,
PPC_MULLDo = 507,
PPC_MULLI = 508,
PPC_MULLI8 = 509,
PPC_MULLW = 510,
PPC_MULLWo = 511,
PPC_MovePCtoLR = 512,
PPC_MovePCtoLR8 = 513,
PPC_NAND = 514,
PPC_NAND8 = 515,
PPC_NAND8o = 516,
PPC_NANDo = 517,
PPC_NEG = 518,
PPC_NEG8 = 519,
PPC_NEG8o = 520,
PPC_NEGo = 521,
PPC_NOP = 522,
PPC_NOP_GT_PWR6 = 523,
PPC_NOP_GT_PWR7 = 524,
PPC_NOR = 525,
PPC_NOR8 = 526,
PPC_NOR8o = 527,
PPC_NORo = 528,
PPC_OR = 529,
PPC_OR8 = 530,
PPC_OR8o = 531,
PPC_ORC = 532,
PPC_ORC8 = 533,
PPC_ORC8o = 534,
PPC_ORCo = 535,
PPC_ORI = 536,
PPC_ORI8 = 537,
PPC_ORIS = 538,
PPC_ORIS8 = 539,
PPC_ORo = 540,
PPC_POPCNTD = 541,
PPC_POPCNTW = 542,
PPC_PPC32GOT = 543,
PPC_RESTORE_CR = 544,
PPC_RESTORE_VRSAVE = 545,
PPC_RLDCL = 546,
PPC_RLDCLo = 547,
PPC_RLDCR = 548,
PPC_RLDCRo = 549,
PPC_RLDIC = 550,
PPC_RLDICL = 551,
PPC_RLDICL_32_64 = 552,
PPC_RLDICLo = 553,
PPC_RLDICR = 554,
PPC_RLDICRo = 555,
PPC_RLDICo = 556,
PPC_RLDIMI = 557,
PPC_RLDIMIo = 558,
PPC_RLWIMI = 559,
PPC_RLWIMIo = 560,
PPC_RLWINM = 561,
PPC_RLWINM8 = 562,
PPC_RLWINM8o = 563,
PPC_RLWINMo = 564,
PPC_RLWNM = 565,
PPC_RLWNMo = 566,
PPC_ROTRDI = 567,
PPC_ROTRDIo = 568,
PPC_ROTRWI = 569,
PPC_ROTRWIo = 570,
PPC_SC = 571,
PPC_SELECT_CC_F4 = 572,
PPC_SELECT_CC_F8 = 573,
PPC_SELECT_CC_I4 = 574,
PPC_SELECT_CC_I8 = 575,
PPC_SELECT_CC_VRRC = 576,
PPC_SLBIA = 577,
PPC_SLBIE = 578,
PPC_SLBMFEE = 579,
PPC_SLBMTE = 580,
PPC_SLD = 581,
PPC_SLDI = 582,
PPC_SLDIo = 583,
PPC_SLDo = 584,
PPC_SLW = 585,
PPC_SLWI = 586,
PPC_SLWIo = 587,
PPC_SLWo = 588,
PPC_SPILL_CR = 589,
PPC_SPILL_VRSAVE = 590,
PPC_SRAD = 591,
PPC_SRADI = 592,
PPC_SRADIo = 593,
PPC_SRADo = 594,
PPC_SRAW = 595,
PPC_SRAWI = 596,
PPC_SRAWIo = 597,
PPC_SRAWo = 598,
PPC_SRD = 599,
PPC_SRDI = 600,
PPC_SRDIo = 601,
PPC_SRDo = 602,
PPC_SRW = 603,
PPC_SRWI = 604,
PPC_SRWIo = 605,
PPC_SRWo = 606,
PPC_STB = 607,
PPC_STB8 = 608,
PPC_STBU = 609,
PPC_STBU8 = 610,
PPC_STBUX = 611,
PPC_STBUX8 = 612,
PPC_STBX = 613,
PPC_STBX8 = 614,
PPC_STD = 615,
PPC_STDBRX = 616,
PPC_STDCX = 617,
PPC_STDU = 618,
PPC_STDUX = 619,
PPC_STDX = 620,
PPC_STFD = 621,
PPC_STFDU = 622,
PPC_STFDUX = 623,
PPC_STFDX = 624,
PPC_STFIWX = 625,
PPC_STFS = 626,
PPC_STFSU = 627,
PPC_STFSUX = 628,
PPC_STFSX = 629,
PPC_STH = 630,
PPC_STH8 = 631,
PPC_STHBRX = 632,
PPC_STHU = 633,
PPC_STHU8 = 634,
PPC_STHUX = 635,
PPC_STHUX8 = 636,
PPC_STHX = 637,
PPC_STHX8 = 638,
PPC_STMW = 639,
PPC_STVEBX = 640,
PPC_STVEHX = 641,
PPC_STVEWX = 642,
PPC_STVX = 643,
PPC_STVXL = 644,
PPC_STW = 645,
PPC_STW8 = 646,
PPC_STWBRX = 647,
PPC_STWCX = 648,
PPC_STWU = 649,
PPC_STWU8 = 650,
PPC_STWUX = 651,
PPC_STWUX8 = 652,
PPC_STWX = 653,
PPC_STWX8 = 654,
PPC_SUBF = 655,
PPC_SUBF8 = 656,
PPC_SUBF8o = 657,
PPC_SUBFC = 658,
PPC_SUBFC8 = 659,
PPC_SUBFC8o = 660,
PPC_SUBFCo = 661,
PPC_SUBFE = 662,
PPC_SUBFE8 = 663,
PPC_SUBFE8o = 664,
PPC_SUBFEo = 665,
PPC_SUBFIC = 666,
PPC_SUBFIC8 = 667,
PPC_SUBFME = 668,
PPC_SUBFME8 = 669,
PPC_SUBFME8o = 670,
PPC_SUBFMEo = 671,
PPC_SUBFZE = 672,
PPC_SUBFZE8 = 673,
PPC_SUBFZE8o = 674,
PPC_SUBFZEo = 675,
PPC_SUBFo = 676,
PPC_SUBI = 677,
PPC_SUBIC = 678,
PPC_SUBICo = 679,
PPC_SUBIS = 680,
PPC_SYNC = 681,
PPC_TAILB = 682,
PPC_TAILB8 = 683,
PPC_TAILBA = 684,
PPC_TAILBA8 = 685,
PPC_TAILBCTR = 686,
PPC_TAILBCTR8 = 687,
PPC_TCRETURNai = 688,
PPC_TCRETURNai8 = 689,
PPC_TCRETURNdi = 690,
PPC_TCRETURNdi8 = 691,
PPC_TCRETURNri = 692,
PPC_TCRETURNri8 = 693,
PPC_TD = 694,
PPC_TDI = 695,
PPC_TLBIE = 696,
PPC_TLBIEL = 697,
PPC_TLBSYNC = 698,
PPC_TRAP = 699,
PPC_TW = 700,
PPC_TWI = 701,
PPC_UPDATE_VRSAVE = 702,
PPC_VADDCUW = 703,
PPC_VADDFP = 704,
PPC_VADDSBS = 705,
PPC_VADDSHS = 706,
PPC_VADDSWS = 707,
PPC_VADDUBM = 708,
PPC_VADDUBS = 709,
PPC_VADDUHM = 710,
PPC_VADDUHS = 711,
PPC_VADDUWM = 712,
PPC_VADDUWS = 713,
PPC_VAND = 714,
PPC_VANDC = 715,
PPC_VAVGSB = 716,
PPC_VAVGSH = 717,
PPC_VAVGSW = 718,
PPC_VAVGUB = 719,
PPC_VAVGUH = 720,
PPC_VAVGUW = 721,
PPC_VCFSX = 722,
PPC_VCFSX_0 = 723,
PPC_VCFUX = 724,
PPC_VCFUX_0 = 725,
PPC_VCMPBFP = 726,
PPC_VCMPBFPo = 727,
PPC_VCMPEQFP = 728,
PPC_VCMPEQFPo = 729,
PPC_VCMPEQUB = 730,
PPC_VCMPEQUBo = 731,
PPC_VCMPEQUH = 732,
PPC_VCMPEQUHo = 733,
PPC_VCMPEQUW = 734,
PPC_VCMPEQUWo = 735,
PPC_VCMPGEFP = 736,
PPC_VCMPGEFPo = 737,
PPC_VCMPGTFP = 738,
PPC_VCMPGTFPo = 739,
PPC_VCMPGTSB = 740,
PPC_VCMPGTSBo = 741,
PPC_VCMPGTSH = 742,
PPC_VCMPGTSHo = 743,
PPC_VCMPGTSW = 744,
PPC_VCMPGTSWo = 745,
PPC_VCMPGTUB = 746,
PPC_VCMPGTUBo = 747,
PPC_VCMPGTUH = 748,
PPC_VCMPGTUHo = 749,
PPC_VCMPGTUW = 750,
PPC_VCMPGTUWo = 751,
PPC_VCTSXS = 752,
PPC_VCTSXS_0 = 753,
PPC_VCTUXS = 754,
PPC_VCTUXS_0 = 755,
PPC_VEXPTEFP = 756,
PPC_VLOGEFP = 757,
PPC_VMADDFP = 758,
PPC_VMAXFP = 759,
PPC_VMAXSB = 760,
PPC_VMAXSH = 761,
PPC_VMAXSW = 762,
PPC_VMAXUB = 763,
PPC_VMAXUH = 764,
PPC_VMAXUW = 765,
PPC_VMHADDSHS = 766,
PPC_VMHRADDSHS = 767,
PPC_VMINFP = 768,
PPC_VMINSB = 769,
PPC_VMINSH = 770,
PPC_VMINSW = 771,
PPC_VMINUB = 772,
PPC_VMINUH = 773,
PPC_VMINUW = 774,
PPC_VMLADDUHM = 775,
PPC_VMRGHB = 776,
PPC_VMRGHH = 777,
PPC_VMRGHW = 778,
PPC_VMRGLB = 779,
PPC_VMRGLH = 780,
PPC_VMRGLW = 781,
PPC_VMSUMMBM = 782,
PPC_VMSUMSHM = 783,
PPC_VMSUMSHS = 784,
PPC_VMSUMUBM = 785,
PPC_VMSUMUHM = 786,
PPC_VMSUMUHS = 787,
PPC_VMULESB = 788,
PPC_VMULESH = 789,
PPC_VMULEUB = 790,
PPC_VMULEUH = 791,
PPC_VMULOSB = 792,
PPC_VMULOSH = 793,
PPC_VMULOUB = 794,
PPC_VMULOUH = 795,
PPC_VNMSUBFP = 796,
PPC_VNOR = 797,
PPC_VOR = 798,
PPC_VPERM = 799,
PPC_VPKPX = 800,
PPC_VPKSHSS = 801,
PPC_VPKSHUS = 802,
PPC_VPKSWSS = 803,
PPC_VPKSWUS = 804,
PPC_VPKUHUM = 805,
PPC_VPKUHUS = 806,
PPC_VPKUWUM = 807,
PPC_VPKUWUS = 808,
PPC_VREFP = 809,
PPC_VRFIM = 810,
PPC_VRFIN = 811,
PPC_VRFIP = 812,
PPC_VRFIZ = 813,
PPC_VRLB = 814,
PPC_VRLH = 815,
PPC_VRLW = 816,
PPC_VRSQRTEFP = 817,
PPC_VSEL = 818,
PPC_VSL = 819,
PPC_VSLB = 820,
PPC_VSLDOI = 821,
PPC_VSLH = 822,
PPC_VSLO = 823,
PPC_VSLW = 824,
PPC_VSPLTB = 825,
PPC_VSPLTH = 826,
PPC_VSPLTISB = 827,
PPC_VSPLTISH = 828,
PPC_VSPLTISW = 829,
PPC_VSPLTW = 830,
PPC_VSR = 831,
PPC_VSRAB = 832,
PPC_VSRAH = 833,
PPC_VSRAW = 834,
PPC_VSRB = 835,
PPC_VSRH = 836,
PPC_VSRO = 837,
PPC_VSRW = 838,
PPC_VSUBCUW = 839,
PPC_VSUBFP = 840,
PPC_VSUBSBS = 841,
PPC_VSUBSHS = 842,
PPC_VSUBSWS = 843,
PPC_VSUBUBM = 844,
PPC_VSUBUBS = 845,
PPC_VSUBUHM = 846,
PPC_VSUBUHS = 847,
PPC_VSUBUWM = 848,
PPC_VSUBUWS = 849,
PPC_VSUM2SWS = 850,
PPC_VSUM4SBS = 851,
PPC_VSUM4SHS = 852,
PPC_VSUM4UBS = 853,
PPC_VSUMSWS = 854,
PPC_VUPKHPX = 855,
PPC_VUPKHSB = 856,
PPC_VUPKHSH = 857,
PPC_VUPKLPX = 858,
PPC_VUPKLSB = 859,
PPC_VUPKLSH = 860,
PPC_VXOR = 861,
PPC_V_SET0 = 862,
PPC_V_SET0B = 863,
PPC_V_SET0H = 864,
PPC_V_SETALLONES = 865,
PPC_V_SETALLONESB = 866,
PPC_V_SETALLONESH = 867,
PPC_WAIT = 868,
PPC_XOR = 869,
PPC_XOR8 = 870,
PPC_XOR8o = 871,
PPC_XORI = 872,
PPC_XORI8 = 873,
PPC_XORIS = 874,
PPC_XORIS8 = 875,
PPC_XORo = 876,
PPC_gBC = 877,
PPC_gBCA = 878,
PPC_gBCCTR = 879,
PPC_gBCCTRL = 880,
PPC_gBCL = 881,
PPC_gBCLA = 882,
PPC_gBCLR = 883,
PPC_gBCLRL = 884,
PPC_INSTRUCTION_LIST_END = 885
};
#endif // GET_INSTRINFO_ENUM

@ -12,6 +12,7 @@
#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
enum {
PPC_NoRegister,
PPC_BP = 1,

@ -71,9 +71,9 @@ void PPC_printInst(MCInst *MI, SStream *O, void *Info)
{
// Check for slwi/srwi mnemonics.
if (MCInst_getOpcode(MI) == PPC_RLWINM) {
unsigned char SH = MCOperand_getImm(MCInst_getOperand(MI, 2));
unsigned char MB = MCOperand_getImm(MCInst_getOperand(MI, 3));
unsigned char ME = MCOperand_getImm(MCInst_getOperand(MI, 4));
unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
unsigned char MB = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 4));
bool useSubstituteMnemonic = false;
if (SH <= 31 && MB == 0 && ME == (31-SH)) {
@ -110,8 +110,8 @@ void PPC_printInst(MCInst *MI, SStream *O, void *Info)
}
if (MCInst_getOpcode(MI) == PPC_RLDICR) {
unsigned char SH = MCOperand_getImm(MCInst_getOperand(MI, 2));
unsigned char ME = MCOperand_getImm(MCInst_getOperand(MI, 3));
unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
// rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
if (63-SH == ME) {
SStream_concat(O, "sldi\t");
@ -146,7 +146,7 @@ void PPC_printInst(MCInst *MI, SStream *O, void *Info)
static void printPredicateOperand(MCInst *MI, unsigned OpNo,
SStream *O, const char *Modifier)
{
unsigned Code = MCOperand_getImm(MCInst_getOperand(MI, OpNo));
unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
MI->flat_insn.ppc.bc = (ppc_bc)Code;
@ -238,7 +238,7 @@ static void printPredicateOperand(MCInst *MI, unsigned OpNo,
static void printS5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
int Value = MCOperand_getImm(MCInst_getOperand(MI, OpNo));
int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
Value = SignExtend32(Value, 5);
if (Value >= 0) {
@ -262,7 +262,7 @@ static void printS5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
static void printU5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
unsigned int Value = MCOperand_getImm(MCInst_getOperand(MI, OpNo));
unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
//assert(Value <= 31 && "Invalid u5imm argument!");
if (Value > HEX_THRESHOLD)
SStream_concat(O, "0x%x", Value);
@ -278,7 +278,7 @@ static void printU5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
static void printU6ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
unsigned int Value = MCOperand_getImm(MCInst_getOperand(MI, OpNo));
unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
//assert(Value <= 63 && "Invalid u6imm argument!");
if (Value > HEX_THRESHOLD)
SStream_concat(O, "0x%x", Value);
@ -371,7 +371,10 @@ static void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
static void printBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo)))
return printOperand(MI, OpNo, O);
{
printOperand(MI, OpNo, O);
return;
}
// Branches can take an immediate operand. This is used by the branch
// selection pass to print .+8, an eight byte displacement from the PC.
@ -382,7 +385,10 @@ static void printBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo)))
return printOperand(MI, OpNo, O);
{
printOperand(MI, OpNo, O);
return;
}
int tmp = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4;
if (tmp >= 0) {
@ -512,7 +518,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
}
if (MCOperand_isImm(Op)) {
int32_t imm = MCOperand_getImm(Op);
int32_t imm = (int32_t)MCOperand_getImm(Op);
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", imm);

File diff suppressed because it is too large Load Diff

@ -13,15 +13,8 @@ const char *PPC_reg_name(csh handle, unsigned int reg);
// given internal insn id, return public instruction info
void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
// given public insn id, return internal insn id
unsigned int PPC_get_insn_id2(unsigned int id);
// given public insn id, return internal insn id
const char *PPC_insn_name(csh handle, unsigned int id);
// map instruction name to instruction ID
ppc_reg PPC_map_insn(const char *name);
// map internal raw register to 'public' register
ppc_reg PPC_map_register(unsigned int r);

@ -11,12 +11,14 @@ void enable_powerpc() {};
static cs_err init(cs_struct *ud)
{
MCRegisterInfo *mri;
// verify if requested mode is valid
if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 |
CS_MODE_BIG_ENDIAN))
return CS_ERR_MODE;
MCRegisterInfo *mri = cs_mem_malloc(sizeof(*mri));
mri = cs_mem_malloc(sizeof(*mri));
PPC_init(mri);
ud->printer = PPC_printInst;

@ -33,6 +33,7 @@
const char *X86ATT_getRegisterName(unsigned RegNo);
static void printMemReference(MCInst *MI, unsigned Op, SStream *O);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O)
{
@ -116,12 +117,88 @@ static void printf512mem(MCInst *MI, unsigned OpNo, SStream *O)
printMemReference(MI, OpNo, O);
}
static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *SegReg;
SegReg = MCInst_getOperand(MI, Op+1);
SStream_concat(O, "%s", markup("<mem:"));
// If this has a segment register, print it.
if (MCOperand_getReg(SegReg)) {
printOperand(MI, Op+1, O);
SStream_concat(O, ":");
}
SStream_concat(O, "(");
printOperand(MI, Op, O);
SStream_concat(O, ")%s", markup(">"));
}
static void printDstIdx(MCInst *MI, unsigned Op, SStream *O)
{
SStream_concat(O, "%s%s", markup("<mem:"), "%es:(");
printOperand(MI, Op, O);
SStream_concat(O, ")%s", markup(">"));
}
static void printSrcIdx8(MCInst *MI, unsigned OpNo, SStream *O)
{
printSrcIdx(MI, OpNo, O);
}
static void printSrcIdx16(MCInst *MI, unsigned OpNo, SStream *O)
{
printSrcIdx(MI, OpNo, O);
}
static void printSrcIdx32(MCInst *MI, unsigned OpNo, SStream *O)
{
printSrcIdx(MI, OpNo, O);
}
static void printSrcIdx64(MCInst *MI, unsigned OpNo, SStream *O)
{
printSrcIdx(MI, OpNo, O);
}
static void printDstIdx8(MCInst *MI, unsigned OpNo, SStream *O)
{
printDstIdx(MI, OpNo, O);
}
static void printDstIdx16(MCInst *MI, unsigned OpNo, SStream *O)
{
printDstIdx(MI, OpNo, O);
}
static void printDstIdx32(MCInst *MI, unsigned OpNo, SStream *O)
{
printDstIdx(MI, OpNo, O);
}
static void printDstIdx64(MCInst *MI, unsigned OpNo, SStream *O)
{
printDstIdx(MI, OpNo, O);
}
static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *DispSpec = MCInst_getOperand(MI, Op);
MCOperand *SegReg = MCInst_getOperand(MI, Op+1);
SStream_concat(O, "%s", markup("<mem:"));
// If this has a segment register, print it.
if (MCOperand_getReg(SegReg)) {
printOperand(MI, Op+1, O);
SStream_concat(O, ":");
}
if (MI->csh->detail) {
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_MEM;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.base = X86_REG_INVALID;
@ -155,34 +232,16 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
static void printMemOffs8(MCInst *MI, unsigned OpNo, SStream *O)
{
// If this has a segment register, print it.
// this is a hack. will fix it later
if (MI->x86_segment) {
SStream_concat(O, "%%%s:", X86_reg_name(1, MI->x86_segment));
}
printMemOffset(MI, OpNo, O);
}
static void printMemOffs16(MCInst *MI, unsigned OpNo, SStream *O)
{
// If this has a segment register, print it.
// this is a hack. will fix it later
if (MI->x86_segment) {
SStream_concat(O, "%%%s:", X86_reg_name(1, MI->x86_segment));
}
printMemOffset(MI, OpNo, O);
}
static void printMemOffs32(MCInst *MI, unsigned OpNo, SStream *O)
{
// If this has a segment register, print it.
// this is a hack. will fix it later
if (MI->x86_segment) {
SStream_concat(O, "%%%s:", X86_reg_name(1, MI->x86_segment));
}
printMemOffset(MI, OpNo, O);
}
@ -221,7 +280,7 @@ static void printAVXCC(MCInst *MI, unsigned Op, SStream *O)
{
int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f;
switch (Imm) {
default: printf("Invalid avxcc argument!\n"); break;
default: break;//printf("Invalid avxcc argument!\n"); break;
case 0: SStream_concat(O, "eq"); break;
case 1: SStream_concat(O, "lt"); break;
case 2: SStream_concat(O, "le"); break;
@ -257,6 +316,18 @@ static void printAVXCC(MCInst *MI, unsigned Op, SStream *O)
}
}
static void printRoundingControl(MCInst *MI, unsigned Op, SStream *O)
{
int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x3;
switch (Imm) {
case 0: SStream_concat(O, "{rn-sae}"); break;
case 1: SStream_concat(O, "{rd-sae}"); break;
case 2: SStream_concat(O, "{ru-sae}"); break;
case 3: SStream_concat(O, "{rz-sae}"); break;
default: break; // never reach
}
}
/// printPCRelImm - This is used to print an immediate value that ends up
/// being encoded as a pc-relative value (e.g. for jumps and calls). These
/// print slightly differently than normal immediates. For example, a $ is not
@ -391,9 +462,9 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
if (MCOperand_getReg(IndexReg)) {
SStream_concat(O, ", ");
_printOperand(MI, Op+2, O);
unsigned ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op+1));
uint64_t ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op+1));
if (MI->csh->detail)
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.scale = ScaleVal;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.scale = (int)ScaleVal;
if (ScaleVal != 1) {
SStream_concat(O, ", %s%u%s", markup("<imm:"), ScaleVal, markup(">"));
}
@ -424,59 +495,34 @@ static void printRegName(SStream *OS, unsigned RegNo)
SStream_concat(OS, "%s%%%s%s", markup("<reg:"), getRegisterName(RegNo), markup(">"));
}
// get the first op from the asm buffer
// NOTE: make sure firstop is big enough to contain the resulted string
static void get_last_op(char *buffer, char *lastop)
{
char *comma = strrchr(buffer, ',');
if (comma) {
// skip a space after the comma
strcpy(lastop, comma + 2);
} else // no op
lastop[0] = '\0';
}
void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info)
{
// FIXME
//const MCInstrDesc *Desc = MII.get(MI->getOpcode());
//uint64_t TSFlags = Desc.TSFlags;
//if (TSFlags & X86II::LOCK)
// OS << "\tlock\n";
char *mnem;
unsigned int i;
x86_reg reg;
// Try to print any aliases first.
if (printAliasInstr(MI, OS)) {
char *mnem = cs_strdup(OS->buffer);
char *tab = strchr(mnem, '\t');
if (tab)
*tab = '\0';
// reflect the new insn name (alias) in the opcode
MCInst_setOpcode(MI, X86_get_insn_id2(X86_map_insn(mnem)));
mnem = printAliasInstr(MI, OS, NULL);
if (mnem)
cs_mem_free(mnem);
} else
printInstruction(MI, OS, NULL);
else
printInstruction(MI, OS, NULL);
if (MI->csh->detail) {
// first op can be embedded in the asm by llvm.
// so we have to handle that case to not miss the first op.
char lastop[32];
get_last_op(OS->buffer, lastop);
char *acc_regs[] = {"al", "ax", "eax", "rax", NULL};
int post;
if (lastop[0] == '%' && ((post = str_in_list(acc_regs, lastop+1)) != -1)) {
// set operand size following register size
MI->flat_insn.x86.op_size = 1 << post;
// this is one of the registers AL, AX, EAX, RAX
// canonicalize the register name first
//int i;
//for (i = 1; lastop[i]; i++)
// lastop[i] = tolower(lastop[i]);
if (MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count - 1].type != X86_OP_REG) {
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_REG;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].reg = x86_map_regname(lastop + 1);
MI->flat_insn.x86.op_count++;
// special instruction needs to supply register op
reg = X86_insn_reg(MCInst_getOpcode(MI));
if (reg) {
// add register operand
for (i = 0;; i++) {
// find the first empty slot to put it there
if (MI->flat_insn.x86.operands[i].type == 0) {
MI->flat_insn.x86.operands[i].type = X86_OP_REG;
MI->flat_insn.x86.operands[i].reg = reg;
MI->flat_insn.x86.op_count++;
break;
}
}
}
}
}

@ -63,11 +63,11 @@ enum {
/// @param reg - The Reg to append.
static void translateRegister(MCInst *mcInst, Reg reg)
{
//#define ENTRY(x) X86_x,
//#define ENTRY(x) X86_x,
#define ENTRY(x) X86_##x,
uint8_t llvmRegnums[] = {
ALL_REGS
0
0
};
#undef ENTRY
@ -75,6 +75,68 @@ static void translateRegister(MCInst *mcInst, Reg reg)
MCInst_addOperand(mcInst, MCOperand_CreateReg(llvmRegnum));
}
static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
0, // SEG_OVERRIDE_NONE
X86_CS,
X86_SS,
X86_DS,
X86_ES,
X86_FS,
X86_GS
};
/// translateSrcIndex - Appends a source index operand to an MCInst.
///
/// @param mcInst - The MCInst to append to.
/// @param insn - The internal instruction.
static bool translateSrcIndex(MCInst *mcInst, InternalInstruction *insn)
{
unsigned baseRegNo;
MCOperand *segmentReg;
MCOperand *baseReg;
if (insn->mode == MODE_64BIT)
baseRegNo = insn->prefixPresent[0x67] ? X86_ESI : X86_RSI;
else if (insn->mode == MODE_32BIT)
baseRegNo = insn->prefixPresent[0x67] ? X86_SI : X86_ESI;
else {
// assert(insn->mode == MODE_16BIT);
baseRegNo = insn->prefixPresent[0x67] ? X86_ESI : X86_SI;
}
baseReg = MCOperand_CreateReg(baseRegNo);
MCInst_addOperand(mcInst, baseReg);
segmentReg = MCOperand_CreateReg(segmentRegnums[insn->segmentOverride]);
MCInst_addOperand(mcInst, segmentReg);
return false;
}
/// translateDstIndex - Appends a destination index operand to an MCInst.
///
/// @param mcInst - The MCInst to append to.
/// @param insn - The internal instruction.
static bool translateDstIndex(MCInst *mcInst, InternalInstruction *insn)
{
unsigned baseRegNo;
MCOperand *baseReg;
if (insn->mode == MODE_64BIT)
baseRegNo = insn->prefixPresent[0x67] ? X86_EDI : X86_RDI;
else if (insn->mode == MODE_32BIT)
baseRegNo = insn->prefixPresent[0x67] ? X86_DI : X86_EDI;
else {
// assert(insn->mode == MODE_16BIT);
baseRegNo = insn->prefixPresent[0x67] ? X86_EDI : X86_DI;
}
baseReg = MCOperand_CreateReg(baseRegNo);
MCInst_addOperand(mcInst, baseReg);
return false;
}
/// translateImmediate - Appends an immediate operand to an MCInst.
///
/// @param mcInst - The MCInst to append to.
@ -84,8 +146,10 @@ static void translateRegister(MCInst *mcInst, Reg reg)
static void translateImmediate(MCInst *mcInst, uint64_t immediate,
const OperandSpecifier *operand, InternalInstruction *insn)
{
OperandType type = (OperandType)operand->type;
OperandType type;
MCOperand *segmentReg;
type = (OperandType)operand->type;
if (type == TYPE_RELv) {
//isBranch = true;
//pcrel = insn->startLocation + insn->immediateOffset + insn->immediateSize;
@ -146,13 +210,13 @@ static void translateImmediate(MCInst *mcInst, uint64_t immediate,
case TYPE_XMM32:
case TYPE_XMM64:
case TYPE_XMM128:
MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_XMM0 + (immediate >> 4)));
MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_XMM0 + ((uint32_t)immediate >> 4)));
return;
case TYPE_XMM256:
MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_YMM0 + (immediate >> 4)));
MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_YMM0 + ((uint32_t)immediate >> 4)));
return;
case TYPE_XMM512:
MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_ZMM0 + (immediate >> 4)));
MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_ZMM0 + ((uint32_t)immediate >> 4)));
return;
case TYPE_REL8:
if(immediate & 0x80)
@ -169,6 +233,12 @@ static void translateImmediate(MCInst *mcInst, uint64_t immediate,
}
MCInst_addOperand(mcInst, MCOperand_CreateImm(immediate));
if (type == TYPE_MOFFS8 || type == TYPE_MOFFS16 ||
type == TYPE_MOFFS32 || type == TYPE_MOFFS64) {
segmentReg = MCOperand_CreateReg(segmentRegnums[insn->segmentOverride]);
MCInst_addOperand(mcInst, segmentReg);
}
}
/// translateRMRegister - Translates a register stored in the R/M field of the
@ -196,7 +266,7 @@ static bool translateRMRegister(MCInst *mcInst, InternalInstruction *insn)
return true;
#define ENTRY(x) \
case EA_REG_##x: \
MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_##x)); break;
MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_##x)); break;
ALL_REGS
#undef ENTRY
default:
@ -234,13 +304,14 @@ static bool translateRMMemory(MCInst *mcInst, InternalInstruction *insn)
MCOperand *indexReg;
MCOperand *displacement;
MCOperand *segmentReg;
bool IndexIs512;
if (insn->eaBase == EA_BASE_sib || insn->eaBase == EA_BASE_sib64) {
if (insn->sibBase != SIB_BASE_NONE) {
switch (insn->sibBase) {
#define ENTRY(x) \
case SIB_BASE_##x: \
baseReg = MCOperand_CreateReg(X86_##x); break;
baseReg = MCOperand_CreateReg(X86_##x); break;
ALL_SIB_BASES
#undef ENTRY
default:
@ -271,13 +342,24 @@ static bool translateRMMemory(MCInst *mcInst, InternalInstruction *insn)
bool IndexIs256 = (Opcode == X86_VGATHERQPDYrm ||
Opcode == X86_VGATHERDPSYrm ||
Opcode == X86_VGATHERQPSYrm ||
Opcode == X86_VGATHERDPDZrm ||
Opcode == X86_VPGATHERDQZrm ||
Opcode == X86_VPGATHERQQYrm ||
Opcode == X86_VPGATHERDDYrm ||
Opcode == X86_VPGATHERQDYrm);
if (IndexIs128 || IndexIs256) {
IndexIs512 = (Opcode == X86_VGATHERQPDZrm ||
Opcode == X86_VGATHERDPSZrm ||
Opcode == X86_VGATHERQPSZrm ||
Opcode == X86_VPGATHERQQZrm ||
Opcode == X86_VPGATHERDDZrm ||
Opcode == X86_VPGATHERQDZrm);
if (IndexIs128 || IndexIs256 || IndexIs512) {
unsigned IndexOffset = insn->sibIndex -
(insn->addressSize == 8 ? SIB_INDEX_RAX:SIB_INDEX_EAX);
SIBIndex IndexBase = IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0;
SIBIndex IndexBase = IndexIs512 ? SIB_INDEX_ZMM0 :
IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0;
insn->sibIndex = (SIBIndex)(IndexBase + (insn->sibIndex == SIB_INDEX_NONE ? 4 : IndexOffset));
}
@ -288,12 +370,12 @@ static bool translateRMMemory(MCInst *mcInst, InternalInstruction *insn)
return true;
#define ENTRY(x) \
case SIB_INDEX_##x: \
indexReg = MCOperand_CreateReg(X86_##x); break;
indexReg = MCOperand_CreateReg(X86_##x); break;
EA_BASES_32BIT
EA_BASES_64BIT
REGS_XMM
REGS_YMM
REGS_ZMM
EA_BASES_64BIT
REGS_XMM
REGS_YMM
REGS_ZMM
#undef ENTRY
}
} else {
@ -343,7 +425,7 @@ static bool translateRMMemory(MCInst *mcInst, InternalInstruction *insn)
// placeholders to keep the compiler happy.
#define ENTRY(x) \
case EA_BASE_##x: \
baseReg = MCOperand_CreateReg(X86_##x); break;
baseReg = MCOperand_CreateReg(X86_##x); break;
ALL_EA_BASES
#undef ENTRY
#define ENTRY(x) case EA_REG_##x:
@ -360,16 +442,6 @@ static bool translateRMMemory(MCInst *mcInst, InternalInstruction *insn)
displacement = MCOperand_CreateImm(insn->displacement);
static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
0, // SEG_OVERRIDE_NONE
X86_CS,
X86_SS,
X86_DS,
X86_ES,
X86_FS,
X86_GS
};
segmentReg = MCOperand_CreateReg(segmentRegnums[insn->segmentOverride]);
MCInst_addOperand(mcInst, baseReg);
@ -408,6 +480,9 @@ static bool translateRM(MCInst *mcInst, const OperandSpecifier *operand,
case TYPE_XMM128:
case TYPE_XMM256:
case TYPE_XMM512:
case TYPE_VK1:
case TYPE_VK8:
case TYPE_VK16:
case TYPE_DEBUGREG:
case TYPE_CONTROLREG:
return translateRMRegister(mcInst, insn);
@ -442,15 +517,25 @@ static bool translateRM(MCInst *mcInst, const OperandSpecifier *operand,
///
/// @param mcInst - The MCInst to append to.
/// @param stackPos - The stack position to translate.
/// @return - 0 on success; nonzero otherwise.
static bool translateFPRegister(MCInst *mcInst, uint8_t stackPos)
static void translateFPRegister(MCInst *mcInst, uint8_t stackPos)
{
if (stackPos >= 8) {
//debug("Invalid FP stack position");
MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_ST0 + stackPos));
}
/// translateMaskRegister - Translates a 3-bit mask register number to
/// LLVM form, and appends it to an MCInst.
///
/// @param mcInst - The MCInst to append to.
/// @param maskRegNum - Number of mask register from 0 to 7.
/// @return - false on success; true otherwise.
static bool translateMaskRegister(MCInst *mcInst, uint8_t maskRegNum)
{
if (maskRegNum >= 8) {
// debug("Invalid mask register number");
return true;
}
MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_ST0 + stackPos));
MCInst_addOperand(mcInst, MCOperand_CreateReg(X86_K0 + maskRegNum));
return false;
}
@ -468,6 +553,8 @@ static bool translateOperand(MCInst *mcInst, const OperandSpecifier *operand, In
case ENCODING_REG:
translateRegister(mcInst, insn->reg);
return false;
case ENCODING_WRITEMASK:
return translateMaskRegister(mcInst, insn->writemask);
case ENCODING_RM:
return translateRM(mcInst, operand, insn);
case ENCODING_CB:
@ -486,17 +573,20 @@ static bool translateOperand(MCInst *mcInst, const OperandSpecifier *operand, In
case ENCODING_Ia:
translateImmediate(mcInst, insn->immediates[insn->numImmediatesTranslated++], operand, insn);
return false;
case ENCODING_SI:
return translateSrcIndex(mcInst, insn);
case ENCODING_DI:
return translateDstIndex(mcInst, insn);
case ENCODING_RB:
case ENCODING_RW:
case ENCODING_RD:
case ENCODING_RO:
translateRegister(mcInst, insn->opcodeRegister);
return false;
case ENCODING_I:
return translateFPRegister(mcInst, insn->opcodeModifier);
case ENCODING_Rv:
translateRegister(mcInst, insn->opcodeRegister);
return false;
case ENCODING_FP:
translateFPRegister(mcInst, insn->modRM & 7);
return false;
case ENCODING_VVVV:
translateRegister(mcInst, insn->vvvv);
return false;
@ -570,8 +660,8 @@ static void update_pub_insn(cs_insn_flat *pub, InternalInstruction *inter)
pub->x86.segment = x86_map_segment(inter->segmentOverride);
if (inter->vexXopType > 0)
memcpy(pub->x86.opcode, inter->vexXopPrefix, sizeof(pub->x86.opcode));
if (inter->vectorExtensionType > 0)
memcpy(pub->x86.opcode, inter->vectorExtensionPrefix, sizeof(pub->x86.opcode));
else {
pub->x86.opcode[0] = inter->opcode;
pub->x86.opcode[1] = inter->twoByteEscape;
@ -624,13 +714,11 @@ bool X86_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *in
MODE_64BIT);
if (ret) {
*size = insn.readerCursor - address;
*size = (uint16_t)(insn.readerCursor - address);
return false;
} else {
*size = insn.length;
*size = (uint16_t)insn.length;
result = (!translateInstruction(instr, &insn)) ? true : false;
// save segment for printing hack
instr->x86_segment = x86_map_segment(insn.segmentOverride);
if (handle->detail)
update_pub_insn(&instr->flat_insn, &insn);
return result;

File diff suppressed because it is too large Load Diff

@ -52,6 +52,21 @@ extern "C" {
#define xFromREX(rex) (((rex) & 0x2) >> 1)
#define bFromREX(rex) ((rex) & 0x1)
#define rFromEVEX2of4(evex) (((~(evex)) & 0x80) >> 7)
#define xFromEVEX2of4(evex) (((~(evex)) & 0x40) >> 6)
#define bFromEVEX2of4(evex) (((~(evex)) & 0x20) >> 5)
#define r2FromEVEX2of4(evex) (((~(evex)) & 0x10) >> 4)
#define mmFromEVEX2of4(evex) ((evex) & 0x3)
#define wFromEVEX3of4(evex) (((evex) & 0x80) >> 7)
#define vvvvFromEVEX3of4(evex) (((~(evex)) & 0x78) >> 3)
#define ppFromEVEX3of4(evex) ((evex) & 0x3)
#define zFromEVEX4of4(evex) (((evex) & 0x80) >> 7)
#define l2FromEVEX4of4(evex) (((evex) & 0x40) >> 6)
#define lFromEVEX4of4(evex) (((evex) & 0x20) >> 5)
#define bFromEVEX4of4(evex) (((evex) & 0x10) >> 4)
#define v2FromEVEX4of4(evex) (((~evex) & 0x8) >> 3)
#define aaaFromEVEX4of4(evex) ((evex) & 0x7)
#define rFromVEX2of3(vex) (((~(vex)) & 0x80) >> 7)
#define xFromVEX2of3(vex) (((~(vex)) & 0x40) >> 6)
#define bFromVEX2of3(vex) (((~(vex)) & 0x20) >> 5)
@ -322,6 +337,16 @@ extern "C" {
ENTRY(ZMM30) \
ENTRY(ZMM31)
#define REGS_MASKS \
ENTRY(K0) \
ENTRY(K1) \
ENTRY(K2) \
ENTRY(K3) \
ENTRY(K4) \
ENTRY(K5) \
ENTRY(K6) \
ENTRY(K7)
#define REGS_SEGMENT \
ENTRY(ES) \
ENTRY(CS) \
@ -369,6 +394,7 @@ extern "C" {
REGS_XMM \
REGS_YMM \
REGS_ZMM \
REGS_MASKS \
REGS_SEGMENT \
REGS_DEBUG \
REGS_CONTROL \
@ -471,7 +497,7 @@ typedef enum {
} XOPMapSelect;
/*
* VEXPrefixCode - Possible values for the VEX.pp field
* VEXPrefixCode - Possible values for the VEX.pp/EVEX.pp field
*/
typedef enum {
@ -482,11 +508,12 @@ typedef enum {
} VEXPrefixCode;
typedef enum {
TYPE_NO_VEX_XOP = 0x0,
TYPE_VEX_2B = 0x1,
TYPE_VEX_3B = 0x2,
TYPE_XOP = 0x3
} VEXXOPType;
TYPE_NO_VEX_XOP = 0x0,
TYPE_VEX_2B = 0x1,
TYPE_VEX_3B = 0x2,
TYPE_EVEX = 0x3,
TYPE_XOP = 0x4
} VectorExtensionType;
typedef uint8_t BOOL;
@ -545,10 +572,10 @@ typedef struct InternalInstruction {
uint8_t prefixPresent[0x100];
/* contains the location (for use with the reader) of the prefix byte */
uint64_t prefixLocations[0x100];
/* The value of the VEX/XOP prefix, if present */
uint8_t vexXopPrefix[3];
/* The length of the VEX prefix (0 if not present) */
VEXXOPType vexXopType;
/* The value of the vector extension prefix(EVEX/VEX/XOP), if present */
uint8_t vectorExtensionPrefix[4];
/* The type of the vector extension prefix */
VectorExtensionType vectorExtensionType;
/* The value of the REX prefix, if present */
uint8_t rexPrefix;
/* The location where a mandatory prefix would have to be (i.e., right before
@ -596,6 +623,9 @@ typedef struct InternalInstruction {
instructions */
Reg vvvv;
/* The writemask for AVX-512 instructions which is contained in EVEX.aaa */
Reg writemask;
/* The ModR/M byte, which contains most register operands and some portion of
all memory operands */
BOOL consumedModRM;
@ -615,8 +645,6 @@ typedef struct InternalInstruction {
uint64_t immediates[2];
/* A register or immediate operand encoded into the opcode */
BOOL consumedOpcodeModifier;
uint8_t opcodeModifier;
Reg opcodeRegister;
/* Portions of the ModR/M byte */

@ -33,8 +33,6 @@
#define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes
#define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes
#define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes
#define THREEBYTEA6_SYM x86DisassemblerThreeByteA6Opcodes
#define THREEBYTEA7_SYM x86DisassemblerThreeByteA7Opcodes
#define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes
#define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes
#define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes
@ -44,16 +42,22 @@
* processed correctly. Most of these indicate the presence of particular
* prefixes, but ATTR_64BIT is simply an attribute of the decoding context.
*/
#define ATTRIBUTE_BITS \
ENUM_ENTRY(ATTR_NONE, 0x00) \
ENUM_ENTRY(ATTR_64BIT, 0x01) \
ENUM_ENTRY(ATTR_XS, 0x02) \
ENUM_ENTRY(ATTR_XD, 0x04) \
ENUM_ENTRY(ATTR_REXW, 0x08) \
ENUM_ENTRY(ATTR_OPSIZE, 0x10) \
ENUM_ENTRY(ATTR_ADSIZE, 0x20) \
ENUM_ENTRY(ATTR_VEX, 0x40) \
ENUM_ENTRY(ATTR_VEXL, 0x80)
#define ATTRIBUTE_BITS \
ENUM_ENTRY(ATTR_NONE, 0x00) \
ENUM_ENTRY(ATTR_64BIT, (0x1 << 0)) \
ENUM_ENTRY(ATTR_XS, (0x1 << 1)) \
ENUM_ENTRY(ATTR_XD, (0x1 << 2)) \
ENUM_ENTRY(ATTR_REXW, (0x1 << 3)) \
ENUM_ENTRY(ATTR_OPSIZE, (0x1 << 4)) \
ENUM_ENTRY(ATTR_ADSIZE, (0x1 << 5)) \
ENUM_ENTRY(ATTR_VEX, (0x1 << 6)) \
ENUM_ENTRY(ATTR_VEXL, (0x1 << 7)) \
ENUM_ENTRY(ATTR_EVEX, (0x1 << 8)) \
ENUM_ENTRY(ATTR_EVEXL, (0x1 << 9)) \
ENUM_ENTRY(ATTR_EVEXL2, (0x1 << 10)) \
ENUM_ENTRY(ATTR_EVEXK, (0x1 << 11)) \
ENUM_ENTRY(ATTR_EVEXKZ, (0x1 << 12)) \
ENUM_ENTRY(ATTR_EVEXB, (0x1 << 13))
#define ENUM_ENTRY(n, v) n = v,
enum attributeBits {
@ -64,7 +68,7 @@ enum attributeBits {
/*
* Combinations of the above attributes that are relevant to instruction
* decode. Although other combinations are possible, they can be reduced to
* decode. Although other combinations are possible, they can be reduced to
* these without affecting the ultimately decoded instruction.
*/
@ -189,38 +193,38 @@ ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W")
ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \
ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \
ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \
ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \
ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \
ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \
ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \
ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \
ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\
ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\
ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \
ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \
ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \
ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \
ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, W and OpSize") \
ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \
ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\
ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\
ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \
ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \
ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and OpSize") \
ENUM_ENTRY(IC_EVEX_KZ_B, 1, "requires EVEX_B and EVEX_KZ prefix") \
ENUM_ENTRY(IC_EVEX_XS_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XS prefix") \
ENUM_ENTRY(IC_EVEX_XD_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XD prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the W prefix") \
ENUM_ENTRY(IC_EVEX_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XS prefix") \
ENUM_ENTRY(IC_EVEX_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XD prefix") \
ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and OpSize") \
ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \
ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \
ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \
ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \
ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \
ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \
ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \
ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\
ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\
ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \
ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \
ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \
ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \
ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L, W and OpSize") \
ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \
ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\
ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\
ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \
ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \
ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \
ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L2, W and OpSize") \
ENUM_ENTRY(IC_EVEX_KZ_B, 1, "requires EVEX_B and EVEX_KZ prefix") \
ENUM_ENTRY(IC_EVEX_XS_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XS prefix") \
ENUM_ENTRY(IC_EVEX_XD_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XD prefix") \
ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the OpSize prefix") \
ENUM_ENTRY(IC_EVEX_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the W prefix") \
ENUM_ENTRY(IC_EVEX_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XS prefix") \
ENUM_ENTRY(IC_EVEX_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XD prefix") \
ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and OpSize") \
ENUM_ENTRY(IC_EVEX_L_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L prefix") \
ENUM_ENTRY(IC_EVEX_L_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XS prefix")\
ENUM_ENTRY(IC_EVEX_L_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XD prefix")\
@ -278,11 +282,9 @@ typedef enum {
TWOBYTE = 1,
THREEBYTE_38 = 2,
THREEBYTE_3A = 3,
THREEBYTE_A6 = 4,
THREEBYTE_A7 = 5,
XOP8_MAP = 6,
XOP9_MAP = 7,
XOPA_MAP = 8
XOP8_MAP = 4,
XOP9_MAP = 5,
XOPA_MAP = 6
} OpcodeType;
/*
@ -350,23 +352,12 @@ struct OpcodeDecision {
struct ModRMDecision modRMDecisions[256];
};
/*
* ContextDecision - Specifies which opcode->instruction tables to look at given
* a particular context (set of attributes). Since there are many possible
* contexts, the decoder first uses CONTEXTS_SYM to determine which context
* applies given a specific set of attributes. Hence there are only IC_max
* entries in this table, rather than 2^(ATTR_max).
*/
struct ContextDecision {
struct OpcodeDecision opcodeDecisions[IC_max];
};
/*
* Physical encodings of instruction operands.
*/
#define ENCODINGS \
ENUM_ENTRY(ENCODING_NONE, "") \
#define ENCODINGS \
ENUM_ENTRY(ENCODING_NONE, "") \
ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \
ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \
ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \
@ -382,19 +373,20 @@ ENUM_ENTRY(ENCODING_IW, "2-byte") \
ENUM_ENTRY(ENCODING_ID, "4-byte") \
ENUM_ENTRY(ENCODING_IO, "8-byte") \
ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8L..R15L) Register code added to " \
"the opcode byte") \
"the opcode byte") \
ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \
ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \
ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \
ENUM_ENTRY(ENCODING_I, "Position on floating-point stack added to the " \
"opcode byte") \
\
ENUM_ENTRY(ENCODING_FP, "Position on floating-point stack in ModR/M " \
"byte.") \
ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \
ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \
ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \
"opcode byte") \
"opcode byte") \
ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \
"in type")
"in type") \
ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix") \
ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes")
#define ENUM_ENTRY(n, d) n,
typedef enum {
@ -445,8 +437,16 @@ ENUM_ENTRY(TYPE_M16_32, "2+4-byte two-part memory operand (LIDT, LGDT)") \
ENUM_ENTRY(TYPE_M16_16, "2+2-byte (BOUND)") \
ENUM_ENTRY(TYPE_M32_32, "4+4-byte (BOUND)") \
ENUM_ENTRY(TYPE_M16_64, "2+8-byte (LIDT, LGDT)") \
ENUM_ENTRY(TYPE_SRCIDX8, "1-byte memory at source index") \
ENUM_ENTRY(TYPE_SRCIDX16, "2-byte memory at source index") \
ENUM_ENTRY(TYPE_SRCIDX32, "4-byte memory at source index") \
ENUM_ENTRY(TYPE_SRCIDX64, "8-byte memory at source index") \
ENUM_ENTRY(TYPE_DSTIDX8, "1-byte memory at destination index") \
ENUM_ENTRY(TYPE_DSTIDX16, "2-byte memory at destination index") \
ENUM_ENTRY(TYPE_DSTIDX32, "4-byte memory at destination index") \
ENUM_ENTRY(TYPE_DSTIDX64, "8-byte memory at destination index") \
ENUM_ENTRY(TYPE_MOFFS8, "1-byte memory offset (relative to segment " \
"base)") \
"base)") \
ENUM_ENTRY(TYPE_MOFFS16, "2-byte") \
ENUM_ENTRY(TYPE_MOFFS32, "4-byte") \
ENUM_ENTRY(TYPE_MOFFS64, "8-byte") \
@ -469,6 +469,7 @@ ENUM_ENTRY(TYPE_XMM64, "8-byte") \
ENUM_ENTRY(TYPE_XMM128, "16-byte") \
ENUM_ENTRY(TYPE_XMM256, "32-byte") \
ENUM_ENTRY(TYPE_XMM512, "64-byte") \
ENUM_ENTRY(TYPE_VK1, "1-bit") \
ENUM_ENTRY(TYPE_VK8, "8-bit") \
ENUM_ENTRY(TYPE_VK16, "16-bit") \
ENUM_ENTRY(TYPE_XMM0, "Implicit use of XMM0") \
@ -509,9 +510,7 @@ typedef struct OperandSpecifier {
*/
#define MODIFIER_TYPES \
ENUM_ENTRY(MODIFIER_NONE) \
ENUM_ENTRY(MODIFIER_OPCODE) \
ENUM_ENTRY(MODIFIER_MODRM)
ENUM_ENTRY(MODIFIER_NONE)
#define ENUM_ENTRY(n) n,
typedef enum {
@ -527,9 +526,6 @@ typedef enum {
* its operands.
*/
struct InstructionSpecifier {
uint8_t modifierType;
uint8_t modifierBase;
/* The macro below must be defined wherever this file is included. */
INSTRUCTION_SPECIFIER_FIELDS
};

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

@ -6,9 +6,10 @@
|* *|
\*===----------------------------------------------------------------------===*/
/* Capstone Disassembler Engine */
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
@ -249,76 +250,80 @@ enum {
X86_NUM_TARGET_REGS // 233
};
// Register classes
enum {
X86_GR8RegClassID = 0,
X86_GR8_NOREXRegClassID = 1,
X86_VK8RegClassID = 2,
X86_VK8WMRegClassID = 3,
X86_VK1RegClassID = 0,
X86_VK1WMRegClassID = 1,
X86_GR8RegClassID = 2,
X86_GR8_NOREXRegClassID = 3,
X86_GR8_ABCD_HRegClassID = 4,
X86_GR8_ABCD_LRegClassID = 5,
X86_GR16RegClassID = 6,
X86_GR16_NOREXRegClassID = 7,
X86_VK16RegClassID = 8,
X86_VK16WMRegClassID = 9,
X86_SEGMENT_REGRegClassID = 10,
X86_GR16_ABCDRegClassID = 11,
X86_FPCCRRegClassID = 12,
X86_FR32XRegClassID = 13,
X86_FR32RegClassID = 14,
X86_GR32RegClassID = 15,
X86_GR32_NOAXRegClassID = 16,
X86_GR32_NOSPRegClassID = 17,
X86_GR32_NOAX_and_GR32_NOSPRegClassID = 18,
X86_DEBUG_REGRegClassID = 19,
X86_GR32_NOREXRegClassID = 20,
X86_GR32_NOAX_and_GR32_NOREXRegClassID = 21,
X86_GR32_NOREX_NOSPRegClassID = 22,
X86_RFP32RegClassID = 23,
X86_GR32_NOAX_and_GR32_NOREX_NOSPRegClassID = 24,
X86_GR32_ABCDRegClassID = 25,
X86_GR32_ABCD_and_GR32_NOAXRegClassID = 26,
X86_GR32_TCRegClassID = 27,
X86_GR32_ADRegClassID = 28,
X86_GR32_NOAX_and_GR32_TCRegClassID = 29,
X86_CCRRegClassID = 30,
X86_GR32_AD_and_GR32_NOAXRegClassID = 31,
X86_RFP64RegClassID = 32,
X86_FR64XRegClassID = 33,
X86_GR64RegClassID = 34,
X86_CONTROL_REGRegClassID = 35,
X86_FR64RegClassID = 36,
X86_GR64_with_sub_8bitRegClassID = 37,
X86_GR64_NOSPRegClassID = 38,
X86_GR64_with_sub_32bit_in_GR32_NOAXRegClassID = 39,
X86_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSPRegClassID = 40,
X86_GR64_NOREXRegClassID = 41,
X86_GR64_TCRegClassID = 42,
X86_GR64_NOSP_and_GR64_TCRegClassID = 43,
X86_GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 44,
X86_VR64RegClassID = 45,
X86_GR64_NOREX_NOSPRegClassID = 46,
X86_GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAXRegClassID = 47,
X86_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREXRegClassID = 48,
X86_GR64_NOREX_and_GR64_TCRegClassID = 49,
X86_GR64_TCW64RegClassID = 50,
X86_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSPRegClassID = 51,
X86_GR64_NOREX_NOSP_and_GR64_TCRegClassID = 52,
X86_GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAXRegClassID = 53,
X86_GR64_ABCDRegClassID = 54,
X86_GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREXRegClassID = 55,
X86_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAXRegClassID = 56,
X86_GR64_with_sub_32bit_in_GR32_TCRegClassID = 57,
X86_GR64_with_sub_32bit_in_GR32_ADRegClassID = 58,
X86_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TCRegClassID = 59,
X86_GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAXRegClassID = 60,
X86_RSTRegClassID = 61,
X86_RFP80RegClassID = 62,
X86_VR128XRegClassID = 63,
X86_VR128RegClassID = 64,
X86_VR256XRegClassID = 65,
X86_VR256RegClassID = 66,
X86_VR512RegClassID = 67,
X86_VR512_with_sub_xmm_in_FR32RegClassID = 68
X86_VK8RegClassID = 6,
X86_VK8WMRegClassID = 7,
X86_GR16RegClassID = 8,
X86_GR16_NOREXRegClassID = 9,
X86_VK16RegClassID = 10,
X86_VK16WMRegClassID = 11,
X86_SEGMENT_REGRegClassID = 12,
X86_GR16_ABCDRegClassID = 13,
X86_FPCCRRegClassID = 14,
X86_FR32XRegClassID = 15,
X86_FR32RegClassID = 16,
X86_GR32RegClassID = 17,
X86_GR32_NOAXRegClassID = 18,
X86_GR32_NOSPRegClassID = 19,
X86_GR32_NOAX_and_GR32_NOSPRegClassID = 20,
X86_DEBUG_REGRegClassID = 21,
X86_GR32_NOREXRegClassID = 22,
X86_GR32_NOAX_and_GR32_NOREXRegClassID = 23,
X86_GR32_NOREX_NOSPRegClassID = 24,
X86_RFP32RegClassID = 25,
X86_GR32_NOAX_and_GR32_NOREX_NOSPRegClassID = 26,
X86_GR32_ABCDRegClassID = 27,
X86_GR32_ABCD_and_GR32_NOAXRegClassID = 28,
X86_GR32_TCRegClassID = 29,
X86_GR32_ADRegClassID = 30,
X86_GR32_NOAX_and_GR32_TCRegClassID = 31,
X86_CCRRegClassID = 32,
X86_GR32_AD_and_GR32_NOAXRegClassID = 33,
X86_RFP64RegClassID = 34,
X86_FR64XRegClassID = 35,
X86_GR64RegClassID = 36,
X86_CONTROL_REGRegClassID = 37,
X86_FR64RegClassID = 38,
X86_GR64_with_sub_8bitRegClassID = 39,
X86_GR64_NOSPRegClassID = 40,
X86_GR64_with_sub_32bit_in_GR32_NOAXRegClassID = 41,
X86_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSPRegClassID = 42,
X86_GR64_NOREXRegClassID = 43,
X86_GR64_TCRegClassID = 44,
X86_GR64_NOSP_and_GR64_TCRegClassID = 45,
X86_GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 46,
X86_VR64RegClassID = 47,
X86_GR64_NOREX_NOSPRegClassID = 48,
X86_GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAXRegClassID = 49,
X86_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREXRegClassID = 50,
X86_GR64_NOREX_and_GR64_TCRegClassID = 51,
X86_GR64_TCW64RegClassID = 52,
X86_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSPRegClassID = 53,
X86_GR64_NOREX_NOSP_and_GR64_TCRegClassID = 54,
X86_GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAXRegClassID = 55,
X86_GR64_ABCDRegClassID = 56,
X86_GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREXRegClassID = 57,
X86_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAXRegClassID = 58,
X86_GR64_with_sub_32bit_in_GR32_TCRegClassID = 59,
X86_GR64_with_sub_32bit_in_GR32_ADRegClassID = 60,
X86_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TCRegClassID = 61,
X86_GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAXRegClassID = 62,
X86_RSTRegClassID = 63,
X86_RFP80RegClassID = 64,
X86_VR128XRegClassID = 65,
X86_VR128RegClassID = 66,
X86_VR256XRegClassID = 67,
X86_VR256RegClassID = 68,
X86_VR512RegClassID = 69,
X86_VR512_with_sub_xmm_in_FR32RegClassID = 70
};
#endif // GET_REGINFO_ENUM

@ -29,6 +29,7 @@
#include "X86Mapping.h"
static void printMemReference(MCInst *MI, unsigned Op, SStream *O);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O)
{
@ -114,9 +115,83 @@ static void printf512mem(MCInst *MI, unsigned OpNo, SStream *O)
printMemReference(MI, OpNo, O);
}
static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *SegReg;
SegReg = MCInst_getOperand(MI, Op+1);
// If this has a segment register, print it.
if (MCOperand_getReg(SegReg)) {
printOperand(MI, Op+1, O);
SStream_concat(O, ":");
}
SStream_concat(O, "[");
printOperand(MI, Op, O);
SStream_concat(O, "]");
}
static void printDstIdx(MCInst *MI, unsigned Op, SStream *O)
{
// DI accesses are always ES-based.
SStream_concat(O, "es:[");
printOperand(MI, Op, O);
SStream_concat(O, "]");
}
void printSrcIdx8(MCInst *MI, unsigned OpNo, SStream *O)
{
SStream_concat(O, "byte ptr ");
printSrcIdx(MI, OpNo, O);
}
void printSrcIdx16(MCInst *MI, unsigned OpNo, SStream *O)
{
SStream_concat(O, "word ptr ");
printSrcIdx(MI, OpNo, O);
}
void printSrcIdx32(MCInst *MI, unsigned OpNo, SStream *O)
{
SStream_concat(O, "dword ptr ");
printSrcIdx(MI, OpNo, O);
}
void printSrcIdx64(MCInst *MI, unsigned OpNo, SStream *O)
{
SStream_concat(O, "qword ptr ");
printSrcIdx(MI, OpNo, O);
}
void printDstIdx8(MCInst *MI, unsigned OpNo, SStream *O)
{
SStream_concat(O, "byte ptr ");
printDstIdx(MI, OpNo, O);
}
void printDstIdx16(MCInst *MI, unsigned OpNo, SStream *O)
{
SStream_concat(O, "word ptr ");
printDstIdx(MI, OpNo, O);
}
void printDstIdx32(MCInst *MI, unsigned OpNo, SStream *O)
{
SStream_concat(O, "dword ptr ");
printDstIdx(MI, OpNo, O);
}
void printDstIdx64(MCInst *MI, unsigned OpNo, SStream *O)
{
SStream_concat(O, "qword ptr ");
printDstIdx(MI, OpNo, O);
}
static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *DispSpec = MCInst_getOperand(MI, Op);
MCOperand *SegReg = MCInst_getOperand(MI, Op+1);
if (MI->csh->detail) {
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_MEM;
@ -126,6 +201,12 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = 0;
}
// If this has a segment register, print it.
if (MCOperand_getReg(SegReg)) {
printOperand(MI, Op+1, O);
SStream_concat(O, ":");
}
SStream_concat(O, "[");
if (MCOperand_isImm(DispSpec)) {
@ -155,12 +236,6 @@ static void printMemOffs8(MCInst *MI, unsigned OpNo, SStream *O)
{
SStream_concat(O, "byte ptr ");
// If this has a segment register, print it.
// this is a hack. will fix it later
if (MI->x86_segment) {
SStream_concat(O, "%s:", X86_reg_name(1, MI->x86_segment));
}
printMemOffset(MI, OpNo, O);
}
@ -168,12 +243,6 @@ static void printMemOffs16(MCInst *MI, unsigned OpNo, SStream *O)
{
SStream_concat(O, "word ptr ");
// If this has a segment register, print it.
// this is a hack. will fix it later
if (MI->x86_segment) {
SStream_concat(O, "%s:", X86_reg_name(1, MI->x86_segment));
}
printMemOffset(MI, OpNo, O);
}
@ -182,12 +251,6 @@ static void printMemOffs32(MCInst *MI, unsigned OpNo, SStream *O)
{
SStream_concat(O, "dword ptr ");
// If this has a segment register, print it.
// this is a hack. will fix it later
if (MI->x86_segment) {
SStream_concat(O, "%s:", X86_reg_name(1, MI->x86_segment));
}
printMemOffset(MI, OpNo, O);
}
@ -197,68 +260,33 @@ static void printMemOffs64(MCInst *MI, unsigned OpNo, SStream *O)
printMemOffset(MI, OpNo, O);
}
// get the first op from the asm buffer
// return False if there is no op. On True, put fist op in @firstop
// NOTE: make sure firstop is big enough to contain the resulted string
static bool get_first_op(char *buffer, char *firstop)
{
char *tab = strchr(buffer, '\t');
if (tab) {
char *comma = strchr(tab + 1, ',');
if (comma) {
memcpy(firstop, tab + 1, comma - tab - 1);
firstop[comma - tab - 1] = '\0';
} else
strcpy(firstop, tab + 1);
return true;
} else // no op
return false;
}
static bool printAliasInstr(MCInst *MI, SStream *OS);
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info);
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
void X86_Intel_printInst(MCInst *MI, SStream *O, void *Info)
{
//if (TSFlags & X86II::LOCK)
// O << "\tlock\n";
char *mnem;
x86_reg reg;
if (printAliasInstr(MI, O)) {
char *mnem = cs_strdup(O->buffer);
char *tab = strchr(mnem, '\t');
if (tab)
*tab = '\0';
// reflect the new insn name (alias) in the opcode
MCInst_setOpcode(MI, X86_get_insn_id2(X86_map_insn(mnem)));
// Try to print any aliases first.
mnem = printAliasInstr(MI, O, NULL);
if (mnem)
cs_mem_free(mnem);
} else
else
printInstruction(MI, O, NULL);
if (MI->csh->detail) {
char tmp[64];
if (get_first_op(O->buffer, tmp)) {
int post;
char *acc_regs[] = { "al", "ax", "eax", "rax", NULL };
int acc_regs_id[] = { X86_REG_AL, X86_REG_AX, X86_REG_EAX, X86_REG_RAX };
if (tmp[0] != 0 && ((post = str_in_list(acc_regs, tmp)) != -1)) {
// first op is register, so set operand size following register size
MI->flat_insn.x86.op_size = 1 << post;
// tmp is a register
if ((MI->flat_insn.x86.operands[0].type != X86_OP_INVALID) &&
((MI->flat_insn.x86.operands[0].type != X86_OP_REG) ||
(MI->flat_insn.x86.operands[0].reg != acc_regs_id[post]))) {
// first op is register, so insert its detail to position 0
int i;
for (i = MI->flat_insn.x86.op_count; i > 0; i--) {
memcpy(&(MI->flat_insn.x86.operands[i]), &(MI->flat_insn.x86.operands[i - 1]),
sizeof(MI->flat_insn.x86.operands[0]));
}
MI->flat_insn.x86.operands[0].type = X86_OP_REG;
MI->flat_insn.x86.operands[0].reg = x86_map_regname(tmp);
MI->flat_insn.x86.op_count++;
}
}
// first op can be embedded in the asm by llvm.
// so we have to handle that case to not miss the first op.
reg = X86_insn_reg(MCInst_getOpcode(MI));
if (reg) {
// shift all the ops right to leave 1st slot for this new register op
memmove(&(MI->flat_insn.x86.operands[1]), &(MI->flat_insn.x86.operands[0]),
sizeof(MI->flat_insn.x86.operands[0]) * (ARR_SIZE(MI->flat_insn.x86.operands) - 1));
MI->flat_insn.x86.operands[0].type = X86_OP_REG;
MI->flat_insn.x86.operands[0].reg = reg;
MI->flat_insn.x86.op_count++;
}
}
}
@ -290,7 +318,7 @@ static void printAVXCC(MCInst *MI, unsigned Op, SStream *O)
{
int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x1f;
switch (Imm) {
default: printf("Invalid avxcc argument!\n"); break;
default: break;//printf("Invalid avxcc argument!\n"); break;
case 0: SStream_concat(O, "eq"); break;
case 1: SStream_concat(O, "lt"); break;
case 2: SStream_concat(O, "le"); break;
@ -326,6 +354,18 @@ static void printAVXCC(MCInst *MI, unsigned Op, SStream *O)
}
}
static void printRoundingControl(MCInst *MI, unsigned Op, SStream *O)
{
int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x3;
switch (Imm) {
case 0: SStream_concat(O, "{rn-sae}"); break;
case 1: SStream_concat(O, "{rd-sae}"); break;
case 2: SStream_concat(O, "{ru-sae}"); break;
case 3: SStream_concat(O, "{rz-sae}"); break;
default: break; // never reach
}
}
/// printPCRelImm - This is used to print an immediate value that ends up
/// being encoded as a pc-relative value.
static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O)
@ -352,7 +392,7 @@ static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O)
}
}
static const char *getRegisterName(unsigned RegNo);
static char *getRegisterName(unsigned RegNo);
static void printRegName(SStream *OS, unsigned RegNo)
{
SStream_concat(OS, getRegisterName(RegNo));
@ -415,7 +455,7 @@ static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O)
static void printMemReference(MCInst *MI, unsigned Op, SStream *O) // qqq
{
MCOperand *BaseReg = MCInst_getOperand(MI, Op);
unsigned ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op+1));
uint64_t ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op+1));
MCOperand *IndexReg = MCInst_getOperand(MI, Op+2);
MCOperand *DispSpec = MCInst_getOperand(MI, Op+3);
MCOperand *SegReg = MCInst_getOperand(MI, Op+4);
@ -424,7 +464,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O) // qqq
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].type = X86_OP_MEM;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.base = MCOperand_getReg(BaseReg);
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.index = MCOperand_getReg(IndexReg);
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.scale = ScaleVal;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.scale = (int)ScaleVal;
MI->flat_insn.x86.operands[MI->flat_insn.x86.op_count].mem.disp = 0;
}

File diff suppressed because it is too large Load Diff

@ -29,18 +29,19 @@ void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
// return insn name, given insn id
const char *X86_insn_name(csh handle, unsigned int id);
// return insn id, given insn mnemonic
x86_reg X86_map_insn(const char *mnem);
// given public insn id, return internal insn id
unsigned int X86_get_insn_id2(unsigned int insn_id);
// post printer for X86.
void X86_post_printer(csh handle, cs_insn *pub_insn, char *insn_asm);
// handle X86 prefixes
bool X86_insn_check_combine(cs_struct *h, cs_insn *insn);
// merge with previous instruction
// this is to handle some 'prefixed' instructions such as LOCK or REP
void X86_insn_combine(cs_struct *h, cs_insn *insn, cs_insn *prev);
// return register of given instruction id
// return 0 if not found
// this is to handle instructions embedding accumulate registers into AsmStrs[]
x86_reg X86_insn_reg(unsigned int id);
#endif

@ -203,7 +203,7 @@ public class Capstone {
public int cs_open(int arch, int mode, NativeLongByReference handle);
public NativeLong cs_disasm_ex(NativeLong handle, byte[] code, NativeLong code_len,
long addr, NativeLong count, PointerByReference insn);
public void cs_free(Pointer p);
public void cs_free(Pointer p, NativeLong count);
public int cs_close(NativeLong handle);
public int cs_option(NativeLong handle, int option, NativeLong optionValue);
@ -217,11 +217,12 @@ public class Capstone {
public byte cs_reg_write(NativeLong csh, Pointer insn, int id);
public int cs_errno(NativeLong csh);
public int cs_version(IntByReference major, IntByReference minor);
public boolean cs_support(int query);
}
// capstone API version
public static final int CS_API_MAJOR = 2;
public static final int CS_API_MINOR = 0;
public static final int CS_API_MINOR = 1;
public static final int CS_ARCH_ARM = 0;
public static final int CS_ARCH_ARM64 = 1;
@ -259,6 +260,8 @@ public class Capstone {
public static final int CS_OPT_ON = 3; // Turn ON an option (CS_OPT_DETAIL)
public static final int CS_OPT_SYNTAX_NOREGNAME = 3; // PPC asm syntax: Prints register name with only number (CS_OPT_SYNTAX)
public static final int CS_SUPPORT_DIET = 0xFFFF+1; // diet mode
protected class NativeStruct {
private NativeLong csh;
private NativeLongByReference handleRef;
@ -272,10 +275,15 @@ public class Capstone {
private int detail;
public Capstone(int arch, int mode) {
cs = (CS)Native.loadLibrary("capstone", CS.class);
int version = cs.cs_version(null, null);
if (version != (CS_API_MAJOR << 8) + CS_API_MINOR) {
throw new RuntimeException("Different API version between core & binding (CS_ERR_VERSION)");
}
this.arch = arch;
this.mode = mode;
ns = new NativeStruct();
cs = (CS)Native.loadLibrary("capstone", CS.class);
ns.handleRef = new NativeLongByReference();
if (cs.cs_open(arch, mode, ns.handleRef) != CS_ERR_OK) {
throw new RuntimeException("ERROR: Wrong arch or mode");
@ -329,6 +337,10 @@ public class Capstone {
_cs_insn byref = new _cs_insn(p);
CsInsn[] allInsn = fromArrayRaw((_cs_insn[]) byref.toArray(c.intValue()));
// free allocated memory
cs.cs_free(p, c);
return allInsn;
}
}

@ -289,355 +289,356 @@ public class Mips_const {
public static final int MIPS_INS_DINSU = 106;
public static final int MIPS_INS_DIV_S = 107;
public static final int MIPS_INS_DIV_U = 108;
public static final int MIPS_INS_DMFC0 = 109;
public static final int MIPS_INS_DMFC1 = 110;
public static final int MIPS_INS_DMFC2 = 111;
public static final int MIPS_INS_DMTC0 = 112;
public static final int MIPS_INS_DMTC1 = 113;
public static final int MIPS_INS_DMTC2 = 114;
public static final int MIPS_INS_DMULT = 115;
public static final int MIPS_INS_DMULTU = 116;
public static final int MIPS_INS_DOTP_S = 117;
public static final int MIPS_INS_DOTP_U = 118;
public static final int MIPS_INS_DPADD_S = 119;
public static final int MIPS_INS_DPADD_U = 120;
public static final int MIPS_INS_DPAQX_SA = 121;
public static final int MIPS_INS_DPAQX_S = 122;
public static final int MIPS_INS_DPAQ_SA = 123;
public static final int MIPS_INS_DPAQ_S = 124;
public static final int MIPS_INS_DPAU = 125;
public static final int MIPS_INS_DPAX = 126;
public static final int MIPS_INS_DPA = 127;
public static final int MIPS_INS_DPSQX_SA = 128;
public static final int MIPS_INS_DPSQX_S = 129;
public static final int MIPS_INS_DPSQ_SA = 130;
public static final int MIPS_INS_DPSQ_S = 131;
public static final int MIPS_INS_DPSUB_S = 132;
public static final int MIPS_INS_DPSUB_U = 133;
public static final int MIPS_INS_DPSU = 134;
public static final int MIPS_INS_DPSX = 135;
public static final int MIPS_INS_DPS = 136;
public static final int MIPS_INS_DROTR = 137;
public static final int MIPS_INS_DROTR32 = 138;
public static final int MIPS_INS_DROTRV = 139;
public static final int MIPS_INS_DSBH = 140;
public static final int MIPS_INS_DDIV = 141;
public static final int MIPS_INS_DSHD = 142;
public static final int MIPS_INS_DSLL = 143;
public static final int MIPS_INS_DSLL32 = 144;
public static final int MIPS_INS_DSLLV = 145;
public static final int MIPS_INS_DSRA = 146;
public static final int MIPS_INS_DSRA32 = 147;
public static final int MIPS_INS_DSRAV = 148;
public static final int MIPS_INS_DSRL = 149;
public static final int MIPS_INS_DSRL32 = 150;
public static final int MIPS_INS_DSRLV = 151;
public static final int MIPS_INS_DSUBU = 152;
public static final int MIPS_INS_DDIVU = 153;
public static final int MIPS_INS_DIV = 154;
public static final int MIPS_INS_DIVU = 155;
public static final int MIPS_INS_EI = 156;
public static final int MIPS_INS_ERET = 157;
public static final int MIPS_INS_EXT = 158;
public static final int MIPS_INS_EXTP = 159;
public static final int MIPS_INS_EXTPDP = 160;
public static final int MIPS_INS_EXTPDPV = 161;
public static final int MIPS_INS_EXTPV = 162;
public static final int MIPS_INS_EXTRV_RS = 163;
public static final int MIPS_INS_EXTRV_R = 164;
public static final int MIPS_INS_EXTRV_S = 165;
public static final int MIPS_INS_EXTRV = 166;
public static final int MIPS_INS_EXTR_RS = 167;
public static final int MIPS_INS_EXTR_R = 168;
public static final int MIPS_INS_EXTR_S = 169;
public static final int MIPS_INS_EXTR = 170;
public static final int MIPS_INS_ABS = 171;
public static final int MIPS_INS_FADD = 172;
public static final int MIPS_INS_FCAF = 173;
public static final int MIPS_INS_FCEQ = 174;
public static final int MIPS_INS_FCLASS = 175;
public static final int MIPS_INS_FCLE = 176;
public static final int MIPS_INS_FCLT = 177;
public static final int MIPS_INS_FCNE = 178;
public static final int MIPS_INS_FCOR = 179;
public static final int MIPS_INS_FCUEQ = 180;
public static final int MIPS_INS_FCULE = 181;
public static final int MIPS_INS_FCULT = 182;
public static final int MIPS_INS_FCUNE = 183;
public static final int MIPS_INS_FCUN = 184;
public static final int MIPS_INS_FDIV = 185;
public static final int MIPS_INS_FEXDO = 186;
public static final int MIPS_INS_FEXP2 = 187;
public static final int MIPS_INS_FEXUPL = 188;
public static final int MIPS_INS_FEXUPR = 189;
public static final int MIPS_INS_FFINT_S = 190;
public static final int MIPS_INS_FFINT_U = 191;
public static final int MIPS_INS_FFQL = 192;
public static final int MIPS_INS_FFQR = 193;
public static final int MIPS_INS_FILL = 194;
public static final int MIPS_INS_FLOG2 = 195;
public static final int MIPS_INS_FLOOR = 196;
public static final int MIPS_INS_FMADD = 197;
public static final int MIPS_INS_FMAX_A = 198;
public static final int MIPS_INS_FMAX = 199;
public static final int MIPS_INS_FMIN_A = 200;
public static final int MIPS_INS_FMIN = 201;
public static final int MIPS_INS_MOV = 202;
public static final int MIPS_INS_FMSUB = 203;
public static final int MIPS_INS_FMUL = 204;
public static final int MIPS_INS_MUL = 205;
public static final int MIPS_INS_NEG = 206;
public static final int MIPS_INS_FRCP = 207;
public static final int MIPS_INS_FRINT = 208;
public static final int MIPS_INS_FRSQRT = 209;
public static final int MIPS_INS_FSAF = 210;
public static final int MIPS_INS_FSEQ = 211;
public static final int MIPS_INS_FSLE = 212;
public static final int MIPS_INS_FSLT = 213;
public static final int MIPS_INS_FSNE = 214;
public static final int MIPS_INS_FSOR = 215;
public static final int MIPS_INS_FSQRT = 216;
public static final int MIPS_INS_SQRT = 217;
public static final int MIPS_INS_FSUB = 218;
public static final int MIPS_INS_SUB = 219;
public static final int MIPS_INS_FSUEQ = 220;
public static final int MIPS_INS_FSULE = 221;
public static final int MIPS_INS_FSULT = 222;
public static final int MIPS_INS_FSUNE = 223;
public static final int MIPS_INS_FSUN = 224;
public static final int MIPS_INS_FTINT_S = 225;
public static final int MIPS_INS_FTINT_U = 226;
public static final int MIPS_INS_FTQ = 227;
public static final int MIPS_INS_FTRUNC_S = 228;
public static final int MIPS_INS_FTRUNC_U = 229;
public static final int MIPS_INS_HADD_S = 230;
public static final int MIPS_INS_HADD_U = 231;
public static final int MIPS_INS_HSUB_S = 232;
public static final int MIPS_INS_HSUB_U = 233;
public static final int MIPS_INS_ILVEV = 234;
public static final int MIPS_INS_ILVL = 235;
public static final int MIPS_INS_ILVOD = 236;
public static final int MIPS_INS_ILVR = 237;
public static final int MIPS_INS_INS = 238;
public static final int MIPS_INS_INSERT = 239;
public static final int MIPS_INS_INSV = 240;
public static final int MIPS_INS_INSVE = 241;
public static final int MIPS_INS_J = 242;
public static final int MIPS_INS_JAL = 243;
public static final int MIPS_INS_JALR = 244;
public static final int MIPS_INS_JR = 245;
public static final int MIPS_INS_JRC = 246;
public static final int MIPS_INS_JALRC = 247;
public static final int MIPS_INS_LB = 248;
public static final int MIPS_INS_LBUX = 249;
public static final int MIPS_INS_LBU = 250;
public static final int MIPS_INS_LD = 251;
public static final int MIPS_INS_LDC1 = 252;
public static final int MIPS_INS_LDC2 = 253;
public static final int MIPS_INS_LDI = 254;
public static final int MIPS_INS_LDL = 255;
public static final int MIPS_INS_LDR = 256;
public static final int MIPS_INS_LDXC1 = 257;
public static final int MIPS_INS_LH = 258;
public static final int MIPS_INS_LHX = 259;
public static final int MIPS_INS_LHU = 260;
public static final int MIPS_INS_LL = 261;
public static final int MIPS_INS_LLD = 262;
public static final int MIPS_INS_LSA = 263;
public static final int MIPS_INS_LUXC1 = 264;
public static final int MIPS_INS_LUI = 265;
public static final int MIPS_INS_LW = 266;
public static final int MIPS_INS_LWC1 = 267;
public static final int MIPS_INS_LWC2 = 268;
public static final int MIPS_INS_LWL = 269;
public static final int MIPS_INS_LWR = 270;
public static final int MIPS_INS_LWX = 271;
public static final int MIPS_INS_LWXC1 = 272;
public static final int MIPS_INS_LWU = 273;
public static final int MIPS_INS_LI = 274;
public static final int MIPS_INS_MADD = 275;
public static final int MIPS_INS_MADDR_Q = 276;
public static final int MIPS_INS_MADDU = 277;
public static final int MIPS_INS_MADDV = 278;
public static final int MIPS_INS_MADD_Q = 279;
public static final int MIPS_INS_MAQ_SA = 280;
public static final int MIPS_INS_MAQ_S = 281;
public static final int MIPS_INS_MAXI_S = 282;
public static final int MIPS_INS_MAXI_U = 283;
public static final int MIPS_INS_MAX_A = 284;
public static final int MIPS_INS_MAX_S = 285;
public static final int MIPS_INS_MAX_U = 286;
public static final int MIPS_INS_MFC0 = 287;
public static final int MIPS_INS_MFC1 = 288;
public static final int MIPS_INS_MFC2 = 289;
public static final int MIPS_INS_MFHC1 = 290;
public static final int MIPS_INS_MFHI = 291;
public static final int MIPS_INS_MFLO = 292;
public static final int MIPS_INS_MINI_S = 293;
public static final int MIPS_INS_MINI_U = 294;
public static final int MIPS_INS_MIN_A = 295;
public static final int MIPS_INS_MIN_S = 296;
public static final int MIPS_INS_MIN_U = 297;
public static final int MIPS_INS_MODSUB = 298;
public static final int MIPS_INS_MOD_S = 299;
public static final int MIPS_INS_MOD_U = 300;
public static final int MIPS_INS_MOVE = 301;
public static final int MIPS_INS_MOVF = 302;
public static final int MIPS_INS_MOVN = 303;
public static final int MIPS_INS_MOVT = 304;
public static final int MIPS_INS_MOVZ = 305;
public static final int MIPS_INS_MSUB = 306;
public static final int MIPS_INS_MSUBR_Q = 307;
public static final int MIPS_INS_MSUBU = 308;
public static final int MIPS_INS_MSUBV = 309;
public static final int MIPS_INS_MSUB_Q = 310;
public static final int MIPS_INS_MTC0 = 311;
public static final int MIPS_INS_MTC1 = 312;
public static final int MIPS_INS_MTC2 = 313;
public static final int MIPS_INS_MTHC1 = 314;
public static final int MIPS_INS_MTHI = 315;
public static final int MIPS_INS_MTHLIP = 316;
public static final int MIPS_INS_MTLO = 317;
public static final int MIPS_INS_MULEQ_S = 318;
public static final int MIPS_INS_MULEU_S = 319;
public static final int MIPS_INS_MULQ_RS = 320;
public static final int MIPS_INS_MULQ_S = 321;
public static final int MIPS_INS_MULR_Q = 322;
public static final int MIPS_INS_MULSAQ_S = 323;
public static final int MIPS_INS_MULSA = 324;
public static final int MIPS_INS_MULT = 325;
public static final int MIPS_INS_MULTU = 326;
public static final int MIPS_INS_MULV = 327;
public static final int MIPS_INS_MUL_Q = 328;
public static final int MIPS_INS_MUL_S = 329;
public static final int MIPS_INS_NLOC = 330;
public static final int MIPS_INS_NLZC = 331;
public static final int MIPS_INS_NMADD = 332;
public static final int MIPS_INS_NMSUB = 333;
public static final int MIPS_INS_NOR = 334;
public static final int MIPS_INS_NORI = 335;
public static final int MIPS_INS_NOT = 336;
public static final int MIPS_INS_OR = 337;
public static final int MIPS_INS_ORI = 338;
public static final int MIPS_INS_PACKRL = 339;
public static final int MIPS_INS_PCKEV = 340;
public static final int MIPS_INS_PCKOD = 341;
public static final int MIPS_INS_PCNT = 342;
public static final int MIPS_INS_PICK = 343;
public static final int MIPS_INS_PRECEQU = 344;
public static final int MIPS_INS_PRECEQ = 345;
public static final int MIPS_INS_PRECEU = 346;
public static final int MIPS_INS_PRECRQU_S = 347;
public static final int MIPS_INS_PRECRQ = 348;
public static final int MIPS_INS_PRECRQ_RS = 349;
public static final int MIPS_INS_PRECR = 350;
public static final int MIPS_INS_PRECR_SRA = 351;
public static final int MIPS_INS_PRECR_SRA_R = 352;
public static final int MIPS_INS_PREPEND = 353;
public static final int MIPS_INS_RADDU = 354;
public static final int MIPS_INS_RDDSP = 355;
public static final int MIPS_INS_RDHWR = 356;
public static final int MIPS_INS_REPLV = 357;
public static final int MIPS_INS_REPL = 358;
public static final int MIPS_INS_ROTR = 359;
public static final int MIPS_INS_ROTRV = 360;
public static final int MIPS_INS_ROUND = 361;
public static final int MIPS_INS_SAT_S = 362;
public static final int MIPS_INS_SAT_U = 363;
public static final int MIPS_INS_SB = 364;
public static final int MIPS_INS_SC = 365;
public static final int MIPS_INS_SCD = 366;
public static final int MIPS_INS_SD = 367;
public static final int MIPS_INS_SDC1 = 368;
public static final int MIPS_INS_SDC2 = 369;
public static final int MIPS_INS_SDL = 370;
public static final int MIPS_INS_SDR = 371;
public static final int MIPS_INS_SDXC1 = 372;
public static final int MIPS_INS_SEB = 373;
public static final int MIPS_INS_SEH = 374;
public static final int MIPS_INS_SH = 375;
public static final int MIPS_INS_SHF = 376;
public static final int MIPS_INS_SHILO = 377;
public static final int MIPS_INS_SHILOV = 378;
public static final int MIPS_INS_SHLLV = 379;
public static final int MIPS_INS_SHLLV_S = 380;
public static final int MIPS_INS_SHLL = 381;
public static final int MIPS_INS_SHLL_S = 382;
public static final int MIPS_INS_SHRAV = 383;
public static final int MIPS_INS_SHRAV_R = 384;
public static final int MIPS_INS_SHRA = 385;
public static final int MIPS_INS_SHRA_R = 386;
public static final int MIPS_INS_SHRLV = 387;
public static final int MIPS_INS_SHRL = 388;
public static final int MIPS_INS_SLDI = 389;
public static final int MIPS_INS_SLD = 390;
public static final int MIPS_INS_SLL = 391;
public static final int MIPS_INS_SLLI = 392;
public static final int MIPS_INS_SLLV = 393;
public static final int MIPS_INS_SLT = 394;
public static final int MIPS_INS_SLTI = 395;
public static final int MIPS_INS_SLTIU = 396;
public static final int MIPS_INS_SLTU = 397;
public static final int MIPS_INS_SPLATI = 398;
public static final int MIPS_INS_SPLAT = 399;
public static final int MIPS_INS_SRA = 400;
public static final int MIPS_INS_SRAI = 401;
public static final int MIPS_INS_SRARI = 402;
public static final int MIPS_INS_SRAR = 403;
public static final int MIPS_INS_SRAV = 404;
public static final int MIPS_INS_SRL = 405;
public static final int MIPS_INS_SRLI = 406;
public static final int MIPS_INS_SRLRI = 407;
public static final int MIPS_INS_SRLR = 408;
public static final int MIPS_INS_SRLV = 409;
public static final int MIPS_INS_ST = 410;
public static final int MIPS_INS_SUBQH = 411;
public static final int MIPS_INS_SUBQH_R = 412;
public static final int MIPS_INS_SUBQ = 413;
public static final int MIPS_INS_SUBQ_S = 414;
public static final int MIPS_INS_SUBSUS_U = 415;
public static final int MIPS_INS_SUBSUU_S = 416;
public static final int MIPS_INS_SUBS_S = 417;
public static final int MIPS_INS_SUBS_U = 418;
public static final int MIPS_INS_SUBUH = 419;
public static final int MIPS_INS_SUBUH_R = 420;
public static final int MIPS_INS_SUBU = 421;
public static final int MIPS_INS_SUBU_S = 422;
public static final int MIPS_INS_SUBVI = 423;
public static final int MIPS_INS_SUBV = 424;
public static final int MIPS_INS_SUXC1 = 425;
public static final int MIPS_INS_SW = 426;
public static final int MIPS_INS_SWC1 = 427;
public static final int MIPS_INS_SWC2 = 428;
public static final int MIPS_INS_SWL = 429;
public static final int MIPS_INS_SWR = 430;
public static final int MIPS_INS_SWXC1 = 431;
public static final int MIPS_INS_SYNC = 432;
public static final int MIPS_INS_SYSCALL = 433;
public static final int MIPS_INS_TEQ = 434;
public static final int MIPS_INS_TEQI = 435;
public static final int MIPS_INS_TGE = 436;
public static final int MIPS_INS_TGEI = 437;
public static final int MIPS_INS_TGEIU = 438;
public static final int MIPS_INS_TGEU = 439;
public static final int MIPS_INS_TLT = 440;
public static final int MIPS_INS_TLTI = 441;
public static final int MIPS_INS_TLTIU = 442;
public static final int MIPS_INS_TLTU = 443;
public static final int MIPS_INS_TNE = 444;
public static final int MIPS_INS_TNEI = 445;
public static final int MIPS_INS_TRUNC = 446;
public static final int MIPS_INS_VSHF = 447;
public static final int MIPS_INS_WAIT = 448;
public static final int MIPS_INS_WRDSP = 449;
public static final int MIPS_INS_WSBH = 450;
public static final int MIPS_INS_XOR = 451;
public static final int MIPS_INS_XORI = 452;
public static final int MIPS_INS_DLSA = 109;
public static final int MIPS_INS_DMFC0 = 110;
public static final int MIPS_INS_DMFC1 = 111;
public static final int MIPS_INS_DMFC2 = 112;
public static final int MIPS_INS_DMTC0 = 113;
public static final int MIPS_INS_DMTC1 = 114;
public static final int MIPS_INS_DMTC2 = 115;
public static final int MIPS_INS_DMULT = 116;
public static final int MIPS_INS_DMULTU = 117;
public static final int MIPS_INS_DOTP_S = 118;
public static final int MIPS_INS_DOTP_U = 119;
public static final int MIPS_INS_DPADD_S = 120;
public static final int MIPS_INS_DPADD_U = 121;
public static final int MIPS_INS_DPAQX_SA = 122;
public static final int MIPS_INS_DPAQX_S = 123;
public static final int MIPS_INS_DPAQ_SA = 124;
public static final int MIPS_INS_DPAQ_S = 125;
public static final int MIPS_INS_DPAU = 126;
public static final int MIPS_INS_DPAX = 127;
public static final int MIPS_INS_DPA = 128;
public static final int MIPS_INS_DPSQX_SA = 129;
public static final int MIPS_INS_DPSQX_S = 130;
public static final int MIPS_INS_DPSQ_SA = 131;
public static final int MIPS_INS_DPSQ_S = 132;
public static final int MIPS_INS_DPSUB_S = 133;
public static final int MIPS_INS_DPSUB_U = 134;
public static final int MIPS_INS_DPSU = 135;
public static final int MIPS_INS_DPSX = 136;
public static final int MIPS_INS_DPS = 137;
public static final int MIPS_INS_DROTR = 138;
public static final int MIPS_INS_DROTR32 = 139;
public static final int MIPS_INS_DROTRV = 140;
public static final int MIPS_INS_DSBH = 141;
public static final int MIPS_INS_DDIV = 142;
public static final int MIPS_INS_DSHD = 143;
public static final int MIPS_INS_DSLL = 144;
public static final int MIPS_INS_DSLL32 = 145;
public static final int MIPS_INS_DSLLV = 146;
public static final int MIPS_INS_DSRA = 147;
public static final int MIPS_INS_DSRA32 = 148;
public static final int MIPS_INS_DSRAV = 149;
public static final int MIPS_INS_DSRL = 150;
public static final int MIPS_INS_DSRL32 = 151;
public static final int MIPS_INS_DSRLV = 152;
public static final int MIPS_INS_DSUBU = 153;
public static final int MIPS_INS_DDIVU = 154;
public static final int MIPS_INS_DIV = 155;
public static final int MIPS_INS_DIVU = 156;
public static final int MIPS_INS_EI = 157;
public static final int MIPS_INS_ERET = 158;
public static final int MIPS_INS_EXT = 159;
public static final int MIPS_INS_EXTP = 160;
public static final int MIPS_INS_EXTPDP = 161;
public static final int MIPS_INS_EXTPDPV = 162;
public static final int MIPS_INS_EXTPV = 163;
public static final int MIPS_INS_EXTRV_RS = 164;
public static final int MIPS_INS_EXTRV_R = 165;
public static final int MIPS_INS_EXTRV_S = 166;
public static final int MIPS_INS_EXTRV = 167;
public static final int MIPS_INS_EXTR_RS = 168;
public static final int MIPS_INS_EXTR_R = 169;
public static final int MIPS_INS_EXTR_S = 170;
public static final int MIPS_INS_EXTR = 171;
public static final int MIPS_INS_ABS = 172;
public static final int MIPS_INS_FADD = 173;
public static final int MIPS_INS_FCAF = 174;
public static final int MIPS_INS_FCEQ = 175;
public static final int MIPS_INS_FCLASS = 176;
public static final int MIPS_INS_FCLE = 177;
public static final int MIPS_INS_FCLT = 178;
public static final int MIPS_INS_FCNE = 179;
public static final int MIPS_INS_FCOR = 180;
public static final int MIPS_INS_FCUEQ = 181;
public static final int MIPS_INS_FCULE = 182;
public static final int MIPS_INS_FCULT = 183;
public static final int MIPS_INS_FCUNE = 184;
public static final int MIPS_INS_FCUN = 185;
public static final int MIPS_INS_FDIV = 186;
public static final int MIPS_INS_FEXDO = 187;
public static final int MIPS_INS_FEXP2 = 188;
public static final int MIPS_INS_FEXUPL = 189;
public static final int MIPS_INS_FEXUPR = 190;
public static final int MIPS_INS_FFINT_S = 191;
public static final int MIPS_INS_FFINT_U = 192;
public static final int MIPS_INS_FFQL = 193;
public static final int MIPS_INS_FFQR = 194;
public static final int MIPS_INS_FILL = 195;
public static final int MIPS_INS_FLOG2 = 196;
public static final int MIPS_INS_FLOOR = 197;
public static final int MIPS_INS_FMADD = 198;
public static final int MIPS_INS_FMAX_A = 199;
public static final int MIPS_INS_FMAX = 200;
public static final int MIPS_INS_FMIN_A = 201;
public static final int MIPS_INS_FMIN = 202;
public static final int MIPS_INS_MOV = 203;
public static final int MIPS_INS_FMSUB = 204;
public static final int MIPS_INS_FMUL = 205;
public static final int MIPS_INS_MUL = 206;
public static final int MIPS_INS_NEG = 207;
public static final int MIPS_INS_FRCP = 208;
public static final int MIPS_INS_FRINT = 209;
public static final int MIPS_INS_FRSQRT = 210;
public static final int MIPS_INS_FSAF = 211;
public static final int MIPS_INS_FSEQ = 212;
public static final int MIPS_INS_FSLE = 213;
public static final int MIPS_INS_FSLT = 214;
public static final int MIPS_INS_FSNE = 215;
public static final int MIPS_INS_FSOR = 216;
public static final int MIPS_INS_FSQRT = 217;
public static final int MIPS_INS_SQRT = 218;
public static final int MIPS_INS_FSUB = 219;
public static final int MIPS_INS_SUB = 220;
public static final int MIPS_INS_FSUEQ = 221;
public static final int MIPS_INS_FSULE = 222;
public static final int MIPS_INS_FSULT = 223;
public static final int MIPS_INS_FSUNE = 224;
public static final int MIPS_INS_FSUN = 225;
public static final int MIPS_INS_FTINT_S = 226;
public static final int MIPS_INS_FTINT_U = 227;
public static final int MIPS_INS_FTQ = 228;
public static final int MIPS_INS_FTRUNC_S = 229;
public static final int MIPS_INS_FTRUNC_U = 230;
public static final int MIPS_INS_HADD_S = 231;
public static final int MIPS_INS_HADD_U = 232;
public static final int MIPS_INS_HSUB_S = 233;
public static final int MIPS_INS_HSUB_U = 234;
public static final int MIPS_INS_ILVEV = 235;
public static final int MIPS_INS_ILVL = 236;
public static final int MIPS_INS_ILVOD = 237;
public static final int MIPS_INS_ILVR = 238;
public static final int MIPS_INS_INS = 239;
public static final int MIPS_INS_INSERT = 240;
public static final int MIPS_INS_INSV = 241;
public static final int MIPS_INS_INSVE = 242;
public static final int MIPS_INS_J = 243;
public static final int MIPS_INS_JAL = 244;
public static final int MIPS_INS_JALR = 245;
public static final int MIPS_INS_JR = 246;
public static final int MIPS_INS_JRC = 247;
public static final int MIPS_INS_JALRC = 248;
public static final int MIPS_INS_LB = 249;
public static final int MIPS_INS_LBUX = 250;
public static final int MIPS_INS_LBU = 251;
public static final int MIPS_INS_LD = 252;
public static final int MIPS_INS_LDC1 = 253;
public static final int MIPS_INS_LDC2 = 254;
public static final int MIPS_INS_LDI = 255;
public static final int MIPS_INS_LDL = 256;
public static final int MIPS_INS_LDR = 257;
public static final int MIPS_INS_LDXC1 = 258;
public static final int MIPS_INS_LH = 259;
public static final int MIPS_INS_LHX = 260;
public static final int MIPS_INS_LHU = 261;
public static final int MIPS_INS_LL = 262;
public static final int MIPS_INS_LLD = 263;
public static final int MIPS_INS_LSA = 264;
public static final int MIPS_INS_LUXC1 = 265;
public static final int MIPS_INS_LUI = 266;
public static final int MIPS_INS_LW = 267;
public static final int MIPS_INS_LWC1 = 268;
public static final int MIPS_INS_LWC2 = 269;
public static final int MIPS_INS_LWL = 270;
public static final int MIPS_INS_LWR = 271;
public static final int MIPS_INS_LWU = 272;
public static final int MIPS_INS_LWX = 273;
public static final int MIPS_INS_LWXC1 = 274;
public static final int MIPS_INS_LI = 275;
public static final int MIPS_INS_MADD = 276;
public static final int MIPS_INS_MADDR_Q = 277;
public static final int MIPS_INS_MADDU = 278;
public static final int MIPS_INS_MADDV = 279;
public static final int MIPS_INS_MADD_Q = 280;
public static final int MIPS_INS_MAQ_SA = 281;
public static final int MIPS_INS_MAQ_S = 282;
public static final int MIPS_INS_MAXI_S = 283;
public static final int MIPS_INS_MAXI_U = 284;
public static final int MIPS_INS_MAX_A = 285;
public static final int MIPS_INS_MAX_S = 286;
public static final int MIPS_INS_MAX_U = 287;
public static final int MIPS_INS_MFC0 = 288;
public static final int MIPS_INS_MFC1 = 289;
public static final int MIPS_INS_MFC2 = 290;
public static final int MIPS_INS_MFHC1 = 291;
public static final int MIPS_INS_MFHI = 292;
public static final int MIPS_INS_MFLO = 293;
public static final int MIPS_INS_MINI_S = 294;
public static final int MIPS_INS_MINI_U = 295;
public static final int MIPS_INS_MIN_A = 296;
public static final int MIPS_INS_MIN_S = 297;
public static final int MIPS_INS_MIN_U = 298;
public static final int MIPS_INS_MODSUB = 299;
public static final int MIPS_INS_MOD_S = 300;
public static final int MIPS_INS_MOD_U = 301;
public static final int MIPS_INS_MOVE = 302;
public static final int MIPS_INS_MOVF = 303;
public static final int MIPS_INS_MOVN = 304;
public static final int MIPS_INS_MOVT = 305;
public static final int MIPS_INS_MOVZ = 306;
public static final int MIPS_INS_MSUB = 307;
public static final int MIPS_INS_MSUBR_Q = 308;
public static final int MIPS_INS_MSUBU = 309;
public static final int MIPS_INS_MSUBV = 310;
public static final int MIPS_INS_MSUB_Q = 311;
public static final int MIPS_INS_MTC0 = 312;
public static final int MIPS_INS_MTC1 = 313;
public static final int MIPS_INS_MTC2 = 314;
public static final int MIPS_INS_MTHC1 = 315;
public static final int MIPS_INS_MTHI = 316;
public static final int MIPS_INS_MTHLIP = 317;
public static final int MIPS_INS_MTLO = 318;
public static final int MIPS_INS_MULEQ_S = 319;
public static final int MIPS_INS_MULEU_S = 320;
public static final int MIPS_INS_MULQ_RS = 321;
public static final int MIPS_INS_MULQ_S = 322;
public static final int MIPS_INS_MULR_Q = 323;
public static final int MIPS_INS_MULSAQ_S = 324;
public static final int MIPS_INS_MULSA = 325;
public static final int MIPS_INS_MULT = 326;
public static final int MIPS_INS_MULTU = 327;
public static final int MIPS_INS_MULV = 328;
public static final int MIPS_INS_MUL_Q = 329;
public static final int MIPS_INS_MUL_S = 330;
public static final int MIPS_INS_NLOC = 331;
public static final int MIPS_INS_NLZC = 332;
public static final int MIPS_INS_NMADD = 333;
public static final int MIPS_INS_NMSUB = 334;
public static final int MIPS_INS_NOR = 335;
public static final int MIPS_INS_NORI = 336;
public static final int MIPS_INS_NOT = 337;
public static final int MIPS_INS_OR = 338;
public static final int MIPS_INS_ORI = 339;
public static final int MIPS_INS_PACKRL = 340;
public static final int MIPS_INS_PCKEV = 341;
public static final int MIPS_INS_PCKOD = 342;
public static final int MIPS_INS_PCNT = 343;
public static final int MIPS_INS_PICK = 344;
public static final int MIPS_INS_PRECEQU = 345;
public static final int MIPS_INS_PRECEQ = 346;
public static final int MIPS_INS_PRECEU = 347;
public static final int MIPS_INS_PRECRQU_S = 348;
public static final int MIPS_INS_PRECRQ = 349;
public static final int MIPS_INS_PRECRQ_RS = 350;
public static final int MIPS_INS_PRECR = 351;
public static final int MIPS_INS_PRECR_SRA = 352;
public static final int MIPS_INS_PRECR_SRA_R = 353;
public static final int MIPS_INS_PREPEND = 354;
public static final int MIPS_INS_RADDU = 355;
public static final int MIPS_INS_RDDSP = 356;
public static final int MIPS_INS_RDHWR = 357;
public static final int MIPS_INS_REPLV = 358;
public static final int MIPS_INS_REPL = 359;
public static final int MIPS_INS_ROTR = 360;
public static final int MIPS_INS_ROTRV = 361;
public static final int MIPS_INS_ROUND = 362;
public static final int MIPS_INS_SAT_S = 363;
public static final int MIPS_INS_SAT_U = 364;
public static final int MIPS_INS_SB = 365;
public static final int MIPS_INS_SC = 366;
public static final int MIPS_INS_SCD = 367;
public static final int MIPS_INS_SD = 368;
public static final int MIPS_INS_SDC1 = 369;
public static final int MIPS_INS_SDC2 = 370;
public static final int MIPS_INS_SDL = 371;
public static final int MIPS_INS_SDR = 372;
public static final int MIPS_INS_SDXC1 = 373;
public static final int MIPS_INS_SEB = 374;
public static final int MIPS_INS_SEH = 375;
public static final int MIPS_INS_SH = 376;
public static final int MIPS_INS_SHF = 377;
public static final int MIPS_INS_SHILO = 378;
public static final int MIPS_INS_SHILOV = 379;
public static final int MIPS_INS_SHLLV = 380;
public static final int MIPS_INS_SHLLV_S = 381;
public static final int MIPS_INS_SHLL = 382;
public static final int MIPS_INS_SHLL_S = 383;
public static final int MIPS_INS_SHRAV = 384;
public static final int MIPS_INS_SHRAV_R = 385;
public static final int MIPS_INS_SHRA = 386;
public static final int MIPS_INS_SHRA_R = 387;
public static final int MIPS_INS_SHRLV = 388;
public static final int MIPS_INS_SHRL = 389;
public static final int MIPS_INS_SLDI = 390;
public static final int MIPS_INS_SLD = 391;
public static final int MIPS_INS_SLL = 392;
public static final int MIPS_INS_SLLI = 393;
public static final int MIPS_INS_SLLV = 394;
public static final int MIPS_INS_SLT = 395;
public static final int MIPS_INS_SLTI = 396;
public static final int MIPS_INS_SLTIU = 397;
public static final int MIPS_INS_SLTU = 398;
public static final int MIPS_INS_SPLATI = 399;
public static final int MIPS_INS_SPLAT = 400;
public static final int MIPS_INS_SRA = 401;
public static final int MIPS_INS_SRAI = 402;
public static final int MIPS_INS_SRARI = 403;
public static final int MIPS_INS_SRAR = 404;
public static final int MIPS_INS_SRAV = 405;
public static final int MIPS_INS_SRL = 406;
public static final int MIPS_INS_SRLI = 407;
public static final int MIPS_INS_SRLRI = 408;
public static final int MIPS_INS_SRLR = 409;
public static final int MIPS_INS_SRLV = 410;
public static final int MIPS_INS_ST = 411;
public static final int MIPS_INS_SUBQH = 412;
public static final int MIPS_INS_SUBQH_R = 413;
public static final int MIPS_INS_SUBQ = 414;
public static final int MIPS_INS_SUBQ_S = 415;
public static final int MIPS_INS_SUBSUS_U = 416;
public static final int MIPS_INS_SUBSUU_S = 417;
public static final int MIPS_INS_SUBS_S = 418;
public static final int MIPS_INS_SUBS_U = 419;
public static final int MIPS_INS_SUBUH = 420;
public static final int MIPS_INS_SUBUH_R = 421;
public static final int MIPS_INS_SUBU = 422;
public static final int MIPS_INS_SUBU_S = 423;
public static final int MIPS_INS_SUBVI = 424;
public static final int MIPS_INS_SUBV = 425;
public static final int MIPS_INS_SUXC1 = 426;
public static final int MIPS_INS_SW = 427;
public static final int MIPS_INS_SWC1 = 428;
public static final int MIPS_INS_SWC2 = 429;
public static final int MIPS_INS_SWL = 430;
public static final int MIPS_INS_SWR = 431;
public static final int MIPS_INS_SWXC1 = 432;
public static final int MIPS_INS_SYNC = 433;
public static final int MIPS_INS_SYSCALL = 434;
public static final int MIPS_INS_TEQ = 435;
public static final int MIPS_INS_TEQI = 436;
public static final int MIPS_INS_TGE = 437;
public static final int MIPS_INS_TGEI = 438;
public static final int MIPS_INS_TGEIU = 439;
public static final int MIPS_INS_TGEU = 440;
public static final int MIPS_INS_TLT = 441;
public static final int MIPS_INS_TLTI = 442;
public static final int MIPS_INS_TLTIU = 443;
public static final int MIPS_INS_TLTU = 444;
public static final int MIPS_INS_TNE = 445;
public static final int MIPS_INS_TNEI = 446;
public static final int MIPS_INS_TRUNC = 447;
public static final int MIPS_INS_VSHF = 448;
public static final int MIPS_INS_WAIT = 449;
public static final int MIPS_INS_WRDSP = 450;
public static final int MIPS_INS_WSBH = 451;
public static final int MIPS_INS_XOR = 452;
public static final int MIPS_INS_XORI = 453;
// some alias instructions
public static final int MIPS_INS_NOP = 453;
public static final int MIPS_INS_NEGU = 454;
public static final int MIPS_INS_MAX = 455;
public static final int MIPS_INS_NOP = 454;
public static final int MIPS_INS_NEGU = 455;
public static final int MIPS_INS_MAX = 456;
// Group of MIPS instructions
@ -659,6 +660,7 @@ public class Mips_const {
public static final int MIPS_GRP_NONANSFPMATH = 15;
public static final int MIPS_GRP_NOTFP64BIT = 16;
public static final int MIPS_GRP_NOTINMICROMIPS = 17;
public static final int MIPS_GRP_JUMP = 18;
public static final int MIPS_GRP_MAX = 19;
public static final int MIPS_GRP_NOTNACL = 18;
public static final int MIPS_GRP_JUMP = 19;
public static final int MIPS_GRP_MAX = 20;
}

@ -279,347 +279,349 @@ public class Ppc_const {
public static final int PPC_INS_FDIVS = 91;
public static final int PPC_INS_FMADD = 92;
public static final int PPC_INS_FMADDS = 93;
public static final int PPC_INS_FMSUB = 94;
public static final int PPC_INS_FMSUBS = 95;
public static final int PPC_INS_FMUL = 96;
public static final int PPC_INS_FMULS = 97;
public static final int PPC_INS_FNABS = 98;
public static final int PPC_INS_FNEG = 99;
public static final int PPC_INS_FNMADD = 100;
public static final int PPC_INS_FNMADDS = 101;
public static final int PPC_INS_FNMSUB = 102;
public static final int PPC_INS_FNMSUBS = 103;
public static final int PPC_INS_FRE = 104;
public static final int PPC_INS_FRES = 105;
public static final int PPC_INS_FRIM = 106;
public static final int PPC_INS_FRIN = 107;
public static final int PPC_INS_FRIP = 108;
public static final int PPC_INS_FRIZ = 109;
public static final int PPC_INS_FRSP = 110;
public static final int PPC_INS_FRSQRTE = 111;
public static final int PPC_INS_FRSQRTES = 112;
public static final int PPC_INS_FSEL = 113;
public static final int PPC_INS_FSQRT = 114;
public static final int PPC_INS_FSQRTS = 115;
public static final int PPC_INS_FSUB = 116;
public static final int PPC_INS_FSUBS = 117;
public static final int PPC_INS_ICBI = 118;
public static final int PPC_INS_ISEL = 119;
public static final int PPC_INS_ISYNC = 120;
public static final int PPC_INS_LA = 121;
public static final int PPC_INS_LBZ = 122;
public static final int PPC_INS_LBZU = 123;
public static final int PPC_INS_LBZUX = 124;
public static final int PPC_INS_LBZX = 125;
public static final int PPC_INS_LD = 126;
public static final int PPC_INS_LDARX = 127;
public static final int PPC_INS_LDBRX = 128;
public static final int PPC_INS_LDU = 129;
public static final int PPC_INS_LDUX = 130;
public static final int PPC_INS_LDX = 131;
public static final int PPC_INS_LFD = 132;
public static final int PPC_INS_LFDU = 133;
public static final int PPC_INS_LFDUX = 134;
public static final int PPC_INS_LFDX = 135;
public static final int PPC_INS_LFIWAX = 136;
public static final int PPC_INS_LFIWZX = 137;
public static final int PPC_INS_LFS = 138;
public static final int PPC_INS_LFSU = 139;
public static final int PPC_INS_LFSUX = 140;
public static final int PPC_INS_LFSX = 141;
public static final int PPC_INS_LHA = 142;
public static final int PPC_INS_LHAU = 143;
public static final int PPC_INS_LHAUX = 144;
public static final int PPC_INS_LHAX = 145;
public static final int PPC_INS_LHBRX = 146;
public static final int PPC_INS_LHZ = 147;
public static final int PPC_INS_LHZU = 148;
public static final int PPC_INS_LHZUX = 149;
public static final int PPC_INS_LHZX = 150;
public static final int PPC_INS_LI = 151;
public static final int PPC_INS_LIS = 152;
public static final int PPC_INS_LMW = 153;
public static final int PPC_INS_LVEBX = 154;
public static final int PPC_INS_LVEHX = 155;
public static final int PPC_INS_LVEWX = 156;
public static final int PPC_INS_LVSL = 157;
public static final int PPC_INS_LVSR = 158;
public static final int PPC_INS_LVX = 159;
public static final int PPC_INS_LVXL = 160;
public static final int PPC_INS_LWA = 161;
public static final int PPC_INS_LWARX = 162;
public static final int PPC_INS_LWAUX = 163;
public static final int PPC_INS_LWAX = 164;
public static final int PPC_INS_LWBRX = 165;
public static final int PPC_INS_LWZ = 166;
public static final int PPC_INS_LWZU = 167;
public static final int PPC_INS_LWZUX = 168;
public static final int PPC_INS_LWZX = 169;
public static final int PPC_INS_MCRF = 170;
public static final int PPC_INS_MFCR = 171;
public static final int PPC_INS_MFCTR = 172;
public static final int PPC_INS_MFFS = 173;
public static final int PPC_INS_MFLR = 174;
public static final int PPC_INS_MFMSR = 175;
public static final int PPC_INS_MFOCRF = 176;
public static final int PPC_INS_MFSPR = 177;
public static final int PPC_INS_MFTB = 178;
public static final int PPC_INS_MFVSCR = 179;
public static final int PPC_INS_MTCRF = 180;
public static final int PPC_INS_MTCTR = 181;
public static final int PPC_INS_MTFSB0 = 182;
public static final int PPC_INS_MTFSB1 = 183;
public static final int PPC_INS_MTFSF = 184;
public static final int PPC_INS_MTLR = 185;
public static final int PPC_INS_MTMSR = 186;
public static final int PPC_INS_MTMSRD = 187;
public static final int PPC_INS_MTOCRF = 188;
public static final int PPC_INS_MTSPR = 189;
public static final int PPC_INS_MTVSCR = 190;
public static final int PPC_INS_MULHD = 191;
public static final int PPC_INS_MULHDU = 192;
public static final int PPC_INS_MULHW = 193;
public static final int PPC_INS_MULHWU = 194;
public static final int PPC_INS_MULLD = 195;
public static final int PPC_INS_MULLI = 196;
public static final int PPC_INS_MULLW = 197;
public static final int PPC_INS_NAND = 198;
public static final int PPC_INS_NEG = 199;
public static final int PPC_INS_NOP = 200;
public static final int PPC_INS_ORI = 201;
public static final int PPC_INS_NOR = 202;
public static final int PPC_INS_OR = 203;
public static final int PPC_INS_ORC = 204;
public static final int PPC_INS_ORIS = 205;
public static final int PPC_INS_POPCNTD = 206;
public static final int PPC_INS_POPCNTW = 207;
public static final int PPC_INS_RLDCL = 208;
public static final int PPC_INS_RLDCR = 209;
public static final int PPC_INS_RLDIC = 210;
public static final int PPC_INS_RLDICL = 211;
public static final int PPC_INS_RLDICR = 212;
public static final int PPC_INS_RLDIMI = 213;
public static final int PPC_INS_RLWIMI = 214;
public static final int PPC_INS_RLWINM = 215;
public static final int PPC_INS_RLWNM = 216;
public static final int PPC_INS_SC = 217;
public static final int PPC_INS_SLBIA = 218;
public static final int PPC_INS_SLBIE = 219;
public static final int PPC_INS_SLBMFEE = 220;
public static final int PPC_INS_SLBMTE = 221;
public static final int PPC_INS_SLD = 222;
public static final int PPC_INS_SLW = 223;
public static final int PPC_INS_SRAD = 224;
public static final int PPC_INS_SRADI = 225;
public static final int PPC_INS_SRAW = 226;
public static final int PPC_INS_SRAWI = 227;
public static final int PPC_INS_SRD = 228;
public static final int PPC_INS_SRW = 229;
public static final int PPC_INS_STB = 230;
public static final int PPC_INS_STBU = 231;
public static final int PPC_INS_STBUX = 232;
public static final int PPC_INS_STBX = 233;
public static final int PPC_INS_STD = 234;
public static final int PPC_INS_STDBRX = 235;
public static final int PPC_INS_STDCX = 236;
public static final int PPC_INS_STDU = 237;
public static final int PPC_INS_STDUX = 238;
public static final int PPC_INS_STDX = 239;
public static final int PPC_INS_STFD = 240;
public static final int PPC_INS_STFDU = 241;
public static final int PPC_INS_STFDUX = 242;
public static final int PPC_INS_STFDX = 243;
public static final int PPC_INS_STFIWX = 244;
public static final int PPC_INS_STFS = 245;
public static final int PPC_INS_STFSU = 246;
public static final int PPC_INS_STFSUX = 247;
public static final int PPC_INS_STFSX = 248;
public static final int PPC_INS_STH = 249;
public static final int PPC_INS_STHBRX = 250;
public static final int PPC_INS_STHU = 251;
public static final int PPC_INS_STHUX = 252;
public static final int PPC_INS_STHX = 253;
public static final int PPC_INS_STMW = 254;
public static final int PPC_INS_STVEBX = 255;
public static final int PPC_INS_STVEHX = 256;
public static final int PPC_INS_STVEWX = 257;
public static final int PPC_INS_STVX = 258;
public static final int PPC_INS_STVXL = 259;
public static final int PPC_INS_STW = 260;
public static final int PPC_INS_STWBRX = 261;
public static final int PPC_INS_STWCX = 262;
public static final int PPC_INS_STWU = 263;
public static final int PPC_INS_STWUX = 264;
public static final int PPC_INS_STWX = 265;
public static final int PPC_INS_SUBF = 266;
public static final int PPC_INS_SUBFC = 267;
public static final int PPC_INS_SUBFE = 268;
public static final int PPC_INS_SUBFIC = 269;
public static final int PPC_INS_SUBFME = 270;
public static final int PPC_INS_SUBFZE = 271;
public static final int PPC_INS_SYNC = 272;
public static final int PPC_INS_TD = 273;
public static final int PPC_INS_TDI = 274;
public static final int PPC_INS_TLBIE = 275;
public static final int PPC_INS_TLBIEL = 276;
public static final int PPC_INS_TLBSYNC = 277;
public static final int PPC_INS_TRAP = 278;
public static final int PPC_INS_TW = 279;
public static final int PPC_INS_TWI = 280;
public static final int PPC_INS_VADDCUW = 281;
public static final int PPC_INS_VADDFP = 282;
public static final int PPC_INS_VADDSBS = 283;
public static final int PPC_INS_VADDSHS = 284;
public static final int PPC_INS_VADDSWS = 285;
public static final int PPC_INS_VADDUBM = 286;
public static final int PPC_INS_VADDUBS = 287;
public static final int PPC_INS_VADDUHM = 288;
public static final int PPC_INS_VADDUHS = 289;
public static final int PPC_INS_VADDUWM = 290;
public static final int PPC_INS_VADDUWS = 291;
public static final int PPC_INS_VAND = 292;
public static final int PPC_INS_VANDC = 293;
public static final int PPC_INS_VAVGSB = 294;
public static final int PPC_INS_VAVGSH = 295;
public static final int PPC_INS_VAVGSW = 296;
public static final int PPC_INS_VAVGUB = 297;
public static final int PPC_INS_VAVGUH = 298;
public static final int PPC_INS_VAVGUW = 299;
public static final int PPC_INS_VCFSX = 300;
public static final int PPC_INS_VCFUX = 301;
public static final int PPC_INS_VCMPBFP = 302;
public static final int PPC_INS_VCMPEQFP = 303;
public static final int PPC_INS_VCMPEQUB = 304;
public static final int PPC_INS_VCMPEQUH = 305;
public static final int PPC_INS_VCMPEQUW = 306;
public static final int PPC_INS_VCMPGEFP = 307;
public static final int PPC_INS_VCMPGTFP = 308;
public static final int PPC_INS_VCMPGTSB = 309;
public static final int PPC_INS_VCMPGTSH = 310;
public static final int PPC_INS_VCMPGTSW = 311;
public static final int PPC_INS_VCMPGTUB = 312;
public static final int PPC_INS_VCMPGTUH = 313;
public static final int PPC_INS_VCMPGTUW = 314;
public static final int PPC_INS_VCTSXS = 315;
public static final int PPC_INS_VCTUXS = 316;
public static final int PPC_INS_VEXPTEFP = 317;
public static final int PPC_INS_VLOGEFP = 318;
public static final int PPC_INS_VMADDFP = 319;
public static final int PPC_INS_VMAXFP = 320;
public static final int PPC_INS_VMAXSB = 321;
public static final int PPC_INS_VMAXSH = 322;
public static final int PPC_INS_VMAXSW = 323;
public static final int PPC_INS_VMAXUB = 324;
public static final int PPC_INS_VMAXUH = 325;
public static final int PPC_INS_VMAXUW = 326;
public static final int PPC_INS_VMHADDSHS = 327;
public static final int PPC_INS_VMHRADDSHS = 328;
public static final int PPC_INS_VMINFP = 329;
public static final int PPC_INS_VMINSB = 330;
public static final int PPC_INS_VMINSH = 331;
public static final int PPC_INS_VMINSW = 332;
public static final int PPC_INS_VMINUB = 333;
public static final int PPC_INS_VMINUH = 334;
public static final int PPC_INS_VMINUW = 335;
public static final int PPC_INS_VMLADDUHM = 336;
public static final int PPC_INS_VMRGHB = 337;
public static final int PPC_INS_VMRGHH = 338;
public static final int PPC_INS_VMRGHW = 339;
public static final int PPC_INS_VMRGLB = 340;
public static final int PPC_INS_VMRGLH = 341;
public static final int PPC_INS_VMRGLW = 342;
public static final int PPC_INS_VMSUMMBM = 343;
public static final int PPC_INS_VMSUMSHM = 344;
public static final int PPC_INS_VMSUMSHS = 345;
public static final int PPC_INS_VMSUMUBM = 346;
public static final int PPC_INS_VMSUMUHM = 347;
public static final int PPC_INS_VMSUMUHS = 348;
public static final int PPC_INS_VMULESB = 349;
public static final int PPC_INS_VMULESH = 350;
public static final int PPC_INS_VMULEUB = 351;
public static final int PPC_INS_VMULEUH = 352;
public static final int PPC_INS_VMULOSB = 353;
public static final int PPC_INS_VMULOSH = 354;
public static final int PPC_INS_VMULOUB = 355;
public static final int PPC_INS_VMULOUH = 356;
public static final int PPC_INS_VNMSUBFP = 357;
public static final int PPC_INS_VNOR = 358;
public static final int PPC_INS_VOR = 359;
public static final int PPC_INS_VPERM = 360;
public static final int PPC_INS_VPKPX = 361;
public static final int PPC_INS_VPKSHSS = 362;
public static final int PPC_INS_VPKSHUS = 363;
public static final int PPC_INS_VPKSWSS = 364;
public static final int PPC_INS_VPKSWUS = 365;
public static final int PPC_INS_VPKUHUM = 366;
public static final int PPC_INS_VPKUHUS = 367;
public static final int PPC_INS_VPKUWUM = 368;
public static final int PPC_INS_VPKUWUS = 369;
public static final int PPC_INS_VREFP = 370;
public static final int PPC_INS_VRFIM = 371;
public static final int PPC_INS_VRFIN = 372;
public static final int PPC_INS_VRFIP = 373;
public static final int PPC_INS_VRFIZ = 374;
public static final int PPC_INS_VRLB = 375;
public static final int PPC_INS_VRLH = 376;
public static final int PPC_INS_VRLW = 377;
public static final int PPC_INS_VRSQRTEFP = 378;
public static final int PPC_INS_VSEL = 379;
public static final int PPC_INS_VSL = 380;
public static final int PPC_INS_VSLB = 381;
public static final int PPC_INS_VSLDOI = 382;
public static final int PPC_INS_VSLH = 383;
public static final int PPC_INS_VSLO = 384;
public static final int PPC_INS_VSLW = 385;
public static final int PPC_INS_VSPLTB = 386;
public static final int PPC_INS_VSPLTH = 387;
public static final int PPC_INS_VSPLTISB = 388;
public static final int PPC_INS_VSPLTISH = 389;
public static final int PPC_INS_VSPLTISW = 390;
public static final int PPC_INS_VSPLTW = 391;
public static final int PPC_INS_VSR = 392;
public static final int PPC_INS_VSRAB = 393;
public static final int PPC_INS_VSRAH = 394;
public static final int PPC_INS_VSRAW = 395;
public static final int PPC_INS_VSRB = 396;
public static final int PPC_INS_VSRH = 397;
public static final int PPC_INS_VSRO = 398;
public static final int PPC_INS_VSRW = 399;
public static final int PPC_INS_VSUBCUW = 400;
public static final int PPC_INS_VSUBFP = 401;
public static final int PPC_INS_VSUBSBS = 402;
public static final int PPC_INS_VSUBSHS = 403;
public static final int PPC_INS_VSUBSWS = 404;
public static final int PPC_INS_VSUBUBM = 405;
public static final int PPC_INS_VSUBUBS = 406;
public static final int PPC_INS_VSUBUHM = 407;
public static final int PPC_INS_VSUBUHS = 408;
public static final int PPC_INS_VSUBUWM = 409;
public static final int PPC_INS_VSUBUWS = 410;
public static final int PPC_INS_VSUM2SWS = 411;
public static final int PPC_INS_VSUM4SBS = 412;
public static final int PPC_INS_VSUM4SHS = 413;
public static final int PPC_INS_VSUM4UBS = 414;
public static final int PPC_INS_VSUMSWS = 415;
public static final int PPC_INS_VUPKHPX = 416;
public static final int PPC_INS_VUPKHSB = 417;
public static final int PPC_INS_VUPKHSH = 418;
public static final int PPC_INS_VUPKLPX = 419;
public static final int PPC_INS_VUPKLSB = 420;
public static final int PPC_INS_VUPKLSH = 421;
public static final int PPC_INS_VXOR = 422;
public static final int PPC_INS_WAIT = 423;
public static final int PPC_INS_XOR = 424;
public static final int PPC_INS_XORI = 425;
public static final int PPC_INS_XORIS = 426;
public static final int PPC_INS_BC = 427;
public static final int PPC_INS_BCA = 428;
public static final int PPC_INS_BCCTR = 429;
public static final int PPC_INS_BCCTRL = 430;
public static final int PPC_INS_BCLA = 431;
public static final int PPC_INS_BCLR = 432;
public static final int PPC_INS_BCLRL = 433;
public static final int PPC_INS_MAX = 434;
public static final int PPC_INS_FMR = 94;
public static final int PPC_INS_FMSUB = 95;
public static final int PPC_INS_FMSUBS = 96;
public static final int PPC_INS_FMUL = 97;
public static final int PPC_INS_FMULS = 98;
public static final int PPC_INS_FNABS = 99;
public static final int PPC_INS_FNEG = 100;
public static final int PPC_INS_FNMADD = 101;
public static final int PPC_INS_FNMADDS = 102;
public static final int PPC_INS_FNMSUB = 103;
public static final int PPC_INS_FNMSUBS = 104;
public static final int PPC_INS_FRE = 105;
public static final int PPC_INS_FRES = 106;
public static final int PPC_INS_FRIM = 107;
public static final int PPC_INS_FRIN = 108;
public static final int PPC_INS_FRIP = 109;
public static final int PPC_INS_FRIZ = 110;
public static final int PPC_INS_FRSP = 111;
public static final int PPC_INS_FRSQRTE = 112;
public static final int PPC_INS_FRSQRTES = 113;
public static final int PPC_INS_FSEL = 114;
public static final int PPC_INS_FSQRT = 115;
public static final int PPC_INS_FSQRTS = 116;
public static final int PPC_INS_FSUB = 117;
public static final int PPC_INS_FSUBS = 118;
public static final int PPC_INS_ICBI = 119;
public static final int PPC_INS_ISEL = 120;
public static final int PPC_INS_ISYNC = 121;
public static final int PPC_INS_LA = 122;
public static final int PPC_INS_LBZ = 123;
public static final int PPC_INS_LBZU = 124;
public static final int PPC_INS_LBZUX = 125;
public static final int PPC_INS_LBZX = 126;
public static final int PPC_INS_LD = 127;
public static final int PPC_INS_LDARX = 128;
public static final int PPC_INS_LDBRX = 129;
public static final int PPC_INS_LDU = 130;
public static final int PPC_INS_LDUX = 131;
public static final int PPC_INS_LDX = 132;
public static final int PPC_INS_LFD = 133;
public static final int PPC_INS_LFDU = 134;
public static final int PPC_INS_LFDUX = 135;
public static final int PPC_INS_LFDX = 136;
public static final int PPC_INS_LFIWAX = 137;
public static final int PPC_INS_LFIWZX = 138;
public static final int PPC_INS_LFS = 139;
public static final int PPC_INS_LFSU = 140;
public static final int PPC_INS_LFSUX = 141;
public static final int PPC_INS_LFSX = 142;
public static final int PPC_INS_LHA = 143;
public static final int PPC_INS_LHAU = 144;
public static final int PPC_INS_LHAUX = 145;
public static final int PPC_INS_LHAX = 146;
public static final int PPC_INS_LHBRX = 147;
public static final int PPC_INS_LHZ = 148;
public static final int PPC_INS_LHZU = 149;
public static final int PPC_INS_LHZUX = 150;
public static final int PPC_INS_LHZX = 151;
public static final int PPC_INS_LI = 152;
public static final int PPC_INS_LIS = 153;
public static final int PPC_INS_LMW = 154;
public static final int PPC_INS_LVEBX = 155;
public static final int PPC_INS_LVEHX = 156;
public static final int PPC_INS_LVEWX = 157;
public static final int PPC_INS_LVSL = 158;
public static final int PPC_INS_LVSR = 159;
public static final int PPC_INS_LVX = 160;
public static final int PPC_INS_LVXL = 161;
public static final int PPC_INS_LWA = 162;
public static final int PPC_INS_LWARX = 163;
public static final int PPC_INS_LWAUX = 164;
public static final int PPC_INS_LWAX = 165;
public static final int PPC_INS_LWBRX = 166;
public static final int PPC_INS_LWZ = 167;
public static final int PPC_INS_LWZU = 168;
public static final int PPC_INS_LWZUX = 169;
public static final int PPC_INS_LWZX = 170;
public static final int PPC_INS_MCRF = 171;
public static final int PPC_INS_MFCR = 172;
public static final int PPC_INS_MFCTR = 173;
public static final int PPC_INS_MFFS = 174;
public static final int PPC_INS_MFLR = 175;
public static final int PPC_INS_MFMSR = 176;
public static final int PPC_INS_MFOCRF = 177;
public static final int PPC_INS_MFSPR = 178;
public static final int PPC_INS_MFTB = 179;
public static final int PPC_INS_MFVSCR = 180;
public static final int PPC_INS_MSYNC = 181;
public static final int PPC_INS_MTCRF = 182;
public static final int PPC_INS_MTCTR = 183;
public static final int PPC_INS_MTFSB0 = 184;
public static final int PPC_INS_MTFSB1 = 185;
public static final int PPC_INS_MTFSF = 186;
public static final int PPC_INS_MTLR = 187;
public static final int PPC_INS_MTMSR = 188;
public static final int PPC_INS_MTMSRD = 189;
public static final int PPC_INS_MTOCRF = 190;
public static final int PPC_INS_MTSPR = 191;
public static final int PPC_INS_MTVSCR = 192;
public static final int PPC_INS_MULHD = 193;
public static final int PPC_INS_MULHDU = 194;
public static final int PPC_INS_MULHW = 195;
public static final int PPC_INS_MULHWU = 196;
public static final int PPC_INS_MULLD = 197;
public static final int PPC_INS_MULLI = 198;
public static final int PPC_INS_MULLW = 199;
public static final int PPC_INS_NAND = 200;
public static final int PPC_INS_NEG = 201;
public static final int PPC_INS_NOP = 202;
public static final int PPC_INS_ORI = 203;
public static final int PPC_INS_NOR = 204;
public static final int PPC_INS_OR = 205;
public static final int PPC_INS_ORC = 206;
public static final int PPC_INS_ORIS = 207;
public static final int PPC_INS_POPCNTD = 208;
public static final int PPC_INS_POPCNTW = 209;
public static final int PPC_INS_RLDCL = 210;
public static final int PPC_INS_RLDCR = 211;
public static final int PPC_INS_RLDIC = 212;
public static final int PPC_INS_RLDICL = 213;
public static final int PPC_INS_RLDICR = 214;
public static final int PPC_INS_RLDIMI = 215;
public static final int PPC_INS_RLWIMI = 216;
public static final int PPC_INS_RLWINM = 217;
public static final int PPC_INS_RLWNM = 218;
public static final int PPC_INS_SC = 219;
public static final int PPC_INS_SLBIA = 220;
public static final int PPC_INS_SLBIE = 221;
public static final int PPC_INS_SLBMFEE = 222;
public static final int PPC_INS_SLBMTE = 223;
public static final int PPC_INS_SLD = 224;
public static final int PPC_INS_SLW = 225;
public static final int PPC_INS_SRAD = 226;
public static final int PPC_INS_SRADI = 227;
public static final int PPC_INS_SRAW = 228;
public static final int PPC_INS_SRAWI = 229;
public static final int PPC_INS_SRD = 230;
public static final int PPC_INS_SRW = 231;
public static final int PPC_INS_STB = 232;
public static final int PPC_INS_STBU = 233;
public static final int PPC_INS_STBUX = 234;
public static final int PPC_INS_STBX = 235;
public static final int PPC_INS_STD = 236;
public static final int PPC_INS_STDBRX = 237;
public static final int PPC_INS_STDCX = 238;
public static final int PPC_INS_STDU = 239;
public static final int PPC_INS_STDUX = 240;
public static final int PPC_INS_STDX = 241;
public static final int PPC_INS_STFD = 242;
public static final int PPC_INS_STFDU = 243;
public static final int PPC_INS_STFDUX = 244;
public static final int PPC_INS_STFDX = 245;
public static final int PPC_INS_STFIWX = 246;
public static final int PPC_INS_STFS = 247;
public static final int PPC_INS_STFSU = 248;
public static final int PPC_INS_STFSUX = 249;
public static final int PPC_INS_STFSX = 250;
public static final int PPC_INS_STH = 251;
public static final int PPC_INS_STHBRX = 252;
public static final int PPC_INS_STHU = 253;
public static final int PPC_INS_STHUX = 254;
public static final int PPC_INS_STHX = 255;
public static final int PPC_INS_STMW = 256;
public static final int PPC_INS_STVEBX = 257;
public static final int PPC_INS_STVEHX = 258;
public static final int PPC_INS_STVEWX = 259;
public static final int PPC_INS_STVX = 260;
public static final int PPC_INS_STVXL = 261;
public static final int PPC_INS_STW = 262;
public static final int PPC_INS_STWBRX = 263;
public static final int PPC_INS_STWCX = 264;
public static final int PPC_INS_STWU = 265;
public static final int PPC_INS_STWUX = 266;
public static final int PPC_INS_STWX = 267;
public static final int PPC_INS_SUBF = 268;
public static final int PPC_INS_SUBFC = 269;
public static final int PPC_INS_SUBFE = 270;
public static final int PPC_INS_SUBFIC = 271;
public static final int PPC_INS_SUBFME = 272;
public static final int PPC_INS_SUBFZE = 273;
public static final int PPC_INS_SYNC = 274;
public static final int PPC_INS_TD = 275;
public static final int PPC_INS_TDI = 276;
public static final int PPC_INS_TLBIE = 277;
public static final int PPC_INS_TLBIEL = 278;
public static final int PPC_INS_TLBSYNC = 279;
public static final int PPC_INS_TRAP = 280;
public static final int PPC_INS_TW = 281;
public static final int PPC_INS_TWI = 282;
public static final int PPC_INS_VADDCUW = 283;
public static final int PPC_INS_VADDFP = 284;
public static final int PPC_INS_VADDSBS = 285;
public static final int PPC_INS_VADDSHS = 286;
public static final int PPC_INS_VADDSWS = 287;
public static final int PPC_INS_VADDUBM = 288;
public static final int PPC_INS_VADDUBS = 289;
public static final int PPC_INS_VADDUHM = 290;
public static final int PPC_INS_VADDUHS = 291;
public static final int PPC_INS_VADDUWM = 292;
public static final int PPC_INS_VADDUWS = 293;
public static final int PPC_INS_VAND = 294;
public static final int PPC_INS_VANDC = 295;
public static final int PPC_INS_VAVGSB = 296;
public static final int PPC_INS_VAVGSH = 297;
public static final int PPC_INS_VAVGSW = 298;
public static final int PPC_INS_VAVGUB = 299;
public static final int PPC_INS_VAVGUH = 300;
public static final int PPC_INS_VAVGUW = 301;
public static final int PPC_INS_VCFSX = 302;
public static final int PPC_INS_VCFUX = 303;
public static final int PPC_INS_VCMPBFP = 304;
public static final int PPC_INS_VCMPEQFP = 305;
public static final int PPC_INS_VCMPEQUB = 306;
public static final int PPC_INS_VCMPEQUH = 307;
public static final int PPC_INS_VCMPEQUW = 308;
public static final int PPC_INS_VCMPGEFP = 309;
public static final int PPC_INS_VCMPGTFP = 310;
public static final int PPC_INS_VCMPGTSB = 311;
public static final int PPC_INS_VCMPGTSH = 312;
public static final int PPC_INS_VCMPGTSW = 313;
public static final int PPC_INS_VCMPGTUB = 314;
public static final int PPC_INS_VCMPGTUH = 315;
public static final int PPC_INS_VCMPGTUW = 316;
public static final int PPC_INS_VCTSXS = 317;
public static final int PPC_INS_VCTUXS = 318;
public static final int PPC_INS_VEXPTEFP = 319;
public static final int PPC_INS_VLOGEFP = 320;
public static final int PPC_INS_VMADDFP = 321;
public static final int PPC_INS_VMAXFP = 322;
public static final int PPC_INS_VMAXSB = 323;
public static final int PPC_INS_VMAXSH = 324;
public static final int PPC_INS_VMAXSW = 325;
public static final int PPC_INS_VMAXUB = 326;
public static final int PPC_INS_VMAXUH = 327;
public static final int PPC_INS_VMAXUW = 328;
public static final int PPC_INS_VMHADDSHS = 329;
public static final int PPC_INS_VMHRADDSHS = 330;
public static final int PPC_INS_VMINFP = 331;
public static final int PPC_INS_VMINSB = 332;
public static final int PPC_INS_VMINSH = 333;
public static final int PPC_INS_VMINSW = 334;
public static final int PPC_INS_VMINUB = 335;
public static final int PPC_INS_VMINUH = 336;
public static final int PPC_INS_VMINUW = 337;
public static final int PPC_INS_VMLADDUHM = 338;
public static final int PPC_INS_VMRGHB = 339;
public static final int PPC_INS_VMRGHH = 340;
public static final int PPC_INS_VMRGHW = 341;
public static final int PPC_INS_VMRGLB = 342;
public static final int PPC_INS_VMRGLH = 343;
public static final int PPC_INS_VMRGLW = 344;
public static final int PPC_INS_VMSUMMBM = 345;
public static final int PPC_INS_VMSUMSHM = 346;
public static final int PPC_INS_VMSUMSHS = 347;
public static final int PPC_INS_VMSUMUBM = 348;
public static final int PPC_INS_VMSUMUHM = 349;
public static final int PPC_INS_VMSUMUHS = 350;
public static final int PPC_INS_VMULESB = 351;
public static final int PPC_INS_VMULESH = 352;
public static final int PPC_INS_VMULEUB = 353;
public static final int PPC_INS_VMULEUH = 354;
public static final int PPC_INS_VMULOSB = 355;
public static final int PPC_INS_VMULOSH = 356;
public static final int PPC_INS_VMULOUB = 357;
public static final int PPC_INS_VMULOUH = 358;
public static final int PPC_INS_VNMSUBFP = 359;
public static final int PPC_INS_VNOR = 360;
public static final int PPC_INS_VOR = 361;
public static final int PPC_INS_VPERM = 362;
public static final int PPC_INS_VPKPX = 363;
public static final int PPC_INS_VPKSHSS = 364;
public static final int PPC_INS_VPKSHUS = 365;
public static final int PPC_INS_VPKSWSS = 366;
public static final int PPC_INS_VPKSWUS = 367;
public static final int PPC_INS_VPKUHUM = 368;
public static final int PPC_INS_VPKUHUS = 369;
public static final int PPC_INS_VPKUWUM = 370;
public static final int PPC_INS_VPKUWUS = 371;
public static final int PPC_INS_VREFP = 372;
public static final int PPC_INS_VRFIM = 373;
public static final int PPC_INS_VRFIN = 374;
public static final int PPC_INS_VRFIP = 375;
public static final int PPC_INS_VRFIZ = 376;
public static final int PPC_INS_VRLB = 377;
public static final int PPC_INS_VRLH = 378;
public static final int PPC_INS_VRLW = 379;
public static final int PPC_INS_VRSQRTEFP = 380;
public static final int PPC_INS_VSEL = 381;
public static final int PPC_INS_VSL = 382;
public static final int PPC_INS_VSLB = 383;
public static final int PPC_INS_VSLDOI = 384;
public static final int PPC_INS_VSLH = 385;
public static final int PPC_INS_VSLO = 386;
public static final int PPC_INS_VSLW = 387;
public static final int PPC_INS_VSPLTB = 388;
public static final int PPC_INS_VSPLTH = 389;
public static final int PPC_INS_VSPLTISB = 390;
public static final int PPC_INS_VSPLTISH = 391;
public static final int PPC_INS_VSPLTISW = 392;
public static final int PPC_INS_VSPLTW = 393;
public static final int PPC_INS_VSR = 394;
public static final int PPC_INS_VSRAB = 395;
public static final int PPC_INS_VSRAH = 396;
public static final int PPC_INS_VSRAW = 397;
public static final int PPC_INS_VSRB = 398;
public static final int PPC_INS_VSRH = 399;
public static final int PPC_INS_VSRO = 400;
public static final int PPC_INS_VSRW = 401;
public static final int PPC_INS_VSUBCUW = 402;
public static final int PPC_INS_VSUBFP = 403;
public static final int PPC_INS_VSUBSBS = 404;
public static final int PPC_INS_VSUBSHS = 405;
public static final int PPC_INS_VSUBSWS = 406;
public static final int PPC_INS_VSUBUBM = 407;
public static final int PPC_INS_VSUBUBS = 408;
public static final int PPC_INS_VSUBUHM = 409;
public static final int PPC_INS_VSUBUHS = 410;
public static final int PPC_INS_VSUBUWM = 411;
public static final int PPC_INS_VSUBUWS = 412;
public static final int PPC_INS_VSUM2SWS = 413;
public static final int PPC_INS_VSUM4SBS = 414;
public static final int PPC_INS_VSUM4SHS = 415;
public static final int PPC_INS_VSUM4UBS = 416;
public static final int PPC_INS_VSUMSWS = 417;
public static final int PPC_INS_VUPKHPX = 418;
public static final int PPC_INS_VUPKHSB = 419;
public static final int PPC_INS_VUPKHSH = 420;
public static final int PPC_INS_VUPKLPX = 421;
public static final int PPC_INS_VUPKLSB = 422;
public static final int PPC_INS_VUPKLSH = 423;
public static final int PPC_INS_VXOR = 424;
public static final int PPC_INS_WAIT = 425;
public static final int PPC_INS_XOR = 426;
public static final int PPC_INS_XORI = 427;
public static final int PPC_INS_XORIS = 428;
public static final int PPC_INS_BC = 429;
public static final int PPC_INS_BCA = 430;
public static final int PPC_INS_BCCTR = 431;
public static final int PPC_INS_BCCTRL = 432;
public static final int PPC_INS_BCLA = 433;
public static final int PPC_INS_BCLR = 434;
public static final int PPC_INS_BCLRL = 435;
public static final int PPC_INS_MAX = 436;
// Group of PPC instructions
@ -627,6 +629,8 @@ public class Ppc_const {
public static final int PPC_GRP_ALTIVEC = 1;
public static final int PPC_GRP_MODE32 = 2;
public static final int PPC_GRP_MODE64 = 3;
public static final int PPC_GRP_JUMP = 4;
public static final int PPC_GRP_MAX = 5;
public static final int PPC_GRP_BOOKE = 4;
public static final int PPC_GRP_NOTBOOKE = 5;
public static final int PPC_GRP_JUMP = 6;
public static final int PPC_GRP_MAX = 7;
}

File diff suppressed because it is too large Load Diff

@ -48,6 +48,15 @@ This directory contains some test code to show how to use Capstone API.
information out of disassembled instruction, such as address, mnemonic and
operand string.
- test_lite.py
Similarly to test.py, but this code shows how to use disasm_lite(), a lighter
method to disassemble binary. Unlike disasm() API (used by test.py), which returns
CsInsn objects, this API just returns tuples of (address, size, mnemonic, op_str).
The main reason for using this API is better performance: disasm_lite() is at least
20% faster than disasm(). Memory usage is also less. So if you just need basic
information out of disassembler, use disasm_lite() instead of disasm().
- test_detail.py:
This code shows how to access to architecture-neutral information in disassembled
instructions, such as implicit registers read/written, or groups of instructions

@ -1 +1 @@
from capstone import Cs, CsError, cs_disasm_quick, cs_version, cs_support, CS_API_MAJOR, CS_API_MINOR, CS_ARCH_ARM, CS_ARCH_ARM64, CS_ARCH_MIPS, CS_ARCH_X86, CS_ARCH_PPC, CS_ARCH_ALL, CS_MODE_LITTLE_ENDIAN, CS_MODE_ARM, CS_MODE_THUMB, CS_OPT_SYNTAX, CS_OPT_SYNTAX_DEFAULT, CS_OPT_SYNTAX_INTEL, CS_OPT_SYNTAX_ATT, CS_OPT_SYNTAX_NOREGNAME, CS_OPT_DETAIL, CS_OPT_ON, CS_OPT_OFF, CS_MODE_16, CS_MODE_32, CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_MODE_MICRO, CS_MODE_N64
from capstone import Cs, CsError, cs_disasm_quick, cs_disasm_lite, cs_version, cs_support, CS_API_MAJOR, CS_API_MINOR, CS_ARCH_ARM, CS_ARCH_ARM64, CS_ARCH_MIPS, CS_ARCH_X86, CS_ARCH_PPC, CS_ARCH_ALL, CS_MODE_LITTLE_ENDIAN, CS_MODE_ARM, CS_MODE_THUMB, CS_OPT_SYNTAX, CS_OPT_SYNTAX_DEFAULT, CS_OPT_SYNTAX_INTEL, CS_OPT_SYNTAX_ATT, CS_OPT_SYNTAX_NOREGNAME, CS_OPT_DETAIL, CS_OPT_ON, CS_OPT_OFF, CS_MODE_16, CS_MODE_32, CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_MODE_MICRO, CS_MODE_N64, CS_SUPPORT_DIET

@ -49,13 +49,18 @@ __all__ = [
'CS_ERR_MODE',
'CS_ERR_OPTION',
'CS_ERR_DETAIL',
'CS_ERR_VERSION',
'CS_ERR_MEMSETUP',
'CS_ERR_DIET',
'CS_SUPPORT_DIET',
]
# Capstone C interface
# API version
CS_API_MAJOR = 2
CS_API_MINOR = 0
CS_API_MINOR = 1
# architectures
CS_ARCH_ARM = 0
@ -100,7 +105,12 @@ CS_ERR_CSH = 4 # Invalid csh argument: cs_close(), cs_errno(), cs_option()
CS_ERR_MODE = 5 # Invalid/unsupported mode: cs_open()
CS_ERR_OPTION = 6 # Invalid/unsupported option: cs_option()
CS_ERR_DETAIL = 7 # Invalid/unsupported option: cs_option()
CS_ERR_MEMSETUP = 8
CS_ERR_VERSION = 9 # Unsupported version (bindings)
CS_ERR_DIET = 10 # Information irrelevant in diet engine
# query id for cs_support()
CS_SUPPORT_DIET = CS_ARCH_ALL+1
import ctypes, ctypes.util, sys
from os.path import split, join, dirname
@ -219,8 +229,8 @@ def cs_version():
return (major.value, minor.value, combined)
def cs_support(arch):
return _cs.cs_support(arch)
def cs_support(query):
return _cs.cs_support(query)
# dummy class resembling Cs class, just for cs_disasm_quick()
@ -231,8 +241,16 @@ class _dummy_cs(object):
self.arch = arch
# quick & dirty Python function to disasm raw binary code
# Quick & dirty Python function to disasm raw binary code
# This function return CsInsn objects
# NOTE: you might want to use more efficient Cs class & its methods.
def cs_disasm_quick(arch, mode, code, offset, count = 0):
# verify version compatibility with the core before doing anything
(major, minor, _combined) = cs_version()
if major != CS_API_MAJOR or minor != CS_API_MINOR:
# our binding version is different from the core's API version
raise CsError(CS_ERR_VERSION)
csh = ctypes.c_size_t()
status = _cs.cs_open(arch, mode, ctypes.byref(csh))
if status != CS_ERR_OK:
@ -257,6 +275,47 @@ def cs_disasm_quick(arch, mode, code, offset, count = 0):
raise CsError(status)
# Another quick, but lighter function to disasm raw binary code.
# This function is faster than cs_disasm_quick() around 20% because
# cs_disasm_lite() only return tuples of (address, size, mnemonic, op_str),
# rather than CsInsn objects.
# NOTE: you might want to use more efficient Cs class & its methods.
def cs_disasm_lite(arch, mode, code, offset, count = 0):
# verify version compatibility with the core before doing anything
(major, minor, _combined) = cs_version()
if major != CS_API_MAJOR or minor != CS_API_MINOR:
# our binding version is different from the core's API version
raise CsError(CS_ERR_VERSION)
if cs_support(CS_SUPPORT_DIET):
# Diet engine cannot provide @mnemonic & @op_str
raise CsError(CS_ERR_DIET)
csh = ctypes.c_size_t()
status = _cs.cs_open(arch, mode, ctypes.byref(csh))
if status != CS_ERR_OK:
raise CsError(status)
all_insn = ctypes.POINTER(_cs_insn)()
res = _cs.cs_disasm_ex(csh, code, len(code), offset, count, ctypes.byref(all_insn))
if res > 0:
for i in xrange(res):
insn = all_insn[i]
yield (insn.address, insn.size, insn.mnemonic, insn.op_str)
_cs.cs_free(all_insn, res)
else:
status = _cs.cs_errno(csh)
if status != CS_ERR_OK:
raise CsError(status)
return
yield
status = _cs.cs_close(csh)
if status != CS_ERR_OK:
raise CsError(status)
# Python-style class to disasm code
class CsInsn(object):
def __init__(self, cs, all_info):
@ -281,14 +340,26 @@ class CsInsn(object):
@property
def mnemonic(self):
if self._cs._diet:
# Diet engine cannot provide @mnemonic
raise CsError(CS_ERR_DIET)
return self._raw.mnemonic
@property
def op_str(self):
if self._cs._diet:
# Diet engine cannot provide @op_str
raise CsError(CS_ERR_DIET)
return self._raw.op_str
@property
def regs_read(self):
if self._cs._diet:
# Diet engine cannot provide @regs_read
raise CsError(CS_ERR_DIET)
if self._cs._detail:
detail = self._raw.detail.contents
return detail.regs_read[:detail.regs_read_count]
@ -297,6 +368,10 @@ class CsInsn(object):
@property
def regs_write(self):
if self._cs._diet:
# Diet engine cannot provide @regs_write
raise CsError(CS_ERR_DIET)
if self._cs._detail:
detail = self._raw.detail.contents
return detail.regs_write[:detail.regs_write_count]
@ -305,6 +380,10 @@ class CsInsn(object):
@property
def groups(self):
if self._cs._diet:
# Diet engine cannot provide @groups
raise CsError(CS_ERR_DIET)
if self._cs._detail:
detail = self._raw.detail.contents
return detail.groups[:detail.groups_count]
@ -350,22 +429,42 @@ class CsInsn(object):
# get the register name, given the register ID
def reg_name(self, reg_id):
if self._cs._diet:
# Diet engine cannot provide register name
raise CsError(CS_ERR_DIET)
return _cs.cs_reg_name(self._cs.csh, reg_id)
# get the instruction string
def insn_name(self):
if self._cs._diet:
# Diet engine cannot provide instruction name
raise CsError(CS_ERR_DIET)
return _cs.cs_insn_name(self._cs.csh, self.id)
# verify if this insn belong to group with id as @group_id
def group(self, group_id):
if self._cs._diet:
# Diet engine cannot provide group information
raise CsError(CS_ERR_DIET)
return group_id in self.groups
# verify if this instruction implicitly read register @reg_id
def reg_read(self, reg_id):
if self._cs._diet:
# Diet engine cannot provide regs_read information
raise CsError(CS_ERR_DIET)
return reg_id in self.regs_read
# verify if this instruction implicitly modified register @reg_id
def reg_write(self, reg_id):
if self._cs._diet:
# Diet engine cannot provide regs_write information
raise CsError(CS_ERR_DIET)
return reg_id in self.regs_write
# return number of operands having same operand type @op_type
@ -388,6 +487,13 @@ class CsInsn(object):
class Cs(object):
def __init__(self, arch, mode):
# verify version compatibility with the core before doing anything
(major, minor, _combined) = cs_version()
if major != CS_API_MAJOR or minor != CS_API_MINOR:
self.csh = None
# our binding version is different from the core's API version
raise CsError(CS_ERR_VERSION)
self.arch, self._mode = arch, mode
self.csh = ctypes.c_size_t()
status = _cs.cs_open(arch, mode, ctypes.byref(self.csh))
@ -409,6 +515,7 @@ class Cs(object):
self._syntax = None
self._detail = False # by default, do not produce instruction details
self._diet = cs_support(CS_SUPPORT_DIET)
def __del__(self):
if self.csh:
@ -419,6 +526,11 @@ class Cs(object):
#def option(self, opt_type, opt_value):
# return _cs.cs_option(self.csh, opt_type, opt_value)
@property
def diet(self):
return self._diet
@property
def syntax(self):
return self._syntax
@ -435,6 +547,11 @@ class Cs(object):
def detail(self):
return self._detail
def support(self, query):
return cs_support(query)
@detail.setter
def detail(self, opt): # opt is boolean type, so must be either 'True' or 'False'
if opt == False:
@ -458,6 +575,8 @@ class Cs(object):
# save mode
self._mode = opt
# Disassemble binary & return disassembled instructions in CsInsn objects
def disasm(self, code, offset, count = 0):
all_insn = ctypes.POINTER(_cs_insn)()
res = _cs.cs_disasm_ex(self.csh, code, len(code), offset, count, ctypes.byref(all_insn))
@ -472,3 +591,26 @@ class Cs(object):
return
yield
# Light function to disassemble binary. This is about 20% faster than disasm() because
# unlike disasm(), disasm_lite() only return tuples of (address, size, mnemonic, op_str),
# rather than CsInsn objects.
def disasm_lite(self, code, offset, count = 0):
if self._diet:
# Diet engine cannot provide @mnemonic & @op_str
raise CsError(CS_ERR_DIET)
all_insn = ctypes.POINTER(_cs_insn)()
res = _cs.cs_disasm_ex(self.csh, code, len(code), offset, count, ctypes.byref(all_insn))
if res > 0:
for i in xrange(res):
insn = all_insn[i]
yield (insn.address, insn.size, insn.mnemonic, insn.op_str)
_cs.cs_free(all_insn, res)
else:
status = _cs.cs_errno(self.csh)
if status != CS_ERR_OK:
raise CsError(status)
return
yield

@ -286,355 +286,356 @@ MIPS_INS_DINSM = 105
MIPS_INS_DINSU = 106
MIPS_INS_DIV_S = 107
MIPS_INS_DIV_U = 108
MIPS_INS_DMFC0 = 109
MIPS_INS_DMFC1 = 110
MIPS_INS_DMFC2 = 111
MIPS_INS_DMTC0 = 112
MIPS_INS_DMTC1 = 113
MIPS_INS_DMTC2 = 114
MIPS_INS_DMULT = 115
MIPS_INS_DMULTU = 116
MIPS_INS_DOTP_S = 117
MIPS_INS_DOTP_U = 118
MIPS_INS_DPADD_S = 119
MIPS_INS_DPADD_U = 120
MIPS_INS_DPAQX_SA = 121
MIPS_INS_DPAQX_S = 122
MIPS_INS_DPAQ_SA = 123
MIPS_INS_DPAQ_S = 124
MIPS_INS_DPAU = 125
MIPS_INS_DPAX = 126
MIPS_INS_DPA = 127
MIPS_INS_DPSQX_SA = 128
MIPS_INS_DPSQX_S = 129
MIPS_INS_DPSQ_SA = 130
MIPS_INS_DPSQ_S = 131
MIPS_INS_DPSUB_S = 132
MIPS_INS_DPSUB_U = 133
MIPS_INS_DPSU = 134
MIPS_INS_DPSX = 135
MIPS_INS_DPS = 136
MIPS_INS_DROTR = 137
MIPS_INS_DROTR32 = 138
MIPS_INS_DROTRV = 139
MIPS_INS_DSBH = 140
MIPS_INS_DDIV = 141
MIPS_INS_DSHD = 142
MIPS_INS_DSLL = 143
MIPS_INS_DSLL32 = 144
MIPS_INS_DSLLV = 145
MIPS_INS_DSRA = 146
MIPS_INS_DSRA32 = 147
MIPS_INS_DSRAV = 148
MIPS_INS_DSRL = 149
MIPS_INS_DSRL32 = 150
MIPS_INS_DSRLV = 151
MIPS_INS_DSUBU = 152
MIPS_INS_DDIVU = 153
MIPS_INS_DIV = 154
MIPS_INS_DIVU = 155
MIPS_INS_EI = 156
MIPS_INS_ERET = 157
MIPS_INS_EXT = 158
MIPS_INS_EXTP = 159
MIPS_INS_EXTPDP = 160
MIPS_INS_EXTPDPV = 161
MIPS_INS_EXTPV = 162
MIPS_INS_EXTRV_RS = 163
MIPS_INS_EXTRV_R = 164
MIPS_INS_EXTRV_S = 165
MIPS_INS_EXTRV = 166
MIPS_INS_EXTR_RS = 167
MIPS_INS_EXTR_R = 168
MIPS_INS_EXTR_S = 169
MIPS_INS_EXTR = 170
MIPS_INS_ABS = 171
MIPS_INS_FADD = 172
MIPS_INS_FCAF = 173
MIPS_INS_FCEQ = 174
MIPS_INS_FCLASS = 175
MIPS_INS_FCLE = 176
MIPS_INS_FCLT = 177
MIPS_INS_FCNE = 178
MIPS_INS_FCOR = 179
MIPS_INS_FCUEQ = 180
MIPS_INS_FCULE = 181
MIPS_INS_FCULT = 182
MIPS_INS_FCUNE = 183
MIPS_INS_FCUN = 184
MIPS_INS_FDIV = 185
MIPS_INS_FEXDO = 186
MIPS_INS_FEXP2 = 187
MIPS_INS_FEXUPL = 188
MIPS_INS_FEXUPR = 189
MIPS_INS_FFINT_S = 190
MIPS_INS_FFINT_U = 191
MIPS_INS_FFQL = 192
MIPS_INS_FFQR = 193
MIPS_INS_FILL = 194
MIPS_INS_FLOG2 = 195
MIPS_INS_FLOOR = 196
MIPS_INS_FMADD = 197
MIPS_INS_FMAX_A = 198
MIPS_INS_FMAX = 199
MIPS_INS_FMIN_A = 200
MIPS_INS_FMIN = 201
MIPS_INS_MOV = 202
MIPS_INS_FMSUB = 203
MIPS_INS_FMUL = 204
MIPS_INS_MUL = 205
MIPS_INS_NEG = 206
MIPS_INS_FRCP = 207
MIPS_INS_FRINT = 208
MIPS_INS_FRSQRT = 209
MIPS_INS_FSAF = 210
MIPS_INS_FSEQ = 211
MIPS_INS_FSLE = 212
MIPS_INS_FSLT = 213
MIPS_INS_FSNE = 214
MIPS_INS_FSOR = 215
MIPS_INS_FSQRT = 216
MIPS_INS_SQRT = 217
MIPS_INS_FSUB = 218
MIPS_INS_SUB = 219
MIPS_INS_FSUEQ = 220
MIPS_INS_FSULE = 221
MIPS_INS_FSULT = 222
MIPS_INS_FSUNE = 223
MIPS_INS_FSUN = 224
MIPS_INS_FTINT_S = 225
MIPS_INS_FTINT_U = 226
MIPS_INS_FTQ = 227
MIPS_INS_FTRUNC_S = 228
MIPS_INS_FTRUNC_U = 229
MIPS_INS_HADD_S = 230
MIPS_INS_HADD_U = 231
MIPS_INS_HSUB_S = 232
MIPS_INS_HSUB_U = 233
MIPS_INS_ILVEV = 234
MIPS_INS_ILVL = 235
MIPS_INS_ILVOD = 236
MIPS_INS_ILVR = 237
MIPS_INS_INS = 238
MIPS_INS_INSERT = 239
MIPS_INS_INSV = 240
MIPS_INS_INSVE = 241
MIPS_INS_J = 242
MIPS_INS_JAL = 243
MIPS_INS_JALR = 244
MIPS_INS_JR = 245
MIPS_INS_JRC = 246
MIPS_INS_JALRC = 247
MIPS_INS_LB = 248
MIPS_INS_LBUX = 249
MIPS_INS_LBU = 250
MIPS_INS_LD = 251
MIPS_INS_LDC1 = 252
MIPS_INS_LDC2 = 253
MIPS_INS_LDI = 254
MIPS_INS_LDL = 255
MIPS_INS_LDR = 256
MIPS_INS_LDXC1 = 257
MIPS_INS_LH = 258
MIPS_INS_LHX = 259
MIPS_INS_LHU = 260
MIPS_INS_LL = 261
MIPS_INS_LLD = 262
MIPS_INS_LSA = 263
MIPS_INS_LUXC1 = 264
MIPS_INS_LUI = 265
MIPS_INS_LW = 266
MIPS_INS_LWC1 = 267
MIPS_INS_LWC2 = 268
MIPS_INS_LWL = 269
MIPS_INS_LWR = 270
MIPS_INS_LWX = 271
MIPS_INS_LWXC1 = 272
MIPS_INS_LWU = 273
MIPS_INS_LI = 274
MIPS_INS_MADD = 275
MIPS_INS_MADDR_Q = 276
MIPS_INS_MADDU = 277
MIPS_INS_MADDV = 278
MIPS_INS_MADD_Q = 279
MIPS_INS_MAQ_SA = 280
MIPS_INS_MAQ_S = 281
MIPS_INS_MAXI_S = 282
MIPS_INS_MAXI_U = 283
MIPS_INS_MAX_A = 284
MIPS_INS_MAX_S = 285
MIPS_INS_MAX_U = 286
MIPS_INS_MFC0 = 287
MIPS_INS_MFC1 = 288
MIPS_INS_MFC2 = 289
MIPS_INS_MFHC1 = 290
MIPS_INS_MFHI = 291
MIPS_INS_MFLO = 292
MIPS_INS_MINI_S = 293
MIPS_INS_MINI_U = 294
MIPS_INS_MIN_A = 295
MIPS_INS_MIN_S = 296
MIPS_INS_MIN_U = 297
MIPS_INS_MODSUB = 298
MIPS_INS_MOD_S = 299
MIPS_INS_MOD_U = 300
MIPS_INS_MOVE = 301
MIPS_INS_MOVF = 302
MIPS_INS_MOVN = 303
MIPS_INS_MOVT = 304
MIPS_INS_MOVZ = 305
MIPS_INS_MSUB = 306
MIPS_INS_MSUBR_Q = 307
MIPS_INS_MSUBU = 308
MIPS_INS_MSUBV = 309
MIPS_INS_MSUB_Q = 310
MIPS_INS_MTC0 = 311
MIPS_INS_MTC1 = 312
MIPS_INS_MTC2 = 313
MIPS_INS_MTHC1 = 314
MIPS_INS_MTHI = 315
MIPS_INS_MTHLIP = 316
MIPS_INS_MTLO = 317
MIPS_INS_MULEQ_S = 318
MIPS_INS_MULEU_S = 319
MIPS_INS_MULQ_RS = 320
MIPS_INS_MULQ_S = 321
MIPS_INS_MULR_Q = 322
MIPS_INS_MULSAQ_S = 323
MIPS_INS_MULSA = 324
MIPS_INS_MULT = 325
MIPS_INS_MULTU = 326
MIPS_INS_MULV = 327
MIPS_INS_MUL_Q = 328
MIPS_INS_MUL_S = 329
MIPS_INS_NLOC = 330
MIPS_INS_NLZC = 331
MIPS_INS_NMADD = 332
MIPS_INS_NMSUB = 333
MIPS_INS_NOR = 334
MIPS_INS_NORI = 335
MIPS_INS_NOT = 336
MIPS_INS_OR = 337
MIPS_INS_ORI = 338
MIPS_INS_PACKRL = 339
MIPS_INS_PCKEV = 340
MIPS_INS_PCKOD = 341
MIPS_INS_PCNT = 342
MIPS_INS_PICK = 343
MIPS_INS_PRECEQU = 344
MIPS_INS_PRECEQ = 345
MIPS_INS_PRECEU = 346
MIPS_INS_PRECRQU_S = 347
MIPS_INS_PRECRQ = 348
MIPS_INS_PRECRQ_RS = 349
MIPS_INS_PRECR = 350
MIPS_INS_PRECR_SRA = 351
MIPS_INS_PRECR_SRA_R = 352
MIPS_INS_PREPEND = 353
MIPS_INS_RADDU = 354
MIPS_INS_RDDSP = 355
MIPS_INS_RDHWR = 356
MIPS_INS_REPLV = 357
MIPS_INS_REPL = 358
MIPS_INS_ROTR = 359
MIPS_INS_ROTRV = 360
MIPS_INS_ROUND = 361
MIPS_INS_SAT_S = 362
MIPS_INS_SAT_U = 363
MIPS_INS_SB = 364
MIPS_INS_SC = 365
MIPS_INS_SCD = 366
MIPS_INS_SD = 367
MIPS_INS_SDC1 = 368
MIPS_INS_SDC2 = 369
MIPS_INS_SDL = 370
MIPS_INS_SDR = 371
MIPS_INS_SDXC1 = 372
MIPS_INS_SEB = 373
MIPS_INS_SEH = 374
MIPS_INS_SH = 375
MIPS_INS_SHF = 376
MIPS_INS_SHILO = 377
MIPS_INS_SHILOV = 378
MIPS_INS_SHLLV = 379
MIPS_INS_SHLLV_S = 380
MIPS_INS_SHLL = 381
MIPS_INS_SHLL_S = 382
MIPS_INS_SHRAV = 383
MIPS_INS_SHRAV_R = 384
MIPS_INS_SHRA = 385
MIPS_INS_SHRA_R = 386
MIPS_INS_SHRLV = 387
MIPS_INS_SHRL = 388
MIPS_INS_SLDI = 389
MIPS_INS_SLD = 390
MIPS_INS_SLL = 391
MIPS_INS_SLLI = 392
MIPS_INS_SLLV = 393
MIPS_INS_SLT = 394
MIPS_INS_SLTI = 395
MIPS_INS_SLTIU = 396
MIPS_INS_SLTU = 397
MIPS_INS_SPLATI = 398
MIPS_INS_SPLAT = 399
MIPS_INS_SRA = 400
MIPS_INS_SRAI = 401
MIPS_INS_SRARI = 402
MIPS_INS_SRAR = 403
MIPS_INS_SRAV = 404
MIPS_INS_SRL = 405
MIPS_INS_SRLI = 406
MIPS_INS_SRLRI = 407
MIPS_INS_SRLR = 408
MIPS_INS_SRLV = 409
MIPS_INS_ST = 410
MIPS_INS_SUBQH = 411
MIPS_INS_SUBQH_R = 412
MIPS_INS_SUBQ = 413
MIPS_INS_SUBQ_S = 414
MIPS_INS_SUBSUS_U = 415
MIPS_INS_SUBSUU_S = 416
MIPS_INS_SUBS_S = 417
MIPS_INS_SUBS_U = 418
MIPS_INS_SUBUH = 419
MIPS_INS_SUBUH_R = 420
MIPS_INS_SUBU = 421
MIPS_INS_SUBU_S = 422
MIPS_INS_SUBVI = 423
MIPS_INS_SUBV = 424
MIPS_INS_SUXC1 = 425
MIPS_INS_SW = 426
MIPS_INS_SWC1 = 427
MIPS_INS_SWC2 = 428
MIPS_INS_SWL = 429
MIPS_INS_SWR = 430
MIPS_INS_SWXC1 = 431
MIPS_INS_SYNC = 432
MIPS_INS_SYSCALL = 433
MIPS_INS_TEQ = 434
MIPS_INS_TEQI = 435
MIPS_INS_TGE = 436
MIPS_INS_TGEI = 437
MIPS_INS_TGEIU = 438
MIPS_INS_TGEU = 439
MIPS_INS_TLT = 440
MIPS_INS_TLTI = 441
MIPS_INS_TLTIU = 442
MIPS_INS_TLTU = 443
MIPS_INS_TNE = 444
MIPS_INS_TNEI = 445
MIPS_INS_TRUNC = 446
MIPS_INS_VSHF = 447
MIPS_INS_WAIT = 448
MIPS_INS_WRDSP = 449
MIPS_INS_WSBH = 450
MIPS_INS_XOR = 451
MIPS_INS_XORI = 452
MIPS_INS_DLSA = 109
MIPS_INS_DMFC0 = 110
MIPS_INS_DMFC1 = 111
MIPS_INS_DMFC2 = 112
MIPS_INS_DMTC0 = 113
MIPS_INS_DMTC1 = 114
MIPS_INS_DMTC2 = 115
MIPS_INS_DMULT = 116
MIPS_INS_DMULTU = 117
MIPS_INS_DOTP_S = 118
MIPS_INS_DOTP_U = 119
MIPS_INS_DPADD_S = 120
MIPS_INS_DPADD_U = 121
MIPS_INS_DPAQX_SA = 122
MIPS_INS_DPAQX_S = 123
MIPS_INS_DPAQ_SA = 124
MIPS_INS_DPAQ_S = 125
MIPS_INS_DPAU = 126
MIPS_INS_DPAX = 127
MIPS_INS_DPA = 128
MIPS_INS_DPSQX_SA = 129
MIPS_INS_DPSQX_S = 130
MIPS_INS_DPSQ_SA = 131
MIPS_INS_DPSQ_S = 132
MIPS_INS_DPSUB_S = 133
MIPS_INS_DPSUB_U = 134
MIPS_INS_DPSU = 135
MIPS_INS_DPSX = 136
MIPS_INS_DPS = 137
MIPS_INS_DROTR = 138
MIPS_INS_DROTR32 = 139
MIPS_INS_DROTRV = 140
MIPS_INS_DSBH = 141
MIPS_INS_DDIV = 142
MIPS_INS_DSHD = 143
MIPS_INS_DSLL = 144
MIPS_INS_DSLL32 = 145
MIPS_INS_DSLLV = 146
MIPS_INS_DSRA = 147
MIPS_INS_DSRA32 = 148
MIPS_INS_DSRAV = 149
MIPS_INS_DSRL = 150
MIPS_INS_DSRL32 = 151
MIPS_INS_DSRLV = 152
MIPS_INS_DSUBU = 153
MIPS_INS_DDIVU = 154
MIPS_INS_DIV = 155
MIPS_INS_DIVU = 156
MIPS_INS_EI = 157
MIPS_INS_ERET = 158
MIPS_INS_EXT = 159
MIPS_INS_EXTP = 160
MIPS_INS_EXTPDP = 161
MIPS_INS_EXTPDPV = 162
MIPS_INS_EXTPV = 163
MIPS_INS_EXTRV_RS = 164
MIPS_INS_EXTRV_R = 165
MIPS_INS_EXTRV_S = 166
MIPS_INS_EXTRV = 167
MIPS_INS_EXTR_RS = 168
MIPS_INS_EXTR_R = 169
MIPS_INS_EXTR_S = 170
MIPS_INS_EXTR = 171
MIPS_INS_ABS = 172
MIPS_INS_FADD = 173
MIPS_INS_FCAF = 174
MIPS_INS_FCEQ = 175
MIPS_INS_FCLASS = 176
MIPS_INS_FCLE = 177
MIPS_INS_FCLT = 178
MIPS_INS_FCNE = 179
MIPS_INS_FCOR = 180
MIPS_INS_FCUEQ = 181
MIPS_INS_FCULE = 182
MIPS_INS_FCULT = 183
MIPS_INS_FCUNE = 184
MIPS_INS_FCUN = 185
MIPS_INS_FDIV = 186
MIPS_INS_FEXDO = 187
MIPS_INS_FEXP2 = 188
MIPS_INS_FEXUPL = 189
MIPS_INS_FEXUPR = 190
MIPS_INS_FFINT_S = 191
MIPS_INS_FFINT_U = 192
MIPS_INS_FFQL = 193
MIPS_INS_FFQR = 194
MIPS_INS_FILL = 195
MIPS_INS_FLOG2 = 196
MIPS_INS_FLOOR = 197
MIPS_INS_FMADD = 198
MIPS_INS_FMAX_A = 199
MIPS_INS_FMAX = 200
MIPS_INS_FMIN_A = 201
MIPS_INS_FMIN = 202
MIPS_INS_MOV = 203
MIPS_INS_FMSUB = 204
MIPS_INS_FMUL = 205
MIPS_INS_MUL = 206
MIPS_INS_NEG = 207
MIPS_INS_FRCP = 208
MIPS_INS_FRINT = 209
MIPS_INS_FRSQRT = 210
MIPS_INS_FSAF = 211
MIPS_INS_FSEQ = 212
MIPS_INS_FSLE = 213
MIPS_INS_FSLT = 214
MIPS_INS_FSNE = 215
MIPS_INS_FSOR = 216
MIPS_INS_FSQRT = 217
MIPS_INS_SQRT = 218
MIPS_INS_FSUB = 219
MIPS_INS_SUB = 220
MIPS_INS_FSUEQ = 221
MIPS_INS_FSULE = 222
MIPS_INS_FSULT = 223
MIPS_INS_FSUNE = 224
MIPS_INS_FSUN = 225
MIPS_INS_FTINT_S = 226
MIPS_INS_FTINT_U = 227
MIPS_INS_FTQ = 228
MIPS_INS_FTRUNC_S = 229
MIPS_INS_FTRUNC_U = 230
MIPS_INS_HADD_S = 231
MIPS_INS_HADD_U = 232
MIPS_INS_HSUB_S = 233
MIPS_INS_HSUB_U = 234
MIPS_INS_ILVEV = 235
MIPS_INS_ILVL = 236
MIPS_INS_ILVOD = 237
MIPS_INS_ILVR = 238
MIPS_INS_INS = 239
MIPS_INS_INSERT = 240
MIPS_INS_INSV = 241
MIPS_INS_INSVE = 242
MIPS_INS_J = 243
MIPS_INS_JAL = 244
MIPS_INS_JALR = 245
MIPS_INS_JR = 246
MIPS_INS_JRC = 247
MIPS_INS_JALRC = 248
MIPS_INS_LB = 249
MIPS_INS_LBUX = 250
MIPS_INS_LBU = 251
MIPS_INS_LD = 252
MIPS_INS_LDC1 = 253
MIPS_INS_LDC2 = 254
MIPS_INS_LDI = 255
MIPS_INS_LDL = 256
MIPS_INS_LDR = 257
MIPS_INS_LDXC1 = 258
MIPS_INS_LH = 259
MIPS_INS_LHX = 260
MIPS_INS_LHU = 261
MIPS_INS_LL = 262
MIPS_INS_LLD = 263
MIPS_INS_LSA = 264
MIPS_INS_LUXC1 = 265
MIPS_INS_LUI = 266
MIPS_INS_LW = 267
MIPS_INS_LWC1 = 268
MIPS_INS_LWC2 = 269
MIPS_INS_LWL = 270
MIPS_INS_LWR = 271
MIPS_INS_LWU = 272
MIPS_INS_LWX = 273
MIPS_INS_LWXC1 = 274
MIPS_INS_LI = 275
MIPS_INS_MADD = 276
MIPS_INS_MADDR_Q = 277
MIPS_INS_MADDU = 278
MIPS_INS_MADDV = 279
MIPS_INS_MADD_Q = 280
MIPS_INS_MAQ_SA = 281
MIPS_INS_MAQ_S = 282
MIPS_INS_MAXI_S = 283
MIPS_INS_MAXI_U = 284
MIPS_INS_MAX_A = 285
MIPS_INS_MAX_S = 286
MIPS_INS_MAX_U = 287
MIPS_INS_MFC0 = 288
MIPS_INS_MFC1 = 289
MIPS_INS_MFC2 = 290
MIPS_INS_MFHC1 = 291
MIPS_INS_MFHI = 292
MIPS_INS_MFLO = 293
MIPS_INS_MINI_S = 294
MIPS_INS_MINI_U = 295
MIPS_INS_MIN_A = 296
MIPS_INS_MIN_S = 297
MIPS_INS_MIN_U = 298
MIPS_INS_MODSUB = 299
MIPS_INS_MOD_S = 300
MIPS_INS_MOD_U = 301
MIPS_INS_MOVE = 302
MIPS_INS_MOVF = 303
MIPS_INS_MOVN = 304
MIPS_INS_MOVT = 305
MIPS_INS_MOVZ = 306
MIPS_INS_MSUB = 307
MIPS_INS_MSUBR_Q = 308
MIPS_INS_MSUBU = 309
MIPS_INS_MSUBV = 310
MIPS_INS_MSUB_Q = 311
MIPS_INS_MTC0 = 312
MIPS_INS_MTC1 = 313
MIPS_INS_MTC2 = 314
MIPS_INS_MTHC1 = 315
MIPS_INS_MTHI = 316
MIPS_INS_MTHLIP = 317
MIPS_INS_MTLO = 318
MIPS_INS_MULEQ_S = 319
MIPS_INS_MULEU_S = 320
MIPS_INS_MULQ_RS = 321
MIPS_INS_MULQ_S = 322
MIPS_INS_MULR_Q = 323
MIPS_INS_MULSAQ_S = 324
MIPS_INS_MULSA = 325
MIPS_INS_MULT = 326
MIPS_INS_MULTU = 327
MIPS_INS_MULV = 328
MIPS_INS_MUL_Q = 329
MIPS_INS_MUL_S = 330
MIPS_INS_NLOC = 331
MIPS_INS_NLZC = 332
MIPS_INS_NMADD = 333
MIPS_INS_NMSUB = 334
MIPS_INS_NOR = 335
MIPS_INS_NORI = 336
MIPS_INS_NOT = 337
MIPS_INS_OR = 338
MIPS_INS_ORI = 339
MIPS_INS_PACKRL = 340
MIPS_INS_PCKEV = 341
MIPS_INS_PCKOD = 342
MIPS_INS_PCNT = 343
MIPS_INS_PICK = 344
MIPS_INS_PRECEQU = 345
MIPS_INS_PRECEQ = 346
MIPS_INS_PRECEU = 347
MIPS_INS_PRECRQU_S = 348
MIPS_INS_PRECRQ = 349
MIPS_INS_PRECRQ_RS = 350
MIPS_INS_PRECR = 351
MIPS_INS_PRECR_SRA = 352
MIPS_INS_PRECR_SRA_R = 353
MIPS_INS_PREPEND = 354
MIPS_INS_RADDU = 355
MIPS_INS_RDDSP = 356
MIPS_INS_RDHWR = 357
MIPS_INS_REPLV = 358
MIPS_INS_REPL = 359
MIPS_INS_ROTR = 360
MIPS_INS_ROTRV = 361
MIPS_INS_ROUND = 362
MIPS_INS_SAT_S = 363
MIPS_INS_SAT_U = 364
MIPS_INS_SB = 365
MIPS_INS_SC = 366
MIPS_INS_SCD = 367
MIPS_INS_SD = 368
MIPS_INS_SDC1 = 369
MIPS_INS_SDC2 = 370
MIPS_INS_SDL = 371
MIPS_INS_SDR = 372
MIPS_INS_SDXC1 = 373
MIPS_INS_SEB = 374
MIPS_INS_SEH = 375
MIPS_INS_SH = 376
MIPS_INS_SHF = 377
MIPS_INS_SHILO = 378
MIPS_INS_SHILOV = 379
MIPS_INS_SHLLV = 380
MIPS_INS_SHLLV_S = 381
MIPS_INS_SHLL = 382
MIPS_INS_SHLL_S = 383
MIPS_INS_SHRAV = 384
MIPS_INS_SHRAV_R = 385
MIPS_INS_SHRA = 386
MIPS_INS_SHRA_R = 387
MIPS_INS_SHRLV = 388
MIPS_INS_SHRL = 389
MIPS_INS_SLDI = 390
MIPS_INS_SLD = 391
MIPS_INS_SLL = 392
MIPS_INS_SLLI = 393
MIPS_INS_SLLV = 394
MIPS_INS_SLT = 395
MIPS_INS_SLTI = 396
MIPS_INS_SLTIU = 397
MIPS_INS_SLTU = 398
MIPS_INS_SPLATI = 399
MIPS_INS_SPLAT = 400
MIPS_INS_SRA = 401
MIPS_INS_SRAI = 402
MIPS_INS_SRARI = 403
MIPS_INS_SRAR = 404
MIPS_INS_SRAV = 405
MIPS_INS_SRL = 406
MIPS_INS_SRLI = 407
MIPS_INS_SRLRI = 408
MIPS_INS_SRLR = 409
MIPS_INS_SRLV = 410
MIPS_INS_ST = 411
MIPS_INS_SUBQH = 412
MIPS_INS_SUBQH_R = 413
MIPS_INS_SUBQ = 414
MIPS_INS_SUBQ_S = 415
MIPS_INS_SUBSUS_U = 416
MIPS_INS_SUBSUU_S = 417
MIPS_INS_SUBS_S = 418
MIPS_INS_SUBS_U = 419
MIPS_INS_SUBUH = 420
MIPS_INS_SUBUH_R = 421
MIPS_INS_SUBU = 422
MIPS_INS_SUBU_S = 423
MIPS_INS_SUBVI = 424
MIPS_INS_SUBV = 425
MIPS_INS_SUXC1 = 426
MIPS_INS_SW = 427
MIPS_INS_SWC1 = 428
MIPS_INS_SWC2 = 429
MIPS_INS_SWL = 430
MIPS_INS_SWR = 431
MIPS_INS_SWXC1 = 432
MIPS_INS_SYNC = 433
MIPS_INS_SYSCALL = 434
MIPS_INS_TEQ = 435
MIPS_INS_TEQI = 436
MIPS_INS_TGE = 437
MIPS_INS_TGEI = 438
MIPS_INS_TGEIU = 439
MIPS_INS_TGEU = 440
MIPS_INS_TLT = 441
MIPS_INS_TLTI = 442
MIPS_INS_TLTIU = 443
MIPS_INS_TLTU = 444
MIPS_INS_TNE = 445
MIPS_INS_TNEI = 446
MIPS_INS_TRUNC = 447
MIPS_INS_VSHF = 448
MIPS_INS_WAIT = 449
MIPS_INS_WRDSP = 450
MIPS_INS_WSBH = 451
MIPS_INS_XOR = 452
MIPS_INS_XORI = 453
# some alias instructions
MIPS_INS_NOP = 453
MIPS_INS_NEGU = 454
MIPS_INS_MAX = 455
MIPS_INS_NOP = 454
MIPS_INS_NEGU = 455
MIPS_INS_MAX = 456
# Group of MIPS instructions
@ -656,5 +657,6 @@ MIPS_GRP_FP64BIT = 14
MIPS_GRP_NONANSFPMATH = 15
MIPS_GRP_NOTFP64BIT = 16
MIPS_GRP_NOTINMICROMIPS = 17
MIPS_GRP_JUMP = 18
MIPS_GRP_MAX = 19
MIPS_GRP_NOTNACL = 18
MIPS_GRP_JUMP = 19
MIPS_GRP_MAX = 20

@ -276,347 +276,349 @@ PPC_INS_FDIV = 90
PPC_INS_FDIVS = 91
PPC_INS_FMADD = 92
PPC_INS_FMADDS = 93
PPC_INS_FMSUB = 94
PPC_INS_FMSUBS = 95
PPC_INS_FMUL = 96
PPC_INS_FMULS = 97
PPC_INS_FNABS = 98
PPC_INS_FNEG = 99
PPC_INS_FNMADD = 100
PPC_INS_FNMADDS = 101
PPC_INS_FNMSUB = 102
PPC_INS_FNMSUBS = 103
PPC_INS_FRE = 104
PPC_INS_FRES = 105
PPC_INS_FRIM = 106
PPC_INS_FRIN = 107
PPC_INS_FRIP = 108
PPC_INS_FRIZ = 109
PPC_INS_FRSP = 110
PPC_INS_FRSQRTE = 111
PPC_INS_FRSQRTES = 112
PPC_INS_FSEL = 113
PPC_INS_FSQRT = 114
PPC_INS_FSQRTS = 115
PPC_INS_FSUB = 116
PPC_INS_FSUBS = 117
PPC_INS_ICBI = 118
PPC_INS_ISEL = 119
PPC_INS_ISYNC = 120
PPC_INS_LA = 121
PPC_INS_LBZ = 122
PPC_INS_LBZU = 123
PPC_INS_LBZUX = 124
PPC_INS_LBZX = 125
PPC_INS_LD = 126
PPC_INS_LDARX = 127
PPC_INS_LDBRX = 128
PPC_INS_LDU = 129
PPC_INS_LDUX = 130
PPC_INS_LDX = 131
PPC_INS_LFD = 132
PPC_INS_LFDU = 133
PPC_INS_LFDUX = 134
PPC_INS_LFDX = 135
PPC_INS_LFIWAX = 136
PPC_INS_LFIWZX = 137
PPC_INS_LFS = 138
PPC_INS_LFSU = 139
PPC_INS_LFSUX = 140
PPC_INS_LFSX = 141
PPC_INS_LHA = 142
PPC_INS_LHAU = 143
PPC_INS_LHAUX = 144
PPC_INS_LHAX = 145
PPC_INS_LHBRX = 146
PPC_INS_LHZ = 147
PPC_INS_LHZU = 148
PPC_INS_LHZUX = 149
PPC_INS_LHZX = 150
PPC_INS_LI = 151
PPC_INS_LIS = 152
PPC_INS_LMW = 153
PPC_INS_LVEBX = 154
PPC_INS_LVEHX = 155
PPC_INS_LVEWX = 156
PPC_INS_LVSL = 157
PPC_INS_LVSR = 158
PPC_INS_LVX = 159
PPC_INS_LVXL = 160
PPC_INS_LWA = 161
PPC_INS_LWARX = 162
PPC_INS_LWAUX = 163
PPC_INS_LWAX = 164
PPC_INS_LWBRX = 165
PPC_INS_LWZ = 166
PPC_INS_LWZU = 167
PPC_INS_LWZUX = 168
PPC_INS_LWZX = 169
PPC_INS_MCRF = 170
PPC_INS_MFCR = 171
PPC_INS_MFCTR = 172
PPC_INS_MFFS = 173
PPC_INS_MFLR = 174
PPC_INS_MFMSR = 175
PPC_INS_MFOCRF = 176
PPC_INS_MFSPR = 177
PPC_INS_MFTB = 178
PPC_INS_MFVSCR = 179
PPC_INS_MTCRF = 180
PPC_INS_MTCTR = 181
PPC_INS_MTFSB0 = 182
PPC_INS_MTFSB1 = 183
PPC_INS_MTFSF = 184
PPC_INS_MTLR = 185
PPC_INS_MTMSR = 186
PPC_INS_MTMSRD = 187
PPC_INS_MTOCRF = 188
PPC_INS_MTSPR = 189
PPC_INS_MTVSCR = 190
PPC_INS_MULHD = 191
PPC_INS_MULHDU = 192
PPC_INS_MULHW = 193
PPC_INS_MULHWU = 194
PPC_INS_MULLD = 195
PPC_INS_MULLI = 196
PPC_INS_MULLW = 197
PPC_INS_NAND = 198
PPC_INS_NEG = 199
PPC_INS_NOP = 200
PPC_INS_ORI = 201
PPC_INS_NOR = 202
PPC_INS_OR = 203
PPC_INS_ORC = 204
PPC_INS_ORIS = 205
PPC_INS_POPCNTD = 206
PPC_INS_POPCNTW = 207
PPC_INS_RLDCL = 208
PPC_INS_RLDCR = 209
PPC_INS_RLDIC = 210
PPC_INS_RLDICL = 211
PPC_INS_RLDICR = 212
PPC_INS_RLDIMI = 213
PPC_INS_RLWIMI = 214
PPC_INS_RLWINM = 215
PPC_INS_RLWNM = 216
PPC_INS_SC = 217
PPC_INS_SLBIA = 218
PPC_INS_SLBIE = 219
PPC_INS_SLBMFEE = 220
PPC_INS_SLBMTE = 221
PPC_INS_SLD = 222
PPC_INS_SLW = 223
PPC_INS_SRAD = 224
PPC_INS_SRADI = 225
PPC_INS_SRAW = 226
PPC_INS_SRAWI = 227
PPC_INS_SRD = 228
PPC_INS_SRW = 229
PPC_INS_STB = 230
PPC_INS_STBU = 231
PPC_INS_STBUX = 232
PPC_INS_STBX = 233
PPC_INS_STD = 234
PPC_INS_STDBRX = 235
PPC_INS_STDCX = 236
PPC_INS_STDU = 237
PPC_INS_STDUX = 238
PPC_INS_STDX = 239
PPC_INS_STFD = 240
PPC_INS_STFDU = 241
PPC_INS_STFDUX = 242
PPC_INS_STFDX = 243
PPC_INS_STFIWX = 244
PPC_INS_STFS = 245
PPC_INS_STFSU = 246
PPC_INS_STFSUX = 247
PPC_INS_STFSX = 248
PPC_INS_STH = 249
PPC_INS_STHBRX = 250
PPC_INS_STHU = 251
PPC_INS_STHUX = 252
PPC_INS_STHX = 253
PPC_INS_STMW = 254
PPC_INS_STVEBX = 255
PPC_INS_STVEHX = 256
PPC_INS_STVEWX = 257
PPC_INS_STVX = 258
PPC_INS_STVXL = 259
PPC_INS_STW = 260
PPC_INS_STWBRX = 261
PPC_INS_STWCX = 262
PPC_INS_STWU = 263
PPC_INS_STWUX = 264
PPC_INS_STWX = 265
PPC_INS_SUBF = 266
PPC_INS_SUBFC = 267
PPC_INS_SUBFE = 268
PPC_INS_SUBFIC = 269
PPC_INS_SUBFME = 270
PPC_INS_SUBFZE = 271
PPC_INS_SYNC = 272
PPC_INS_TD = 273
PPC_INS_TDI = 274
PPC_INS_TLBIE = 275
PPC_INS_TLBIEL = 276
PPC_INS_TLBSYNC = 277
PPC_INS_TRAP = 278
PPC_INS_TW = 279
PPC_INS_TWI = 280
PPC_INS_VADDCUW = 281
PPC_INS_VADDFP = 282
PPC_INS_VADDSBS = 283
PPC_INS_VADDSHS = 284
PPC_INS_VADDSWS = 285
PPC_INS_VADDUBM = 286
PPC_INS_VADDUBS = 287
PPC_INS_VADDUHM = 288
PPC_INS_VADDUHS = 289
PPC_INS_VADDUWM = 290
PPC_INS_VADDUWS = 291
PPC_INS_VAND = 292
PPC_INS_VANDC = 293
PPC_INS_VAVGSB = 294
PPC_INS_VAVGSH = 295
PPC_INS_VAVGSW = 296
PPC_INS_VAVGUB = 297
PPC_INS_VAVGUH = 298
PPC_INS_VAVGUW = 299
PPC_INS_VCFSX = 300
PPC_INS_VCFUX = 301
PPC_INS_VCMPBFP = 302
PPC_INS_VCMPEQFP = 303
PPC_INS_VCMPEQUB = 304
PPC_INS_VCMPEQUH = 305
PPC_INS_VCMPEQUW = 306
PPC_INS_VCMPGEFP = 307
PPC_INS_VCMPGTFP = 308
PPC_INS_VCMPGTSB = 309
PPC_INS_VCMPGTSH = 310
PPC_INS_VCMPGTSW = 311
PPC_INS_VCMPGTUB = 312
PPC_INS_VCMPGTUH = 313
PPC_INS_VCMPGTUW = 314
PPC_INS_VCTSXS = 315
PPC_INS_VCTUXS = 316
PPC_INS_VEXPTEFP = 317
PPC_INS_VLOGEFP = 318
PPC_INS_VMADDFP = 319
PPC_INS_VMAXFP = 320
PPC_INS_VMAXSB = 321
PPC_INS_VMAXSH = 322
PPC_INS_VMAXSW = 323
PPC_INS_VMAXUB = 324
PPC_INS_VMAXUH = 325
PPC_INS_VMAXUW = 326
PPC_INS_VMHADDSHS = 327
PPC_INS_VMHRADDSHS = 328
PPC_INS_VMINFP = 329
PPC_INS_VMINSB = 330
PPC_INS_VMINSH = 331
PPC_INS_VMINSW = 332
PPC_INS_VMINUB = 333
PPC_INS_VMINUH = 334
PPC_INS_VMINUW = 335
PPC_INS_VMLADDUHM = 336
PPC_INS_VMRGHB = 337
PPC_INS_VMRGHH = 338
PPC_INS_VMRGHW = 339
PPC_INS_VMRGLB = 340
PPC_INS_VMRGLH = 341
PPC_INS_VMRGLW = 342
PPC_INS_VMSUMMBM = 343
PPC_INS_VMSUMSHM = 344
PPC_INS_VMSUMSHS = 345
PPC_INS_VMSUMUBM = 346
PPC_INS_VMSUMUHM = 347
PPC_INS_VMSUMUHS = 348
PPC_INS_VMULESB = 349
PPC_INS_VMULESH = 350
PPC_INS_VMULEUB = 351
PPC_INS_VMULEUH = 352
PPC_INS_VMULOSB = 353
PPC_INS_VMULOSH = 354
PPC_INS_VMULOUB = 355
PPC_INS_VMULOUH = 356
PPC_INS_VNMSUBFP = 357
PPC_INS_VNOR = 358
PPC_INS_VOR = 359
PPC_INS_VPERM = 360
PPC_INS_VPKPX = 361
PPC_INS_VPKSHSS = 362
PPC_INS_VPKSHUS = 363
PPC_INS_VPKSWSS = 364
PPC_INS_VPKSWUS = 365
PPC_INS_VPKUHUM = 366
PPC_INS_VPKUHUS = 367
PPC_INS_VPKUWUM = 368
PPC_INS_VPKUWUS = 369
PPC_INS_VREFP = 370
PPC_INS_VRFIM = 371
PPC_INS_VRFIN = 372
PPC_INS_VRFIP = 373
PPC_INS_VRFIZ = 374
PPC_INS_VRLB = 375
PPC_INS_VRLH = 376
PPC_INS_VRLW = 377
PPC_INS_VRSQRTEFP = 378
PPC_INS_VSEL = 379
PPC_INS_VSL = 380
PPC_INS_VSLB = 381
PPC_INS_VSLDOI = 382
PPC_INS_VSLH = 383
PPC_INS_VSLO = 384
PPC_INS_VSLW = 385
PPC_INS_VSPLTB = 386
PPC_INS_VSPLTH = 387
PPC_INS_VSPLTISB = 388
PPC_INS_VSPLTISH = 389
PPC_INS_VSPLTISW = 390
PPC_INS_VSPLTW = 391
PPC_INS_VSR = 392
PPC_INS_VSRAB = 393
PPC_INS_VSRAH = 394
PPC_INS_VSRAW = 395
PPC_INS_VSRB = 396
PPC_INS_VSRH = 397
PPC_INS_VSRO = 398
PPC_INS_VSRW = 399
PPC_INS_VSUBCUW = 400
PPC_INS_VSUBFP = 401
PPC_INS_VSUBSBS = 402
PPC_INS_VSUBSHS = 403
PPC_INS_VSUBSWS = 404
PPC_INS_VSUBUBM = 405
PPC_INS_VSUBUBS = 406
PPC_INS_VSUBUHM = 407
PPC_INS_VSUBUHS = 408
PPC_INS_VSUBUWM = 409
PPC_INS_VSUBUWS = 410
PPC_INS_VSUM2SWS = 411
PPC_INS_VSUM4SBS = 412
PPC_INS_VSUM4SHS = 413
PPC_INS_VSUM4UBS = 414
PPC_INS_VSUMSWS = 415
PPC_INS_VUPKHPX = 416
PPC_INS_VUPKHSB = 417
PPC_INS_VUPKHSH = 418
PPC_INS_VUPKLPX = 419
PPC_INS_VUPKLSB = 420
PPC_INS_VUPKLSH = 421
PPC_INS_VXOR = 422
PPC_INS_WAIT = 423
PPC_INS_XOR = 424
PPC_INS_XORI = 425
PPC_INS_XORIS = 426
PPC_INS_BC = 427
PPC_INS_BCA = 428
PPC_INS_BCCTR = 429
PPC_INS_BCCTRL = 430
PPC_INS_BCLA = 431
PPC_INS_BCLR = 432
PPC_INS_BCLRL = 433
PPC_INS_MAX = 434
PPC_INS_FMR = 94
PPC_INS_FMSUB = 95
PPC_INS_FMSUBS = 96
PPC_INS_FMUL = 97
PPC_INS_FMULS = 98
PPC_INS_FNABS = 99
PPC_INS_FNEG = 100
PPC_INS_FNMADD = 101
PPC_INS_FNMADDS = 102
PPC_INS_FNMSUB = 103
PPC_INS_FNMSUBS = 104
PPC_INS_FRE = 105
PPC_INS_FRES = 106
PPC_INS_FRIM = 107
PPC_INS_FRIN = 108
PPC_INS_FRIP = 109
PPC_INS_FRIZ = 110
PPC_INS_FRSP = 111
PPC_INS_FRSQRTE = 112
PPC_INS_FRSQRTES = 113
PPC_INS_FSEL = 114
PPC_INS_FSQRT = 115
PPC_INS_FSQRTS = 116
PPC_INS_FSUB = 117
PPC_INS_FSUBS = 118
PPC_INS_ICBI = 119
PPC_INS_ISEL = 120
PPC_INS_ISYNC = 121
PPC_INS_LA = 122
PPC_INS_LBZ = 123
PPC_INS_LBZU = 124
PPC_INS_LBZUX = 125
PPC_INS_LBZX = 126
PPC_INS_LD = 127
PPC_INS_LDARX = 128
PPC_INS_LDBRX = 129
PPC_INS_LDU = 130
PPC_INS_LDUX = 131
PPC_INS_LDX = 132
PPC_INS_LFD = 133
PPC_INS_LFDU = 134
PPC_INS_LFDUX = 135
PPC_INS_LFDX = 136
PPC_INS_LFIWAX = 137
PPC_INS_LFIWZX = 138
PPC_INS_LFS = 139
PPC_INS_LFSU = 140
PPC_INS_LFSUX = 141
PPC_INS_LFSX = 142
PPC_INS_LHA = 143
PPC_INS_LHAU = 144
PPC_INS_LHAUX = 145
PPC_INS_LHAX = 146
PPC_INS_LHBRX = 147
PPC_INS_LHZ = 148
PPC_INS_LHZU = 149
PPC_INS_LHZUX = 150
PPC_INS_LHZX = 151
PPC_INS_LI = 152
PPC_INS_LIS = 153
PPC_INS_LMW = 154
PPC_INS_LVEBX = 155
PPC_INS_LVEHX = 156
PPC_INS_LVEWX = 157
PPC_INS_LVSL = 158
PPC_INS_LVSR = 159
PPC_INS_LVX = 160
PPC_INS_LVXL = 161
PPC_INS_LWA = 162
PPC_INS_LWARX = 163
PPC_INS_LWAUX = 164
PPC_INS_LWAX = 165
PPC_INS_LWBRX = 166
PPC_INS_LWZ = 167
PPC_INS_LWZU = 168
PPC_INS_LWZUX = 169
PPC_INS_LWZX = 170
PPC_INS_MCRF = 171
PPC_INS_MFCR = 172
PPC_INS_MFCTR = 173
PPC_INS_MFFS = 174
PPC_INS_MFLR = 175
PPC_INS_MFMSR = 176
PPC_INS_MFOCRF = 177
PPC_INS_MFSPR = 178
PPC_INS_MFTB = 179
PPC_INS_MFVSCR = 180
PPC_INS_MSYNC = 181
PPC_INS_MTCRF = 182
PPC_INS_MTCTR = 183
PPC_INS_MTFSB0 = 184
PPC_INS_MTFSB1 = 185
PPC_INS_MTFSF = 186
PPC_INS_MTLR = 187
PPC_INS_MTMSR = 188
PPC_INS_MTMSRD = 189
PPC_INS_MTOCRF = 190
PPC_INS_MTSPR = 191
PPC_INS_MTVSCR = 192
PPC_INS_MULHD = 193
PPC_INS_MULHDU = 194
PPC_INS_MULHW = 195
PPC_INS_MULHWU = 196
PPC_INS_MULLD = 197
PPC_INS_MULLI = 198
PPC_INS_MULLW = 199
PPC_INS_NAND = 200
PPC_INS_NEG = 201
PPC_INS_NOP = 202
PPC_INS_ORI = 203
PPC_INS_NOR = 204
PPC_INS_OR = 205
PPC_INS_ORC = 206
PPC_INS_ORIS = 207
PPC_INS_POPCNTD = 208
PPC_INS_POPCNTW = 209
PPC_INS_RLDCL = 210
PPC_INS_RLDCR = 211
PPC_INS_RLDIC = 212
PPC_INS_RLDICL = 213
PPC_INS_RLDICR = 214
PPC_INS_RLDIMI = 215
PPC_INS_RLWIMI = 216
PPC_INS_RLWINM = 217
PPC_INS_RLWNM = 218
PPC_INS_SC = 219
PPC_INS_SLBIA = 220
PPC_INS_SLBIE = 221
PPC_INS_SLBMFEE = 222
PPC_INS_SLBMTE = 223
PPC_INS_SLD = 224
PPC_INS_SLW = 225
PPC_INS_SRAD = 226
PPC_INS_SRADI = 227
PPC_INS_SRAW = 228
PPC_INS_SRAWI = 229
PPC_INS_SRD = 230
PPC_INS_SRW = 231
PPC_INS_STB = 232
PPC_INS_STBU = 233
PPC_INS_STBUX = 234
PPC_INS_STBX = 235
PPC_INS_STD = 236
PPC_INS_STDBRX = 237
PPC_INS_STDCX = 238
PPC_INS_STDU = 239
PPC_INS_STDUX = 240
PPC_INS_STDX = 241
PPC_INS_STFD = 242
PPC_INS_STFDU = 243
PPC_INS_STFDUX = 244
PPC_INS_STFDX = 245
PPC_INS_STFIWX = 246
PPC_INS_STFS = 247
PPC_INS_STFSU = 248
PPC_INS_STFSUX = 249
PPC_INS_STFSX = 250
PPC_INS_STH = 251
PPC_INS_STHBRX = 252
PPC_INS_STHU = 253
PPC_INS_STHUX = 254
PPC_INS_STHX = 255
PPC_INS_STMW = 256
PPC_INS_STVEBX = 257
PPC_INS_STVEHX = 258
PPC_INS_STVEWX = 259
PPC_INS_STVX = 260
PPC_INS_STVXL = 261
PPC_INS_STW = 262
PPC_INS_STWBRX = 263
PPC_INS_STWCX = 264
PPC_INS_STWU = 265
PPC_INS_STWUX = 266
PPC_INS_STWX = 267
PPC_INS_SUBF = 268
PPC_INS_SUBFC = 269
PPC_INS_SUBFE = 270
PPC_INS_SUBFIC = 271
PPC_INS_SUBFME = 272
PPC_INS_SUBFZE = 273
PPC_INS_SYNC = 274
PPC_INS_TD = 275
PPC_INS_TDI = 276
PPC_INS_TLBIE = 277
PPC_INS_TLBIEL = 278
PPC_INS_TLBSYNC = 279
PPC_INS_TRAP = 280
PPC_INS_TW = 281
PPC_INS_TWI = 282
PPC_INS_VADDCUW = 283
PPC_INS_VADDFP = 284
PPC_INS_VADDSBS = 285
PPC_INS_VADDSHS = 286
PPC_INS_VADDSWS = 287
PPC_INS_VADDUBM = 288
PPC_INS_VADDUBS = 289
PPC_INS_VADDUHM = 290
PPC_INS_VADDUHS = 291
PPC_INS_VADDUWM = 292
PPC_INS_VADDUWS = 293
PPC_INS_VAND = 294
PPC_INS_VANDC = 295
PPC_INS_VAVGSB = 296
PPC_INS_VAVGSH = 297
PPC_INS_VAVGSW = 298
PPC_INS_VAVGUB = 299
PPC_INS_VAVGUH = 300
PPC_INS_VAVGUW = 301
PPC_INS_VCFSX = 302
PPC_INS_VCFUX = 303
PPC_INS_VCMPBFP = 304
PPC_INS_VCMPEQFP = 305
PPC_INS_VCMPEQUB = 306
PPC_INS_VCMPEQUH = 307
PPC_INS_VCMPEQUW = 308
PPC_INS_VCMPGEFP = 309
PPC_INS_VCMPGTFP = 310
PPC_INS_VCMPGTSB = 311
PPC_INS_VCMPGTSH = 312
PPC_INS_VCMPGTSW = 313
PPC_INS_VCMPGTUB = 314
PPC_INS_VCMPGTUH = 315
PPC_INS_VCMPGTUW = 316
PPC_INS_VCTSXS = 317
PPC_INS_VCTUXS = 318
PPC_INS_VEXPTEFP = 319
PPC_INS_VLOGEFP = 320
PPC_INS_VMADDFP = 321
PPC_INS_VMAXFP = 322
PPC_INS_VMAXSB = 323
PPC_INS_VMAXSH = 324
PPC_INS_VMAXSW = 325
PPC_INS_VMAXUB = 326
PPC_INS_VMAXUH = 327
PPC_INS_VMAXUW = 328
PPC_INS_VMHADDSHS = 329
PPC_INS_VMHRADDSHS = 330
PPC_INS_VMINFP = 331
PPC_INS_VMINSB = 332
PPC_INS_VMINSH = 333
PPC_INS_VMINSW = 334
PPC_INS_VMINUB = 335
PPC_INS_VMINUH = 336
PPC_INS_VMINUW = 337
PPC_INS_VMLADDUHM = 338
PPC_INS_VMRGHB = 339
PPC_INS_VMRGHH = 340
PPC_INS_VMRGHW = 341
PPC_INS_VMRGLB = 342
PPC_INS_VMRGLH = 343
PPC_INS_VMRGLW = 344
PPC_INS_VMSUMMBM = 345
PPC_INS_VMSUMSHM = 346
PPC_INS_VMSUMSHS = 347
PPC_INS_VMSUMUBM = 348
PPC_INS_VMSUMUHM = 349
PPC_INS_VMSUMUHS = 350
PPC_INS_VMULESB = 351
PPC_INS_VMULESH = 352
PPC_INS_VMULEUB = 353
PPC_INS_VMULEUH = 354
PPC_INS_VMULOSB = 355
PPC_INS_VMULOSH = 356
PPC_INS_VMULOUB = 357
PPC_INS_VMULOUH = 358
PPC_INS_VNMSUBFP = 359
PPC_INS_VNOR = 360
PPC_INS_VOR = 361
PPC_INS_VPERM = 362
PPC_INS_VPKPX = 363
PPC_INS_VPKSHSS = 364
PPC_INS_VPKSHUS = 365
PPC_INS_VPKSWSS = 366
PPC_INS_VPKSWUS = 367
PPC_INS_VPKUHUM = 368
PPC_INS_VPKUHUS = 369
PPC_INS_VPKUWUM = 370
PPC_INS_VPKUWUS = 371
PPC_INS_VREFP = 372
PPC_INS_VRFIM = 373
PPC_INS_VRFIN = 374
PPC_INS_VRFIP = 375
PPC_INS_VRFIZ = 376
PPC_INS_VRLB = 377
PPC_INS_VRLH = 378
PPC_INS_VRLW = 379
PPC_INS_VRSQRTEFP = 380
PPC_INS_VSEL = 381
PPC_INS_VSL = 382
PPC_INS_VSLB = 383
PPC_INS_VSLDOI = 384
PPC_INS_VSLH = 385
PPC_INS_VSLO = 386
PPC_INS_VSLW = 387
PPC_INS_VSPLTB = 388
PPC_INS_VSPLTH = 389
PPC_INS_VSPLTISB = 390
PPC_INS_VSPLTISH = 391
PPC_INS_VSPLTISW = 392
PPC_INS_VSPLTW = 393
PPC_INS_VSR = 394
PPC_INS_VSRAB = 395
PPC_INS_VSRAH = 396
PPC_INS_VSRAW = 397
PPC_INS_VSRB = 398
PPC_INS_VSRH = 399
PPC_INS_VSRO = 400
PPC_INS_VSRW = 401
PPC_INS_VSUBCUW = 402
PPC_INS_VSUBFP = 403
PPC_INS_VSUBSBS = 404
PPC_INS_VSUBSHS = 405
PPC_INS_VSUBSWS = 406
PPC_INS_VSUBUBM = 407
PPC_INS_VSUBUBS = 408
PPC_INS_VSUBUHM = 409
PPC_INS_VSUBUHS = 410
PPC_INS_VSUBUWM = 411
PPC_INS_VSUBUWS = 412
PPC_INS_VSUM2SWS = 413
PPC_INS_VSUM4SBS = 414
PPC_INS_VSUM4SHS = 415
PPC_INS_VSUM4UBS = 416
PPC_INS_VSUMSWS = 417
PPC_INS_VUPKHPX = 418
PPC_INS_VUPKHSB = 419
PPC_INS_VUPKHSH = 420
PPC_INS_VUPKLPX = 421
PPC_INS_VUPKLSB = 422
PPC_INS_VUPKLSH = 423
PPC_INS_VXOR = 424
PPC_INS_WAIT = 425
PPC_INS_XOR = 426
PPC_INS_XORI = 427
PPC_INS_XORIS = 428
PPC_INS_BC = 429
PPC_INS_BCA = 430
PPC_INS_BCCTR = 431
PPC_INS_BCCTRL = 432
PPC_INS_BCLA = 433
PPC_INS_BCLR = 434
PPC_INS_BCLRL = 435
PPC_INS_MAX = 436
# Group of PPC instructions
@ -624,5 +626,7 @@ PPC_GRP_INVALID = 0
PPC_GRP_ALTIVEC = 1
PPC_GRP_MODE32 = 2
PPC_GRP_MODE64 = 3
PPC_GRP_JUMP = 4
PPC_GRP_MAX = 5
PPC_GRP_BOOKE = 4
PPC_GRP_NOTBOOKE = 5
PPC_GRP_JUMP = 6
PPC_GRP_MAX = 7

File diff suppressed because it is too large Load Diff

@ -4,6 +4,8 @@ cimport pyx.ccapstone as cc
import capstone, ctypes
from capstone import arm, x86, mips, ppc, arm64, CsError
_diet = cc.cs_support(capstone.CS_SUPPORT_DIET)
class CsDetail:
def __init__(self, arch, raw_detail = None):
@ -69,14 +71,26 @@ cdef class CsInsn(object):
@property
def mnemonic(self):
if _diet:
# Diet engine cannot provide @mnemonic & @op_str
raise CsError(capstone.CS_ERR_DIET)
return self._raw.mnemonic
@property
def op_str(self):
if _diet:
# Diet engine cannot provide @mnemonic & @op_str
raise CsError(capstone.CS_ERR_DIET)
return self._raw.op_str
@property
def regs_read(self):
if _diet:
# Diet engine cannot provide @mnemonic & @op_str
raise CsError(capstone.CS_ERR_DIET)
if self._detail:
detail = self._detail
return detail.regs_read[:detail.regs_read_count]
@ -85,6 +99,10 @@ cdef class CsInsn(object):
@property
def regs_write(self):
if _diet:
# Diet engine cannot provide @mnemonic & @op_str
raise CsError(capstone.CS_ERR_DIET)
if self._detail:
detail = self._detail
return detail.regs_write[:detail.regs_write_count]
@ -93,6 +111,10 @@ cdef class CsInsn(object):
@property
def groups(self):
if _diet:
# Diet engine cannot provide @mnemonic & @op_str
raise CsError(capstone.CS_ERR_DIET)
if self._detail:
detail = self._detail
return detail.groups[:detail.groups_count]
@ -105,22 +127,42 @@ cdef class CsInsn(object):
# get the register name, given the register ID
def reg_name(self, reg_id):
if _diet:
# Diet engine cannot provide @mnemonic & @op_str
raise CsError(capstone.CS_ERR_DIET)
return cc.cs_reg_name(self._csh, reg_id)
# get the instruction string
def insn_name(self):
if _diet:
# Diet engine cannot provide @mnemonic & @op_str
raise CsError(capstone.CS_ERR_DIET)
return cc.cs_insn_name(self._csh, self.id)
# verify if this insn belong to group with id as @group_id
def group(self, group_id):
if _diet:
# Diet engine cannot provide @mnemonic & @op_str
raise CsError(capstone.CS_ERR_DIET)
return group_id in self._detail.groups
# verify if this instruction implicitly read register @reg_id
def reg_read(self, reg_id):
if _diet:
# Diet engine cannot provide @mnemonic & @op_str
raise CsError(capstone.CS_ERR_DIET)
return reg_id in self._detail.regs_read
# verify if this instruction implicitly modified register @reg_id
def reg_write(self, reg_id):
if _diet:
# Diet engine cannot provide @mnemonic & @op_str
raise CsError(capstone.CS_ERR_DIET)
return reg_id in self._detail.regs_write
# return number of operands having same operand type @op_type
@ -147,11 +189,17 @@ cdef class Cs:
cdef object _cs
def __cinit__(self, _cs):
cdef version = cc.cs_version(NULL, NULL)
if (version != (capstone.CS_API_MAJOR << 8) + capstone.CS_API_MINOR):
# our binding version is different from the core's API version
raise CsError(capstone.CS_ERR_VERSION)
self.csh = <cc.csh> _cs.csh.value
self._cs = _cs
def disasm(self, code, addr, count=0):
cdef cc.cs_insn *allinsn
cdef res = cc.cs_disasm_ex(self.csh, code, len(code), addr, count, &allinsn)
detail = self._cs.detail
arch = self._cs.arch
@ -165,3 +213,22 @@ cdef class Cs:
dummy._raw = allinsn[i]
dummy._csh = self.csh
yield dummy
cc.cs_free(allinsn, res)
def disasm_lite(self, code, addr, count=0):
# TODO: dont need detail, so we might turn off detail, then turn on again when done
cdef cc.cs_insn *allinsn
if _diet:
# Diet engine cannot provide @mnemonic & @op_str
raise CsError(capstone.CS_ERR_DIET)
cdef res = cc.cs_disasm_ex(self.csh, code, len(code), addr, count, &allinsn)
for i from 0 <= i < res:
insn = allinsn[i]
yield (insn.address, insn.size, insn.mnemonic, insn.op_str)
cc.cs_free(allinsn, res)

@ -2,7 +2,7 @@
from distutils.core import setup
VERSION = '2.0'
VERSION = '2.1'
# clean package directory first
import os.path, shutil, sys

@ -3,7 +3,7 @@ from distutils.extension import Extension
from distutils.command.install_lib import install_lib as _install
from Cython.Distutils import build_ext
VERSION = '2.0'
VERSION = '2.1'
compile_args = ['-O3', '-fomit-frame-pointer']

@ -40,7 +40,7 @@ def to_hex(s):
### Test cs_disasm_quick()
def test_cs_disasm_quick():
for (arch, mode, code, comment) in all_tests:
for (arch, mode, code, comment, syntax) in all_tests:
print('*' * 40)
print("Platform: %s" %comment)
print("Disasm:"),

@ -0,0 +1,78 @@
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from capstone import *
import binascii
X86_CODE16 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
X86_CODE32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
X86_CODE64 = "\x55\x48\x8b\x05\xb8\x13\x00\x00"
ARM_CODE = "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
ARM_CODE2 = "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
THUMB_CODE = "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
THUMB_CODE2 = "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
MIPS_CODE = "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
MIPS_CODE2 = "\x56\x34\x21\x34\xc2\x17\x01\x00"
ARM64_CODE = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
PPC_CODE = "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
all_tests = (
(CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", 0),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX_ATT),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", 0),
(CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", 0),
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", 0),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", 0),
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", 0),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", 0),
(CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_64+ CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", 0),
(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", 0),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", 0),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
)
def to_hex(s):
return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK
### Test cs_disasm_quick()
def test_cs_disasm_quick():
for (arch, mode, code, comment, syntax) in all_tests:
print('*' * 40)
print("Platform: %s" %comment)
print("Disasm:"),
print to_hex(code)
for (addr, size, mnemonic, op_str) in cs_disasm_lite(arch, mode, code, 0x1000):
print("0x%x:\t%s\t%s" %(addr, mnemonic, op_str))
print
### Test class Cs
def test_class():
for (arch, mode, code, comment, syntax) in all_tests:
print('*' * 16)
print("Platform: %s" %comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
if syntax != 0:
md.syntax = syntax
for (addr, size, mnemonic, op_str) in md.disasm_lite(code, 0x1000):
print("0x%x:\t%s\t%s" %(addr, mnemonic, op_str))
print("0x%x:" % (addr + size))
print
except CsError as e:
print("ERROR: %s" %e)
#test_cs_disasm_quick()
#print "*" * 40
test_class()

@ -1,10 +1,5 @@
# Comment out the line below 'USE_SYS_DYN_MEM = yes' if you do not want to use
# system's malloc()/calloc()/realloc()/free() for internal dynamic memory management.
# NOTE: in that case, your program must specify your own malloc/calloc/realloc/free
# functions with cs_option(), using CS_OPT_MEM option type.
USE_SYS_DYN_MEM = yes
# Specify which archs you want to compile in
################################################################################
# Specify which archs you want to compile in.
# DO NOT touch the line below.
CAPSTONE_ARCHS =
@ -17,8 +12,30 @@ CAPSTONE_ARCHS += aarch64
# Comment out the line below if you don't want to support Mips
CAPSTONE_ARCHS += mips
# Comment out the line below if you don't want to support X86
CAPSTONE_ARCHS += x86
# Comment out the line below if you don't want to support PowerPC
CAPSTONE_ARCHS += powerpc
# Comment out the line below if you don't want to support Intel (16/32/64-bit)
CAPSTONE_ARCHS += x86
################################################################################
# Comment out the line below ('USE_SYS_DYN_MEM = yes') if you do not want to use
# system's malloc()/calloc()/realloc()/free() for internal dynamic memory management.
#
# NOTE: in that case, your program must specify your own malloc/calloc/realloc/free
# functions via API cs_option(), using CS_OPT_MEM option type.
USE_SYS_DYN_MEM = yes
################################################################################
# Change 'CAPSTONE_DIET = no' to 'CAPSTONE_DIET = yes' to make the library
# more compact: use less memory & smaller in binary size.
# This setup will remove the @mnemonic & @op_str data, plus semantic information
# such as @regs_read/write & @group. The amount of reduced size in the binary
# is up to 50% in some individual archs.
#
# NOTE: we still keep all those related fileds @mnemonic, @op_str, @regs_read,
# @regs_write, @groups, etc in fields in cs_insn structure regardless, but they
# will not be updated (i.e empty) at the output of related APIs.
CAPSTONE_DIET = no

106
cs.c

@ -74,14 +74,26 @@ unsigned int cs_version(int *major, int *minor)
return (CS_API_MAJOR << 8) + CS_API_MINOR;
}
bool cs_support(int arch)
bool cs_support(int query)
{
if (arch == CS_ARCH_ALL)
if (query == CS_ARCH_ALL)
return all_arch == ((1 << CS_ARCH_ARM) | (1 << CS_ARCH_ARM64) |
(1 << CS_ARCH_MIPS) | (1 << CS_ARCH_X86) |
(1 << CS_ARCH_PPC));
return all_arch & (1 << arch);
if (query < CS_ARCH_MAX)
return all_arch & (1 << query);
if (query == CS_SUPPORT_DIET) {
#ifdef CAPSTONE_DIET
return true;
#else
return false;
#endif
}
// unsupported query
return false;
}
cs_err cs_errno(csh handle)
@ -89,7 +101,7 @@ cs_err cs_errno(csh handle)
if (!handle)
return CS_ERR_CSH;
cs_struct *ud = (cs_struct *)(uintptr_t)handle;
struct cs_struct *ud = (struct cs_struct *)(uintptr_t)handle;
return ud->errnum;
}
@ -117,6 +129,10 @@ const char *cs_strerror(cs_err code)
return "Details are unavailable (CS_ERR_DETAIL)";
case CS_ERR_MEMSETUP:
return "Dynamic memory management uninitialized (CS_ERR_MEMSETUP)";
case CS_ERR_VERSION:
return "Different API version between core & binding (CS_ERR_VERSION)";
case CS_ERR_DIET:
return "Information irrelevant in diet engine (CS_ERR_DIET)";
}
}
@ -130,7 +146,7 @@ cs_err cs_open(cs_arch arch, cs_mode mode, csh *handle)
archs_enable();
if (arch < CS_ARCH_MAX && arch_init[arch]) {
cs_struct *ud;
struct cs_struct *ud;
ud = cs_mem_calloc(1, sizeof(*ud));
if (!ud) {
@ -166,7 +182,7 @@ cs_err cs_close(csh handle)
if (!handle)
return CS_ERR_CSH;
cs_struct *ud = (cs_struct *)(uintptr_t)handle;
struct cs_struct *ud = (struct cs_struct *)(uintptr_t)handle;
switch (ud->arch) {
case CS_ARCH_X86:
@ -193,7 +209,7 @@ cs_err cs_close(csh handle)
#define MIN(x, y) ((x) < (y) ? (x) : (y))
// fill insn with mnemonic & operands info
static void fill_insn(cs_struct *handle, cs_insn *insn, char *buffer, MCInst *mci,
static void fill_insn(struct cs_struct *handle, cs_insn *insn, char *buffer, MCInst *mci,
PostPrinter_t postprinter, const uint8_t *code)
{
if (handle->detail) {
@ -205,11 +221,12 @@ static void fill_insn(cs_struct *handle, cs_insn *insn, char *buffer, MCInst *mc
memcpy(insn->detail, (void *)(&(mci->flat_insn)) + offsetof(cs_insn_flat, regs_read),
offsetof(cs_detail, arm) - offsetof(cs_detail, regs_read));
// then copy from @arm until end
memcpy((void *)(insn->detail) + offsetof(cs_detail, arm), (void *)(&(mci->flat_insn)) + offsetof(cs_insn_flat, arm),
memcpy((void *)((uintptr_t)(insn->detail) + offsetof(cs_detail, arm)),
(void *)((uintptr_t)(&(mci->flat_insn)) + offsetof(cs_insn_flat, arm)),
sizeof(cs_detail) - offsetof(cs_detail, arm));
} else {
insn->address = mci->address;
insn->size = mci->insn_size;
insn->size = (uint16_t)mci->insn_size;
}
// fill the instruction bytes
@ -227,6 +244,7 @@ static void fill_insn(cs_struct *handle, cs_insn *insn, char *buffer, MCInst *mc
if (postprinter)
postprinter((csh)handle, insn, buffer);
#ifndef CAPSTONE_DIET
// fill in mnemonic & operands
// find first space or tab
char *sp = buffer;
@ -245,6 +263,7 @@ static void fill_insn(cs_struct *handle, cs_insn *insn, char *buffer, MCInst *mc
strncpy(insn->mnemonic, buffer, sizeof(insn->mnemonic) - 1);
insn->mnemonic[sizeof(insn->mnemonic) - 1] = '\0';
#endif
}
cs_err cs_option(csh ud, cs_opt_type type, size_t value)
@ -263,7 +282,7 @@ cs_err cs_option(csh ud, cs_opt_type type, size_t value)
return CS_ERR_OK;
}
cs_struct *handle = (cs_struct *)(uintptr_t)ud;
struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle)
return CS_ERR_CSH;
@ -283,7 +302,7 @@ static cs_insn *get_prev_insn(cs_insn *cache, unsigned int f, void *total, size_
return NULL;
// get the trailing insn from total buffer, which is at
// the end of the latest cache trunk
return (cs_insn *)(total + total_size - (sizeof(cs_insn) * INSN_CACHE_SIZE));
return (cs_insn *)((void*)((uintptr_t)total + total_size - sizeof(cs_insn)));
} else
return &cache[f - 1];
}
@ -292,7 +311,7 @@ static cs_insn *get_prev_insn(cs_insn *cache, unsigned int f, void *total, size_
// NOTE: caller must free() the allocated memory itself to avoid memory leaking
size_t cs_disasm_ex(csh ud, const uint8_t *buffer, size_t size, uint64_t offset, size_t count, cs_insn **insn)
{
cs_struct *handle = (cs_struct *)(uintptr_t)ud;
struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
MCInst mci;
uint16_t insn_size;
size_t c = 0;
@ -353,14 +372,15 @@ size_t cs_disasm_ex(csh ud, const uint8_t *buffer, size_t size, uint64_t offset,
}
total = tmp;
memcpy(total + total_size - sizeof(insn_cache), insn_cache, sizeof(insn_cache));
memcpy((void*)((uintptr_t)total + total_size - sizeof(insn_cache)), insn_cache, sizeof(insn_cache));
// reset f back to 0
f = 0;
}
c++;
} else {
// combine this instruction with previous prefix instruction
// combine this instruction with previous prefix "instruction"
cs_insn *prev = get_prev_insn(insn_cache, f, total, total_size);
handle->combine(handle, &insn_cache[f], prev);
}
@ -369,8 +389,25 @@ size_t cs_disasm_ex(csh ud, const uint8_t *buffer, size_t size, uint64_t offset,
size -= insn_size;
offset += insn_size;
if (count > 0 && c == count)
break;
if (count > 0) {
// x86 hacky
if (!handle->prev_prefix) {
if (c == count)
break;
} else {
// only combine 1 prefix with regular instruction
if (c == count + 1) {
// the last insn is redundant
c--;
f--;
// free allocated detail pointer of the last redundant instruction
if (handle->detail)
cs_mem_free(insn_cache[f].detail);
break;
}
}
}
} else {
// encounter a broken instruction
// XXX: TODO: JOXEAN continue here
@ -388,7 +425,8 @@ size_t cs_disasm_ex(csh ud, const uint8_t *buffer, size_t size, uint64_t offset,
}
total = tmp;
memcpy(total + total_size, insn_cache, f * sizeof(insn_cache[0]));
memcpy((void*)((uintptr_t)total + total_size), insn_cache, f * sizeof(insn_cache[0]));
}
*insn = total;
@ -411,7 +449,7 @@ void cs_free(cs_insn *insn, size_t count)
// return friendly name of regiser in a string
const char *cs_reg_name(csh ud, unsigned int reg)
{
cs_struct *handle = (cs_struct *)(uintptr_t)ud;
struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle || handle->reg_name == NULL) {
return NULL;
@ -422,7 +460,7 @@ const char *cs_reg_name(csh ud, unsigned int reg)
const char *cs_insn_name(csh ud, unsigned int insn)
{
cs_struct *handle = (cs_struct *)(uintptr_t)ud;
struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle || handle->insn_name == NULL) {
return NULL;
@ -448,7 +486,7 @@ bool cs_insn_group(csh ud, cs_insn *insn, unsigned int group_id)
if (!ud)
return false;
cs_struct *handle = (cs_struct *)(uintptr_t)ud;
struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle->detail) {
handle->errnum = CS_ERR_DETAIL;
return false;
@ -462,7 +500,7 @@ bool cs_reg_read(csh ud, cs_insn *insn, unsigned int reg_id)
if (!ud)
return false;
cs_struct *handle = (cs_struct *)(uintptr_t)ud;
struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle->detail) {
handle->errnum = CS_ERR_DETAIL;
return false;
@ -476,7 +514,7 @@ bool cs_reg_write(csh ud, cs_insn *insn, unsigned int reg_id)
if (!ud)
return false;
cs_struct *handle = (cs_struct *)(uintptr_t)ud;
struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle->detail) {
handle->errnum = CS_ERR_DETAIL;
return false;
@ -490,7 +528,7 @@ int cs_op_count(csh ud, cs_insn *insn, unsigned int op_type)
if (!ud)
return -1;
cs_struct *handle = (cs_struct *)(uintptr_t)ud;
struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle->detail) {
handle->errnum = CS_ERR_DETAIL;
return -1;
@ -506,27 +544,27 @@ int cs_op_count(csh ud, cs_insn *insn, unsigned int op_type)
return -1;
case CS_ARCH_ARM:
for (i = 0; i < insn->detail->arm.op_count; i++)
if (insn->detail->arm.operands[i].type == op_type)
if (insn->detail->arm.operands[i].type == (arm_op_type)op_type)
count++;
break;
case CS_ARCH_ARM64:
for (i = 0; i < insn->detail->arm64.op_count; i++)
if (insn->detail->arm64.operands[i].type == op_type)
if (insn->detail->arm64.operands[i].type == (arm64_op_type)op_type)
count++;
break;
case CS_ARCH_X86:
for (i = 0; i < insn->detail->x86.op_count; i++)
if (insn->detail->x86.operands[i].type == op_type)
if (insn->detail->x86.operands[i].type == (x86_op_type)op_type)
count++;
break;
case CS_ARCH_MIPS:
for (i = 0; i < insn->detail->mips.op_count; i++)
if (insn->detail->mips.operands[i].type == op_type)
if (insn->detail->mips.operands[i].type == (mips_op_type)op_type)
count++;
break;
case CS_ARCH_PPC:
for (i = 0; i < insn->detail->ppc.op_count; i++)
if (insn->detail->ppc.operands[i].type == op_type)
if (insn->detail->ppc.operands[i].type == (ppc_op_type)op_type)
count++;
break;
}
@ -540,7 +578,7 @@ int cs_op_index(csh ud, cs_insn *insn, unsigned int op_type,
if (!ud)
return -1;
cs_struct *handle = (cs_struct *)(uintptr_t)ud;
struct cs_struct *handle = (struct cs_struct *)(uintptr_t)ud;
if (!handle->detail) {
handle->errnum = CS_ERR_DETAIL;
return -1;
@ -556,7 +594,7 @@ int cs_op_index(csh ud, cs_insn *insn, unsigned int op_type,
return -1;
case CS_ARCH_ARM:
for (i = 0; i < insn->detail->arm.op_count; i++) {
if (insn->detail->arm.operands[i].type == op_type)
if (insn->detail->arm.operands[i].type == (arm_op_type)op_type)
count++;
if (count == post)
return i;
@ -564,7 +602,7 @@ int cs_op_index(csh ud, cs_insn *insn, unsigned int op_type,
break;
case CS_ARCH_ARM64:
for (i = 0; i < insn->detail->arm64.op_count; i++) {
if (insn->detail->arm64.operands[i].type == op_type)
if (insn->detail->arm64.operands[i].type == (arm64_op_type)op_type)
count++;
if (count == post)
return i;
@ -572,7 +610,7 @@ int cs_op_index(csh ud, cs_insn *insn, unsigned int op_type,
break;
case CS_ARCH_X86:
for (i = 0; i < insn->detail->x86.op_count; i++) {
if (insn->detail->x86.operands[i].type == op_type)
if (insn->detail->x86.operands[i].type == (x86_op_type)op_type)
count++;
if (count == post)
return i;
@ -580,7 +618,7 @@ int cs_op_index(csh ud, cs_insn *insn, unsigned int op_type,
break;
case CS_ARCH_MIPS:
for (i = 0; i < insn->detail->mips.op_count; i++) {
if (insn->detail->mips.operands[i].type == op_type)
if (insn->detail->mips.operands[i].type == (mips_op_type)op_type)
count++;
if (count == post)
return i;
@ -588,7 +626,7 @@ int cs_op_index(csh ud, cs_insn *insn, unsigned int op_type,
break;
case CS_ARCH_PPC:
for (i = 0; i < insn->detail->ppc.op_count; i++) {
if (insn->detail->ppc.operands[i].type == op_type)
if (insn->detail->ppc.operands[i].type == (ppc_op_type)op_type)
count++;
if (count == post)
return i;

@ -1 +1,27 @@
All the tutorials are available at http://capstone-engine.org/documentation.html
Documention of Capstone disassembly framework.
* For instructions to compile & install Capstone, see:
http://capstone-engine.org/documentation.html
* Programming with C language.
http://capstone-engine.org/lang_c.html
* Programming with Python language.
http://capstone-engine.org/lang_python.html
* Programming with Java language.
http://capstone-engine.org/lang_java.html
* Build compact engine with only selected architectures.
http://capstone-engine.org/compile.html
* Build "diet" engine for even smaller libraries.
http://capstone-engine.org/diet.html

@ -11,6 +11,10 @@ extern "C" {
#include <stdint.h>
#include <stdbool.h>
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
//> ARM shift type
typedef enum arm_shifter {
ARM_SFT_INVALID = 0,
@ -647,7 +651,7 @@ typedef enum arm_insn {
ARM_INS_POP,
ARM_INS_PUSH,
ARM_INS_MAX,
ARM_INS_MAX, // <-- mark the end of the list of instructions
} arm_insn;
//> Group of ARM instructions

@ -11,6 +11,10 @@ extern "C" {
#include <stdint.h>
#include <stdbool.h>
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
//> ARM64 shift type
typedef enum arm64_shifter {
ARM64_SFT_INVALID = 0,

@ -14,9 +14,16 @@ extern "C" {
#include <stdbool.h>
#include <stdlib.h>
#include "diet.h" // CAPSTONE_DIET
#ifdef _MSC_VER
#pragma warning(disable:4201)
#pragma warning(disable:4100)
#endif
// Capstone API version
#define CS_API_MAJOR 2
#define CS_API_MINOR 0
#define CS_API_MINOR 1
// Macro to create combined version which can be compared to
// result of cs_version() API.
@ -36,6 +43,8 @@ typedef enum cs_arch {
CS_ARCH_ALL = 0xFFFF,
} cs_arch;
#define CS_SUPPORT_DIET (CS_ARCH_ALL + 1)
// Mode type
typedef enum cs_mode {
CS_MODE_LITTLE_ENDIAN = 0, // little endian mode (default mode)
@ -165,6 +174,8 @@ typedef enum cs_err {
CS_ERR_OPTION, // Invalid/unsupported option: cs_option()
CS_ERR_DETAIL, // Information is unavailable because detail option is OFF
CS_ERR_MEMSETUP, // Dynamic memory management uninitialized (see CS_OPT_MEM)
CS_ERR_VERSION, // Unsupported version (bindings)
CS_ERR_DIET, // Access irrelevant data in "diet" engine
} cs_err;
/*
@ -188,14 +199,19 @@ unsigned int cs_version(int *major, int *minor);
/*
Check if a particular arch is supported by this library.
This API can be used to either ask for archs supported by this library,
or check to see if the library was compile with 'diet' option (or called
in 'diet' mode).
To check if a particular arch is supported by this library, set @query to
arch mode (CS_ARCH_* value).
To verify if this library supports all the archs, use CS_ARCH_ALL.
@arch: the architecture to be checked.
To verify if this library supports everything, use CS_ARCH_ALL
To check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.
@return True if this library supports the given arch.
@return True if this library supports the given arch, or in 'diet' mode.
*/
bool cs_support(int arch);
bool cs_support(int query);
/*
Initialize CS handle: this must be done before any usage of CS.
@ -297,7 +313,11 @@ void cs_free(cs_insn *insn, size_t count);
/*
Return friendly name of regiser in a string
Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
Find the instruction id from header file of corresponding architecture (arm.h for ARM,
x86.h for X86, ...)
WARN: when in 'diet' mode, this API is irrelevant because engine does not
store register name.
@handle: handle returned by cs_open()
@reg: register id
@ -309,6 +329,9 @@ const char *cs_reg_name(csh handle, unsigned int reg_id);
Return friendly name of an instruction in a string
Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
store instruction name.
@handle: handle returned by cs_open()
@insn: instruction id
@ -321,7 +344,10 @@ const char *cs_insn_name(csh handle, unsigned int insn_id);
Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
Internally, this simply verifies if @group_id matches any member of insn->groups array.
NOTE: this API is only valid when detail option is ON (which is OFF by default)
NOTE: this API is only valid when detail option is ON (which is OFF by default).
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
update @groups array.
@handle: handle returned by cs_open()
@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_ex()
@ -338,6 +364,9 @@ bool cs_insn_group(csh handle, cs_insn *insn, unsigned int group_id);
NOTE: this API is only valid when detail option is ON (which is OFF by default)
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
update @regs_read array.
@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_ex()
@reg_id: register that you want to check if this instruction used it.
@ -352,6 +381,9 @@ bool cs_reg_read(csh handle, cs_insn *insn, unsigned int reg_id);
NOTE: this API is only valid when detail option is ON (which is OFF by default)
WARN: when in 'diet' mode, this API is irrelevant because the engine does not
update @regs_write array.
@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_ex()
@reg_id: register that you want to check if this instruction modified it.

@ -11,6 +11,10 @@ extern "C" {
#include <stdint.h>
#include <stdbool.h>
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
//> Operand type for instruction's operands
typedef enum mips_op_type {
MIPS_OP_INVALID = 0, // Uninitialized.
@ -340,6 +344,7 @@ typedef enum mips_insn {
MIPS_INS_DINSU,
MIPS_INS_DIV_S,
MIPS_INS_DIV_U,
MIPS_INS_DLSA,
MIPS_INS_DMFC0,
MIPS_INS_DMFC1,
MIPS_INS_DMFC2,
@ -502,9 +507,9 @@ typedef enum mips_insn {
MIPS_INS_LWC2,
MIPS_INS_LWL,
MIPS_INS_LWR,
MIPS_INS_LWU,
MIPS_INS_LWX,
MIPS_INS_LWXC1,
MIPS_INS_LWU,
MIPS_INS_LI,
MIPS_INS_MADD,
MIPS_INS_MADDR_Q,
@ -713,6 +718,7 @@ typedef enum mips_insn_group {
MIPS_GRP_NONANSFPMATH,
MIPS_GRP_NOTFP64BIT,
MIPS_GRP_NOTINMICROMIPS,
MIPS_GRP_NOTNACL,
MIPS_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps)

@ -11,6 +11,9 @@ extern "C" {
#include <stdint.h>
#include <stdbool.h>
#ifdef _MSC_VER
#pragma warning(disable:4201)
#endif
//> PPC branch codes for some branch instructions
typedef enum ppc_bc {
@ -332,6 +335,7 @@ typedef enum ppc_insn {
PPC_INS_FDIVS,
PPC_INS_FMADD,
PPC_INS_FMADDS,
PPC_INS_FMR,
PPC_INS_FMSUB,
PPC_INS_FMSUBS,
PPC_INS_FMUL,
@ -418,6 +422,7 @@ typedef enum ppc_insn {
PPC_INS_MFSPR,
PPC_INS_MFTB,
PPC_INS_MFVSCR,
PPC_INS_MSYNC,
PPC_INS_MTCRF,
PPC_INS_MTCTR,
PPC_INS_MTFSB0,
@ -683,6 +688,8 @@ typedef enum ppc_insn_group {
PPC_GRP_ALTIVEC,
PPC_GRP_MODE32,
PPC_GRP_MODE64,
PPC_GRP_BOOKE,
PPC_GRP_NOTBOOKE,
PPC_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps)

@ -208,7 +208,6 @@ typedef enum x86_insn {
X86_INS_BTS,
X86_INS_BZHI,
X86_INS_CALL,
X86_INS_CALLW,
X86_INS_CBW,
X86_INS_CDQ,
X86_INS_CDQE,
@ -339,14 +338,15 @@ typedef enum x86_insn {
X86_INS_FRSTOR,
X86_INS_FNSAVE,
X86_INS_FSCALE,
X86_INS_FSETPM,
X86_INS_FSINCOS,
X86_INS_FNSTENV,
X86_INS_FS,
X86_INS_FXAM,
X86_INS_FXRSTOR,
X86_INS_FXRSTORQ,
X86_INS_FXRSTOR64,
X86_INS_FXSAVE,
X86_INS_FXSAVEQ,
X86_INS_FXSAVE64,
X86_INS_FXTRACT,
X86_INS_FYL2X,
X86_INS_FYL2XP1,
@ -358,6 +358,7 @@ typedef enum x86_insn {
X86_INS_VMOVAPS,
X86_INS_XORPD,
X86_INS_XORPS,
X86_INS_GETSEC,
X86_INS_GS,
X86_INS_HADDPD,
X86_INS_HADDPS,
@ -367,12 +368,15 @@ typedef enum x86_insn {
X86_INS_IDIV,
X86_INS_FILD,
X86_INS_IMUL,
X86_INS_INS,
X86_INS_INSW,
X86_INS_IN,
X86_INS_INSD,
X86_INS_INSB,
X86_INS_INC,
X86_INS_INSERTPS,
X86_INS_INSERTQ,
X86_INS_INT,
X86_INS_INT1,
X86_INS_INT3,
X86_INS_INTO,
X86_INS_INVD,
@ -416,7 +420,6 @@ typedef enum x86_insn {
X86_INS_JLE,
X86_INS_JL,
X86_INS_JMP,
X86_INS_JMPQ,
X86_INS_JNE,
X86_INS_JNO,
X86_INS_JNP,
@ -425,7 +428,6 @@ typedef enum x86_insn {
X86_INS_JP,
X86_INS_JRCXZ,
X86_INS_JS,
X86_INS_KADDW,
X86_INS_KANDNW,
X86_INS_KANDW,
X86_INS_KMOVW,
@ -434,7 +436,6 @@ typedef enum x86_insn {
X86_INS_KORW,
X86_INS_KSHIFTLW,
X86_INS_KSHIFTRW,
X86_INS_KTESTW,
X86_INS_KUNPCKBW,
X86_INS_KXNORW,
X86_INS_KXORW,
@ -468,6 +469,7 @@ typedef enum x86_insn {
X86_INS_LOOPE,
X86_INS_LOOPNE,
X86_INS_RETF,
X86_INS_RETFQ,
X86_INS_LSL,
X86_INS_LSS,
X86_INS_LTR,
@ -690,7 +692,8 @@ typedef enum x86_insn {
X86_INS_PMULHRW,
X86_INS_PMULLD,
X86_INS_POP,
X86_INS_POPA,
X86_INS_POPAW,
X86_INS_POPAL,
X86_INS_POPCNT,
X86_INS_POPF,
X86_INS_POPFD,
@ -711,7 +714,8 @@ typedef enum x86_insn {
X86_INS_PUNPCKHQDQ,
X86_INS_PUNPCKLQDQ,
X86_INS_PUSH,
X86_INS_PUSHA,
X86_INS_PUSHAW,
X86_INS_PUSHAL,
X86_INS_PUSHF,
X86_INS_PUSHFD,
X86_INS_PUSHFQ,
@ -742,6 +746,7 @@ typedef enum x86_insn {
X86_INS_RSQRTPS,
X86_INS_RSQRTSS,
X86_INS_SAHF,
X86_INS_SALC,
X86_INS_SAR,
X86_INS_SARX,
X86_INS_SBB,
@ -875,10 +880,12 @@ typedef enum x86_insn {
X86_INS_VCVTPD2DQ,
X86_INS_VCVTPD2PSX,
X86_INS_VCVTPD2PS,
X86_INS_VCVTPD2UDQ,
X86_INS_VCVTPH2PS,
X86_INS_VCVTPS2DQ,
X86_INS_VCVTPS2PD,
X86_INS_VCVTPS2PH,
X86_INS_VCVTPS2UDQ,
X86_INS_VCVTSD2SI,
X86_INS_VCVTSD2USI,
X86_INS_VCVTSS2SI,
@ -1147,6 +1154,10 @@ typedef enum x86_insn {
X86_INS_VPERMPD,
X86_INS_VPERMPS,
X86_INS_VPERMQ,
X86_INS_VPERMT2D,
X86_INS_VPERMT2PD,
X86_INS_VPERMT2PS,
X86_INS_VPERMT2Q,
X86_INS_VPEXTRB,
X86_INS_VPEXTRD,
X86_INS_VPEXTRQ,
@ -1303,6 +1314,8 @@ typedef enum x86_insn {
X86_INS_VPSUBW,
X86_INS_VPTESTMD,
X86_INS_VPTESTMQ,
X86_INS_VPTESTNMD,
X86_INS_VPTESTNMQ,
X86_INS_VPTEST,
X86_INS_VPUNPCKHBW,
X86_INS_VPUNPCKHDQ,
@ -1325,10 +1338,10 @@ typedef enum x86_insn {
X86_INS_VRCP28SS,
X86_INS_VRCPPS,
X86_INS_VRCPSS,
X86_INS_VRNDSCALESD,
X86_INS_VRNDSCALESS,
X86_INS_VRNDSCALEPD,
X86_INS_VRNDSCALEPS,
X86_INS_VRNDSCALESD,
X86_INS_VRNDSCALESS,
X86_INS_VROUNDPD,
X86_INS_VROUNDPS,
X86_INS_VROUNDSD,
@ -1350,7 +1363,6 @@ typedef enum x86_insn {
X86_INS_VSHUFPD,
X86_INS_VSHUFPS,
X86_INS_VSQRTPD,
X86_INS_VSQRT,
X86_INS_VSQRTPS,
X86_INS_VSQRTSD,
X86_INS_VSQRTSS,
@ -1404,6 +1416,7 @@ typedef enum x86_insn {
//> Group of X86 instructions
typedef enum x86_insn_group {
X86_GRP_INVALID = 0,
X86_GRP_3DNOW,
X86_GRP_AES,
X86_GRP_ADX,
@ -1435,6 +1448,8 @@ typedef enum x86_insn_group {
X86_GRP_CDI,
X86_GRP_ERI,
X86_GRP_TBM,
X86_GRP_16BITMODE,
X86_GRP_NOT64BITMODE,
X86_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps)

@ -6,11 +6,7 @@
# Note: to cross-compile "nix32" on Linux, package gcc-multilib is required.
function build {
if [ ${MAKE}x = x ]; then
MAKE=make
fi
CROSS= ${MAKE} clean
${MAKE} clean
if [ ${CC}x != x ]; then
${MAKE} CC=$CC
@ -20,10 +16,6 @@ function build {
}
function install {
if [ ${MAKE}x = x ]; then
MAKE=make
fi
if [ ${CC}x != x ]; then
${MAKE} CC=$CC install
else
@ -31,6 +23,7 @@ function install {
fi
}
MAKE=make
if [ "$(uname)" == "SunOS" ]; then
export MAKE=gmake
export INSTALL_BIN=ginstall
@ -46,6 +39,7 @@ case "$1" in
"" ) build;;
"default" ) build;;
"install" ) install;;
"uninstall" ) ${MAKE} uninstall;;
"nix32" ) CFLAGS=-m32 LDFLAGS=-m32 build;;
"cross-win32" ) CROSS=i686-w64-mingw32- build;;
"cross-win64" ) CROSS=x86_64-w64-mingw32- build;;
@ -53,5 +47,5 @@ case "$1" in
"cygwin-mingw64" ) CROSS=x86_64-w64-mingw32- build;;
"clang" ) CC=clang build;;
"gcc" ) CC=gcc build;;
* ) echo "Usage: make.sh [nix32|cross-win32|cross-win64|cygwin-mingw32|cygwin-mingw64|clang|gcc]"; exit 1;;
* ) echo "Usage: make.sh [nix32|cross-win32|cross-win64|cygwin-mingw32|cygwin-mingw64|clang|gcc|install|uninstall]"; exit 1;;
esac

@ -0,0 +1,22 @@
# $FreeBSD$
PORTNAME= capstone
PORTVERSION= 2.0
CATEGORIES= devel
MASTER_SITES= http://capstone-engine.org/download/2.0/
MAINTAINER= oliver.pntr@gmail.com
COMMENT= Multi-platform, multi-architecture disassembly framework
LICENSE= BSD3CLAUSE
USES= gmake
USE_LDCONFIG= yes
MAKE_ENV= INSTALL_LIBRARY="${INSTALL_LIB}"
post-build:
# The pkgconfig file is generated and points to stagedir
${REINPLACE_CMD} -e '/libdir/s|\(libdir=\)\(.*\)\(devel/capstone/work/stage\)|\1|g' ${WRKSRC}/capstone.pc
.include <bsd.port.mk>

@ -0,0 +1,2 @@
SHA256 (capstone-2.0.tar.gz) = 5d871b1e52047d1b2882bbcc6f049205ba6acc8d55d746937d22af5d0b33fa9e
SIZE (capstone-2.0.tar.gz) = 1731759

@ -0,0 +1,52 @@
--- Makefile.orig 2014-01-22 11:33:35.000000000 +0100
+++ Makefile 2014-01-25 19:13:32.000000000 +0100
@@ -15,7 +15,7 @@
STRIP = $(CROSS)strip
endif
-CFLAGS += -fPIC -O3 -Wall -Iinclude
+CFLAGS += -fPIC -Wall -Iinclude
ifeq ($(USE_SYS_DYN_MEM),yes)
CFLAGS += -DUSE_SYS_DYN_MEM
@@ -38,6 +38,14 @@
endif
endif
+LIBDATADIR = $(LIBDIR)
+UNAME_S := $(shell uname -s)
+ifeq ($(UNAME_S), FreeBSD)
+LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata
+else
+LIBDATADIR = $(LIBDIR)
+endif
+
INSTALL_BIN ?= install
INSTALL_DATA ?= $(INSTALL_BIN) -m0644
INSTALL_LIBRARY ?= $(INSTALL_BIN) -m0755
@@ -88,7 +96,6 @@
LIBOBJ += MCInst.o
-UNAME_S := $(shell uname -s)
# OSX?
ifeq ($(UNAME_S),Darwin)
EXT = dylib
@@ -156,14 +163,14 @@
$(INSTALL_DATA) lib$(LIBNAME).$(AR_EXT) $(LIBDIR)
mkdir -p $(INCDIR)/$(LIBNAME)
$(INSTALL_DATA) include/*.h $(INCDIR)/$(LIBNAME)
- mkdir -p $(LIBDIR)/pkgconfig
- $(INSTALL_DATA) $(PKGCFGF) $(LIBDIR)/pkgconfig/
+ mkdir -p $(LIBDATADIR)/pkgconfig
+ $(INSTALL_DATA) $(PKGCFGF) $(LIBDATADIR)/pkgconfig/
uninstall:
rm -rf $(INCDIR)/$(LIBNAME)
rm -f $(LIBDIR)/lib$(LIBNAME).$(EXT)
rm -f $(LIBDIR)/lib$(LIBNAME).$(AR_EXT)
- rm -f $(LIBDIR)/pkgconfig/$(LIBNAME).pc
+ rm -f $(LIBDATADIR)/pkgconfig/$(LIBNAME).pc
clean:
rm -f $(LIBOBJ) lib$(LIBNAME).*

@ -0,0 +1,22 @@
--- tests/Makefile.orig 2014-01-25 19:14:03.000000000 +0100
+++ tests/Makefile 2014-01-25 19:14:24.000000000 +0100
@@ -11,7 +11,7 @@
endif
-CFLAGS += -fPIC -O3 -Wall -I$(INCDIR) -L$(LIBDIR)
+CFLAGS += -fPIC -Wall -I$(INCDIR) -L$(LIBDIR)
LIBNAME = capstone
@@ -48,8 +48,8 @@
$(BINARY): $(OBJS)
%$(BIN_EXT): %.o
- ${CC} $(CFLAGS) $(LDFLAGS) $< -O3 -Wall -l$(LIBNAME) -o $@
- ${CC} $(CFLAGS) $(LDFLAGS) $< -O3 -Wall ../lib$(LIBNAME).$(AR_EXT) -o $(subst $(BIN_EXT),,$@).static$(BIN_EXT)
+ ${CC} $(CFLAGS) $(LDFLAGS) $< -Wall -l$(LIBNAME) -o $@
+ ${CC} $(CFLAGS) $(LDFLAGS) $< -Wall ../lib$(LIBNAME).$(AR_EXT) -o $(subst $(BIN_EXT),,$@).static$(BIN_EXT)
%.o: %.c
${CC} ${CFLAGS} -c $< -o $@

@ -0,0 +1,16 @@
Capstone is a lightweight multi-platform, multi-architecture disassembly
framework.
Features:
* Supported architectures: ARM, ARM64 (aka ARMv8), Mips, PowerPC & X86
* Clean/simple/lightweight/intuitive architecture-neutral API
* Provide details on disassembled instruction (called "decomposer")
* Provide some semantics of the disassembled instruction, such as list of
implicit registers read & written.
* Implemented in pure C language, with bindings for Python, Ruby, C#, Java,
GO, OCaml & Vala available.
* Native support for Windows & *nix (including MacOSX, Linux, *BSD & Solaris)
* Thread-safe by design
* Distributed under the open source BSD license
WWW: http://capstone-engine.org/

@ -0,0 +1,10 @@
include/capstone/arm.h
include/capstone/arm64.h
include/capstone/capstone.h
include/capstone/mips.h
include/capstone/ppc.h
include/capstone/x86.h
lib/libcapstone.a
lib/libcapstone.so
libdata/pkgconfig/capstone.pc
@dirrmtry include/capstone

@ -0,0 +1,2 @@
This directory contains the Homebrew formula for Capstone.
File capstone.rb should be put in its directory Library/Formula.

@ -0,0 +1,14 @@
require 'formula'
class Capstone < Formula
homepage 'http://capstone-engine.org'
url 'http://capstone-engine.org/download/2.0/capstone-2.0.tgz'
sha1 '209cdc69518f754c5d7d07672d8e28cdda9feae7'
def install
inreplace 'Makefile', 'lib64', 'lib'
system "./make.sh"
ENV["PREFIX"] = prefix
system "./make.sh", "install"
end
end

@ -0,0 +1,40 @@
# -*- coding: utf-8; mode: tcl; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 4 -*- vim:fenc=utf-8:ft=tcl:et:sw=4:ts=4:sts=4
# $Id: Portfile 117078 2014-02-15 00:49:41Z ryandesign@macports.org $
PortSystem 1.0
name capstone
version 2.0
revision 1
categories devel
platforms darwin
maintainers gmail.com:aquynh
license BSD
description Capstone disassembly engine
long_description Capstone is a multi-arch, multi-platform disassembly framework with advanced features
homepage http://www.capstone-engine.org/
master_sites ${homepage}download/${version}/
extract.suffix .tgz
checksums sha256 5d871b1e52047d1b2882bbcc6f049205ba6acc8d55d746937d22af5d0b33fa9e \
rmd160 bb7551404e203fa99240b5e33c3d30ca8555830f
patchfiles patch-Makefile.diff
variant universal {}
use_configure no
build.env CC=${configure.cc} \
CFLAGS="${configure.cflags} [get_canonical_archflags cc]" \
LDFLAGS="${configure.ldflags} [get_canonical_archflags ld]" \
PREFIX=${prefix}
eval destroot.env ${build.env}
livecheck.type regex
livecheck.url ${homepage}download.html
livecheck.regex ${name}-(\[0-9.\]+)${extract.suffix}

@ -0,0 +1,81 @@
--- Makefile.orig 2014-01-22 04:33:35.000000000 -0600
+++ Makefile 2014-02-14 18:38:48.000000000 -0600
@@ -21,20 +21,23 @@
CFLAGS += -DUSE_SYS_DYN_MEM
endif
-LDFLAGS += -shared
-
PREFIX ?= /usr
DESTDIR ?=
-INCDIR = $(DESTDIR)$(PREFIX)/include
+INCDIR = $(PREFIX)/include
+
+UNAME_S := $(shell uname -s)
+ifeq ($(UNAME_S),Darwin)
+LDFLAGS += -dynamiclib -install_name $(LIBDIR)/$(LIBRARY)
+else
+LDFLAGS += -shared
+endif
-LIBDIR = $(DESTDIR)$(PREFIX)/lib
+LIBDIR = $(PREFIX)/lib
# on x86_64, we might have /usr/lib64 directory instead of /usr/lib
-MACHINE := $(shell uname -m)
-ifeq ($(MACHINE), x86_64)
+UNAME_M := $(shell uname -m)
+ifeq ($(UNAME_M),x86_64)
ifeq (,$(wildcard $(LIBDIR)))
-LIBDIR = $(DESTDIR)$(PREFIX)/lib64
-else
-LIBDIR = $(DESTDIR)$(PREFIX)/lib
+LIBDIR = $(PREFIX)/lib64
endif
endif
@@ -88,7 +91,6 @@
LIBOBJ += MCInst.o
-UNAME_S := $(shell uname -s)
# OSX?
ifeq ($(UNAME_S),Darwin)
EXT = dylib
@@ -145,25 +147,25 @@
echo 'Description: Capstone disassembler engine' >> $(PKGCFGF)
echo 'Version: $(VERSION)' >> $(PKGCFGF)
echo 'libdir=$(LIBDIR)' >> $(PKGCFGF)
- echo 'includedir=$(PREFIX)/include/capstone' >> $(PKGCFGF)
+ echo 'includedir=$(INCDIR)/capstone' >> $(PKGCFGF)
echo 'archive=$${libdir}/libcapstone.a' >> $(PKGCFGF)
echo 'Libs: -L$${libdir} -lcapstone' >> $(PKGCFGF)
echo 'Cflags: -I$${includedir}' >> $(PKGCFGF)
install: $(PKGCFGF) $(ARCHIVE) $(LIBRARY)
- mkdir -p $(LIBDIR)
- $(INSTALL_LIBRARY) lib$(LIBNAME).$(EXT) $(LIBDIR)
- $(INSTALL_DATA) lib$(LIBNAME).$(AR_EXT) $(LIBDIR)
- mkdir -p $(INCDIR)/$(LIBNAME)
- $(INSTALL_DATA) include/*.h $(INCDIR)/$(LIBNAME)
- mkdir -p $(LIBDIR)/pkgconfig
- $(INSTALL_DATA) $(PKGCFGF) $(LIBDIR)/pkgconfig/
+ mkdir -p $(DESTDIR)$(LIBDIR)
+ $(INSTALL_LIBRARY) lib$(LIBNAME).$(EXT) $(DESTDIR)$(LIBDIR)
+ $(INSTALL_DATA) lib$(LIBNAME).$(AR_EXT) $(DESTDIR)$(LIBDIR)
+ mkdir -p $(DESTDIR)$(INCDIR)/$(LIBNAME)
+ $(INSTALL_DATA) include/*.h $(DESTDIR)$(INCDIR)/$(LIBNAME)
+ mkdir -p $(DESTDIR)$(LIBDIR)/pkgconfig
+ $(INSTALL_DATA) $(PKGCFGF) $(DESTDIR)$(LIBDIR)/pkgconfig/
uninstall:
- rm -rf $(INCDIR)/$(LIBNAME)
- rm -f $(LIBDIR)/lib$(LIBNAME).$(EXT)
- rm -f $(LIBDIR)/lib$(LIBNAME).$(AR_EXT)
- rm -f $(LIBDIR)/pkgconfig/$(LIBNAME).pc
+ rm -rf $(DESTDIR)$(INCDIR)/$(LIBNAME)
+ rm -f $(DESTDIR)$(LIBDIR)/lib$(LIBNAME).$(EXT)
+ rm -f $(DESTDIR)$(LIBDIR)/lib$(LIBNAME).$(AR_EXT)
+ rm -f $(DESTDIR)$(LIBDIR)/pkgconfig/$(LIBNAME).pc
clean:
rm -f $(LIBOBJ) lib$(LIBNAME).*

@ -59,6 +59,13 @@ def cs(md, code):
print i
def cs_lite(md, code):
insns = md.disasm_lite(code, 0)
for (addr, size, mnem, ops) in insns:
if addr == 0x100000:
print i
cfile = open(FILE)
for (arch, mode, comment, syntax) in all_tests:
@ -73,6 +80,7 @@ for (arch, mode, comment, syntax) in all_tests:
try:
md = Cs(arch, mode)
#md.detail = True
if syntax != 0:
md.syntax = syntax
@ -96,7 +104,21 @@ for (arch, mode, comment, syntax) in all_tests:
cs(md, code)
c_t += time() - t1
print "Benchmark:", c_t, "seconds"
print "Benchmark - full obj:", c_t, "seconds"
print
cfile.seek(0)
c_t = 0
for i in xrange(50000):
code = get_code(cfile, 128)
#print to_hex(code)
#print
t1 = time()
cs_lite(md, code)
c_t += time() - t1
print "Benchmark - lite:", c_t, "seconds"
print
except CsError as e:
print("ERROR: %s" %e)

@ -155,7 +155,7 @@ static void test()
cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
if (err) {
printf("Failed on cs_open() with error returned: %u\n", err);
return;
continue;
}
if (platforms[i].opt_type)

@ -196,7 +196,7 @@ static void test()
cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
if (err) {
printf("Failed on cs_open() with error returned: %u\n", err);
return;
continue;
}
cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);

@ -154,7 +154,7 @@ static void test()
cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
if (err) {
printf("Failed on cs_open() with error returned: %u\n", err);
return;
continue;
}
cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);

@ -152,7 +152,7 @@ static void test()
cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
if (err) {
printf("Failed on cs_open() with error returned: %u\n", err);
return;
continue;
}
if (platforms[i].opt_type)

@ -101,7 +101,7 @@ static void test()
cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
if (err) {
printf("Failed on cs_open() with error returned: %u\n", err);
return;
continue;
}
cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);

@ -93,7 +93,7 @@ static void test()
cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
if (err) {
printf("Failed on cs_open() with error returned: %u\n", err);
return;
continue;
}
cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);

@ -168,7 +168,7 @@ static void test()
cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
if (err) {
printf("Failed on cs_open() with error returned: %u\n", err);
return;
continue;
}
if (platforms[i].opt_type)

@ -26,7 +26,7 @@ static unsigned short *make_id2insn(insn_map *insns, unsigned int size)
{
// NOTE: assume that the max id is always put at the end of insns array
unsigned short max_id = insns[size - 1].id;
unsigned int i;
unsigned short i;
unsigned short *cache = (unsigned short *)cs_mem_calloc(sizeof(*cache), max_id + 1);
@ -63,19 +63,6 @@ int name2id(name_map* map, int max, const char *name)
return -1;
}
unsigned int insn_reverse_id(insn_map *insns, unsigned int max, unsigned int id)
{
unsigned int i;
for (i = 0; i < max; i++) {
if (id == insns[i].mapid)
return insns[i].id;
}
// found nothing
return 0;
}
// count number of positive members in a list.
// NOTE: list must be guaranteed to end in 0
unsigned int count_positive(unsigned char *list)

@ -14,11 +14,13 @@
typedef struct insn_map {
unsigned short id;
unsigned short mapid;
#ifndef CAPSTONE_DIET
unsigned char regs_use[12]; // list of implicit registers used by this instruction
unsigned char regs_mod[20]; // list of implicit registers modified by this instruction
unsigned char groups[8]; // list of group this instruction belong to
bool branch; // branch instruction?
bool indirect_branch; // indirect branch instruction?
#endif
} insn_map;
// return the position of a string in a list of strings
@ -39,10 +41,6 @@ typedef struct name_map {
// return 0 if not found
int name2id(name_map* map, int max, const char *name);
// reverse mapid to id
// return 0 if not found
unsigned int insn_reverse_id(insn_map *insns, unsigned int max, unsigned int id);
// count number of positive members in a list.
// NOTE: list must be guaranteed to end in 0
unsigned int count_positive(unsigned char *list);

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