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/* Second-Best Disassembler Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
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#include <stdio.h>
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#include <stdlib.h>
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#include <inttypes.h>
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#include <capstone.h>
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static csh handle;
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struct platform {
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cs_arch arch;
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cs_mode mode;
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unsigned char *code;
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size_t size;
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char *comment;
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cs_opt_type opt_type;
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cs_opt_value opt_value;
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};
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static void print_string_hex(char *comment, unsigned char *str, int len)
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{
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unsigned char *c;
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printf("%s", comment);
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for (c = str; c < str + len; c++) {
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printf("0x%02x ", *c & 0xff);
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}
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printf("\n");
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}
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static void print_insn_detail(csh ud, cs_mode mode, cs_insn *ins)
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{
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int i;
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cs_x86 *x86 = &(ins->x86);
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print_string_hex("\tPrefix:", x86->prefix, 5);
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if (x86->segment != X86_REG_INVALID)
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printf("\tSegment override: %s\n", cs_reg_name(handle, x86->segment));
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print_string_hex("\tOpcode:", x86->opcode, 3);
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printf("\top_size: %u, addr_size: %u, disp_size: %u, imm_size: %u\n", x86->op_size, x86->addr_size, x86->disp_size, x86->imm_size);
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printf("\tmodrm: 0x%x\n", x86->modrm);
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printf("\tdisp: 0x%x\n", x86->disp);
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// SIB is not available in 16-bit mode
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if ((mode & CS_MODE_16) == 0) {
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printf("\tsib: 0x%x\n", x86->sib);
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if (x86->sib_index != X86_REG_INVALID)
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printf("\tsib_index: %s, sib_scale: %u, sib_base: %s\n",
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cs_reg_name(handle, x86->sib_index),
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x86->sib_scale,
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cs_reg_name(handle, x86->sib_base));
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}
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int count = cs_op_count(ud, ins, X86_OP_IMM);
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if (count) {
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printf("\timm_count: %u\n", count);
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for (i = 1; i < count + 1; i++) {
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int index = cs_op_index(ud, ins, X86_OP_IMM, i);
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printf("\t\timms[%u]: 0x%"PRIx64 "\n", i, x86->operands[index].imm);
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}
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}
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if (x86->op_count)
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printf("\top_count: %u\n", x86->op_count);
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for (i = 0; i < x86->op_count; i++) {
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cs_x86_op *op = &(x86->operands[i]);
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switch((int)op->type) {
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case X86_OP_REG:
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printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
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break;
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case X86_OP_IMM:
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printf("\t\toperands[%u].type: IMM = 0x%"PRIx64 "\n", i, op->imm);
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break;
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case X86_OP_FP:
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printf("\t\toperands[%u].type: FP = %f\n", i, op->fp);
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break;
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case X86_OP_MEM:
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printf("\t\toperands[%u].type: MEM\n", i);
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if (op->mem.base != 0)
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printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base));
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if (op->mem.index != 0)
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printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index));
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if (op->mem.scale != 1)
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printf("\t\t\toperands[%u].mem.scale: %u\n", i, op->mem.scale);
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if (op->mem.disp != 0)
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printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp);
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break;
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default:
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break;
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}
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}
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printf("\n");
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}
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static void test()
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{
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//#define X86_CODE32 "\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x78\x56\x00\x00"
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//#define X86_CODE32 "\x05\x78\x56\x00\x00"
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//#define X86_CODE32 "\x01\xd8"
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//#define X86_CODE32 "\x05\x23\x01\x00\x00"
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//#define X86_CODE32 "\x8d\x87\x89\x67\x00\x00"
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//#define X86_CODE32 "\xa1\x13\x48\x6d\x3a\x8b\x81\x23\x01\x00\x00\x8b\x84\x39\x23\x01\x00\x00"
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//#define X86_CODE32 "\xb4\xc6" // mov ah, 0x6c
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//#define X86_CODE32 "\x77\x04" // ja +6
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#define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00"
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//#define X86_CODE64 "\xe9\x79\xff\xff\xff" // jmp 0xf7e
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#define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
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//#define X86_CODE16 "\x67\x00\x18"
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#define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
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//#define X86_CODE32 "\x64\xa1\x18\x00\x00\x00" // mov eax, dword ptr fs:[18]
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//#define X86_CODE32 "\x64\xa3\x00\x00\x00\x00" // mov [fs:0x0], eax
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//#define X86_CODE32 "\xd1\xe1" // shl ecx, 1
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//#define X86_CODE32 "\xd1\xc8" // ror eax, 1
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//#define X86_CODE32 "\xcd\x80" // int 0x80
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//#define X86_CODE32 "\x83\xC0\x80" // add eax, -x80
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//#define X86_CODE32 "\x24\xb8" // and $0xb8,%al
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struct platform platforms[] = {
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{
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.arch = CS_ARCH_X86,
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.mode = CS_MODE_16,
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.code = (unsigned char *)X86_CODE16,
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.size = sizeof(X86_CODE16) - 1,
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.comment = "X86 16bit (Intel syntax)"
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},
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{
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.arch = CS_ARCH_X86,
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.mode = CS_MODE_32,
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.code = (unsigned char *)X86_CODE32,
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.size = sizeof(X86_CODE32) - 1,
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.comment = "X86 32 (AT&T syntax)",
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.opt_type = CS_OPT_SYNTAX,
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.opt_value = CS_OPT_V_ATT,
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},
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{
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.arch = CS_ARCH_X86,
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.mode = CS_MODE_32,
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.code = (unsigned char *)X86_CODE32,
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.size = sizeof(X86_CODE32) - 1,
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.comment = "X86 32 (Intel syntax)"
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},
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{
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.arch = CS_ARCH_X86,
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.mode = CS_MODE_64,
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.code = (unsigned char *)X86_CODE64,
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.size = sizeof(X86_CODE64) - 1,
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.comment = "X86 64 (Intel syntax)"
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},
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};
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uint64_t address = 0x1000;
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//cs_insn insn[16];
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cs_insn *insn;
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int i;
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for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
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if (cs_open(platforms[i].arch, platforms[i].mode, &handle))
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return;
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if (platforms[i].opt_type)
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cs_option(handle, platforms[i].opt_type, platforms[i].opt_value);
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//size_t count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, insn);
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size_t count = cs_disasm_dyn(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
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if (count) {
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printf("****************\n");
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printf("Platform: %s\n", platforms[i].comment);
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print_string_hex("Code:", platforms[i].code, platforms[i].size);
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printf("Disasm:\n");
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size_t j;
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for (j = 0; j < count; j++) {
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printf("0x%"PRIx64":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
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print_insn_detail(handle, platforms[i].mode, &insn[j]);
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}
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printf("0x%"PRIx64":\n", insn[j-1].address + insn[j-1].size);
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// free memory allocated by cs_disasm_dyn()
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cs_free(insn);
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} else {
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printf("****************\n");
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printf("Platform: %s\n", platforms[i].comment);
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print_string_hex("Code:", platforms[i].code, platforms[i].size);
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printf("ERROR: Failed to disasm given code!\n");
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}
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printf("\n");
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cs_close(handle);
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}
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}
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int main()
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{
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test();
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return 0;
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}
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